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Differential D154632

[4/8][RISCV] Add rounding mode control variant for vfmacc, vfnmacc, vfmsac, vfnmsac, vfmadd, vfnmadd, vfmsub, vfnmsub
ClosedPublic

Authored by eopXD on Jul 6 2023, 11:00 AM.

Details

Reviewers
craig.topper
reames
kito-cheng
rogfer01
frasercrmck
Commits
rGe1f224a647e6: [4/8][RISCV] Add rounding mode control variant for vfmacc, vfnmacc, vfmsac…
Summary

Depends on D154631

For the cover letter of the patch-set, please checkout D154628.

This is the 4th patch of the patch-set.

Diff Detail

Event Timeline

eopXD created this revision.Jul 6 2023, 11:00 AM
Herald added a project: Restricted Project. · View Herald TranscriptJul 6 2023, 11:00 AM
Herald added subscribers: jobnoorman, luke, VincentWu and 25 others. · View Herald Transcript
eopXD requested review of this revision.Jul 6 2023, 11:00 AM
Herald added projects: Restricted Project, Restricted Project. · View Herald TranscriptJul 6 2023, 11:00 AM
Herald added subscribers: llvm-commits, cfe-commits, wangpc, MaskRay. · View Herald Transcript
eopXD added a child revision: D154633: [5/8][RISCV] Add rounding mode control variant for vfwmacc, vfwnmacc, vfwmsac, vfwnmsac.Jul 6 2023, 11:00 AM
eopXD retitled this revision from [RISCV] Add rounding mode control variant for vfmacc, vfnmacc, vfmsac, vfnmsac, vfmadd, vfnmadd, vfmsub, vfnmsub to [4/8][RISCV] Add rounding mode control variant for vfmacc, vfnmacc, vfmsac, vfnmsac, vfmadd, vfnmadd, vfmsub, vfnmsub.Jul 6 2023, 11:10 AM
eopXD edited the summary of this revision. (Show Details)
Harbormaster completed remote builds in B243524: Diff 537800.Jul 6 2023, 12:37 PM
eopXD updated this revision to Diff 538006.Jul 6 2023, 11:34 PM

Bump CI.

Harbormaster completed remote builds in B243678: Diff 538006.Jul 7 2023, 12:56 AM
craig.topper accepted this revision.Jul 10 2023, 12:30 PM

LGTM

This revision is now accepted and ready to land.Jul 10 2023, 12:30 PM
eopXD updated this revision to Diff 539439.Jul 12 2023, 2:32 AM

Change:

  • Rebase upon latest main and updated parent revisions.
Harbormaster completed remote builds in B244706: Diff 539439.Jul 12 2023, 5:09 AM
This revision was landed with ongoing or failed builds.Jul 13 2023, 12:47 AM
Closed by commit rGe1f224a647e6: [4/8][RISCV] Add rounding mode control variant for vfmacc, vfnmacc, vfmsac… (authored by eopXD). · Explain Why
This revision was automatically updated to reflect the committed changes.
eopXD added a commit: rGe1f224a647e6: [4/8][RISCV] Add rounding mode control variant for vfmacc, vfnmacc, vfmsac….

Revision Contents

PathSize
clang/
include/
clang/
Basic/
73 lines
lib/
Sema/
96 lines
test/
CodeGen/
RISCV/
rvv-intrinsics-autogenerated/
non-policy/
non-overloaded/
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overloaded/
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policy/
non-overloaded/
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overloaded/
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rvv-intrinsics-handcrafted/
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llvm/
include/
llvm/
IR/
43 lines
lib/
Target/
RISCV/
207 lines
30 lines
98 lines
test/
CodeGen/
RISCV/
rvv/
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Diff 539877

clang/include/clang/Basic/riscv_vector.td

Show First 20 Lines • Show All 205 Lines • ▼ Show 20 Lines defm "" : RVVOutOp1BuiltinSet<NAME, "csil",
["vv", "Uv", "UvUvUvUv"], ["vv", "Uv", "UvUvUvUv"],
["vx", "Uv", "UvUvUeUv"]]>; ["vx", "Uv", "UvUvUeUv"]]>;
} }
multiclass RVVFloatingTerBuiltinSet { multiclass RVVFloatingTerBuiltinSet {
defm "" : RVVOutOp1BuiltinSet<NAME, "xfd", defm "" : RVVOutOp1BuiltinSet<NAME, "xfd",
[["vv", "v", "vvvv"], [["vv", "v", "vvvv"],
["vf", "v", "vvev"]]>; ["vf", "v", "vvev"]]>;
} }
multiclass RVVFloatingTerBuiltinSetRoundingMode {
defm "" : RVVOutOp1BuiltinSet<NAME, "xfd",
[["vv", "v", "vvvvu"],
["vf", "v", "vvevu"]]>;
}
} }
let HasMaskedOffOperand = false, Log2LMUL = [-2, -1, 0, 1, 2] in { let HasMaskedOffOperand = false, Log2LMUL = [-2, -1, 0, 1, 2] in {
multiclass RVVFloatingWidenTerBuiltinSet { multiclass RVVFloatingWidenTerBuiltinSet {
defm "" : RVVOutOp1Op2BuiltinSet<NAME, "xf", defm "" : RVVOutOp1Op2BuiltinSet<NAME, "xf",
[["vv", "w", "wwvv"], [["vv", "w", "wwvv"],
["vf", "w", "wwev"]]>; ["vf", "w", "wwev"]]>;
} }
▲ Show 20 Lines • Show All 1,812 Lines • ▼ Show 20 Lineslet ManualCodegen = [{
let Log2LMUL = [-2, -1, 0, 1, 2] in { let Log2LMUL = [-2, -1, 0, 1, 2] in {
defm vfwmul : RVVOutOp0Op1BuiltinSet<"vfwmul", "xf", defm vfwmul : RVVOutOp0Op1BuiltinSet<"vfwmul", "xf",
[["vv", "w", "wvv"], [["vv", "w", "wvv"],
["vf", "w", "wve"]]>; ["vf", "w", "wve"]]>;
} }
} }
} }
// 14.6. Vector Single-Width Floating-Point Fused Multiply-Add Instructions
let UnMaskedPolicyScheme = HasPolicyOperand in { let UnMaskedPolicyScheme = HasPolicyOperand in {
let ManualCodegen = [{
{
// LLVM intrinsic
// Unmasked: (passthru, op0, op1, round_mode, vl)
// Masked: (passthru, vector_in, vector_in/scalar_in, mask, frm, vl, policy)
SmallVector<llvm::Value*, 7> Operands;
bool HasRoundModeOp = IsMasked ? Ops.size() == 6 : Ops.size() == 5;
unsigned Offset = IsMasked ? 2 : 1;
Operands.push_back(Ops[IsMasked ? 1 : 0]); // passthrough
Operands.push_back(Ops[Offset]); // op0
Operands.push_back(Ops[Offset + 1]); // op1
if (IsMasked)
Operands.push_back(Ops[0]); // mask
if (HasRoundModeOp) {
Operands.push_back(Ops[Offset + 2]); // frm
Operands.push_back(Ops[Offset + 3]); // vl
} else {
Operands.push_back(ConstantInt::get(Ops[Offset + 2]->getType(), 7)); // frm
Operands.push_back(Ops[Offset + 2]); // vl
}
Operands.push_back(ConstantInt::get(Ops.back()->getType(), PolicyAttrs));
IntrinsicTypes = {ResultType, Ops[Offset]->getType(),
Operands.back()->getType()};
llvm::Function *F = CGM.getIntrinsic(ID, IntrinsicTypes);
return Builder.CreateCall(F, Operands, "");
}
}] in {
let HasFRMRoundModeOp = 1 in {
// 14.6. Vector Single-Width Floating-Point Fused Multiply-Add Instructions
defm vfmacc : RVVFloatingTerBuiltinSetRoundingMode;
defm vfnmacc : RVVFloatingTerBuiltinSetRoundingMode;
defm vfmsac : RVVFloatingTerBuiltinSetRoundingMode;
defm vfnmsac : RVVFloatingTerBuiltinSetRoundingMode;
defm vfmadd : RVVFloatingTerBuiltinSetRoundingMode;
defm vfnmadd : RVVFloatingTerBuiltinSetRoundingMode;
defm vfmsub : RVVFloatingTerBuiltinSetRoundingMode;
defm vfnmsub : RVVFloatingTerBuiltinSetRoundingMode;
}
// 14.6. Vector Single-Width Floating-Point Fused Multiply-Add Instructions
defm vfmacc : RVVFloatingTerBuiltinSet; defm vfmacc : RVVFloatingTerBuiltinSet;
defm vfnmacc : RVVFloatingTerBuiltinSet; defm vfnmacc : RVVFloatingTerBuiltinSet;
defm vfmsac : RVVFloatingTerBuiltinSet; defm vfmsac : RVVFloatingTerBuiltinSet;
defm vfnmsac : RVVFloatingTerBuiltinSet; defm vfnmsac : RVVFloatingTerBuiltinSet;
defm vfmadd : RVVFloatingTerBuiltinSet; defm vfmadd : RVVFloatingTerBuiltinSet;
defm vfnmadd : RVVFloatingTerBuiltinSet; defm vfnmadd : RVVFloatingTerBuiltinSet;
defm vfmsub : RVVFloatingTerBuiltinSet; defm vfmsub : RVVFloatingTerBuiltinSet;
defm vfnmsub : RVVFloatingTerBuiltinSet; defm vfnmsub : RVVFloatingTerBuiltinSet;
}
// 14.7. Vector Widening Floating-Point Fused Multiply-Add Instructions // 14.7. Vector Widening Floating-Point Fused Multiply-Add Instructions
defm vfwmacc : RVVFloatingWidenTerBuiltinSet; defm vfwmacc : RVVFloatingWidenTerBuiltinSet;
defm vfwnmacc : RVVFloatingWidenTerBuiltinSet; defm vfwnmacc : RVVFloatingWidenTerBuiltinSet;
defm vfwmsac : RVVFloatingWidenTerBuiltinSet; defm vfwmsac : RVVFloatingWidenTerBuiltinSet;
defm vfwnmsac : RVVFloatingWidenTerBuiltinSet; defm vfwnmsac : RVVFloatingWidenTerBuiltinSet;
} }
▲ Show 20 Lines • Show All 464 Lines • Show Last 20 Lines

clang/lib/Sema/SemaChecking.cpp

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 4,843 Lines • ▼ Show 20 Linesbool Sema::CheckRISCVBuiltinFunctionCall(const TargetInfo &TI,
case RISCVVector::BI__builtin_rvv_vfwsub_wf_rm_tu: case RISCVVector::BI__builtin_rvv_vfwsub_wf_rm_tu:
case RISCVVector::BI__builtin_rvv_vfmul_vv_rm_tu: case RISCVVector::BI__builtin_rvv_vfmul_vv_rm_tu:
case RISCVVector::BI__builtin_rvv_vfmul_vf_rm_tu: case RISCVVector::BI__builtin_rvv_vfmul_vf_rm_tu:
case RISCVVector::BI__builtin_rvv_vfdiv_vv_rm_tu: case RISCVVector::BI__builtin_rvv_vfdiv_vv_rm_tu:
case RISCVVector::BI__builtin_rvv_vfdiv_vf_rm_tu: case RISCVVector::BI__builtin_rvv_vfdiv_vf_rm_tu:
case RISCVVector::BI__builtin_rvv_vfrdiv_vf_rm_tu: case RISCVVector::BI__builtin_rvv_vfrdiv_vf_rm_tu:
case RISCVVector::BI__builtin_rvv_vfwmul_vv_rm_tu: case RISCVVector::BI__builtin_rvv_vfwmul_vv_rm_tu:
case RISCVVector::BI__builtin_rvv_vfwmul_vf_rm_tu: case RISCVVector::BI__builtin_rvv_vfwmul_vf_rm_tu:
case RISCVVector::BI__builtin_rvv_vfmacc_vv_rm:
case RISCVVector::BI__builtin_rvv_vfmacc_vf_rm:
case RISCVVector::BI__builtin_rvv_vfnmacc_vv_rm:
case RISCVVector::BI__builtin_rvv_vfnmacc_vf_rm:
case RISCVVector::BI__builtin_rvv_vfmsac_vv_rm:
case RISCVVector::BI__builtin_rvv_vfmsac_vf_rm:
case RISCVVector::BI__builtin_rvv_vfnmsac_vv_rm:
case RISCVVector::BI__builtin_rvv_vfnmsac_vf_rm:
case RISCVVector::BI__builtin_rvv_vfmadd_vv_rm:
case RISCVVector::BI__builtin_rvv_vfmadd_vf_rm:
case RISCVVector::BI__builtin_rvv_vfnmadd_vv_rm:
case RISCVVector::BI__builtin_rvv_vfnmadd_vf_rm:
case RISCVVector::BI__builtin_rvv_vfmsub_vv_rm:
case RISCVVector::BI__builtin_rvv_vfmsub_vf_rm:
case RISCVVector::BI__builtin_rvv_vfnmsub_vv_rm:
case RISCVVector::BI__builtin_rvv_vfnmsub_vf_rm:
case RISCVVector::BI__builtin_rvv_vfmacc_vv_rm_tu:
case RISCVVector::BI__builtin_rvv_vfmacc_vf_rm_tu:
case RISCVVector::BI__builtin_rvv_vfnmacc_vv_rm_tu:
case RISCVVector::BI__builtin_rvv_vfnmacc_vf_rm_tu:
case RISCVVector::BI__builtin_rvv_vfmsac_vv_rm_tu:
case RISCVVector::BI__builtin_rvv_vfmsac_vf_rm_tu:
case RISCVVector::BI__builtin_rvv_vfnmsac_vv_rm_tu:
case RISCVVector::BI__builtin_rvv_vfnmsac_vf_rm_tu:
case RISCVVector::BI__builtin_rvv_vfmadd_vv_rm_tu:
case RISCVVector::BI__builtin_rvv_vfmadd_vf_rm_tu:
case RISCVVector::BI__builtin_rvv_vfnmadd_vv_rm_tu:
case RISCVVector::BI__builtin_rvv_vfnmadd_vf_rm_tu:
case RISCVVector::BI__builtin_rvv_vfmsub_vv_rm_tu:
case RISCVVector::BI__builtin_rvv_vfmsub_vf_rm_tu:
case RISCVVector::BI__builtin_rvv_vfnmsub_vv_rm_tu:
case RISCVVector::BI__builtin_rvv_vfnmsub_vf_rm_tu:
case RISCVVector::BI__builtin_rvv_vfadd_vv_rm_tama: case RISCVVector::BI__builtin_rvv_vfadd_vv_rm_tama:
case RISCVVector::BI__builtin_rvv_vfadd_vf_rm_tama: case RISCVVector::BI__builtin_rvv_vfadd_vf_rm_tama:
case RISCVVector::BI__builtin_rvv_vfsub_vv_rm_tama: case RISCVVector::BI__builtin_rvv_vfsub_vv_rm_tama:
case RISCVVector::BI__builtin_rvv_vfsub_vf_rm_tama: case RISCVVector::BI__builtin_rvv_vfsub_vf_rm_tama:
case RISCVVector::BI__builtin_rvv_vfrsub_vf_rm_tama: case RISCVVector::BI__builtin_rvv_vfrsub_vf_rm_tama:
case RISCVVector::BI__builtin_rvv_vfwadd_vv_rm_tama: case RISCVVector::BI__builtin_rvv_vfwadd_vv_rm_tama:
case RISCVVector::BI__builtin_rvv_vfwadd_vf_rm_tama: case RISCVVector::BI__builtin_rvv_vfwadd_vf_rm_tama:
case RISCVVector::BI__builtin_rvv_vfwsub_vv_rm_tama: case RISCVVector::BI__builtin_rvv_vfwsub_vv_rm_tama:
case RISCVVector::BI__builtin_rvv_vfwsub_vf_rm_tama: case RISCVVector::BI__builtin_rvv_vfwsub_vf_rm_tama:
case RISCVVector::BI__builtin_rvv_vfwadd_wv_rm_tama: case RISCVVector::BI__builtin_rvv_vfwadd_wv_rm_tama:
case RISCVVector::BI__builtin_rvv_vfwadd_wf_rm_tama: case RISCVVector::BI__builtin_rvv_vfwadd_wf_rm_tama:
case RISCVVector::BI__builtin_rvv_vfwsub_wv_rm_tama: case RISCVVector::BI__builtin_rvv_vfwsub_wv_rm_tama:
case RISCVVector::BI__builtin_rvv_vfwsub_wf_rm_tama: case RISCVVector::BI__builtin_rvv_vfwsub_wf_rm_tama:
case RISCVVector::BI__builtin_rvv_vfmul_vv_rm_tama: case RISCVVector::BI__builtin_rvv_vfmul_vv_rm_tama:
case RISCVVector::BI__builtin_rvv_vfmul_vf_rm_tama: case RISCVVector::BI__builtin_rvv_vfmul_vf_rm_tama:
case RISCVVector::BI__builtin_rvv_vfdiv_vv_rm_tama: case RISCVVector::BI__builtin_rvv_vfdiv_vv_rm_tama:
case RISCVVector::BI__builtin_rvv_vfdiv_vf_rm_tama: case RISCVVector::BI__builtin_rvv_vfdiv_vf_rm_tama:
case RISCVVector::BI__builtin_rvv_vfrdiv_vf_rm_tama: case RISCVVector::BI__builtin_rvv_vfrdiv_vf_rm_tama:
case RISCVVector::BI__builtin_rvv_vfwmul_vv_rm_tama: case RISCVVector::BI__builtin_rvv_vfwmul_vv_rm_tama:
case RISCVVector::BI__builtin_rvv_vfwmul_vf_rm_tama: case RISCVVector::BI__builtin_rvv_vfwmul_vf_rm_tama:
return SemaBuiltinConstantArgRange(TheCall, 3, 0, 4); return SemaBuiltinConstantArgRange(TheCall, 3, 0, 4);
case RISCVVector::BI__builtin_rvv_vfmacc_vv_rm_tama:
case RISCVVector::BI__builtin_rvv_vfmacc_vf_rm_tama:
case RISCVVector::BI__builtin_rvv_vfnmacc_vv_rm_tama:
case RISCVVector::BI__builtin_rvv_vfnmacc_vf_rm_tama:
case RISCVVector::BI__builtin_rvv_vfmsac_vv_rm_tama:
case RISCVVector::BI__builtin_rvv_vfmsac_vf_rm_tama:
case RISCVVector::BI__builtin_rvv_vfnmsac_vv_rm_tama:
case RISCVVector::BI__builtin_rvv_vfnmsac_vf_rm_tama:
case RISCVVector::BI__builtin_rvv_vfmadd_vv_rm_tama:
case RISCVVector::BI__builtin_rvv_vfmadd_vf_rm_tama:
case RISCVVector::BI__builtin_rvv_vfnmadd_vv_rm_tama:
case RISCVVector::BI__builtin_rvv_vfnmadd_vf_rm_tama:
case RISCVVector::BI__builtin_rvv_vfmsub_vv_rm_tama:
case RISCVVector::BI__builtin_rvv_vfmsub_vf_rm_tama:
case RISCVVector::BI__builtin_rvv_vfnmsub_vv_rm_tama:
case RISCVVector::BI__builtin_rvv_vfnmsub_vf_rm_tama:
case RISCVVector::BI__builtin_rvv_vfadd_vv_rm_tum: case RISCVVector::BI__builtin_rvv_vfadd_vv_rm_tum:
case RISCVVector::BI__builtin_rvv_vfadd_vf_rm_tum: case RISCVVector::BI__builtin_rvv_vfadd_vf_rm_tum:
case RISCVVector::BI__builtin_rvv_vfsub_vv_rm_tum: case RISCVVector::BI__builtin_rvv_vfsub_vv_rm_tum:
case RISCVVector::BI__builtin_rvv_vfsub_vf_rm_tum: case RISCVVector::BI__builtin_rvv_vfsub_vf_rm_tum:
case RISCVVector::BI__builtin_rvv_vfrsub_vf_rm_tum: case RISCVVector::BI__builtin_rvv_vfrsub_vf_rm_tum:
case RISCVVector::BI__builtin_rvv_vfwadd_vv_rm_tum: case RISCVVector::BI__builtin_rvv_vfwadd_vv_rm_tum:
case RISCVVector::BI__builtin_rvv_vfwadd_vf_rm_tum: case RISCVVector::BI__builtin_rvv_vfwadd_vf_rm_tum:
case RISCVVector::BI__builtin_rvv_vfwsub_vv_rm_tum: case RISCVVector::BI__builtin_rvv_vfwsub_vv_rm_tum:
case RISCVVector::BI__builtin_rvv_vfwsub_vf_rm_tum: case RISCVVector::BI__builtin_rvv_vfwsub_vf_rm_tum:
case RISCVVector::BI__builtin_rvv_vfwadd_wv_rm_tum: case RISCVVector::BI__builtin_rvv_vfwadd_wv_rm_tum:
case RISCVVector::BI__builtin_rvv_vfwadd_wf_rm_tum: case RISCVVector::BI__builtin_rvv_vfwadd_wf_rm_tum:
case RISCVVector::BI__builtin_rvv_vfwsub_wv_rm_tum: case RISCVVector::BI__builtin_rvv_vfwsub_wv_rm_tum:
case RISCVVector::BI__builtin_rvv_vfwsub_wf_rm_tum: case RISCVVector::BI__builtin_rvv_vfwsub_wf_rm_tum:
case RISCVVector::BI__builtin_rvv_vfmul_vv_rm_tum: case RISCVVector::BI__builtin_rvv_vfmul_vv_rm_tum:
case RISCVVector::BI__builtin_rvv_vfmul_vf_rm_tum: case RISCVVector::BI__builtin_rvv_vfmul_vf_rm_tum:
case RISCVVector::BI__builtin_rvv_vfdiv_vv_rm_tum: case RISCVVector::BI__builtin_rvv_vfdiv_vv_rm_tum:
case RISCVVector::BI__builtin_rvv_vfdiv_vf_rm_tum: case RISCVVector::BI__builtin_rvv_vfdiv_vf_rm_tum:
case RISCVVector::BI__builtin_rvv_vfrdiv_vf_rm_tum: case RISCVVector::BI__builtin_rvv_vfrdiv_vf_rm_tum:
case RISCVVector::BI__builtin_rvv_vfwmul_vv_rm_tum: case RISCVVector::BI__builtin_rvv_vfwmul_vv_rm_tum:
case RISCVVector::BI__builtin_rvv_vfwmul_vf_rm_tum: case RISCVVector::BI__builtin_rvv_vfwmul_vf_rm_tum:
case RISCVVector::BI__builtin_rvv_vfmacc_vv_rm_tum:
case RISCVVector::BI__builtin_rvv_vfmacc_vf_rm_tum:
case RISCVVector::BI__builtin_rvv_vfnmacc_vv_rm_tum:
case RISCVVector::BI__builtin_rvv_vfnmacc_vf_rm_tum:
case RISCVVector::BI__builtin_rvv_vfmsac_vv_rm_tum:
case RISCVVector::BI__builtin_rvv_vfmsac_vf_rm_tum:
case RISCVVector::BI__builtin_rvv_vfnmsac_vv_rm_tum:
case RISCVVector::BI__builtin_rvv_vfnmsac_vf_rm_tum:
case RISCVVector::BI__builtin_rvv_vfmadd_vv_rm_tum:
case RISCVVector::BI__builtin_rvv_vfmadd_vf_rm_tum:
case RISCVVector::BI__builtin_rvv_vfnmadd_vv_rm_tum:
case RISCVVector::BI__builtin_rvv_vfnmadd_vf_rm_tum:
case RISCVVector::BI__builtin_rvv_vfmsub_vv_rm_tum:
case RISCVVector::BI__builtin_rvv_vfmsub_vf_rm_tum:
case RISCVVector::BI__builtin_rvv_vfnmsub_vv_rm_tum:
case RISCVVector::BI__builtin_rvv_vfnmsub_vf_rm_tum:
case RISCVVector::BI__builtin_rvv_vfadd_vv_rm_tumu: case RISCVVector::BI__builtin_rvv_vfadd_vv_rm_tumu:
case RISCVVector::BI__builtin_rvv_vfadd_vf_rm_tumu: case RISCVVector::BI__builtin_rvv_vfadd_vf_rm_tumu:
case RISCVVector::BI__builtin_rvv_vfsub_vv_rm_tumu: case RISCVVector::BI__builtin_rvv_vfsub_vv_rm_tumu:
case RISCVVector::BI__builtin_rvv_vfsub_vf_rm_tumu: case RISCVVector::BI__builtin_rvv_vfsub_vf_rm_tumu:
case RISCVVector::BI__builtin_rvv_vfrsub_vf_rm_tumu: case RISCVVector::BI__builtin_rvv_vfrsub_vf_rm_tumu:
case RISCVVector::BI__builtin_rvv_vfwadd_vv_rm_tumu: case RISCVVector::BI__builtin_rvv_vfwadd_vv_rm_tumu:
case RISCVVector::BI__builtin_rvv_vfwadd_vf_rm_tumu: case RISCVVector::BI__builtin_rvv_vfwadd_vf_rm_tumu:
case RISCVVector::BI__builtin_rvv_vfwsub_vv_rm_tumu: case RISCVVector::BI__builtin_rvv_vfwsub_vv_rm_tumu:
case RISCVVector::BI__builtin_rvv_vfwsub_vf_rm_tumu: case RISCVVector::BI__builtin_rvv_vfwsub_vf_rm_tumu:
case RISCVVector::BI__builtin_rvv_vfwadd_wv_rm_tumu: case RISCVVector::BI__builtin_rvv_vfwadd_wv_rm_tumu:
case RISCVVector::BI__builtin_rvv_vfwadd_wf_rm_tumu: case RISCVVector::BI__builtin_rvv_vfwadd_wf_rm_tumu:
case RISCVVector::BI__builtin_rvv_vfwsub_wv_rm_tumu: case RISCVVector::BI__builtin_rvv_vfwsub_wv_rm_tumu:
case RISCVVector::BI__builtin_rvv_vfwsub_wf_rm_tumu: case RISCVVector::BI__builtin_rvv_vfwsub_wf_rm_tumu:
case RISCVVector::BI__builtin_rvv_vfmul_vv_rm_tumu: case RISCVVector::BI__builtin_rvv_vfmul_vv_rm_tumu:
case RISCVVector::BI__builtin_rvv_vfmul_vf_rm_tumu: case RISCVVector::BI__builtin_rvv_vfmul_vf_rm_tumu:
case RISCVVector::BI__builtin_rvv_vfdiv_vv_rm_tumu: case RISCVVector::BI__builtin_rvv_vfdiv_vv_rm_tumu:
case RISCVVector::BI__builtin_rvv_vfdiv_vf_rm_tumu: case RISCVVector::BI__builtin_rvv_vfdiv_vf_rm_tumu:
case RISCVVector::BI__builtin_rvv_vfrdiv_vf_rm_tumu: case RISCVVector::BI__builtin_rvv_vfrdiv_vf_rm_tumu:
case RISCVVector::BI__builtin_rvv_vfwmul_vv_rm_tumu: case RISCVVector::BI__builtin_rvv_vfwmul_vv_rm_tumu:
case RISCVVector::BI__builtin_rvv_vfwmul_vf_rm_tumu: case RISCVVector::BI__builtin_rvv_vfwmul_vf_rm_tumu:
case RISCVVector::BI__builtin_rvv_vfmacc_vv_rm_tumu:
case RISCVVector::BI__builtin_rvv_vfmacc_vf_rm_tumu:
case RISCVVector::BI__builtin_rvv_vfnmacc_vv_rm_tumu:
case RISCVVector::BI__builtin_rvv_vfnmacc_vf_rm_tumu:
case RISCVVector::BI__builtin_rvv_vfmsac_vv_rm_tumu:
case RISCVVector::BI__builtin_rvv_vfmsac_vf_rm_tumu:
case RISCVVector::BI__builtin_rvv_vfnmsac_vv_rm_tumu:
case RISCVVector::BI__builtin_rvv_vfnmsac_vf_rm_tumu:
case RISCVVector::BI__builtin_rvv_vfmadd_vv_rm_tumu:
case RISCVVector::BI__builtin_rvv_vfmadd_vf_rm_tumu:
case RISCVVector::BI__builtin_rvv_vfnmadd_vv_rm_tumu:
case RISCVVector::BI__builtin_rvv_vfnmadd_vf_rm_tumu:
case RISCVVector::BI__builtin_rvv_vfmsub_vv_rm_tumu:
case RISCVVector::BI__builtin_rvv_vfmsub_vf_rm_tumu:
case RISCVVector::BI__builtin_rvv_vfnmsub_vv_rm_tumu:
case RISCVVector::BI__builtin_rvv_vfnmsub_vf_rm_tumu:
case RISCVVector::BI__builtin_rvv_vfadd_vv_rm_mu: case RISCVVector::BI__builtin_rvv_vfadd_vv_rm_mu:
case RISCVVector::BI__builtin_rvv_vfadd_vf_rm_mu: case RISCVVector::BI__builtin_rvv_vfadd_vf_rm_mu:
case RISCVVector::BI__builtin_rvv_vfsub_vv_rm_mu: case RISCVVector::BI__builtin_rvv_vfsub_vv_rm_mu:
case RISCVVector::BI__builtin_rvv_vfsub_vf_rm_mu: case RISCVVector::BI__builtin_rvv_vfsub_vf_rm_mu:
case RISCVVector::BI__builtin_rvv_vfrsub_vf_rm_mu: case RISCVVector::BI__builtin_rvv_vfrsub_vf_rm_mu:
case RISCVVector::BI__builtin_rvv_vfwadd_vv_rm_mu: case RISCVVector::BI__builtin_rvv_vfwadd_vv_rm_mu:
case RISCVVector::BI__builtin_rvv_vfwadd_vf_rm_mu: case RISCVVector::BI__builtin_rvv_vfwadd_vf_rm_mu:
case RISCVVector::BI__builtin_rvv_vfwsub_vv_rm_mu: case RISCVVector::BI__builtin_rvv_vfwsub_vv_rm_mu:
case RISCVVector::BI__builtin_rvv_vfwsub_vf_rm_mu: case RISCVVector::BI__builtin_rvv_vfwsub_vf_rm_mu:
case RISCVVector::BI__builtin_rvv_vfwadd_wv_rm_mu: case RISCVVector::BI__builtin_rvv_vfwadd_wv_rm_mu:
case RISCVVector::BI__builtin_rvv_vfwadd_wf_rm_mu: case RISCVVector::BI__builtin_rvv_vfwadd_wf_rm_mu:
case RISCVVector::BI__builtin_rvv_vfwsub_wv_rm_mu: case RISCVVector::BI__builtin_rvv_vfwsub_wv_rm_mu:
case RISCVVector::BI__builtin_rvv_vfwsub_wf_rm_mu: case RISCVVector::BI__builtin_rvv_vfwsub_wf_rm_mu:
case RISCVVector::BI__builtin_rvv_vfmul_vv_rm_mu: case RISCVVector::BI__builtin_rvv_vfmul_vv_rm_mu:
case RISCVVector::BI__builtin_rvv_vfmul_vf_rm_mu: case RISCVVector::BI__builtin_rvv_vfmul_vf_rm_mu:
case RISCVVector::BI__builtin_rvv_vfdiv_vv_rm_mu: case RISCVVector::BI__builtin_rvv_vfdiv_vv_rm_mu:
case RISCVVector::BI__builtin_rvv_vfdiv_vf_rm_mu: case RISCVVector::BI__builtin_rvv_vfdiv_vf_rm_mu:
case RISCVVector::BI__builtin_rvv_vfrdiv_vf_rm_mu: case RISCVVector::BI__builtin_rvv_vfrdiv_vf_rm_mu:
case RISCVVector::BI__builtin_rvv_vfwmul_vv_rm_mu: case RISCVVector::BI__builtin_rvv_vfwmul_vv_rm_mu:
case RISCVVector::BI__builtin_rvv_vfwmul_vf_rm_mu: case RISCVVector::BI__builtin_rvv_vfwmul_vf_rm_mu:
case RISCVVector::BI__builtin_rvv_vfmacc_vv_rm_mu:
case RISCVVector::BI__builtin_rvv_vfmacc_vf_rm_mu:
case RISCVVector::BI__builtin_rvv_vfnmacc_vv_rm_mu:
case RISCVVector::BI__builtin_rvv_vfnmacc_vf_rm_mu:
case RISCVVector::BI__builtin_rvv_vfmsac_vv_rm_mu:
case RISCVVector::BI__builtin_rvv_vfmsac_vf_rm_mu:
case RISCVVector::BI__builtin_rvv_vfnmsac_vv_rm_mu:
case RISCVVector::BI__builtin_rvv_vfnmsac_vf_rm_mu:
case RISCVVector::BI__builtin_rvv_vfmadd_vv_rm_mu:
case RISCVVector::BI__builtin_rvv_vfmadd_vf_rm_mu:
case RISCVVector::BI__builtin_rvv_vfnmadd_vv_rm_mu:
case RISCVVector::BI__builtin_rvv_vfnmadd_vf_rm_mu:
case RISCVVector::BI__builtin_rvv_vfmsub_vv_rm_mu:
case RISCVVector::BI__builtin_rvv_vfmsub_vf_rm_mu:
case RISCVVector::BI__builtin_rvv_vfnmsub_vv_rm_mu:
case RISCVVector::BI__builtin_rvv_vfnmsub_vf_rm_mu:
return SemaBuiltinConstantArgRange(TheCall, 4, 0, 4); return SemaBuiltinConstantArgRange(TheCall, 4, 0, 4);
case RISCV::BI__builtin_riscv_ntl_load: case RISCV::BI__builtin_riscv_ntl_load:
case RISCV::BI__builtin_riscv_ntl_store: case RISCV::BI__builtin_riscv_ntl_store:
DeclRefExpr *DRE = DeclRefExpr *DRE =
cast<DeclRefExpr>(TheCall->getCallee()->IgnoreParenCasts()); cast<DeclRefExpr>(TheCall->getCallee()->IgnoreParenCasts());
assert((BuiltinID == RISCV::BI__builtin_riscv_ntl_store || assert((BuiltinID == RISCV::BI__builtin_riscv_ntl_store ||
BuiltinID == RISCV::BI__builtin_riscv_ntl_load) && BuiltinID == RISCV::BI__builtin_riscv_ntl_load) &&
"Unexpected RISC-V nontemporal load/store builtin!"); "Unexpected RISC-V nontemporal load/store builtin!");
▲ Show 20 Lines • Show All 13,907 Lines • Show Last 20 Lines

clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmacc.c

// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target // REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh \ // RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh \
// RUN: -target-feature +experimental-zvfh -disable-O0-optnone \ // RUN: -target-feature +experimental-zvfh -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ // RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s // RUN: FileCheck --check-prefix=CHECK-RV64 %s
#include <riscv_vector.h> #include <riscv_vector.h>
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmacc_vv_f16mf4 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmacc_vv_f16mf4
// CHECK-RV64-SAME: (<vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK-RV64-SAME: (<vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmacc.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmacc.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
// //
vfloat16mf4_t test_vfmacc_vv_f16mf4(vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) { vfloat16mf4_t test_vfmacc_vv_f16mf4(vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfmacc_vv_f16mf4(vd, vs1, vs2, vl); return __riscv_vfmacc_vv_f16mf4(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmacc_vf_f16mf4 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmacc_vf_f16mf4
// CHECK-RV64-SAME: (<vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmacc.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmacc.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
// //
vfloat16mf4_t test_vfmacc_vf_f16mf4(vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) { vfloat16mf4_t test_vfmacc_vf_f16mf4(vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfmacc_vf_f16mf4(vd, rs1, vs2, vl); return __riscv_vfmacc_vf_f16mf4(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmacc_vv_f16mf2 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmacc_vv_f16mf2
// CHECK-RV64-SAME: (<vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmacc.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmacc.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
// //
vfloat16mf2_t test_vfmacc_vv_f16mf2(vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) { vfloat16mf2_t test_vfmacc_vv_f16mf2(vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfmacc_vv_f16mf2(vd, vs1, vs2, vl); return __riscv_vfmacc_vv_f16mf2(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmacc_vf_f16mf2 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmacc_vf_f16mf2
// CHECK-RV64-SAME: (<vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmacc.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmacc.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
// //
vfloat16mf2_t test_vfmacc_vf_f16mf2(vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) { vfloat16mf2_t test_vfmacc_vf_f16mf2(vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfmacc_vf_f16mf2(vd, rs1, vs2, vl); return __riscv_vfmacc_vf_f16mf2(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmacc_vv_f16m1 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmacc_vv_f16m1
// CHECK-RV64-SAME: (<vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmacc.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmacc.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
// //
vfloat16m1_t test_vfmacc_vv_f16m1(vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) { vfloat16m1_t test_vfmacc_vv_f16m1(vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfmacc_vv_f16m1(vd, vs1, vs2, vl); return __riscv_vfmacc_vv_f16m1(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmacc_vf_f16m1 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmacc_vf_f16m1
// CHECK-RV64-SAME: (<vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmacc.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmacc.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
// //
vfloat16m1_t test_vfmacc_vf_f16m1(vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) { vfloat16m1_t test_vfmacc_vf_f16m1(vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfmacc_vf_f16m1(vd, rs1, vs2, vl); return __riscv_vfmacc_vf_f16m1(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmacc_vv_f16m2 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmacc_vv_f16m2
// CHECK-RV64-SAME: (<vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmacc.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmacc.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
// //
vfloat16m2_t test_vfmacc_vv_f16m2(vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) { vfloat16m2_t test_vfmacc_vv_f16m2(vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfmacc_vv_f16m2(vd, vs1, vs2, vl); return __riscv_vfmacc_vv_f16m2(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmacc_vf_f16m2 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmacc_vf_f16m2
// CHECK-RV64-SAME: (<vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmacc.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmacc.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
// //
vfloat16m2_t test_vfmacc_vf_f16m2(vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) { vfloat16m2_t test_vfmacc_vf_f16m2(vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfmacc_vf_f16m2(vd, rs1, vs2, vl); return __riscv_vfmacc_vf_f16m2(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmacc_vv_f16m4 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmacc_vv_f16m4
// CHECK-RV64-SAME: (<vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmacc.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmacc.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
// //
vfloat16m4_t test_vfmacc_vv_f16m4(vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) { vfloat16m4_t test_vfmacc_vv_f16m4(vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfmacc_vv_f16m4(vd, vs1, vs2, vl); return __riscv_vfmacc_vv_f16m4(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmacc_vf_f16m4 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmacc_vf_f16m4
// CHECK-RV64-SAME: (<vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmacc.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmacc.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
// //
vfloat16m4_t test_vfmacc_vf_f16m4(vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) { vfloat16m4_t test_vfmacc_vf_f16m4(vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfmacc_vf_f16m4(vd, rs1, vs2, vl); return __riscv_vfmacc_vf_f16m4(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmacc_vv_f16m8 // CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmacc_vv_f16m8
// CHECK-RV64-SAME: (<vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmacc.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmacc.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
// //
vfloat16m8_t test_vfmacc_vv_f16m8(vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) { vfloat16m8_t test_vfmacc_vv_f16m8(vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfmacc_vv_f16m8(vd, vs1, vs2, vl); return __riscv_vfmacc_vv_f16m8(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmacc_vf_f16m8 // CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmacc_vf_f16m8
// CHECK-RV64-SAME: (<vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmacc.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmacc.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
// //
vfloat16m8_t test_vfmacc_vf_f16m8(vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) { vfloat16m8_t test_vfmacc_vf_f16m8(vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfmacc_vf_f16m8(vd, rs1, vs2, vl); return __riscv_vfmacc_vf_f16m8(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmacc_vv_f32mf2 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmacc_vv_f32mf2
// CHECK-RV64-SAME: (<vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmacc.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmacc.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfmacc_vv_f32mf2(vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) { vfloat32mf2_t test_vfmacc_vv_f32mf2(vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfmacc_vv_f32mf2(vd, vs1, vs2, vl); return __riscv_vfmacc_vv_f32mf2(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmacc_vf_f32mf2 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmacc_vf_f32mf2
// CHECK-RV64-SAME: (<vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmacc.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmacc.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfmacc_vf_f32mf2(vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) { vfloat32mf2_t test_vfmacc_vf_f32mf2(vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfmacc_vf_f32mf2(vd, rs1, vs2, vl); return __riscv_vfmacc_vf_f32mf2(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmacc_vv_f32m1 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmacc_vv_f32m1
// CHECK-RV64-SAME: (<vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmacc.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmacc.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfmacc_vv_f32m1(vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) { vfloat32m1_t test_vfmacc_vv_f32m1(vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfmacc_vv_f32m1(vd, vs1, vs2, vl); return __riscv_vfmacc_vv_f32m1(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmacc_vf_f32m1 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmacc_vf_f32m1
// CHECK-RV64-SAME: (<vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmacc.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmacc.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfmacc_vf_f32m1(vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) { vfloat32m1_t test_vfmacc_vf_f32m1(vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfmacc_vf_f32m1(vd, rs1, vs2, vl); return __riscv_vfmacc_vf_f32m1(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmacc_vv_f32m2 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmacc_vv_f32m2
// CHECK-RV64-SAME: (<vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmacc.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmacc.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfmacc_vv_f32m2(vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) { vfloat32m2_t test_vfmacc_vv_f32m2(vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfmacc_vv_f32m2(vd, vs1, vs2, vl); return __riscv_vfmacc_vv_f32m2(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmacc_vf_f32m2 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmacc_vf_f32m2
// CHECK-RV64-SAME: (<vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmacc.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmacc.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfmacc_vf_f32m2(vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) { vfloat32m2_t test_vfmacc_vf_f32m2(vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfmacc_vf_f32m2(vd, rs1, vs2, vl); return __riscv_vfmacc_vf_f32m2(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmacc_vv_f32m4 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmacc_vv_f32m4
// CHECK-RV64-SAME: (<vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmacc.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmacc.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfmacc_vv_f32m4(vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) { vfloat32m4_t test_vfmacc_vv_f32m4(vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfmacc_vv_f32m4(vd, vs1, vs2, vl); return __riscv_vfmacc_vv_f32m4(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmacc_vf_f32m4 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmacc_vf_f32m4
// CHECK-RV64-SAME: (<vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmacc.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmacc.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfmacc_vf_f32m4(vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) { vfloat32m4_t test_vfmacc_vf_f32m4(vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfmacc_vf_f32m4(vd, rs1, vs2, vl); return __riscv_vfmacc_vf_f32m4(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmacc_vv_f32m8 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmacc_vv_f32m8
// CHECK-RV64-SAME: (<vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmacc.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmacc.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfmacc_vv_f32m8(vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) { vfloat32m8_t test_vfmacc_vv_f32m8(vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfmacc_vv_f32m8(vd, vs1, vs2, vl); return __riscv_vfmacc_vv_f32m8(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmacc_vf_f32m8 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmacc_vf_f32m8
// CHECK-RV64-SAME: (<vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmacc.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmacc.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfmacc_vf_f32m8(vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) { vfloat32m8_t test_vfmacc_vf_f32m8(vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfmacc_vf_f32m8(vd, rs1, vs2, vl); return __riscv_vfmacc_vf_f32m8(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmacc_vv_f64m1 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmacc_vv_f64m1
// CHECK-RV64-SAME: (<vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmacc.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmacc.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfmacc_vv_f64m1(vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) { vfloat64m1_t test_vfmacc_vv_f64m1(vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfmacc_vv_f64m1(vd, vs1, vs2, vl); return __riscv_vfmacc_vv_f64m1(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmacc_vf_f64m1 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmacc_vf_f64m1
// CHECK-RV64-SAME: (<vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmacc.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmacc.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfmacc_vf_f64m1(vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) { vfloat64m1_t test_vfmacc_vf_f64m1(vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfmacc_vf_f64m1(vd, rs1, vs2, vl); return __riscv_vfmacc_vf_f64m1(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmacc_vv_f64m2 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmacc_vv_f64m2
// CHECK-RV64-SAME: (<vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmacc.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmacc.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfmacc_vv_f64m2(vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) { vfloat64m2_t test_vfmacc_vv_f64m2(vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfmacc_vv_f64m2(vd, vs1, vs2, vl); return __riscv_vfmacc_vv_f64m2(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmacc_vf_f64m2 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmacc_vf_f64m2
// CHECK-RV64-SAME: (<vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmacc.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmacc.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfmacc_vf_f64m2(vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) { vfloat64m2_t test_vfmacc_vf_f64m2(vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfmacc_vf_f64m2(vd, rs1, vs2, vl); return __riscv_vfmacc_vf_f64m2(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmacc_vv_f64m4 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmacc_vv_f64m4
// CHECK-RV64-SAME: (<vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmacc.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmacc.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfmacc_vv_f64m4(vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) { vfloat64m4_t test_vfmacc_vv_f64m4(vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfmacc_vv_f64m4(vd, vs1, vs2, vl); return __riscv_vfmacc_vv_f64m4(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmacc_vf_f64m4 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmacc_vf_f64m4
// CHECK-RV64-SAME: (<vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmacc.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmacc.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfmacc_vf_f64m4(vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) { vfloat64m4_t test_vfmacc_vf_f64m4(vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfmacc_vf_f64m4(vd, rs1, vs2, vl); return __riscv_vfmacc_vf_f64m4(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmacc_vv_f64m8 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmacc_vv_f64m8
// CHECK-RV64-SAME: (<vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmacc.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmacc.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfmacc_vv_f64m8(vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) { vfloat64m8_t test_vfmacc_vv_f64m8(vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfmacc_vv_f64m8(vd, vs1, vs2, vl); return __riscv_vfmacc_vv_f64m8(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmacc_vf_f64m8 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmacc_vf_f64m8
// CHECK-RV64-SAME: (<vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmacc.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmacc.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfmacc_vf_f64m8(vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) { vfloat64m8_t test_vfmacc_vf_f64m8(vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfmacc_vf_f64m8(vd, rs1, vs2, vl); return __riscv_vfmacc_vf_f64m8(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmacc_vv_f16mf4_m // CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmacc_vv_f16mf4_m
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmacc.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmacc.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
// //
vfloat16mf4_t test_vfmacc_vv_f16mf4_m(vbool64_t mask, vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) { vfloat16mf4_t test_vfmacc_vv_f16mf4_m(vbool64_t mask, vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfmacc_vv_f16mf4_m(mask, vd, vs1, vs2, vl); return __riscv_vfmacc_vv_f16mf4_m(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmacc_vf_f16mf4_m // CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmacc_vf_f16mf4_m
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmacc.mask.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmacc.mask.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
// //
vfloat16mf4_t test_vfmacc_vf_f16mf4_m(vbool64_t mask, vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) { vfloat16mf4_t test_vfmacc_vf_f16mf4_m(vbool64_t mask, vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfmacc_vf_f16mf4_m(mask, vd, rs1, vs2, vl); return __riscv_vfmacc_vf_f16mf4_m(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmacc_vv_f16mf2_m // CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmacc_vv_f16mf2_m
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmacc.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmacc.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
// //
vfloat16mf2_t test_vfmacc_vv_f16mf2_m(vbool32_t mask, vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) { vfloat16mf2_t test_vfmacc_vv_f16mf2_m(vbool32_t mask, vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfmacc_vv_f16mf2_m(mask, vd, vs1, vs2, vl); return __riscv_vfmacc_vv_f16mf2_m(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmacc_vf_f16mf2_m // CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmacc_vf_f16mf2_m
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmacc.mask.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmacc.mask.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
// //
vfloat16mf2_t test_vfmacc_vf_f16mf2_m(vbool32_t mask, vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) { vfloat16mf2_t test_vfmacc_vf_f16mf2_m(vbool32_t mask, vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfmacc_vf_f16mf2_m(mask, vd, rs1, vs2, vl); return __riscv_vfmacc_vf_f16mf2_m(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmacc_vv_f16m1_m // CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmacc_vv_f16m1_m
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmacc.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmacc.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
// //
vfloat16m1_t test_vfmacc_vv_f16m1_m(vbool16_t mask, vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) { vfloat16m1_t test_vfmacc_vv_f16m1_m(vbool16_t mask, vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfmacc_vv_f16m1_m(mask, vd, vs1, vs2, vl); return __riscv_vfmacc_vv_f16m1_m(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmacc_vf_f16m1_m // CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmacc_vf_f16m1_m
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmacc.mask.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmacc.mask.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
// //
vfloat16m1_t test_vfmacc_vf_f16m1_m(vbool16_t mask, vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) { vfloat16m1_t test_vfmacc_vf_f16m1_m(vbool16_t mask, vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfmacc_vf_f16m1_m(mask, vd, rs1, vs2, vl); return __riscv_vfmacc_vf_f16m1_m(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmacc_vv_f16m2_m // CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmacc_vv_f16m2_m
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmacc.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmacc.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
// //
vfloat16m2_t test_vfmacc_vv_f16m2_m(vbool8_t mask, vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) { vfloat16m2_t test_vfmacc_vv_f16m2_m(vbool8_t mask, vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfmacc_vv_f16m2_m(mask, vd, vs1, vs2, vl); return __riscv_vfmacc_vv_f16m2_m(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmacc_vf_f16m2_m // CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmacc_vf_f16m2_m
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmacc.mask.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmacc.mask.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
// //
vfloat16m2_t test_vfmacc_vf_f16m2_m(vbool8_t mask, vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) { vfloat16m2_t test_vfmacc_vf_f16m2_m(vbool8_t mask, vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfmacc_vf_f16m2_m(mask, vd, rs1, vs2, vl); return __riscv_vfmacc_vf_f16m2_m(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmacc_vv_f16m4_m // CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmacc_vv_f16m4_m
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmacc.mask.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmacc.mask.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
// //
vfloat16m4_t test_vfmacc_vv_f16m4_m(vbool4_t mask, vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) { vfloat16m4_t test_vfmacc_vv_f16m4_m(vbool4_t mask, vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfmacc_vv_f16m4_m(mask, vd, vs1, vs2, vl); return __riscv_vfmacc_vv_f16m4_m(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmacc_vf_f16m4_m // CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmacc_vf_f16m4_m
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmacc.mask.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmacc.mask.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
// //
vfloat16m4_t test_vfmacc_vf_f16m4_m(vbool4_t mask, vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) { vfloat16m4_t test_vfmacc_vf_f16m4_m(vbool4_t mask, vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfmacc_vf_f16m4_m(mask, vd, rs1, vs2, vl); return __riscv_vfmacc_vf_f16m4_m(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmacc_vv_f16m8_m // CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmacc_vv_f16m8_m
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmacc.mask.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmacc.mask.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
// //
vfloat16m8_t test_vfmacc_vv_f16m8_m(vbool2_t mask, vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) { vfloat16m8_t test_vfmacc_vv_f16m8_m(vbool2_t mask, vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfmacc_vv_f16m8_m(mask, vd, vs1, vs2, vl); return __riscv_vfmacc_vv_f16m8_m(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmacc_vf_f16m8_m // CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmacc_vf_f16m8_m
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmacc.mask.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmacc.mask.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
// //
vfloat16m8_t test_vfmacc_vf_f16m8_m(vbool2_t mask, vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) { vfloat16m8_t test_vfmacc_vf_f16m8_m(vbool2_t mask, vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfmacc_vf_f16m8_m(mask, vd, rs1, vs2, vl); return __riscv_vfmacc_vf_f16m8_m(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmacc_vv_f32mf2_m // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmacc_vv_f32mf2_m
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmacc.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmacc.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfmacc_vv_f32mf2_m(vbool64_t mask, vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) { vfloat32mf2_t test_vfmacc_vv_f32mf2_m(vbool64_t mask, vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfmacc_vv_f32mf2_m(mask, vd, vs1, vs2, vl); return __riscv_vfmacc_vv_f32mf2_m(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmacc_vf_f32mf2_m // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmacc_vf_f32mf2_m
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmacc.mask.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmacc.mask.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfmacc_vf_f32mf2_m(vbool64_t mask, vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) { vfloat32mf2_t test_vfmacc_vf_f32mf2_m(vbool64_t mask, vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfmacc_vf_f32mf2_m(mask, vd, rs1, vs2, vl); return __riscv_vfmacc_vf_f32mf2_m(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmacc_vv_f32m1_m // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmacc_vv_f32m1_m
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmacc.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmacc.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfmacc_vv_f32m1_m(vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) { vfloat32m1_t test_vfmacc_vv_f32m1_m(vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfmacc_vv_f32m1_m(mask, vd, vs1, vs2, vl); return __riscv_vfmacc_vv_f32m1_m(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmacc_vf_f32m1_m // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmacc_vf_f32m1_m
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmacc.mask.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmacc.mask.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfmacc_vf_f32m1_m(vbool32_t mask, vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) { vfloat32m1_t test_vfmacc_vf_f32m1_m(vbool32_t mask, vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfmacc_vf_f32m1_m(mask, vd, rs1, vs2, vl); return __riscv_vfmacc_vf_f32m1_m(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmacc_vv_f32m2_m // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmacc_vv_f32m2_m
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmacc.mask.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmacc.mask.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfmacc_vv_f32m2_m(vbool16_t mask, vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) { vfloat32m2_t test_vfmacc_vv_f32m2_m(vbool16_t mask, vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfmacc_vv_f32m2_m(mask, vd, vs1, vs2, vl); return __riscv_vfmacc_vv_f32m2_m(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmacc_vf_f32m2_m // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmacc_vf_f32m2_m
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmacc.mask.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmacc.mask.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfmacc_vf_f32m2_m(vbool16_t mask, vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) { vfloat32m2_t test_vfmacc_vf_f32m2_m(vbool16_t mask, vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfmacc_vf_f32m2_m(mask, vd, rs1, vs2, vl); return __riscv_vfmacc_vf_f32m2_m(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmacc_vv_f32m4_m // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmacc_vv_f32m4_m
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmacc.mask.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmacc.mask.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfmacc_vv_f32m4_m(vbool8_t mask, vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) { vfloat32m4_t test_vfmacc_vv_f32m4_m(vbool8_t mask, vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfmacc_vv_f32m4_m(mask, vd, vs1, vs2, vl); return __riscv_vfmacc_vv_f32m4_m(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmacc_vf_f32m4_m // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmacc_vf_f32m4_m
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmacc.mask.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmacc.mask.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfmacc_vf_f32m4_m(vbool8_t mask, vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) { vfloat32m4_t test_vfmacc_vf_f32m4_m(vbool8_t mask, vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfmacc_vf_f32m4_m(mask, vd, rs1, vs2, vl); return __riscv_vfmacc_vf_f32m4_m(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmacc_vv_f32m8_m // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmacc_vv_f32m8_m
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmacc.mask.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmacc.mask.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfmacc_vv_f32m8_m(vbool4_t mask, vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) { vfloat32m8_t test_vfmacc_vv_f32m8_m(vbool4_t mask, vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfmacc_vv_f32m8_m(mask, vd, vs1, vs2, vl); return __riscv_vfmacc_vv_f32m8_m(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmacc_vf_f32m8_m // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmacc_vf_f32m8_m
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmacc.mask.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmacc.mask.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfmacc_vf_f32m8_m(vbool4_t mask, vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) { vfloat32m8_t test_vfmacc_vf_f32m8_m(vbool4_t mask, vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfmacc_vf_f32m8_m(mask, vd, rs1, vs2, vl); return __riscv_vfmacc_vf_f32m8_m(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmacc_vv_f64m1_m // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmacc_vv_f64m1_m
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmacc.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmacc.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfmacc_vv_f64m1_m(vbool64_t mask, vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) { vfloat64m1_t test_vfmacc_vv_f64m1_m(vbool64_t mask, vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfmacc_vv_f64m1_m(mask, vd, vs1, vs2, vl); return __riscv_vfmacc_vv_f64m1_m(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmacc_vf_f64m1_m // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmacc_vf_f64m1_m
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmacc.mask.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmacc.mask.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfmacc_vf_f64m1_m(vbool64_t mask, vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) { vfloat64m1_t test_vfmacc_vf_f64m1_m(vbool64_t mask, vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfmacc_vf_f64m1_m(mask, vd, rs1, vs2, vl); return __riscv_vfmacc_vf_f64m1_m(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmacc_vv_f64m2_m // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmacc_vv_f64m2_m
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmacc.mask.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmacc.mask.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfmacc_vv_f64m2_m(vbool32_t mask, vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) { vfloat64m2_t test_vfmacc_vv_f64m2_m(vbool32_t mask, vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfmacc_vv_f64m2_m(mask, vd, vs1, vs2, vl); return __riscv_vfmacc_vv_f64m2_m(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmacc_vf_f64m2_m // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmacc_vf_f64m2_m
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmacc.mask.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmacc.mask.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfmacc_vf_f64m2_m(vbool32_t mask, vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) { vfloat64m2_t test_vfmacc_vf_f64m2_m(vbool32_t mask, vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfmacc_vf_f64m2_m(mask, vd, rs1, vs2, vl); return __riscv_vfmacc_vf_f64m2_m(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmacc_vv_f64m4_m // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmacc_vv_f64m4_m
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmacc.mask.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmacc.mask.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfmacc_vv_f64m4_m(vbool16_t mask, vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) { vfloat64m4_t test_vfmacc_vv_f64m4_m(vbool16_t mask, vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfmacc_vv_f64m4_m(mask, vd, vs1, vs2, vl); return __riscv_vfmacc_vv_f64m4_m(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmacc_vf_f64m4_m // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmacc_vf_f64m4_m
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmacc.mask.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmacc.mask.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfmacc_vf_f64m4_m(vbool16_t mask, vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) { vfloat64m4_t test_vfmacc_vf_f64m4_m(vbool16_t mask, vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfmacc_vf_f64m4_m(mask, vd, rs1, vs2, vl); return __riscv_vfmacc_vf_f64m4_m(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmacc_vv_f64m8_m // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmacc_vv_f64m8_m
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmacc.mask.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmacc.mask.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfmacc_vv_f64m8_m(vbool8_t mask, vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) { vfloat64m8_t test_vfmacc_vv_f64m8_m(vbool8_t mask, vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfmacc_vv_f64m8_m(mask, vd, vs1, vs2, vl); return __riscv_vfmacc_vv_f64m8_m(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmacc_vf_f64m8_m // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmacc_vf_f64m8_m
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmacc.mask.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmacc.mask.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfmacc_vf_f64m8_m(vbool8_t mask, vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) { vfloat64m8_t test_vfmacc_vf_f64m8_m(vbool8_t mask, vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfmacc_vf_f64m8_m(mask, vd, rs1, vs2, vl); return __riscv_vfmacc_vf_f64m8_m(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmacc_vv_f16mf4_rm
// CHECK-RV64-SAME: (<vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmacc.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
//
vfloat16mf4_t test_vfmacc_vv_f16mf4_rm(vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfmacc_vv_f16mf4_rm(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmacc_vf_f16mf4_rm
// CHECK-RV64-SAME: (<vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmacc.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
//
vfloat16mf4_t test_vfmacc_vf_f16mf4_rm(vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfmacc_vf_f16mf4_rm(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmacc_vv_f16mf2_rm
// CHECK-RV64-SAME: (<vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmacc.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
//
vfloat16mf2_t test_vfmacc_vv_f16mf2_rm(vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfmacc_vv_f16mf2_rm(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmacc_vf_f16mf2_rm
// CHECK-RV64-SAME: (<vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmacc.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
//
vfloat16mf2_t test_vfmacc_vf_f16mf2_rm(vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfmacc_vf_f16mf2_rm(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmacc_vv_f16m1_rm
// CHECK-RV64-SAME: (<vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmacc.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfmacc_vv_f16m1_rm(vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfmacc_vv_f16m1_rm(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmacc_vf_f16m1_rm
// CHECK-RV64-SAME: (<vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmacc.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfmacc_vf_f16m1_rm(vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfmacc_vf_f16m1_rm(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmacc_vv_f16m2_rm
// CHECK-RV64-SAME: (<vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmacc.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
//
vfloat16m2_t test_vfmacc_vv_f16m2_rm(vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfmacc_vv_f16m2_rm(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmacc_vf_f16m2_rm
// CHECK-RV64-SAME: (<vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmacc.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
//
vfloat16m2_t test_vfmacc_vf_f16m2_rm(vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfmacc_vf_f16m2_rm(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmacc_vv_f16m4_rm
// CHECK-RV64-SAME: (<vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmacc.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
//
vfloat16m4_t test_vfmacc_vv_f16m4_rm(vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfmacc_vv_f16m4_rm(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmacc_vf_f16m4_rm
// CHECK-RV64-SAME: (<vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmacc.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
//
vfloat16m4_t test_vfmacc_vf_f16m4_rm(vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfmacc_vf_f16m4_rm(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmacc_vv_f16m8_rm
// CHECK-RV64-SAME: (<vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmacc.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
//
vfloat16m8_t test_vfmacc_vv_f16m8_rm(vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfmacc_vv_f16m8_rm(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmacc_vf_f16m8_rm
// CHECK-RV64-SAME: (<vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmacc.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
//
vfloat16m8_t test_vfmacc_vf_f16m8_rm(vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfmacc_vf_f16m8_rm(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmacc_vv_f32mf2_rm
// CHECK-RV64-SAME: (<vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmacc.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
//
vfloat32mf2_t test_vfmacc_vv_f32mf2_rm(vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfmacc_vv_f32mf2_rm(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmacc_vf_f32mf2_rm
// CHECK-RV64-SAME: (<vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmacc.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
//
vfloat32mf2_t test_vfmacc_vf_f32mf2_rm(vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfmacc_vf_f32mf2_rm(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmacc_vv_f32m1_rm
// CHECK-RV64-SAME: (<vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmacc.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfmacc_vv_f32m1_rm(vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfmacc_vv_f32m1_rm(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmacc_vf_f32m1_rm
// CHECK-RV64-SAME: (<vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmacc.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfmacc_vf_f32m1_rm(vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfmacc_vf_f32m1_rm(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmacc_vv_f32m2_rm
// CHECK-RV64-SAME: (<vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmacc.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
//
vfloat32m2_t test_vfmacc_vv_f32m2_rm(vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfmacc_vv_f32m2_rm(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmacc_vf_f32m2_rm
// CHECK-RV64-SAME: (<vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmacc.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
//
vfloat32m2_t test_vfmacc_vf_f32m2_rm(vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfmacc_vf_f32m2_rm(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmacc_vv_f32m4_rm
// CHECK-RV64-SAME: (<vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmacc.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
//
vfloat32m4_t test_vfmacc_vv_f32m4_rm(vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfmacc_vv_f32m4_rm(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmacc_vf_f32m4_rm
// CHECK-RV64-SAME: (<vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmacc.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
//
vfloat32m4_t test_vfmacc_vf_f32m4_rm(vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfmacc_vf_f32m4_rm(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmacc_vv_f32m8_rm
// CHECK-RV64-SAME: (<vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmacc.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
//
vfloat32m8_t test_vfmacc_vv_f32m8_rm(vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfmacc_vv_f32m8_rm(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmacc_vf_f32m8_rm
// CHECK-RV64-SAME: (<vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmacc.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
//
vfloat32m8_t test_vfmacc_vf_f32m8_rm(vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfmacc_vf_f32m8_rm(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmacc_vv_f64m1_rm
// CHECK-RV64-SAME: (<vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmacc.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfmacc_vv_f64m1_rm(vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfmacc_vv_f64m1_rm(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmacc_vf_f64m1_rm
// CHECK-RV64-SAME: (<vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmacc.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfmacc_vf_f64m1_rm(vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfmacc_vf_f64m1_rm(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmacc_vv_f64m2_rm
// CHECK-RV64-SAME: (<vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmacc.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
//
vfloat64m2_t test_vfmacc_vv_f64m2_rm(vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfmacc_vv_f64m2_rm(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmacc_vf_f64m2_rm
// CHECK-RV64-SAME: (<vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmacc.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
//
vfloat64m2_t test_vfmacc_vf_f64m2_rm(vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfmacc_vf_f64m2_rm(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmacc_vv_f64m4_rm
// CHECK-RV64-SAME: (<vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmacc.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
//
vfloat64m4_t test_vfmacc_vv_f64m4_rm(vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfmacc_vv_f64m4_rm(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmacc_vf_f64m4_rm
// CHECK-RV64-SAME: (<vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmacc.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
//
vfloat64m4_t test_vfmacc_vf_f64m4_rm(vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfmacc_vf_f64m4_rm(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmacc_vv_f64m8_rm
// CHECK-RV64-SAME: (<vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmacc.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
//
vfloat64m8_t test_vfmacc_vv_f64m8_rm(vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfmacc_vv_f64m8_rm(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmacc_vf_f64m8_rm
// CHECK-RV64-SAME: (<vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmacc.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
//
vfloat64m8_t test_vfmacc_vf_f64m8_rm(vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfmacc_vf_f64m8_rm(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmacc_vv_f16mf4_rm_m
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmacc.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
//
vfloat16mf4_t test_vfmacc_vv_f16mf4_rm_m(vbool64_t mask, vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfmacc_vv_f16mf4_rm_m(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmacc_vf_f16mf4_rm_m
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmacc.mask.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
//
vfloat16mf4_t test_vfmacc_vf_f16mf4_rm_m(vbool64_t mask, vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfmacc_vf_f16mf4_rm_m(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmacc_vv_f16mf2_rm_m
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmacc.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
//
vfloat16mf2_t test_vfmacc_vv_f16mf2_rm_m(vbool32_t mask, vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfmacc_vv_f16mf2_rm_m(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmacc_vf_f16mf2_rm_m
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmacc.mask.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
//
vfloat16mf2_t test_vfmacc_vf_f16mf2_rm_m(vbool32_t mask, vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfmacc_vf_f16mf2_rm_m(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmacc_vv_f16m1_rm_m
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmacc.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfmacc_vv_f16m1_rm_m(vbool16_t mask, vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfmacc_vv_f16m1_rm_m(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmacc_vf_f16m1_rm_m
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmacc.mask.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfmacc_vf_f16m1_rm_m(vbool16_t mask, vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfmacc_vf_f16m1_rm_m(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmacc_vv_f16m2_rm_m
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmacc.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
//
vfloat16m2_t test_vfmacc_vv_f16m2_rm_m(vbool8_t mask, vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfmacc_vv_f16m2_rm_m(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmacc_vf_f16m2_rm_m
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmacc.mask.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
//
vfloat16m2_t test_vfmacc_vf_f16m2_rm_m(vbool8_t mask, vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfmacc_vf_f16m2_rm_m(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmacc_vv_f16m4_rm_m
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmacc.mask.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
//
vfloat16m4_t test_vfmacc_vv_f16m4_rm_m(vbool4_t mask, vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfmacc_vv_f16m4_rm_m(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmacc_vf_f16m4_rm_m
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmacc.mask.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
//
vfloat16m4_t test_vfmacc_vf_f16m4_rm_m(vbool4_t mask, vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfmacc_vf_f16m4_rm_m(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmacc_vv_f16m8_rm_m
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmacc.mask.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
//
vfloat16m8_t test_vfmacc_vv_f16m8_rm_m(vbool2_t mask, vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfmacc_vv_f16m8_rm_m(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmacc_vf_f16m8_rm_m
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmacc.mask.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
//
vfloat16m8_t test_vfmacc_vf_f16m8_rm_m(vbool2_t mask, vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfmacc_vf_f16m8_rm_m(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmacc_vv_f32mf2_rm_m
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmacc.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
//
vfloat32mf2_t test_vfmacc_vv_f32mf2_rm_m(vbool64_t mask, vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfmacc_vv_f32mf2_rm_m(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmacc_vf_f32mf2_rm_m
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmacc.mask.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
//
vfloat32mf2_t test_vfmacc_vf_f32mf2_rm_m(vbool64_t mask, vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfmacc_vf_f32mf2_rm_m(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmacc_vv_f32m1_rm_m
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmacc.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfmacc_vv_f32m1_rm_m(vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfmacc_vv_f32m1_rm_m(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmacc_vf_f32m1_rm_m
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmacc.mask.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfmacc_vf_f32m1_rm_m(vbool32_t mask, vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfmacc_vf_f32m1_rm_m(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmacc_vv_f32m2_rm_m
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmacc.mask.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
//
vfloat32m2_t test_vfmacc_vv_f32m2_rm_m(vbool16_t mask, vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfmacc_vv_f32m2_rm_m(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmacc_vf_f32m2_rm_m
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmacc.mask.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
//
vfloat32m2_t test_vfmacc_vf_f32m2_rm_m(vbool16_t mask, vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfmacc_vf_f32m2_rm_m(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmacc_vv_f32m4_rm_m
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmacc.mask.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
//
vfloat32m4_t test_vfmacc_vv_f32m4_rm_m(vbool8_t mask, vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfmacc_vv_f32m4_rm_m(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmacc_vf_f32m4_rm_m
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmacc.mask.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
//
vfloat32m4_t test_vfmacc_vf_f32m4_rm_m(vbool8_t mask, vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfmacc_vf_f32m4_rm_m(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmacc_vv_f32m8_rm_m
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmacc.mask.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
//
vfloat32m8_t test_vfmacc_vv_f32m8_rm_m(vbool4_t mask, vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfmacc_vv_f32m8_rm_m(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmacc_vf_f32m8_rm_m
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmacc.mask.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
//
vfloat32m8_t test_vfmacc_vf_f32m8_rm_m(vbool4_t mask, vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfmacc_vf_f32m8_rm_m(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmacc_vv_f64m1_rm_m
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmacc.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfmacc_vv_f64m1_rm_m(vbool64_t mask, vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfmacc_vv_f64m1_rm_m(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmacc_vf_f64m1_rm_m
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmacc.mask.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfmacc_vf_f64m1_rm_m(vbool64_t mask, vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfmacc_vf_f64m1_rm_m(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmacc_vv_f64m2_rm_m
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmacc.mask.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
//
vfloat64m2_t test_vfmacc_vv_f64m2_rm_m(vbool32_t mask, vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfmacc_vv_f64m2_rm_m(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmacc_vf_f64m2_rm_m
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmacc.mask.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
//
vfloat64m2_t test_vfmacc_vf_f64m2_rm_m(vbool32_t mask, vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfmacc_vf_f64m2_rm_m(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmacc_vv_f64m4_rm_m
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmacc.mask.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
//
vfloat64m4_t test_vfmacc_vv_f64m4_rm_m(vbool16_t mask, vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfmacc_vv_f64m4_rm_m(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmacc_vf_f64m4_rm_m
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmacc.mask.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
//
vfloat64m4_t test_vfmacc_vf_f64m4_rm_m(vbool16_t mask, vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfmacc_vf_f64m4_rm_m(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmacc_vv_f64m8_rm_m
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmacc.mask.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
//
vfloat64m8_t test_vfmacc_vv_f64m8_rm_m(vbool8_t mask, vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfmacc_vv_f64m8_rm_m(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmacc_vf_f64m8_rm_m
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmacc.mask.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
//
vfloat64m8_t test_vfmacc_vf_f64m8_rm_m(vbool8_t mask, vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfmacc_vf_f64m8_rm_m(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}

clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmadd.c

// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target // REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh \ // RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh \
// RUN: -target-feature +experimental-zvfh -disable-O0-optnone \ // RUN: -target-feature +experimental-zvfh -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ // RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s // RUN: FileCheck --check-prefix=CHECK-RV64 %s
#include <riscv_vector.h> #include <riscv_vector.h>
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmadd_vv_f16mf4 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmadd_vv_f16mf4
// CHECK-RV64-SAME: (<vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK-RV64-SAME: (<vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmadd.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmadd.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
// //
vfloat16mf4_t test_vfmadd_vv_f16mf4(vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) { vfloat16mf4_t test_vfmadd_vv_f16mf4(vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfmadd_vv_f16mf4(vd, vs1, vs2, vl); return __riscv_vfmadd_vv_f16mf4(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmadd_vf_f16mf4 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmadd_vf_f16mf4
// CHECK-RV64-SAME: (<vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmadd.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmadd.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
// //
vfloat16mf4_t test_vfmadd_vf_f16mf4(vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) { vfloat16mf4_t test_vfmadd_vf_f16mf4(vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfmadd_vf_f16mf4(vd, rs1, vs2, vl); return __riscv_vfmadd_vf_f16mf4(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmadd_vv_f16mf2 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmadd_vv_f16mf2
// CHECK-RV64-SAME: (<vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmadd.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmadd.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
// //
vfloat16mf2_t test_vfmadd_vv_f16mf2(vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) { vfloat16mf2_t test_vfmadd_vv_f16mf2(vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfmadd_vv_f16mf2(vd, vs1, vs2, vl); return __riscv_vfmadd_vv_f16mf2(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmadd_vf_f16mf2 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmadd_vf_f16mf2
// CHECK-RV64-SAME: (<vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmadd.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmadd.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
// //
vfloat16mf2_t test_vfmadd_vf_f16mf2(vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) { vfloat16mf2_t test_vfmadd_vf_f16mf2(vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfmadd_vf_f16mf2(vd, rs1, vs2, vl); return __riscv_vfmadd_vf_f16mf2(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmadd_vv_f16m1 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmadd_vv_f16m1
// CHECK-RV64-SAME: (<vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmadd.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmadd.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
// //
vfloat16m1_t test_vfmadd_vv_f16m1(vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) { vfloat16m1_t test_vfmadd_vv_f16m1(vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfmadd_vv_f16m1(vd, vs1, vs2, vl); return __riscv_vfmadd_vv_f16m1(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmadd_vf_f16m1 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmadd_vf_f16m1
// CHECK-RV64-SAME: (<vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmadd.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmadd.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
// //
vfloat16m1_t test_vfmadd_vf_f16m1(vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) { vfloat16m1_t test_vfmadd_vf_f16m1(vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfmadd_vf_f16m1(vd, rs1, vs2, vl); return __riscv_vfmadd_vf_f16m1(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmadd_vv_f16m2 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmadd_vv_f16m2
// CHECK-RV64-SAME: (<vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmadd.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmadd.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
// //
vfloat16m2_t test_vfmadd_vv_f16m2(vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) { vfloat16m2_t test_vfmadd_vv_f16m2(vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfmadd_vv_f16m2(vd, vs1, vs2, vl); return __riscv_vfmadd_vv_f16m2(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmadd_vf_f16m2 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmadd_vf_f16m2
// CHECK-RV64-SAME: (<vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmadd.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmadd.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
// //
vfloat16m2_t test_vfmadd_vf_f16m2(vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) { vfloat16m2_t test_vfmadd_vf_f16m2(vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfmadd_vf_f16m2(vd, rs1, vs2, vl); return __riscv_vfmadd_vf_f16m2(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmadd_vv_f16m4 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmadd_vv_f16m4
// CHECK-RV64-SAME: (<vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmadd.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmadd.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
// //
vfloat16m4_t test_vfmadd_vv_f16m4(vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) { vfloat16m4_t test_vfmadd_vv_f16m4(vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfmadd_vv_f16m4(vd, vs1, vs2, vl); return __riscv_vfmadd_vv_f16m4(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmadd_vf_f16m4 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmadd_vf_f16m4
// CHECK-RV64-SAME: (<vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmadd.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmadd.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
// //
vfloat16m4_t test_vfmadd_vf_f16m4(vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) { vfloat16m4_t test_vfmadd_vf_f16m4(vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfmadd_vf_f16m4(vd, rs1, vs2, vl); return __riscv_vfmadd_vf_f16m4(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmadd_vv_f16m8 // CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmadd_vv_f16m8
// CHECK-RV64-SAME: (<vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmadd.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmadd.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
// //
vfloat16m8_t test_vfmadd_vv_f16m8(vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) { vfloat16m8_t test_vfmadd_vv_f16m8(vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfmadd_vv_f16m8(vd, vs1, vs2, vl); return __riscv_vfmadd_vv_f16m8(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmadd_vf_f16m8 // CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmadd_vf_f16m8
// CHECK-RV64-SAME: (<vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmadd.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmadd.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
// //
vfloat16m8_t test_vfmadd_vf_f16m8(vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) { vfloat16m8_t test_vfmadd_vf_f16m8(vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfmadd_vf_f16m8(vd, rs1, vs2, vl); return __riscv_vfmadd_vf_f16m8(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmadd_vv_f32mf2 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmadd_vv_f32mf2
// CHECK-RV64-SAME: (<vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmadd.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmadd.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfmadd_vv_f32mf2(vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) { vfloat32mf2_t test_vfmadd_vv_f32mf2(vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfmadd_vv_f32mf2(vd, vs1, vs2, vl); return __riscv_vfmadd_vv_f32mf2(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmadd_vf_f32mf2 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmadd_vf_f32mf2
// CHECK-RV64-SAME: (<vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmadd.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmadd.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfmadd_vf_f32mf2(vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) { vfloat32mf2_t test_vfmadd_vf_f32mf2(vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfmadd_vf_f32mf2(vd, rs1, vs2, vl); return __riscv_vfmadd_vf_f32mf2(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmadd_vv_f32m1 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmadd_vv_f32m1
// CHECK-RV64-SAME: (<vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmadd.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmadd.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfmadd_vv_f32m1(vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) { vfloat32m1_t test_vfmadd_vv_f32m1(vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfmadd_vv_f32m1(vd, vs1, vs2, vl); return __riscv_vfmadd_vv_f32m1(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmadd_vf_f32m1 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmadd_vf_f32m1
// CHECK-RV64-SAME: (<vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmadd.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmadd.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfmadd_vf_f32m1(vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) { vfloat32m1_t test_vfmadd_vf_f32m1(vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfmadd_vf_f32m1(vd, rs1, vs2, vl); return __riscv_vfmadd_vf_f32m1(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmadd_vv_f32m2 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmadd_vv_f32m2
// CHECK-RV64-SAME: (<vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmadd.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmadd.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfmadd_vv_f32m2(vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) { vfloat32m2_t test_vfmadd_vv_f32m2(vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfmadd_vv_f32m2(vd, vs1, vs2, vl); return __riscv_vfmadd_vv_f32m2(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmadd_vf_f32m2 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmadd_vf_f32m2
// CHECK-RV64-SAME: (<vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmadd.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmadd.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfmadd_vf_f32m2(vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) { vfloat32m2_t test_vfmadd_vf_f32m2(vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfmadd_vf_f32m2(vd, rs1, vs2, vl); return __riscv_vfmadd_vf_f32m2(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmadd_vv_f32m4 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmadd_vv_f32m4
// CHECK-RV64-SAME: (<vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmadd.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmadd.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfmadd_vv_f32m4(vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) { vfloat32m4_t test_vfmadd_vv_f32m4(vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfmadd_vv_f32m4(vd, vs1, vs2, vl); return __riscv_vfmadd_vv_f32m4(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmadd_vf_f32m4 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmadd_vf_f32m4
// CHECK-RV64-SAME: (<vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmadd.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmadd.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfmadd_vf_f32m4(vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) { vfloat32m4_t test_vfmadd_vf_f32m4(vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfmadd_vf_f32m4(vd, rs1, vs2, vl); return __riscv_vfmadd_vf_f32m4(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmadd_vv_f32m8 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmadd_vv_f32m8
// CHECK-RV64-SAME: (<vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmadd.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmadd.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfmadd_vv_f32m8(vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) { vfloat32m8_t test_vfmadd_vv_f32m8(vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfmadd_vv_f32m8(vd, vs1, vs2, vl); return __riscv_vfmadd_vv_f32m8(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmadd_vf_f32m8 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmadd_vf_f32m8
// CHECK-RV64-SAME: (<vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmadd.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmadd.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfmadd_vf_f32m8(vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) { vfloat32m8_t test_vfmadd_vf_f32m8(vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfmadd_vf_f32m8(vd, rs1, vs2, vl); return __riscv_vfmadd_vf_f32m8(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmadd_vv_f64m1 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmadd_vv_f64m1
// CHECK-RV64-SAME: (<vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmadd.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmadd.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfmadd_vv_f64m1(vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) { vfloat64m1_t test_vfmadd_vv_f64m1(vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfmadd_vv_f64m1(vd, vs1, vs2, vl); return __riscv_vfmadd_vv_f64m1(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmadd_vf_f64m1 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmadd_vf_f64m1
// CHECK-RV64-SAME: (<vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmadd.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmadd.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfmadd_vf_f64m1(vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) { vfloat64m1_t test_vfmadd_vf_f64m1(vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfmadd_vf_f64m1(vd, rs1, vs2, vl); return __riscv_vfmadd_vf_f64m1(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmadd_vv_f64m2 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmadd_vv_f64m2
// CHECK-RV64-SAME: (<vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmadd.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmadd.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfmadd_vv_f64m2(vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) { vfloat64m2_t test_vfmadd_vv_f64m2(vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfmadd_vv_f64m2(vd, vs1, vs2, vl); return __riscv_vfmadd_vv_f64m2(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmadd_vf_f64m2 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmadd_vf_f64m2
// CHECK-RV64-SAME: (<vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmadd.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmadd.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfmadd_vf_f64m2(vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) { vfloat64m2_t test_vfmadd_vf_f64m2(vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfmadd_vf_f64m2(vd, rs1, vs2, vl); return __riscv_vfmadd_vf_f64m2(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmadd_vv_f64m4 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmadd_vv_f64m4
// CHECK-RV64-SAME: (<vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmadd.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmadd.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfmadd_vv_f64m4(vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) { vfloat64m4_t test_vfmadd_vv_f64m4(vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfmadd_vv_f64m4(vd, vs1, vs2, vl); return __riscv_vfmadd_vv_f64m4(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmadd_vf_f64m4 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmadd_vf_f64m4
// CHECK-RV64-SAME: (<vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmadd.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmadd.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfmadd_vf_f64m4(vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) { vfloat64m4_t test_vfmadd_vf_f64m4(vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfmadd_vf_f64m4(vd, rs1, vs2, vl); return __riscv_vfmadd_vf_f64m4(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmadd_vv_f64m8 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmadd_vv_f64m8
// CHECK-RV64-SAME: (<vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmadd.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmadd.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfmadd_vv_f64m8(vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) { vfloat64m8_t test_vfmadd_vv_f64m8(vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfmadd_vv_f64m8(vd, vs1, vs2, vl); return __riscv_vfmadd_vv_f64m8(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmadd_vf_f64m8 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmadd_vf_f64m8
// CHECK-RV64-SAME: (<vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmadd.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmadd.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfmadd_vf_f64m8(vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) { vfloat64m8_t test_vfmadd_vf_f64m8(vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfmadd_vf_f64m8(vd, rs1, vs2, vl); return __riscv_vfmadd_vf_f64m8(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmadd_vv_f16mf4_m // CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmadd_vv_f16mf4_m
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmadd.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmadd.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
// //
vfloat16mf4_t test_vfmadd_vv_f16mf4_m(vbool64_t mask, vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) { vfloat16mf4_t test_vfmadd_vv_f16mf4_m(vbool64_t mask, vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfmadd_vv_f16mf4_m(mask, vd, vs1, vs2, vl); return __riscv_vfmadd_vv_f16mf4_m(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmadd_vf_f16mf4_m // CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmadd_vf_f16mf4_m
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmadd.mask.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmadd.mask.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
// //
vfloat16mf4_t test_vfmadd_vf_f16mf4_m(vbool64_t mask, vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) { vfloat16mf4_t test_vfmadd_vf_f16mf4_m(vbool64_t mask, vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfmadd_vf_f16mf4_m(mask, vd, rs1, vs2, vl); return __riscv_vfmadd_vf_f16mf4_m(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmadd_vv_f16mf2_m // CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmadd_vv_f16mf2_m
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmadd.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmadd.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
// //
vfloat16mf2_t test_vfmadd_vv_f16mf2_m(vbool32_t mask, vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) { vfloat16mf2_t test_vfmadd_vv_f16mf2_m(vbool32_t mask, vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfmadd_vv_f16mf2_m(mask, vd, vs1, vs2, vl); return __riscv_vfmadd_vv_f16mf2_m(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmadd_vf_f16mf2_m // CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmadd_vf_f16mf2_m
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmadd.mask.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmadd.mask.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
// //
vfloat16mf2_t test_vfmadd_vf_f16mf2_m(vbool32_t mask, vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) { vfloat16mf2_t test_vfmadd_vf_f16mf2_m(vbool32_t mask, vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfmadd_vf_f16mf2_m(mask, vd, rs1, vs2, vl); return __riscv_vfmadd_vf_f16mf2_m(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmadd_vv_f16m1_m // CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmadd_vv_f16m1_m
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmadd.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmadd.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
// //
vfloat16m1_t test_vfmadd_vv_f16m1_m(vbool16_t mask, vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) { vfloat16m1_t test_vfmadd_vv_f16m1_m(vbool16_t mask, vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfmadd_vv_f16m1_m(mask, vd, vs1, vs2, vl); return __riscv_vfmadd_vv_f16m1_m(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmadd_vf_f16m1_m // CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmadd_vf_f16m1_m
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmadd.mask.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmadd.mask.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
// //
vfloat16m1_t test_vfmadd_vf_f16m1_m(vbool16_t mask, vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) { vfloat16m1_t test_vfmadd_vf_f16m1_m(vbool16_t mask, vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfmadd_vf_f16m1_m(mask, vd, rs1, vs2, vl); return __riscv_vfmadd_vf_f16m1_m(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmadd_vv_f16m2_m // CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmadd_vv_f16m2_m
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmadd.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmadd.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
// //
vfloat16m2_t test_vfmadd_vv_f16m2_m(vbool8_t mask, vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) { vfloat16m2_t test_vfmadd_vv_f16m2_m(vbool8_t mask, vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfmadd_vv_f16m2_m(mask, vd, vs1, vs2, vl); return __riscv_vfmadd_vv_f16m2_m(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmadd_vf_f16m2_m // CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmadd_vf_f16m2_m
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmadd.mask.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmadd.mask.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
// //
vfloat16m2_t test_vfmadd_vf_f16m2_m(vbool8_t mask, vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) { vfloat16m2_t test_vfmadd_vf_f16m2_m(vbool8_t mask, vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfmadd_vf_f16m2_m(mask, vd, rs1, vs2, vl); return __riscv_vfmadd_vf_f16m2_m(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmadd_vv_f16m4_m // CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmadd_vv_f16m4_m
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmadd.mask.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmadd.mask.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
// //
vfloat16m4_t test_vfmadd_vv_f16m4_m(vbool4_t mask, vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) { vfloat16m4_t test_vfmadd_vv_f16m4_m(vbool4_t mask, vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfmadd_vv_f16m4_m(mask, vd, vs1, vs2, vl); return __riscv_vfmadd_vv_f16m4_m(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmadd_vf_f16m4_m // CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmadd_vf_f16m4_m
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmadd.mask.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmadd.mask.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
// //
vfloat16m4_t test_vfmadd_vf_f16m4_m(vbool4_t mask, vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) { vfloat16m4_t test_vfmadd_vf_f16m4_m(vbool4_t mask, vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfmadd_vf_f16m4_m(mask, vd, rs1, vs2, vl); return __riscv_vfmadd_vf_f16m4_m(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmadd_vv_f16m8_m // CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmadd_vv_f16m8_m
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmadd.mask.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmadd.mask.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
// //
vfloat16m8_t test_vfmadd_vv_f16m8_m(vbool2_t mask, vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) { vfloat16m8_t test_vfmadd_vv_f16m8_m(vbool2_t mask, vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfmadd_vv_f16m8_m(mask, vd, vs1, vs2, vl); return __riscv_vfmadd_vv_f16m8_m(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmadd_vf_f16m8_m // CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmadd_vf_f16m8_m
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmadd.mask.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmadd.mask.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
// //
vfloat16m8_t test_vfmadd_vf_f16m8_m(vbool2_t mask, vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) { vfloat16m8_t test_vfmadd_vf_f16m8_m(vbool2_t mask, vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfmadd_vf_f16m8_m(mask, vd, rs1, vs2, vl); return __riscv_vfmadd_vf_f16m8_m(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmadd_vv_f32mf2_m // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmadd_vv_f32mf2_m
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmadd.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmadd.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfmadd_vv_f32mf2_m(vbool64_t mask, vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) { vfloat32mf2_t test_vfmadd_vv_f32mf2_m(vbool64_t mask, vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfmadd_vv_f32mf2_m(mask, vd, vs1, vs2, vl); return __riscv_vfmadd_vv_f32mf2_m(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmadd_vf_f32mf2_m // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmadd_vf_f32mf2_m
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmadd.mask.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmadd.mask.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfmadd_vf_f32mf2_m(vbool64_t mask, vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) { vfloat32mf2_t test_vfmadd_vf_f32mf2_m(vbool64_t mask, vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfmadd_vf_f32mf2_m(mask, vd, rs1, vs2, vl); return __riscv_vfmadd_vf_f32mf2_m(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmadd_vv_f32m1_m // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmadd_vv_f32m1_m
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmadd.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmadd.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfmadd_vv_f32m1_m(vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) { vfloat32m1_t test_vfmadd_vv_f32m1_m(vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfmadd_vv_f32m1_m(mask, vd, vs1, vs2, vl); return __riscv_vfmadd_vv_f32m1_m(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmadd_vf_f32m1_m // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmadd_vf_f32m1_m
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmadd.mask.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmadd.mask.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfmadd_vf_f32m1_m(vbool32_t mask, vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) { vfloat32m1_t test_vfmadd_vf_f32m1_m(vbool32_t mask, vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfmadd_vf_f32m1_m(mask, vd, rs1, vs2, vl); return __riscv_vfmadd_vf_f32m1_m(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmadd_vv_f32m2_m // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmadd_vv_f32m2_m
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmadd.mask.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmadd.mask.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfmadd_vv_f32m2_m(vbool16_t mask, vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) { vfloat32m2_t test_vfmadd_vv_f32m2_m(vbool16_t mask, vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfmadd_vv_f32m2_m(mask, vd, vs1, vs2, vl); return __riscv_vfmadd_vv_f32m2_m(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmadd_vf_f32m2_m // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmadd_vf_f32m2_m
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmadd.mask.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmadd.mask.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfmadd_vf_f32m2_m(vbool16_t mask, vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) { vfloat32m2_t test_vfmadd_vf_f32m2_m(vbool16_t mask, vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfmadd_vf_f32m2_m(mask, vd, rs1, vs2, vl); return __riscv_vfmadd_vf_f32m2_m(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmadd_vv_f32m4_m // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmadd_vv_f32m4_m
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmadd.mask.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmadd.mask.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfmadd_vv_f32m4_m(vbool8_t mask, vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) { vfloat32m4_t test_vfmadd_vv_f32m4_m(vbool8_t mask, vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfmadd_vv_f32m4_m(mask, vd, vs1, vs2, vl); return __riscv_vfmadd_vv_f32m4_m(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmadd_vf_f32m4_m // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmadd_vf_f32m4_m
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmadd.mask.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmadd.mask.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfmadd_vf_f32m4_m(vbool8_t mask, vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) { vfloat32m4_t test_vfmadd_vf_f32m4_m(vbool8_t mask, vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfmadd_vf_f32m4_m(mask, vd, rs1, vs2, vl); return __riscv_vfmadd_vf_f32m4_m(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmadd_vv_f32m8_m // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmadd_vv_f32m8_m
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmadd.mask.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmadd.mask.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfmadd_vv_f32m8_m(vbool4_t mask, vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) { vfloat32m8_t test_vfmadd_vv_f32m8_m(vbool4_t mask, vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfmadd_vv_f32m8_m(mask, vd, vs1, vs2, vl); return __riscv_vfmadd_vv_f32m8_m(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmadd_vf_f32m8_m // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmadd_vf_f32m8_m
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmadd.mask.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmadd.mask.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfmadd_vf_f32m8_m(vbool4_t mask, vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) { vfloat32m8_t test_vfmadd_vf_f32m8_m(vbool4_t mask, vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfmadd_vf_f32m8_m(mask, vd, rs1, vs2, vl); return __riscv_vfmadd_vf_f32m8_m(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmadd_vv_f64m1_m // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmadd_vv_f64m1_m
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmadd.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmadd.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfmadd_vv_f64m1_m(vbool64_t mask, vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) { vfloat64m1_t test_vfmadd_vv_f64m1_m(vbool64_t mask, vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfmadd_vv_f64m1_m(mask, vd, vs1, vs2, vl); return __riscv_vfmadd_vv_f64m1_m(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmadd_vf_f64m1_m // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmadd_vf_f64m1_m
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmadd.mask.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmadd.mask.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfmadd_vf_f64m1_m(vbool64_t mask, vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) { vfloat64m1_t test_vfmadd_vf_f64m1_m(vbool64_t mask, vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfmadd_vf_f64m1_m(mask, vd, rs1, vs2, vl); return __riscv_vfmadd_vf_f64m1_m(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmadd_vv_f64m2_m // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmadd_vv_f64m2_m
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmadd.mask.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmadd.mask.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfmadd_vv_f64m2_m(vbool32_t mask, vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) { vfloat64m2_t test_vfmadd_vv_f64m2_m(vbool32_t mask, vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfmadd_vv_f64m2_m(mask, vd, vs1, vs2, vl); return __riscv_vfmadd_vv_f64m2_m(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmadd_vf_f64m2_m // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmadd_vf_f64m2_m
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmadd.mask.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmadd.mask.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfmadd_vf_f64m2_m(vbool32_t mask, vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) { vfloat64m2_t test_vfmadd_vf_f64m2_m(vbool32_t mask, vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfmadd_vf_f64m2_m(mask, vd, rs1, vs2, vl); return __riscv_vfmadd_vf_f64m2_m(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmadd_vv_f64m4_m // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmadd_vv_f64m4_m
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmadd.mask.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmadd.mask.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfmadd_vv_f64m4_m(vbool16_t mask, vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) { vfloat64m4_t test_vfmadd_vv_f64m4_m(vbool16_t mask, vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfmadd_vv_f64m4_m(mask, vd, vs1, vs2, vl); return __riscv_vfmadd_vv_f64m4_m(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmadd_vf_f64m4_m // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmadd_vf_f64m4_m
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmadd.mask.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmadd.mask.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfmadd_vf_f64m4_m(vbool16_t mask, vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) { vfloat64m4_t test_vfmadd_vf_f64m4_m(vbool16_t mask, vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfmadd_vf_f64m4_m(mask, vd, rs1, vs2, vl); return __riscv_vfmadd_vf_f64m4_m(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmadd_vv_f64m8_m // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmadd_vv_f64m8_m
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmadd.mask.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmadd.mask.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfmadd_vv_f64m8_m(vbool8_t mask, vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) { vfloat64m8_t test_vfmadd_vv_f64m8_m(vbool8_t mask, vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfmadd_vv_f64m8_m(mask, vd, vs1, vs2, vl); return __riscv_vfmadd_vv_f64m8_m(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmadd_vf_f64m8_m // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmadd_vf_f64m8_m
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmadd.mask.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmadd.mask.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfmadd_vf_f64m8_m(vbool8_t mask, vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) { vfloat64m8_t test_vfmadd_vf_f64m8_m(vbool8_t mask, vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfmadd_vf_f64m8_m(mask, vd, rs1, vs2, vl); return __riscv_vfmadd_vf_f64m8_m(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmadd_vv_f16mf4_rm
// CHECK-RV64-SAME: (<vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmadd.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
//
vfloat16mf4_t test_vfmadd_vv_f16mf4_rm(vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfmadd_vv_f16mf4_rm(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmadd_vf_f16mf4_rm
// CHECK-RV64-SAME: (<vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmadd.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
//
vfloat16mf4_t test_vfmadd_vf_f16mf4_rm(vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfmadd_vf_f16mf4_rm(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmadd_vv_f16mf2_rm
// CHECK-RV64-SAME: (<vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmadd.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
//
vfloat16mf2_t test_vfmadd_vv_f16mf2_rm(vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfmadd_vv_f16mf2_rm(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmadd_vf_f16mf2_rm
// CHECK-RV64-SAME: (<vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmadd.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
//
vfloat16mf2_t test_vfmadd_vf_f16mf2_rm(vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfmadd_vf_f16mf2_rm(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmadd_vv_f16m1_rm
// CHECK-RV64-SAME: (<vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmadd.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfmadd_vv_f16m1_rm(vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfmadd_vv_f16m1_rm(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmadd_vf_f16m1_rm
// CHECK-RV64-SAME: (<vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmadd.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfmadd_vf_f16m1_rm(vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfmadd_vf_f16m1_rm(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmadd_vv_f16m2_rm
// CHECK-RV64-SAME: (<vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmadd.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
//
vfloat16m2_t test_vfmadd_vv_f16m2_rm(vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfmadd_vv_f16m2_rm(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmadd_vf_f16m2_rm
// CHECK-RV64-SAME: (<vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmadd.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
//
vfloat16m2_t test_vfmadd_vf_f16m2_rm(vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfmadd_vf_f16m2_rm(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmadd_vv_f16m4_rm
// CHECK-RV64-SAME: (<vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmadd.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
//
vfloat16m4_t test_vfmadd_vv_f16m4_rm(vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfmadd_vv_f16m4_rm(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmadd_vf_f16m4_rm
// CHECK-RV64-SAME: (<vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmadd.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
//
vfloat16m4_t test_vfmadd_vf_f16m4_rm(vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfmadd_vf_f16m4_rm(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmadd_vv_f16m8_rm
// CHECK-RV64-SAME: (<vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmadd.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
//
vfloat16m8_t test_vfmadd_vv_f16m8_rm(vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfmadd_vv_f16m8_rm(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmadd_vf_f16m8_rm
// CHECK-RV64-SAME: (<vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmadd.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
//
vfloat16m8_t test_vfmadd_vf_f16m8_rm(vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfmadd_vf_f16m8_rm(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmadd_vv_f32mf2_rm
// CHECK-RV64-SAME: (<vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmadd.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
//
vfloat32mf2_t test_vfmadd_vv_f32mf2_rm(vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfmadd_vv_f32mf2_rm(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmadd_vf_f32mf2_rm
// CHECK-RV64-SAME: (<vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmadd.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
//
vfloat32mf2_t test_vfmadd_vf_f32mf2_rm(vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfmadd_vf_f32mf2_rm(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmadd_vv_f32m1_rm
// CHECK-RV64-SAME: (<vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmadd.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfmadd_vv_f32m1_rm(vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfmadd_vv_f32m1_rm(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmadd_vf_f32m1_rm
// CHECK-RV64-SAME: (<vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmadd.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfmadd_vf_f32m1_rm(vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfmadd_vf_f32m1_rm(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmadd_vv_f32m2_rm
// CHECK-RV64-SAME: (<vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmadd.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
//
vfloat32m2_t test_vfmadd_vv_f32m2_rm(vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfmadd_vv_f32m2_rm(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmadd_vf_f32m2_rm
// CHECK-RV64-SAME: (<vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmadd.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
//
vfloat32m2_t test_vfmadd_vf_f32m2_rm(vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfmadd_vf_f32m2_rm(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmadd_vv_f32m4_rm
// CHECK-RV64-SAME: (<vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmadd.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
//
vfloat32m4_t test_vfmadd_vv_f32m4_rm(vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfmadd_vv_f32m4_rm(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmadd_vf_f32m4_rm
// CHECK-RV64-SAME: (<vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmadd.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
//
vfloat32m4_t test_vfmadd_vf_f32m4_rm(vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfmadd_vf_f32m4_rm(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmadd_vv_f32m8_rm
// CHECK-RV64-SAME: (<vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmadd.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
//
vfloat32m8_t test_vfmadd_vv_f32m8_rm(vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfmadd_vv_f32m8_rm(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmadd_vf_f32m8_rm
// CHECK-RV64-SAME: (<vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmadd.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
//
vfloat32m8_t test_vfmadd_vf_f32m8_rm(vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfmadd_vf_f32m8_rm(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmadd_vv_f64m1_rm
// CHECK-RV64-SAME: (<vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmadd.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfmadd_vv_f64m1_rm(vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfmadd_vv_f64m1_rm(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmadd_vf_f64m1_rm
// CHECK-RV64-SAME: (<vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmadd.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfmadd_vf_f64m1_rm(vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfmadd_vf_f64m1_rm(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmadd_vv_f64m2_rm
// CHECK-RV64-SAME: (<vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmadd.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
//
vfloat64m2_t test_vfmadd_vv_f64m2_rm(vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfmadd_vv_f64m2_rm(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmadd_vf_f64m2_rm
// CHECK-RV64-SAME: (<vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmadd.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
//
vfloat64m2_t test_vfmadd_vf_f64m2_rm(vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfmadd_vf_f64m2_rm(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmadd_vv_f64m4_rm
// CHECK-RV64-SAME: (<vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmadd.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
//
vfloat64m4_t test_vfmadd_vv_f64m4_rm(vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfmadd_vv_f64m4_rm(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmadd_vf_f64m4_rm
// CHECK-RV64-SAME: (<vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmadd.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
//
vfloat64m4_t test_vfmadd_vf_f64m4_rm(vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfmadd_vf_f64m4_rm(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmadd_vv_f64m8_rm
// CHECK-RV64-SAME: (<vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmadd.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
//
vfloat64m8_t test_vfmadd_vv_f64m8_rm(vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfmadd_vv_f64m8_rm(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmadd_vf_f64m8_rm
// CHECK-RV64-SAME: (<vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmadd.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
//
vfloat64m8_t test_vfmadd_vf_f64m8_rm(vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfmadd_vf_f64m8_rm(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmadd_vv_f16mf4_rm_m
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmadd.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
//
vfloat16mf4_t test_vfmadd_vv_f16mf4_rm_m(vbool64_t mask, vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfmadd_vv_f16mf4_rm_m(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmadd_vf_f16mf4_rm_m
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmadd.mask.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
//
vfloat16mf4_t test_vfmadd_vf_f16mf4_rm_m(vbool64_t mask, vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfmadd_vf_f16mf4_rm_m(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmadd_vv_f16mf2_rm_m
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmadd.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
//
vfloat16mf2_t test_vfmadd_vv_f16mf2_rm_m(vbool32_t mask, vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfmadd_vv_f16mf2_rm_m(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmadd_vf_f16mf2_rm_m
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmadd.mask.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
//
vfloat16mf2_t test_vfmadd_vf_f16mf2_rm_m(vbool32_t mask, vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfmadd_vf_f16mf2_rm_m(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmadd_vv_f16m1_rm_m
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmadd.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfmadd_vv_f16m1_rm_m(vbool16_t mask, vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfmadd_vv_f16m1_rm_m(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmadd_vf_f16m1_rm_m
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmadd.mask.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfmadd_vf_f16m1_rm_m(vbool16_t mask, vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfmadd_vf_f16m1_rm_m(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmadd_vv_f16m2_rm_m
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmadd.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
//
vfloat16m2_t test_vfmadd_vv_f16m2_rm_m(vbool8_t mask, vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfmadd_vv_f16m2_rm_m(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmadd_vf_f16m2_rm_m
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmadd.mask.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
//
vfloat16m2_t test_vfmadd_vf_f16m2_rm_m(vbool8_t mask, vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfmadd_vf_f16m2_rm_m(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmadd_vv_f16m4_rm_m
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmadd.mask.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
//
vfloat16m4_t test_vfmadd_vv_f16m4_rm_m(vbool4_t mask, vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfmadd_vv_f16m4_rm_m(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmadd_vf_f16m4_rm_m
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmadd.mask.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
//
vfloat16m4_t test_vfmadd_vf_f16m4_rm_m(vbool4_t mask, vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfmadd_vf_f16m4_rm_m(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmadd_vv_f16m8_rm_m
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmadd.mask.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
//
vfloat16m8_t test_vfmadd_vv_f16m8_rm_m(vbool2_t mask, vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfmadd_vv_f16m8_rm_m(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmadd_vf_f16m8_rm_m
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmadd.mask.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
//
vfloat16m8_t test_vfmadd_vf_f16m8_rm_m(vbool2_t mask, vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfmadd_vf_f16m8_rm_m(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmadd_vv_f32mf2_rm_m
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmadd.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
//
vfloat32mf2_t test_vfmadd_vv_f32mf2_rm_m(vbool64_t mask, vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfmadd_vv_f32mf2_rm_m(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmadd_vf_f32mf2_rm_m
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmadd.mask.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
//
vfloat32mf2_t test_vfmadd_vf_f32mf2_rm_m(vbool64_t mask, vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfmadd_vf_f32mf2_rm_m(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmadd_vv_f32m1_rm_m
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmadd.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfmadd_vv_f32m1_rm_m(vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfmadd_vv_f32m1_rm_m(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmadd_vf_f32m1_rm_m
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmadd.mask.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfmadd_vf_f32m1_rm_m(vbool32_t mask, vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfmadd_vf_f32m1_rm_m(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmadd_vv_f32m2_rm_m
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmadd.mask.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
//
vfloat32m2_t test_vfmadd_vv_f32m2_rm_m(vbool16_t mask, vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfmadd_vv_f32m2_rm_m(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmadd_vf_f32m2_rm_m
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmadd.mask.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
//
vfloat32m2_t test_vfmadd_vf_f32m2_rm_m(vbool16_t mask, vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfmadd_vf_f32m2_rm_m(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmadd_vv_f32m4_rm_m
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmadd.mask.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
//
vfloat32m4_t test_vfmadd_vv_f32m4_rm_m(vbool8_t mask, vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfmadd_vv_f32m4_rm_m(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmadd_vf_f32m4_rm_m
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmadd.mask.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
//
vfloat32m4_t test_vfmadd_vf_f32m4_rm_m(vbool8_t mask, vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfmadd_vf_f32m4_rm_m(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmadd_vv_f32m8_rm_m
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmadd.mask.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
//
vfloat32m8_t test_vfmadd_vv_f32m8_rm_m(vbool4_t mask, vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfmadd_vv_f32m8_rm_m(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmadd_vf_f32m8_rm_m
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmadd.mask.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
//
vfloat32m8_t test_vfmadd_vf_f32m8_rm_m(vbool4_t mask, vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfmadd_vf_f32m8_rm_m(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmadd_vv_f64m1_rm_m
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmadd.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfmadd_vv_f64m1_rm_m(vbool64_t mask, vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfmadd_vv_f64m1_rm_m(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmadd_vf_f64m1_rm_m
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmadd.mask.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfmadd_vf_f64m1_rm_m(vbool64_t mask, vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfmadd_vf_f64m1_rm_m(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmadd_vv_f64m2_rm_m
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmadd.mask.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
//
vfloat64m2_t test_vfmadd_vv_f64m2_rm_m(vbool32_t mask, vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfmadd_vv_f64m2_rm_m(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmadd_vf_f64m2_rm_m
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmadd.mask.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
//
vfloat64m2_t test_vfmadd_vf_f64m2_rm_m(vbool32_t mask, vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfmadd_vf_f64m2_rm_m(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmadd_vv_f64m4_rm_m
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmadd.mask.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
//
vfloat64m4_t test_vfmadd_vv_f64m4_rm_m(vbool16_t mask, vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfmadd_vv_f64m4_rm_m(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmadd_vf_f64m4_rm_m
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmadd.mask.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
//
vfloat64m4_t test_vfmadd_vf_f64m4_rm_m(vbool16_t mask, vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfmadd_vf_f64m4_rm_m(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmadd_vv_f64m8_rm_m
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmadd.mask.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
//
vfloat64m8_t test_vfmadd_vv_f64m8_rm_m(vbool8_t mask, vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfmadd_vv_f64m8_rm_m(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmadd_vf_f64m8_rm_m
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmadd.mask.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
//
vfloat64m8_t test_vfmadd_vf_f64m8_rm_m(vbool8_t mask, vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfmadd_vf_f64m8_rm_m(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}

clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmsac.c

// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target // REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh \ // RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh \
// RUN: -target-feature +experimental-zvfh -disable-O0-optnone \ // RUN: -target-feature +experimental-zvfh -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ // RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s // RUN: FileCheck --check-prefix=CHECK-RV64 %s
#include <riscv_vector.h> #include <riscv_vector.h>
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmsac_vv_f16mf4 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmsac_vv_f16mf4
// CHECK-RV64-SAME: (<vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK-RV64-SAME: (<vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmsac.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmsac.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
// //
vfloat16mf4_t test_vfmsac_vv_f16mf4(vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) { vfloat16mf4_t test_vfmsac_vv_f16mf4(vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfmsac_vv_f16mf4(vd, vs1, vs2, vl); return __riscv_vfmsac_vv_f16mf4(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmsac_vf_f16mf4 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmsac_vf_f16mf4
// CHECK-RV64-SAME: (<vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmsac.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmsac.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
// //
vfloat16mf4_t test_vfmsac_vf_f16mf4(vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) { vfloat16mf4_t test_vfmsac_vf_f16mf4(vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfmsac_vf_f16mf4(vd, rs1, vs2, vl); return __riscv_vfmsac_vf_f16mf4(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmsac_vv_f16mf2 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmsac_vv_f16mf2
// CHECK-RV64-SAME: (<vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmsac.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmsac.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
// //
vfloat16mf2_t test_vfmsac_vv_f16mf2(vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) { vfloat16mf2_t test_vfmsac_vv_f16mf2(vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfmsac_vv_f16mf2(vd, vs1, vs2, vl); return __riscv_vfmsac_vv_f16mf2(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmsac_vf_f16mf2 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmsac_vf_f16mf2
// CHECK-RV64-SAME: (<vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmsac.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmsac.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
// //
vfloat16mf2_t test_vfmsac_vf_f16mf2(vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) { vfloat16mf2_t test_vfmsac_vf_f16mf2(vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfmsac_vf_f16mf2(vd, rs1, vs2, vl); return __riscv_vfmsac_vf_f16mf2(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmsac_vv_f16m1 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmsac_vv_f16m1
// CHECK-RV64-SAME: (<vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmsac.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmsac.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
// //
vfloat16m1_t test_vfmsac_vv_f16m1(vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) { vfloat16m1_t test_vfmsac_vv_f16m1(vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfmsac_vv_f16m1(vd, vs1, vs2, vl); return __riscv_vfmsac_vv_f16m1(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmsac_vf_f16m1 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmsac_vf_f16m1
// CHECK-RV64-SAME: (<vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmsac.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmsac.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
// //
vfloat16m1_t test_vfmsac_vf_f16m1(vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) { vfloat16m1_t test_vfmsac_vf_f16m1(vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfmsac_vf_f16m1(vd, rs1, vs2, vl); return __riscv_vfmsac_vf_f16m1(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmsac_vv_f16m2 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmsac_vv_f16m2
// CHECK-RV64-SAME: (<vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmsac.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmsac.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
// //
vfloat16m2_t test_vfmsac_vv_f16m2(vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) { vfloat16m2_t test_vfmsac_vv_f16m2(vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfmsac_vv_f16m2(vd, vs1, vs2, vl); return __riscv_vfmsac_vv_f16m2(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmsac_vf_f16m2 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmsac_vf_f16m2
// CHECK-RV64-SAME: (<vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmsac.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmsac.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
// //
vfloat16m2_t test_vfmsac_vf_f16m2(vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) { vfloat16m2_t test_vfmsac_vf_f16m2(vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfmsac_vf_f16m2(vd, rs1, vs2, vl); return __riscv_vfmsac_vf_f16m2(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmsac_vv_f16m4 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmsac_vv_f16m4
// CHECK-RV64-SAME: (<vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmsac.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmsac.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
// //
vfloat16m4_t test_vfmsac_vv_f16m4(vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) { vfloat16m4_t test_vfmsac_vv_f16m4(vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfmsac_vv_f16m4(vd, vs1, vs2, vl); return __riscv_vfmsac_vv_f16m4(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmsac_vf_f16m4 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmsac_vf_f16m4
// CHECK-RV64-SAME: (<vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmsac.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmsac.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
// //
vfloat16m4_t test_vfmsac_vf_f16m4(vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) { vfloat16m4_t test_vfmsac_vf_f16m4(vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfmsac_vf_f16m4(vd, rs1, vs2, vl); return __riscv_vfmsac_vf_f16m4(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmsac_vv_f16m8 // CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmsac_vv_f16m8
// CHECK-RV64-SAME: (<vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmsac.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmsac.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
// //
vfloat16m8_t test_vfmsac_vv_f16m8(vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) { vfloat16m8_t test_vfmsac_vv_f16m8(vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfmsac_vv_f16m8(vd, vs1, vs2, vl); return __riscv_vfmsac_vv_f16m8(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmsac_vf_f16m8 // CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmsac_vf_f16m8
// CHECK-RV64-SAME: (<vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmsac.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmsac.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
// //
vfloat16m8_t test_vfmsac_vf_f16m8(vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) { vfloat16m8_t test_vfmsac_vf_f16m8(vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfmsac_vf_f16m8(vd, rs1, vs2, vl); return __riscv_vfmsac_vf_f16m8(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmsac_vv_f32mf2 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmsac_vv_f32mf2
// CHECK-RV64-SAME: (<vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmsac.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmsac.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfmsac_vv_f32mf2(vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) { vfloat32mf2_t test_vfmsac_vv_f32mf2(vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfmsac_vv_f32mf2(vd, vs1, vs2, vl); return __riscv_vfmsac_vv_f32mf2(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmsac_vf_f32mf2 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmsac_vf_f32mf2
// CHECK-RV64-SAME: (<vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmsac.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmsac.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfmsac_vf_f32mf2(vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) { vfloat32mf2_t test_vfmsac_vf_f32mf2(vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfmsac_vf_f32mf2(vd, rs1, vs2, vl); return __riscv_vfmsac_vf_f32mf2(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmsac_vv_f32m1 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmsac_vv_f32m1
// CHECK-RV64-SAME: (<vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmsac.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmsac.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfmsac_vv_f32m1(vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) { vfloat32m1_t test_vfmsac_vv_f32m1(vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfmsac_vv_f32m1(vd, vs1, vs2, vl); return __riscv_vfmsac_vv_f32m1(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmsac_vf_f32m1 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmsac_vf_f32m1
// CHECK-RV64-SAME: (<vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmsac.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmsac.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfmsac_vf_f32m1(vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) { vfloat32m1_t test_vfmsac_vf_f32m1(vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfmsac_vf_f32m1(vd, rs1, vs2, vl); return __riscv_vfmsac_vf_f32m1(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmsac_vv_f32m2 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmsac_vv_f32m2
// CHECK-RV64-SAME: (<vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmsac.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmsac.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfmsac_vv_f32m2(vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) { vfloat32m2_t test_vfmsac_vv_f32m2(vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfmsac_vv_f32m2(vd, vs1, vs2, vl); return __riscv_vfmsac_vv_f32m2(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmsac_vf_f32m2 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmsac_vf_f32m2
// CHECK-RV64-SAME: (<vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmsac.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmsac.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfmsac_vf_f32m2(vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) { vfloat32m2_t test_vfmsac_vf_f32m2(vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfmsac_vf_f32m2(vd, rs1, vs2, vl); return __riscv_vfmsac_vf_f32m2(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmsac_vv_f32m4 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmsac_vv_f32m4
// CHECK-RV64-SAME: (<vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmsac.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmsac.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfmsac_vv_f32m4(vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) { vfloat32m4_t test_vfmsac_vv_f32m4(vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfmsac_vv_f32m4(vd, vs1, vs2, vl); return __riscv_vfmsac_vv_f32m4(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmsac_vf_f32m4 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmsac_vf_f32m4
// CHECK-RV64-SAME: (<vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmsac.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmsac.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfmsac_vf_f32m4(vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) { vfloat32m4_t test_vfmsac_vf_f32m4(vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfmsac_vf_f32m4(vd, rs1, vs2, vl); return __riscv_vfmsac_vf_f32m4(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmsac_vv_f32m8 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmsac_vv_f32m8
// CHECK-RV64-SAME: (<vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmsac.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmsac.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfmsac_vv_f32m8(vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) { vfloat32m8_t test_vfmsac_vv_f32m8(vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfmsac_vv_f32m8(vd, vs1, vs2, vl); return __riscv_vfmsac_vv_f32m8(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmsac_vf_f32m8 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmsac_vf_f32m8
// CHECK-RV64-SAME: (<vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmsac.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmsac.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfmsac_vf_f32m8(vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) { vfloat32m8_t test_vfmsac_vf_f32m8(vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfmsac_vf_f32m8(vd, rs1, vs2, vl); return __riscv_vfmsac_vf_f32m8(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmsac_vv_f64m1 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmsac_vv_f64m1
// CHECK-RV64-SAME: (<vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmsac.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmsac.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfmsac_vv_f64m1(vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) { vfloat64m1_t test_vfmsac_vv_f64m1(vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfmsac_vv_f64m1(vd, vs1, vs2, vl); return __riscv_vfmsac_vv_f64m1(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmsac_vf_f64m1 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmsac_vf_f64m1
// CHECK-RV64-SAME: (<vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmsac.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmsac.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfmsac_vf_f64m1(vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) { vfloat64m1_t test_vfmsac_vf_f64m1(vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfmsac_vf_f64m1(vd, rs1, vs2, vl); return __riscv_vfmsac_vf_f64m1(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmsac_vv_f64m2 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmsac_vv_f64m2
// CHECK-RV64-SAME: (<vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmsac.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmsac.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfmsac_vv_f64m2(vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) { vfloat64m2_t test_vfmsac_vv_f64m2(vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfmsac_vv_f64m2(vd, vs1, vs2, vl); return __riscv_vfmsac_vv_f64m2(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmsac_vf_f64m2 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmsac_vf_f64m2
// CHECK-RV64-SAME: (<vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmsac.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmsac.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfmsac_vf_f64m2(vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) { vfloat64m2_t test_vfmsac_vf_f64m2(vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfmsac_vf_f64m2(vd, rs1, vs2, vl); return __riscv_vfmsac_vf_f64m2(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmsac_vv_f64m4 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmsac_vv_f64m4
// CHECK-RV64-SAME: (<vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmsac.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmsac.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfmsac_vv_f64m4(vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) { vfloat64m4_t test_vfmsac_vv_f64m4(vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfmsac_vv_f64m4(vd, vs1, vs2, vl); return __riscv_vfmsac_vv_f64m4(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmsac_vf_f64m4 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmsac_vf_f64m4
// CHECK-RV64-SAME: (<vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmsac.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmsac.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfmsac_vf_f64m4(vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) { vfloat64m4_t test_vfmsac_vf_f64m4(vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfmsac_vf_f64m4(vd, rs1, vs2, vl); return __riscv_vfmsac_vf_f64m4(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmsac_vv_f64m8 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmsac_vv_f64m8
// CHECK-RV64-SAME: (<vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmsac.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmsac.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfmsac_vv_f64m8(vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) { vfloat64m8_t test_vfmsac_vv_f64m8(vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfmsac_vv_f64m8(vd, vs1, vs2, vl); return __riscv_vfmsac_vv_f64m8(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmsac_vf_f64m8 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmsac_vf_f64m8
// CHECK-RV64-SAME: (<vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmsac.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmsac.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfmsac_vf_f64m8(vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) { vfloat64m8_t test_vfmsac_vf_f64m8(vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfmsac_vf_f64m8(vd, rs1, vs2, vl); return __riscv_vfmsac_vf_f64m8(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmsac_vv_f16mf4_m // CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmsac_vv_f16mf4_m
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmsac.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmsac.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
// //
vfloat16mf4_t test_vfmsac_vv_f16mf4_m(vbool64_t mask, vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) { vfloat16mf4_t test_vfmsac_vv_f16mf4_m(vbool64_t mask, vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfmsac_vv_f16mf4_m(mask, vd, vs1, vs2, vl); return __riscv_vfmsac_vv_f16mf4_m(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmsac_vf_f16mf4_m // CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmsac_vf_f16mf4_m
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmsac.mask.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmsac.mask.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
// //
vfloat16mf4_t test_vfmsac_vf_f16mf4_m(vbool64_t mask, vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) { vfloat16mf4_t test_vfmsac_vf_f16mf4_m(vbool64_t mask, vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfmsac_vf_f16mf4_m(mask, vd, rs1, vs2, vl); return __riscv_vfmsac_vf_f16mf4_m(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmsac_vv_f16mf2_m // CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmsac_vv_f16mf2_m
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmsac.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmsac.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
// //
vfloat16mf2_t test_vfmsac_vv_f16mf2_m(vbool32_t mask, vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) { vfloat16mf2_t test_vfmsac_vv_f16mf2_m(vbool32_t mask, vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfmsac_vv_f16mf2_m(mask, vd, vs1, vs2, vl); return __riscv_vfmsac_vv_f16mf2_m(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmsac_vf_f16mf2_m // CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmsac_vf_f16mf2_m
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmsac.mask.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmsac.mask.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
// //
vfloat16mf2_t test_vfmsac_vf_f16mf2_m(vbool32_t mask, vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) { vfloat16mf2_t test_vfmsac_vf_f16mf2_m(vbool32_t mask, vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfmsac_vf_f16mf2_m(mask, vd, rs1, vs2, vl); return __riscv_vfmsac_vf_f16mf2_m(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmsac_vv_f16m1_m // CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmsac_vv_f16m1_m
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmsac.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmsac.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
// //
vfloat16m1_t test_vfmsac_vv_f16m1_m(vbool16_t mask, vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) { vfloat16m1_t test_vfmsac_vv_f16m1_m(vbool16_t mask, vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfmsac_vv_f16m1_m(mask, vd, vs1, vs2, vl); return __riscv_vfmsac_vv_f16m1_m(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmsac_vf_f16m1_m // CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmsac_vf_f16m1_m
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmsac.mask.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmsac.mask.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
// //
vfloat16m1_t test_vfmsac_vf_f16m1_m(vbool16_t mask, vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) { vfloat16m1_t test_vfmsac_vf_f16m1_m(vbool16_t mask, vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfmsac_vf_f16m1_m(mask, vd, rs1, vs2, vl); return __riscv_vfmsac_vf_f16m1_m(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmsac_vv_f16m2_m // CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmsac_vv_f16m2_m
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmsac.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmsac.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
// //
vfloat16m2_t test_vfmsac_vv_f16m2_m(vbool8_t mask, vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) { vfloat16m2_t test_vfmsac_vv_f16m2_m(vbool8_t mask, vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfmsac_vv_f16m2_m(mask, vd, vs1, vs2, vl); return __riscv_vfmsac_vv_f16m2_m(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmsac_vf_f16m2_m // CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmsac_vf_f16m2_m
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmsac.mask.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmsac.mask.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
// //
vfloat16m2_t test_vfmsac_vf_f16m2_m(vbool8_t mask, vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) { vfloat16m2_t test_vfmsac_vf_f16m2_m(vbool8_t mask, vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfmsac_vf_f16m2_m(mask, vd, rs1, vs2, vl); return __riscv_vfmsac_vf_f16m2_m(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmsac_vv_f16m4_m // CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmsac_vv_f16m4_m
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmsac.mask.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmsac.mask.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
// //
vfloat16m4_t test_vfmsac_vv_f16m4_m(vbool4_t mask, vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) { vfloat16m4_t test_vfmsac_vv_f16m4_m(vbool4_t mask, vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfmsac_vv_f16m4_m(mask, vd, vs1, vs2, vl); return __riscv_vfmsac_vv_f16m4_m(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmsac_vf_f16m4_m // CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmsac_vf_f16m4_m
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmsac.mask.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmsac.mask.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
// //
vfloat16m4_t test_vfmsac_vf_f16m4_m(vbool4_t mask, vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) { vfloat16m4_t test_vfmsac_vf_f16m4_m(vbool4_t mask, vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfmsac_vf_f16m4_m(mask, vd, rs1, vs2, vl); return __riscv_vfmsac_vf_f16m4_m(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmsac_vv_f16m8_m // CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmsac_vv_f16m8_m
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmsac.mask.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmsac.mask.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
// //
vfloat16m8_t test_vfmsac_vv_f16m8_m(vbool2_t mask, vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) { vfloat16m8_t test_vfmsac_vv_f16m8_m(vbool2_t mask, vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfmsac_vv_f16m8_m(mask, vd, vs1, vs2, vl); return __riscv_vfmsac_vv_f16m8_m(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmsac_vf_f16m8_m // CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmsac_vf_f16m8_m
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmsac.mask.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmsac.mask.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
// //
vfloat16m8_t test_vfmsac_vf_f16m8_m(vbool2_t mask, vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) { vfloat16m8_t test_vfmsac_vf_f16m8_m(vbool2_t mask, vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfmsac_vf_f16m8_m(mask, vd, rs1, vs2, vl); return __riscv_vfmsac_vf_f16m8_m(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmsac_vv_f32mf2_m // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmsac_vv_f32mf2_m
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmsac.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmsac.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfmsac_vv_f32mf2_m(vbool64_t mask, vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) { vfloat32mf2_t test_vfmsac_vv_f32mf2_m(vbool64_t mask, vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfmsac_vv_f32mf2_m(mask, vd, vs1, vs2, vl); return __riscv_vfmsac_vv_f32mf2_m(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmsac_vf_f32mf2_m // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmsac_vf_f32mf2_m
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmsac.mask.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmsac.mask.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfmsac_vf_f32mf2_m(vbool64_t mask, vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) { vfloat32mf2_t test_vfmsac_vf_f32mf2_m(vbool64_t mask, vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfmsac_vf_f32mf2_m(mask, vd, rs1, vs2, vl); return __riscv_vfmsac_vf_f32mf2_m(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmsac_vv_f32m1_m // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmsac_vv_f32m1_m
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmsac.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmsac.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfmsac_vv_f32m1_m(vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) { vfloat32m1_t test_vfmsac_vv_f32m1_m(vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfmsac_vv_f32m1_m(mask, vd, vs1, vs2, vl); return __riscv_vfmsac_vv_f32m1_m(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmsac_vf_f32m1_m // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmsac_vf_f32m1_m
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmsac.mask.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmsac.mask.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfmsac_vf_f32m1_m(vbool32_t mask, vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) { vfloat32m1_t test_vfmsac_vf_f32m1_m(vbool32_t mask, vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfmsac_vf_f32m1_m(mask, vd, rs1, vs2, vl); return __riscv_vfmsac_vf_f32m1_m(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmsac_vv_f32m2_m // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmsac_vv_f32m2_m
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmsac.mask.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmsac.mask.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfmsac_vv_f32m2_m(vbool16_t mask, vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) { vfloat32m2_t test_vfmsac_vv_f32m2_m(vbool16_t mask, vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfmsac_vv_f32m2_m(mask, vd, vs1, vs2, vl); return __riscv_vfmsac_vv_f32m2_m(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmsac_vf_f32m2_m // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmsac_vf_f32m2_m
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmsac.mask.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmsac.mask.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfmsac_vf_f32m2_m(vbool16_t mask, vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) { vfloat32m2_t test_vfmsac_vf_f32m2_m(vbool16_t mask, vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfmsac_vf_f32m2_m(mask, vd, rs1, vs2, vl); return __riscv_vfmsac_vf_f32m2_m(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmsac_vv_f32m4_m // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmsac_vv_f32m4_m
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmsac.mask.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmsac.mask.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfmsac_vv_f32m4_m(vbool8_t mask, vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) { vfloat32m4_t test_vfmsac_vv_f32m4_m(vbool8_t mask, vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfmsac_vv_f32m4_m(mask, vd, vs1, vs2, vl); return __riscv_vfmsac_vv_f32m4_m(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmsac_vf_f32m4_m // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmsac_vf_f32m4_m
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmsac.mask.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmsac.mask.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfmsac_vf_f32m4_m(vbool8_t mask, vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) { vfloat32m4_t test_vfmsac_vf_f32m4_m(vbool8_t mask, vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfmsac_vf_f32m4_m(mask, vd, rs1, vs2, vl); return __riscv_vfmsac_vf_f32m4_m(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmsac_vv_f32m8_m // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmsac_vv_f32m8_m
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmsac.mask.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmsac.mask.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfmsac_vv_f32m8_m(vbool4_t mask, vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) { vfloat32m8_t test_vfmsac_vv_f32m8_m(vbool4_t mask, vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfmsac_vv_f32m8_m(mask, vd, vs1, vs2, vl); return __riscv_vfmsac_vv_f32m8_m(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmsac_vf_f32m8_m // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmsac_vf_f32m8_m
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmsac.mask.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmsac.mask.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfmsac_vf_f32m8_m(vbool4_t mask, vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) { vfloat32m8_t test_vfmsac_vf_f32m8_m(vbool4_t mask, vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfmsac_vf_f32m8_m(mask, vd, rs1, vs2, vl); return __riscv_vfmsac_vf_f32m8_m(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmsac_vv_f64m1_m // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmsac_vv_f64m1_m
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmsac.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmsac.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfmsac_vv_f64m1_m(vbool64_t mask, vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) { vfloat64m1_t test_vfmsac_vv_f64m1_m(vbool64_t mask, vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfmsac_vv_f64m1_m(mask, vd, vs1, vs2, vl); return __riscv_vfmsac_vv_f64m1_m(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmsac_vf_f64m1_m // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmsac_vf_f64m1_m
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmsac.mask.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmsac.mask.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfmsac_vf_f64m1_m(vbool64_t mask, vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) { vfloat64m1_t test_vfmsac_vf_f64m1_m(vbool64_t mask, vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfmsac_vf_f64m1_m(mask, vd, rs1, vs2, vl); return __riscv_vfmsac_vf_f64m1_m(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmsac_vv_f64m2_m // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmsac_vv_f64m2_m
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmsac.mask.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmsac.mask.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfmsac_vv_f64m2_m(vbool32_t mask, vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) { vfloat64m2_t test_vfmsac_vv_f64m2_m(vbool32_t mask, vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfmsac_vv_f64m2_m(mask, vd, vs1, vs2, vl); return __riscv_vfmsac_vv_f64m2_m(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmsac_vf_f64m2_m // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmsac_vf_f64m2_m
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmsac.mask.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmsac.mask.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfmsac_vf_f64m2_m(vbool32_t mask, vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) { vfloat64m2_t test_vfmsac_vf_f64m2_m(vbool32_t mask, vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfmsac_vf_f64m2_m(mask, vd, rs1, vs2, vl); return __riscv_vfmsac_vf_f64m2_m(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmsac_vv_f64m4_m // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmsac_vv_f64m4_m
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmsac.mask.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmsac.mask.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfmsac_vv_f64m4_m(vbool16_t mask, vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) { vfloat64m4_t test_vfmsac_vv_f64m4_m(vbool16_t mask, vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfmsac_vv_f64m4_m(mask, vd, vs1, vs2, vl); return __riscv_vfmsac_vv_f64m4_m(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmsac_vf_f64m4_m // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmsac_vf_f64m4_m
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmsac.mask.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmsac.mask.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfmsac_vf_f64m4_m(vbool16_t mask, vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) { vfloat64m4_t test_vfmsac_vf_f64m4_m(vbool16_t mask, vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfmsac_vf_f64m4_m(mask, vd, rs1, vs2, vl); return __riscv_vfmsac_vf_f64m4_m(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmsac_vv_f64m8_m // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmsac_vv_f64m8_m
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmsac.mask.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmsac.mask.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfmsac_vv_f64m8_m(vbool8_t mask, vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) { vfloat64m8_t test_vfmsac_vv_f64m8_m(vbool8_t mask, vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfmsac_vv_f64m8_m(mask, vd, vs1, vs2, vl); return __riscv_vfmsac_vv_f64m8_m(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmsac_vf_f64m8_m // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmsac_vf_f64m8_m
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmsac.mask.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmsac.mask.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfmsac_vf_f64m8_m(vbool8_t mask, vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) { vfloat64m8_t test_vfmsac_vf_f64m8_m(vbool8_t mask, vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfmsac_vf_f64m8_m(mask, vd, rs1, vs2, vl); return __riscv_vfmsac_vf_f64m8_m(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmsac_vv_f16mf4_rm
// CHECK-RV64-SAME: (<vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmsac.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
//
vfloat16mf4_t test_vfmsac_vv_f16mf4_rm(vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfmsac_vv_f16mf4_rm(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmsac_vf_f16mf4_rm
// CHECK-RV64-SAME: (<vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmsac.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
//
vfloat16mf4_t test_vfmsac_vf_f16mf4_rm(vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfmsac_vf_f16mf4_rm(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmsac_vv_f16mf2_rm
// CHECK-RV64-SAME: (<vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmsac.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
//
vfloat16mf2_t test_vfmsac_vv_f16mf2_rm(vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfmsac_vv_f16mf2_rm(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmsac_vf_f16mf2_rm
// CHECK-RV64-SAME: (<vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmsac.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
//
vfloat16mf2_t test_vfmsac_vf_f16mf2_rm(vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfmsac_vf_f16mf2_rm(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmsac_vv_f16m1_rm
// CHECK-RV64-SAME: (<vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmsac.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfmsac_vv_f16m1_rm(vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfmsac_vv_f16m1_rm(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmsac_vf_f16m1_rm
// CHECK-RV64-SAME: (<vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmsac.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfmsac_vf_f16m1_rm(vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfmsac_vf_f16m1_rm(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmsac_vv_f16m2_rm
// CHECK-RV64-SAME: (<vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmsac.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
//
vfloat16m2_t test_vfmsac_vv_f16m2_rm(vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfmsac_vv_f16m2_rm(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmsac_vf_f16m2_rm
// CHECK-RV64-SAME: (<vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmsac.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
//
vfloat16m2_t test_vfmsac_vf_f16m2_rm(vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfmsac_vf_f16m2_rm(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmsac_vv_f16m4_rm
// CHECK-RV64-SAME: (<vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmsac.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
//
vfloat16m4_t test_vfmsac_vv_f16m4_rm(vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfmsac_vv_f16m4_rm(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmsac_vf_f16m4_rm
// CHECK-RV64-SAME: (<vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmsac.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
//
vfloat16m4_t test_vfmsac_vf_f16m4_rm(vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfmsac_vf_f16m4_rm(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmsac_vv_f16m8_rm
// CHECK-RV64-SAME: (<vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmsac.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
//
vfloat16m8_t test_vfmsac_vv_f16m8_rm(vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfmsac_vv_f16m8_rm(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmsac_vf_f16m8_rm
// CHECK-RV64-SAME: (<vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmsac.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
//
vfloat16m8_t test_vfmsac_vf_f16m8_rm(vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfmsac_vf_f16m8_rm(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmsac_vv_f32mf2_rm
// CHECK-RV64-SAME: (<vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmsac.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
//
vfloat32mf2_t test_vfmsac_vv_f32mf2_rm(vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfmsac_vv_f32mf2_rm(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmsac_vf_f32mf2_rm
// CHECK-RV64-SAME: (<vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmsac.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
//
vfloat32mf2_t test_vfmsac_vf_f32mf2_rm(vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfmsac_vf_f32mf2_rm(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmsac_vv_f32m1_rm
// CHECK-RV64-SAME: (<vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmsac.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfmsac_vv_f32m1_rm(vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfmsac_vv_f32m1_rm(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmsac_vf_f32m1_rm
// CHECK-RV64-SAME: (<vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmsac.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfmsac_vf_f32m1_rm(vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfmsac_vf_f32m1_rm(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmsac_vv_f32m2_rm
// CHECK-RV64-SAME: (<vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmsac.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
//
vfloat32m2_t test_vfmsac_vv_f32m2_rm(vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfmsac_vv_f32m2_rm(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmsac_vf_f32m2_rm
// CHECK-RV64-SAME: (<vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmsac.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
//
vfloat32m2_t test_vfmsac_vf_f32m2_rm(vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfmsac_vf_f32m2_rm(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmsac_vv_f32m4_rm
// CHECK-RV64-SAME: (<vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmsac.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
//
vfloat32m4_t test_vfmsac_vv_f32m4_rm(vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfmsac_vv_f32m4_rm(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmsac_vf_f32m4_rm
// CHECK-RV64-SAME: (<vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmsac.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
//
vfloat32m4_t test_vfmsac_vf_f32m4_rm(vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfmsac_vf_f32m4_rm(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmsac_vv_f32m8_rm
// CHECK-RV64-SAME: (<vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmsac.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
//
vfloat32m8_t test_vfmsac_vv_f32m8_rm(vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfmsac_vv_f32m8_rm(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmsac_vf_f32m8_rm
// CHECK-RV64-SAME: (<vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmsac.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
//
vfloat32m8_t test_vfmsac_vf_f32m8_rm(vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfmsac_vf_f32m8_rm(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmsac_vv_f64m1_rm
// CHECK-RV64-SAME: (<vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmsac.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfmsac_vv_f64m1_rm(vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfmsac_vv_f64m1_rm(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmsac_vf_f64m1_rm
// CHECK-RV64-SAME: (<vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmsac.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfmsac_vf_f64m1_rm(vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfmsac_vf_f64m1_rm(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmsac_vv_f64m2_rm
// CHECK-RV64-SAME: (<vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmsac.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
//
vfloat64m2_t test_vfmsac_vv_f64m2_rm(vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfmsac_vv_f64m2_rm(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmsac_vf_f64m2_rm
// CHECK-RV64-SAME: (<vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmsac.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
//
vfloat64m2_t test_vfmsac_vf_f64m2_rm(vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfmsac_vf_f64m2_rm(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmsac_vv_f64m4_rm
// CHECK-RV64-SAME: (<vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmsac.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
//
vfloat64m4_t test_vfmsac_vv_f64m4_rm(vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfmsac_vv_f64m4_rm(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmsac_vf_f64m4_rm
// CHECK-RV64-SAME: (<vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmsac.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
//
vfloat64m4_t test_vfmsac_vf_f64m4_rm(vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfmsac_vf_f64m4_rm(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmsac_vv_f64m8_rm
// CHECK-RV64-SAME: (<vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmsac.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
//
vfloat64m8_t test_vfmsac_vv_f64m8_rm(vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfmsac_vv_f64m8_rm(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmsac_vf_f64m8_rm
// CHECK-RV64-SAME: (<vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmsac.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
//
vfloat64m8_t test_vfmsac_vf_f64m8_rm(vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfmsac_vf_f64m8_rm(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmsac_vv_f16mf4_rm_m
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmsac.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
//
vfloat16mf4_t test_vfmsac_vv_f16mf4_rm_m(vbool64_t mask, vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfmsac_vv_f16mf4_rm_m(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmsac_vf_f16mf4_rm_m
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmsac.mask.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
//
vfloat16mf4_t test_vfmsac_vf_f16mf4_rm_m(vbool64_t mask, vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfmsac_vf_f16mf4_rm_m(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmsac_vv_f16mf2_rm_m
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmsac.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
//
vfloat16mf2_t test_vfmsac_vv_f16mf2_rm_m(vbool32_t mask, vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfmsac_vv_f16mf2_rm_m(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmsac_vf_f16mf2_rm_m
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmsac.mask.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
//
vfloat16mf2_t test_vfmsac_vf_f16mf2_rm_m(vbool32_t mask, vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfmsac_vf_f16mf2_rm_m(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmsac_vv_f16m1_rm_m
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmsac.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfmsac_vv_f16m1_rm_m(vbool16_t mask, vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfmsac_vv_f16m1_rm_m(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmsac_vf_f16m1_rm_m
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmsac.mask.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfmsac_vf_f16m1_rm_m(vbool16_t mask, vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfmsac_vf_f16m1_rm_m(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmsac_vv_f16m2_rm_m
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmsac.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
//
vfloat16m2_t test_vfmsac_vv_f16m2_rm_m(vbool8_t mask, vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfmsac_vv_f16m2_rm_m(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmsac_vf_f16m2_rm_m
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmsac.mask.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
//
vfloat16m2_t test_vfmsac_vf_f16m2_rm_m(vbool8_t mask, vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfmsac_vf_f16m2_rm_m(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmsac_vv_f16m4_rm_m
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmsac.mask.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
//
vfloat16m4_t test_vfmsac_vv_f16m4_rm_m(vbool4_t mask, vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfmsac_vv_f16m4_rm_m(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmsac_vf_f16m4_rm_m
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmsac.mask.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
//
vfloat16m4_t test_vfmsac_vf_f16m4_rm_m(vbool4_t mask, vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfmsac_vf_f16m4_rm_m(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmsac_vv_f16m8_rm_m
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmsac.mask.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
//
vfloat16m8_t test_vfmsac_vv_f16m8_rm_m(vbool2_t mask, vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfmsac_vv_f16m8_rm_m(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmsac_vf_f16m8_rm_m
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmsac.mask.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
//
vfloat16m8_t test_vfmsac_vf_f16m8_rm_m(vbool2_t mask, vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfmsac_vf_f16m8_rm_m(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmsac_vv_f32mf2_rm_m
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmsac.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
//
vfloat32mf2_t test_vfmsac_vv_f32mf2_rm_m(vbool64_t mask, vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfmsac_vv_f32mf2_rm_m(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmsac_vf_f32mf2_rm_m
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmsac.mask.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
//
vfloat32mf2_t test_vfmsac_vf_f32mf2_rm_m(vbool64_t mask, vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfmsac_vf_f32mf2_rm_m(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmsac_vv_f32m1_rm_m
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmsac.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfmsac_vv_f32m1_rm_m(vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfmsac_vv_f32m1_rm_m(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmsac_vf_f32m1_rm_m
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmsac.mask.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfmsac_vf_f32m1_rm_m(vbool32_t mask, vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfmsac_vf_f32m1_rm_m(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmsac_vv_f32m2_rm_m
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmsac.mask.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
//
vfloat32m2_t test_vfmsac_vv_f32m2_rm_m(vbool16_t mask, vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfmsac_vv_f32m2_rm_m(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmsac_vf_f32m2_rm_m
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmsac.mask.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
//
vfloat32m2_t test_vfmsac_vf_f32m2_rm_m(vbool16_t mask, vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfmsac_vf_f32m2_rm_m(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmsac_vv_f32m4_rm_m
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmsac.mask.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
//
vfloat32m4_t test_vfmsac_vv_f32m4_rm_m(vbool8_t mask, vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfmsac_vv_f32m4_rm_m(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmsac_vf_f32m4_rm_m
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmsac.mask.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
//
vfloat32m4_t test_vfmsac_vf_f32m4_rm_m(vbool8_t mask, vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfmsac_vf_f32m4_rm_m(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmsac_vv_f32m8_rm_m
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmsac.mask.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
//
vfloat32m8_t test_vfmsac_vv_f32m8_rm_m(vbool4_t mask, vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfmsac_vv_f32m8_rm_m(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmsac_vf_f32m8_rm_m
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmsac.mask.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
//
vfloat32m8_t test_vfmsac_vf_f32m8_rm_m(vbool4_t mask, vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfmsac_vf_f32m8_rm_m(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmsac_vv_f64m1_rm_m
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmsac.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfmsac_vv_f64m1_rm_m(vbool64_t mask, vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfmsac_vv_f64m1_rm_m(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmsac_vf_f64m1_rm_m
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmsac.mask.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfmsac_vf_f64m1_rm_m(vbool64_t mask, vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfmsac_vf_f64m1_rm_m(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmsac_vv_f64m2_rm_m
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmsac.mask.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
//
vfloat64m2_t test_vfmsac_vv_f64m2_rm_m(vbool32_t mask, vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfmsac_vv_f64m2_rm_m(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmsac_vf_f64m2_rm_m
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmsac.mask.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
//
vfloat64m2_t test_vfmsac_vf_f64m2_rm_m(vbool32_t mask, vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfmsac_vf_f64m2_rm_m(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmsac_vv_f64m4_rm_m
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmsac.mask.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
//
vfloat64m4_t test_vfmsac_vv_f64m4_rm_m(vbool16_t mask, vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfmsac_vv_f64m4_rm_m(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmsac_vf_f64m4_rm_m
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmsac.mask.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
//
vfloat64m4_t test_vfmsac_vf_f64m4_rm_m(vbool16_t mask, vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfmsac_vf_f64m4_rm_m(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmsac_vv_f64m8_rm_m
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmsac.mask.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
//
vfloat64m8_t test_vfmsac_vv_f64m8_rm_m(vbool8_t mask, vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfmsac_vv_f64m8_rm_m(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmsac_vf_f64m8_rm_m
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmsac.mask.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
//
vfloat64m8_t test_vfmsac_vf_f64m8_rm_m(vbool8_t mask, vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfmsac_vf_f64m8_rm_m(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}

clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfmsub.c

// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target // REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh \ // RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh \
// RUN: -target-feature +experimental-zvfh -disable-O0-optnone \ // RUN: -target-feature +experimental-zvfh -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ // RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s // RUN: FileCheck --check-prefix=CHECK-RV64 %s
#include <riscv_vector.h> #include <riscv_vector.h>
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmsub_vv_f16mf4 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmsub_vv_f16mf4
// CHECK-RV64-SAME: (<vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK-RV64-SAME: (<vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmsub.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmsub.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
// //
vfloat16mf4_t test_vfmsub_vv_f16mf4(vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) { vfloat16mf4_t test_vfmsub_vv_f16mf4(vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfmsub_vv_f16mf4(vd, vs1, vs2, vl); return __riscv_vfmsub_vv_f16mf4(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmsub_vf_f16mf4 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmsub_vf_f16mf4
// CHECK-RV64-SAME: (<vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmsub.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmsub.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
// //
vfloat16mf4_t test_vfmsub_vf_f16mf4(vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) { vfloat16mf4_t test_vfmsub_vf_f16mf4(vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfmsub_vf_f16mf4(vd, rs1, vs2, vl); return __riscv_vfmsub_vf_f16mf4(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmsub_vv_f16mf2 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmsub_vv_f16mf2
// CHECK-RV64-SAME: (<vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmsub.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmsub.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
// //
vfloat16mf2_t test_vfmsub_vv_f16mf2(vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) { vfloat16mf2_t test_vfmsub_vv_f16mf2(vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfmsub_vv_f16mf2(vd, vs1, vs2, vl); return __riscv_vfmsub_vv_f16mf2(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmsub_vf_f16mf2 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmsub_vf_f16mf2
// CHECK-RV64-SAME: (<vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmsub.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmsub.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
// //
vfloat16mf2_t test_vfmsub_vf_f16mf2(vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) { vfloat16mf2_t test_vfmsub_vf_f16mf2(vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfmsub_vf_f16mf2(vd, rs1, vs2, vl); return __riscv_vfmsub_vf_f16mf2(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmsub_vv_f16m1 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmsub_vv_f16m1
// CHECK-RV64-SAME: (<vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmsub.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmsub.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
// //
vfloat16m1_t test_vfmsub_vv_f16m1(vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) { vfloat16m1_t test_vfmsub_vv_f16m1(vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfmsub_vv_f16m1(vd, vs1, vs2, vl); return __riscv_vfmsub_vv_f16m1(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmsub_vf_f16m1 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmsub_vf_f16m1
// CHECK-RV64-SAME: (<vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmsub.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmsub.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
// //
vfloat16m1_t test_vfmsub_vf_f16m1(vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) { vfloat16m1_t test_vfmsub_vf_f16m1(vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfmsub_vf_f16m1(vd, rs1, vs2, vl); return __riscv_vfmsub_vf_f16m1(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmsub_vv_f16m2 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmsub_vv_f16m2
// CHECK-RV64-SAME: (<vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmsub.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmsub.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
// //
vfloat16m2_t test_vfmsub_vv_f16m2(vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) { vfloat16m2_t test_vfmsub_vv_f16m2(vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfmsub_vv_f16m2(vd, vs1, vs2, vl); return __riscv_vfmsub_vv_f16m2(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmsub_vf_f16m2 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmsub_vf_f16m2
// CHECK-RV64-SAME: (<vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmsub.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmsub.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
// //
vfloat16m2_t test_vfmsub_vf_f16m2(vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) { vfloat16m2_t test_vfmsub_vf_f16m2(vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfmsub_vf_f16m2(vd, rs1, vs2, vl); return __riscv_vfmsub_vf_f16m2(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmsub_vv_f16m4 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmsub_vv_f16m4
// CHECK-RV64-SAME: (<vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmsub.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmsub.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
// //
vfloat16m4_t test_vfmsub_vv_f16m4(vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) { vfloat16m4_t test_vfmsub_vv_f16m4(vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfmsub_vv_f16m4(vd, vs1, vs2, vl); return __riscv_vfmsub_vv_f16m4(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmsub_vf_f16m4 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmsub_vf_f16m4
// CHECK-RV64-SAME: (<vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmsub.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmsub.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
// //
vfloat16m4_t test_vfmsub_vf_f16m4(vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) { vfloat16m4_t test_vfmsub_vf_f16m4(vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfmsub_vf_f16m4(vd, rs1, vs2, vl); return __riscv_vfmsub_vf_f16m4(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmsub_vv_f16m8 // CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmsub_vv_f16m8
// CHECK-RV64-SAME: (<vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmsub.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmsub.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
// //
vfloat16m8_t test_vfmsub_vv_f16m8(vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) { vfloat16m8_t test_vfmsub_vv_f16m8(vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfmsub_vv_f16m8(vd, vs1, vs2, vl); return __riscv_vfmsub_vv_f16m8(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmsub_vf_f16m8 // CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmsub_vf_f16m8
// CHECK-RV64-SAME: (<vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmsub.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmsub.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
// //
vfloat16m8_t test_vfmsub_vf_f16m8(vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) { vfloat16m8_t test_vfmsub_vf_f16m8(vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfmsub_vf_f16m8(vd, rs1, vs2, vl); return __riscv_vfmsub_vf_f16m8(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmsub_vv_f32mf2 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmsub_vv_f32mf2
// CHECK-RV64-SAME: (<vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmsub.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmsub.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfmsub_vv_f32mf2(vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) { vfloat32mf2_t test_vfmsub_vv_f32mf2(vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfmsub_vv_f32mf2(vd, vs1, vs2, vl); return __riscv_vfmsub_vv_f32mf2(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmsub_vf_f32mf2 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmsub_vf_f32mf2
// CHECK-RV64-SAME: (<vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmsub.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmsub.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfmsub_vf_f32mf2(vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) { vfloat32mf2_t test_vfmsub_vf_f32mf2(vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfmsub_vf_f32mf2(vd, rs1, vs2, vl); return __riscv_vfmsub_vf_f32mf2(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmsub_vv_f32m1 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmsub_vv_f32m1
// CHECK-RV64-SAME: (<vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmsub.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmsub.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfmsub_vv_f32m1(vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) { vfloat32m1_t test_vfmsub_vv_f32m1(vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfmsub_vv_f32m1(vd, vs1, vs2, vl); return __riscv_vfmsub_vv_f32m1(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmsub_vf_f32m1 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmsub_vf_f32m1
// CHECK-RV64-SAME: (<vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmsub.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmsub.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfmsub_vf_f32m1(vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) { vfloat32m1_t test_vfmsub_vf_f32m1(vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfmsub_vf_f32m1(vd, rs1, vs2, vl); return __riscv_vfmsub_vf_f32m1(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmsub_vv_f32m2 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmsub_vv_f32m2
// CHECK-RV64-SAME: (<vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmsub.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmsub.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfmsub_vv_f32m2(vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) { vfloat32m2_t test_vfmsub_vv_f32m2(vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfmsub_vv_f32m2(vd, vs1, vs2, vl); return __riscv_vfmsub_vv_f32m2(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmsub_vf_f32m2 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmsub_vf_f32m2
// CHECK-RV64-SAME: (<vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmsub.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmsub.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfmsub_vf_f32m2(vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) { vfloat32m2_t test_vfmsub_vf_f32m2(vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfmsub_vf_f32m2(vd, rs1, vs2, vl); return __riscv_vfmsub_vf_f32m2(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmsub_vv_f32m4 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmsub_vv_f32m4
// CHECK-RV64-SAME: (<vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmsub.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmsub.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfmsub_vv_f32m4(vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) { vfloat32m4_t test_vfmsub_vv_f32m4(vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfmsub_vv_f32m4(vd, vs1, vs2, vl); return __riscv_vfmsub_vv_f32m4(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmsub_vf_f32m4 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmsub_vf_f32m4
// CHECK-RV64-SAME: (<vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmsub.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmsub.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfmsub_vf_f32m4(vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) { vfloat32m4_t test_vfmsub_vf_f32m4(vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfmsub_vf_f32m4(vd, rs1, vs2, vl); return __riscv_vfmsub_vf_f32m4(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmsub_vv_f32m8 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmsub_vv_f32m8
// CHECK-RV64-SAME: (<vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmsub.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmsub.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfmsub_vv_f32m8(vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) { vfloat32m8_t test_vfmsub_vv_f32m8(vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfmsub_vv_f32m8(vd, vs1, vs2, vl); return __riscv_vfmsub_vv_f32m8(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmsub_vf_f32m8 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmsub_vf_f32m8
// CHECK-RV64-SAME: (<vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmsub.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmsub.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfmsub_vf_f32m8(vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) { vfloat32m8_t test_vfmsub_vf_f32m8(vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfmsub_vf_f32m8(vd, rs1, vs2, vl); return __riscv_vfmsub_vf_f32m8(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmsub_vv_f64m1 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmsub_vv_f64m1
// CHECK-RV64-SAME: (<vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmsub.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmsub.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfmsub_vv_f64m1(vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) { vfloat64m1_t test_vfmsub_vv_f64m1(vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfmsub_vv_f64m1(vd, vs1, vs2, vl); return __riscv_vfmsub_vv_f64m1(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmsub_vf_f64m1 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmsub_vf_f64m1
// CHECK-RV64-SAME: (<vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmsub.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmsub.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfmsub_vf_f64m1(vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) { vfloat64m1_t test_vfmsub_vf_f64m1(vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfmsub_vf_f64m1(vd, rs1, vs2, vl); return __riscv_vfmsub_vf_f64m1(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmsub_vv_f64m2 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmsub_vv_f64m2
// CHECK-RV64-SAME: (<vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmsub.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmsub.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfmsub_vv_f64m2(vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) { vfloat64m2_t test_vfmsub_vv_f64m2(vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfmsub_vv_f64m2(vd, vs1, vs2, vl); return __riscv_vfmsub_vv_f64m2(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmsub_vf_f64m2 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmsub_vf_f64m2
// CHECK-RV64-SAME: (<vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmsub.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmsub.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfmsub_vf_f64m2(vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) { vfloat64m2_t test_vfmsub_vf_f64m2(vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfmsub_vf_f64m2(vd, rs1, vs2, vl); return __riscv_vfmsub_vf_f64m2(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmsub_vv_f64m4 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmsub_vv_f64m4
// CHECK-RV64-SAME: (<vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmsub.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmsub.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfmsub_vv_f64m4(vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) { vfloat64m4_t test_vfmsub_vv_f64m4(vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfmsub_vv_f64m4(vd, vs1, vs2, vl); return __riscv_vfmsub_vv_f64m4(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmsub_vf_f64m4 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmsub_vf_f64m4
// CHECK-RV64-SAME: (<vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmsub.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmsub.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfmsub_vf_f64m4(vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) { vfloat64m4_t test_vfmsub_vf_f64m4(vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfmsub_vf_f64m4(vd, rs1, vs2, vl); return __riscv_vfmsub_vf_f64m4(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmsub_vv_f64m8 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmsub_vv_f64m8
// CHECK-RV64-SAME: (<vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmsub.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmsub.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfmsub_vv_f64m8(vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) { vfloat64m8_t test_vfmsub_vv_f64m8(vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfmsub_vv_f64m8(vd, vs1, vs2, vl); return __riscv_vfmsub_vv_f64m8(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmsub_vf_f64m8 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmsub_vf_f64m8
// CHECK-RV64-SAME: (<vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmsub.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmsub.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfmsub_vf_f64m8(vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) { vfloat64m8_t test_vfmsub_vf_f64m8(vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfmsub_vf_f64m8(vd, rs1, vs2, vl); return __riscv_vfmsub_vf_f64m8(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmsub_vv_f16mf4_m // CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmsub_vv_f16mf4_m
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmsub.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmsub.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
// //
vfloat16mf4_t test_vfmsub_vv_f16mf4_m(vbool64_t mask, vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) { vfloat16mf4_t test_vfmsub_vv_f16mf4_m(vbool64_t mask, vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfmsub_vv_f16mf4_m(mask, vd, vs1, vs2, vl); return __riscv_vfmsub_vv_f16mf4_m(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmsub_vf_f16mf4_m // CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmsub_vf_f16mf4_m
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmsub.mask.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmsub.mask.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
// //
vfloat16mf4_t test_vfmsub_vf_f16mf4_m(vbool64_t mask, vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) { vfloat16mf4_t test_vfmsub_vf_f16mf4_m(vbool64_t mask, vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfmsub_vf_f16mf4_m(mask, vd, rs1, vs2, vl); return __riscv_vfmsub_vf_f16mf4_m(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmsub_vv_f16mf2_m // CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmsub_vv_f16mf2_m
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmsub.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmsub.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
// //
vfloat16mf2_t test_vfmsub_vv_f16mf2_m(vbool32_t mask, vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) { vfloat16mf2_t test_vfmsub_vv_f16mf2_m(vbool32_t mask, vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfmsub_vv_f16mf2_m(mask, vd, vs1, vs2, vl); return __riscv_vfmsub_vv_f16mf2_m(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmsub_vf_f16mf2_m // CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmsub_vf_f16mf2_m
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmsub.mask.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmsub.mask.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
// //
vfloat16mf2_t test_vfmsub_vf_f16mf2_m(vbool32_t mask, vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) { vfloat16mf2_t test_vfmsub_vf_f16mf2_m(vbool32_t mask, vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfmsub_vf_f16mf2_m(mask, vd, rs1, vs2, vl); return __riscv_vfmsub_vf_f16mf2_m(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmsub_vv_f16m1_m // CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmsub_vv_f16m1_m
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmsub.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmsub.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
// //
vfloat16m1_t test_vfmsub_vv_f16m1_m(vbool16_t mask, vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) { vfloat16m1_t test_vfmsub_vv_f16m1_m(vbool16_t mask, vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfmsub_vv_f16m1_m(mask, vd, vs1, vs2, vl); return __riscv_vfmsub_vv_f16m1_m(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmsub_vf_f16m1_m // CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmsub_vf_f16m1_m
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmsub.mask.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmsub.mask.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
// //
vfloat16m1_t test_vfmsub_vf_f16m1_m(vbool16_t mask, vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) { vfloat16m1_t test_vfmsub_vf_f16m1_m(vbool16_t mask, vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfmsub_vf_f16m1_m(mask, vd, rs1, vs2, vl); return __riscv_vfmsub_vf_f16m1_m(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmsub_vv_f16m2_m // CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmsub_vv_f16m2_m
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmsub.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmsub.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
// //
vfloat16m2_t test_vfmsub_vv_f16m2_m(vbool8_t mask, vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) { vfloat16m2_t test_vfmsub_vv_f16m2_m(vbool8_t mask, vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfmsub_vv_f16m2_m(mask, vd, vs1, vs2, vl); return __riscv_vfmsub_vv_f16m2_m(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmsub_vf_f16m2_m // CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmsub_vf_f16m2_m
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmsub.mask.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmsub.mask.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
// //
vfloat16m2_t test_vfmsub_vf_f16m2_m(vbool8_t mask, vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) { vfloat16m2_t test_vfmsub_vf_f16m2_m(vbool8_t mask, vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfmsub_vf_f16m2_m(mask, vd, rs1, vs2, vl); return __riscv_vfmsub_vf_f16m2_m(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmsub_vv_f16m4_m // CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmsub_vv_f16m4_m
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmsub.mask.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmsub.mask.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
// //
vfloat16m4_t test_vfmsub_vv_f16m4_m(vbool4_t mask, vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) { vfloat16m4_t test_vfmsub_vv_f16m4_m(vbool4_t mask, vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfmsub_vv_f16m4_m(mask, vd, vs1, vs2, vl); return __riscv_vfmsub_vv_f16m4_m(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmsub_vf_f16m4_m // CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmsub_vf_f16m4_m
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmsub.mask.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmsub.mask.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
// //
vfloat16m4_t test_vfmsub_vf_f16m4_m(vbool4_t mask, vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) { vfloat16m4_t test_vfmsub_vf_f16m4_m(vbool4_t mask, vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfmsub_vf_f16m4_m(mask, vd, rs1, vs2, vl); return __riscv_vfmsub_vf_f16m4_m(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmsub_vv_f16m8_m // CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmsub_vv_f16m8_m
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmsub.mask.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmsub.mask.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
// //
vfloat16m8_t test_vfmsub_vv_f16m8_m(vbool2_t mask, vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) { vfloat16m8_t test_vfmsub_vv_f16m8_m(vbool2_t mask, vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfmsub_vv_f16m8_m(mask, vd, vs1, vs2, vl); return __riscv_vfmsub_vv_f16m8_m(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmsub_vf_f16m8_m // CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmsub_vf_f16m8_m
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmsub.mask.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmsub.mask.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
// //
vfloat16m8_t test_vfmsub_vf_f16m8_m(vbool2_t mask, vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) { vfloat16m8_t test_vfmsub_vf_f16m8_m(vbool2_t mask, vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfmsub_vf_f16m8_m(mask, vd, rs1, vs2, vl); return __riscv_vfmsub_vf_f16m8_m(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmsub_vv_f32mf2_m // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmsub_vv_f32mf2_m
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmsub.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmsub.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfmsub_vv_f32mf2_m(vbool64_t mask, vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) { vfloat32mf2_t test_vfmsub_vv_f32mf2_m(vbool64_t mask, vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfmsub_vv_f32mf2_m(mask, vd, vs1, vs2, vl); return __riscv_vfmsub_vv_f32mf2_m(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmsub_vf_f32mf2_m // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmsub_vf_f32mf2_m
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmsub.mask.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmsub.mask.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfmsub_vf_f32mf2_m(vbool64_t mask, vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) { vfloat32mf2_t test_vfmsub_vf_f32mf2_m(vbool64_t mask, vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfmsub_vf_f32mf2_m(mask, vd, rs1, vs2, vl); return __riscv_vfmsub_vf_f32mf2_m(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmsub_vv_f32m1_m // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmsub_vv_f32m1_m
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmsub.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmsub.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfmsub_vv_f32m1_m(vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) { vfloat32m1_t test_vfmsub_vv_f32m1_m(vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfmsub_vv_f32m1_m(mask, vd, vs1, vs2, vl); return __riscv_vfmsub_vv_f32m1_m(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmsub_vf_f32m1_m // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmsub_vf_f32m1_m
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmsub.mask.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmsub.mask.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfmsub_vf_f32m1_m(vbool32_t mask, vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) { vfloat32m1_t test_vfmsub_vf_f32m1_m(vbool32_t mask, vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfmsub_vf_f32m1_m(mask, vd, rs1, vs2, vl); return __riscv_vfmsub_vf_f32m1_m(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmsub_vv_f32m2_m // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmsub_vv_f32m2_m
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmsub.mask.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmsub.mask.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfmsub_vv_f32m2_m(vbool16_t mask, vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) { vfloat32m2_t test_vfmsub_vv_f32m2_m(vbool16_t mask, vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfmsub_vv_f32m2_m(mask, vd, vs1, vs2, vl); return __riscv_vfmsub_vv_f32m2_m(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmsub_vf_f32m2_m // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmsub_vf_f32m2_m
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmsub.mask.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmsub.mask.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfmsub_vf_f32m2_m(vbool16_t mask, vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) { vfloat32m2_t test_vfmsub_vf_f32m2_m(vbool16_t mask, vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfmsub_vf_f32m2_m(mask, vd, rs1, vs2, vl); return __riscv_vfmsub_vf_f32m2_m(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmsub_vv_f32m4_m // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmsub_vv_f32m4_m
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmsub.mask.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmsub.mask.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfmsub_vv_f32m4_m(vbool8_t mask, vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) { vfloat32m4_t test_vfmsub_vv_f32m4_m(vbool8_t mask, vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfmsub_vv_f32m4_m(mask, vd, vs1, vs2, vl); return __riscv_vfmsub_vv_f32m4_m(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmsub_vf_f32m4_m // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmsub_vf_f32m4_m
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmsub.mask.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmsub.mask.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfmsub_vf_f32m4_m(vbool8_t mask, vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) { vfloat32m4_t test_vfmsub_vf_f32m4_m(vbool8_t mask, vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfmsub_vf_f32m4_m(mask, vd, rs1, vs2, vl); return __riscv_vfmsub_vf_f32m4_m(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmsub_vv_f32m8_m // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmsub_vv_f32m8_m
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmsub.mask.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmsub.mask.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfmsub_vv_f32m8_m(vbool4_t mask, vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) { vfloat32m8_t test_vfmsub_vv_f32m8_m(vbool4_t mask, vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfmsub_vv_f32m8_m(mask, vd, vs1, vs2, vl); return __riscv_vfmsub_vv_f32m8_m(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmsub_vf_f32m8_m // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmsub_vf_f32m8_m
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmsub.mask.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmsub.mask.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfmsub_vf_f32m8_m(vbool4_t mask, vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) { vfloat32m8_t test_vfmsub_vf_f32m8_m(vbool4_t mask, vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfmsub_vf_f32m8_m(mask, vd, rs1, vs2, vl); return __riscv_vfmsub_vf_f32m8_m(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmsub_vv_f64m1_m // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmsub_vv_f64m1_m
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmsub.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmsub.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfmsub_vv_f64m1_m(vbool64_t mask, vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) { vfloat64m1_t test_vfmsub_vv_f64m1_m(vbool64_t mask, vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfmsub_vv_f64m1_m(mask, vd, vs1, vs2, vl); return __riscv_vfmsub_vv_f64m1_m(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmsub_vf_f64m1_m // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmsub_vf_f64m1_m
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmsub.mask.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmsub.mask.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfmsub_vf_f64m1_m(vbool64_t mask, vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) { vfloat64m1_t test_vfmsub_vf_f64m1_m(vbool64_t mask, vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfmsub_vf_f64m1_m(mask, vd, rs1, vs2, vl); return __riscv_vfmsub_vf_f64m1_m(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmsub_vv_f64m2_m // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmsub_vv_f64m2_m
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmsub.mask.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmsub.mask.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfmsub_vv_f64m2_m(vbool32_t mask, vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) { vfloat64m2_t test_vfmsub_vv_f64m2_m(vbool32_t mask, vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfmsub_vv_f64m2_m(mask, vd, vs1, vs2, vl); return __riscv_vfmsub_vv_f64m2_m(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmsub_vf_f64m2_m // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmsub_vf_f64m2_m
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmsub.mask.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmsub.mask.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfmsub_vf_f64m2_m(vbool32_t mask, vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) { vfloat64m2_t test_vfmsub_vf_f64m2_m(vbool32_t mask, vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfmsub_vf_f64m2_m(mask, vd, rs1, vs2, vl); return __riscv_vfmsub_vf_f64m2_m(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmsub_vv_f64m4_m // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmsub_vv_f64m4_m
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmsub.mask.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmsub.mask.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfmsub_vv_f64m4_m(vbool16_t mask, vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) { vfloat64m4_t test_vfmsub_vv_f64m4_m(vbool16_t mask, vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfmsub_vv_f64m4_m(mask, vd, vs1, vs2, vl); return __riscv_vfmsub_vv_f64m4_m(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmsub_vf_f64m4_m // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmsub_vf_f64m4_m
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmsub.mask.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmsub.mask.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfmsub_vf_f64m4_m(vbool16_t mask, vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) { vfloat64m4_t test_vfmsub_vf_f64m4_m(vbool16_t mask, vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfmsub_vf_f64m4_m(mask, vd, rs1, vs2, vl); return __riscv_vfmsub_vf_f64m4_m(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmsub_vv_f64m8_m // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmsub_vv_f64m8_m
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmsub.mask.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmsub.mask.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfmsub_vv_f64m8_m(vbool8_t mask, vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) { vfloat64m8_t test_vfmsub_vv_f64m8_m(vbool8_t mask, vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfmsub_vv_f64m8_m(mask, vd, vs1, vs2, vl); return __riscv_vfmsub_vv_f64m8_m(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmsub_vf_f64m8_m // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmsub_vf_f64m8_m
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmsub.mask.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmsub.mask.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfmsub_vf_f64m8_m(vbool8_t mask, vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) { vfloat64m8_t test_vfmsub_vf_f64m8_m(vbool8_t mask, vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfmsub_vf_f64m8_m(mask, vd, rs1, vs2, vl); return __riscv_vfmsub_vf_f64m8_m(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmsub_vv_f16mf4_rm
// CHECK-RV64-SAME: (<vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmsub.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
//
vfloat16mf4_t test_vfmsub_vv_f16mf4_rm(vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfmsub_vv_f16mf4_rm(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmsub_vf_f16mf4_rm
// CHECK-RV64-SAME: (<vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmsub.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
//
vfloat16mf4_t test_vfmsub_vf_f16mf4_rm(vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfmsub_vf_f16mf4_rm(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmsub_vv_f16mf2_rm
// CHECK-RV64-SAME: (<vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmsub.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
//
vfloat16mf2_t test_vfmsub_vv_f16mf2_rm(vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfmsub_vv_f16mf2_rm(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmsub_vf_f16mf2_rm
// CHECK-RV64-SAME: (<vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmsub.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
//
vfloat16mf2_t test_vfmsub_vf_f16mf2_rm(vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfmsub_vf_f16mf2_rm(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmsub_vv_f16m1_rm
// CHECK-RV64-SAME: (<vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmsub.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfmsub_vv_f16m1_rm(vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfmsub_vv_f16m1_rm(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmsub_vf_f16m1_rm
// CHECK-RV64-SAME: (<vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmsub.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfmsub_vf_f16m1_rm(vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfmsub_vf_f16m1_rm(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmsub_vv_f16m2_rm
// CHECK-RV64-SAME: (<vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmsub.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
//
vfloat16m2_t test_vfmsub_vv_f16m2_rm(vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfmsub_vv_f16m2_rm(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmsub_vf_f16m2_rm
// CHECK-RV64-SAME: (<vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmsub.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
//
vfloat16m2_t test_vfmsub_vf_f16m2_rm(vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfmsub_vf_f16m2_rm(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmsub_vv_f16m4_rm
// CHECK-RV64-SAME: (<vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmsub.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
//
vfloat16m4_t test_vfmsub_vv_f16m4_rm(vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfmsub_vv_f16m4_rm(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmsub_vf_f16m4_rm
// CHECK-RV64-SAME: (<vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmsub.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
//
vfloat16m4_t test_vfmsub_vf_f16m4_rm(vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfmsub_vf_f16m4_rm(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmsub_vv_f16m8_rm
// CHECK-RV64-SAME: (<vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmsub.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
//
vfloat16m8_t test_vfmsub_vv_f16m8_rm(vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfmsub_vv_f16m8_rm(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmsub_vf_f16m8_rm
// CHECK-RV64-SAME: (<vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmsub.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
//
vfloat16m8_t test_vfmsub_vf_f16m8_rm(vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfmsub_vf_f16m8_rm(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmsub_vv_f32mf2_rm
// CHECK-RV64-SAME: (<vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmsub.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
//
vfloat32mf2_t test_vfmsub_vv_f32mf2_rm(vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfmsub_vv_f32mf2_rm(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmsub_vf_f32mf2_rm
// CHECK-RV64-SAME: (<vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmsub.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
//
vfloat32mf2_t test_vfmsub_vf_f32mf2_rm(vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfmsub_vf_f32mf2_rm(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmsub_vv_f32m1_rm
// CHECK-RV64-SAME: (<vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmsub.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfmsub_vv_f32m1_rm(vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfmsub_vv_f32m1_rm(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmsub_vf_f32m1_rm
// CHECK-RV64-SAME: (<vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmsub.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfmsub_vf_f32m1_rm(vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfmsub_vf_f32m1_rm(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmsub_vv_f32m2_rm
// CHECK-RV64-SAME: (<vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmsub.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
//
vfloat32m2_t test_vfmsub_vv_f32m2_rm(vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfmsub_vv_f32m2_rm(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmsub_vf_f32m2_rm
// CHECK-RV64-SAME: (<vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmsub.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
//
vfloat32m2_t test_vfmsub_vf_f32m2_rm(vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfmsub_vf_f32m2_rm(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmsub_vv_f32m4_rm
// CHECK-RV64-SAME: (<vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmsub.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
//
vfloat32m4_t test_vfmsub_vv_f32m4_rm(vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfmsub_vv_f32m4_rm(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmsub_vf_f32m4_rm
// CHECK-RV64-SAME: (<vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmsub.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
//
vfloat32m4_t test_vfmsub_vf_f32m4_rm(vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfmsub_vf_f32m4_rm(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmsub_vv_f32m8_rm
// CHECK-RV64-SAME: (<vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmsub.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
//
vfloat32m8_t test_vfmsub_vv_f32m8_rm(vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfmsub_vv_f32m8_rm(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmsub_vf_f32m8_rm
// CHECK-RV64-SAME: (<vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmsub.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
//
vfloat32m8_t test_vfmsub_vf_f32m8_rm(vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfmsub_vf_f32m8_rm(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmsub_vv_f64m1_rm
// CHECK-RV64-SAME: (<vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmsub.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfmsub_vv_f64m1_rm(vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfmsub_vv_f64m1_rm(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmsub_vf_f64m1_rm
// CHECK-RV64-SAME: (<vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmsub.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfmsub_vf_f64m1_rm(vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfmsub_vf_f64m1_rm(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmsub_vv_f64m2_rm
// CHECK-RV64-SAME: (<vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmsub.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
//
vfloat64m2_t test_vfmsub_vv_f64m2_rm(vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfmsub_vv_f64m2_rm(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmsub_vf_f64m2_rm
// CHECK-RV64-SAME: (<vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmsub.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
//
vfloat64m2_t test_vfmsub_vf_f64m2_rm(vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfmsub_vf_f64m2_rm(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmsub_vv_f64m4_rm
// CHECK-RV64-SAME: (<vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmsub.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
//
vfloat64m4_t test_vfmsub_vv_f64m4_rm(vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfmsub_vv_f64m4_rm(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmsub_vf_f64m4_rm
// CHECK-RV64-SAME: (<vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmsub.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
//
vfloat64m4_t test_vfmsub_vf_f64m4_rm(vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfmsub_vf_f64m4_rm(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmsub_vv_f64m8_rm
// CHECK-RV64-SAME: (<vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmsub.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
//
vfloat64m8_t test_vfmsub_vv_f64m8_rm(vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfmsub_vv_f64m8_rm(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmsub_vf_f64m8_rm
// CHECK-RV64-SAME: (<vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmsub.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
//
vfloat64m8_t test_vfmsub_vf_f64m8_rm(vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfmsub_vf_f64m8_rm(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmsub_vv_f16mf4_rm_m
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmsub.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
//
vfloat16mf4_t test_vfmsub_vv_f16mf4_rm_m(vbool64_t mask, vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfmsub_vv_f16mf4_rm_m(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmsub_vf_f16mf4_rm_m
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmsub.mask.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
//
vfloat16mf4_t test_vfmsub_vf_f16mf4_rm_m(vbool64_t mask, vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfmsub_vf_f16mf4_rm_m(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmsub_vv_f16mf2_rm_m
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmsub.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
//
vfloat16mf2_t test_vfmsub_vv_f16mf2_rm_m(vbool32_t mask, vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfmsub_vv_f16mf2_rm_m(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmsub_vf_f16mf2_rm_m
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmsub.mask.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
//
vfloat16mf2_t test_vfmsub_vf_f16mf2_rm_m(vbool32_t mask, vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfmsub_vf_f16mf2_rm_m(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmsub_vv_f16m1_rm_m
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmsub.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfmsub_vv_f16m1_rm_m(vbool16_t mask, vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfmsub_vv_f16m1_rm_m(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmsub_vf_f16m1_rm_m
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmsub.mask.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfmsub_vf_f16m1_rm_m(vbool16_t mask, vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfmsub_vf_f16m1_rm_m(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmsub_vv_f16m2_rm_m
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmsub.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
//
vfloat16m2_t test_vfmsub_vv_f16m2_rm_m(vbool8_t mask, vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfmsub_vv_f16m2_rm_m(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmsub_vf_f16m2_rm_m
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmsub.mask.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
//
vfloat16m2_t test_vfmsub_vf_f16m2_rm_m(vbool8_t mask, vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfmsub_vf_f16m2_rm_m(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmsub_vv_f16m4_rm_m
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmsub.mask.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
//
vfloat16m4_t test_vfmsub_vv_f16m4_rm_m(vbool4_t mask, vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfmsub_vv_f16m4_rm_m(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmsub_vf_f16m4_rm_m
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmsub.mask.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
//
vfloat16m4_t test_vfmsub_vf_f16m4_rm_m(vbool4_t mask, vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfmsub_vf_f16m4_rm_m(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmsub_vv_f16m8_rm_m
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmsub.mask.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
//
vfloat16m8_t test_vfmsub_vv_f16m8_rm_m(vbool2_t mask, vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfmsub_vv_f16m8_rm_m(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmsub_vf_f16m8_rm_m
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmsub.mask.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
//
vfloat16m8_t test_vfmsub_vf_f16m8_rm_m(vbool2_t mask, vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfmsub_vf_f16m8_rm_m(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmsub_vv_f32mf2_rm_m
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmsub.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
//
vfloat32mf2_t test_vfmsub_vv_f32mf2_rm_m(vbool64_t mask, vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfmsub_vv_f32mf2_rm_m(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmsub_vf_f32mf2_rm_m
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmsub.mask.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
//
vfloat32mf2_t test_vfmsub_vf_f32mf2_rm_m(vbool64_t mask, vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfmsub_vf_f32mf2_rm_m(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmsub_vv_f32m1_rm_m
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmsub.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfmsub_vv_f32m1_rm_m(vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfmsub_vv_f32m1_rm_m(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmsub_vf_f32m1_rm_m
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmsub.mask.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfmsub_vf_f32m1_rm_m(vbool32_t mask, vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfmsub_vf_f32m1_rm_m(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmsub_vv_f32m2_rm_m
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmsub.mask.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
//
vfloat32m2_t test_vfmsub_vv_f32m2_rm_m(vbool16_t mask, vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfmsub_vv_f32m2_rm_m(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmsub_vf_f32m2_rm_m
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmsub.mask.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
//
vfloat32m2_t test_vfmsub_vf_f32m2_rm_m(vbool16_t mask, vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfmsub_vf_f32m2_rm_m(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmsub_vv_f32m4_rm_m
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmsub.mask.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
//
vfloat32m4_t test_vfmsub_vv_f32m4_rm_m(vbool8_t mask, vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfmsub_vv_f32m4_rm_m(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmsub_vf_f32m4_rm_m
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmsub.mask.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
//
vfloat32m4_t test_vfmsub_vf_f32m4_rm_m(vbool8_t mask, vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfmsub_vf_f32m4_rm_m(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmsub_vv_f32m8_rm_m
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmsub.mask.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
//
vfloat32m8_t test_vfmsub_vv_f32m8_rm_m(vbool4_t mask, vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfmsub_vv_f32m8_rm_m(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmsub_vf_f32m8_rm_m
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmsub.mask.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
//
vfloat32m8_t test_vfmsub_vf_f32m8_rm_m(vbool4_t mask, vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfmsub_vf_f32m8_rm_m(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmsub_vv_f64m1_rm_m
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmsub.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfmsub_vv_f64m1_rm_m(vbool64_t mask, vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfmsub_vv_f64m1_rm_m(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmsub_vf_f64m1_rm_m
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmsub.mask.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfmsub_vf_f64m1_rm_m(vbool64_t mask, vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfmsub_vf_f64m1_rm_m(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmsub_vv_f64m2_rm_m
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmsub.mask.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
//
vfloat64m2_t test_vfmsub_vv_f64m2_rm_m(vbool32_t mask, vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfmsub_vv_f64m2_rm_m(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmsub_vf_f64m2_rm_m
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmsub.mask.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
//
vfloat64m2_t test_vfmsub_vf_f64m2_rm_m(vbool32_t mask, vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfmsub_vf_f64m2_rm_m(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmsub_vv_f64m4_rm_m
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmsub.mask.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
//
vfloat64m4_t test_vfmsub_vv_f64m4_rm_m(vbool16_t mask, vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfmsub_vv_f64m4_rm_m(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmsub_vf_f64m4_rm_m
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmsub.mask.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
//
vfloat64m4_t test_vfmsub_vf_f64m4_rm_m(vbool16_t mask, vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfmsub_vf_f64m4_rm_m(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmsub_vv_f64m8_rm_m
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmsub.mask.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
//
vfloat64m8_t test_vfmsub_vv_f64m8_rm_m(vbool8_t mask, vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfmsub_vv_f64m8_rm_m(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmsub_vf_f64m8_rm_m
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmsub.mask.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
//
vfloat64m8_t test_vfmsub_vf_f64m8_rm_m(vbool8_t mask, vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfmsub_vf_f64m8_rm_m(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}

clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmacc.c

// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target // REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh \ // RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh \
// RUN: -target-feature +experimental-zvfh -disable-O0-optnone \ // RUN: -target-feature +experimental-zvfh -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ // RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s // RUN: FileCheck --check-prefix=CHECK-RV64 %s
#include <riscv_vector.h> #include <riscv_vector.h>
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmacc_vv_f16mf4 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmacc_vv_f16mf4
// CHECK-RV64-SAME: (<vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK-RV64-SAME: (<vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmacc.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmacc.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
// //
vfloat16mf4_t test_vfnmacc_vv_f16mf4(vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) { vfloat16mf4_t test_vfnmacc_vv_f16mf4(vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfnmacc_vv_f16mf4(vd, vs1, vs2, vl); return __riscv_vfnmacc_vv_f16mf4(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmacc_vf_f16mf4 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmacc_vf_f16mf4
// CHECK-RV64-SAME: (<vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmacc.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmacc.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
// //
vfloat16mf4_t test_vfnmacc_vf_f16mf4(vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) { vfloat16mf4_t test_vfnmacc_vf_f16mf4(vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfnmacc_vf_f16mf4(vd, rs1, vs2, vl); return __riscv_vfnmacc_vf_f16mf4(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmacc_vv_f16mf2 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmacc_vv_f16mf2
// CHECK-RV64-SAME: (<vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmacc.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmacc.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
// //
vfloat16mf2_t test_vfnmacc_vv_f16mf2(vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) { vfloat16mf2_t test_vfnmacc_vv_f16mf2(vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfnmacc_vv_f16mf2(vd, vs1, vs2, vl); return __riscv_vfnmacc_vv_f16mf2(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmacc_vf_f16mf2 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmacc_vf_f16mf2
// CHECK-RV64-SAME: (<vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmacc.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmacc.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
// //
vfloat16mf2_t test_vfnmacc_vf_f16mf2(vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) { vfloat16mf2_t test_vfnmacc_vf_f16mf2(vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfnmacc_vf_f16mf2(vd, rs1, vs2, vl); return __riscv_vfnmacc_vf_f16mf2(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmacc_vv_f16m1 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmacc_vv_f16m1
// CHECK-RV64-SAME: (<vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmacc.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmacc.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
// //
vfloat16m1_t test_vfnmacc_vv_f16m1(vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) { vfloat16m1_t test_vfnmacc_vv_f16m1(vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfnmacc_vv_f16m1(vd, vs1, vs2, vl); return __riscv_vfnmacc_vv_f16m1(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmacc_vf_f16m1 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmacc_vf_f16m1
// CHECK-RV64-SAME: (<vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmacc.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmacc.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
// //
vfloat16m1_t test_vfnmacc_vf_f16m1(vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) { vfloat16m1_t test_vfnmacc_vf_f16m1(vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfnmacc_vf_f16m1(vd, rs1, vs2, vl); return __riscv_vfnmacc_vf_f16m1(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmacc_vv_f16m2 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmacc_vv_f16m2
// CHECK-RV64-SAME: (<vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmacc.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmacc.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
// //
vfloat16m2_t test_vfnmacc_vv_f16m2(vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) { vfloat16m2_t test_vfnmacc_vv_f16m2(vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfnmacc_vv_f16m2(vd, vs1, vs2, vl); return __riscv_vfnmacc_vv_f16m2(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmacc_vf_f16m2 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmacc_vf_f16m2
// CHECK-RV64-SAME: (<vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmacc.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmacc.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
// //
vfloat16m2_t test_vfnmacc_vf_f16m2(vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) { vfloat16m2_t test_vfnmacc_vf_f16m2(vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfnmacc_vf_f16m2(vd, rs1, vs2, vl); return __riscv_vfnmacc_vf_f16m2(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmacc_vv_f16m4 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmacc_vv_f16m4
// CHECK-RV64-SAME: (<vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmacc.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmacc.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
// //
vfloat16m4_t test_vfnmacc_vv_f16m4(vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) { vfloat16m4_t test_vfnmacc_vv_f16m4(vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfnmacc_vv_f16m4(vd, vs1, vs2, vl); return __riscv_vfnmacc_vv_f16m4(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmacc_vf_f16m4 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmacc_vf_f16m4
// CHECK-RV64-SAME: (<vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmacc.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmacc.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
// //
vfloat16m4_t test_vfnmacc_vf_f16m4(vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) { vfloat16m4_t test_vfnmacc_vf_f16m4(vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfnmacc_vf_f16m4(vd, rs1, vs2, vl); return __riscv_vfnmacc_vf_f16m4(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmacc_vv_f16m8 // CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmacc_vv_f16m8
// CHECK-RV64-SAME: (<vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmacc.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmacc.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
// //
vfloat16m8_t test_vfnmacc_vv_f16m8(vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) { vfloat16m8_t test_vfnmacc_vv_f16m8(vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfnmacc_vv_f16m8(vd, vs1, vs2, vl); return __riscv_vfnmacc_vv_f16m8(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmacc_vf_f16m8 // CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmacc_vf_f16m8
// CHECK-RV64-SAME: (<vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmacc.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmacc.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
// //
vfloat16m8_t test_vfnmacc_vf_f16m8(vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) { vfloat16m8_t test_vfnmacc_vf_f16m8(vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfnmacc_vf_f16m8(vd, rs1, vs2, vl); return __riscv_vfnmacc_vf_f16m8(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmacc_vv_f32mf2 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmacc_vv_f32mf2
// CHECK-RV64-SAME: (<vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmacc.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmacc.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfnmacc_vv_f32mf2(vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) { vfloat32mf2_t test_vfnmacc_vv_f32mf2(vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfnmacc_vv_f32mf2(vd, vs1, vs2, vl); return __riscv_vfnmacc_vv_f32mf2(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmacc_vf_f32mf2 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmacc_vf_f32mf2
// CHECK-RV64-SAME: (<vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmacc.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmacc.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfnmacc_vf_f32mf2(vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) { vfloat32mf2_t test_vfnmacc_vf_f32mf2(vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfnmacc_vf_f32mf2(vd, rs1, vs2, vl); return __riscv_vfnmacc_vf_f32mf2(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmacc_vv_f32m1 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmacc_vv_f32m1
// CHECK-RV64-SAME: (<vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmacc.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmacc.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfnmacc_vv_f32m1(vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) { vfloat32m1_t test_vfnmacc_vv_f32m1(vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfnmacc_vv_f32m1(vd, vs1, vs2, vl); return __riscv_vfnmacc_vv_f32m1(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmacc_vf_f32m1 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmacc_vf_f32m1
// CHECK-RV64-SAME: (<vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmacc.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmacc.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfnmacc_vf_f32m1(vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) { vfloat32m1_t test_vfnmacc_vf_f32m1(vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfnmacc_vf_f32m1(vd, rs1, vs2, vl); return __riscv_vfnmacc_vf_f32m1(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmacc_vv_f32m2 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmacc_vv_f32m2
// CHECK-RV64-SAME: (<vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmacc.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmacc.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfnmacc_vv_f32m2(vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) { vfloat32m2_t test_vfnmacc_vv_f32m2(vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfnmacc_vv_f32m2(vd, vs1, vs2, vl); return __riscv_vfnmacc_vv_f32m2(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmacc_vf_f32m2 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmacc_vf_f32m2
// CHECK-RV64-SAME: (<vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmacc.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmacc.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfnmacc_vf_f32m2(vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) { vfloat32m2_t test_vfnmacc_vf_f32m2(vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfnmacc_vf_f32m2(vd, rs1, vs2, vl); return __riscv_vfnmacc_vf_f32m2(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmacc_vv_f32m4 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmacc_vv_f32m4
// CHECK-RV64-SAME: (<vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmacc.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmacc.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfnmacc_vv_f32m4(vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) { vfloat32m4_t test_vfnmacc_vv_f32m4(vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfnmacc_vv_f32m4(vd, vs1, vs2, vl); return __riscv_vfnmacc_vv_f32m4(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmacc_vf_f32m4 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmacc_vf_f32m4
// CHECK-RV64-SAME: (<vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmacc.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmacc.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfnmacc_vf_f32m4(vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) { vfloat32m4_t test_vfnmacc_vf_f32m4(vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfnmacc_vf_f32m4(vd, rs1, vs2, vl); return __riscv_vfnmacc_vf_f32m4(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmacc_vv_f32m8 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmacc_vv_f32m8
// CHECK-RV64-SAME: (<vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmacc.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmacc.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfnmacc_vv_f32m8(vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) { vfloat32m8_t test_vfnmacc_vv_f32m8(vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfnmacc_vv_f32m8(vd, vs1, vs2, vl); return __riscv_vfnmacc_vv_f32m8(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmacc_vf_f32m8 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmacc_vf_f32m8
// CHECK-RV64-SAME: (<vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmacc.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmacc.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfnmacc_vf_f32m8(vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) { vfloat32m8_t test_vfnmacc_vf_f32m8(vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfnmacc_vf_f32m8(vd, rs1, vs2, vl); return __riscv_vfnmacc_vf_f32m8(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmacc_vv_f64m1 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmacc_vv_f64m1
// CHECK-RV64-SAME: (<vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmacc.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmacc.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfnmacc_vv_f64m1(vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) { vfloat64m1_t test_vfnmacc_vv_f64m1(vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfnmacc_vv_f64m1(vd, vs1, vs2, vl); return __riscv_vfnmacc_vv_f64m1(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmacc_vf_f64m1 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmacc_vf_f64m1
// CHECK-RV64-SAME: (<vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmacc.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmacc.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfnmacc_vf_f64m1(vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) { vfloat64m1_t test_vfnmacc_vf_f64m1(vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfnmacc_vf_f64m1(vd, rs1, vs2, vl); return __riscv_vfnmacc_vf_f64m1(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmacc_vv_f64m2 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmacc_vv_f64m2
// CHECK-RV64-SAME: (<vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmacc.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmacc.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfnmacc_vv_f64m2(vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) { vfloat64m2_t test_vfnmacc_vv_f64m2(vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfnmacc_vv_f64m2(vd, vs1, vs2, vl); return __riscv_vfnmacc_vv_f64m2(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmacc_vf_f64m2 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmacc_vf_f64m2
// CHECK-RV64-SAME: (<vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmacc.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmacc.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfnmacc_vf_f64m2(vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) { vfloat64m2_t test_vfnmacc_vf_f64m2(vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfnmacc_vf_f64m2(vd, rs1, vs2, vl); return __riscv_vfnmacc_vf_f64m2(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmacc_vv_f64m4 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmacc_vv_f64m4
// CHECK-RV64-SAME: (<vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmacc.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmacc.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfnmacc_vv_f64m4(vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) { vfloat64m4_t test_vfnmacc_vv_f64m4(vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfnmacc_vv_f64m4(vd, vs1, vs2, vl); return __riscv_vfnmacc_vv_f64m4(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmacc_vf_f64m4 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmacc_vf_f64m4
// CHECK-RV64-SAME: (<vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmacc.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmacc.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfnmacc_vf_f64m4(vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) { vfloat64m4_t test_vfnmacc_vf_f64m4(vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfnmacc_vf_f64m4(vd, rs1, vs2, vl); return __riscv_vfnmacc_vf_f64m4(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmacc_vv_f64m8 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmacc_vv_f64m8
// CHECK-RV64-SAME: (<vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmacc.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmacc.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfnmacc_vv_f64m8(vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) { vfloat64m8_t test_vfnmacc_vv_f64m8(vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfnmacc_vv_f64m8(vd, vs1, vs2, vl); return __riscv_vfnmacc_vv_f64m8(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmacc_vf_f64m8 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmacc_vf_f64m8
// CHECK-RV64-SAME: (<vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmacc.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmacc.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfnmacc_vf_f64m8(vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) { vfloat64m8_t test_vfnmacc_vf_f64m8(vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfnmacc_vf_f64m8(vd, rs1, vs2, vl); return __riscv_vfnmacc_vf_f64m8(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmacc_vv_f16mf4_m // CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmacc_vv_f16mf4_m
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmacc.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmacc.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
// //
vfloat16mf4_t test_vfnmacc_vv_f16mf4_m(vbool64_t mask, vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) { vfloat16mf4_t test_vfnmacc_vv_f16mf4_m(vbool64_t mask, vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfnmacc_vv_f16mf4_m(mask, vd, vs1, vs2, vl); return __riscv_vfnmacc_vv_f16mf4_m(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmacc_vf_f16mf4_m // CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmacc_vf_f16mf4_m
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmacc.mask.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmacc.mask.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
// //
vfloat16mf4_t test_vfnmacc_vf_f16mf4_m(vbool64_t mask, vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) { vfloat16mf4_t test_vfnmacc_vf_f16mf4_m(vbool64_t mask, vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfnmacc_vf_f16mf4_m(mask, vd, rs1, vs2, vl); return __riscv_vfnmacc_vf_f16mf4_m(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmacc_vv_f16mf2_m // CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmacc_vv_f16mf2_m
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmacc.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmacc.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
// //
vfloat16mf2_t test_vfnmacc_vv_f16mf2_m(vbool32_t mask, vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) { vfloat16mf2_t test_vfnmacc_vv_f16mf2_m(vbool32_t mask, vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfnmacc_vv_f16mf2_m(mask, vd, vs1, vs2, vl); return __riscv_vfnmacc_vv_f16mf2_m(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmacc_vf_f16mf2_m // CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmacc_vf_f16mf2_m
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmacc.mask.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmacc.mask.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
// //
vfloat16mf2_t test_vfnmacc_vf_f16mf2_m(vbool32_t mask, vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) { vfloat16mf2_t test_vfnmacc_vf_f16mf2_m(vbool32_t mask, vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfnmacc_vf_f16mf2_m(mask, vd, rs1, vs2, vl); return __riscv_vfnmacc_vf_f16mf2_m(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmacc_vv_f16m1_m // CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmacc_vv_f16m1_m
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmacc.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmacc.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
// //
vfloat16m1_t test_vfnmacc_vv_f16m1_m(vbool16_t mask, vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) { vfloat16m1_t test_vfnmacc_vv_f16m1_m(vbool16_t mask, vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfnmacc_vv_f16m1_m(mask, vd, vs1, vs2, vl); return __riscv_vfnmacc_vv_f16m1_m(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmacc_vf_f16m1_m // CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmacc_vf_f16m1_m
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmacc.mask.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmacc.mask.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
// //
vfloat16m1_t test_vfnmacc_vf_f16m1_m(vbool16_t mask, vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) { vfloat16m1_t test_vfnmacc_vf_f16m1_m(vbool16_t mask, vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfnmacc_vf_f16m1_m(mask, vd, rs1, vs2, vl); return __riscv_vfnmacc_vf_f16m1_m(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmacc_vv_f16m2_m // CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmacc_vv_f16m2_m
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmacc.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmacc.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
// //
vfloat16m2_t test_vfnmacc_vv_f16m2_m(vbool8_t mask, vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) { vfloat16m2_t test_vfnmacc_vv_f16m2_m(vbool8_t mask, vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfnmacc_vv_f16m2_m(mask, vd, vs1, vs2, vl); return __riscv_vfnmacc_vv_f16m2_m(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmacc_vf_f16m2_m // CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmacc_vf_f16m2_m
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmacc.mask.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmacc.mask.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
// //
vfloat16m2_t test_vfnmacc_vf_f16m2_m(vbool8_t mask, vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) { vfloat16m2_t test_vfnmacc_vf_f16m2_m(vbool8_t mask, vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfnmacc_vf_f16m2_m(mask, vd, rs1, vs2, vl); return __riscv_vfnmacc_vf_f16m2_m(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmacc_vv_f16m4_m // CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmacc_vv_f16m4_m
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmacc.mask.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmacc.mask.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
// //
vfloat16m4_t test_vfnmacc_vv_f16m4_m(vbool4_t mask, vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) { vfloat16m4_t test_vfnmacc_vv_f16m4_m(vbool4_t mask, vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfnmacc_vv_f16m4_m(mask, vd, vs1, vs2, vl); return __riscv_vfnmacc_vv_f16m4_m(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmacc_vf_f16m4_m // CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmacc_vf_f16m4_m
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmacc.mask.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmacc.mask.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
// //
vfloat16m4_t test_vfnmacc_vf_f16m4_m(vbool4_t mask, vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) { vfloat16m4_t test_vfnmacc_vf_f16m4_m(vbool4_t mask, vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfnmacc_vf_f16m4_m(mask, vd, rs1, vs2, vl); return __riscv_vfnmacc_vf_f16m4_m(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmacc_vv_f16m8_m // CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmacc_vv_f16m8_m
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmacc.mask.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmacc.mask.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
// //
vfloat16m8_t test_vfnmacc_vv_f16m8_m(vbool2_t mask, vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) { vfloat16m8_t test_vfnmacc_vv_f16m8_m(vbool2_t mask, vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfnmacc_vv_f16m8_m(mask, vd, vs1, vs2, vl); return __riscv_vfnmacc_vv_f16m8_m(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmacc_vf_f16m8_m // CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmacc_vf_f16m8_m
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmacc.mask.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmacc.mask.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
// //
vfloat16m8_t test_vfnmacc_vf_f16m8_m(vbool2_t mask, vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) { vfloat16m8_t test_vfnmacc_vf_f16m8_m(vbool2_t mask, vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfnmacc_vf_f16m8_m(mask, vd, rs1, vs2, vl); return __riscv_vfnmacc_vf_f16m8_m(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmacc_vv_f32mf2_m // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmacc_vv_f32mf2_m
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmacc.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmacc.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfnmacc_vv_f32mf2_m(vbool64_t mask, vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) { vfloat32mf2_t test_vfnmacc_vv_f32mf2_m(vbool64_t mask, vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfnmacc_vv_f32mf2_m(mask, vd, vs1, vs2, vl); return __riscv_vfnmacc_vv_f32mf2_m(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmacc_vf_f32mf2_m // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmacc_vf_f32mf2_m
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmacc.mask.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmacc.mask.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfnmacc_vf_f32mf2_m(vbool64_t mask, vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) { vfloat32mf2_t test_vfnmacc_vf_f32mf2_m(vbool64_t mask, vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfnmacc_vf_f32mf2_m(mask, vd, rs1, vs2, vl); return __riscv_vfnmacc_vf_f32mf2_m(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmacc_vv_f32m1_m // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmacc_vv_f32m1_m
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmacc.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmacc.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfnmacc_vv_f32m1_m(vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) { vfloat32m1_t test_vfnmacc_vv_f32m1_m(vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfnmacc_vv_f32m1_m(mask, vd, vs1, vs2, vl); return __riscv_vfnmacc_vv_f32m1_m(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmacc_vf_f32m1_m // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmacc_vf_f32m1_m
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmacc.mask.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmacc.mask.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfnmacc_vf_f32m1_m(vbool32_t mask, vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) { vfloat32m1_t test_vfnmacc_vf_f32m1_m(vbool32_t mask, vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfnmacc_vf_f32m1_m(mask, vd, rs1, vs2, vl); return __riscv_vfnmacc_vf_f32m1_m(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmacc_vv_f32m2_m // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmacc_vv_f32m2_m
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmacc.mask.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmacc.mask.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfnmacc_vv_f32m2_m(vbool16_t mask, vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) { vfloat32m2_t test_vfnmacc_vv_f32m2_m(vbool16_t mask, vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfnmacc_vv_f32m2_m(mask, vd, vs1, vs2, vl); return __riscv_vfnmacc_vv_f32m2_m(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmacc_vf_f32m2_m // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmacc_vf_f32m2_m
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmacc.mask.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmacc.mask.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfnmacc_vf_f32m2_m(vbool16_t mask, vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) { vfloat32m2_t test_vfnmacc_vf_f32m2_m(vbool16_t mask, vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfnmacc_vf_f32m2_m(mask, vd, rs1, vs2, vl); return __riscv_vfnmacc_vf_f32m2_m(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmacc_vv_f32m4_m // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmacc_vv_f32m4_m
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmacc.mask.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmacc.mask.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfnmacc_vv_f32m4_m(vbool8_t mask, vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) { vfloat32m4_t test_vfnmacc_vv_f32m4_m(vbool8_t mask, vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfnmacc_vv_f32m4_m(mask, vd, vs1, vs2, vl); return __riscv_vfnmacc_vv_f32m4_m(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmacc_vf_f32m4_m // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmacc_vf_f32m4_m
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmacc.mask.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmacc.mask.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfnmacc_vf_f32m4_m(vbool8_t mask, vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) { vfloat32m4_t test_vfnmacc_vf_f32m4_m(vbool8_t mask, vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfnmacc_vf_f32m4_m(mask, vd, rs1, vs2, vl); return __riscv_vfnmacc_vf_f32m4_m(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmacc_vv_f32m8_m // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmacc_vv_f32m8_m
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmacc.mask.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmacc.mask.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfnmacc_vv_f32m8_m(vbool4_t mask, vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) { vfloat32m8_t test_vfnmacc_vv_f32m8_m(vbool4_t mask, vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfnmacc_vv_f32m8_m(mask, vd, vs1, vs2, vl); return __riscv_vfnmacc_vv_f32m8_m(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmacc_vf_f32m8_m // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmacc_vf_f32m8_m
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmacc.mask.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmacc.mask.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfnmacc_vf_f32m8_m(vbool4_t mask, vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) { vfloat32m8_t test_vfnmacc_vf_f32m8_m(vbool4_t mask, vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfnmacc_vf_f32m8_m(mask, vd, rs1, vs2, vl); return __riscv_vfnmacc_vf_f32m8_m(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmacc_vv_f64m1_m // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmacc_vv_f64m1_m
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmacc.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmacc.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfnmacc_vv_f64m1_m(vbool64_t mask, vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) { vfloat64m1_t test_vfnmacc_vv_f64m1_m(vbool64_t mask, vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfnmacc_vv_f64m1_m(mask, vd, vs1, vs2, vl); return __riscv_vfnmacc_vv_f64m1_m(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmacc_vf_f64m1_m // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmacc_vf_f64m1_m
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmacc.mask.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmacc.mask.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfnmacc_vf_f64m1_m(vbool64_t mask, vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) { vfloat64m1_t test_vfnmacc_vf_f64m1_m(vbool64_t mask, vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfnmacc_vf_f64m1_m(mask, vd, rs1, vs2, vl); return __riscv_vfnmacc_vf_f64m1_m(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmacc_vv_f64m2_m // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmacc_vv_f64m2_m
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmacc.mask.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmacc.mask.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfnmacc_vv_f64m2_m(vbool32_t mask, vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) { vfloat64m2_t test_vfnmacc_vv_f64m2_m(vbool32_t mask, vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfnmacc_vv_f64m2_m(mask, vd, vs1, vs2, vl); return __riscv_vfnmacc_vv_f64m2_m(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmacc_vf_f64m2_m // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmacc_vf_f64m2_m
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmacc.mask.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmacc.mask.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfnmacc_vf_f64m2_m(vbool32_t mask, vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) { vfloat64m2_t test_vfnmacc_vf_f64m2_m(vbool32_t mask, vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfnmacc_vf_f64m2_m(mask, vd, rs1, vs2, vl); return __riscv_vfnmacc_vf_f64m2_m(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmacc_vv_f64m4_m // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmacc_vv_f64m4_m
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmacc.mask.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmacc.mask.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfnmacc_vv_f64m4_m(vbool16_t mask, vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) { vfloat64m4_t test_vfnmacc_vv_f64m4_m(vbool16_t mask, vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfnmacc_vv_f64m4_m(mask, vd, vs1, vs2, vl); return __riscv_vfnmacc_vv_f64m4_m(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmacc_vf_f64m4_m // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmacc_vf_f64m4_m
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmacc.mask.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmacc.mask.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfnmacc_vf_f64m4_m(vbool16_t mask, vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) { vfloat64m4_t test_vfnmacc_vf_f64m4_m(vbool16_t mask, vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfnmacc_vf_f64m4_m(mask, vd, rs1, vs2, vl); return __riscv_vfnmacc_vf_f64m4_m(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmacc_vv_f64m8_m // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmacc_vv_f64m8_m
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmacc.mask.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmacc.mask.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfnmacc_vv_f64m8_m(vbool8_t mask, vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) { vfloat64m8_t test_vfnmacc_vv_f64m8_m(vbool8_t mask, vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfnmacc_vv_f64m8_m(mask, vd, vs1, vs2, vl); return __riscv_vfnmacc_vv_f64m8_m(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmacc_vf_f64m8_m // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmacc_vf_f64m8_m
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmacc.mask.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmacc.mask.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfnmacc_vf_f64m8_m(vbool8_t mask, vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) { vfloat64m8_t test_vfnmacc_vf_f64m8_m(vbool8_t mask, vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfnmacc_vf_f64m8_m(mask, vd, rs1, vs2, vl); return __riscv_vfnmacc_vf_f64m8_m(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmacc_vv_f16mf4_rm
// CHECK-RV64-SAME: (<vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmacc.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
//
vfloat16mf4_t test_vfnmacc_vv_f16mf4_rm(vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfnmacc_vv_f16mf4_rm(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmacc_vf_f16mf4_rm
// CHECK-RV64-SAME: (<vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmacc.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
//
vfloat16mf4_t test_vfnmacc_vf_f16mf4_rm(vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfnmacc_vf_f16mf4_rm(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmacc_vv_f16mf2_rm
// CHECK-RV64-SAME: (<vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmacc.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
//
vfloat16mf2_t test_vfnmacc_vv_f16mf2_rm(vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfnmacc_vv_f16mf2_rm(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmacc_vf_f16mf2_rm
// CHECK-RV64-SAME: (<vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmacc.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
//
vfloat16mf2_t test_vfnmacc_vf_f16mf2_rm(vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfnmacc_vf_f16mf2_rm(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmacc_vv_f16m1_rm
// CHECK-RV64-SAME: (<vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmacc.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfnmacc_vv_f16m1_rm(vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfnmacc_vv_f16m1_rm(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmacc_vf_f16m1_rm
// CHECK-RV64-SAME: (<vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmacc.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfnmacc_vf_f16m1_rm(vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfnmacc_vf_f16m1_rm(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmacc_vv_f16m2_rm
// CHECK-RV64-SAME: (<vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmacc.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
//
vfloat16m2_t test_vfnmacc_vv_f16m2_rm(vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfnmacc_vv_f16m2_rm(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmacc_vf_f16m2_rm
// CHECK-RV64-SAME: (<vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmacc.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
//
vfloat16m2_t test_vfnmacc_vf_f16m2_rm(vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfnmacc_vf_f16m2_rm(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmacc_vv_f16m4_rm
// CHECK-RV64-SAME: (<vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmacc.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
//
vfloat16m4_t test_vfnmacc_vv_f16m4_rm(vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfnmacc_vv_f16m4_rm(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmacc_vf_f16m4_rm
// CHECK-RV64-SAME: (<vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmacc.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
//
vfloat16m4_t test_vfnmacc_vf_f16m4_rm(vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfnmacc_vf_f16m4_rm(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmacc_vv_f16m8_rm
// CHECK-RV64-SAME: (<vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmacc.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
//
vfloat16m8_t test_vfnmacc_vv_f16m8_rm(vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfnmacc_vv_f16m8_rm(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmacc_vf_f16m8_rm
// CHECK-RV64-SAME: (<vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmacc.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
//
vfloat16m8_t test_vfnmacc_vf_f16m8_rm(vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfnmacc_vf_f16m8_rm(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmacc_vv_f32mf2_rm
// CHECK-RV64-SAME: (<vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmacc.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
//
vfloat32mf2_t test_vfnmacc_vv_f32mf2_rm(vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfnmacc_vv_f32mf2_rm(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmacc_vf_f32mf2_rm
// CHECK-RV64-SAME: (<vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmacc.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
//
vfloat32mf2_t test_vfnmacc_vf_f32mf2_rm(vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfnmacc_vf_f32mf2_rm(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmacc_vv_f32m1_rm
// CHECK-RV64-SAME: (<vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmacc.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfnmacc_vv_f32m1_rm(vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfnmacc_vv_f32m1_rm(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmacc_vf_f32m1_rm
// CHECK-RV64-SAME: (<vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmacc.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfnmacc_vf_f32m1_rm(vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfnmacc_vf_f32m1_rm(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmacc_vv_f32m2_rm
// CHECK-RV64-SAME: (<vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmacc.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
//
vfloat32m2_t test_vfnmacc_vv_f32m2_rm(vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfnmacc_vv_f32m2_rm(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmacc_vf_f32m2_rm
// CHECK-RV64-SAME: (<vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmacc.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
//
vfloat32m2_t test_vfnmacc_vf_f32m2_rm(vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfnmacc_vf_f32m2_rm(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmacc_vv_f32m4_rm
// CHECK-RV64-SAME: (<vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmacc.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
//
vfloat32m4_t test_vfnmacc_vv_f32m4_rm(vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfnmacc_vv_f32m4_rm(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmacc_vf_f32m4_rm
// CHECK-RV64-SAME: (<vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmacc.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
//
vfloat32m4_t test_vfnmacc_vf_f32m4_rm(vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfnmacc_vf_f32m4_rm(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmacc_vv_f32m8_rm
// CHECK-RV64-SAME: (<vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmacc.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
//
vfloat32m8_t test_vfnmacc_vv_f32m8_rm(vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfnmacc_vv_f32m8_rm(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmacc_vf_f32m8_rm
// CHECK-RV64-SAME: (<vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmacc.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
//
vfloat32m8_t test_vfnmacc_vf_f32m8_rm(vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfnmacc_vf_f32m8_rm(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmacc_vv_f64m1_rm
// CHECK-RV64-SAME: (<vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmacc.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfnmacc_vv_f64m1_rm(vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfnmacc_vv_f64m1_rm(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmacc_vf_f64m1_rm
// CHECK-RV64-SAME: (<vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmacc.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfnmacc_vf_f64m1_rm(vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfnmacc_vf_f64m1_rm(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmacc_vv_f64m2_rm
// CHECK-RV64-SAME: (<vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmacc.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
//
vfloat64m2_t test_vfnmacc_vv_f64m2_rm(vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfnmacc_vv_f64m2_rm(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmacc_vf_f64m2_rm
// CHECK-RV64-SAME: (<vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmacc.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
//
vfloat64m2_t test_vfnmacc_vf_f64m2_rm(vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfnmacc_vf_f64m2_rm(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmacc_vv_f64m4_rm
// CHECK-RV64-SAME: (<vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmacc.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
//
vfloat64m4_t test_vfnmacc_vv_f64m4_rm(vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfnmacc_vv_f64m4_rm(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmacc_vf_f64m4_rm
// CHECK-RV64-SAME: (<vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmacc.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
//
vfloat64m4_t test_vfnmacc_vf_f64m4_rm(vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfnmacc_vf_f64m4_rm(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmacc_vv_f64m8_rm
// CHECK-RV64-SAME: (<vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmacc.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
//
vfloat64m8_t test_vfnmacc_vv_f64m8_rm(vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfnmacc_vv_f64m8_rm(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmacc_vf_f64m8_rm
// CHECK-RV64-SAME: (<vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmacc.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
//
vfloat64m8_t test_vfnmacc_vf_f64m8_rm(vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfnmacc_vf_f64m8_rm(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmacc_vv_f16mf4_rm_m
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmacc.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
//
vfloat16mf4_t test_vfnmacc_vv_f16mf4_rm_m(vbool64_t mask, vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfnmacc_vv_f16mf4_rm_m(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmacc_vf_f16mf4_rm_m
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmacc.mask.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
//
vfloat16mf4_t test_vfnmacc_vf_f16mf4_rm_m(vbool64_t mask, vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfnmacc_vf_f16mf4_rm_m(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmacc_vv_f16mf2_rm_m
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmacc.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
//
vfloat16mf2_t test_vfnmacc_vv_f16mf2_rm_m(vbool32_t mask, vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfnmacc_vv_f16mf2_rm_m(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmacc_vf_f16mf2_rm_m
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmacc.mask.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
//
vfloat16mf2_t test_vfnmacc_vf_f16mf2_rm_m(vbool32_t mask, vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfnmacc_vf_f16mf2_rm_m(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmacc_vv_f16m1_rm_m
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmacc.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfnmacc_vv_f16m1_rm_m(vbool16_t mask, vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfnmacc_vv_f16m1_rm_m(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmacc_vf_f16m1_rm_m
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmacc.mask.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfnmacc_vf_f16m1_rm_m(vbool16_t mask, vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfnmacc_vf_f16m1_rm_m(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmacc_vv_f16m2_rm_m
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmacc.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
//
vfloat16m2_t test_vfnmacc_vv_f16m2_rm_m(vbool8_t mask, vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfnmacc_vv_f16m2_rm_m(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmacc_vf_f16m2_rm_m
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmacc.mask.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
//
vfloat16m2_t test_vfnmacc_vf_f16m2_rm_m(vbool8_t mask, vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfnmacc_vf_f16m2_rm_m(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmacc_vv_f16m4_rm_m
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmacc.mask.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
//
vfloat16m4_t test_vfnmacc_vv_f16m4_rm_m(vbool4_t mask, vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfnmacc_vv_f16m4_rm_m(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmacc_vf_f16m4_rm_m
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmacc.mask.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
//
vfloat16m4_t test_vfnmacc_vf_f16m4_rm_m(vbool4_t mask, vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfnmacc_vf_f16m4_rm_m(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmacc_vv_f16m8_rm_m
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmacc.mask.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
//
vfloat16m8_t test_vfnmacc_vv_f16m8_rm_m(vbool2_t mask, vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfnmacc_vv_f16m8_rm_m(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmacc_vf_f16m8_rm_m
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmacc.mask.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
//
vfloat16m8_t test_vfnmacc_vf_f16m8_rm_m(vbool2_t mask, vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfnmacc_vf_f16m8_rm_m(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmacc_vv_f32mf2_rm_m
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmacc.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
//
vfloat32mf2_t test_vfnmacc_vv_f32mf2_rm_m(vbool64_t mask, vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfnmacc_vv_f32mf2_rm_m(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmacc_vf_f32mf2_rm_m
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmacc.mask.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
//
vfloat32mf2_t test_vfnmacc_vf_f32mf2_rm_m(vbool64_t mask, vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfnmacc_vf_f32mf2_rm_m(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmacc_vv_f32m1_rm_m
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmacc.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfnmacc_vv_f32m1_rm_m(vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfnmacc_vv_f32m1_rm_m(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmacc_vf_f32m1_rm_m
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmacc.mask.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfnmacc_vf_f32m1_rm_m(vbool32_t mask, vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfnmacc_vf_f32m1_rm_m(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmacc_vv_f32m2_rm_m
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmacc.mask.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
//
vfloat32m2_t test_vfnmacc_vv_f32m2_rm_m(vbool16_t mask, vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfnmacc_vv_f32m2_rm_m(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmacc_vf_f32m2_rm_m
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmacc.mask.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
//
vfloat32m2_t test_vfnmacc_vf_f32m2_rm_m(vbool16_t mask, vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfnmacc_vf_f32m2_rm_m(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmacc_vv_f32m4_rm_m
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmacc.mask.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
//
vfloat32m4_t test_vfnmacc_vv_f32m4_rm_m(vbool8_t mask, vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfnmacc_vv_f32m4_rm_m(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmacc_vf_f32m4_rm_m
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmacc.mask.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
//
vfloat32m4_t test_vfnmacc_vf_f32m4_rm_m(vbool8_t mask, vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfnmacc_vf_f32m4_rm_m(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmacc_vv_f32m8_rm_m
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmacc.mask.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
//
vfloat32m8_t test_vfnmacc_vv_f32m8_rm_m(vbool4_t mask, vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfnmacc_vv_f32m8_rm_m(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmacc_vf_f32m8_rm_m
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmacc.mask.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
//
vfloat32m8_t test_vfnmacc_vf_f32m8_rm_m(vbool4_t mask, vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfnmacc_vf_f32m8_rm_m(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmacc_vv_f64m1_rm_m
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmacc.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfnmacc_vv_f64m1_rm_m(vbool64_t mask, vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfnmacc_vv_f64m1_rm_m(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmacc_vf_f64m1_rm_m
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmacc.mask.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfnmacc_vf_f64m1_rm_m(vbool64_t mask, vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfnmacc_vf_f64m1_rm_m(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmacc_vv_f64m2_rm_m
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmacc.mask.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
//
vfloat64m2_t test_vfnmacc_vv_f64m2_rm_m(vbool32_t mask, vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfnmacc_vv_f64m2_rm_m(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmacc_vf_f64m2_rm_m
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmacc.mask.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
//
vfloat64m2_t test_vfnmacc_vf_f64m2_rm_m(vbool32_t mask, vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfnmacc_vf_f64m2_rm_m(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmacc_vv_f64m4_rm_m
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmacc.mask.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
//
vfloat64m4_t test_vfnmacc_vv_f64m4_rm_m(vbool16_t mask, vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfnmacc_vv_f64m4_rm_m(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmacc_vf_f64m4_rm_m
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmacc.mask.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
//
vfloat64m4_t test_vfnmacc_vf_f64m4_rm_m(vbool16_t mask, vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfnmacc_vf_f64m4_rm_m(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmacc_vv_f64m8_rm_m
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmacc.mask.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
//
vfloat64m8_t test_vfnmacc_vv_f64m8_rm_m(vbool8_t mask, vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfnmacc_vv_f64m8_rm_m(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmacc_vf_f64m8_rm_m
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmacc.mask.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
//
vfloat64m8_t test_vfnmacc_vf_f64m8_rm_m(vbool8_t mask, vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfnmacc_vf_f64m8_rm_m(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}

clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmadd.c

// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target // REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh \ // RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh \
// RUN: -target-feature +experimental-zvfh -disable-O0-optnone \ // RUN: -target-feature +experimental-zvfh -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ // RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s // RUN: FileCheck --check-prefix=CHECK-RV64 %s
#include <riscv_vector.h> #include <riscv_vector.h>
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmadd_vv_f16mf4 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmadd_vv_f16mf4
// CHECK-RV64-SAME: (<vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK-RV64-SAME: (<vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmadd.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmadd.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
// //
vfloat16mf4_t test_vfnmadd_vv_f16mf4(vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) { vfloat16mf4_t test_vfnmadd_vv_f16mf4(vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfnmadd_vv_f16mf4(vd, vs1, vs2, vl); return __riscv_vfnmadd_vv_f16mf4(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmadd_vf_f16mf4 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmadd_vf_f16mf4
// CHECK-RV64-SAME: (<vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmadd.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmadd.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
// //
vfloat16mf4_t test_vfnmadd_vf_f16mf4(vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) { vfloat16mf4_t test_vfnmadd_vf_f16mf4(vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfnmadd_vf_f16mf4(vd, rs1, vs2, vl); return __riscv_vfnmadd_vf_f16mf4(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmadd_vv_f16mf2 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmadd_vv_f16mf2
// CHECK-RV64-SAME: (<vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmadd.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmadd.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
// //
vfloat16mf2_t test_vfnmadd_vv_f16mf2(vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) { vfloat16mf2_t test_vfnmadd_vv_f16mf2(vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfnmadd_vv_f16mf2(vd, vs1, vs2, vl); return __riscv_vfnmadd_vv_f16mf2(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmadd_vf_f16mf2 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmadd_vf_f16mf2
// CHECK-RV64-SAME: (<vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmadd.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmadd.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
// //
vfloat16mf2_t test_vfnmadd_vf_f16mf2(vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) { vfloat16mf2_t test_vfnmadd_vf_f16mf2(vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfnmadd_vf_f16mf2(vd, rs1, vs2, vl); return __riscv_vfnmadd_vf_f16mf2(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmadd_vv_f16m1 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmadd_vv_f16m1
// CHECK-RV64-SAME: (<vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmadd.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmadd.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
// //
vfloat16m1_t test_vfnmadd_vv_f16m1(vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) { vfloat16m1_t test_vfnmadd_vv_f16m1(vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfnmadd_vv_f16m1(vd, vs1, vs2, vl); return __riscv_vfnmadd_vv_f16m1(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmadd_vf_f16m1 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmadd_vf_f16m1
// CHECK-RV64-SAME: (<vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmadd.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmadd.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
// //
vfloat16m1_t test_vfnmadd_vf_f16m1(vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) { vfloat16m1_t test_vfnmadd_vf_f16m1(vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfnmadd_vf_f16m1(vd, rs1, vs2, vl); return __riscv_vfnmadd_vf_f16m1(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmadd_vv_f16m2 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmadd_vv_f16m2
// CHECK-RV64-SAME: (<vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmadd.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmadd.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
// //
vfloat16m2_t test_vfnmadd_vv_f16m2(vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) { vfloat16m2_t test_vfnmadd_vv_f16m2(vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfnmadd_vv_f16m2(vd, vs1, vs2, vl); return __riscv_vfnmadd_vv_f16m2(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmadd_vf_f16m2 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmadd_vf_f16m2
// CHECK-RV64-SAME: (<vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmadd.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmadd.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
// //
vfloat16m2_t test_vfnmadd_vf_f16m2(vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) { vfloat16m2_t test_vfnmadd_vf_f16m2(vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfnmadd_vf_f16m2(vd, rs1, vs2, vl); return __riscv_vfnmadd_vf_f16m2(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmadd_vv_f16m4 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmadd_vv_f16m4
// CHECK-RV64-SAME: (<vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmadd.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmadd.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
// //
vfloat16m4_t test_vfnmadd_vv_f16m4(vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) { vfloat16m4_t test_vfnmadd_vv_f16m4(vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfnmadd_vv_f16m4(vd, vs1, vs2, vl); return __riscv_vfnmadd_vv_f16m4(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmadd_vf_f16m4 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmadd_vf_f16m4
// CHECK-RV64-SAME: (<vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmadd.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmadd.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
// //
vfloat16m4_t test_vfnmadd_vf_f16m4(vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) { vfloat16m4_t test_vfnmadd_vf_f16m4(vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfnmadd_vf_f16m4(vd, rs1, vs2, vl); return __riscv_vfnmadd_vf_f16m4(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmadd_vv_f16m8 // CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmadd_vv_f16m8
// CHECK-RV64-SAME: (<vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmadd.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmadd.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
// //
vfloat16m8_t test_vfnmadd_vv_f16m8(vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) { vfloat16m8_t test_vfnmadd_vv_f16m8(vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfnmadd_vv_f16m8(vd, vs1, vs2, vl); return __riscv_vfnmadd_vv_f16m8(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmadd_vf_f16m8 // CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmadd_vf_f16m8
// CHECK-RV64-SAME: (<vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmadd.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmadd.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
// //
vfloat16m8_t test_vfnmadd_vf_f16m8(vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) { vfloat16m8_t test_vfnmadd_vf_f16m8(vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfnmadd_vf_f16m8(vd, rs1, vs2, vl); return __riscv_vfnmadd_vf_f16m8(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmadd_vv_f32mf2 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmadd_vv_f32mf2
// CHECK-RV64-SAME: (<vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmadd.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmadd.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfnmadd_vv_f32mf2(vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) { vfloat32mf2_t test_vfnmadd_vv_f32mf2(vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfnmadd_vv_f32mf2(vd, vs1, vs2, vl); return __riscv_vfnmadd_vv_f32mf2(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmadd_vf_f32mf2 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmadd_vf_f32mf2
// CHECK-RV64-SAME: (<vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmadd.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmadd.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfnmadd_vf_f32mf2(vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) { vfloat32mf2_t test_vfnmadd_vf_f32mf2(vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfnmadd_vf_f32mf2(vd, rs1, vs2, vl); return __riscv_vfnmadd_vf_f32mf2(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmadd_vv_f32m1 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmadd_vv_f32m1
// CHECK-RV64-SAME: (<vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmadd.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmadd.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfnmadd_vv_f32m1(vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) { vfloat32m1_t test_vfnmadd_vv_f32m1(vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfnmadd_vv_f32m1(vd, vs1, vs2, vl); return __riscv_vfnmadd_vv_f32m1(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmadd_vf_f32m1 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmadd_vf_f32m1
// CHECK-RV64-SAME: (<vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmadd.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmadd.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfnmadd_vf_f32m1(vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) { vfloat32m1_t test_vfnmadd_vf_f32m1(vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfnmadd_vf_f32m1(vd, rs1, vs2, vl); return __riscv_vfnmadd_vf_f32m1(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmadd_vv_f32m2 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmadd_vv_f32m2
// CHECK-RV64-SAME: (<vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmadd.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmadd.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfnmadd_vv_f32m2(vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) { vfloat32m2_t test_vfnmadd_vv_f32m2(vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfnmadd_vv_f32m2(vd, vs1, vs2, vl); return __riscv_vfnmadd_vv_f32m2(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmadd_vf_f32m2 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmadd_vf_f32m2
// CHECK-RV64-SAME: (<vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmadd.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmadd.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfnmadd_vf_f32m2(vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) { vfloat32m2_t test_vfnmadd_vf_f32m2(vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfnmadd_vf_f32m2(vd, rs1, vs2, vl); return __riscv_vfnmadd_vf_f32m2(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmadd_vv_f32m4 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmadd_vv_f32m4
// CHECK-RV64-SAME: (<vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmadd.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmadd.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfnmadd_vv_f32m4(vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) { vfloat32m4_t test_vfnmadd_vv_f32m4(vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfnmadd_vv_f32m4(vd, vs1, vs2, vl); return __riscv_vfnmadd_vv_f32m4(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmadd_vf_f32m4 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmadd_vf_f32m4
// CHECK-RV64-SAME: (<vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmadd.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmadd.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfnmadd_vf_f32m4(vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) { vfloat32m4_t test_vfnmadd_vf_f32m4(vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfnmadd_vf_f32m4(vd, rs1, vs2, vl); return __riscv_vfnmadd_vf_f32m4(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmadd_vv_f32m8 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmadd_vv_f32m8
// CHECK-RV64-SAME: (<vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmadd.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmadd.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfnmadd_vv_f32m8(vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) { vfloat32m8_t test_vfnmadd_vv_f32m8(vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfnmadd_vv_f32m8(vd, vs1, vs2, vl); return __riscv_vfnmadd_vv_f32m8(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmadd_vf_f32m8 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmadd_vf_f32m8
// CHECK-RV64-SAME: (<vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmadd.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmadd.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfnmadd_vf_f32m8(vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) { vfloat32m8_t test_vfnmadd_vf_f32m8(vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfnmadd_vf_f32m8(vd, rs1, vs2, vl); return __riscv_vfnmadd_vf_f32m8(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmadd_vv_f64m1 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmadd_vv_f64m1
// CHECK-RV64-SAME: (<vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmadd.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmadd.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfnmadd_vv_f64m1(vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) { vfloat64m1_t test_vfnmadd_vv_f64m1(vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfnmadd_vv_f64m1(vd, vs1, vs2, vl); return __riscv_vfnmadd_vv_f64m1(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmadd_vf_f64m1 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmadd_vf_f64m1
// CHECK-RV64-SAME: (<vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmadd.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmadd.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfnmadd_vf_f64m1(vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) { vfloat64m1_t test_vfnmadd_vf_f64m1(vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfnmadd_vf_f64m1(vd, rs1, vs2, vl); return __riscv_vfnmadd_vf_f64m1(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmadd_vv_f64m2 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmadd_vv_f64m2
// CHECK-RV64-SAME: (<vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmadd.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmadd.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfnmadd_vv_f64m2(vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) { vfloat64m2_t test_vfnmadd_vv_f64m2(vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfnmadd_vv_f64m2(vd, vs1, vs2, vl); return __riscv_vfnmadd_vv_f64m2(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmadd_vf_f64m2 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmadd_vf_f64m2
// CHECK-RV64-SAME: (<vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmadd.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmadd.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfnmadd_vf_f64m2(vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) { vfloat64m2_t test_vfnmadd_vf_f64m2(vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfnmadd_vf_f64m2(vd, rs1, vs2, vl); return __riscv_vfnmadd_vf_f64m2(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmadd_vv_f64m4 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmadd_vv_f64m4
// CHECK-RV64-SAME: (<vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmadd.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmadd.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfnmadd_vv_f64m4(vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) { vfloat64m4_t test_vfnmadd_vv_f64m4(vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfnmadd_vv_f64m4(vd, vs1, vs2, vl); return __riscv_vfnmadd_vv_f64m4(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmadd_vf_f64m4 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmadd_vf_f64m4
// CHECK-RV64-SAME: (<vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmadd.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmadd.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfnmadd_vf_f64m4(vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) { vfloat64m4_t test_vfnmadd_vf_f64m4(vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfnmadd_vf_f64m4(vd, rs1, vs2, vl); return __riscv_vfnmadd_vf_f64m4(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmadd_vv_f64m8 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmadd_vv_f64m8
// CHECK-RV64-SAME: (<vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmadd.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmadd.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfnmadd_vv_f64m8(vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) { vfloat64m8_t test_vfnmadd_vv_f64m8(vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfnmadd_vv_f64m8(vd, vs1, vs2, vl); return __riscv_vfnmadd_vv_f64m8(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmadd_vf_f64m8 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmadd_vf_f64m8
// CHECK-RV64-SAME: (<vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmadd.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmadd.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfnmadd_vf_f64m8(vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) { vfloat64m8_t test_vfnmadd_vf_f64m8(vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfnmadd_vf_f64m8(vd, rs1, vs2, vl); return __riscv_vfnmadd_vf_f64m8(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmadd_vv_f16mf4_m // CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmadd_vv_f16mf4_m
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmadd.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmadd.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
// //
vfloat16mf4_t test_vfnmadd_vv_f16mf4_m(vbool64_t mask, vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) { vfloat16mf4_t test_vfnmadd_vv_f16mf4_m(vbool64_t mask, vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfnmadd_vv_f16mf4_m(mask, vd, vs1, vs2, vl); return __riscv_vfnmadd_vv_f16mf4_m(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmadd_vf_f16mf4_m // CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmadd_vf_f16mf4_m
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmadd.mask.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmadd.mask.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
// //
vfloat16mf4_t test_vfnmadd_vf_f16mf4_m(vbool64_t mask, vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) { vfloat16mf4_t test_vfnmadd_vf_f16mf4_m(vbool64_t mask, vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfnmadd_vf_f16mf4_m(mask, vd, rs1, vs2, vl); return __riscv_vfnmadd_vf_f16mf4_m(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmadd_vv_f16mf2_m // CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmadd_vv_f16mf2_m
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmadd.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmadd.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
// //
vfloat16mf2_t test_vfnmadd_vv_f16mf2_m(vbool32_t mask, vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) { vfloat16mf2_t test_vfnmadd_vv_f16mf2_m(vbool32_t mask, vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfnmadd_vv_f16mf2_m(mask, vd, vs1, vs2, vl); return __riscv_vfnmadd_vv_f16mf2_m(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmadd_vf_f16mf2_m // CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmadd_vf_f16mf2_m
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmadd.mask.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmadd.mask.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
// //
vfloat16mf2_t test_vfnmadd_vf_f16mf2_m(vbool32_t mask, vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) { vfloat16mf2_t test_vfnmadd_vf_f16mf2_m(vbool32_t mask, vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfnmadd_vf_f16mf2_m(mask, vd, rs1, vs2, vl); return __riscv_vfnmadd_vf_f16mf2_m(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmadd_vv_f16m1_m // CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmadd_vv_f16m1_m
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmadd.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmadd.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
// //
vfloat16m1_t test_vfnmadd_vv_f16m1_m(vbool16_t mask, vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) { vfloat16m1_t test_vfnmadd_vv_f16m1_m(vbool16_t mask, vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfnmadd_vv_f16m1_m(mask, vd, vs1, vs2, vl); return __riscv_vfnmadd_vv_f16m1_m(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmadd_vf_f16m1_m // CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmadd_vf_f16m1_m
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmadd.mask.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmadd.mask.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
// //
vfloat16m1_t test_vfnmadd_vf_f16m1_m(vbool16_t mask, vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) { vfloat16m1_t test_vfnmadd_vf_f16m1_m(vbool16_t mask, vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfnmadd_vf_f16m1_m(mask, vd, rs1, vs2, vl); return __riscv_vfnmadd_vf_f16m1_m(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmadd_vv_f16m2_m // CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmadd_vv_f16m2_m
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmadd.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmadd.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
// //
vfloat16m2_t test_vfnmadd_vv_f16m2_m(vbool8_t mask, vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) { vfloat16m2_t test_vfnmadd_vv_f16m2_m(vbool8_t mask, vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfnmadd_vv_f16m2_m(mask, vd, vs1, vs2, vl); return __riscv_vfnmadd_vv_f16m2_m(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmadd_vf_f16m2_m // CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmadd_vf_f16m2_m
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmadd.mask.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmadd.mask.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
// //
vfloat16m2_t test_vfnmadd_vf_f16m2_m(vbool8_t mask, vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) { vfloat16m2_t test_vfnmadd_vf_f16m2_m(vbool8_t mask, vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfnmadd_vf_f16m2_m(mask, vd, rs1, vs2, vl); return __riscv_vfnmadd_vf_f16m2_m(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmadd_vv_f16m4_m // CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmadd_vv_f16m4_m
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmadd.mask.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmadd.mask.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
// //
vfloat16m4_t test_vfnmadd_vv_f16m4_m(vbool4_t mask, vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) { vfloat16m4_t test_vfnmadd_vv_f16m4_m(vbool4_t mask, vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfnmadd_vv_f16m4_m(mask, vd, vs1, vs2, vl); return __riscv_vfnmadd_vv_f16m4_m(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmadd_vf_f16m4_m // CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmadd_vf_f16m4_m
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmadd.mask.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmadd.mask.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
// //
vfloat16m4_t test_vfnmadd_vf_f16m4_m(vbool4_t mask, vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) { vfloat16m4_t test_vfnmadd_vf_f16m4_m(vbool4_t mask, vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfnmadd_vf_f16m4_m(mask, vd, rs1, vs2, vl); return __riscv_vfnmadd_vf_f16m4_m(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmadd_vv_f16m8_m // CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmadd_vv_f16m8_m
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmadd.mask.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmadd.mask.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
// //
vfloat16m8_t test_vfnmadd_vv_f16m8_m(vbool2_t mask, vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) { vfloat16m8_t test_vfnmadd_vv_f16m8_m(vbool2_t mask, vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfnmadd_vv_f16m8_m(mask, vd, vs1, vs2, vl); return __riscv_vfnmadd_vv_f16m8_m(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmadd_vf_f16m8_m // CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmadd_vf_f16m8_m
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmadd.mask.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmadd.mask.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
// //
vfloat16m8_t test_vfnmadd_vf_f16m8_m(vbool2_t mask, vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) { vfloat16m8_t test_vfnmadd_vf_f16m8_m(vbool2_t mask, vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfnmadd_vf_f16m8_m(mask, vd, rs1, vs2, vl); return __riscv_vfnmadd_vf_f16m8_m(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmadd_vv_f32mf2_m // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmadd_vv_f32mf2_m
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmadd.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmadd.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfnmadd_vv_f32mf2_m(vbool64_t mask, vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) { vfloat32mf2_t test_vfnmadd_vv_f32mf2_m(vbool64_t mask, vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfnmadd_vv_f32mf2_m(mask, vd, vs1, vs2, vl); return __riscv_vfnmadd_vv_f32mf2_m(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmadd_vf_f32mf2_m // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmadd_vf_f32mf2_m
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmadd.mask.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmadd.mask.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfnmadd_vf_f32mf2_m(vbool64_t mask, vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) { vfloat32mf2_t test_vfnmadd_vf_f32mf2_m(vbool64_t mask, vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfnmadd_vf_f32mf2_m(mask, vd, rs1, vs2, vl); return __riscv_vfnmadd_vf_f32mf2_m(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmadd_vv_f32m1_m // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmadd_vv_f32m1_m
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmadd.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmadd.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfnmadd_vv_f32m1_m(vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) { vfloat32m1_t test_vfnmadd_vv_f32m1_m(vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfnmadd_vv_f32m1_m(mask, vd, vs1, vs2, vl); return __riscv_vfnmadd_vv_f32m1_m(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmadd_vf_f32m1_m // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmadd_vf_f32m1_m
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmadd.mask.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmadd.mask.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfnmadd_vf_f32m1_m(vbool32_t mask, vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) { vfloat32m1_t test_vfnmadd_vf_f32m1_m(vbool32_t mask, vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfnmadd_vf_f32m1_m(mask, vd, rs1, vs2, vl); return __riscv_vfnmadd_vf_f32m1_m(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmadd_vv_f32m2_m // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmadd_vv_f32m2_m
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmadd.mask.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmadd.mask.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfnmadd_vv_f32m2_m(vbool16_t mask, vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) { vfloat32m2_t test_vfnmadd_vv_f32m2_m(vbool16_t mask, vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfnmadd_vv_f32m2_m(mask, vd, vs1, vs2, vl); return __riscv_vfnmadd_vv_f32m2_m(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmadd_vf_f32m2_m // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmadd_vf_f32m2_m
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmadd.mask.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmadd.mask.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfnmadd_vf_f32m2_m(vbool16_t mask, vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) { vfloat32m2_t test_vfnmadd_vf_f32m2_m(vbool16_t mask, vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfnmadd_vf_f32m2_m(mask, vd, rs1, vs2, vl); return __riscv_vfnmadd_vf_f32m2_m(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmadd_vv_f32m4_m // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmadd_vv_f32m4_m
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmadd.mask.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmadd.mask.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfnmadd_vv_f32m4_m(vbool8_t mask, vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) { vfloat32m4_t test_vfnmadd_vv_f32m4_m(vbool8_t mask, vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfnmadd_vv_f32m4_m(mask, vd, vs1, vs2, vl); return __riscv_vfnmadd_vv_f32m4_m(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmadd_vf_f32m4_m // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmadd_vf_f32m4_m
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmadd.mask.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmadd.mask.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfnmadd_vf_f32m4_m(vbool8_t mask, vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) { vfloat32m4_t test_vfnmadd_vf_f32m4_m(vbool8_t mask, vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfnmadd_vf_f32m4_m(mask, vd, rs1, vs2, vl); return __riscv_vfnmadd_vf_f32m4_m(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmadd_vv_f32m8_m // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmadd_vv_f32m8_m
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmadd.mask.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmadd.mask.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfnmadd_vv_f32m8_m(vbool4_t mask, vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) { vfloat32m8_t test_vfnmadd_vv_f32m8_m(vbool4_t mask, vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfnmadd_vv_f32m8_m(mask, vd, vs1, vs2, vl); return __riscv_vfnmadd_vv_f32m8_m(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmadd_vf_f32m8_m // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmadd_vf_f32m8_m
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmadd.mask.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmadd.mask.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfnmadd_vf_f32m8_m(vbool4_t mask, vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) { vfloat32m8_t test_vfnmadd_vf_f32m8_m(vbool4_t mask, vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfnmadd_vf_f32m8_m(mask, vd, rs1, vs2, vl); return __riscv_vfnmadd_vf_f32m8_m(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmadd_vv_f64m1_m // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmadd_vv_f64m1_m
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmadd.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmadd.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfnmadd_vv_f64m1_m(vbool64_t mask, vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) { vfloat64m1_t test_vfnmadd_vv_f64m1_m(vbool64_t mask, vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfnmadd_vv_f64m1_m(mask, vd, vs1, vs2, vl); return __riscv_vfnmadd_vv_f64m1_m(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmadd_vf_f64m1_m // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmadd_vf_f64m1_m
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmadd.mask.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmadd.mask.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfnmadd_vf_f64m1_m(vbool64_t mask, vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) { vfloat64m1_t test_vfnmadd_vf_f64m1_m(vbool64_t mask, vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfnmadd_vf_f64m1_m(mask, vd, rs1, vs2, vl); return __riscv_vfnmadd_vf_f64m1_m(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmadd_vv_f64m2_m // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmadd_vv_f64m2_m
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmadd.mask.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmadd.mask.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfnmadd_vv_f64m2_m(vbool32_t mask, vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) { vfloat64m2_t test_vfnmadd_vv_f64m2_m(vbool32_t mask, vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfnmadd_vv_f64m2_m(mask, vd, vs1, vs2, vl); return __riscv_vfnmadd_vv_f64m2_m(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmadd_vf_f64m2_m // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmadd_vf_f64m2_m
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmadd.mask.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmadd.mask.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfnmadd_vf_f64m2_m(vbool32_t mask, vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) { vfloat64m2_t test_vfnmadd_vf_f64m2_m(vbool32_t mask, vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfnmadd_vf_f64m2_m(mask, vd, rs1, vs2, vl); return __riscv_vfnmadd_vf_f64m2_m(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmadd_vv_f64m4_m // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmadd_vv_f64m4_m
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmadd.mask.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmadd.mask.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfnmadd_vv_f64m4_m(vbool16_t mask, vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) { vfloat64m4_t test_vfnmadd_vv_f64m4_m(vbool16_t mask, vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfnmadd_vv_f64m4_m(mask, vd, vs1, vs2, vl); return __riscv_vfnmadd_vv_f64m4_m(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmadd_vf_f64m4_m // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmadd_vf_f64m4_m
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmadd.mask.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmadd.mask.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfnmadd_vf_f64m4_m(vbool16_t mask, vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) { vfloat64m4_t test_vfnmadd_vf_f64m4_m(vbool16_t mask, vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfnmadd_vf_f64m4_m(mask, vd, rs1, vs2, vl); return __riscv_vfnmadd_vf_f64m4_m(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmadd_vv_f64m8_m // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmadd_vv_f64m8_m
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmadd.mask.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmadd.mask.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfnmadd_vv_f64m8_m(vbool8_t mask, vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) { vfloat64m8_t test_vfnmadd_vv_f64m8_m(vbool8_t mask, vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfnmadd_vv_f64m8_m(mask, vd, vs1, vs2, vl); return __riscv_vfnmadd_vv_f64m8_m(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmadd_vf_f64m8_m // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmadd_vf_f64m8_m
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmadd.mask.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmadd.mask.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfnmadd_vf_f64m8_m(vbool8_t mask, vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) { vfloat64m8_t test_vfnmadd_vf_f64m8_m(vbool8_t mask, vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfnmadd_vf_f64m8_m(mask, vd, rs1, vs2, vl); return __riscv_vfnmadd_vf_f64m8_m(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmadd_vv_f16mf4_rm
// CHECK-RV64-SAME: (<vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmadd.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
//
vfloat16mf4_t test_vfnmadd_vv_f16mf4_rm(vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfnmadd_vv_f16mf4_rm(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmadd_vf_f16mf4_rm
// CHECK-RV64-SAME: (<vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmadd.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
//
vfloat16mf4_t test_vfnmadd_vf_f16mf4_rm(vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfnmadd_vf_f16mf4_rm(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmadd_vv_f16mf2_rm
// CHECK-RV64-SAME: (<vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmadd.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
//
vfloat16mf2_t test_vfnmadd_vv_f16mf2_rm(vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfnmadd_vv_f16mf2_rm(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmadd_vf_f16mf2_rm
// CHECK-RV64-SAME: (<vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmadd.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
//
vfloat16mf2_t test_vfnmadd_vf_f16mf2_rm(vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfnmadd_vf_f16mf2_rm(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmadd_vv_f16m1_rm
// CHECK-RV64-SAME: (<vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmadd.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfnmadd_vv_f16m1_rm(vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfnmadd_vv_f16m1_rm(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmadd_vf_f16m1_rm
// CHECK-RV64-SAME: (<vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmadd.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfnmadd_vf_f16m1_rm(vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfnmadd_vf_f16m1_rm(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmadd_vv_f16m2_rm
// CHECK-RV64-SAME: (<vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmadd.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
//
vfloat16m2_t test_vfnmadd_vv_f16m2_rm(vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfnmadd_vv_f16m2_rm(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmadd_vf_f16m2_rm
// CHECK-RV64-SAME: (<vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmadd.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
//
vfloat16m2_t test_vfnmadd_vf_f16m2_rm(vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfnmadd_vf_f16m2_rm(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmadd_vv_f16m4_rm
// CHECK-RV64-SAME: (<vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmadd.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
//
vfloat16m4_t test_vfnmadd_vv_f16m4_rm(vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfnmadd_vv_f16m4_rm(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmadd_vf_f16m4_rm
// CHECK-RV64-SAME: (<vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmadd.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
//
vfloat16m4_t test_vfnmadd_vf_f16m4_rm(vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfnmadd_vf_f16m4_rm(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmadd_vv_f16m8_rm
// CHECK-RV64-SAME: (<vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmadd.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
//
vfloat16m8_t test_vfnmadd_vv_f16m8_rm(vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfnmadd_vv_f16m8_rm(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmadd_vf_f16m8_rm
// CHECK-RV64-SAME: (<vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmadd.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
//
vfloat16m8_t test_vfnmadd_vf_f16m8_rm(vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfnmadd_vf_f16m8_rm(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmadd_vv_f32mf2_rm
// CHECK-RV64-SAME: (<vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmadd.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
//
vfloat32mf2_t test_vfnmadd_vv_f32mf2_rm(vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfnmadd_vv_f32mf2_rm(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmadd_vf_f32mf2_rm
// CHECK-RV64-SAME: (<vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmadd.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
//
vfloat32mf2_t test_vfnmadd_vf_f32mf2_rm(vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfnmadd_vf_f32mf2_rm(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmadd_vv_f32m1_rm
// CHECK-RV64-SAME: (<vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmadd.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfnmadd_vv_f32m1_rm(vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfnmadd_vv_f32m1_rm(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmadd_vf_f32m1_rm
// CHECK-RV64-SAME: (<vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmadd.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfnmadd_vf_f32m1_rm(vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfnmadd_vf_f32m1_rm(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmadd_vv_f32m2_rm
// CHECK-RV64-SAME: (<vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmadd.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
//
vfloat32m2_t test_vfnmadd_vv_f32m2_rm(vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfnmadd_vv_f32m2_rm(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmadd_vf_f32m2_rm
// CHECK-RV64-SAME: (<vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmadd.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
//
vfloat32m2_t test_vfnmadd_vf_f32m2_rm(vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfnmadd_vf_f32m2_rm(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmadd_vv_f32m4_rm
// CHECK-RV64-SAME: (<vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmadd.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
//
vfloat32m4_t test_vfnmadd_vv_f32m4_rm(vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfnmadd_vv_f32m4_rm(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmadd_vf_f32m4_rm
// CHECK-RV64-SAME: (<vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmadd.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
//
vfloat32m4_t test_vfnmadd_vf_f32m4_rm(vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfnmadd_vf_f32m4_rm(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmadd_vv_f32m8_rm
// CHECK-RV64-SAME: (<vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmadd.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
//
vfloat32m8_t test_vfnmadd_vv_f32m8_rm(vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfnmadd_vv_f32m8_rm(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmadd_vf_f32m8_rm
// CHECK-RV64-SAME: (<vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmadd.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
//
vfloat32m8_t test_vfnmadd_vf_f32m8_rm(vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfnmadd_vf_f32m8_rm(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmadd_vv_f64m1_rm
// CHECK-RV64-SAME: (<vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmadd.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfnmadd_vv_f64m1_rm(vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfnmadd_vv_f64m1_rm(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmadd_vf_f64m1_rm
// CHECK-RV64-SAME: (<vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmadd.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfnmadd_vf_f64m1_rm(vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfnmadd_vf_f64m1_rm(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmadd_vv_f64m2_rm
// CHECK-RV64-SAME: (<vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmadd.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
//
vfloat64m2_t test_vfnmadd_vv_f64m2_rm(vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfnmadd_vv_f64m2_rm(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmadd_vf_f64m2_rm
// CHECK-RV64-SAME: (<vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmadd.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
//
vfloat64m2_t test_vfnmadd_vf_f64m2_rm(vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfnmadd_vf_f64m2_rm(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmadd_vv_f64m4_rm
// CHECK-RV64-SAME: (<vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmadd.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
//
vfloat64m4_t test_vfnmadd_vv_f64m4_rm(vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfnmadd_vv_f64m4_rm(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmadd_vf_f64m4_rm
// CHECK-RV64-SAME: (<vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmadd.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
//
vfloat64m4_t test_vfnmadd_vf_f64m4_rm(vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfnmadd_vf_f64m4_rm(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmadd_vv_f64m8_rm
// CHECK-RV64-SAME: (<vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmadd.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
//
vfloat64m8_t test_vfnmadd_vv_f64m8_rm(vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfnmadd_vv_f64m8_rm(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmadd_vf_f64m8_rm
// CHECK-RV64-SAME: (<vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmadd.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
//
vfloat64m8_t test_vfnmadd_vf_f64m8_rm(vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfnmadd_vf_f64m8_rm(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmadd_vv_f16mf4_rm_m
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmadd.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
//
vfloat16mf4_t test_vfnmadd_vv_f16mf4_rm_m(vbool64_t mask, vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfnmadd_vv_f16mf4_rm_m(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmadd_vf_f16mf4_rm_m
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmadd.mask.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
//
vfloat16mf4_t test_vfnmadd_vf_f16mf4_rm_m(vbool64_t mask, vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfnmadd_vf_f16mf4_rm_m(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmadd_vv_f16mf2_rm_m
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmadd.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
//
vfloat16mf2_t test_vfnmadd_vv_f16mf2_rm_m(vbool32_t mask, vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfnmadd_vv_f16mf2_rm_m(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmadd_vf_f16mf2_rm_m
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmadd.mask.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
//
vfloat16mf2_t test_vfnmadd_vf_f16mf2_rm_m(vbool32_t mask, vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfnmadd_vf_f16mf2_rm_m(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmadd_vv_f16m1_rm_m
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmadd.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfnmadd_vv_f16m1_rm_m(vbool16_t mask, vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfnmadd_vv_f16m1_rm_m(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmadd_vf_f16m1_rm_m
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmadd.mask.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfnmadd_vf_f16m1_rm_m(vbool16_t mask, vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfnmadd_vf_f16m1_rm_m(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmadd_vv_f16m2_rm_m
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmadd.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
//
vfloat16m2_t test_vfnmadd_vv_f16m2_rm_m(vbool8_t mask, vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfnmadd_vv_f16m2_rm_m(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmadd_vf_f16m2_rm_m
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmadd.mask.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
//
vfloat16m2_t test_vfnmadd_vf_f16m2_rm_m(vbool8_t mask, vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfnmadd_vf_f16m2_rm_m(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmadd_vv_f16m4_rm_m
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmadd.mask.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
//
vfloat16m4_t test_vfnmadd_vv_f16m4_rm_m(vbool4_t mask, vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfnmadd_vv_f16m4_rm_m(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmadd_vf_f16m4_rm_m
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmadd.mask.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
//
vfloat16m4_t test_vfnmadd_vf_f16m4_rm_m(vbool4_t mask, vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfnmadd_vf_f16m4_rm_m(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmadd_vv_f16m8_rm_m
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmadd.mask.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
//
vfloat16m8_t test_vfnmadd_vv_f16m8_rm_m(vbool2_t mask, vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfnmadd_vv_f16m8_rm_m(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmadd_vf_f16m8_rm_m
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmadd.mask.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
//
vfloat16m8_t test_vfnmadd_vf_f16m8_rm_m(vbool2_t mask, vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfnmadd_vf_f16m8_rm_m(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmadd_vv_f32mf2_rm_m
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmadd.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
//
vfloat32mf2_t test_vfnmadd_vv_f32mf2_rm_m(vbool64_t mask, vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfnmadd_vv_f32mf2_rm_m(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmadd_vf_f32mf2_rm_m
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmadd.mask.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
//
vfloat32mf2_t test_vfnmadd_vf_f32mf2_rm_m(vbool64_t mask, vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfnmadd_vf_f32mf2_rm_m(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmadd_vv_f32m1_rm_m
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmadd.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfnmadd_vv_f32m1_rm_m(vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfnmadd_vv_f32m1_rm_m(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmadd_vf_f32m1_rm_m
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmadd.mask.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfnmadd_vf_f32m1_rm_m(vbool32_t mask, vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfnmadd_vf_f32m1_rm_m(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmadd_vv_f32m2_rm_m
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmadd.mask.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
//
vfloat32m2_t test_vfnmadd_vv_f32m2_rm_m(vbool16_t mask, vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfnmadd_vv_f32m2_rm_m(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmadd_vf_f32m2_rm_m
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmadd.mask.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
//
vfloat32m2_t test_vfnmadd_vf_f32m2_rm_m(vbool16_t mask, vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfnmadd_vf_f32m2_rm_m(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmadd_vv_f32m4_rm_m
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmadd.mask.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
//
vfloat32m4_t test_vfnmadd_vv_f32m4_rm_m(vbool8_t mask, vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfnmadd_vv_f32m4_rm_m(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmadd_vf_f32m4_rm_m
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmadd.mask.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
//
vfloat32m4_t test_vfnmadd_vf_f32m4_rm_m(vbool8_t mask, vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfnmadd_vf_f32m4_rm_m(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmadd_vv_f32m8_rm_m
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmadd.mask.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
//
vfloat32m8_t test_vfnmadd_vv_f32m8_rm_m(vbool4_t mask, vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfnmadd_vv_f32m8_rm_m(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmadd_vf_f32m8_rm_m
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmadd.mask.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
//
vfloat32m8_t test_vfnmadd_vf_f32m8_rm_m(vbool4_t mask, vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfnmadd_vf_f32m8_rm_m(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmadd_vv_f64m1_rm_m
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmadd.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfnmadd_vv_f64m1_rm_m(vbool64_t mask, vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfnmadd_vv_f64m1_rm_m(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmadd_vf_f64m1_rm_m
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmadd.mask.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfnmadd_vf_f64m1_rm_m(vbool64_t mask, vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfnmadd_vf_f64m1_rm_m(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmadd_vv_f64m2_rm_m
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmadd.mask.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
//
vfloat64m2_t test_vfnmadd_vv_f64m2_rm_m(vbool32_t mask, vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfnmadd_vv_f64m2_rm_m(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmadd_vf_f64m2_rm_m
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmadd.mask.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
//
vfloat64m2_t test_vfnmadd_vf_f64m2_rm_m(vbool32_t mask, vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfnmadd_vf_f64m2_rm_m(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmadd_vv_f64m4_rm_m
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmadd.mask.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
//
vfloat64m4_t test_vfnmadd_vv_f64m4_rm_m(vbool16_t mask, vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfnmadd_vv_f64m4_rm_m(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmadd_vf_f64m4_rm_m
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmadd.mask.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
//
vfloat64m4_t test_vfnmadd_vf_f64m4_rm_m(vbool16_t mask, vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfnmadd_vf_f64m4_rm_m(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmadd_vv_f64m8_rm_m
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmadd.mask.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
//
vfloat64m8_t test_vfnmadd_vv_f64m8_rm_m(vbool8_t mask, vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfnmadd_vv_f64m8_rm_m(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmadd_vf_f64m8_rm_m
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmadd.mask.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
//
vfloat64m8_t test_vfnmadd_vf_f64m8_rm_m(vbool8_t mask, vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfnmadd_vf_f64m8_rm_m(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}

clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmsac.c

// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target // REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh \ // RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh \
// RUN: -target-feature +experimental-zvfh -disable-O0-optnone \ // RUN: -target-feature +experimental-zvfh -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ // RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s // RUN: FileCheck --check-prefix=CHECK-RV64 %s
#include <riscv_vector.h> #include <riscv_vector.h>
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmsac_vv_f16mf4 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmsac_vv_f16mf4
// CHECK-RV64-SAME: (<vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK-RV64-SAME: (<vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmsac.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmsac.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
// //
vfloat16mf4_t test_vfnmsac_vv_f16mf4(vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) { vfloat16mf4_t test_vfnmsac_vv_f16mf4(vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfnmsac_vv_f16mf4(vd, vs1, vs2, vl); return __riscv_vfnmsac_vv_f16mf4(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmsac_vf_f16mf4 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmsac_vf_f16mf4
// CHECK-RV64-SAME: (<vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmsac.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmsac.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
// //
vfloat16mf4_t test_vfnmsac_vf_f16mf4(vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) { vfloat16mf4_t test_vfnmsac_vf_f16mf4(vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfnmsac_vf_f16mf4(vd, rs1, vs2, vl); return __riscv_vfnmsac_vf_f16mf4(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmsac_vv_f16mf2 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmsac_vv_f16mf2
// CHECK-RV64-SAME: (<vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmsac.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmsac.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
// //
vfloat16mf2_t test_vfnmsac_vv_f16mf2(vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) { vfloat16mf2_t test_vfnmsac_vv_f16mf2(vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfnmsac_vv_f16mf2(vd, vs1, vs2, vl); return __riscv_vfnmsac_vv_f16mf2(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmsac_vf_f16mf2 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmsac_vf_f16mf2
// CHECK-RV64-SAME: (<vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmsac.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmsac.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
// //
vfloat16mf2_t test_vfnmsac_vf_f16mf2(vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) { vfloat16mf2_t test_vfnmsac_vf_f16mf2(vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfnmsac_vf_f16mf2(vd, rs1, vs2, vl); return __riscv_vfnmsac_vf_f16mf2(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmsac_vv_f16m1 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmsac_vv_f16m1
// CHECK-RV64-SAME: (<vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmsac.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmsac.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
// //
vfloat16m1_t test_vfnmsac_vv_f16m1(vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) { vfloat16m1_t test_vfnmsac_vv_f16m1(vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfnmsac_vv_f16m1(vd, vs1, vs2, vl); return __riscv_vfnmsac_vv_f16m1(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmsac_vf_f16m1 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmsac_vf_f16m1
// CHECK-RV64-SAME: (<vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmsac.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmsac.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
// //
vfloat16m1_t test_vfnmsac_vf_f16m1(vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) { vfloat16m1_t test_vfnmsac_vf_f16m1(vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfnmsac_vf_f16m1(vd, rs1, vs2, vl); return __riscv_vfnmsac_vf_f16m1(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmsac_vv_f16m2 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmsac_vv_f16m2
// CHECK-RV64-SAME: (<vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmsac.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmsac.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
// //
vfloat16m2_t test_vfnmsac_vv_f16m2(vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) { vfloat16m2_t test_vfnmsac_vv_f16m2(vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfnmsac_vv_f16m2(vd, vs1, vs2, vl); return __riscv_vfnmsac_vv_f16m2(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmsac_vf_f16m2 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmsac_vf_f16m2
// CHECK-RV64-SAME: (<vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmsac.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmsac.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
// //
vfloat16m2_t test_vfnmsac_vf_f16m2(vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) { vfloat16m2_t test_vfnmsac_vf_f16m2(vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfnmsac_vf_f16m2(vd, rs1, vs2, vl); return __riscv_vfnmsac_vf_f16m2(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmsac_vv_f16m4 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmsac_vv_f16m4
// CHECK-RV64-SAME: (<vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmsac.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmsac.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
// //
vfloat16m4_t test_vfnmsac_vv_f16m4(vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) { vfloat16m4_t test_vfnmsac_vv_f16m4(vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfnmsac_vv_f16m4(vd, vs1, vs2, vl); return __riscv_vfnmsac_vv_f16m4(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmsac_vf_f16m4 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmsac_vf_f16m4
// CHECK-RV64-SAME: (<vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmsac.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmsac.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
// //
vfloat16m4_t test_vfnmsac_vf_f16m4(vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) { vfloat16m4_t test_vfnmsac_vf_f16m4(vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfnmsac_vf_f16m4(vd, rs1, vs2, vl); return __riscv_vfnmsac_vf_f16m4(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmsac_vv_f16m8 // CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmsac_vv_f16m8
// CHECK-RV64-SAME: (<vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmsac.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmsac.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
// //
vfloat16m8_t test_vfnmsac_vv_f16m8(vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) { vfloat16m8_t test_vfnmsac_vv_f16m8(vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfnmsac_vv_f16m8(vd, vs1, vs2, vl); return __riscv_vfnmsac_vv_f16m8(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmsac_vf_f16m8 // CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmsac_vf_f16m8
// CHECK-RV64-SAME: (<vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmsac.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmsac.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
// //
vfloat16m8_t test_vfnmsac_vf_f16m8(vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) { vfloat16m8_t test_vfnmsac_vf_f16m8(vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfnmsac_vf_f16m8(vd, rs1, vs2, vl); return __riscv_vfnmsac_vf_f16m8(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmsac_vv_f32mf2 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmsac_vv_f32mf2
// CHECK-RV64-SAME: (<vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmsac.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmsac.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfnmsac_vv_f32mf2(vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) { vfloat32mf2_t test_vfnmsac_vv_f32mf2(vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfnmsac_vv_f32mf2(vd, vs1, vs2, vl); return __riscv_vfnmsac_vv_f32mf2(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmsac_vf_f32mf2 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmsac_vf_f32mf2
// CHECK-RV64-SAME: (<vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmsac.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmsac.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfnmsac_vf_f32mf2(vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) { vfloat32mf2_t test_vfnmsac_vf_f32mf2(vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfnmsac_vf_f32mf2(vd, rs1, vs2, vl); return __riscv_vfnmsac_vf_f32mf2(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmsac_vv_f32m1 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmsac_vv_f32m1
// CHECK-RV64-SAME: (<vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmsac.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmsac.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfnmsac_vv_f32m1(vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) { vfloat32m1_t test_vfnmsac_vv_f32m1(vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfnmsac_vv_f32m1(vd, vs1, vs2, vl); return __riscv_vfnmsac_vv_f32m1(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmsac_vf_f32m1 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmsac_vf_f32m1
// CHECK-RV64-SAME: (<vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmsac.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmsac.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfnmsac_vf_f32m1(vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) { vfloat32m1_t test_vfnmsac_vf_f32m1(vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfnmsac_vf_f32m1(vd, rs1, vs2, vl); return __riscv_vfnmsac_vf_f32m1(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmsac_vv_f32m2 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmsac_vv_f32m2
// CHECK-RV64-SAME: (<vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmsac.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmsac.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfnmsac_vv_f32m2(vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) { vfloat32m2_t test_vfnmsac_vv_f32m2(vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfnmsac_vv_f32m2(vd, vs1, vs2, vl); return __riscv_vfnmsac_vv_f32m2(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmsac_vf_f32m2 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmsac_vf_f32m2
// CHECK-RV64-SAME: (<vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmsac.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmsac.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfnmsac_vf_f32m2(vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) { vfloat32m2_t test_vfnmsac_vf_f32m2(vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfnmsac_vf_f32m2(vd, rs1, vs2, vl); return __riscv_vfnmsac_vf_f32m2(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmsac_vv_f32m4 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmsac_vv_f32m4
// CHECK-RV64-SAME: (<vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmsac.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmsac.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfnmsac_vv_f32m4(vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) { vfloat32m4_t test_vfnmsac_vv_f32m4(vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfnmsac_vv_f32m4(vd, vs1, vs2, vl); return __riscv_vfnmsac_vv_f32m4(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmsac_vf_f32m4 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmsac_vf_f32m4
// CHECK-RV64-SAME: (<vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmsac.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmsac.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfnmsac_vf_f32m4(vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) { vfloat32m4_t test_vfnmsac_vf_f32m4(vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfnmsac_vf_f32m4(vd, rs1, vs2, vl); return __riscv_vfnmsac_vf_f32m4(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmsac_vv_f32m8 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmsac_vv_f32m8
// CHECK-RV64-SAME: (<vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmsac.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmsac.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfnmsac_vv_f32m8(vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) { vfloat32m8_t test_vfnmsac_vv_f32m8(vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfnmsac_vv_f32m8(vd, vs1, vs2, vl); return __riscv_vfnmsac_vv_f32m8(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmsac_vf_f32m8 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmsac_vf_f32m8
// CHECK-RV64-SAME: (<vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmsac.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmsac.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfnmsac_vf_f32m8(vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) { vfloat32m8_t test_vfnmsac_vf_f32m8(vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfnmsac_vf_f32m8(vd, rs1, vs2, vl); return __riscv_vfnmsac_vf_f32m8(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmsac_vv_f64m1 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmsac_vv_f64m1
// CHECK-RV64-SAME: (<vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmsac.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmsac.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfnmsac_vv_f64m1(vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) { vfloat64m1_t test_vfnmsac_vv_f64m1(vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfnmsac_vv_f64m1(vd, vs1, vs2, vl); return __riscv_vfnmsac_vv_f64m1(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmsac_vf_f64m1 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmsac_vf_f64m1
// CHECK-RV64-SAME: (<vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmsac.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmsac.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfnmsac_vf_f64m1(vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) { vfloat64m1_t test_vfnmsac_vf_f64m1(vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfnmsac_vf_f64m1(vd, rs1, vs2, vl); return __riscv_vfnmsac_vf_f64m1(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmsac_vv_f64m2 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmsac_vv_f64m2
// CHECK-RV64-SAME: (<vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmsac.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmsac.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfnmsac_vv_f64m2(vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) { vfloat64m2_t test_vfnmsac_vv_f64m2(vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfnmsac_vv_f64m2(vd, vs1, vs2, vl); return __riscv_vfnmsac_vv_f64m2(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmsac_vf_f64m2 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmsac_vf_f64m2
// CHECK-RV64-SAME: (<vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmsac.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmsac.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfnmsac_vf_f64m2(vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) { vfloat64m2_t test_vfnmsac_vf_f64m2(vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfnmsac_vf_f64m2(vd, rs1, vs2, vl); return __riscv_vfnmsac_vf_f64m2(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmsac_vv_f64m4 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmsac_vv_f64m4
// CHECK-RV64-SAME: (<vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmsac.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmsac.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfnmsac_vv_f64m4(vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) { vfloat64m4_t test_vfnmsac_vv_f64m4(vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfnmsac_vv_f64m4(vd, vs1, vs2, vl); return __riscv_vfnmsac_vv_f64m4(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmsac_vf_f64m4 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmsac_vf_f64m4
// CHECK-RV64-SAME: (<vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmsac.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmsac.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfnmsac_vf_f64m4(vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) { vfloat64m4_t test_vfnmsac_vf_f64m4(vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfnmsac_vf_f64m4(vd, rs1, vs2, vl); return __riscv_vfnmsac_vf_f64m4(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmsac_vv_f64m8 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmsac_vv_f64m8
// CHECK-RV64-SAME: (<vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmsac.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmsac.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfnmsac_vv_f64m8(vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) { vfloat64m8_t test_vfnmsac_vv_f64m8(vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfnmsac_vv_f64m8(vd, vs1, vs2, vl); return __riscv_vfnmsac_vv_f64m8(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmsac_vf_f64m8 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmsac_vf_f64m8
// CHECK-RV64-SAME: (<vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmsac.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmsac.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfnmsac_vf_f64m8(vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) { vfloat64m8_t test_vfnmsac_vf_f64m8(vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfnmsac_vf_f64m8(vd, rs1, vs2, vl); return __riscv_vfnmsac_vf_f64m8(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmsac_vv_f16mf4_m // CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmsac_vv_f16mf4_m
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmsac.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmsac.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
// //
vfloat16mf4_t test_vfnmsac_vv_f16mf4_m(vbool64_t mask, vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) { vfloat16mf4_t test_vfnmsac_vv_f16mf4_m(vbool64_t mask, vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfnmsac_vv_f16mf4_m(mask, vd, vs1, vs2, vl); return __riscv_vfnmsac_vv_f16mf4_m(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmsac_vf_f16mf4_m // CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmsac_vf_f16mf4_m
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmsac.mask.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmsac.mask.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
// //
vfloat16mf4_t test_vfnmsac_vf_f16mf4_m(vbool64_t mask, vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) { vfloat16mf4_t test_vfnmsac_vf_f16mf4_m(vbool64_t mask, vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfnmsac_vf_f16mf4_m(mask, vd, rs1, vs2, vl); return __riscv_vfnmsac_vf_f16mf4_m(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmsac_vv_f16mf2_m // CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmsac_vv_f16mf2_m
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmsac.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmsac.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
// //
vfloat16mf2_t test_vfnmsac_vv_f16mf2_m(vbool32_t mask, vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) { vfloat16mf2_t test_vfnmsac_vv_f16mf2_m(vbool32_t mask, vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfnmsac_vv_f16mf2_m(mask, vd, vs1, vs2, vl); return __riscv_vfnmsac_vv_f16mf2_m(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmsac_vf_f16mf2_m // CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmsac_vf_f16mf2_m
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmsac.mask.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmsac.mask.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
// //
vfloat16mf2_t test_vfnmsac_vf_f16mf2_m(vbool32_t mask, vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) { vfloat16mf2_t test_vfnmsac_vf_f16mf2_m(vbool32_t mask, vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfnmsac_vf_f16mf2_m(mask, vd, rs1, vs2, vl); return __riscv_vfnmsac_vf_f16mf2_m(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmsac_vv_f16m1_m // CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmsac_vv_f16m1_m
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmsac.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmsac.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
// //
vfloat16m1_t test_vfnmsac_vv_f16m1_m(vbool16_t mask, vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) { vfloat16m1_t test_vfnmsac_vv_f16m1_m(vbool16_t mask, vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfnmsac_vv_f16m1_m(mask, vd, vs1, vs2, vl); return __riscv_vfnmsac_vv_f16m1_m(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmsac_vf_f16m1_m // CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmsac_vf_f16m1_m
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmsac.mask.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmsac.mask.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
// //
vfloat16m1_t test_vfnmsac_vf_f16m1_m(vbool16_t mask, vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) { vfloat16m1_t test_vfnmsac_vf_f16m1_m(vbool16_t mask, vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfnmsac_vf_f16m1_m(mask, vd, rs1, vs2, vl); return __riscv_vfnmsac_vf_f16m1_m(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmsac_vv_f16m2_m // CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmsac_vv_f16m2_m
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmsac.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmsac.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
// //
vfloat16m2_t test_vfnmsac_vv_f16m2_m(vbool8_t mask, vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) { vfloat16m2_t test_vfnmsac_vv_f16m2_m(vbool8_t mask, vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfnmsac_vv_f16m2_m(mask, vd, vs1, vs2, vl); return __riscv_vfnmsac_vv_f16m2_m(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmsac_vf_f16m2_m // CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmsac_vf_f16m2_m
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmsac.mask.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmsac.mask.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
// //
vfloat16m2_t test_vfnmsac_vf_f16m2_m(vbool8_t mask, vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) { vfloat16m2_t test_vfnmsac_vf_f16m2_m(vbool8_t mask, vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfnmsac_vf_f16m2_m(mask, vd, rs1, vs2, vl); return __riscv_vfnmsac_vf_f16m2_m(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmsac_vv_f16m4_m // CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmsac_vv_f16m4_m
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmsac.mask.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmsac.mask.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
// //
vfloat16m4_t test_vfnmsac_vv_f16m4_m(vbool4_t mask, vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) { vfloat16m4_t test_vfnmsac_vv_f16m4_m(vbool4_t mask, vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfnmsac_vv_f16m4_m(mask, vd, vs1, vs2, vl); return __riscv_vfnmsac_vv_f16m4_m(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmsac_vf_f16m4_m // CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmsac_vf_f16m4_m
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmsac.mask.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmsac.mask.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
// //
vfloat16m4_t test_vfnmsac_vf_f16m4_m(vbool4_t mask, vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) { vfloat16m4_t test_vfnmsac_vf_f16m4_m(vbool4_t mask, vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfnmsac_vf_f16m4_m(mask, vd, rs1, vs2, vl); return __riscv_vfnmsac_vf_f16m4_m(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmsac_vv_f16m8_m // CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmsac_vv_f16m8_m
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmsac.mask.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmsac.mask.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
// //
vfloat16m8_t test_vfnmsac_vv_f16m8_m(vbool2_t mask, vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) { vfloat16m8_t test_vfnmsac_vv_f16m8_m(vbool2_t mask, vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfnmsac_vv_f16m8_m(mask, vd, vs1, vs2, vl); return __riscv_vfnmsac_vv_f16m8_m(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmsac_vf_f16m8_m // CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmsac_vf_f16m8_m
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmsac.mask.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmsac.mask.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
// //
vfloat16m8_t test_vfnmsac_vf_f16m8_m(vbool2_t mask, vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) { vfloat16m8_t test_vfnmsac_vf_f16m8_m(vbool2_t mask, vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfnmsac_vf_f16m8_m(mask, vd, rs1, vs2, vl); return __riscv_vfnmsac_vf_f16m8_m(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmsac_vv_f32mf2_m // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmsac_vv_f32mf2_m
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmsac.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmsac.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfnmsac_vv_f32mf2_m(vbool64_t mask, vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) { vfloat32mf2_t test_vfnmsac_vv_f32mf2_m(vbool64_t mask, vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfnmsac_vv_f32mf2_m(mask, vd, vs1, vs2, vl); return __riscv_vfnmsac_vv_f32mf2_m(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmsac_vf_f32mf2_m // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmsac_vf_f32mf2_m
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmsac.mask.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmsac.mask.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfnmsac_vf_f32mf2_m(vbool64_t mask, vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) { vfloat32mf2_t test_vfnmsac_vf_f32mf2_m(vbool64_t mask, vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfnmsac_vf_f32mf2_m(mask, vd, rs1, vs2, vl); return __riscv_vfnmsac_vf_f32mf2_m(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmsac_vv_f32m1_m // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmsac_vv_f32m1_m
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmsac.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmsac.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfnmsac_vv_f32m1_m(vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) { vfloat32m1_t test_vfnmsac_vv_f32m1_m(vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfnmsac_vv_f32m1_m(mask, vd, vs1, vs2, vl); return __riscv_vfnmsac_vv_f32m1_m(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmsac_vf_f32m1_m // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmsac_vf_f32m1_m
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmsac.mask.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmsac.mask.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfnmsac_vf_f32m1_m(vbool32_t mask, vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) { vfloat32m1_t test_vfnmsac_vf_f32m1_m(vbool32_t mask, vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfnmsac_vf_f32m1_m(mask, vd, rs1, vs2, vl); return __riscv_vfnmsac_vf_f32m1_m(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmsac_vv_f32m2_m // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmsac_vv_f32m2_m
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmsac.mask.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmsac.mask.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfnmsac_vv_f32m2_m(vbool16_t mask, vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) { vfloat32m2_t test_vfnmsac_vv_f32m2_m(vbool16_t mask, vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfnmsac_vv_f32m2_m(mask, vd, vs1, vs2, vl); return __riscv_vfnmsac_vv_f32m2_m(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmsac_vf_f32m2_m // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmsac_vf_f32m2_m
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmsac.mask.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmsac.mask.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfnmsac_vf_f32m2_m(vbool16_t mask, vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) { vfloat32m2_t test_vfnmsac_vf_f32m2_m(vbool16_t mask, vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfnmsac_vf_f32m2_m(mask, vd, rs1, vs2, vl); return __riscv_vfnmsac_vf_f32m2_m(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmsac_vv_f32m4_m // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmsac_vv_f32m4_m
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmsac.mask.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmsac.mask.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfnmsac_vv_f32m4_m(vbool8_t mask, vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) { vfloat32m4_t test_vfnmsac_vv_f32m4_m(vbool8_t mask, vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfnmsac_vv_f32m4_m(mask, vd, vs1, vs2, vl); return __riscv_vfnmsac_vv_f32m4_m(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmsac_vf_f32m4_m // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmsac_vf_f32m4_m
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmsac.mask.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmsac.mask.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfnmsac_vf_f32m4_m(vbool8_t mask, vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) { vfloat32m4_t test_vfnmsac_vf_f32m4_m(vbool8_t mask, vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfnmsac_vf_f32m4_m(mask, vd, rs1, vs2, vl); return __riscv_vfnmsac_vf_f32m4_m(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmsac_vv_f32m8_m // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmsac_vv_f32m8_m
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmsac.mask.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmsac.mask.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfnmsac_vv_f32m8_m(vbool4_t mask, vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) { vfloat32m8_t test_vfnmsac_vv_f32m8_m(vbool4_t mask, vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfnmsac_vv_f32m8_m(mask, vd, vs1, vs2, vl); return __riscv_vfnmsac_vv_f32m8_m(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmsac_vf_f32m8_m // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmsac_vf_f32m8_m
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmsac.mask.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmsac.mask.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfnmsac_vf_f32m8_m(vbool4_t mask, vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) { vfloat32m8_t test_vfnmsac_vf_f32m8_m(vbool4_t mask, vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfnmsac_vf_f32m8_m(mask, vd, rs1, vs2, vl); return __riscv_vfnmsac_vf_f32m8_m(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmsac_vv_f64m1_m // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmsac_vv_f64m1_m
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmsac.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmsac.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfnmsac_vv_f64m1_m(vbool64_t mask, vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) { vfloat64m1_t test_vfnmsac_vv_f64m1_m(vbool64_t mask, vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfnmsac_vv_f64m1_m(mask, vd, vs1, vs2, vl); return __riscv_vfnmsac_vv_f64m1_m(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmsac_vf_f64m1_m // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmsac_vf_f64m1_m
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmsac.mask.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmsac.mask.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfnmsac_vf_f64m1_m(vbool64_t mask, vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) { vfloat64m1_t test_vfnmsac_vf_f64m1_m(vbool64_t mask, vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfnmsac_vf_f64m1_m(mask, vd, rs1, vs2, vl); return __riscv_vfnmsac_vf_f64m1_m(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmsac_vv_f64m2_m // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmsac_vv_f64m2_m
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmsac.mask.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmsac.mask.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfnmsac_vv_f64m2_m(vbool32_t mask, vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) { vfloat64m2_t test_vfnmsac_vv_f64m2_m(vbool32_t mask, vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfnmsac_vv_f64m2_m(mask, vd, vs1, vs2, vl); return __riscv_vfnmsac_vv_f64m2_m(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmsac_vf_f64m2_m // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmsac_vf_f64m2_m
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmsac.mask.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmsac.mask.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfnmsac_vf_f64m2_m(vbool32_t mask, vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) { vfloat64m2_t test_vfnmsac_vf_f64m2_m(vbool32_t mask, vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfnmsac_vf_f64m2_m(mask, vd, rs1, vs2, vl); return __riscv_vfnmsac_vf_f64m2_m(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmsac_vv_f64m4_m // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmsac_vv_f64m4_m
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmsac.mask.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmsac.mask.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfnmsac_vv_f64m4_m(vbool16_t mask, vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) { vfloat64m4_t test_vfnmsac_vv_f64m4_m(vbool16_t mask, vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfnmsac_vv_f64m4_m(mask, vd, vs1, vs2, vl); return __riscv_vfnmsac_vv_f64m4_m(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmsac_vf_f64m4_m // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmsac_vf_f64m4_m
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmsac.mask.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmsac.mask.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfnmsac_vf_f64m4_m(vbool16_t mask, vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) { vfloat64m4_t test_vfnmsac_vf_f64m4_m(vbool16_t mask, vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfnmsac_vf_f64m4_m(mask, vd, rs1, vs2, vl); return __riscv_vfnmsac_vf_f64m4_m(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmsac_vv_f64m8_m // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmsac_vv_f64m8_m
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmsac.mask.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmsac.mask.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfnmsac_vv_f64m8_m(vbool8_t mask, vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) { vfloat64m8_t test_vfnmsac_vv_f64m8_m(vbool8_t mask, vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfnmsac_vv_f64m8_m(mask, vd, vs1, vs2, vl); return __riscv_vfnmsac_vv_f64m8_m(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmsac_vf_f64m8_m // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmsac_vf_f64m8_m
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmsac.mask.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmsac.mask.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfnmsac_vf_f64m8_m(vbool8_t mask, vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) { vfloat64m8_t test_vfnmsac_vf_f64m8_m(vbool8_t mask, vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfnmsac_vf_f64m8_m(mask, vd, rs1, vs2, vl); return __riscv_vfnmsac_vf_f64m8_m(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmsac_vv_f16mf4_rm
// CHECK-RV64-SAME: (<vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmsac.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
//
vfloat16mf4_t test_vfnmsac_vv_f16mf4_rm(vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfnmsac_vv_f16mf4_rm(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmsac_vf_f16mf4_rm
// CHECK-RV64-SAME: (<vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmsac.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
//
vfloat16mf4_t test_vfnmsac_vf_f16mf4_rm(vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfnmsac_vf_f16mf4_rm(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmsac_vv_f16mf2_rm
// CHECK-RV64-SAME: (<vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmsac.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
//
vfloat16mf2_t test_vfnmsac_vv_f16mf2_rm(vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfnmsac_vv_f16mf2_rm(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmsac_vf_f16mf2_rm
// CHECK-RV64-SAME: (<vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmsac.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
//
vfloat16mf2_t test_vfnmsac_vf_f16mf2_rm(vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfnmsac_vf_f16mf2_rm(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmsac_vv_f16m1_rm
// CHECK-RV64-SAME: (<vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmsac.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfnmsac_vv_f16m1_rm(vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfnmsac_vv_f16m1_rm(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmsac_vf_f16m1_rm
// CHECK-RV64-SAME: (<vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmsac.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfnmsac_vf_f16m1_rm(vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfnmsac_vf_f16m1_rm(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmsac_vv_f16m2_rm
// CHECK-RV64-SAME: (<vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmsac.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
//
vfloat16m2_t test_vfnmsac_vv_f16m2_rm(vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfnmsac_vv_f16m2_rm(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmsac_vf_f16m2_rm
// CHECK-RV64-SAME: (<vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmsac.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
//
vfloat16m2_t test_vfnmsac_vf_f16m2_rm(vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfnmsac_vf_f16m2_rm(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmsac_vv_f16m4_rm
// CHECK-RV64-SAME: (<vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmsac.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
//
vfloat16m4_t test_vfnmsac_vv_f16m4_rm(vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfnmsac_vv_f16m4_rm(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmsac_vf_f16m4_rm
// CHECK-RV64-SAME: (<vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmsac.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
//
vfloat16m4_t test_vfnmsac_vf_f16m4_rm(vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfnmsac_vf_f16m4_rm(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmsac_vv_f16m8_rm
// CHECK-RV64-SAME: (<vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmsac.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
//
vfloat16m8_t test_vfnmsac_vv_f16m8_rm(vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfnmsac_vv_f16m8_rm(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmsac_vf_f16m8_rm
// CHECK-RV64-SAME: (<vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmsac.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
//
vfloat16m8_t test_vfnmsac_vf_f16m8_rm(vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfnmsac_vf_f16m8_rm(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmsac_vv_f32mf2_rm
// CHECK-RV64-SAME: (<vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmsac.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
//
vfloat32mf2_t test_vfnmsac_vv_f32mf2_rm(vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfnmsac_vv_f32mf2_rm(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmsac_vf_f32mf2_rm
// CHECK-RV64-SAME: (<vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmsac.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
//
vfloat32mf2_t test_vfnmsac_vf_f32mf2_rm(vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfnmsac_vf_f32mf2_rm(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmsac_vv_f32m1_rm
// CHECK-RV64-SAME: (<vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmsac.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfnmsac_vv_f32m1_rm(vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfnmsac_vv_f32m1_rm(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmsac_vf_f32m1_rm
// CHECK-RV64-SAME: (<vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmsac.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfnmsac_vf_f32m1_rm(vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfnmsac_vf_f32m1_rm(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmsac_vv_f32m2_rm
// CHECK-RV64-SAME: (<vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmsac.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
//
vfloat32m2_t test_vfnmsac_vv_f32m2_rm(vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfnmsac_vv_f32m2_rm(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmsac_vf_f32m2_rm
// CHECK-RV64-SAME: (<vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmsac.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
//
vfloat32m2_t test_vfnmsac_vf_f32m2_rm(vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfnmsac_vf_f32m2_rm(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmsac_vv_f32m4_rm
// CHECK-RV64-SAME: (<vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmsac.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
//
vfloat32m4_t test_vfnmsac_vv_f32m4_rm(vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfnmsac_vv_f32m4_rm(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmsac_vf_f32m4_rm
// CHECK-RV64-SAME: (<vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmsac.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
//
vfloat32m4_t test_vfnmsac_vf_f32m4_rm(vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfnmsac_vf_f32m4_rm(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmsac_vv_f32m8_rm
// CHECK-RV64-SAME: (<vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmsac.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
//
vfloat32m8_t test_vfnmsac_vv_f32m8_rm(vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfnmsac_vv_f32m8_rm(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmsac_vf_f32m8_rm
// CHECK-RV64-SAME: (<vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmsac.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
//
vfloat32m8_t test_vfnmsac_vf_f32m8_rm(vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfnmsac_vf_f32m8_rm(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmsac_vv_f64m1_rm
// CHECK-RV64-SAME: (<vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmsac.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfnmsac_vv_f64m1_rm(vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfnmsac_vv_f64m1_rm(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmsac_vf_f64m1_rm
// CHECK-RV64-SAME: (<vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmsac.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfnmsac_vf_f64m1_rm(vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfnmsac_vf_f64m1_rm(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmsac_vv_f64m2_rm
// CHECK-RV64-SAME: (<vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmsac.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
//
vfloat64m2_t test_vfnmsac_vv_f64m2_rm(vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfnmsac_vv_f64m2_rm(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmsac_vf_f64m2_rm
// CHECK-RV64-SAME: (<vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmsac.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
//
vfloat64m2_t test_vfnmsac_vf_f64m2_rm(vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfnmsac_vf_f64m2_rm(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmsac_vv_f64m4_rm
// CHECK-RV64-SAME: (<vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmsac.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
//
vfloat64m4_t test_vfnmsac_vv_f64m4_rm(vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfnmsac_vv_f64m4_rm(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmsac_vf_f64m4_rm
// CHECK-RV64-SAME: (<vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmsac.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
//
vfloat64m4_t test_vfnmsac_vf_f64m4_rm(vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfnmsac_vf_f64m4_rm(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmsac_vv_f64m8_rm
// CHECK-RV64-SAME: (<vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmsac.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
//
vfloat64m8_t test_vfnmsac_vv_f64m8_rm(vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfnmsac_vv_f64m8_rm(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmsac_vf_f64m8_rm
// CHECK-RV64-SAME: (<vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmsac.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
//
vfloat64m8_t test_vfnmsac_vf_f64m8_rm(vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfnmsac_vf_f64m8_rm(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmsac_vv_f16mf4_rm_m
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmsac.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
//
vfloat16mf4_t test_vfnmsac_vv_f16mf4_rm_m(vbool64_t mask, vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfnmsac_vv_f16mf4_rm_m(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmsac_vf_f16mf4_rm_m
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmsac.mask.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
//
vfloat16mf4_t test_vfnmsac_vf_f16mf4_rm_m(vbool64_t mask, vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfnmsac_vf_f16mf4_rm_m(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmsac_vv_f16mf2_rm_m
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmsac.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
//
vfloat16mf2_t test_vfnmsac_vv_f16mf2_rm_m(vbool32_t mask, vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfnmsac_vv_f16mf2_rm_m(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmsac_vf_f16mf2_rm_m
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmsac.mask.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
//
vfloat16mf2_t test_vfnmsac_vf_f16mf2_rm_m(vbool32_t mask, vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfnmsac_vf_f16mf2_rm_m(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmsac_vv_f16m1_rm_m
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmsac.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfnmsac_vv_f16m1_rm_m(vbool16_t mask, vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfnmsac_vv_f16m1_rm_m(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmsac_vf_f16m1_rm_m
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmsac.mask.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfnmsac_vf_f16m1_rm_m(vbool16_t mask, vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfnmsac_vf_f16m1_rm_m(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmsac_vv_f16m2_rm_m
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmsac.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
//
vfloat16m2_t test_vfnmsac_vv_f16m2_rm_m(vbool8_t mask, vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfnmsac_vv_f16m2_rm_m(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmsac_vf_f16m2_rm_m
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmsac.mask.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
//
vfloat16m2_t test_vfnmsac_vf_f16m2_rm_m(vbool8_t mask, vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfnmsac_vf_f16m2_rm_m(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmsac_vv_f16m4_rm_m
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmsac.mask.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
//
vfloat16m4_t test_vfnmsac_vv_f16m4_rm_m(vbool4_t mask, vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfnmsac_vv_f16m4_rm_m(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmsac_vf_f16m4_rm_m
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmsac.mask.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
//
vfloat16m4_t test_vfnmsac_vf_f16m4_rm_m(vbool4_t mask, vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfnmsac_vf_f16m4_rm_m(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmsac_vv_f16m8_rm_m
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmsac.mask.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
//
vfloat16m8_t test_vfnmsac_vv_f16m8_rm_m(vbool2_t mask, vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfnmsac_vv_f16m8_rm_m(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmsac_vf_f16m8_rm_m
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmsac.mask.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
//
vfloat16m8_t test_vfnmsac_vf_f16m8_rm_m(vbool2_t mask, vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfnmsac_vf_f16m8_rm_m(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmsac_vv_f32mf2_rm_m
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmsac.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
//
vfloat32mf2_t test_vfnmsac_vv_f32mf2_rm_m(vbool64_t mask, vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfnmsac_vv_f32mf2_rm_m(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmsac_vf_f32mf2_rm_m
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmsac.mask.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
//
vfloat32mf2_t test_vfnmsac_vf_f32mf2_rm_m(vbool64_t mask, vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfnmsac_vf_f32mf2_rm_m(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmsac_vv_f32m1_rm_m
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmsac.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfnmsac_vv_f32m1_rm_m(vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfnmsac_vv_f32m1_rm_m(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmsac_vf_f32m1_rm_m
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmsac.mask.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfnmsac_vf_f32m1_rm_m(vbool32_t mask, vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfnmsac_vf_f32m1_rm_m(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmsac_vv_f32m2_rm_m
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmsac.mask.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
//
vfloat32m2_t test_vfnmsac_vv_f32m2_rm_m(vbool16_t mask, vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfnmsac_vv_f32m2_rm_m(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmsac_vf_f32m2_rm_m
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmsac.mask.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
//
vfloat32m2_t test_vfnmsac_vf_f32m2_rm_m(vbool16_t mask, vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfnmsac_vf_f32m2_rm_m(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmsac_vv_f32m4_rm_m
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmsac.mask.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
//
vfloat32m4_t test_vfnmsac_vv_f32m4_rm_m(vbool8_t mask, vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfnmsac_vv_f32m4_rm_m(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmsac_vf_f32m4_rm_m
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmsac.mask.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
//
vfloat32m4_t test_vfnmsac_vf_f32m4_rm_m(vbool8_t mask, vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfnmsac_vf_f32m4_rm_m(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmsac_vv_f32m8_rm_m
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmsac.mask.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
//
vfloat32m8_t test_vfnmsac_vv_f32m8_rm_m(vbool4_t mask, vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfnmsac_vv_f32m8_rm_m(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmsac_vf_f32m8_rm_m
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmsac.mask.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
//
vfloat32m8_t test_vfnmsac_vf_f32m8_rm_m(vbool4_t mask, vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfnmsac_vf_f32m8_rm_m(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmsac_vv_f64m1_rm_m
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmsac.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfnmsac_vv_f64m1_rm_m(vbool64_t mask, vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfnmsac_vv_f64m1_rm_m(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmsac_vf_f64m1_rm_m
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmsac.mask.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfnmsac_vf_f64m1_rm_m(vbool64_t mask, vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfnmsac_vf_f64m1_rm_m(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmsac_vv_f64m2_rm_m
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmsac.mask.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
//
vfloat64m2_t test_vfnmsac_vv_f64m2_rm_m(vbool32_t mask, vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfnmsac_vv_f64m2_rm_m(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmsac_vf_f64m2_rm_m
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmsac.mask.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
//
vfloat64m2_t test_vfnmsac_vf_f64m2_rm_m(vbool32_t mask, vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfnmsac_vf_f64m2_rm_m(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmsac_vv_f64m4_rm_m
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmsac.mask.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
//
vfloat64m4_t test_vfnmsac_vv_f64m4_rm_m(vbool16_t mask, vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfnmsac_vv_f64m4_rm_m(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmsac_vf_f64m4_rm_m
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmsac.mask.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
//
vfloat64m4_t test_vfnmsac_vf_f64m4_rm_m(vbool16_t mask, vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfnmsac_vf_f64m4_rm_m(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmsac_vv_f64m8_rm_m
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmsac.mask.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
//
vfloat64m8_t test_vfnmsac_vv_f64m8_rm_m(vbool8_t mask, vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfnmsac_vv_f64m8_rm_m(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmsac_vf_f64m8_rm_m
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmsac.mask.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
//
vfloat64m8_t test_vfnmsac_vf_f64m8_rm_m(vbool8_t mask, vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfnmsac_vf_f64m8_rm_m(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}

clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/vfnmsub.c

// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target // REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh \ // RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh \
// RUN: -target-feature +experimental-zvfh -disable-O0-optnone \ // RUN: -target-feature +experimental-zvfh -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ // RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s // RUN: FileCheck --check-prefix=CHECK-RV64 %s
#include <riscv_vector.h> #include <riscv_vector.h>
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmsub_vv_f16mf4 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmsub_vv_f16mf4
// CHECK-RV64-SAME: (<vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK-RV64-SAME: (<vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmsub.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmsub.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
// //
vfloat16mf4_t test_vfnmsub_vv_f16mf4(vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) { vfloat16mf4_t test_vfnmsub_vv_f16mf4(vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfnmsub_vv_f16mf4(vd, vs1, vs2, vl); return __riscv_vfnmsub_vv_f16mf4(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmsub_vf_f16mf4 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmsub_vf_f16mf4
// CHECK-RV64-SAME: (<vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmsub.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmsub.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
// //
vfloat16mf4_t test_vfnmsub_vf_f16mf4(vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) { vfloat16mf4_t test_vfnmsub_vf_f16mf4(vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfnmsub_vf_f16mf4(vd, rs1, vs2, vl); return __riscv_vfnmsub_vf_f16mf4(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmsub_vv_f16mf2 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmsub_vv_f16mf2
// CHECK-RV64-SAME: (<vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmsub.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmsub.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
// //
vfloat16mf2_t test_vfnmsub_vv_f16mf2(vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) { vfloat16mf2_t test_vfnmsub_vv_f16mf2(vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfnmsub_vv_f16mf2(vd, vs1, vs2, vl); return __riscv_vfnmsub_vv_f16mf2(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmsub_vf_f16mf2 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmsub_vf_f16mf2
// CHECK-RV64-SAME: (<vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmsub.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmsub.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
// //
vfloat16mf2_t test_vfnmsub_vf_f16mf2(vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) { vfloat16mf2_t test_vfnmsub_vf_f16mf2(vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfnmsub_vf_f16mf2(vd, rs1, vs2, vl); return __riscv_vfnmsub_vf_f16mf2(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmsub_vv_f16m1 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmsub_vv_f16m1
// CHECK-RV64-SAME: (<vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmsub.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmsub.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
// //
vfloat16m1_t test_vfnmsub_vv_f16m1(vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) { vfloat16m1_t test_vfnmsub_vv_f16m1(vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfnmsub_vv_f16m1(vd, vs1, vs2, vl); return __riscv_vfnmsub_vv_f16m1(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmsub_vf_f16m1 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmsub_vf_f16m1
// CHECK-RV64-SAME: (<vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmsub.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmsub.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
// //
vfloat16m1_t test_vfnmsub_vf_f16m1(vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) { vfloat16m1_t test_vfnmsub_vf_f16m1(vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfnmsub_vf_f16m1(vd, rs1, vs2, vl); return __riscv_vfnmsub_vf_f16m1(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmsub_vv_f16m2 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmsub_vv_f16m2
// CHECK-RV64-SAME: (<vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmsub.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmsub.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
// //
vfloat16m2_t test_vfnmsub_vv_f16m2(vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) { vfloat16m2_t test_vfnmsub_vv_f16m2(vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfnmsub_vv_f16m2(vd, vs1, vs2, vl); return __riscv_vfnmsub_vv_f16m2(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmsub_vf_f16m2 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmsub_vf_f16m2
// CHECK-RV64-SAME: (<vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmsub.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmsub.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
// //
vfloat16m2_t test_vfnmsub_vf_f16m2(vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) { vfloat16m2_t test_vfnmsub_vf_f16m2(vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfnmsub_vf_f16m2(vd, rs1, vs2, vl); return __riscv_vfnmsub_vf_f16m2(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmsub_vv_f16m4 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmsub_vv_f16m4
// CHECK-RV64-SAME: (<vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmsub.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmsub.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
// //
vfloat16m4_t test_vfnmsub_vv_f16m4(vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) { vfloat16m4_t test_vfnmsub_vv_f16m4(vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfnmsub_vv_f16m4(vd, vs1, vs2, vl); return __riscv_vfnmsub_vv_f16m4(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmsub_vf_f16m4 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmsub_vf_f16m4
// CHECK-RV64-SAME: (<vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmsub.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmsub.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
// //
vfloat16m4_t test_vfnmsub_vf_f16m4(vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) { vfloat16m4_t test_vfnmsub_vf_f16m4(vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfnmsub_vf_f16m4(vd, rs1, vs2, vl); return __riscv_vfnmsub_vf_f16m4(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmsub_vv_f16m8 // CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmsub_vv_f16m8
// CHECK-RV64-SAME: (<vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmsub.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmsub.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
// //
vfloat16m8_t test_vfnmsub_vv_f16m8(vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) { vfloat16m8_t test_vfnmsub_vv_f16m8(vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfnmsub_vv_f16m8(vd, vs1, vs2, vl); return __riscv_vfnmsub_vv_f16m8(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmsub_vf_f16m8 // CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmsub_vf_f16m8
// CHECK-RV64-SAME: (<vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmsub.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmsub.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
// //
vfloat16m8_t test_vfnmsub_vf_f16m8(vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) { vfloat16m8_t test_vfnmsub_vf_f16m8(vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfnmsub_vf_f16m8(vd, rs1, vs2, vl); return __riscv_vfnmsub_vf_f16m8(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmsub_vv_f32mf2 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmsub_vv_f32mf2
// CHECK-RV64-SAME: (<vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmsub.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmsub.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfnmsub_vv_f32mf2(vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) { vfloat32mf2_t test_vfnmsub_vv_f32mf2(vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfnmsub_vv_f32mf2(vd, vs1, vs2, vl); return __riscv_vfnmsub_vv_f32mf2(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmsub_vf_f32mf2 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmsub_vf_f32mf2
// CHECK-RV64-SAME: (<vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmsub.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmsub.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfnmsub_vf_f32mf2(vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) { vfloat32mf2_t test_vfnmsub_vf_f32mf2(vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfnmsub_vf_f32mf2(vd, rs1, vs2, vl); return __riscv_vfnmsub_vf_f32mf2(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmsub_vv_f32m1 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmsub_vv_f32m1
// CHECK-RV64-SAME: (<vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmsub.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmsub.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfnmsub_vv_f32m1(vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) { vfloat32m1_t test_vfnmsub_vv_f32m1(vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfnmsub_vv_f32m1(vd, vs1, vs2, vl); return __riscv_vfnmsub_vv_f32m1(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmsub_vf_f32m1 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmsub_vf_f32m1
// CHECK-RV64-SAME: (<vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmsub.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmsub.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfnmsub_vf_f32m1(vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) { vfloat32m1_t test_vfnmsub_vf_f32m1(vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfnmsub_vf_f32m1(vd, rs1, vs2, vl); return __riscv_vfnmsub_vf_f32m1(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmsub_vv_f32m2 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmsub_vv_f32m2
// CHECK-RV64-SAME: (<vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmsub.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmsub.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfnmsub_vv_f32m2(vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) { vfloat32m2_t test_vfnmsub_vv_f32m2(vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfnmsub_vv_f32m2(vd, vs1, vs2, vl); return __riscv_vfnmsub_vv_f32m2(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmsub_vf_f32m2 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmsub_vf_f32m2
// CHECK-RV64-SAME: (<vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmsub.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmsub.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfnmsub_vf_f32m2(vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) { vfloat32m2_t test_vfnmsub_vf_f32m2(vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfnmsub_vf_f32m2(vd, rs1, vs2, vl); return __riscv_vfnmsub_vf_f32m2(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmsub_vv_f32m4 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmsub_vv_f32m4
// CHECK-RV64-SAME: (<vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmsub.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmsub.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfnmsub_vv_f32m4(vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) { vfloat32m4_t test_vfnmsub_vv_f32m4(vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfnmsub_vv_f32m4(vd, vs1, vs2, vl); return __riscv_vfnmsub_vv_f32m4(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmsub_vf_f32m4 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmsub_vf_f32m4
// CHECK-RV64-SAME: (<vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmsub.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmsub.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfnmsub_vf_f32m4(vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) { vfloat32m4_t test_vfnmsub_vf_f32m4(vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfnmsub_vf_f32m4(vd, rs1, vs2, vl); return __riscv_vfnmsub_vf_f32m4(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmsub_vv_f32m8 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmsub_vv_f32m8
// CHECK-RV64-SAME: (<vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmsub.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmsub.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfnmsub_vv_f32m8(vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) { vfloat32m8_t test_vfnmsub_vv_f32m8(vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfnmsub_vv_f32m8(vd, vs1, vs2, vl); return __riscv_vfnmsub_vv_f32m8(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmsub_vf_f32m8 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmsub_vf_f32m8
// CHECK-RV64-SAME: (<vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmsub.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmsub.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfnmsub_vf_f32m8(vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) { vfloat32m8_t test_vfnmsub_vf_f32m8(vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfnmsub_vf_f32m8(vd, rs1, vs2, vl); return __riscv_vfnmsub_vf_f32m8(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmsub_vv_f64m1 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmsub_vv_f64m1
// CHECK-RV64-SAME: (<vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmsub.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmsub.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfnmsub_vv_f64m1(vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) { vfloat64m1_t test_vfnmsub_vv_f64m1(vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfnmsub_vv_f64m1(vd, vs1, vs2, vl); return __riscv_vfnmsub_vv_f64m1(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmsub_vf_f64m1 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmsub_vf_f64m1
// CHECK-RV64-SAME: (<vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmsub.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmsub.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfnmsub_vf_f64m1(vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) { vfloat64m1_t test_vfnmsub_vf_f64m1(vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfnmsub_vf_f64m1(vd, rs1, vs2, vl); return __riscv_vfnmsub_vf_f64m1(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmsub_vv_f64m2 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmsub_vv_f64m2
// CHECK-RV64-SAME: (<vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmsub.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmsub.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfnmsub_vv_f64m2(vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) { vfloat64m2_t test_vfnmsub_vv_f64m2(vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfnmsub_vv_f64m2(vd, vs1, vs2, vl); return __riscv_vfnmsub_vv_f64m2(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmsub_vf_f64m2 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmsub_vf_f64m2
// CHECK-RV64-SAME: (<vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmsub.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmsub.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfnmsub_vf_f64m2(vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) { vfloat64m2_t test_vfnmsub_vf_f64m2(vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfnmsub_vf_f64m2(vd, rs1, vs2, vl); return __riscv_vfnmsub_vf_f64m2(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmsub_vv_f64m4 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmsub_vv_f64m4
// CHECK-RV64-SAME: (<vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmsub.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmsub.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfnmsub_vv_f64m4(vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) { vfloat64m4_t test_vfnmsub_vv_f64m4(vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfnmsub_vv_f64m4(vd, vs1, vs2, vl); return __riscv_vfnmsub_vv_f64m4(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmsub_vf_f64m4 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmsub_vf_f64m4
// CHECK-RV64-SAME: (<vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmsub.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmsub.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfnmsub_vf_f64m4(vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) { vfloat64m4_t test_vfnmsub_vf_f64m4(vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfnmsub_vf_f64m4(vd, rs1, vs2, vl); return __riscv_vfnmsub_vf_f64m4(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmsub_vv_f64m8 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmsub_vv_f64m8
// CHECK-RV64-SAME: (<vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmsub.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmsub.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfnmsub_vv_f64m8(vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) { vfloat64m8_t test_vfnmsub_vv_f64m8(vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfnmsub_vv_f64m8(vd, vs1, vs2, vl); return __riscv_vfnmsub_vv_f64m8(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmsub_vf_f64m8 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmsub_vf_f64m8
// CHECK-RV64-SAME: (<vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmsub.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmsub.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfnmsub_vf_f64m8(vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) { vfloat64m8_t test_vfnmsub_vf_f64m8(vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfnmsub_vf_f64m8(vd, rs1, vs2, vl); return __riscv_vfnmsub_vf_f64m8(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmsub_vv_f16mf4_m // CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmsub_vv_f16mf4_m
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmsub.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmsub.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
// //
vfloat16mf4_t test_vfnmsub_vv_f16mf4_m(vbool64_t mask, vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) { vfloat16mf4_t test_vfnmsub_vv_f16mf4_m(vbool64_t mask, vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfnmsub_vv_f16mf4_m(mask, vd, vs1, vs2, vl); return __riscv_vfnmsub_vv_f16mf4_m(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmsub_vf_f16mf4_m // CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmsub_vf_f16mf4_m
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmsub.mask.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmsub.mask.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
// //
vfloat16mf4_t test_vfnmsub_vf_f16mf4_m(vbool64_t mask, vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) { vfloat16mf4_t test_vfnmsub_vf_f16mf4_m(vbool64_t mask, vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfnmsub_vf_f16mf4_m(mask, vd, rs1, vs2, vl); return __riscv_vfnmsub_vf_f16mf4_m(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmsub_vv_f16mf2_m // CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmsub_vv_f16mf2_m
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmsub.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmsub.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
// //
vfloat16mf2_t test_vfnmsub_vv_f16mf2_m(vbool32_t mask, vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) { vfloat16mf2_t test_vfnmsub_vv_f16mf2_m(vbool32_t mask, vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfnmsub_vv_f16mf2_m(mask, vd, vs1, vs2, vl); return __riscv_vfnmsub_vv_f16mf2_m(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmsub_vf_f16mf2_m // CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmsub_vf_f16mf2_m
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmsub.mask.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmsub.mask.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
// //
vfloat16mf2_t test_vfnmsub_vf_f16mf2_m(vbool32_t mask, vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) { vfloat16mf2_t test_vfnmsub_vf_f16mf2_m(vbool32_t mask, vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfnmsub_vf_f16mf2_m(mask, vd, rs1, vs2, vl); return __riscv_vfnmsub_vf_f16mf2_m(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmsub_vv_f16m1_m // CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmsub_vv_f16m1_m
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmsub.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmsub.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
// //
vfloat16m1_t test_vfnmsub_vv_f16m1_m(vbool16_t mask, vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) { vfloat16m1_t test_vfnmsub_vv_f16m1_m(vbool16_t mask, vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfnmsub_vv_f16m1_m(mask, vd, vs1, vs2, vl); return __riscv_vfnmsub_vv_f16m1_m(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmsub_vf_f16m1_m // CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmsub_vf_f16m1_m
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmsub.mask.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmsub.mask.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
// //
vfloat16m1_t test_vfnmsub_vf_f16m1_m(vbool16_t mask, vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) { vfloat16m1_t test_vfnmsub_vf_f16m1_m(vbool16_t mask, vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfnmsub_vf_f16m1_m(mask, vd, rs1, vs2, vl); return __riscv_vfnmsub_vf_f16m1_m(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmsub_vv_f16m2_m // CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmsub_vv_f16m2_m
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmsub.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmsub.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
// //
vfloat16m2_t test_vfnmsub_vv_f16m2_m(vbool8_t mask, vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) { vfloat16m2_t test_vfnmsub_vv_f16m2_m(vbool8_t mask, vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfnmsub_vv_f16m2_m(mask, vd, vs1, vs2, vl); return __riscv_vfnmsub_vv_f16m2_m(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmsub_vf_f16m2_m // CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmsub_vf_f16m2_m
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmsub.mask.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmsub.mask.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
// //
vfloat16m2_t test_vfnmsub_vf_f16m2_m(vbool8_t mask, vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) { vfloat16m2_t test_vfnmsub_vf_f16m2_m(vbool8_t mask, vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfnmsub_vf_f16m2_m(mask, vd, rs1, vs2, vl); return __riscv_vfnmsub_vf_f16m2_m(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmsub_vv_f16m4_m // CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmsub_vv_f16m4_m
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmsub.mask.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmsub.mask.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
// //
vfloat16m4_t test_vfnmsub_vv_f16m4_m(vbool4_t mask, vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) { vfloat16m4_t test_vfnmsub_vv_f16m4_m(vbool4_t mask, vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfnmsub_vv_f16m4_m(mask, vd, vs1, vs2, vl); return __riscv_vfnmsub_vv_f16m4_m(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmsub_vf_f16m4_m // CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmsub_vf_f16m4_m
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmsub.mask.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmsub.mask.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
// //
vfloat16m4_t test_vfnmsub_vf_f16m4_m(vbool4_t mask, vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) { vfloat16m4_t test_vfnmsub_vf_f16m4_m(vbool4_t mask, vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfnmsub_vf_f16m4_m(mask, vd, rs1, vs2, vl); return __riscv_vfnmsub_vf_f16m4_m(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmsub_vv_f16m8_m // CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmsub_vv_f16m8_m
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmsub.mask.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmsub.mask.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
// //
vfloat16m8_t test_vfnmsub_vv_f16m8_m(vbool2_t mask, vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) { vfloat16m8_t test_vfnmsub_vv_f16m8_m(vbool2_t mask, vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfnmsub_vv_f16m8_m(mask, vd, vs1, vs2, vl); return __riscv_vfnmsub_vv_f16m8_m(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmsub_vf_f16m8_m // CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmsub_vf_f16m8_m
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmsub.mask.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmsub.mask.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
// //
vfloat16m8_t test_vfnmsub_vf_f16m8_m(vbool2_t mask, vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) { vfloat16m8_t test_vfnmsub_vf_f16m8_m(vbool2_t mask, vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfnmsub_vf_f16m8_m(mask, vd, rs1, vs2, vl); return __riscv_vfnmsub_vf_f16m8_m(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmsub_vv_f32mf2_m // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmsub_vv_f32mf2_m
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmsub.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmsub.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfnmsub_vv_f32mf2_m(vbool64_t mask, vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) { vfloat32mf2_t test_vfnmsub_vv_f32mf2_m(vbool64_t mask, vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfnmsub_vv_f32mf2_m(mask, vd, vs1, vs2, vl); return __riscv_vfnmsub_vv_f32mf2_m(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmsub_vf_f32mf2_m // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmsub_vf_f32mf2_m
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmsub.mask.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmsub.mask.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfnmsub_vf_f32mf2_m(vbool64_t mask, vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) { vfloat32mf2_t test_vfnmsub_vf_f32mf2_m(vbool64_t mask, vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfnmsub_vf_f32mf2_m(mask, vd, rs1, vs2, vl); return __riscv_vfnmsub_vf_f32mf2_m(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmsub_vv_f32m1_m // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmsub_vv_f32m1_m
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmsub.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmsub.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfnmsub_vv_f32m1_m(vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) { vfloat32m1_t test_vfnmsub_vv_f32m1_m(vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfnmsub_vv_f32m1_m(mask, vd, vs1, vs2, vl); return __riscv_vfnmsub_vv_f32m1_m(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmsub_vf_f32m1_m // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmsub_vf_f32m1_m
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmsub.mask.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmsub.mask.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfnmsub_vf_f32m1_m(vbool32_t mask, vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) { vfloat32m1_t test_vfnmsub_vf_f32m1_m(vbool32_t mask, vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfnmsub_vf_f32m1_m(mask, vd, rs1, vs2, vl); return __riscv_vfnmsub_vf_f32m1_m(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmsub_vv_f32m2_m // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmsub_vv_f32m2_m
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmsub.mask.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmsub.mask.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfnmsub_vv_f32m2_m(vbool16_t mask, vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) { vfloat32m2_t test_vfnmsub_vv_f32m2_m(vbool16_t mask, vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfnmsub_vv_f32m2_m(mask, vd, vs1, vs2, vl); return __riscv_vfnmsub_vv_f32m2_m(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmsub_vf_f32m2_m // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmsub_vf_f32m2_m
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmsub.mask.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmsub.mask.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfnmsub_vf_f32m2_m(vbool16_t mask, vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) { vfloat32m2_t test_vfnmsub_vf_f32m2_m(vbool16_t mask, vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfnmsub_vf_f32m2_m(mask, vd, rs1, vs2, vl); return __riscv_vfnmsub_vf_f32m2_m(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmsub_vv_f32m4_m // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmsub_vv_f32m4_m
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmsub.mask.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmsub.mask.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfnmsub_vv_f32m4_m(vbool8_t mask, vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) { vfloat32m4_t test_vfnmsub_vv_f32m4_m(vbool8_t mask, vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfnmsub_vv_f32m4_m(mask, vd, vs1, vs2, vl); return __riscv_vfnmsub_vv_f32m4_m(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmsub_vf_f32m4_m // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmsub_vf_f32m4_m
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmsub.mask.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmsub.mask.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfnmsub_vf_f32m4_m(vbool8_t mask, vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) { vfloat32m4_t test_vfnmsub_vf_f32m4_m(vbool8_t mask, vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfnmsub_vf_f32m4_m(mask, vd, rs1, vs2, vl); return __riscv_vfnmsub_vf_f32m4_m(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmsub_vv_f32m8_m // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmsub_vv_f32m8_m
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmsub.mask.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmsub.mask.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfnmsub_vv_f32m8_m(vbool4_t mask, vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) { vfloat32m8_t test_vfnmsub_vv_f32m8_m(vbool4_t mask, vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfnmsub_vv_f32m8_m(mask, vd, vs1, vs2, vl); return __riscv_vfnmsub_vv_f32m8_m(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmsub_vf_f32m8_m // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmsub_vf_f32m8_m
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmsub.mask.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmsub.mask.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfnmsub_vf_f32m8_m(vbool4_t mask, vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) { vfloat32m8_t test_vfnmsub_vf_f32m8_m(vbool4_t mask, vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfnmsub_vf_f32m8_m(mask, vd, rs1, vs2, vl); return __riscv_vfnmsub_vf_f32m8_m(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmsub_vv_f64m1_m // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmsub_vv_f64m1_m
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmsub.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmsub.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfnmsub_vv_f64m1_m(vbool64_t mask, vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) { vfloat64m1_t test_vfnmsub_vv_f64m1_m(vbool64_t mask, vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfnmsub_vv_f64m1_m(mask, vd, vs1, vs2, vl); return __riscv_vfnmsub_vv_f64m1_m(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmsub_vf_f64m1_m // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmsub_vf_f64m1_m
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmsub.mask.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmsub.mask.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfnmsub_vf_f64m1_m(vbool64_t mask, vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) { vfloat64m1_t test_vfnmsub_vf_f64m1_m(vbool64_t mask, vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfnmsub_vf_f64m1_m(mask, vd, rs1, vs2, vl); return __riscv_vfnmsub_vf_f64m1_m(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmsub_vv_f64m2_m // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmsub_vv_f64m2_m
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmsub.mask.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmsub.mask.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfnmsub_vv_f64m2_m(vbool32_t mask, vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) { vfloat64m2_t test_vfnmsub_vv_f64m2_m(vbool32_t mask, vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfnmsub_vv_f64m2_m(mask, vd, vs1, vs2, vl); return __riscv_vfnmsub_vv_f64m2_m(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmsub_vf_f64m2_m // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmsub_vf_f64m2_m
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmsub.mask.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmsub.mask.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfnmsub_vf_f64m2_m(vbool32_t mask, vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) { vfloat64m2_t test_vfnmsub_vf_f64m2_m(vbool32_t mask, vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfnmsub_vf_f64m2_m(mask, vd, rs1, vs2, vl); return __riscv_vfnmsub_vf_f64m2_m(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmsub_vv_f64m4_m // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmsub_vv_f64m4_m
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmsub.mask.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmsub.mask.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfnmsub_vv_f64m4_m(vbool16_t mask, vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) { vfloat64m4_t test_vfnmsub_vv_f64m4_m(vbool16_t mask, vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfnmsub_vv_f64m4_m(mask, vd, vs1, vs2, vl); return __riscv_vfnmsub_vv_f64m4_m(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmsub_vf_f64m4_m // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmsub_vf_f64m4_m
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmsub.mask.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmsub.mask.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfnmsub_vf_f64m4_m(vbool16_t mask, vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) { vfloat64m4_t test_vfnmsub_vf_f64m4_m(vbool16_t mask, vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfnmsub_vf_f64m4_m(mask, vd, rs1, vs2, vl); return __riscv_vfnmsub_vf_f64m4_m(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmsub_vv_f64m8_m // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmsub_vv_f64m8_m
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmsub.mask.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmsub.mask.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfnmsub_vv_f64m8_m(vbool8_t mask, vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) { vfloat64m8_t test_vfnmsub_vv_f64m8_m(vbool8_t mask, vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfnmsub_vv_f64m8_m(mask, vd, vs1, vs2, vl); return __riscv_vfnmsub_vv_f64m8_m(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmsub_vf_f64m8_m // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmsub_vf_f64m8_m
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmsub.mask.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmsub.mask.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfnmsub_vf_f64m8_m(vbool8_t mask, vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) { vfloat64m8_t test_vfnmsub_vf_f64m8_m(vbool8_t mask, vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfnmsub_vf_f64m8_m(mask, vd, rs1, vs2, vl); return __riscv_vfnmsub_vf_f64m8_m(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmsub_vv_f16mf4_rm
// CHECK-RV64-SAME: (<vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmsub.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
//
vfloat16mf4_t test_vfnmsub_vv_f16mf4_rm(vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfnmsub_vv_f16mf4_rm(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmsub_vf_f16mf4_rm
// CHECK-RV64-SAME: (<vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmsub.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
//
vfloat16mf4_t test_vfnmsub_vf_f16mf4_rm(vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfnmsub_vf_f16mf4_rm(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmsub_vv_f16mf2_rm
// CHECK-RV64-SAME: (<vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmsub.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
//
vfloat16mf2_t test_vfnmsub_vv_f16mf2_rm(vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfnmsub_vv_f16mf2_rm(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmsub_vf_f16mf2_rm
// CHECK-RV64-SAME: (<vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmsub.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
//
vfloat16mf2_t test_vfnmsub_vf_f16mf2_rm(vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfnmsub_vf_f16mf2_rm(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmsub_vv_f16m1_rm
// CHECK-RV64-SAME: (<vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmsub.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfnmsub_vv_f16m1_rm(vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfnmsub_vv_f16m1_rm(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmsub_vf_f16m1_rm
// CHECK-RV64-SAME: (<vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmsub.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfnmsub_vf_f16m1_rm(vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfnmsub_vf_f16m1_rm(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmsub_vv_f16m2_rm
// CHECK-RV64-SAME: (<vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmsub.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
//
vfloat16m2_t test_vfnmsub_vv_f16m2_rm(vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfnmsub_vv_f16m2_rm(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmsub_vf_f16m2_rm
// CHECK-RV64-SAME: (<vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmsub.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
//
vfloat16m2_t test_vfnmsub_vf_f16m2_rm(vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfnmsub_vf_f16m2_rm(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmsub_vv_f16m4_rm
// CHECK-RV64-SAME: (<vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmsub.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
//
vfloat16m4_t test_vfnmsub_vv_f16m4_rm(vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfnmsub_vv_f16m4_rm(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmsub_vf_f16m4_rm
// CHECK-RV64-SAME: (<vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmsub.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
//
vfloat16m4_t test_vfnmsub_vf_f16m4_rm(vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfnmsub_vf_f16m4_rm(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmsub_vv_f16m8_rm
// CHECK-RV64-SAME: (<vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmsub.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
//
vfloat16m8_t test_vfnmsub_vv_f16m8_rm(vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfnmsub_vv_f16m8_rm(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmsub_vf_f16m8_rm
// CHECK-RV64-SAME: (<vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmsub.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
//
vfloat16m8_t test_vfnmsub_vf_f16m8_rm(vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfnmsub_vf_f16m8_rm(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmsub_vv_f32mf2_rm
// CHECK-RV64-SAME: (<vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmsub.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
//
vfloat32mf2_t test_vfnmsub_vv_f32mf2_rm(vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfnmsub_vv_f32mf2_rm(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmsub_vf_f32mf2_rm
// CHECK-RV64-SAME: (<vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmsub.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
//
vfloat32mf2_t test_vfnmsub_vf_f32mf2_rm(vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfnmsub_vf_f32mf2_rm(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmsub_vv_f32m1_rm
// CHECK-RV64-SAME: (<vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmsub.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfnmsub_vv_f32m1_rm(vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfnmsub_vv_f32m1_rm(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmsub_vf_f32m1_rm
// CHECK-RV64-SAME: (<vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmsub.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfnmsub_vf_f32m1_rm(vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfnmsub_vf_f32m1_rm(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmsub_vv_f32m2_rm
// CHECK-RV64-SAME: (<vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmsub.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
//
vfloat32m2_t test_vfnmsub_vv_f32m2_rm(vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfnmsub_vv_f32m2_rm(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmsub_vf_f32m2_rm
// CHECK-RV64-SAME: (<vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmsub.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
//
vfloat32m2_t test_vfnmsub_vf_f32m2_rm(vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfnmsub_vf_f32m2_rm(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmsub_vv_f32m4_rm
// CHECK-RV64-SAME: (<vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmsub.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
//
vfloat32m4_t test_vfnmsub_vv_f32m4_rm(vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfnmsub_vv_f32m4_rm(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmsub_vf_f32m4_rm
// CHECK-RV64-SAME: (<vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmsub.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
//
vfloat32m4_t test_vfnmsub_vf_f32m4_rm(vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfnmsub_vf_f32m4_rm(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmsub_vv_f32m8_rm
// CHECK-RV64-SAME: (<vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmsub.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
//
vfloat32m8_t test_vfnmsub_vv_f32m8_rm(vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfnmsub_vv_f32m8_rm(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmsub_vf_f32m8_rm
// CHECK-RV64-SAME: (<vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmsub.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
//
vfloat32m8_t test_vfnmsub_vf_f32m8_rm(vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfnmsub_vf_f32m8_rm(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmsub_vv_f64m1_rm
// CHECK-RV64-SAME: (<vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmsub.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfnmsub_vv_f64m1_rm(vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfnmsub_vv_f64m1_rm(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmsub_vf_f64m1_rm
// CHECK-RV64-SAME: (<vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmsub.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfnmsub_vf_f64m1_rm(vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfnmsub_vf_f64m1_rm(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmsub_vv_f64m2_rm
// CHECK-RV64-SAME: (<vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmsub.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
//
vfloat64m2_t test_vfnmsub_vv_f64m2_rm(vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfnmsub_vv_f64m2_rm(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmsub_vf_f64m2_rm
// CHECK-RV64-SAME: (<vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmsub.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
//
vfloat64m2_t test_vfnmsub_vf_f64m2_rm(vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfnmsub_vf_f64m2_rm(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmsub_vv_f64m4_rm
// CHECK-RV64-SAME: (<vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmsub.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
//
vfloat64m4_t test_vfnmsub_vv_f64m4_rm(vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfnmsub_vv_f64m4_rm(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmsub_vf_f64m4_rm
// CHECK-RV64-SAME: (<vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmsub.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
//
vfloat64m4_t test_vfnmsub_vf_f64m4_rm(vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfnmsub_vf_f64m4_rm(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmsub_vv_f64m8_rm
// CHECK-RV64-SAME: (<vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmsub.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
//
vfloat64m8_t test_vfnmsub_vv_f64m8_rm(vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfnmsub_vv_f64m8_rm(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmsub_vf_f64m8_rm
// CHECK-RV64-SAME: (<vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmsub.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
//
vfloat64m8_t test_vfnmsub_vf_f64m8_rm(vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfnmsub_vf_f64m8_rm(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmsub_vv_f16mf4_rm_m
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmsub.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
//
vfloat16mf4_t test_vfnmsub_vv_f16mf4_rm_m(vbool64_t mask, vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfnmsub_vv_f16mf4_rm_m(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmsub_vf_f16mf4_rm_m
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmsub.mask.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
//
vfloat16mf4_t test_vfnmsub_vf_f16mf4_rm_m(vbool64_t mask, vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfnmsub_vf_f16mf4_rm_m(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmsub_vv_f16mf2_rm_m
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmsub.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
//
vfloat16mf2_t test_vfnmsub_vv_f16mf2_rm_m(vbool32_t mask, vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfnmsub_vv_f16mf2_rm_m(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmsub_vf_f16mf2_rm_m
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmsub.mask.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
//
vfloat16mf2_t test_vfnmsub_vf_f16mf2_rm_m(vbool32_t mask, vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfnmsub_vf_f16mf2_rm_m(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmsub_vv_f16m1_rm_m
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmsub.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfnmsub_vv_f16m1_rm_m(vbool16_t mask, vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfnmsub_vv_f16m1_rm_m(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmsub_vf_f16m1_rm_m
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmsub.mask.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfnmsub_vf_f16m1_rm_m(vbool16_t mask, vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfnmsub_vf_f16m1_rm_m(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmsub_vv_f16m2_rm_m
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmsub.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
//
vfloat16m2_t test_vfnmsub_vv_f16m2_rm_m(vbool8_t mask, vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfnmsub_vv_f16m2_rm_m(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmsub_vf_f16m2_rm_m
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmsub.mask.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
//
vfloat16m2_t test_vfnmsub_vf_f16m2_rm_m(vbool8_t mask, vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfnmsub_vf_f16m2_rm_m(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmsub_vv_f16m4_rm_m
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmsub.mask.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
//
vfloat16m4_t test_vfnmsub_vv_f16m4_rm_m(vbool4_t mask, vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfnmsub_vv_f16m4_rm_m(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmsub_vf_f16m4_rm_m
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmsub.mask.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
//
vfloat16m4_t test_vfnmsub_vf_f16m4_rm_m(vbool4_t mask, vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfnmsub_vf_f16m4_rm_m(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmsub_vv_f16m8_rm_m
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmsub.mask.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
//
vfloat16m8_t test_vfnmsub_vv_f16m8_rm_m(vbool2_t mask, vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfnmsub_vv_f16m8_rm_m(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmsub_vf_f16m8_rm_m
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmsub.mask.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
//
vfloat16m8_t test_vfnmsub_vf_f16m8_rm_m(vbool2_t mask, vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfnmsub_vf_f16m8_rm_m(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmsub_vv_f32mf2_rm_m
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmsub.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
//
vfloat32mf2_t test_vfnmsub_vv_f32mf2_rm_m(vbool64_t mask, vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfnmsub_vv_f32mf2_rm_m(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmsub_vf_f32mf2_rm_m
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmsub.mask.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
//
vfloat32mf2_t test_vfnmsub_vf_f32mf2_rm_m(vbool64_t mask, vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfnmsub_vf_f32mf2_rm_m(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmsub_vv_f32m1_rm_m
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmsub.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfnmsub_vv_f32m1_rm_m(vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfnmsub_vv_f32m1_rm_m(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmsub_vf_f32m1_rm_m
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmsub.mask.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfnmsub_vf_f32m1_rm_m(vbool32_t mask, vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfnmsub_vf_f32m1_rm_m(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmsub_vv_f32m2_rm_m
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmsub.mask.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
//
vfloat32m2_t test_vfnmsub_vv_f32m2_rm_m(vbool16_t mask, vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfnmsub_vv_f32m2_rm_m(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmsub_vf_f32m2_rm_m
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmsub.mask.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
//
vfloat32m2_t test_vfnmsub_vf_f32m2_rm_m(vbool16_t mask, vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfnmsub_vf_f32m2_rm_m(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmsub_vv_f32m4_rm_m
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmsub.mask.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
//
vfloat32m4_t test_vfnmsub_vv_f32m4_rm_m(vbool8_t mask, vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfnmsub_vv_f32m4_rm_m(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmsub_vf_f32m4_rm_m
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmsub.mask.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
//
vfloat32m4_t test_vfnmsub_vf_f32m4_rm_m(vbool8_t mask, vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfnmsub_vf_f32m4_rm_m(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmsub_vv_f32m8_rm_m
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmsub.mask.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
//
vfloat32m8_t test_vfnmsub_vv_f32m8_rm_m(vbool4_t mask, vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfnmsub_vv_f32m8_rm_m(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmsub_vf_f32m8_rm_m
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmsub.mask.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
//
vfloat32m8_t test_vfnmsub_vf_f32m8_rm_m(vbool4_t mask, vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfnmsub_vf_f32m8_rm_m(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmsub_vv_f64m1_rm_m
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmsub.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfnmsub_vv_f64m1_rm_m(vbool64_t mask, vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfnmsub_vv_f64m1_rm_m(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmsub_vf_f64m1_rm_m
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmsub.mask.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfnmsub_vf_f64m1_rm_m(vbool64_t mask, vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfnmsub_vf_f64m1_rm_m(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmsub_vv_f64m2_rm_m
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmsub.mask.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
//
vfloat64m2_t test_vfnmsub_vv_f64m2_rm_m(vbool32_t mask, vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfnmsub_vv_f64m2_rm_m(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmsub_vf_f64m2_rm_m
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmsub.mask.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
//
vfloat64m2_t test_vfnmsub_vf_f64m2_rm_m(vbool32_t mask, vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfnmsub_vf_f64m2_rm_m(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmsub_vv_f64m4_rm_m
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmsub.mask.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
//
vfloat64m4_t test_vfnmsub_vv_f64m4_rm_m(vbool16_t mask, vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfnmsub_vv_f64m4_rm_m(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmsub_vf_f64m4_rm_m
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmsub.mask.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
//
vfloat64m4_t test_vfnmsub_vf_f64m4_rm_m(vbool16_t mask, vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfnmsub_vf_f64m4_rm_m(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmsub_vv_f64m8_rm_m
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmsub.mask.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
//
vfloat64m8_t test_vfnmsub_vv_f64m8_rm_m(vbool8_t mask, vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfnmsub_vv_f64m8_rm_m(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmsub_vf_f64m8_rm_m
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmsub.mask.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
//
vfloat64m8_t test_vfnmsub_vf_f64m8_rm_m(vbool8_t mask, vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfnmsub_vf_f64m8_rm_m(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}

clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmacc.c

// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target // REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh \ // RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh \
// RUN: -target-feature +experimental-zvfh -disable-O0-optnone \ // RUN: -target-feature +experimental-zvfh -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ // RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s // RUN: FileCheck --check-prefix=CHECK-RV64 %s
#include <riscv_vector.h> #include <riscv_vector.h>
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmacc_vv_f16mf4 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmacc_vv_f16mf4
// CHECK-RV64-SAME: (<vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK-RV64-SAME: (<vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmacc.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmacc.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
// //
vfloat16mf4_t test_vfmacc_vv_f16mf4(vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) { vfloat16mf4_t test_vfmacc_vv_f16mf4(vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfmacc(vd, vs1, vs2, vl); return __riscv_vfmacc(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmacc_vf_f16mf4 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmacc_vf_f16mf4
// CHECK-RV64-SAME: (<vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmacc.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmacc.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
// //
vfloat16mf4_t test_vfmacc_vf_f16mf4(vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) { vfloat16mf4_t test_vfmacc_vf_f16mf4(vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfmacc(vd, rs1, vs2, vl); return __riscv_vfmacc(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmacc_vv_f16mf2 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmacc_vv_f16mf2
// CHECK-RV64-SAME: (<vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmacc.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmacc.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
// //
vfloat16mf2_t test_vfmacc_vv_f16mf2(vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) { vfloat16mf2_t test_vfmacc_vv_f16mf2(vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfmacc(vd, vs1, vs2, vl); return __riscv_vfmacc(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmacc_vf_f16mf2 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmacc_vf_f16mf2
// CHECK-RV64-SAME: (<vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmacc.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmacc.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
// //
vfloat16mf2_t test_vfmacc_vf_f16mf2(vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) { vfloat16mf2_t test_vfmacc_vf_f16mf2(vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfmacc(vd, rs1, vs2, vl); return __riscv_vfmacc(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmacc_vv_f16m1 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmacc_vv_f16m1
// CHECK-RV64-SAME: (<vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmacc.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmacc.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
// //
vfloat16m1_t test_vfmacc_vv_f16m1(vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) { vfloat16m1_t test_vfmacc_vv_f16m1(vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfmacc(vd, vs1, vs2, vl); return __riscv_vfmacc(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmacc_vf_f16m1 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmacc_vf_f16m1
// CHECK-RV64-SAME: (<vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmacc.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmacc.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
// //
vfloat16m1_t test_vfmacc_vf_f16m1(vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) { vfloat16m1_t test_vfmacc_vf_f16m1(vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfmacc(vd, rs1, vs2, vl); return __riscv_vfmacc(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmacc_vv_f16m2 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmacc_vv_f16m2
// CHECK-RV64-SAME: (<vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmacc.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmacc.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
// //
vfloat16m2_t test_vfmacc_vv_f16m2(vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) { vfloat16m2_t test_vfmacc_vv_f16m2(vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfmacc(vd, vs1, vs2, vl); return __riscv_vfmacc(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmacc_vf_f16m2 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmacc_vf_f16m2
// CHECK-RV64-SAME: (<vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmacc.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmacc.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
// //
vfloat16m2_t test_vfmacc_vf_f16m2(vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) { vfloat16m2_t test_vfmacc_vf_f16m2(vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfmacc(vd, rs1, vs2, vl); return __riscv_vfmacc(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmacc_vv_f16m4 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmacc_vv_f16m4
// CHECK-RV64-SAME: (<vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmacc.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmacc.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
// //
vfloat16m4_t test_vfmacc_vv_f16m4(vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) { vfloat16m4_t test_vfmacc_vv_f16m4(vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfmacc(vd, vs1, vs2, vl); return __riscv_vfmacc(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmacc_vf_f16m4 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmacc_vf_f16m4
// CHECK-RV64-SAME: (<vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmacc.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmacc.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
// //
vfloat16m4_t test_vfmacc_vf_f16m4(vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) { vfloat16m4_t test_vfmacc_vf_f16m4(vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfmacc(vd, rs1, vs2, vl); return __riscv_vfmacc(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmacc_vv_f16m8 // CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmacc_vv_f16m8
// CHECK-RV64-SAME: (<vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmacc.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmacc.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
// //
vfloat16m8_t test_vfmacc_vv_f16m8(vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) { vfloat16m8_t test_vfmacc_vv_f16m8(vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfmacc(vd, vs1, vs2, vl); return __riscv_vfmacc(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmacc_vf_f16m8 // CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmacc_vf_f16m8
// CHECK-RV64-SAME: (<vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmacc.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmacc.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
// //
vfloat16m8_t test_vfmacc_vf_f16m8(vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) { vfloat16m8_t test_vfmacc_vf_f16m8(vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfmacc(vd, rs1, vs2, vl); return __riscv_vfmacc(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmacc_vv_f32mf2 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmacc_vv_f32mf2
// CHECK-RV64-SAME: (<vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmacc.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmacc.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfmacc_vv_f32mf2(vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) { vfloat32mf2_t test_vfmacc_vv_f32mf2(vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfmacc(vd, vs1, vs2, vl); return __riscv_vfmacc(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmacc_vf_f32mf2 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmacc_vf_f32mf2
// CHECK-RV64-SAME: (<vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmacc.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmacc.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfmacc_vf_f32mf2(vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) { vfloat32mf2_t test_vfmacc_vf_f32mf2(vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfmacc(vd, rs1, vs2, vl); return __riscv_vfmacc(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmacc_vv_f32m1 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmacc_vv_f32m1
// CHECK-RV64-SAME: (<vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmacc.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmacc.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfmacc_vv_f32m1(vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) { vfloat32m1_t test_vfmacc_vv_f32m1(vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfmacc(vd, vs1, vs2, vl); return __riscv_vfmacc(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmacc_vf_f32m1 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmacc_vf_f32m1
// CHECK-RV64-SAME: (<vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmacc.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmacc.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfmacc_vf_f32m1(vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) { vfloat32m1_t test_vfmacc_vf_f32m1(vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfmacc(vd, rs1, vs2, vl); return __riscv_vfmacc(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmacc_vv_f32m2 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmacc_vv_f32m2
// CHECK-RV64-SAME: (<vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmacc.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmacc.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfmacc_vv_f32m2(vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) { vfloat32m2_t test_vfmacc_vv_f32m2(vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfmacc(vd, vs1, vs2, vl); return __riscv_vfmacc(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmacc_vf_f32m2 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmacc_vf_f32m2
// CHECK-RV64-SAME: (<vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmacc.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmacc.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfmacc_vf_f32m2(vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) { vfloat32m2_t test_vfmacc_vf_f32m2(vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfmacc(vd, rs1, vs2, vl); return __riscv_vfmacc(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmacc_vv_f32m4 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmacc_vv_f32m4
// CHECK-RV64-SAME: (<vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmacc.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmacc.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfmacc_vv_f32m4(vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) { vfloat32m4_t test_vfmacc_vv_f32m4(vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfmacc(vd, vs1, vs2, vl); return __riscv_vfmacc(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmacc_vf_f32m4 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmacc_vf_f32m4
// CHECK-RV64-SAME: (<vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmacc.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmacc.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfmacc_vf_f32m4(vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) { vfloat32m4_t test_vfmacc_vf_f32m4(vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfmacc(vd, rs1, vs2, vl); return __riscv_vfmacc(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmacc_vv_f32m8 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmacc_vv_f32m8
// CHECK-RV64-SAME: (<vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmacc.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmacc.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfmacc_vv_f32m8(vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) { vfloat32m8_t test_vfmacc_vv_f32m8(vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfmacc(vd, vs1, vs2, vl); return __riscv_vfmacc(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmacc_vf_f32m8 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmacc_vf_f32m8
// CHECK-RV64-SAME: (<vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmacc.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmacc.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfmacc_vf_f32m8(vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) { vfloat32m8_t test_vfmacc_vf_f32m8(vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfmacc(vd, rs1, vs2, vl); return __riscv_vfmacc(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmacc_vv_f64m1 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmacc_vv_f64m1
// CHECK-RV64-SAME: (<vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmacc.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmacc.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfmacc_vv_f64m1(vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) { vfloat64m1_t test_vfmacc_vv_f64m1(vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfmacc(vd, vs1, vs2, vl); return __riscv_vfmacc(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmacc_vf_f64m1 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmacc_vf_f64m1
// CHECK-RV64-SAME: (<vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmacc.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmacc.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfmacc_vf_f64m1(vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) { vfloat64m1_t test_vfmacc_vf_f64m1(vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfmacc(vd, rs1, vs2, vl); return __riscv_vfmacc(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmacc_vv_f64m2 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmacc_vv_f64m2
// CHECK-RV64-SAME: (<vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmacc.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmacc.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfmacc_vv_f64m2(vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) { vfloat64m2_t test_vfmacc_vv_f64m2(vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfmacc(vd, vs1, vs2, vl); return __riscv_vfmacc(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmacc_vf_f64m2 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmacc_vf_f64m2
// CHECK-RV64-SAME: (<vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmacc.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmacc.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfmacc_vf_f64m2(vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) { vfloat64m2_t test_vfmacc_vf_f64m2(vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfmacc(vd, rs1, vs2, vl); return __riscv_vfmacc(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmacc_vv_f64m4 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmacc_vv_f64m4
// CHECK-RV64-SAME: (<vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmacc.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmacc.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfmacc_vv_f64m4(vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) { vfloat64m4_t test_vfmacc_vv_f64m4(vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfmacc(vd, vs1, vs2, vl); return __riscv_vfmacc(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmacc_vf_f64m4 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmacc_vf_f64m4
// CHECK-RV64-SAME: (<vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmacc.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmacc.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfmacc_vf_f64m4(vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) { vfloat64m4_t test_vfmacc_vf_f64m4(vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfmacc(vd, rs1, vs2, vl); return __riscv_vfmacc(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmacc_vv_f64m8 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmacc_vv_f64m8
// CHECK-RV64-SAME: (<vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmacc.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmacc.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfmacc_vv_f64m8(vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) { vfloat64m8_t test_vfmacc_vv_f64m8(vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfmacc(vd, vs1, vs2, vl); return __riscv_vfmacc(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmacc_vf_f64m8 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmacc_vf_f64m8
// CHECK-RV64-SAME: (<vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmacc.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmacc.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfmacc_vf_f64m8(vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) { vfloat64m8_t test_vfmacc_vf_f64m8(vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfmacc(vd, rs1, vs2, vl); return __riscv_vfmacc(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmacc_vv_f16mf4_m // CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmacc_vv_f16mf4_m
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmacc.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmacc.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
// //
vfloat16mf4_t test_vfmacc_vv_f16mf4_m(vbool64_t mask, vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) { vfloat16mf4_t test_vfmacc_vv_f16mf4_m(vbool64_t mask, vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfmacc(mask, vd, vs1, vs2, vl); return __riscv_vfmacc(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmacc_vf_f16mf4_m // CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmacc_vf_f16mf4_m
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmacc.mask.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmacc.mask.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
// //
vfloat16mf4_t test_vfmacc_vf_f16mf4_m(vbool64_t mask, vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) { vfloat16mf4_t test_vfmacc_vf_f16mf4_m(vbool64_t mask, vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfmacc(mask, vd, rs1, vs2, vl); return __riscv_vfmacc(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmacc_vv_f16mf2_m // CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmacc_vv_f16mf2_m
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmacc.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmacc.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
// //
vfloat16mf2_t test_vfmacc_vv_f16mf2_m(vbool32_t mask, vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) { vfloat16mf2_t test_vfmacc_vv_f16mf2_m(vbool32_t mask, vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfmacc(mask, vd, vs1, vs2, vl); return __riscv_vfmacc(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmacc_vf_f16mf2_m // CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmacc_vf_f16mf2_m
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmacc.mask.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmacc.mask.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
// //
vfloat16mf2_t test_vfmacc_vf_f16mf2_m(vbool32_t mask, vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) { vfloat16mf2_t test_vfmacc_vf_f16mf2_m(vbool32_t mask, vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfmacc(mask, vd, rs1, vs2, vl); return __riscv_vfmacc(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmacc_vv_f16m1_m // CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmacc_vv_f16m1_m
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmacc.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmacc.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
// //
vfloat16m1_t test_vfmacc_vv_f16m1_m(vbool16_t mask, vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) { vfloat16m1_t test_vfmacc_vv_f16m1_m(vbool16_t mask, vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfmacc(mask, vd, vs1, vs2, vl); return __riscv_vfmacc(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmacc_vf_f16m1_m // CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmacc_vf_f16m1_m
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmacc.mask.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmacc.mask.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
// //
vfloat16m1_t test_vfmacc_vf_f16m1_m(vbool16_t mask, vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) { vfloat16m1_t test_vfmacc_vf_f16m1_m(vbool16_t mask, vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfmacc(mask, vd, rs1, vs2, vl); return __riscv_vfmacc(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmacc_vv_f16m2_m // CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmacc_vv_f16m2_m
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmacc.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmacc.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
// //
vfloat16m2_t test_vfmacc_vv_f16m2_m(vbool8_t mask, vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) { vfloat16m2_t test_vfmacc_vv_f16m2_m(vbool8_t mask, vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfmacc(mask, vd, vs1, vs2, vl); return __riscv_vfmacc(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmacc_vf_f16m2_m // CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmacc_vf_f16m2_m
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmacc.mask.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmacc.mask.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
// //
vfloat16m2_t test_vfmacc_vf_f16m2_m(vbool8_t mask, vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) { vfloat16m2_t test_vfmacc_vf_f16m2_m(vbool8_t mask, vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfmacc(mask, vd, rs1, vs2, vl); return __riscv_vfmacc(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmacc_vv_f16m4_m // CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmacc_vv_f16m4_m
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmacc.mask.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmacc.mask.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
// //
vfloat16m4_t test_vfmacc_vv_f16m4_m(vbool4_t mask, vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) { vfloat16m4_t test_vfmacc_vv_f16m4_m(vbool4_t mask, vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfmacc(mask, vd, vs1, vs2, vl); return __riscv_vfmacc(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmacc_vf_f16m4_m // CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmacc_vf_f16m4_m
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmacc.mask.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmacc.mask.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
// //
vfloat16m4_t test_vfmacc_vf_f16m4_m(vbool4_t mask, vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) { vfloat16m4_t test_vfmacc_vf_f16m4_m(vbool4_t mask, vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfmacc(mask, vd, rs1, vs2, vl); return __riscv_vfmacc(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmacc_vv_f16m8_m // CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmacc_vv_f16m8_m
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmacc.mask.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmacc.mask.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
// //
vfloat16m8_t test_vfmacc_vv_f16m8_m(vbool2_t mask, vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) { vfloat16m8_t test_vfmacc_vv_f16m8_m(vbool2_t mask, vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfmacc(mask, vd, vs1, vs2, vl); return __riscv_vfmacc(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmacc_vf_f16m8_m // CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmacc_vf_f16m8_m
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmacc.mask.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmacc.mask.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
// //
vfloat16m8_t test_vfmacc_vf_f16m8_m(vbool2_t mask, vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) { vfloat16m8_t test_vfmacc_vf_f16m8_m(vbool2_t mask, vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfmacc(mask, vd, rs1, vs2, vl); return __riscv_vfmacc(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmacc_vv_f32mf2_m // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmacc_vv_f32mf2_m
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmacc.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmacc.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfmacc_vv_f32mf2_m(vbool64_t mask, vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) { vfloat32mf2_t test_vfmacc_vv_f32mf2_m(vbool64_t mask, vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfmacc(mask, vd, vs1, vs2, vl); return __riscv_vfmacc(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmacc_vf_f32mf2_m // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmacc_vf_f32mf2_m
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmacc.mask.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmacc.mask.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfmacc_vf_f32mf2_m(vbool64_t mask, vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) { vfloat32mf2_t test_vfmacc_vf_f32mf2_m(vbool64_t mask, vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfmacc(mask, vd, rs1, vs2, vl); return __riscv_vfmacc(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmacc_vv_f32m1_m // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmacc_vv_f32m1_m
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmacc.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmacc.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfmacc_vv_f32m1_m(vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) { vfloat32m1_t test_vfmacc_vv_f32m1_m(vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfmacc(mask, vd, vs1, vs2, vl); return __riscv_vfmacc(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmacc_vf_f32m1_m // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmacc_vf_f32m1_m
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmacc.mask.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmacc.mask.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfmacc_vf_f32m1_m(vbool32_t mask, vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) { vfloat32m1_t test_vfmacc_vf_f32m1_m(vbool32_t mask, vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfmacc(mask, vd, rs1, vs2, vl); return __riscv_vfmacc(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmacc_vv_f32m2_m // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmacc_vv_f32m2_m
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmacc.mask.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmacc.mask.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfmacc_vv_f32m2_m(vbool16_t mask, vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) { vfloat32m2_t test_vfmacc_vv_f32m2_m(vbool16_t mask, vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfmacc(mask, vd, vs1, vs2, vl); return __riscv_vfmacc(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmacc_vf_f32m2_m // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmacc_vf_f32m2_m
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmacc.mask.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmacc.mask.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfmacc_vf_f32m2_m(vbool16_t mask, vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) { vfloat32m2_t test_vfmacc_vf_f32m2_m(vbool16_t mask, vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfmacc(mask, vd, rs1, vs2, vl); return __riscv_vfmacc(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmacc_vv_f32m4_m // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmacc_vv_f32m4_m
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmacc.mask.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmacc.mask.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfmacc_vv_f32m4_m(vbool8_t mask, vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) { vfloat32m4_t test_vfmacc_vv_f32m4_m(vbool8_t mask, vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfmacc(mask, vd, vs1, vs2, vl); return __riscv_vfmacc(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmacc_vf_f32m4_m // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmacc_vf_f32m4_m
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmacc.mask.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmacc.mask.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfmacc_vf_f32m4_m(vbool8_t mask, vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) { vfloat32m4_t test_vfmacc_vf_f32m4_m(vbool8_t mask, vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfmacc(mask, vd, rs1, vs2, vl); return __riscv_vfmacc(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmacc_vv_f32m8_m // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmacc_vv_f32m8_m
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmacc.mask.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmacc.mask.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfmacc_vv_f32m8_m(vbool4_t mask, vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) { vfloat32m8_t test_vfmacc_vv_f32m8_m(vbool4_t mask, vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfmacc(mask, vd, vs1, vs2, vl); return __riscv_vfmacc(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmacc_vf_f32m8_m // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmacc_vf_f32m8_m
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmacc.mask.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmacc.mask.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfmacc_vf_f32m8_m(vbool4_t mask, vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) { vfloat32m8_t test_vfmacc_vf_f32m8_m(vbool4_t mask, vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfmacc(mask, vd, rs1, vs2, vl); return __riscv_vfmacc(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmacc_vv_f64m1_m // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmacc_vv_f64m1_m
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmacc.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmacc.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfmacc_vv_f64m1_m(vbool64_t mask, vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) { vfloat64m1_t test_vfmacc_vv_f64m1_m(vbool64_t mask, vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfmacc(mask, vd, vs1, vs2, vl); return __riscv_vfmacc(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmacc_vf_f64m1_m // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmacc_vf_f64m1_m
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmacc.mask.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmacc.mask.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfmacc_vf_f64m1_m(vbool64_t mask, vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) { vfloat64m1_t test_vfmacc_vf_f64m1_m(vbool64_t mask, vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfmacc(mask, vd, rs1, vs2, vl); return __riscv_vfmacc(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmacc_vv_f64m2_m // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmacc_vv_f64m2_m
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmacc.mask.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmacc.mask.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfmacc_vv_f64m2_m(vbool32_t mask, vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) { vfloat64m2_t test_vfmacc_vv_f64m2_m(vbool32_t mask, vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfmacc(mask, vd, vs1, vs2, vl); return __riscv_vfmacc(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmacc_vf_f64m2_m // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmacc_vf_f64m2_m
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmacc.mask.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmacc.mask.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfmacc_vf_f64m2_m(vbool32_t mask, vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) { vfloat64m2_t test_vfmacc_vf_f64m2_m(vbool32_t mask, vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfmacc(mask, vd, rs1, vs2, vl); return __riscv_vfmacc(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmacc_vv_f64m4_m // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmacc_vv_f64m4_m
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmacc.mask.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmacc.mask.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfmacc_vv_f64m4_m(vbool16_t mask, vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) { vfloat64m4_t test_vfmacc_vv_f64m4_m(vbool16_t mask, vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfmacc(mask, vd, vs1, vs2, vl); return __riscv_vfmacc(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmacc_vf_f64m4_m // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmacc_vf_f64m4_m
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmacc.mask.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmacc.mask.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfmacc_vf_f64m4_m(vbool16_t mask, vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) { vfloat64m4_t test_vfmacc_vf_f64m4_m(vbool16_t mask, vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfmacc(mask, vd, rs1, vs2, vl); return __riscv_vfmacc(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmacc_vv_f64m8_m // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmacc_vv_f64m8_m
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmacc.mask.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmacc.mask.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfmacc_vv_f64m8_m(vbool8_t mask, vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) { vfloat64m8_t test_vfmacc_vv_f64m8_m(vbool8_t mask, vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfmacc(mask, vd, vs1, vs2, vl); return __riscv_vfmacc(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmacc_vf_f64m8_m // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmacc_vf_f64m8_m
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmacc.mask.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmacc.mask.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfmacc_vf_f64m8_m(vbool8_t mask, vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) { vfloat64m8_t test_vfmacc_vf_f64m8_m(vbool8_t mask, vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfmacc(mask, vd, rs1, vs2, vl); return __riscv_vfmacc(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmacc_vv_f16mf4_rm
// CHECK-RV64-SAME: (<vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmacc.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
//
vfloat16mf4_t test_vfmacc_vv_f16mf4_rm(vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfmacc(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmacc_vf_f16mf4_rm
// CHECK-RV64-SAME: (<vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmacc.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
//
vfloat16mf4_t test_vfmacc_vf_f16mf4_rm(vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfmacc(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmacc_vv_f16mf2_rm
// CHECK-RV64-SAME: (<vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmacc.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
//
vfloat16mf2_t test_vfmacc_vv_f16mf2_rm(vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfmacc(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmacc_vf_f16mf2_rm
// CHECK-RV64-SAME: (<vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmacc.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
//
vfloat16mf2_t test_vfmacc_vf_f16mf2_rm(vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfmacc(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmacc_vv_f16m1_rm
// CHECK-RV64-SAME: (<vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmacc.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfmacc_vv_f16m1_rm(vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfmacc(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmacc_vf_f16m1_rm
// CHECK-RV64-SAME: (<vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmacc.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfmacc_vf_f16m1_rm(vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfmacc(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmacc_vv_f16m2_rm
// CHECK-RV64-SAME: (<vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmacc.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
//
vfloat16m2_t test_vfmacc_vv_f16m2_rm(vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfmacc(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmacc_vf_f16m2_rm
// CHECK-RV64-SAME: (<vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmacc.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
//
vfloat16m2_t test_vfmacc_vf_f16m2_rm(vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfmacc(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmacc_vv_f16m4_rm
// CHECK-RV64-SAME: (<vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmacc.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
//
vfloat16m4_t test_vfmacc_vv_f16m4_rm(vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfmacc(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmacc_vf_f16m4_rm
// CHECK-RV64-SAME: (<vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmacc.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
//
vfloat16m4_t test_vfmacc_vf_f16m4_rm(vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfmacc(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmacc_vv_f16m8_rm
// CHECK-RV64-SAME: (<vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmacc.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
//
vfloat16m8_t test_vfmacc_vv_f16m8_rm(vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfmacc(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmacc_vf_f16m8_rm
// CHECK-RV64-SAME: (<vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmacc.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
//
vfloat16m8_t test_vfmacc_vf_f16m8_rm(vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfmacc(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmacc_vv_f32mf2_rm
// CHECK-RV64-SAME: (<vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmacc.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
//
vfloat32mf2_t test_vfmacc_vv_f32mf2_rm(vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfmacc(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmacc_vf_f32mf2_rm
// CHECK-RV64-SAME: (<vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmacc.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
//
vfloat32mf2_t test_vfmacc_vf_f32mf2_rm(vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfmacc(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmacc_vv_f32m1_rm
// CHECK-RV64-SAME: (<vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmacc.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfmacc_vv_f32m1_rm(vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfmacc(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmacc_vf_f32m1_rm
// CHECK-RV64-SAME: (<vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmacc.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfmacc_vf_f32m1_rm(vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfmacc(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmacc_vv_f32m2_rm
// CHECK-RV64-SAME: (<vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmacc.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
//
vfloat32m2_t test_vfmacc_vv_f32m2_rm(vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfmacc(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmacc_vf_f32m2_rm
// CHECK-RV64-SAME: (<vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmacc.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
//
vfloat32m2_t test_vfmacc_vf_f32m2_rm(vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfmacc(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmacc_vv_f32m4_rm
// CHECK-RV64-SAME: (<vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmacc.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
//
vfloat32m4_t test_vfmacc_vv_f32m4_rm(vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfmacc(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmacc_vf_f32m4_rm
// CHECK-RV64-SAME: (<vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmacc.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
//
vfloat32m4_t test_vfmacc_vf_f32m4_rm(vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfmacc(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmacc_vv_f32m8_rm
// CHECK-RV64-SAME: (<vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmacc.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
//
vfloat32m8_t test_vfmacc_vv_f32m8_rm(vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfmacc(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmacc_vf_f32m8_rm
// CHECK-RV64-SAME: (<vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmacc.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
//
vfloat32m8_t test_vfmacc_vf_f32m8_rm(vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfmacc(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmacc_vv_f64m1_rm
// CHECK-RV64-SAME: (<vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmacc.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfmacc_vv_f64m1_rm(vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfmacc(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmacc_vf_f64m1_rm
// CHECK-RV64-SAME: (<vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmacc.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfmacc_vf_f64m1_rm(vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfmacc(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmacc_vv_f64m2_rm
// CHECK-RV64-SAME: (<vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmacc.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
//
vfloat64m2_t test_vfmacc_vv_f64m2_rm(vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfmacc(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmacc_vf_f64m2_rm
// CHECK-RV64-SAME: (<vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmacc.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
//
vfloat64m2_t test_vfmacc_vf_f64m2_rm(vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfmacc(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmacc_vv_f64m4_rm
// CHECK-RV64-SAME: (<vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmacc.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
//
vfloat64m4_t test_vfmacc_vv_f64m4_rm(vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfmacc(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmacc_vf_f64m4_rm
// CHECK-RV64-SAME: (<vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmacc.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
//
vfloat64m4_t test_vfmacc_vf_f64m4_rm(vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfmacc(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmacc_vv_f64m8_rm
// CHECK-RV64-SAME: (<vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmacc.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
//
vfloat64m8_t test_vfmacc_vv_f64m8_rm(vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfmacc(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmacc_vf_f64m8_rm
// CHECK-RV64-SAME: (<vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmacc.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
//
vfloat64m8_t test_vfmacc_vf_f64m8_rm(vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfmacc(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmacc_vv_f16mf4_rm_m
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmacc.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
//
vfloat16mf4_t test_vfmacc_vv_f16mf4_rm_m(vbool64_t mask, vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfmacc(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmacc_vf_f16mf4_rm_m
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmacc.mask.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
//
vfloat16mf4_t test_vfmacc_vf_f16mf4_rm_m(vbool64_t mask, vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfmacc(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmacc_vv_f16mf2_rm_m
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmacc.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
//
vfloat16mf2_t test_vfmacc_vv_f16mf2_rm_m(vbool32_t mask, vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfmacc(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmacc_vf_f16mf2_rm_m
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmacc.mask.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
//
vfloat16mf2_t test_vfmacc_vf_f16mf2_rm_m(vbool32_t mask, vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfmacc(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmacc_vv_f16m1_rm_m
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmacc.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfmacc_vv_f16m1_rm_m(vbool16_t mask, vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfmacc(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmacc_vf_f16m1_rm_m
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmacc.mask.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfmacc_vf_f16m1_rm_m(vbool16_t mask, vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfmacc(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmacc_vv_f16m2_rm_m
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmacc.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
//
vfloat16m2_t test_vfmacc_vv_f16m2_rm_m(vbool8_t mask, vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfmacc(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmacc_vf_f16m2_rm_m
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmacc.mask.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
//
vfloat16m2_t test_vfmacc_vf_f16m2_rm_m(vbool8_t mask, vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfmacc(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmacc_vv_f16m4_rm_m
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmacc.mask.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
//
vfloat16m4_t test_vfmacc_vv_f16m4_rm_m(vbool4_t mask, vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfmacc(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmacc_vf_f16m4_rm_m
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmacc.mask.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
//
vfloat16m4_t test_vfmacc_vf_f16m4_rm_m(vbool4_t mask, vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfmacc(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmacc_vv_f16m8_rm_m
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmacc.mask.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
//
vfloat16m8_t test_vfmacc_vv_f16m8_rm_m(vbool2_t mask, vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfmacc(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmacc_vf_f16m8_rm_m
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmacc.mask.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
//
vfloat16m8_t test_vfmacc_vf_f16m8_rm_m(vbool2_t mask, vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfmacc(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmacc_vv_f32mf2_rm_m
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmacc.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
//
vfloat32mf2_t test_vfmacc_vv_f32mf2_rm_m(vbool64_t mask, vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfmacc(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmacc_vf_f32mf2_rm_m
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmacc.mask.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
//
vfloat32mf2_t test_vfmacc_vf_f32mf2_rm_m(vbool64_t mask, vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfmacc(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmacc_vv_f32m1_rm_m
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmacc.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfmacc_vv_f32m1_rm_m(vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfmacc(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmacc_vf_f32m1_rm_m
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmacc.mask.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfmacc_vf_f32m1_rm_m(vbool32_t mask, vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfmacc(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmacc_vv_f32m2_rm_m
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmacc.mask.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
//
vfloat32m2_t test_vfmacc_vv_f32m2_rm_m(vbool16_t mask, vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfmacc(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmacc_vf_f32m2_rm_m
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmacc.mask.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
//
vfloat32m2_t test_vfmacc_vf_f32m2_rm_m(vbool16_t mask, vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfmacc(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmacc_vv_f32m4_rm_m
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmacc.mask.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
//
vfloat32m4_t test_vfmacc_vv_f32m4_rm_m(vbool8_t mask, vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfmacc(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmacc_vf_f32m4_rm_m
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmacc.mask.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
//
vfloat32m4_t test_vfmacc_vf_f32m4_rm_m(vbool8_t mask, vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfmacc(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmacc_vv_f32m8_rm_m
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmacc.mask.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
//
vfloat32m8_t test_vfmacc_vv_f32m8_rm_m(vbool4_t mask, vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfmacc(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmacc_vf_f32m8_rm_m
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmacc.mask.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
//
vfloat32m8_t test_vfmacc_vf_f32m8_rm_m(vbool4_t mask, vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfmacc(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmacc_vv_f64m1_rm_m
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmacc.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfmacc_vv_f64m1_rm_m(vbool64_t mask, vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfmacc(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmacc_vf_f64m1_rm_m
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmacc.mask.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfmacc_vf_f64m1_rm_m(vbool64_t mask, vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfmacc(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmacc_vv_f64m2_rm_m
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmacc.mask.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
//
vfloat64m2_t test_vfmacc_vv_f64m2_rm_m(vbool32_t mask, vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfmacc(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmacc_vf_f64m2_rm_m
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmacc.mask.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
//
vfloat64m2_t test_vfmacc_vf_f64m2_rm_m(vbool32_t mask, vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfmacc(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmacc_vv_f64m4_rm_m
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmacc.mask.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
//
vfloat64m4_t test_vfmacc_vv_f64m4_rm_m(vbool16_t mask, vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfmacc(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmacc_vf_f64m4_rm_m
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmacc.mask.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
//
vfloat64m4_t test_vfmacc_vf_f64m4_rm_m(vbool16_t mask, vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfmacc(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmacc_vv_f64m8_rm_m
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmacc.mask.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
//
vfloat64m8_t test_vfmacc_vv_f64m8_rm_m(vbool8_t mask, vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfmacc(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmacc_vf_f64m8_rm_m
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmacc.mask.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
//
vfloat64m8_t test_vfmacc_vf_f64m8_rm_m(vbool8_t mask, vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfmacc(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}

clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmadd.c

// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target // REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh \ // RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh \
// RUN: -target-feature +experimental-zvfh -disable-O0-optnone \ // RUN: -target-feature +experimental-zvfh -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ // RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s // RUN: FileCheck --check-prefix=CHECK-RV64 %s
#include <riscv_vector.h> #include <riscv_vector.h>
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmadd_vv_f16mf4 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmadd_vv_f16mf4
// CHECK-RV64-SAME: (<vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK-RV64-SAME: (<vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmadd.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmadd.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
// //
vfloat16mf4_t test_vfmadd_vv_f16mf4(vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) { vfloat16mf4_t test_vfmadd_vv_f16mf4(vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfmadd(vd, vs1, vs2, vl); return __riscv_vfmadd(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmadd_vf_f16mf4 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmadd_vf_f16mf4
// CHECK-RV64-SAME: (<vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmadd.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmadd.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
// //
vfloat16mf4_t test_vfmadd_vf_f16mf4(vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) { vfloat16mf4_t test_vfmadd_vf_f16mf4(vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfmadd(vd, rs1, vs2, vl); return __riscv_vfmadd(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmadd_vv_f16mf2 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmadd_vv_f16mf2
// CHECK-RV64-SAME: (<vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmadd.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmadd.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
// //
vfloat16mf2_t test_vfmadd_vv_f16mf2(vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) { vfloat16mf2_t test_vfmadd_vv_f16mf2(vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfmadd(vd, vs1, vs2, vl); return __riscv_vfmadd(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmadd_vf_f16mf2 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmadd_vf_f16mf2
// CHECK-RV64-SAME: (<vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmadd.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmadd.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
// //
vfloat16mf2_t test_vfmadd_vf_f16mf2(vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) { vfloat16mf2_t test_vfmadd_vf_f16mf2(vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfmadd(vd, rs1, vs2, vl); return __riscv_vfmadd(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmadd_vv_f16m1 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmadd_vv_f16m1
// CHECK-RV64-SAME: (<vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmadd.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmadd.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
// //
vfloat16m1_t test_vfmadd_vv_f16m1(vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) { vfloat16m1_t test_vfmadd_vv_f16m1(vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfmadd(vd, vs1, vs2, vl); return __riscv_vfmadd(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmadd_vf_f16m1 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmadd_vf_f16m1
// CHECK-RV64-SAME: (<vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmadd.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmadd.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
// //
vfloat16m1_t test_vfmadd_vf_f16m1(vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) { vfloat16m1_t test_vfmadd_vf_f16m1(vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfmadd(vd, rs1, vs2, vl); return __riscv_vfmadd(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmadd_vv_f16m2 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmadd_vv_f16m2
// CHECK-RV64-SAME: (<vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmadd.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmadd.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
// //
vfloat16m2_t test_vfmadd_vv_f16m2(vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) { vfloat16m2_t test_vfmadd_vv_f16m2(vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfmadd(vd, vs1, vs2, vl); return __riscv_vfmadd(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmadd_vf_f16m2 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmadd_vf_f16m2
// CHECK-RV64-SAME: (<vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmadd.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmadd.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
// //
vfloat16m2_t test_vfmadd_vf_f16m2(vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) { vfloat16m2_t test_vfmadd_vf_f16m2(vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfmadd(vd, rs1, vs2, vl); return __riscv_vfmadd(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmadd_vv_f16m4 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmadd_vv_f16m4
// CHECK-RV64-SAME: (<vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmadd.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmadd.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
// //
vfloat16m4_t test_vfmadd_vv_f16m4(vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) { vfloat16m4_t test_vfmadd_vv_f16m4(vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfmadd(vd, vs1, vs2, vl); return __riscv_vfmadd(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmadd_vf_f16m4 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmadd_vf_f16m4
// CHECK-RV64-SAME: (<vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmadd.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmadd.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
// //
vfloat16m4_t test_vfmadd_vf_f16m4(vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) { vfloat16m4_t test_vfmadd_vf_f16m4(vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfmadd(vd, rs1, vs2, vl); return __riscv_vfmadd(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmadd_vv_f16m8 // CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmadd_vv_f16m8
// CHECK-RV64-SAME: (<vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmadd.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmadd.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
// //
vfloat16m8_t test_vfmadd_vv_f16m8(vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) { vfloat16m8_t test_vfmadd_vv_f16m8(vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfmadd(vd, vs1, vs2, vl); return __riscv_vfmadd(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmadd_vf_f16m8 // CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmadd_vf_f16m8
// CHECK-RV64-SAME: (<vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmadd.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmadd.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
// //
vfloat16m8_t test_vfmadd_vf_f16m8(vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) { vfloat16m8_t test_vfmadd_vf_f16m8(vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfmadd(vd, rs1, vs2, vl); return __riscv_vfmadd(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmadd_vv_f32mf2 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmadd_vv_f32mf2
// CHECK-RV64-SAME: (<vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmadd.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmadd.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfmadd_vv_f32mf2(vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) { vfloat32mf2_t test_vfmadd_vv_f32mf2(vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfmadd(vd, vs1, vs2, vl); return __riscv_vfmadd(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmadd_vf_f32mf2 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmadd_vf_f32mf2
// CHECK-RV64-SAME: (<vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmadd.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmadd.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfmadd_vf_f32mf2(vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) { vfloat32mf2_t test_vfmadd_vf_f32mf2(vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfmadd(vd, rs1, vs2, vl); return __riscv_vfmadd(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmadd_vv_f32m1 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmadd_vv_f32m1
// CHECK-RV64-SAME: (<vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmadd.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmadd.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfmadd_vv_f32m1(vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) { vfloat32m1_t test_vfmadd_vv_f32m1(vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfmadd(vd, vs1, vs2, vl); return __riscv_vfmadd(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmadd_vf_f32m1 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmadd_vf_f32m1
// CHECK-RV64-SAME: (<vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmadd.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmadd.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfmadd_vf_f32m1(vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) { vfloat32m1_t test_vfmadd_vf_f32m1(vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfmadd(vd, rs1, vs2, vl); return __riscv_vfmadd(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmadd_vv_f32m2 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmadd_vv_f32m2
// CHECK-RV64-SAME: (<vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmadd.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmadd.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfmadd_vv_f32m2(vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) { vfloat32m2_t test_vfmadd_vv_f32m2(vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfmadd(vd, vs1, vs2, vl); return __riscv_vfmadd(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmadd_vf_f32m2 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmadd_vf_f32m2
// CHECK-RV64-SAME: (<vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmadd.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmadd.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfmadd_vf_f32m2(vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) { vfloat32m2_t test_vfmadd_vf_f32m2(vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfmadd(vd, rs1, vs2, vl); return __riscv_vfmadd(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmadd_vv_f32m4 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmadd_vv_f32m4
// CHECK-RV64-SAME: (<vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmadd.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmadd.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfmadd_vv_f32m4(vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) { vfloat32m4_t test_vfmadd_vv_f32m4(vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfmadd(vd, vs1, vs2, vl); return __riscv_vfmadd(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmadd_vf_f32m4 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmadd_vf_f32m4
// CHECK-RV64-SAME: (<vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmadd.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmadd.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfmadd_vf_f32m4(vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) { vfloat32m4_t test_vfmadd_vf_f32m4(vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfmadd(vd, rs1, vs2, vl); return __riscv_vfmadd(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmadd_vv_f32m8 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmadd_vv_f32m8
// CHECK-RV64-SAME: (<vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmadd.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmadd.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfmadd_vv_f32m8(vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) { vfloat32m8_t test_vfmadd_vv_f32m8(vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfmadd(vd, vs1, vs2, vl); return __riscv_vfmadd(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmadd_vf_f32m8 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmadd_vf_f32m8
// CHECK-RV64-SAME: (<vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmadd.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmadd.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfmadd_vf_f32m8(vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) { vfloat32m8_t test_vfmadd_vf_f32m8(vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfmadd(vd, rs1, vs2, vl); return __riscv_vfmadd(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmadd_vv_f64m1 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmadd_vv_f64m1
// CHECK-RV64-SAME: (<vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmadd.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmadd.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfmadd_vv_f64m1(vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) { vfloat64m1_t test_vfmadd_vv_f64m1(vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfmadd(vd, vs1, vs2, vl); return __riscv_vfmadd(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmadd_vf_f64m1 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmadd_vf_f64m1
// CHECK-RV64-SAME: (<vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmadd.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmadd.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfmadd_vf_f64m1(vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) { vfloat64m1_t test_vfmadd_vf_f64m1(vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfmadd(vd, rs1, vs2, vl); return __riscv_vfmadd(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmadd_vv_f64m2 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmadd_vv_f64m2
// CHECK-RV64-SAME: (<vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmadd.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmadd.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfmadd_vv_f64m2(vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) { vfloat64m2_t test_vfmadd_vv_f64m2(vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfmadd(vd, vs1, vs2, vl); return __riscv_vfmadd(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmadd_vf_f64m2 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmadd_vf_f64m2
// CHECK-RV64-SAME: (<vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmadd.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmadd.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfmadd_vf_f64m2(vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) { vfloat64m2_t test_vfmadd_vf_f64m2(vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfmadd(vd, rs1, vs2, vl); return __riscv_vfmadd(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmadd_vv_f64m4 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmadd_vv_f64m4
// CHECK-RV64-SAME: (<vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmadd.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmadd.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfmadd_vv_f64m4(vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) { vfloat64m4_t test_vfmadd_vv_f64m4(vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfmadd(vd, vs1, vs2, vl); return __riscv_vfmadd(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmadd_vf_f64m4 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmadd_vf_f64m4
// CHECK-RV64-SAME: (<vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmadd.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmadd.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfmadd_vf_f64m4(vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) { vfloat64m4_t test_vfmadd_vf_f64m4(vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfmadd(vd, rs1, vs2, vl); return __riscv_vfmadd(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmadd_vv_f64m8 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmadd_vv_f64m8
// CHECK-RV64-SAME: (<vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmadd.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmadd.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfmadd_vv_f64m8(vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) { vfloat64m8_t test_vfmadd_vv_f64m8(vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfmadd(vd, vs1, vs2, vl); return __riscv_vfmadd(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmadd_vf_f64m8 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmadd_vf_f64m8
// CHECK-RV64-SAME: (<vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmadd.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmadd.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfmadd_vf_f64m8(vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) { vfloat64m8_t test_vfmadd_vf_f64m8(vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfmadd(vd, rs1, vs2, vl); return __riscv_vfmadd(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmadd_vv_f16mf4_m // CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmadd_vv_f16mf4_m
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmadd.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmadd.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
// //
vfloat16mf4_t test_vfmadd_vv_f16mf4_m(vbool64_t mask, vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) { vfloat16mf4_t test_vfmadd_vv_f16mf4_m(vbool64_t mask, vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfmadd(mask, vd, vs1, vs2, vl); return __riscv_vfmadd(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmadd_vf_f16mf4_m // CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmadd_vf_f16mf4_m
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmadd.mask.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmadd.mask.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
// //
vfloat16mf4_t test_vfmadd_vf_f16mf4_m(vbool64_t mask, vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) { vfloat16mf4_t test_vfmadd_vf_f16mf4_m(vbool64_t mask, vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfmadd(mask, vd, rs1, vs2, vl); return __riscv_vfmadd(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmadd_vv_f16mf2_m // CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmadd_vv_f16mf2_m
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmadd.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmadd.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
// //
vfloat16mf2_t test_vfmadd_vv_f16mf2_m(vbool32_t mask, vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) { vfloat16mf2_t test_vfmadd_vv_f16mf2_m(vbool32_t mask, vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfmadd(mask, vd, vs1, vs2, vl); return __riscv_vfmadd(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmadd_vf_f16mf2_m // CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmadd_vf_f16mf2_m
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmadd.mask.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmadd.mask.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
// //
vfloat16mf2_t test_vfmadd_vf_f16mf2_m(vbool32_t mask, vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) { vfloat16mf2_t test_vfmadd_vf_f16mf2_m(vbool32_t mask, vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfmadd(mask, vd, rs1, vs2, vl); return __riscv_vfmadd(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmadd_vv_f16m1_m // CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmadd_vv_f16m1_m
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmadd.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmadd.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
// //
vfloat16m1_t test_vfmadd_vv_f16m1_m(vbool16_t mask, vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) { vfloat16m1_t test_vfmadd_vv_f16m1_m(vbool16_t mask, vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfmadd(mask, vd, vs1, vs2, vl); return __riscv_vfmadd(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmadd_vf_f16m1_m // CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmadd_vf_f16m1_m
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmadd.mask.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmadd.mask.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
// //
vfloat16m1_t test_vfmadd_vf_f16m1_m(vbool16_t mask, vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) { vfloat16m1_t test_vfmadd_vf_f16m1_m(vbool16_t mask, vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfmadd(mask, vd, rs1, vs2, vl); return __riscv_vfmadd(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmadd_vv_f16m2_m // CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmadd_vv_f16m2_m
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmadd.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmadd.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
// //
vfloat16m2_t test_vfmadd_vv_f16m2_m(vbool8_t mask, vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) { vfloat16m2_t test_vfmadd_vv_f16m2_m(vbool8_t mask, vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfmadd(mask, vd, vs1, vs2, vl); return __riscv_vfmadd(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmadd_vf_f16m2_m // CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmadd_vf_f16m2_m
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmadd.mask.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmadd.mask.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
// //
vfloat16m2_t test_vfmadd_vf_f16m2_m(vbool8_t mask, vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) { vfloat16m2_t test_vfmadd_vf_f16m2_m(vbool8_t mask, vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfmadd(mask, vd, rs1, vs2, vl); return __riscv_vfmadd(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmadd_vv_f16m4_m // CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmadd_vv_f16m4_m
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmadd.mask.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmadd.mask.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
// //
vfloat16m4_t test_vfmadd_vv_f16m4_m(vbool4_t mask, vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) { vfloat16m4_t test_vfmadd_vv_f16m4_m(vbool4_t mask, vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfmadd(mask, vd, vs1, vs2, vl); return __riscv_vfmadd(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmadd_vf_f16m4_m // CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmadd_vf_f16m4_m
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmadd.mask.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmadd.mask.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
// //
vfloat16m4_t test_vfmadd_vf_f16m4_m(vbool4_t mask, vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) { vfloat16m4_t test_vfmadd_vf_f16m4_m(vbool4_t mask, vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfmadd(mask, vd, rs1, vs2, vl); return __riscv_vfmadd(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmadd_vv_f16m8_m // CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmadd_vv_f16m8_m
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmadd.mask.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmadd.mask.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
// //
vfloat16m8_t test_vfmadd_vv_f16m8_m(vbool2_t mask, vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) { vfloat16m8_t test_vfmadd_vv_f16m8_m(vbool2_t mask, vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfmadd(mask, vd, vs1, vs2, vl); return __riscv_vfmadd(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmadd_vf_f16m8_m // CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmadd_vf_f16m8_m
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmadd.mask.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmadd.mask.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
// //
vfloat16m8_t test_vfmadd_vf_f16m8_m(vbool2_t mask, vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) { vfloat16m8_t test_vfmadd_vf_f16m8_m(vbool2_t mask, vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfmadd(mask, vd, rs1, vs2, vl); return __riscv_vfmadd(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmadd_vv_f32mf2_m // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmadd_vv_f32mf2_m
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmadd.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmadd.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfmadd_vv_f32mf2_m(vbool64_t mask, vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) { vfloat32mf2_t test_vfmadd_vv_f32mf2_m(vbool64_t mask, vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfmadd(mask, vd, vs1, vs2, vl); return __riscv_vfmadd(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmadd_vf_f32mf2_m // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmadd_vf_f32mf2_m
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmadd.mask.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmadd.mask.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfmadd_vf_f32mf2_m(vbool64_t mask, vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) { vfloat32mf2_t test_vfmadd_vf_f32mf2_m(vbool64_t mask, vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfmadd(mask, vd, rs1, vs2, vl); return __riscv_vfmadd(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmadd_vv_f32m1_m // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmadd_vv_f32m1_m
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmadd.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmadd.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfmadd_vv_f32m1_m(vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) { vfloat32m1_t test_vfmadd_vv_f32m1_m(vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfmadd(mask, vd, vs1, vs2, vl); return __riscv_vfmadd(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmadd_vf_f32m1_m // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmadd_vf_f32m1_m
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmadd.mask.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmadd.mask.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfmadd_vf_f32m1_m(vbool32_t mask, vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) { vfloat32m1_t test_vfmadd_vf_f32m1_m(vbool32_t mask, vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfmadd(mask, vd, rs1, vs2, vl); return __riscv_vfmadd(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmadd_vv_f32m2_m // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmadd_vv_f32m2_m
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmadd.mask.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmadd.mask.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfmadd_vv_f32m2_m(vbool16_t mask, vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) { vfloat32m2_t test_vfmadd_vv_f32m2_m(vbool16_t mask, vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfmadd(mask, vd, vs1, vs2, vl); return __riscv_vfmadd(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmadd_vf_f32m2_m // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmadd_vf_f32m2_m
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmadd.mask.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmadd.mask.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfmadd_vf_f32m2_m(vbool16_t mask, vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) { vfloat32m2_t test_vfmadd_vf_f32m2_m(vbool16_t mask, vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfmadd(mask, vd, rs1, vs2, vl); return __riscv_vfmadd(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmadd_vv_f32m4_m // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmadd_vv_f32m4_m
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmadd.mask.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmadd.mask.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfmadd_vv_f32m4_m(vbool8_t mask, vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) { vfloat32m4_t test_vfmadd_vv_f32m4_m(vbool8_t mask, vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfmadd(mask, vd, vs1, vs2, vl); return __riscv_vfmadd(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmadd_vf_f32m4_m // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmadd_vf_f32m4_m
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmadd.mask.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmadd.mask.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfmadd_vf_f32m4_m(vbool8_t mask, vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) { vfloat32m4_t test_vfmadd_vf_f32m4_m(vbool8_t mask, vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfmadd(mask, vd, rs1, vs2, vl); return __riscv_vfmadd(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmadd_vv_f32m8_m // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmadd_vv_f32m8_m
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmadd.mask.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmadd.mask.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfmadd_vv_f32m8_m(vbool4_t mask, vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) { vfloat32m8_t test_vfmadd_vv_f32m8_m(vbool4_t mask, vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfmadd(mask, vd, vs1, vs2, vl); return __riscv_vfmadd(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmadd_vf_f32m8_m // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmadd_vf_f32m8_m
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmadd.mask.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmadd.mask.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfmadd_vf_f32m8_m(vbool4_t mask, vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) { vfloat32m8_t test_vfmadd_vf_f32m8_m(vbool4_t mask, vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfmadd(mask, vd, rs1, vs2, vl); return __riscv_vfmadd(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmadd_vv_f64m1_m // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmadd_vv_f64m1_m
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmadd.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmadd.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfmadd_vv_f64m1_m(vbool64_t mask, vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) { vfloat64m1_t test_vfmadd_vv_f64m1_m(vbool64_t mask, vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfmadd(mask, vd, vs1, vs2, vl); return __riscv_vfmadd(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmadd_vf_f64m1_m // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmadd_vf_f64m1_m
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmadd.mask.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmadd.mask.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfmadd_vf_f64m1_m(vbool64_t mask, vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) { vfloat64m1_t test_vfmadd_vf_f64m1_m(vbool64_t mask, vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfmadd(mask, vd, rs1, vs2, vl); return __riscv_vfmadd(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmadd_vv_f64m2_m // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmadd_vv_f64m2_m
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmadd.mask.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmadd.mask.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfmadd_vv_f64m2_m(vbool32_t mask, vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) { vfloat64m2_t test_vfmadd_vv_f64m2_m(vbool32_t mask, vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfmadd(mask, vd, vs1, vs2, vl); return __riscv_vfmadd(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmadd_vf_f64m2_m // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmadd_vf_f64m2_m
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmadd.mask.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmadd.mask.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfmadd_vf_f64m2_m(vbool32_t mask, vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) { vfloat64m2_t test_vfmadd_vf_f64m2_m(vbool32_t mask, vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfmadd(mask, vd, rs1, vs2, vl); return __riscv_vfmadd(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmadd_vv_f64m4_m // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmadd_vv_f64m4_m
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmadd.mask.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmadd.mask.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfmadd_vv_f64m4_m(vbool16_t mask, vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) { vfloat64m4_t test_vfmadd_vv_f64m4_m(vbool16_t mask, vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfmadd(mask, vd, vs1, vs2, vl); return __riscv_vfmadd(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmadd_vf_f64m4_m // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmadd_vf_f64m4_m
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmadd.mask.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmadd.mask.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfmadd_vf_f64m4_m(vbool16_t mask, vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) { vfloat64m4_t test_vfmadd_vf_f64m4_m(vbool16_t mask, vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfmadd(mask, vd, rs1, vs2, vl); return __riscv_vfmadd(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmadd_vv_f64m8_m // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmadd_vv_f64m8_m
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmadd.mask.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmadd.mask.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfmadd_vv_f64m8_m(vbool8_t mask, vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) { vfloat64m8_t test_vfmadd_vv_f64m8_m(vbool8_t mask, vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfmadd(mask, vd, vs1, vs2, vl); return __riscv_vfmadd(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmadd_vf_f64m8_m // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmadd_vf_f64m8_m
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmadd.mask.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmadd.mask.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfmadd_vf_f64m8_m(vbool8_t mask, vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) { vfloat64m8_t test_vfmadd_vf_f64m8_m(vbool8_t mask, vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfmadd(mask, vd, rs1, vs2, vl); return __riscv_vfmadd(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmadd_vv_f16mf4_rm
// CHECK-RV64-SAME: (<vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmadd.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
//
vfloat16mf4_t test_vfmadd_vv_f16mf4_rm(vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfmadd(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmadd_vf_f16mf4_rm
// CHECK-RV64-SAME: (<vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmadd.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
//
vfloat16mf4_t test_vfmadd_vf_f16mf4_rm(vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfmadd(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmadd_vv_f16mf2_rm
// CHECK-RV64-SAME: (<vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmadd.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
//
vfloat16mf2_t test_vfmadd_vv_f16mf2_rm(vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfmadd(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmadd_vf_f16mf2_rm
// CHECK-RV64-SAME: (<vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmadd.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
//
vfloat16mf2_t test_vfmadd_vf_f16mf2_rm(vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfmadd(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmadd_vv_f16m1_rm
// CHECK-RV64-SAME: (<vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmadd.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfmadd_vv_f16m1_rm(vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfmadd(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmadd_vf_f16m1_rm
// CHECK-RV64-SAME: (<vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmadd.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfmadd_vf_f16m1_rm(vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfmadd(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmadd_vv_f16m2_rm
// CHECK-RV64-SAME: (<vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmadd.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
//
vfloat16m2_t test_vfmadd_vv_f16m2_rm(vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfmadd(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmadd_vf_f16m2_rm
// CHECK-RV64-SAME: (<vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmadd.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
//
vfloat16m2_t test_vfmadd_vf_f16m2_rm(vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfmadd(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmadd_vv_f16m4_rm
// CHECK-RV64-SAME: (<vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmadd.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
//
vfloat16m4_t test_vfmadd_vv_f16m4_rm(vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfmadd(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmadd_vf_f16m4_rm
// CHECK-RV64-SAME: (<vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmadd.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
//
vfloat16m4_t test_vfmadd_vf_f16m4_rm(vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfmadd(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmadd_vv_f16m8_rm
// CHECK-RV64-SAME: (<vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmadd.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
//
vfloat16m8_t test_vfmadd_vv_f16m8_rm(vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfmadd(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmadd_vf_f16m8_rm
// CHECK-RV64-SAME: (<vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmadd.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
//
vfloat16m8_t test_vfmadd_vf_f16m8_rm(vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfmadd(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmadd_vv_f32mf2_rm
// CHECK-RV64-SAME: (<vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmadd.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
//
vfloat32mf2_t test_vfmadd_vv_f32mf2_rm(vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfmadd(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmadd_vf_f32mf2_rm
// CHECK-RV64-SAME: (<vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmadd.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
//
vfloat32mf2_t test_vfmadd_vf_f32mf2_rm(vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfmadd(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmadd_vv_f32m1_rm
// CHECK-RV64-SAME: (<vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmadd.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfmadd_vv_f32m1_rm(vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfmadd(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmadd_vf_f32m1_rm
// CHECK-RV64-SAME: (<vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmadd.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfmadd_vf_f32m1_rm(vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfmadd(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmadd_vv_f32m2_rm
// CHECK-RV64-SAME: (<vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmadd.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
//
vfloat32m2_t test_vfmadd_vv_f32m2_rm(vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfmadd(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmadd_vf_f32m2_rm
// CHECK-RV64-SAME: (<vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmadd.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
//
vfloat32m2_t test_vfmadd_vf_f32m2_rm(vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfmadd(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmadd_vv_f32m4_rm
// CHECK-RV64-SAME: (<vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmadd.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
//
vfloat32m4_t test_vfmadd_vv_f32m4_rm(vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfmadd(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmadd_vf_f32m4_rm
// CHECK-RV64-SAME: (<vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmadd.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
//
vfloat32m4_t test_vfmadd_vf_f32m4_rm(vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfmadd(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmadd_vv_f32m8_rm
// CHECK-RV64-SAME: (<vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmadd.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
//
vfloat32m8_t test_vfmadd_vv_f32m8_rm(vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfmadd(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmadd_vf_f32m8_rm
// CHECK-RV64-SAME: (<vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmadd.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
//
vfloat32m8_t test_vfmadd_vf_f32m8_rm(vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfmadd(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmadd_vv_f64m1_rm
// CHECK-RV64-SAME: (<vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmadd.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfmadd_vv_f64m1_rm(vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfmadd(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmadd_vf_f64m1_rm
// CHECK-RV64-SAME: (<vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmadd.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfmadd_vf_f64m1_rm(vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfmadd(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmadd_vv_f64m2_rm
// CHECK-RV64-SAME: (<vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmadd.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
//
vfloat64m2_t test_vfmadd_vv_f64m2_rm(vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfmadd(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmadd_vf_f64m2_rm
// CHECK-RV64-SAME: (<vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmadd.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
//
vfloat64m2_t test_vfmadd_vf_f64m2_rm(vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfmadd(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmadd_vv_f64m4_rm
// CHECK-RV64-SAME: (<vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmadd.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
//
vfloat64m4_t test_vfmadd_vv_f64m4_rm(vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfmadd(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmadd_vf_f64m4_rm
// CHECK-RV64-SAME: (<vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmadd.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
//
vfloat64m4_t test_vfmadd_vf_f64m4_rm(vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfmadd(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmadd_vv_f64m8_rm
// CHECK-RV64-SAME: (<vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmadd.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
//
vfloat64m8_t test_vfmadd_vv_f64m8_rm(vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfmadd(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmadd_vf_f64m8_rm
// CHECK-RV64-SAME: (<vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmadd.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
//
vfloat64m8_t test_vfmadd_vf_f64m8_rm(vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfmadd(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmadd_vv_f16mf4_rm_m
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmadd.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
//
vfloat16mf4_t test_vfmadd_vv_f16mf4_rm_m(vbool64_t mask, vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfmadd(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmadd_vf_f16mf4_rm_m
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmadd.mask.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
//
vfloat16mf4_t test_vfmadd_vf_f16mf4_rm_m(vbool64_t mask, vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfmadd(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmadd_vv_f16mf2_rm_m
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmadd.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
//
vfloat16mf2_t test_vfmadd_vv_f16mf2_rm_m(vbool32_t mask, vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfmadd(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmadd_vf_f16mf2_rm_m
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmadd.mask.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
//
vfloat16mf2_t test_vfmadd_vf_f16mf2_rm_m(vbool32_t mask, vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfmadd(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmadd_vv_f16m1_rm_m
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmadd.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfmadd_vv_f16m1_rm_m(vbool16_t mask, vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfmadd(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmadd_vf_f16m1_rm_m
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmadd.mask.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfmadd_vf_f16m1_rm_m(vbool16_t mask, vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfmadd(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmadd_vv_f16m2_rm_m
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmadd.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
//
vfloat16m2_t test_vfmadd_vv_f16m2_rm_m(vbool8_t mask, vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfmadd(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmadd_vf_f16m2_rm_m
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmadd.mask.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
//
vfloat16m2_t test_vfmadd_vf_f16m2_rm_m(vbool8_t mask, vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfmadd(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmadd_vv_f16m4_rm_m
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmadd.mask.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
//
vfloat16m4_t test_vfmadd_vv_f16m4_rm_m(vbool4_t mask, vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfmadd(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmadd_vf_f16m4_rm_m
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmadd.mask.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
//
vfloat16m4_t test_vfmadd_vf_f16m4_rm_m(vbool4_t mask, vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfmadd(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmadd_vv_f16m8_rm_m
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmadd.mask.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
//
vfloat16m8_t test_vfmadd_vv_f16m8_rm_m(vbool2_t mask, vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfmadd(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmadd_vf_f16m8_rm_m
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmadd.mask.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
//
vfloat16m8_t test_vfmadd_vf_f16m8_rm_m(vbool2_t mask, vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfmadd(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmadd_vv_f32mf2_rm_m
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmadd.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
//
vfloat32mf2_t test_vfmadd_vv_f32mf2_rm_m(vbool64_t mask, vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfmadd(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmadd_vf_f32mf2_rm_m
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmadd.mask.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
//
vfloat32mf2_t test_vfmadd_vf_f32mf2_rm_m(vbool64_t mask, vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfmadd(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmadd_vv_f32m1_rm_m
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmadd.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfmadd_vv_f32m1_rm_m(vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfmadd(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmadd_vf_f32m1_rm_m
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmadd.mask.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfmadd_vf_f32m1_rm_m(vbool32_t mask, vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfmadd(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmadd_vv_f32m2_rm_m
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmadd.mask.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
//
vfloat32m2_t test_vfmadd_vv_f32m2_rm_m(vbool16_t mask, vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfmadd(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmadd_vf_f32m2_rm_m
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmadd.mask.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
//
vfloat32m2_t test_vfmadd_vf_f32m2_rm_m(vbool16_t mask, vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfmadd(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmadd_vv_f32m4_rm_m
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmadd.mask.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
//
vfloat32m4_t test_vfmadd_vv_f32m4_rm_m(vbool8_t mask, vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfmadd(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmadd_vf_f32m4_rm_m
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmadd.mask.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
//
vfloat32m4_t test_vfmadd_vf_f32m4_rm_m(vbool8_t mask, vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfmadd(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmadd_vv_f32m8_rm_m
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmadd.mask.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
//
vfloat32m8_t test_vfmadd_vv_f32m8_rm_m(vbool4_t mask, vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfmadd(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmadd_vf_f32m8_rm_m
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmadd.mask.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
//
vfloat32m8_t test_vfmadd_vf_f32m8_rm_m(vbool4_t mask, vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfmadd(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmadd_vv_f64m1_rm_m
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmadd.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfmadd_vv_f64m1_rm_m(vbool64_t mask, vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfmadd(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmadd_vf_f64m1_rm_m
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmadd.mask.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfmadd_vf_f64m1_rm_m(vbool64_t mask, vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfmadd(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmadd_vv_f64m2_rm_m
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmadd.mask.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
//
vfloat64m2_t test_vfmadd_vv_f64m2_rm_m(vbool32_t mask, vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfmadd(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmadd_vf_f64m2_rm_m
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmadd.mask.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
//
vfloat64m2_t test_vfmadd_vf_f64m2_rm_m(vbool32_t mask, vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfmadd(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmadd_vv_f64m4_rm_m
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmadd.mask.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
//
vfloat64m4_t test_vfmadd_vv_f64m4_rm_m(vbool16_t mask, vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfmadd(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmadd_vf_f64m4_rm_m
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmadd.mask.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
//
vfloat64m4_t test_vfmadd_vf_f64m4_rm_m(vbool16_t mask, vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfmadd(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmadd_vv_f64m8_rm_m
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmadd.mask.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
//
vfloat64m8_t test_vfmadd_vv_f64m8_rm_m(vbool8_t mask, vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfmadd(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmadd_vf_f64m8_rm_m
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmadd.mask.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
//
vfloat64m8_t test_vfmadd_vf_f64m8_rm_m(vbool8_t mask, vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfmadd(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}

clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmsac.c

// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target // REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh \ // RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh \
// RUN: -target-feature +experimental-zvfh -disable-O0-optnone \ // RUN: -target-feature +experimental-zvfh -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ // RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s // RUN: FileCheck --check-prefix=CHECK-RV64 %s
#include <riscv_vector.h> #include <riscv_vector.h>
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmsac_vv_f16mf4 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmsac_vv_f16mf4
// CHECK-RV64-SAME: (<vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK-RV64-SAME: (<vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmsac.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmsac.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
// //
vfloat16mf4_t test_vfmsac_vv_f16mf4(vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) { vfloat16mf4_t test_vfmsac_vv_f16mf4(vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfmsac(vd, vs1, vs2, vl); return __riscv_vfmsac(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmsac_vf_f16mf4 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmsac_vf_f16mf4
// CHECK-RV64-SAME: (<vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmsac.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmsac.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
// //
vfloat16mf4_t test_vfmsac_vf_f16mf4(vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) { vfloat16mf4_t test_vfmsac_vf_f16mf4(vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfmsac(vd, rs1, vs2, vl); return __riscv_vfmsac(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmsac_vv_f16mf2 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmsac_vv_f16mf2
// CHECK-RV64-SAME: (<vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmsac.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmsac.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
// //
vfloat16mf2_t test_vfmsac_vv_f16mf2(vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) { vfloat16mf2_t test_vfmsac_vv_f16mf2(vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfmsac(vd, vs1, vs2, vl); return __riscv_vfmsac(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmsac_vf_f16mf2 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmsac_vf_f16mf2
// CHECK-RV64-SAME: (<vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmsac.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmsac.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
// //
vfloat16mf2_t test_vfmsac_vf_f16mf2(vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) { vfloat16mf2_t test_vfmsac_vf_f16mf2(vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfmsac(vd, rs1, vs2, vl); return __riscv_vfmsac(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmsac_vv_f16m1 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmsac_vv_f16m1
// CHECK-RV64-SAME: (<vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmsac.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmsac.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
// //
vfloat16m1_t test_vfmsac_vv_f16m1(vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) { vfloat16m1_t test_vfmsac_vv_f16m1(vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfmsac(vd, vs1, vs2, vl); return __riscv_vfmsac(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmsac_vf_f16m1 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmsac_vf_f16m1
// CHECK-RV64-SAME: (<vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmsac.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmsac.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
// //
vfloat16m1_t test_vfmsac_vf_f16m1(vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) { vfloat16m1_t test_vfmsac_vf_f16m1(vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfmsac(vd, rs1, vs2, vl); return __riscv_vfmsac(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmsac_vv_f16m2 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmsac_vv_f16m2
// CHECK-RV64-SAME: (<vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmsac.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmsac.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
// //
vfloat16m2_t test_vfmsac_vv_f16m2(vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) { vfloat16m2_t test_vfmsac_vv_f16m2(vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfmsac(vd, vs1, vs2, vl); return __riscv_vfmsac(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmsac_vf_f16m2 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmsac_vf_f16m2
// CHECK-RV64-SAME: (<vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmsac.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmsac.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
// //
vfloat16m2_t test_vfmsac_vf_f16m2(vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) { vfloat16m2_t test_vfmsac_vf_f16m2(vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfmsac(vd, rs1, vs2, vl); return __riscv_vfmsac(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmsac_vv_f16m4 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmsac_vv_f16m4
// CHECK-RV64-SAME: (<vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmsac.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmsac.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
// //
vfloat16m4_t test_vfmsac_vv_f16m4(vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) { vfloat16m4_t test_vfmsac_vv_f16m4(vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfmsac(vd, vs1, vs2, vl); return __riscv_vfmsac(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmsac_vf_f16m4 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmsac_vf_f16m4
// CHECK-RV64-SAME: (<vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmsac.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmsac.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
// //
vfloat16m4_t test_vfmsac_vf_f16m4(vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) { vfloat16m4_t test_vfmsac_vf_f16m4(vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfmsac(vd, rs1, vs2, vl); return __riscv_vfmsac(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmsac_vv_f16m8 // CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmsac_vv_f16m8
// CHECK-RV64-SAME: (<vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmsac.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmsac.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
// //
vfloat16m8_t test_vfmsac_vv_f16m8(vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) { vfloat16m8_t test_vfmsac_vv_f16m8(vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfmsac(vd, vs1, vs2, vl); return __riscv_vfmsac(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmsac_vf_f16m8 // CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmsac_vf_f16m8
// CHECK-RV64-SAME: (<vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmsac.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmsac.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
// //
vfloat16m8_t test_vfmsac_vf_f16m8(vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) { vfloat16m8_t test_vfmsac_vf_f16m8(vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfmsac(vd, rs1, vs2, vl); return __riscv_vfmsac(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmsac_vv_f32mf2 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmsac_vv_f32mf2
// CHECK-RV64-SAME: (<vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmsac.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmsac.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfmsac_vv_f32mf2(vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) { vfloat32mf2_t test_vfmsac_vv_f32mf2(vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfmsac(vd, vs1, vs2, vl); return __riscv_vfmsac(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmsac_vf_f32mf2 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmsac_vf_f32mf2
// CHECK-RV64-SAME: (<vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmsac.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmsac.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfmsac_vf_f32mf2(vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) { vfloat32mf2_t test_vfmsac_vf_f32mf2(vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfmsac(vd, rs1, vs2, vl); return __riscv_vfmsac(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmsac_vv_f32m1 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmsac_vv_f32m1
// CHECK-RV64-SAME: (<vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmsac.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmsac.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfmsac_vv_f32m1(vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) { vfloat32m1_t test_vfmsac_vv_f32m1(vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfmsac(vd, vs1, vs2, vl); return __riscv_vfmsac(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmsac_vf_f32m1 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmsac_vf_f32m1
// CHECK-RV64-SAME: (<vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmsac.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmsac.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfmsac_vf_f32m1(vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) { vfloat32m1_t test_vfmsac_vf_f32m1(vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfmsac(vd, rs1, vs2, vl); return __riscv_vfmsac(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmsac_vv_f32m2 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmsac_vv_f32m2
// CHECK-RV64-SAME: (<vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmsac.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmsac.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfmsac_vv_f32m2(vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) { vfloat32m2_t test_vfmsac_vv_f32m2(vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfmsac(vd, vs1, vs2, vl); return __riscv_vfmsac(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmsac_vf_f32m2 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmsac_vf_f32m2
// CHECK-RV64-SAME: (<vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmsac.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmsac.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfmsac_vf_f32m2(vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) { vfloat32m2_t test_vfmsac_vf_f32m2(vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfmsac(vd, rs1, vs2, vl); return __riscv_vfmsac(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmsac_vv_f32m4 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmsac_vv_f32m4
// CHECK-RV64-SAME: (<vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmsac.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmsac.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfmsac_vv_f32m4(vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) { vfloat32m4_t test_vfmsac_vv_f32m4(vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfmsac(vd, vs1, vs2, vl); return __riscv_vfmsac(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmsac_vf_f32m4 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmsac_vf_f32m4
// CHECK-RV64-SAME: (<vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmsac.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmsac.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfmsac_vf_f32m4(vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) { vfloat32m4_t test_vfmsac_vf_f32m4(vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfmsac(vd, rs1, vs2, vl); return __riscv_vfmsac(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmsac_vv_f32m8 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmsac_vv_f32m8
// CHECK-RV64-SAME: (<vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmsac.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmsac.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfmsac_vv_f32m8(vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) { vfloat32m8_t test_vfmsac_vv_f32m8(vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfmsac(vd, vs1, vs2, vl); return __riscv_vfmsac(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmsac_vf_f32m8 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmsac_vf_f32m8
// CHECK-RV64-SAME: (<vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmsac.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmsac.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfmsac_vf_f32m8(vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) { vfloat32m8_t test_vfmsac_vf_f32m8(vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfmsac(vd, rs1, vs2, vl); return __riscv_vfmsac(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmsac_vv_f64m1 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmsac_vv_f64m1
// CHECK-RV64-SAME: (<vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmsac.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmsac.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfmsac_vv_f64m1(vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) { vfloat64m1_t test_vfmsac_vv_f64m1(vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfmsac(vd, vs1, vs2, vl); return __riscv_vfmsac(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmsac_vf_f64m1 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmsac_vf_f64m1
// CHECK-RV64-SAME: (<vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmsac.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmsac.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfmsac_vf_f64m1(vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) { vfloat64m1_t test_vfmsac_vf_f64m1(vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfmsac(vd, rs1, vs2, vl); return __riscv_vfmsac(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmsac_vv_f64m2 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmsac_vv_f64m2
// CHECK-RV64-SAME: (<vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmsac.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmsac.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfmsac_vv_f64m2(vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) { vfloat64m2_t test_vfmsac_vv_f64m2(vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfmsac(vd, vs1, vs2, vl); return __riscv_vfmsac(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmsac_vf_f64m2 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmsac_vf_f64m2
// CHECK-RV64-SAME: (<vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmsac.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmsac.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfmsac_vf_f64m2(vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) { vfloat64m2_t test_vfmsac_vf_f64m2(vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfmsac(vd, rs1, vs2, vl); return __riscv_vfmsac(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmsac_vv_f64m4 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmsac_vv_f64m4
// CHECK-RV64-SAME: (<vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmsac.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmsac.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfmsac_vv_f64m4(vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) { vfloat64m4_t test_vfmsac_vv_f64m4(vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfmsac(vd, vs1, vs2, vl); return __riscv_vfmsac(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmsac_vf_f64m4 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmsac_vf_f64m4
// CHECK-RV64-SAME: (<vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmsac.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmsac.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfmsac_vf_f64m4(vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) { vfloat64m4_t test_vfmsac_vf_f64m4(vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfmsac(vd, rs1, vs2, vl); return __riscv_vfmsac(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmsac_vv_f64m8 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmsac_vv_f64m8
// CHECK-RV64-SAME: (<vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmsac.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmsac.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfmsac_vv_f64m8(vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) { vfloat64m8_t test_vfmsac_vv_f64m8(vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfmsac(vd, vs1, vs2, vl); return __riscv_vfmsac(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmsac_vf_f64m8 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmsac_vf_f64m8
// CHECK-RV64-SAME: (<vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmsac.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmsac.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfmsac_vf_f64m8(vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) { vfloat64m8_t test_vfmsac_vf_f64m8(vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfmsac(vd, rs1, vs2, vl); return __riscv_vfmsac(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmsac_vv_f16mf4_m // CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmsac_vv_f16mf4_m
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmsac.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmsac.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
// //
vfloat16mf4_t test_vfmsac_vv_f16mf4_m(vbool64_t mask, vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) { vfloat16mf4_t test_vfmsac_vv_f16mf4_m(vbool64_t mask, vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfmsac(mask, vd, vs1, vs2, vl); return __riscv_vfmsac(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmsac_vf_f16mf4_m // CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmsac_vf_f16mf4_m
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmsac.mask.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmsac.mask.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
// //
vfloat16mf4_t test_vfmsac_vf_f16mf4_m(vbool64_t mask, vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) { vfloat16mf4_t test_vfmsac_vf_f16mf4_m(vbool64_t mask, vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfmsac(mask, vd, rs1, vs2, vl); return __riscv_vfmsac(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmsac_vv_f16mf2_m // CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmsac_vv_f16mf2_m
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmsac.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmsac.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
// //
vfloat16mf2_t test_vfmsac_vv_f16mf2_m(vbool32_t mask, vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) { vfloat16mf2_t test_vfmsac_vv_f16mf2_m(vbool32_t mask, vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfmsac(mask, vd, vs1, vs2, vl); return __riscv_vfmsac(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmsac_vf_f16mf2_m // CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmsac_vf_f16mf2_m
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmsac.mask.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmsac.mask.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
// //
vfloat16mf2_t test_vfmsac_vf_f16mf2_m(vbool32_t mask, vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) { vfloat16mf2_t test_vfmsac_vf_f16mf2_m(vbool32_t mask, vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfmsac(mask, vd, rs1, vs2, vl); return __riscv_vfmsac(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmsac_vv_f16m1_m // CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmsac_vv_f16m1_m
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmsac.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmsac.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
// //
vfloat16m1_t test_vfmsac_vv_f16m1_m(vbool16_t mask, vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) { vfloat16m1_t test_vfmsac_vv_f16m1_m(vbool16_t mask, vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfmsac(mask, vd, vs1, vs2, vl); return __riscv_vfmsac(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmsac_vf_f16m1_m // CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmsac_vf_f16m1_m
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmsac.mask.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmsac.mask.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
// //
vfloat16m1_t test_vfmsac_vf_f16m1_m(vbool16_t mask, vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) { vfloat16m1_t test_vfmsac_vf_f16m1_m(vbool16_t mask, vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfmsac(mask, vd, rs1, vs2, vl); return __riscv_vfmsac(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmsac_vv_f16m2_m // CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmsac_vv_f16m2_m
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmsac.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmsac.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
// //
vfloat16m2_t test_vfmsac_vv_f16m2_m(vbool8_t mask, vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) { vfloat16m2_t test_vfmsac_vv_f16m2_m(vbool8_t mask, vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfmsac(mask, vd, vs1, vs2, vl); return __riscv_vfmsac(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmsac_vf_f16m2_m // CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmsac_vf_f16m2_m
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmsac.mask.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmsac.mask.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
// //
vfloat16m2_t test_vfmsac_vf_f16m2_m(vbool8_t mask, vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) { vfloat16m2_t test_vfmsac_vf_f16m2_m(vbool8_t mask, vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfmsac(mask, vd, rs1, vs2, vl); return __riscv_vfmsac(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmsac_vv_f16m4_m // CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmsac_vv_f16m4_m
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmsac.mask.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmsac.mask.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
// //
vfloat16m4_t test_vfmsac_vv_f16m4_m(vbool4_t mask, vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) { vfloat16m4_t test_vfmsac_vv_f16m4_m(vbool4_t mask, vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfmsac(mask, vd, vs1, vs2, vl); return __riscv_vfmsac(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmsac_vf_f16m4_m // CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmsac_vf_f16m4_m
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmsac.mask.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmsac.mask.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
// //
vfloat16m4_t test_vfmsac_vf_f16m4_m(vbool4_t mask, vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) { vfloat16m4_t test_vfmsac_vf_f16m4_m(vbool4_t mask, vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfmsac(mask, vd, rs1, vs2, vl); return __riscv_vfmsac(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmsac_vv_f16m8_m // CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmsac_vv_f16m8_m
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmsac.mask.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmsac.mask.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
// //
vfloat16m8_t test_vfmsac_vv_f16m8_m(vbool2_t mask, vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) { vfloat16m8_t test_vfmsac_vv_f16m8_m(vbool2_t mask, vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfmsac(mask, vd, vs1, vs2, vl); return __riscv_vfmsac(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmsac_vf_f16m8_m // CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmsac_vf_f16m8_m
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmsac.mask.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmsac.mask.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
// //
vfloat16m8_t test_vfmsac_vf_f16m8_m(vbool2_t mask, vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) { vfloat16m8_t test_vfmsac_vf_f16m8_m(vbool2_t mask, vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfmsac(mask, vd, rs1, vs2, vl); return __riscv_vfmsac(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmsac_vv_f32mf2_m // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmsac_vv_f32mf2_m
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmsac.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmsac.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfmsac_vv_f32mf2_m(vbool64_t mask, vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) { vfloat32mf2_t test_vfmsac_vv_f32mf2_m(vbool64_t mask, vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfmsac(mask, vd, vs1, vs2, vl); return __riscv_vfmsac(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmsac_vf_f32mf2_m // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmsac_vf_f32mf2_m
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmsac.mask.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmsac.mask.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfmsac_vf_f32mf2_m(vbool64_t mask, vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) { vfloat32mf2_t test_vfmsac_vf_f32mf2_m(vbool64_t mask, vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfmsac(mask, vd, rs1, vs2, vl); return __riscv_vfmsac(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmsac_vv_f32m1_m // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmsac_vv_f32m1_m
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmsac.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmsac.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfmsac_vv_f32m1_m(vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) { vfloat32m1_t test_vfmsac_vv_f32m1_m(vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfmsac(mask, vd, vs1, vs2, vl); return __riscv_vfmsac(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmsac_vf_f32m1_m // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmsac_vf_f32m1_m
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmsac.mask.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmsac.mask.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfmsac_vf_f32m1_m(vbool32_t mask, vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) { vfloat32m1_t test_vfmsac_vf_f32m1_m(vbool32_t mask, vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfmsac(mask, vd, rs1, vs2, vl); return __riscv_vfmsac(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmsac_vv_f32m2_m // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmsac_vv_f32m2_m
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmsac.mask.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmsac.mask.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfmsac_vv_f32m2_m(vbool16_t mask, vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) { vfloat32m2_t test_vfmsac_vv_f32m2_m(vbool16_t mask, vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfmsac(mask, vd, vs1, vs2, vl); return __riscv_vfmsac(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmsac_vf_f32m2_m // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmsac_vf_f32m2_m
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmsac.mask.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmsac.mask.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfmsac_vf_f32m2_m(vbool16_t mask, vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) { vfloat32m2_t test_vfmsac_vf_f32m2_m(vbool16_t mask, vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfmsac(mask, vd, rs1, vs2, vl); return __riscv_vfmsac(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmsac_vv_f32m4_m // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmsac_vv_f32m4_m
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmsac.mask.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmsac.mask.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfmsac_vv_f32m4_m(vbool8_t mask, vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) { vfloat32m4_t test_vfmsac_vv_f32m4_m(vbool8_t mask, vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfmsac(mask, vd, vs1, vs2, vl); return __riscv_vfmsac(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmsac_vf_f32m4_m // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmsac_vf_f32m4_m
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmsac.mask.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmsac.mask.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfmsac_vf_f32m4_m(vbool8_t mask, vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) { vfloat32m4_t test_vfmsac_vf_f32m4_m(vbool8_t mask, vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfmsac(mask, vd, rs1, vs2, vl); return __riscv_vfmsac(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmsac_vv_f32m8_m // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmsac_vv_f32m8_m
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmsac.mask.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmsac.mask.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfmsac_vv_f32m8_m(vbool4_t mask, vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) { vfloat32m8_t test_vfmsac_vv_f32m8_m(vbool4_t mask, vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfmsac(mask, vd, vs1, vs2, vl); return __riscv_vfmsac(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmsac_vf_f32m8_m // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmsac_vf_f32m8_m
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmsac.mask.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmsac.mask.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfmsac_vf_f32m8_m(vbool4_t mask, vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) { vfloat32m8_t test_vfmsac_vf_f32m8_m(vbool4_t mask, vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfmsac(mask, vd, rs1, vs2, vl); return __riscv_vfmsac(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmsac_vv_f64m1_m // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmsac_vv_f64m1_m
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmsac.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmsac.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfmsac_vv_f64m1_m(vbool64_t mask, vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) { vfloat64m1_t test_vfmsac_vv_f64m1_m(vbool64_t mask, vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfmsac(mask, vd, vs1, vs2, vl); return __riscv_vfmsac(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmsac_vf_f64m1_m // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmsac_vf_f64m1_m
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmsac.mask.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmsac.mask.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfmsac_vf_f64m1_m(vbool64_t mask, vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) { vfloat64m1_t test_vfmsac_vf_f64m1_m(vbool64_t mask, vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfmsac(mask, vd, rs1, vs2, vl); return __riscv_vfmsac(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmsac_vv_f64m2_m // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmsac_vv_f64m2_m
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmsac.mask.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmsac.mask.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfmsac_vv_f64m2_m(vbool32_t mask, vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) { vfloat64m2_t test_vfmsac_vv_f64m2_m(vbool32_t mask, vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfmsac(mask, vd, vs1, vs2, vl); return __riscv_vfmsac(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmsac_vf_f64m2_m // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmsac_vf_f64m2_m
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmsac.mask.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmsac.mask.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfmsac_vf_f64m2_m(vbool32_t mask, vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) { vfloat64m2_t test_vfmsac_vf_f64m2_m(vbool32_t mask, vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfmsac(mask, vd, rs1, vs2, vl); return __riscv_vfmsac(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmsac_vv_f64m4_m // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmsac_vv_f64m4_m
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmsac.mask.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmsac.mask.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfmsac_vv_f64m4_m(vbool16_t mask, vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) { vfloat64m4_t test_vfmsac_vv_f64m4_m(vbool16_t mask, vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfmsac(mask, vd, vs1, vs2, vl); return __riscv_vfmsac(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmsac_vf_f64m4_m // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmsac_vf_f64m4_m
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmsac.mask.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmsac.mask.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfmsac_vf_f64m4_m(vbool16_t mask, vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) { vfloat64m4_t test_vfmsac_vf_f64m4_m(vbool16_t mask, vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfmsac(mask, vd, rs1, vs2, vl); return __riscv_vfmsac(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmsac_vv_f64m8_m // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmsac_vv_f64m8_m
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmsac.mask.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmsac.mask.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfmsac_vv_f64m8_m(vbool8_t mask, vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) { vfloat64m8_t test_vfmsac_vv_f64m8_m(vbool8_t mask, vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfmsac(mask, vd, vs1, vs2, vl); return __riscv_vfmsac(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmsac_vf_f64m8_m // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmsac_vf_f64m8_m
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmsac.mask.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmsac.mask.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfmsac_vf_f64m8_m(vbool8_t mask, vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) { vfloat64m8_t test_vfmsac_vf_f64m8_m(vbool8_t mask, vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfmsac(mask, vd, rs1, vs2, vl); return __riscv_vfmsac(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmsac_vv_f16mf4_rm
// CHECK-RV64-SAME: (<vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmsac.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
//
vfloat16mf4_t test_vfmsac_vv_f16mf4_rm(vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfmsac(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmsac_vf_f16mf4_rm
// CHECK-RV64-SAME: (<vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmsac.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
//
vfloat16mf4_t test_vfmsac_vf_f16mf4_rm(vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfmsac(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmsac_vv_f16mf2_rm
// CHECK-RV64-SAME: (<vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmsac.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
//
vfloat16mf2_t test_vfmsac_vv_f16mf2_rm(vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfmsac(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmsac_vf_f16mf2_rm
// CHECK-RV64-SAME: (<vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmsac.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
//
vfloat16mf2_t test_vfmsac_vf_f16mf2_rm(vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfmsac(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmsac_vv_f16m1_rm
// CHECK-RV64-SAME: (<vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmsac.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfmsac_vv_f16m1_rm(vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfmsac(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmsac_vf_f16m1_rm
// CHECK-RV64-SAME: (<vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmsac.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfmsac_vf_f16m1_rm(vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfmsac(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmsac_vv_f16m2_rm
// CHECK-RV64-SAME: (<vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmsac.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
//
vfloat16m2_t test_vfmsac_vv_f16m2_rm(vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfmsac(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmsac_vf_f16m2_rm
// CHECK-RV64-SAME: (<vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmsac.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
//
vfloat16m2_t test_vfmsac_vf_f16m2_rm(vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfmsac(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmsac_vv_f16m4_rm
// CHECK-RV64-SAME: (<vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmsac.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
//
vfloat16m4_t test_vfmsac_vv_f16m4_rm(vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfmsac(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmsac_vf_f16m4_rm
// CHECK-RV64-SAME: (<vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmsac.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
//
vfloat16m4_t test_vfmsac_vf_f16m4_rm(vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfmsac(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmsac_vv_f16m8_rm
// CHECK-RV64-SAME: (<vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmsac.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
//
vfloat16m8_t test_vfmsac_vv_f16m8_rm(vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfmsac(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmsac_vf_f16m8_rm
// CHECK-RV64-SAME: (<vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmsac.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
//
vfloat16m8_t test_vfmsac_vf_f16m8_rm(vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfmsac(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmsac_vv_f32mf2_rm
// CHECK-RV64-SAME: (<vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmsac.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
//
vfloat32mf2_t test_vfmsac_vv_f32mf2_rm(vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfmsac(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmsac_vf_f32mf2_rm
// CHECK-RV64-SAME: (<vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmsac.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
//
vfloat32mf2_t test_vfmsac_vf_f32mf2_rm(vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfmsac(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmsac_vv_f32m1_rm
// CHECK-RV64-SAME: (<vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmsac.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfmsac_vv_f32m1_rm(vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfmsac(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmsac_vf_f32m1_rm
// CHECK-RV64-SAME: (<vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmsac.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfmsac_vf_f32m1_rm(vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfmsac(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmsac_vv_f32m2_rm
// CHECK-RV64-SAME: (<vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmsac.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
//
vfloat32m2_t test_vfmsac_vv_f32m2_rm(vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfmsac(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmsac_vf_f32m2_rm
// CHECK-RV64-SAME: (<vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmsac.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
//
vfloat32m2_t test_vfmsac_vf_f32m2_rm(vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfmsac(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmsac_vv_f32m4_rm
// CHECK-RV64-SAME: (<vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmsac.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
//
vfloat32m4_t test_vfmsac_vv_f32m4_rm(vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfmsac(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmsac_vf_f32m4_rm
// CHECK-RV64-SAME: (<vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmsac.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
//
vfloat32m4_t test_vfmsac_vf_f32m4_rm(vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfmsac(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmsac_vv_f32m8_rm
// CHECK-RV64-SAME: (<vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmsac.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
//
vfloat32m8_t test_vfmsac_vv_f32m8_rm(vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfmsac(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmsac_vf_f32m8_rm
// CHECK-RV64-SAME: (<vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmsac.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
//
vfloat32m8_t test_vfmsac_vf_f32m8_rm(vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfmsac(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmsac_vv_f64m1_rm
// CHECK-RV64-SAME: (<vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmsac.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfmsac_vv_f64m1_rm(vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfmsac(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmsac_vf_f64m1_rm
// CHECK-RV64-SAME: (<vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmsac.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfmsac_vf_f64m1_rm(vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfmsac(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmsac_vv_f64m2_rm
// CHECK-RV64-SAME: (<vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmsac.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
//
vfloat64m2_t test_vfmsac_vv_f64m2_rm(vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfmsac(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmsac_vf_f64m2_rm
// CHECK-RV64-SAME: (<vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmsac.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
//
vfloat64m2_t test_vfmsac_vf_f64m2_rm(vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfmsac(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmsac_vv_f64m4_rm
// CHECK-RV64-SAME: (<vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmsac.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
//
vfloat64m4_t test_vfmsac_vv_f64m4_rm(vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfmsac(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmsac_vf_f64m4_rm
// CHECK-RV64-SAME: (<vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmsac.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
//
vfloat64m4_t test_vfmsac_vf_f64m4_rm(vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfmsac(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmsac_vv_f64m8_rm
// CHECK-RV64-SAME: (<vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmsac.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
//
vfloat64m8_t test_vfmsac_vv_f64m8_rm(vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfmsac(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmsac_vf_f64m8_rm
// CHECK-RV64-SAME: (<vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmsac.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
//
vfloat64m8_t test_vfmsac_vf_f64m8_rm(vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfmsac(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmsac_vv_f16mf4_rm_m
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmsac.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
//
vfloat16mf4_t test_vfmsac_vv_f16mf4_rm_m(vbool64_t mask, vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfmsac(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmsac_vf_f16mf4_rm_m
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmsac.mask.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
//
vfloat16mf4_t test_vfmsac_vf_f16mf4_rm_m(vbool64_t mask, vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfmsac(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmsac_vv_f16mf2_rm_m
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmsac.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
//
vfloat16mf2_t test_vfmsac_vv_f16mf2_rm_m(vbool32_t mask, vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfmsac(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmsac_vf_f16mf2_rm_m
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmsac.mask.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
//
vfloat16mf2_t test_vfmsac_vf_f16mf2_rm_m(vbool32_t mask, vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfmsac(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmsac_vv_f16m1_rm_m
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmsac.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfmsac_vv_f16m1_rm_m(vbool16_t mask, vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfmsac(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmsac_vf_f16m1_rm_m
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmsac.mask.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfmsac_vf_f16m1_rm_m(vbool16_t mask, vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfmsac(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmsac_vv_f16m2_rm_m
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmsac.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
//
vfloat16m2_t test_vfmsac_vv_f16m2_rm_m(vbool8_t mask, vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfmsac(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmsac_vf_f16m2_rm_m
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmsac.mask.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
//
vfloat16m2_t test_vfmsac_vf_f16m2_rm_m(vbool8_t mask, vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfmsac(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmsac_vv_f16m4_rm_m
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmsac.mask.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
//
vfloat16m4_t test_vfmsac_vv_f16m4_rm_m(vbool4_t mask, vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfmsac(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmsac_vf_f16m4_rm_m
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmsac.mask.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
//
vfloat16m4_t test_vfmsac_vf_f16m4_rm_m(vbool4_t mask, vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfmsac(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmsac_vv_f16m8_rm_m
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmsac.mask.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
//
vfloat16m8_t test_vfmsac_vv_f16m8_rm_m(vbool2_t mask, vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfmsac(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmsac_vf_f16m8_rm_m
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmsac.mask.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
//
vfloat16m8_t test_vfmsac_vf_f16m8_rm_m(vbool2_t mask, vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfmsac(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmsac_vv_f32mf2_rm_m
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmsac.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
//
vfloat32mf2_t test_vfmsac_vv_f32mf2_rm_m(vbool64_t mask, vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfmsac(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmsac_vf_f32mf2_rm_m
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmsac.mask.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
//
vfloat32mf2_t test_vfmsac_vf_f32mf2_rm_m(vbool64_t mask, vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfmsac(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmsac_vv_f32m1_rm_m
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmsac.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfmsac_vv_f32m1_rm_m(vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfmsac(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmsac_vf_f32m1_rm_m
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmsac.mask.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfmsac_vf_f32m1_rm_m(vbool32_t mask, vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfmsac(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmsac_vv_f32m2_rm_m
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmsac.mask.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
//
vfloat32m2_t test_vfmsac_vv_f32m2_rm_m(vbool16_t mask, vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfmsac(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmsac_vf_f32m2_rm_m
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmsac.mask.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
//
vfloat32m2_t test_vfmsac_vf_f32m2_rm_m(vbool16_t mask, vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfmsac(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmsac_vv_f32m4_rm_m
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmsac.mask.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
//
vfloat32m4_t test_vfmsac_vv_f32m4_rm_m(vbool8_t mask, vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfmsac(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmsac_vf_f32m4_rm_m
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmsac.mask.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
//
vfloat32m4_t test_vfmsac_vf_f32m4_rm_m(vbool8_t mask, vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfmsac(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmsac_vv_f32m8_rm_m
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmsac.mask.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
//
vfloat32m8_t test_vfmsac_vv_f32m8_rm_m(vbool4_t mask, vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfmsac(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmsac_vf_f32m8_rm_m
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmsac.mask.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
//
vfloat32m8_t test_vfmsac_vf_f32m8_rm_m(vbool4_t mask, vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfmsac(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmsac_vv_f64m1_rm_m
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmsac.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfmsac_vv_f64m1_rm_m(vbool64_t mask, vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfmsac(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmsac_vf_f64m1_rm_m
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmsac.mask.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfmsac_vf_f64m1_rm_m(vbool64_t mask, vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfmsac(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmsac_vv_f64m2_rm_m
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmsac.mask.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
//
vfloat64m2_t test_vfmsac_vv_f64m2_rm_m(vbool32_t mask, vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfmsac(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmsac_vf_f64m2_rm_m
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmsac.mask.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
//
vfloat64m2_t test_vfmsac_vf_f64m2_rm_m(vbool32_t mask, vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfmsac(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmsac_vv_f64m4_rm_m
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmsac.mask.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
//
vfloat64m4_t test_vfmsac_vv_f64m4_rm_m(vbool16_t mask, vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfmsac(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmsac_vf_f64m4_rm_m
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmsac.mask.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
//
vfloat64m4_t test_vfmsac_vf_f64m4_rm_m(vbool16_t mask, vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfmsac(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmsac_vv_f64m8_rm_m
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmsac.mask.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
//
vfloat64m8_t test_vfmsac_vv_f64m8_rm_m(vbool8_t mask, vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfmsac(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmsac_vf_f64m8_rm_m
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmsac.mask.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
//
vfloat64m8_t test_vfmsac_vf_f64m8_rm_m(vbool8_t mask, vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfmsac(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}

clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfmsub.c

// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target // REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh \ // RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh \
// RUN: -target-feature +experimental-zvfh -disable-O0-optnone \ // RUN: -target-feature +experimental-zvfh -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ // RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s // RUN: FileCheck --check-prefix=CHECK-RV64 %s
#include <riscv_vector.h> #include <riscv_vector.h>
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmsub_vv_f16mf4 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmsub_vv_f16mf4
// CHECK-RV64-SAME: (<vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK-RV64-SAME: (<vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmsub.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmsub.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
// //
vfloat16mf4_t test_vfmsub_vv_f16mf4(vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) { vfloat16mf4_t test_vfmsub_vv_f16mf4(vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfmsub(vd, vs1, vs2, vl); return __riscv_vfmsub(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmsub_vf_f16mf4 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmsub_vf_f16mf4
// CHECK-RV64-SAME: (<vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmsub.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmsub.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
// //
vfloat16mf4_t test_vfmsub_vf_f16mf4(vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) { vfloat16mf4_t test_vfmsub_vf_f16mf4(vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfmsub(vd, rs1, vs2, vl); return __riscv_vfmsub(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmsub_vv_f16mf2 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmsub_vv_f16mf2
// CHECK-RV64-SAME: (<vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmsub.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmsub.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
// //
vfloat16mf2_t test_vfmsub_vv_f16mf2(vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) { vfloat16mf2_t test_vfmsub_vv_f16mf2(vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfmsub(vd, vs1, vs2, vl); return __riscv_vfmsub(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmsub_vf_f16mf2 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmsub_vf_f16mf2
// CHECK-RV64-SAME: (<vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmsub.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmsub.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
// //
vfloat16mf2_t test_vfmsub_vf_f16mf2(vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) { vfloat16mf2_t test_vfmsub_vf_f16mf2(vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfmsub(vd, rs1, vs2, vl); return __riscv_vfmsub(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmsub_vv_f16m1 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmsub_vv_f16m1
// CHECK-RV64-SAME: (<vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmsub.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmsub.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
// //
vfloat16m1_t test_vfmsub_vv_f16m1(vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) { vfloat16m1_t test_vfmsub_vv_f16m1(vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfmsub(vd, vs1, vs2, vl); return __riscv_vfmsub(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmsub_vf_f16m1 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmsub_vf_f16m1
// CHECK-RV64-SAME: (<vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmsub.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmsub.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
// //
vfloat16m1_t test_vfmsub_vf_f16m1(vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) { vfloat16m1_t test_vfmsub_vf_f16m1(vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfmsub(vd, rs1, vs2, vl); return __riscv_vfmsub(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmsub_vv_f16m2 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmsub_vv_f16m2
// CHECK-RV64-SAME: (<vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmsub.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmsub.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
// //
vfloat16m2_t test_vfmsub_vv_f16m2(vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) { vfloat16m2_t test_vfmsub_vv_f16m2(vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfmsub(vd, vs1, vs2, vl); return __riscv_vfmsub(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmsub_vf_f16m2 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmsub_vf_f16m2
// CHECK-RV64-SAME: (<vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmsub.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmsub.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
// //
vfloat16m2_t test_vfmsub_vf_f16m2(vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) { vfloat16m2_t test_vfmsub_vf_f16m2(vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfmsub(vd, rs1, vs2, vl); return __riscv_vfmsub(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmsub_vv_f16m4 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmsub_vv_f16m4
// CHECK-RV64-SAME: (<vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmsub.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmsub.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
// //
vfloat16m4_t test_vfmsub_vv_f16m4(vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) { vfloat16m4_t test_vfmsub_vv_f16m4(vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfmsub(vd, vs1, vs2, vl); return __riscv_vfmsub(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmsub_vf_f16m4 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmsub_vf_f16m4
// CHECK-RV64-SAME: (<vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmsub.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmsub.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
// //
vfloat16m4_t test_vfmsub_vf_f16m4(vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) { vfloat16m4_t test_vfmsub_vf_f16m4(vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfmsub(vd, rs1, vs2, vl); return __riscv_vfmsub(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmsub_vv_f16m8 // CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmsub_vv_f16m8
// CHECK-RV64-SAME: (<vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmsub.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmsub.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
// //
vfloat16m8_t test_vfmsub_vv_f16m8(vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) { vfloat16m8_t test_vfmsub_vv_f16m8(vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfmsub(vd, vs1, vs2, vl); return __riscv_vfmsub(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmsub_vf_f16m8 // CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmsub_vf_f16m8
// CHECK-RV64-SAME: (<vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmsub.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmsub.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
// //
vfloat16m8_t test_vfmsub_vf_f16m8(vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) { vfloat16m8_t test_vfmsub_vf_f16m8(vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfmsub(vd, rs1, vs2, vl); return __riscv_vfmsub(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmsub_vv_f32mf2 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmsub_vv_f32mf2
// CHECK-RV64-SAME: (<vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmsub.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmsub.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfmsub_vv_f32mf2(vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) { vfloat32mf2_t test_vfmsub_vv_f32mf2(vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfmsub(vd, vs1, vs2, vl); return __riscv_vfmsub(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmsub_vf_f32mf2 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmsub_vf_f32mf2
// CHECK-RV64-SAME: (<vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmsub.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmsub.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfmsub_vf_f32mf2(vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) { vfloat32mf2_t test_vfmsub_vf_f32mf2(vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfmsub(vd, rs1, vs2, vl); return __riscv_vfmsub(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmsub_vv_f32m1 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmsub_vv_f32m1
// CHECK-RV64-SAME: (<vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmsub.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmsub.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfmsub_vv_f32m1(vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) { vfloat32m1_t test_vfmsub_vv_f32m1(vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfmsub(vd, vs1, vs2, vl); return __riscv_vfmsub(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmsub_vf_f32m1 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmsub_vf_f32m1
// CHECK-RV64-SAME: (<vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmsub.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmsub.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfmsub_vf_f32m1(vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) { vfloat32m1_t test_vfmsub_vf_f32m1(vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfmsub(vd, rs1, vs2, vl); return __riscv_vfmsub(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmsub_vv_f32m2 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmsub_vv_f32m2
// CHECK-RV64-SAME: (<vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmsub.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmsub.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfmsub_vv_f32m2(vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) { vfloat32m2_t test_vfmsub_vv_f32m2(vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfmsub(vd, vs1, vs2, vl); return __riscv_vfmsub(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmsub_vf_f32m2 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmsub_vf_f32m2
// CHECK-RV64-SAME: (<vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmsub.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmsub.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfmsub_vf_f32m2(vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) { vfloat32m2_t test_vfmsub_vf_f32m2(vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfmsub(vd, rs1, vs2, vl); return __riscv_vfmsub(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmsub_vv_f32m4 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmsub_vv_f32m4
// CHECK-RV64-SAME: (<vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmsub.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmsub.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfmsub_vv_f32m4(vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) { vfloat32m4_t test_vfmsub_vv_f32m4(vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfmsub(vd, vs1, vs2, vl); return __riscv_vfmsub(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmsub_vf_f32m4 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmsub_vf_f32m4
// CHECK-RV64-SAME: (<vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmsub.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmsub.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfmsub_vf_f32m4(vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) { vfloat32m4_t test_vfmsub_vf_f32m4(vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfmsub(vd, rs1, vs2, vl); return __riscv_vfmsub(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmsub_vv_f32m8 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmsub_vv_f32m8
// CHECK-RV64-SAME: (<vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmsub.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmsub.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfmsub_vv_f32m8(vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) { vfloat32m8_t test_vfmsub_vv_f32m8(vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfmsub(vd, vs1, vs2, vl); return __riscv_vfmsub(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmsub_vf_f32m8 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmsub_vf_f32m8
// CHECK-RV64-SAME: (<vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmsub.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmsub.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfmsub_vf_f32m8(vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) { vfloat32m8_t test_vfmsub_vf_f32m8(vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfmsub(vd, rs1, vs2, vl); return __riscv_vfmsub(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmsub_vv_f64m1 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmsub_vv_f64m1
// CHECK-RV64-SAME: (<vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmsub.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmsub.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfmsub_vv_f64m1(vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) { vfloat64m1_t test_vfmsub_vv_f64m1(vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfmsub(vd, vs1, vs2, vl); return __riscv_vfmsub(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmsub_vf_f64m1 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmsub_vf_f64m1
// CHECK-RV64-SAME: (<vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmsub.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmsub.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfmsub_vf_f64m1(vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) { vfloat64m1_t test_vfmsub_vf_f64m1(vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfmsub(vd, rs1, vs2, vl); return __riscv_vfmsub(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmsub_vv_f64m2 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmsub_vv_f64m2
// CHECK-RV64-SAME: (<vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmsub.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmsub.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfmsub_vv_f64m2(vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) { vfloat64m2_t test_vfmsub_vv_f64m2(vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfmsub(vd, vs1, vs2, vl); return __riscv_vfmsub(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmsub_vf_f64m2 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmsub_vf_f64m2
// CHECK-RV64-SAME: (<vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmsub.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmsub.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfmsub_vf_f64m2(vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) { vfloat64m2_t test_vfmsub_vf_f64m2(vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfmsub(vd, rs1, vs2, vl); return __riscv_vfmsub(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmsub_vv_f64m4 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmsub_vv_f64m4
// CHECK-RV64-SAME: (<vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmsub.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmsub.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfmsub_vv_f64m4(vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) { vfloat64m4_t test_vfmsub_vv_f64m4(vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfmsub(vd, vs1, vs2, vl); return __riscv_vfmsub(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmsub_vf_f64m4 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmsub_vf_f64m4
// CHECK-RV64-SAME: (<vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmsub.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmsub.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfmsub_vf_f64m4(vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) { vfloat64m4_t test_vfmsub_vf_f64m4(vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfmsub(vd, rs1, vs2, vl); return __riscv_vfmsub(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmsub_vv_f64m8 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmsub_vv_f64m8
// CHECK-RV64-SAME: (<vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmsub.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmsub.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfmsub_vv_f64m8(vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) { vfloat64m8_t test_vfmsub_vv_f64m8(vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfmsub(vd, vs1, vs2, vl); return __riscv_vfmsub(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmsub_vf_f64m8 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmsub_vf_f64m8
// CHECK-RV64-SAME: (<vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmsub.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmsub.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfmsub_vf_f64m8(vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) { vfloat64m8_t test_vfmsub_vf_f64m8(vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfmsub(vd, rs1, vs2, vl); return __riscv_vfmsub(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmsub_vv_f16mf4_m // CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmsub_vv_f16mf4_m
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmsub.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmsub.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
// //
vfloat16mf4_t test_vfmsub_vv_f16mf4_m(vbool64_t mask, vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) { vfloat16mf4_t test_vfmsub_vv_f16mf4_m(vbool64_t mask, vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfmsub(mask, vd, vs1, vs2, vl); return __riscv_vfmsub(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmsub_vf_f16mf4_m // CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmsub_vf_f16mf4_m
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmsub.mask.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmsub.mask.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
// //
vfloat16mf4_t test_vfmsub_vf_f16mf4_m(vbool64_t mask, vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) { vfloat16mf4_t test_vfmsub_vf_f16mf4_m(vbool64_t mask, vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfmsub(mask, vd, rs1, vs2, vl); return __riscv_vfmsub(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmsub_vv_f16mf2_m // CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmsub_vv_f16mf2_m
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmsub.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmsub.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
// //
vfloat16mf2_t test_vfmsub_vv_f16mf2_m(vbool32_t mask, vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) { vfloat16mf2_t test_vfmsub_vv_f16mf2_m(vbool32_t mask, vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfmsub(mask, vd, vs1, vs2, vl); return __riscv_vfmsub(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmsub_vf_f16mf2_m // CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmsub_vf_f16mf2_m
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmsub.mask.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmsub.mask.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
// //
vfloat16mf2_t test_vfmsub_vf_f16mf2_m(vbool32_t mask, vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) { vfloat16mf2_t test_vfmsub_vf_f16mf2_m(vbool32_t mask, vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfmsub(mask, vd, rs1, vs2, vl); return __riscv_vfmsub(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmsub_vv_f16m1_m // CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmsub_vv_f16m1_m
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmsub.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmsub.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
// //
vfloat16m1_t test_vfmsub_vv_f16m1_m(vbool16_t mask, vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) { vfloat16m1_t test_vfmsub_vv_f16m1_m(vbool16_t mask, vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfmsub(mask, vd, vs1, vs2, vl); return __riscv_vfmsub(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmsub_vf_f16m1_m // CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmsub_vf_f16m1_m
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmsub.mask.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmsub.mask.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
// //
vfloat16m1_t test_vfmsub_vf_f16m1_m(vbool16_t mask, vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) { vfloat16m1_t test_vfmsub_vf_f16m1_m(vbool16_t mask, vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfmsub(mask, vd, rs1, vs2, vl); return __riscv_vfmsub(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmsub_vv_f16m2_m // CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmsub_vv_f16m2_m
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmsub.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmsub.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
// //
vfloat16m2_t test_vfmsub_vv_f16m2_m(vbool8_t mask, vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) { vfloat16m2_t test_vfmsub_vv_f16m2_m(vbool8_t mask, vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfmsub(mask, vd, vs1, vs2, vl); return __riscv_vfmsub(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmsub_vf_f16m2_m // CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmsub_vf_f16m2_m
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmsub.mask.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmsub.mask.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
// //
vfloat16m2_t test_vfmsub_vf_f16m2_m(vbool8_t mask, vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) { vfloat16m2_t test_vfmsub_vf_f16m2_m(vbool8_t mask, vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfmsub(mask, vd, rs1, vs2, vl); return __riscv_vfmsub(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmsub_vv_f16m4_m // CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmsub_vv_f16m4_m
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmsub.mask.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmsub.mask.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
// //
vfloat16m4_t test_vfmsub_vv_f16m4_m(vbool4_t mask, vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) { vfloat16m4_t test_vfmsub_vv_f16m4_m(vbool4_t mask, vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfmsub(mask, vd, vs1, vs2, vl); return __riscv_vfmsub(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmsub_vf_f16m4_m // CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmsub_vf_f16m4_m
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmsub.mask.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmsub.mask.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
// //
vfloat16m4_t test_vfmsub_vf_f16m4_m(vbool4_t mask, vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) { vfloat16m4_t test_vfmsub_vf_f16m4_m(vbool4_t mask, vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfmsub(mask, vd, rs1, vs2, vl); return __riscv_vfmsub(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmsub_vv_f16m8_m // CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmsub_vv_f16m8_m
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmsub.mask.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmsub.mask.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
// //
vfloat16m8_t test_vfmsub_vv_f16m8_m(vbool2_t mask, vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) { vfloat16m8_t test_vfmsub_vv_f16m8_m(vbool2_t mask, vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfmsub(mask, vd, vs1, vs2, vl); return __riscv_vfmsub(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmsub_vf_f16m8_m // CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmsub_vf_f16m8_m
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmsub.mask.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmsub.mask.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
// //
vfloat16m8_t test_vfmsub_vf_f16m8_m(vbool2_t mask, vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) { vfloat16m8_t test_vfmsub_vf_f16m8_m(vbool2_t mask, vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfmsub(mask, vd, rs1, vs2, vl); return __riscv_vfmsub(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmsub_vv_f32mf2_m // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmsub_vv_f32mf2_m
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmsub.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmsub.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfmsub_vv_f32mf2_m(vbool64_t mask, vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) { vfloat32mf2_t test_vfmsub_vv_f32mf2_m(vbool64_t mask, vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfmsub(mask, vd, vs1, vs2, vl); return __riscv_vfmsub(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmsub_vf_f32mf2_m // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmsub_vf_f32mf2_m
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmsub.mask.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmsub.mask.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfmsub_vf_f32mf2_m(vbool64_t mask, vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) { vfloat32mf2_t test_vfmsub_vf_f32mf2_m(vbool64_t mask, vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfmsub(mask, vd, rs1, vs2, vl); return __riscv_vfmsub(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmsub_vv_f32m1_m // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmsub_vv_f32m1_m
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmsub.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmsub.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfmsub_vv_f32m1_m(vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) { vfloat32m1_t test_vfmsub_vv_f32m1_m(vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfmsub(mask, vd, vs1, vs2, vl); return __riscv_vfmsub(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmsub_vf_f32m1_m // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmsub_vf_f32m1_m
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmsub.mask.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmsub.mask.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfmsub_vf_f32m1_m(vbool32_t mask, vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) { vfloat32m1_t test_vfmsub_vf_f32m1_m(vbool32_t mask, vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfmsub(mask, vd, rs1, vs2, vl); return __riscv_vfmsub(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmsub_vv_f32m2_m // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmsub_vv_f32m2_m
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmsub.mask.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmsub.mask.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfmsub_vv_f32m2_m(vbool16_t mask, vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) { vfloat32m2_t test_vfmsub_vv_f32m2_m(vbool16_t mask, vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfmsub(mask, vd, vs1, vs2, vl); return __riscv_vfmsub(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmsub_vf_f32m2_m // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmsub_vf_f32m2_m
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmsub.mask.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmsub.mask.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfmsub_vf_f32m2_m(vbool16_t mask, vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) { vfloat32m2_t test_vfmsub_vf_f32m2_m(vbool16_t mask, vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfmsub(mask, vd, rs1, vs2, vl); return __riscv_vfmsub(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmsub_vv_f32m4_m // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmsub_vv_f32m4_m
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmsub.mask.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmsub.mask.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfmsub_vv_f32m4_m(vbool8_t mask, vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) { vfloat32m4_t test_vfmsub_vv_f32m4_m(vbool8_t mask, vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfmsub(mask, vd, vs1, vs2, vl); return __riscv_vfmsub(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmsub_vf_f32m4_m // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmsub_vf_f32m4_m
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmsub.mask.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmsub.mask.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfmsub_vf_f32m4_m(vbool8_t mask, vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) { vfloat32m4_t test_vfmsub_vf_f32m4_m(vbool8_t mask, vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfmsub(mask, vd, rs1, vs2, vl); return __riscv_vfmsub(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmsub_vv_f32m8_m // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmsub_vv_f32m8_m
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmsub.mask.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmsub.mask.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfmsub_vv_f32m8_m(vbool4_t mask, vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) { vfloat32m8_t test_vfmsub_vv_f32m8_m(vbool4_t mask, vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfmsub(mask, vd, vs1, vs2, vl); return __riscv_vfmsub(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmsub_vf_f32m8_m // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmsub_vf_f32m8_m
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmsub.mask.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmsub.mask.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfmsub_vf_f32m8_m(vbool4_t mask, vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) { vfloat32m8_t test_vfmsub_vf_f32m8_m(vbool4_t mask, vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfmsub(mask, vd, rs1, vs2, vl); return __riscv_vfmsub(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmsub_vv_f64m1_m // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmsub_vv_f64m1_m
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmsub.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmsub.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfmsub_vv_f64m1_m(vbool64_t mask, vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) { vfloat64m1_t test_vfmsub_vv_f64m1_m(vbool64_t mask, vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfmsub(mask, vd, vs1, vs2, vl); return __riscv_vfmsub(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmsub_vf_f64m1_m // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmsub_vf_f64m1_m
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmsub.mask.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmsub.mask.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfmsub_vf_f64m1_m(vbool64_t mask, vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) { vfloat64m1_t test_vfmsub_vf_f64m1_m(vbool64_t mask, vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfmsub(mask, vd, rs1, vs2, vl); return __riscv_vfmsub(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmsub_vv_f64m2_m // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmsub_vv_f64m2_m
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmsub.mask.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmsub.mask.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfmsub_vv_f64m2_m(vbool32_t mask, vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) { vfloat64m2_t test_vfmsub_vv_f64m2_m(vbool32_t mask, vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfmsub(mask, vd, vs1, vs2, vl); return __riscv_vfmsub(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmsub_vf_f64m2_m // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmsub_vf_f64m2_m
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmsub.mask.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmsub.mask.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfmsub_vf_f64m2_m(vbool32_t mask, vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) { vfloat64m2_t test_vfmsub_vf_f64m2_m(vbool32_t mask, vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfmsub(mask, vd, rs1, vs2, vl); return __riscv_vfmsub(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmsub_vv_f64m4_m // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmsub_vv_f64m4_m
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmsub.mask.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmsub.mask.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfmsub_vv_f64m4_m(vbool16_t mask, vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) { vfloat64m4_t test_vfmsub_vv_f64m4_m(vbool16_t mask, vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfmsub(mask, vd, vs1, vs2, vl); return __riscv_vfmsub(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmsub_vf_f64m4_m // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmsub_vf_f64m4_m
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmsub.mask.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmsub.mask.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfmsub_vf_f64m4_m(vbool16_t mask, vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) { vfloat64m4_t test_vfmsub_vf_f64m4_m(vbool16_t mask, vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfmsub(mask, vd, rs1, vs2, vl); return __riscv_vfmsub(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmsub_vv_f64m8_m // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmsub_vv_f64m8_m
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmsub.mask.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmsub.mask.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfmsub_vv_f64m8_m(vbool8_t mask, vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) { vfloat64m8_t test_vfmsub_vv_f64m8_m(vbool8_t mask, vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfmsub(mask, vd, vs1, vs2, vl); return __riscv_vfmsub(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmsub_vf_f64m8_m // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmsub_vf_f64m8_m
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmsub.mask.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmsub.mask.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfmsub_vf_f64m8_m(vbool8_t mask, vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) { vfloat64m8_t test_vfmsub_vf_f64m8_m(vbool8_t mask, vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfmsub(mask, vd, rs1, vs2, vl); return __riscv_vfmsub(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmsub_vv_f16mf4_rm
// CHECK-RV64-SAME: (<vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmsub.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
//
vfloat16mf4_t test_vfmsub_vv_f16mf4_rm(vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfmsub(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmsub_vf_f16mf4_rm
// CHECK-RV64-SAME: (<vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmsub.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
//
vfloat16mf4_t test_vfmsub_vf_f16mf4_rm(vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfmsub(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmsub_vv_f16mf2_rm
// CHECK-RV64-SAME: (<vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmsub.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
//
vfloat16mf2_t test_vfmsub_vv_f16mf2_rm(vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfmsub(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmsub_vf_f16mf2_rm
// CHECK-RV64-SAME: (<vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmsub.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
//
vfloat16mf2_t test_vfmsub_vf_f16mf2_rm(vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfmsub(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmsub_vv_f16m1_rm
// CHECK-RV64-SAME: (<vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmsub.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfmsub_vv_f16m1_rm(vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfmsub(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmsub_vf_f16m1_rm
// CHECK-RV64-SAME: (<vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmsub.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfmsub_vf_f16m1_rm(vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfmsub(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmsub_vv_f16m2_rm
// CHECK-RV64-SAME: (<vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmsub.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
//
vfloat16m2_t test_vfmsub_vv_f16m2_rm(vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfmsub(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmsub_vf_f16m2_rm
// CHECK-RV64-SAME: (<vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmsub.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
//
vfloat16m2_t test_vfmsub_vf_f16m2_rm(vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfmsub(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmsub_vv_f16m4_rm
// CHECK-RV64-SAME: (<vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmsub.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
//
vfloat16m4_t test_vfmsub_vv_f16m4_rm(vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfmsub(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmsub_vf_f16m4_rm
// CHECK-RV64-SAME: (<vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmsub.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
//
vfloat16m4_t test_vfmsub_vf_f16m4_rm(vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfmsub(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmsub_vv_f16m8_rm
// CHECK-RV64-SAME: (<vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmsub.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
//
vfloat16m8_t test_vfmsub_vv_f16m8_rm(vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfmsub(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmsub_vf_f16m8_rm
// CHECK-RV64-SAME: (<vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmsub.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
//
vfloat16m8_t test_vfmsub_vf_f16m8_rm(vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfmsub(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmsub_vv_f32mf2_rm
// CHECK-RV64-SAME: (<vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmsub.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
//
vfloat32mf2_t test_vfmsub_vv_f32mf2_rm(vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfmsub(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmsub_vf_f32mf2_rm
// CHECK-RV64-SAME: (<vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmsub.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
//
vfloat32mf2_t test_vfmsub_vf_f32mf2_rm(vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfmsub(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmsub_vv_f32m1_rm
// CHECK-RV64-SAME: (<vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmsub.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfmsub_vv_f32m1_rm(vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfmsub(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmsub_vf_f32m1_rm
// CHECK-RV64-SAME: (<vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmsub.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfmsub_vf_f32m1_rm(vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfmsub(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmsub_vv_f32m2_rm
// CHECK-RV64-SAME: (<vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmsub.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
//
vfloat32m2_t test_vfmsub_vv_f32m2_rm(vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfmsub(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmsub_vf_f32m2_rm
// CHECK-RV64-SAME: (<vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmsub.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
//
vfloat32m2_t test_vfmsub_vf_f32m2_rm(vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfmsub(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmsub_vv_f32m4_rm
// CHECK-RV64-SAME: (<vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmsub.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
//
vfloat32m4_t test_vfmsub_vv_f32m4_rm(vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfmsub(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmsub_vf_f32m4_rm
// CHECK-RV64-SAME: (<vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmsub.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
//
vfloat32m4_t test_vfmsub_vf_f32m4_rm(vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfmsub(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmsub_vv_f32m8_rm
// CHECK-RV64-SAME: (<vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmsub.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
//
vfloat32m8_t test_vfmsub_vv_f32m8_rm(vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfmsub(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmsub_vf_f32m8_rm
// CHECK-RV64-SAME: (<vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmsub.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
//
vfloat32m8_t test_vfmsub_vf_f32m8_rm(vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfmsub(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmsub_vv_f64m1_rm
// CHECK-RV64-SAME: (<vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmsub.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfmsub_vv_f64m1_rm(vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfmsub(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmsub_vf_f64m1_rm
// CHECK-RV64-SAME: (<vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmsub.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfmsub_vf_f64m1_rm(vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfmsub(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmsub_vv_f64m2_rm
// CHECK-RV64-SAME: (<vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmsub.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
//
vfloat64m2_t test_vfmsub_vv_f64m2_rm(vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfmsub(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmsub_vf_f64m2_rm
// CHECK-RV64-SAME: (<vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmsub.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
//
vfloat64m2_t test_vfmsub_vf_f64m2_rm(vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfmsub(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmsub_vv_f64m4_rm
// CHECK-RV64-SAME: (<vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmsub.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
//
vfloat64m4_t test_vfmsub_vv_f64m4_rm(vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfmsub(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmsub_vf_f64m4_rm
// CHECK-RV64-SAME: (<vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmsub.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
//
vfloat64m4_t test_vfmsub_vf_f64m4_rm(vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfmsub(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmsub_vv_f64m8_rm
// CHECK-RV64-SAME: (<vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmsub.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
//
vfloat64m8_t test_vfmsub_vv_f64m8_rm(vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfmsub(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmsub_vf_f64m8_rm
// CHECK-RV64-SAME: (<vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmsub.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
//
vfloat64m8_t test_vfmsub_vf_f64m8_rm(vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfmsub(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmsub_vv_f16mf4_rm_m
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmsub.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
//
vfloat16mf4_t test_vfmsub_vv_f16mf4_rm_m(vbool64_t mask, vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfmsub(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmsub_vf_f16mf4_rm_m
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmsub.mask.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
//
vfloat16mf4_t test_vfmsub_vf_f16mf4_rm_m(vbool64_t mask, vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfmsub(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmsub_vv_f16mf2_rm_m
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmsub.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
//
vfloat16mf2_t test_vfmsub_vv_f16mf2_rm_m(vbool32_t mask, vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfmsub(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmsub_vf_f16mf2_rm_m
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmsub.mask.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
//
vfloat16mf2_t test_vfmsub_vf_f16mf2_rm_m(vbool32_t mask, vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfmsub(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmsub_vv_f16m1_rm_m
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmsub.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfmsub_vv_f16m1_rm_m(vbool16_t mask, vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfmsub(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmsub_vf_f16m1_rm_m
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmsub.mask.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfmsub_vf_f16m1_rm_m(vbool16_t mask, vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfmsub(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmsub_vv_f16m2_rm_m
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmsub.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
//
vfloat16m2_t test_vfmsub_vv_f16m2_rm_m(vbool8_t mask, vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfmsub(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmsub_vf_f16m2_rm_m
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmsub.mask.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
//
vfloat16m2_t test_vfmsub_vf_f16m2_rm_m(vbool8_t mask, vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfmsub(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmsub_vv_f16m4_rm_m
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmsub.mask.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
//
vfloat16m4_t test_vfmsub_vv_f16m4_rm_m(vbool4_t mask, vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfmsub(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmsub_vf_f16m4_rm_m
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmsub.mask.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
//
vfloat16m4_t test_vfmsub_vf_f16m4_rm_m(vbool4_t mask, vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfmsub(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmsub_vv_f16m8_rm_m
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmsub.mask.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
//
vfloat16m8_t test_vfmsub_vv_f16m8_rm_m(vbool2_t mask, vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfmsub(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmsub_vf_f16m8_rm_m
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmsub.mask.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
//
vfloat16m8_t test_vfmsub_vf_f16m8_rm_m(vbool2_t mask, vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfmsub(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmsub_vv_f32mf2_rm_m
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmsub.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
//
vfloat32mf2_t test_vfmsub_vv_f32mf2_rm_m(vbool64_t mask, vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfmsub(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmsub_vf_f32mf2_rm_m
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmsub.mask.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
//
vfloat32mf2_t test_vfmsub_vf_f32mf2_rm_m(vbool64_t mask, vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfmsub(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmsub_vv_f32m1_rm_m
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmsub.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfmsub_vv_f32m1_rm_m(vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfmsub(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmsub_vf_f32m1_rm_m
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmsub.mask.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfmsub_vf_f32m1_rm_m(vbool32_t mask, vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfmsub(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmsub_vv_f32m2_rm_m
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmsub.mask.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
//
vfloat32m2_t test_vfmsub_vv_f32m2_rm_m(vbool16_t mask, vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfmsub(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmsub_vf_f32m2_rm_m
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmsub.mask.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
//
vfloat32m2_t test_vfmsub_vf_f32m2_rm_m(vbool16_t mask, vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfmsub(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmsub_vv_f32m4_rm_m
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmsub.mask.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
//
vfloat32m4_t test_vfmsub_vv_f32m4_rm_m(vbool8_t mask, vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfmsub(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmsub_vf_f32m4_rm_m
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmsub.mask.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
//
vfloat32m4_t test_vfmsub_vf_f32m4_rm_m(vbool8_t mask, vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfmsub(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmsub_vv_f32m8_rm_m
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmsub.mask.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
//
vfloat32m8_t test_vfmsub_vv_f32m8_rm_m(vbool4_t mask, vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfmsub(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmsub_vf_f32m8_rm_m
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmsub.mask.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
//
vfloat32m8_t test_vfmsub_vf_f32m8_rm_m(vbool4_t mask, vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfmsub(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmsub_vv_f64m1_rm_m
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmsub.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfmsub_vv_f64m1_rm_m(vbool64_t mask, vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfmsub(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmsub_vf_f64m1_rm_m
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmsub.mask.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfmsub_vf_f64m1_rm_m(vbool64_t mask, vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfmsub(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmsub_vv_f64m2_rm_m
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmsub.mask.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
//
vfloat64m2_t test_vfmsub_vv_f64m2_rm_m(vbool32_t mask, vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfmsub(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmsub_vf_f64m2_rm_m
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmsub.mask.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
//
vfloat64m2_t test_vfmsub_vf_f64m2_rm_m(vbool32_t mask, vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfmsub(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmsub_vv_f64m4_rm_m
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmsub.mask.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
//
vfloat64m4_t test_vfmsub_vv_f64m4_rm_m(vbool16_t mask, vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfmsub(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmsub_vf_f64m4_rm_m
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmsub.mask.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
//
vfloat64m4_t test_vfmsub_vf_f64m4_rm_m(vbool16_t mask, vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfmsub(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmsub_vv_f64m8_rm_m
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmsub.mask.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
//
vfloat64m8_t test_vfmsub_vv_f64m8_rm_m(vbool8_t mask, vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfmsub(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmsub_vf_f64m8_rm_m
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmsub.mask.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
//
vfloat64m8_t test_vfmsub_vf_f64m8_rm_m(vbool8_t mask, vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfmsub(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}

clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmacc.c

// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target // REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh \ // RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh \
// RUN: -target-feature +experimental-zvfh -disable-O0-optnone \ // RUN: -target-feature +experimental-zvfh -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ // RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s // RUN: FileCheck --check-prefix=CHECK-RV64 %s
#include <riscv_vector.h> #include <riscv_vector.h>
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmacc_vv_f16mf4 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmacc_vv_f16mf4
// CHECK-RV64-SAME: (<vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK-RV64-SAME: (<vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmacc.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmacc.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
// //
vfloat16mf4_t test_vfnmacc_vv_f16mf4(vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) { vfloat16mf4_t test_vfnmacc_vv_f16mf4(vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfnmacc(vd, vs1, vs2, vl); return __riscv_vfnmacc(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmacc_vf_f16mf4 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmacc_vf_f16mf4
// CHECK-RV64-SAME: (<vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmacc.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmacc.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
// //
vfloat16mf4_t test_vfnmacc_vf_f16mf4(vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) { vfloat16mf4_t test_vfnmacc_vf_f16mf4(vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfnmacc(vd, rs1, vs2, vl); return __riscv_vfnmacc(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmacc_vv_f16mf2 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmacc_vv_f16mf2
// CHECK-RV64-SAME: (<vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmacc.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmacc.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
// //
vfloat16mf2_t test_vfnmacc_vv_f16mf2(vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) { vfloat16mf2_t test_vfnmacc_vv_f16mf2(vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfnmacc(vd, vs1, vs2, vl); return __riscv_vfnmacc(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmacc_vf_f16mf2 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmacc_vf_f16mf2
// CHECK-RV64-SAME: (<vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmacc.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmacc.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
// //
vfloat16mf2_t test_vfnmacc_vf_f16mf2(vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) { vfloat16mf2_t test_vfnmacc_vf_f16mf2(vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfnmacc(vd, rs1, vs2, vl); return __riscv_vfnmacc(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmacc_vv_f16m1 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmacc_vv_f16m1
// CHECK-RV64-SAME: (<vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmacc.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmacc.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
// //
vfloat16m1_t test_vfnmacc_vv_f16m1(vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) { vfloat16m1_t test_vfnmacc_vv_f16m1(vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfnmacc(vd, vs1, vs2, vl); return __riscv_vfnmacc(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmacc_vf_f16m1 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmacc_vf_f16m1
// CHECK-RV64-SAME: (<vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmacc.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmacc.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
// //
vfloat16m1_t test_vfnmacc_vf_f16m1(vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) { vfloat16m1_t test_vfnmacc_vf_f16m1(vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfnmacc(vd, rs1, vs2, vl); return __riscv_vfnmacc(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmacc_vv_f16m2 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmacc_vv_f16m2
// CHECK-RV64-SAME: (<vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmacc.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmacc.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
// //
vfloat16m2_t test_vfnmacc_vv_f16m2(vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) { vfloat16m2_t test_vfnmacc_vv_f16m2(vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfnmacc(vd, vs1, vs2, vl); return __riscv_vfnmacc(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmacc_vf_f16m2 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmacc_vf_f16m2
// CHECK-RV64-SAME: (<vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmacc.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmacc.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
// //
vfloat16m2_t test_vfnmacc_vf_f16m2(vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) { vfloat16m2_t test_vfnmacc_vf_f16m2(vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfnmacc(vd, rs1, vs2, vl); return __riscv_vfnmacc(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmacc_vv_f16m4 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmacc_vv_f16m4
// CHECK-RV64-SAME: (<vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmacc.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmacc.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
// //
vfloat16m4_t test_vfnmacc_vv_f16m4(vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) { vfloat16m4_t test_vfnmacc_vv_f16m4(vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfnmacc(vd, vs1, vs2, vl); return __riscv_vfnmacc(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmacc_vf_f16m4 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmacc_vf_f16m4
// CHECK-RV64-SAME: (<vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmacc.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmacc.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
// //
vfloat16m4_t test_vfnmacc_vf_f16m4(vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) { vfloat16m4_t test_vfnmacc_vf_f16m4(vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfnmacc(vd, rs1, vs2, vl); return __riscv_vfnmacc(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmacc_vv_f16m8 // CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmacc_vv_f16m8
// CHECK-RV64-SAME: (<vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmacc.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmacc.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
// //
vfloat16m8_t test_vfnmacc_vv_f16m8(vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) { vfloat16m8_t test_vfnmacc_vv_f16m8(vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfnmacc(vd, vs1, vs2, vl); return __riscv_vfnmacc(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmacc_vf_f16m8 // CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmacc_vf_f16m8
// CHECK-RV64-SAME: (<vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmacc.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmacc.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
// //
vfloat16m8_t test_vfnmacc_vf_f16m8(vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) { vfloat16m8_t test_vfnmacc_vf_f16m8(vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfnmacc(vd, rs1, vs2, vl); return __riscv_vfnmacc(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmacc_vv_f32mf2 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmacc_vv_f32mf2
// CHECK-RV64-SAME: (<vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmacc.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmacc.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfnmacc_vv_f32mf2(vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) { vfloat32mf2_t test_vfnmacc_vv_f32mf2(vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfnmacc(vd, vs1, vs2, vl); return __riscv_vfnmacc(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmacc_vf_f32mf2 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmacc_vf_f32mf2
// CHECK-RV64-SAME: (<vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmacc.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmacc.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfnmacc_vf_f32mf2(vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) { vfloat32mf2_t test_vfnmacc_vf_f32mf2(vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfnmacc(vd, rs1, vs2, vl); return __riscv_vfnmacc(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmacc_vv_f32m1 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmacc_vv_f32m1
// CHECK-RV64-SAME: (<vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmacc.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmacc.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfnmacc_vv_f32m1(vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) { vfloat32m1_t test_vfnmacc_vv_f32m1(vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfnmacc(vd, vs1, vs2, vl); return __riscv_vfnmacc(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmacc_vf_f32m1 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmacc_vf_f32m1
// CHECK-RV64-SAME: (<vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmacc.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmacc.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfnmacc_vf_f32m1(vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) { vfloat32m1_t test_vfnmacc_vf_f32m1(vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfnmacc(vd, rs1, vs2, vl); return __riscv_vfnmacc(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmacc_vv_f32m2 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmacc_vv_f32m2
// CHECK-RV64-SAME: (<vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmacc.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmacc.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfnmacc_vv_f32m2(vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) { vfloat32m2_t test_vfnmacc_vv_f32m2(vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfnmacc(vd, vs1, vs2, vl); return __riscv_vfnmacc(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmacc_vf_f32m2 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmacc_vf_f32m2
// CHECK-RV64-SAME: (<vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmacc.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmacc.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfnmacc_vf_f32m2(vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) { vfloat32m2_t test_vfnmacc_vf_f32m2(vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfnmacc(vd, rs1, vs2, vl); return __riscv_vfnmacc(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmacc_vv_f32m4 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmacc_vv_f32m4
// CHECK-RV64-SAME: (<vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmacc.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmacc.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfnmacc_vv_f32m4(vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) { vfloat32m4_t test_vfnmacc_vv_f32m4(vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfnmacc(vd, vs1, vs2, vl); return __riscv_vfnmacc(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmacc_vf_f32m4 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmacc_vf_f32m4
// CHECK-RV64-SAME: (<vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmacc.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmacc.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfnmacc_vf_f32m4(vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) { vfloat32m4_t test_vfnmacc_vf_f32m4(vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfnmacc(vd, rs1, vs2, vl); return __riscv_vfnmacc(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmacc_vv_f32m8 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmacc_vv_f32m8
// CHECK-RV64-SAME: (<vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmacc.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmacc.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfnmacc_vv_f32m8(vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) { vfloat32m8_t test_vfnmacc_vv_f32m8(vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfnmacc(vd, vs1, vs2, vl); return __riscv_vfnmacc(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmacc_vf_f32m8 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmacc_vf_f32m8
// CHECK-RV64-SAME: (<vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmacc.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmacc.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfnmacc_vf_f32m8(vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) { vfloat32m8_t test_vfnmacc_vf_f32m8(vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfnmacc(vd, rs1, vs2, vl); return __riscv_vfnmacc(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmacc_vv_f64m1 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmacc_vv_f64m1
// CHECK-RV64-SAME: (<vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmacc.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmacc.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfnmacc_vv_f64m1(vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) { vfloat64m1_t test_vfnmacc_vv_f64m1(vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfnmacc(vd, vs1, vs2, vl); return __riscv_vfnmacc(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmacc_vf_f64m1 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmacc_vf_f64m1
// CHECK-RV64-SAME: (<vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmacc.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmacc.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfnmacc_vf_f64m1(vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) { vfloat64m1_t test_vfnmacc_vf_f64m1(vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfnmacc(vd, rs1, vs2, vl); return __riscv_vfnmacc(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmacc_vv_f64m2 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmacc_vv_f64m2
// CHECK-RV64-SAME: (<vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmacc.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmacc.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfnmacc_vv_f64m2(vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) { vfloat64m2_t test_vfnmacc_vv_f64m2(vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfnmacc(vd, vs1, vs2, vl); return __riscv_vfnmacc(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmacc_vf_f64m2 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmacc_vf_f64m2
// CHECK-RV64-SAME: (<vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmacc.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmacc.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfnmacc_vf_f64m2(vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) { vfloat64m2_t test_vfnmacc_vf_f64m2(vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfnmacc(vd, rs1, vs2, vl); return __riscv_vfnmacc(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmacc_vv_f64m4 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmacc_vv_f64m4
// CHECK-RV64-SAME: (<vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmacc.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmacc.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfnmacc_vv_f64m4(vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) { vfloat64m4_t test_vfnmacc_vv_f64m4(vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfnmacc(vd, vs1, vs2, vl); return __riscv_vfnmacc(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmacc_vf_f64m4 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmacc_vf_f64m4
// CHECK-RV64-SAME: (<vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmacc.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmacc.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfnmacc_vf_f64m4(vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) { vfloat64m4_t test_vfnmacc_vf_f64m4(vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfnmacc(vd, rs1, vs2, vl); return __riscv_vfnmacc(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmacc_vv_f64m8 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmacc_vv_f64m8
// CHECK-RV64-SAME: (<vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmacc.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmacc.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfnmacc_vv_f64m8(vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) { vfloat64m8_t test_vfnmacc_vv_f64m8(vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfnmacc(vd, vs1, vs2, vl); return __riscv_vfnmacc(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmacc_vf_f64m8 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmacc_vf_f64m8
// CHECK-RV64-SAME: (<vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmacc.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmacc.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfnmacc_vf_f64m8(vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) { vfloat64m8_t test_vfnmacc_vf_f64m8(vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfnmacc(vd, rs1, vs2, vl); return __riscv_vfnmacc(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmacc_vv_f16mf4_m // CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmacc_vv_f16mf4_m
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmacc.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmacc.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
// //
vfloat16mf4_t test_vfnmacc_vv_f16mf4_m(vbool64_t mask, vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) { vfloat16mf4_t test_vfnmacc_vv_f16mf4_m(vbool64_t mask, vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfnmacc(mask, vd, vs1, vs2, vl); return __riscv_vfnmacc(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmacc_vf_f16mf4_m // CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmacc_vf_f16mf4_m
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmacc.mask.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmacc.mask.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
// //
vfloat16mf4_t test_vfnmacc_vf_f16mf4_m(vbool64_t mask, vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) { vfloat16mf4_t test_vfnmacc_vf_f16mf4_m(vbool64_t mask, vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfnmacc(mask, vd, rs1, vs2, vl); return __riscv_vfnmacc(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmacc_vv_f16mf2_m // CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmacc_vv_f16mf2_m
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmacc.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmacc.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
// //
vfloat16mf2_t test_vfnmacc_vv_f16mf2_m(vbool32_t mask, vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) { vfloat16mf2_t test_vfnmacc_vv_f16mf2_m(vbool32_t mask, vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfnmacc(mask, vd, vs1, vs2, vl); return __riscv_vfnmacc(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmacc_vf_f16mf2_m // CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmacc_vf_f16mf2_m
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmacc.mask.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmacc.mask.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
// //
vfloat16mf2_t test_vfnmacc_vf_f16mf2_m(vbool32_t mask, vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) { vfloat16mf2_t test_vfnmacc_vf_f16mf2_m(vbool32_t mask, vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfnmacc(mask, vd, rs1, vs2, vl); return __riscv_vfnmacc(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmacc_vv_f16m1_m // CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmacc_vv_f16m1_m
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmacc.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmacc.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
// //
vfloat16m1_t test_vfnmacc_vv_f16m1_m(vbool16_t mask, vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) { vfloat16m1_t test_vfnmacc_vv_f16m1_m(vbool16_t mask, vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfnmacc(mask, vd, vs1, vs2, vl); return __riscv_vfnmacc(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmacc_vf_f16m1_m // CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmacc_vf_f16m1_m
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmacc.mask.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmacc.mask.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
// //
vfloat16m1_t test_vfnmacc_vf_f16m1_m(vbool16_t mask, vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) { vfloat16m1_t test_vfnmacc_vf_f16m1_m(vbool16_t mask, vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfnmacc(mask, vd, rs1, vs2, vl); return __riscv_vfnmacc(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmacc_vv_f16m2_m // CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmacc_vv_f16m2_m
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmacc.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmacc.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
// //
vfloat16m2_t test_vfnmacc_vv_f16m2_m(vbool8_t mask, vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) { vfloat16m2_t test_vfnmacc_vv_f16m2_m(vbool8_t mask, vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfnmacc(mask, vd, vs1, vs2, vl); return __riscv_vfnmacc(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmacc_vf_f16m2_m // CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmacc_vf_f16m2_m
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmacc.mask.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmacc.mask.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
// //
vfloat16m2_t test_vfnmacc_vf_f16m2_m(vbool8_t mask, vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) { vfloat16m2_t test_vfnmacc_vf_f16m2_m(vbool8_t mask, vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfnmacc(mask, vd, rs1, vs2, vl); return __riscv_vfnmacc(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmacc_vv_f16m4_m // CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmacc_vv_f16m4_m
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmacc.mask.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmacc.mask.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
// //
vfloat16m4_t test_vfnmacc_vv_f16m4_m(vbool4_t mask, vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) { vfloat16m4_t test_vfnmacc_vv_f16m4_m(vbool4_t mask, vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfnmacc(mask, vd, vs1, vs2, vl); return __riscv_vfnmacc(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmacc_vf_f16m4_m // CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmacc_vf_f16m4_m
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmacc.mask.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmacc.mask.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
// //
vfloat16m4_t test_vfnmacc_vf_f16m4_m(vbool4_t mask, vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) { vfloat16m4_t test_vfnmacc_vf_f16m4_m(vbool4_t mask, vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfnmacc(mask, vd, rs1, vs2, vl); return __riscv_vfnmacc(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmacc_vv_f16m8_m // CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmacc_vv_f16m8_m
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmacc.mask.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmacc.mask.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
// //
vfloat16m8_t test_vfnmacc_vv_f16m8_m(vbool2_t mask, vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) { vfloat16m8_t test_vfnmacc_vv_f16m8_m(vbool2_t mask, vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfnmacc(mask, vd, vs1, vs2, vl); return __riscv_vfnmacc(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmacc_vf_f16m8_m // CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmacc_vf_f16m8_m
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmacc.mask.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmacc.mask.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
// //
vfloat16m8_t test_vfnmacc_vf_f16m8_m(vbool2_t mask, vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) { vfloat16m8_t test_vfnmacc_vf_f16m8_m(vbool2_t mask, vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfnmacc(mask, vd, rs1, vs2, vl); return __riscv_vfnmacc(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmacc_vv_f32mf2_m // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmacc_vv_f32mf2_m
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmacc.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmacc.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfnmacc_vv_f32mf2_m(vbool64_t mask, vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) { vfloat32mf2_t test_vfnmacc_vv_f32mf2_m(vbool64_t mask, vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfnmacc(mask, vd, vs1, vs2, vl); return __riscv_vfnmacc(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmacc_vf_f32mf2_m // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmacc_vf_f32mf2_m
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmacc.mask.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmacc.mask.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfnmacc_vf_f32mf2_m(vbool64_t mask, vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) { vfloat32mf2_t test_vfnmacc_vf_f32mf2_m(vbool64_t mask, vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfnmacc(mask, vd, rs1, vs2, vl); return __riscv_vfnmacc(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmacc_vv_f32m1_m // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmacc_vv_f32m1_m
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmacc.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmacc.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfnmacc_vv_f32m1_m(vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) { vfloat32m1_t test_vfnmacc_vv_f32m1_m(vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfnmacc(mask, vd, vs1, vs2, vl); return __riscv_vfnmacc(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmacc_vf_f32m1_m // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmacc_vf_f32m1_m
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmacc.mask.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmacc.mask.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfnmacc_vf_f32m1_m(vbool32_t mask, vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) { vfloat32m1_t test_vfnmacc_vf_f32m1_m(vbool32_t mask, vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfnmacc(mask, vd, rs1, vs2, vl); return __riscv_vfnmacc(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmacc_vv_f32m2_m // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmacc_vv_f32m2_m
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmacc.mask.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmacc.mask.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfnmacc_vv_f32m2_m(vbool16_t mask, vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) { vfloat32m2_t test_vfnmacc_vv_f32m2_m(vbool16_t mask, vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfnmacc(mask, vd, vs1, vs2, vl); return __riscv_vfnmacc(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmacc_vf_f32m2_m // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmacc_vf_f32m2_m
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmacc.mask.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmacc.mask.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfnmacc_vf_f32m2_m(vbool16_t mask, vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) { vfloat32m2_t test_vfnmacc_vf_f32m2_m(vbool16_t mask, vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfnmacc(mask, vd, rs1, vs2, vl); return __riscv_vfnmacc(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmacc_vv_f32m4_m // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmacc_vv_f32m4_m
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmacc.mask.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmacc.mask.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfnmacc_vv_f32m4_m(vbool8_t mask, vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) { vfloat32m4_t test_vfnmacc_vv_f32m4_m(vbool8_t mask, vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfnmacc(mask, vd, vs1, vs2, vl); return __riscv_vfnmacc(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmacc_vf_f32m4_m // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmacc_vf_f32m4_m
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmacc.mask.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmacc.mask.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfnmacc_vf_f32m4_m(vbool8_t mask, vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) { vfloat32m4_t test_vfnmacc_vf_f32m4_m(vbool8_t mask, vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfnmacc(mask, vd, rs1, vs2, vl); return __riscv_vfnmacc(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmacc_vv_f32m8_m // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmacc_vv_f32m8_m
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmacc.mask.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmacc.mask.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfnmacc_vv_f32m8_m(vbool4_t mask, vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) { vfloat32m8_t test_vfnmacc_vv_f32m8_m(vbool4_t mask, vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfnmacc(mask, vd, vs1, vs2, vl); return __riscv_vfnmacc(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmacc_vf_f32m8_m // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmacc_vf_f32m8_m
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmacc.mask.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmacc.mask.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfnmacc_vf_f32m8_m(vbool4_t mask, vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) { vfloat32m8_t test_vfnmacc_vf_f32m8_m(vbool4_t mask, vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfnmacc(mask, vd, rs1, vs2, vl); return __riscv_vfnmacc(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmacc_vv_f64m1_m // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmacc_vv_f64m1_m
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmacc.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmacc.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfnmacc_vv_f64m1_m(vbool64_t mask, vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) { vfloat64m1_t test_vfnmacc_vv_f64m1_m(vbool64_t mask, vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfnmacc(mask, vd, vs1, vs2, vl); return __riscv_vfnmacc(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmacc_vf_f64m1_m // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmacc_vf_f64m1_m
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmacc.mask.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmacc.mask.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfnmacc_vf_f64m1_m(vbool64_t mask, vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) { vfloat64m1_t test_vfnmacc_vf_f64m1_m(vbool64_t mask, vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfnmacc(mask, vd, rs1, vs2, vl); return __riscv_vfnmacc(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmacc_vv_f64m2_m // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmacc_vv_f64m2_m
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmacc.mask.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmacc.mask.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfnmacc_vv_f64m2_m(vbool32_t mask, vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) { vfloat64m2_t test_vfnmacc_vv_f64m2_m(vbool32_t mask, vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfnmacc(mask, vd, vs1, vs2, vl); return __riscv_vfnmacc(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmacc_vf_f64m2_m // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmacc_vf_f64m2_m
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmacc.mask.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmacc.mask.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfnmacc_vf_f64m2_m(vbool32_t mask, vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) { vfloat64m2_t test_vfnmacc_vf_f64m2_m(vbool32_t mask, vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfnmacc(mask, vd, rs1, vs2, vl); return __riscv_vfnmacc(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmacc_vv_f64m4_m // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmacc_vv_f64m4_m
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmacc.mask.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmacc.mask.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfnmacc_vv_f64m4_m(vbool16_t mask, vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) { vfloat64m4_t test_vfnmacc_vv_f64m4_m(vbool16_t mask, vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfnmacc(mask, vd, vs1, vs2, vl); return __riscv_vfnmacc(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmacc_vf_f64m4_m // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmacc_vf_f64m4_m
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmacc.mask.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmacc.mask.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfnmacc_vf_f64m4_m(vbool16_t mask, vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) { vfloat64m4_t test_vfnmacc_vf_f64m4_m(vbool16_t mask, vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfnmacc(mask, vd, rs1, vs2, vl); return __riscv_vfnmacc(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmacc_vv_f64m8_m // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmacc_vv_f64m8_m
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmacc.mask.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmacc.mask.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfnmacc_vv_f64m8_m(vbool8_t mask, vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) { vfloat64m8_t test_vfnmacc_vv_f64m8_m(vbool8_t mask, vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfnmacc(mask, vd, vs1, vs2, vl); return __riscv_vfnmacc(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmacc_vf_f64m8_m // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmacc_vf_f64m8_m
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmacc.mask.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmacc.mask.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfnmacc_vf_f64m8_m(vbool8_t mask, vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) { vfloat64m8_t test_vfnmacc_vf_f64m8_m(vbool8_t mask, vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfnmacc(mask, vd, rs1, vs2, vl); return __riscv_vfnmacc(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmacc_vv_f16mf4_rm
// CHECK-RV64-SAME: (<vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmacc.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
//
vfloat16mf4_t test_vfnmacc_vv_f16mf4_rm(vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfnmacc(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmacc_vf_f16mf4_rm
// CHECK-RV64-SAME: (<vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmacc.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
//
vfloat16mf4_t test_vfnmacc_vf_f16mf4_rm(vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfnmacc(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmacc_vv_f16mf2_rm
// CHECK-RV64-SAME: (<vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmacc.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
//
vfloat16mf2_t test_vfnmacc_vv_f16mf2_rm(vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfnmacc(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmacc_vf_f16mf2_rm
// CHECK-RV64-SAME: (<vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmacc.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
//
vfloat16mf2_t test_vfnmacc_vf_f16mf2_rm(vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfnmacc(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmacc_vv_f16m1_rm
// CHECK-RV64-SAME: (<vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmacc.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfnmacc_vv_f16m1_rm(vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfnmacc(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmacc_vf_f16m1_rm
// CHECK-RV64-SAME: (<vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmacc.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfnmacc_vf_f16m1_rm(vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfnmacc(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmacc_vv_f16m2_rm
// CHECK-RV64-SAME: (<vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmacc.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
//
vfloat16m2_t test_vfnmacc_vv_f16m2_rm(vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfnmacc(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmacc_vf_f16m2_rm
// CHECK-RV64-SAME: (<vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmacc.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
//
vfloat16m2_t test_vfnmacc_vf_f16m2_rm(vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfnmacc(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmacc_vv_f16m4_rm
// CHECK-RV64-SAME: (<vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmacc.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
//
vfloat16m4_t test_vfnmacc_vv_f16m4_rm(vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfnmacc(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmacc_vf_f16m4_rm
// CHECK-RV64-SAME: (<vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmacc.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
//
vfloat16m4_t test_vfnmacc_vf_f16m4_rm(vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfnmacc(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmacc_vv_f16m8_rm
// CHECK-RV64-SAME: (<vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmacc.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
//
vfloat16m8_t test_vfnmacc_vv_f16m8_rm(vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfnmacc(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmacc_vf_f16m8_rm
// CHECK-RV64-SAME: (<vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmacc.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
//
vfloat16m8_t test_vfnmacc_vf_f16m8_rm(vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfnmacc(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmacc_vv_f32mf2_rm
// CHECK-RV64-SAME: (<vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmacc.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
//
vfloat32mf2_t test_vfnmacc_vv_f32mf2_rm(vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfnmacc(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmacc_vf_f32mf2_rm
// CHECK-RV64-SAME: (<vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmacc.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
//
vfloat32mf2_t test_vfnmacc_vf_f32mf2_rm(vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfnmacc(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmacc_vv_f32m1_rm
// CHECK-RV64-SAME: (<vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmacc.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfnmacc_vv_f32m1_rm(vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfnmacc(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmacc_vf_f32m1_rm
// CHECK-RV64-SAME: (<vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmacc.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfnmacc_vf_f32m1_rm(vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfnmacc(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmacc_vv_f32m2_rm
// CHECK-RV64-SAME: (<vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmacc.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
//
vfloat32m2_t test_vfnmacc_vv_f32m2_rm(vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfnmacc(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmacc_vf_f32m2_rm
// CHECK-RV64-SAME: (<vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmacc.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
//
vfloat32m2_t test_vfnmacc_vf_f32m2_rm(vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfnmacc(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmacc_vv_f32m4_rm
// CHECK-RV64-SAME: (<vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmacc.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
//
vfloat32m4_t test_vfnmacc_vv_f32m4_rm(vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfnmacc(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmacc_vf_f32m4_rm
// CHECK-RV64-SAME: (<vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmacc.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
//
vfloat32m4_t test_vfnmacc_vf_f32m4_rm(vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfnmacc(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmacc_vv_f32m8_rm
// CHECK-RV64-SAME: (<vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmacc.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
//
vfloat32m8_t test_vfnmacc_vv_f32m8_rm(vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfnmacc(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmacc_vf_f32m8_rm
// CHECK-RV64-SAME: (<vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmacc.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
//
vfloat32m8_t test_vfnmacc_vf_f32m8_rm(vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfnmacc(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmacc_vv_f64m1_rm
// CHECK-RV64-SAME: (<vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmacc.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfnmacc_vv_f64m1_rm(vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfnmacc(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmacc_vf_f64m1_rm
// CHECK-RV64-SAME: (<vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmacc.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfnmacc_vf_f64m1_rm(vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfnmacc(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmacc_vv_f64m2_rm
// CHECK-RV64-SAME: (<vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmacc.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
//
vfloat64m2_t test_vfnmacc_vv_f64m2_rm(vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfnmacc(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmacc_vf_f64m2_rm
// CHECK-RV64-SAME: (<vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmacc.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
//
vfloat64m2_t test_vfnmacc_vf_f64m2_rm(vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfnmacc(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmacc_vv_f64m4_rm
// CHECK-RV64-SAME: (<vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmacc.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
//
vfloat64m4_t test_vfnmacc_vv_f64m4_rm(vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfnmacc(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmacc_vf_f64m4_rm
// CHECK-RV64-SAME: (<vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmacc.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
//
vfloat64m4_t test_vfnmacc_vf_f64m4_rm(vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfnmacc(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmacc_vv_f64m8_rm
// CHECK-RV64-SAME: (<vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmacc.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
//
vfloat64m8_t test_vfnmacc_vv_f64m8_rm(vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfnmacc(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmacc_vf_f64m8_rm
// CHECK-RV64-SAME: (<vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmacc.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
//
vfloat64m8_t test_vfnmacc_vf_f64m8_rm(vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfnmacc(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmacc_vv_f16mf4_rm_m
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmacc.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
//
vfloat16mf4_t test_vfnmacc_vv_f16mf4_rm_m(vbool64_t mask, vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfnmacc(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmacc_vf_f16mf4_rm_m
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmacc.mask.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
//
vfloat16mf4_t test_vfnmacc_vf_f16mf4_rm_m(vbool64_t mask, vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfnmacc(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmacc_vv_f16mf2_rm_m
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmacc.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
//
vfloat16mf2_t test_vfnmacc_vv_f16mf2_rm_m(vbool32_t mask, vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfnmacc(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmacc_vf_f16mf2_rm_m
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmacc.mask.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
//
vfloat16mf2_t test_vfnmacc_vf_f16mf2_rm_m(vbool32_t mask, vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfnmacc(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmacc_vv_f16m1_rm_m
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmacc.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfnmacc_vv_f16m1_rm_m(vbool16_t mask, vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfnmacc(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmacc_vf_f16m1_rm_m
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmacc.mask.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfnmacc_vf_f16m1_rm_m(vbool16_t mask, vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfnmacc(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmacc_vv_f16m2_rm_m
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmacc.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
//
vfloat16m2_t test_vfnmacc_vv_f16m2_rm_m(vbool8_t mask, vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfnmacc(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmacc_vf_f16m2_rm_m
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmacc.mask.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
//
vfloat16m2_t test_vfnmacc_vf_f16m2_rm_m(vbool8_t mask, vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfnmacc(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmacc_vv_f16m4_rm_m
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmacc.mask.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
//
vfloat16m4_t test_vfnmacc_vv_f16m4_rm_m(vbool4_t mask, vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfnmacc(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmacc_vf_f16m4_rm_m
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmacc.mask.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
//
vfloat16m4_t test_vfnmacc_vf_f16m4_rm_m(vbool4_t mask, vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfnmacc(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmacc_vv_f16m8_rm_m
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmacc.mask.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
//
vfloat16m8_t test_vfnmacc_vv_f16m8_rm_m(vbool2_t mask, vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfnmacc(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmacc_vf_f16m8_rm_m
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmacc.mask.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
//
vfloat16m8_t test_vfnmacc_vf_f16m8_rm_m(vbool2_t mask, vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfnmacc(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmacc_vv_f32mf2_rm_m
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmacc.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
//
vfloat32mf2_t test_vfnmacc_vv_f32mf2_rm_m(vbool64_t mask, vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfnmacc(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmacc_vf_f32mf2_rm_m
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmacc.mask.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
//
vfloat32mf2_t test_vfnmacc_vf_f32mf2_rm_m(vbool64_t mask, vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfnmacc(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmacc_vv_f32m1_rm_m
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmacc.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfnmacc_vv_f32m1_rm_m(vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfnmacc(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmacc_vf_f32m1_rm_m
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmacc.mask.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfnmacc_vf_f32m1_rm_m(vbool32_t mask, vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfnmacc(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmacc_vv_f32m2_rm_m
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmacc.mask.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
//
vfloat32m2_t test_vfnmacc_vv_f32m2_rm_m(vbool16_t mask, vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfnmacc(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmacc_vf_f32m2_rm_m
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmacc.mask.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
//
vfloat32m2_t test_vfnmacc_vf_f32m2_rm_m(vbool16_t mask, vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfnmacc(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmacc_vv_f32m4_rm_m
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmacc.mask.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
//
vfloat32m4_t test_vfnmacc_vv_f32m4_rm_m(vbool8_t mask, vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfnmacc(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmacc_vf_f32m4_rm_m
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmacc.mask.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
//
vfloat32m4_t test_vfnmacc_vf_f32m4_rm_m(vbool8_t mask, vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfnmacc(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmacc_vv_f32m8_rm_m
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmacc.mask.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
//
vfloat32m8_t test_vfnmacc_vv_f32m8_rm_m(vbool4_t mask, vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfnmacc(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmacc_vf_f32m8_rm_m
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmacc.mask.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
//
vfloat32m8_t test_vfnmacc_vf_f32m8_rm_m(vbool4_t mask, vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfnmacc(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmacc_vv_f64m1_rm_m
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmacc.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfnmacc_vv_f64m1_rm_m(vbool64_t mask, vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfnmacc(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmacc_vf_f64m1_rm_m
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmacc.mask.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfnmacc_vf_f64m1_rm_m(vbool64_t mask, vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfnmacc(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmacc_vv_f64m2_rm_m
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmacc.mask.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
//
vfloat64m2_t test_vfnmacc_vv_f64m2_rm_m(vbool32_t mask, vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfnmacc(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmacc_vf_f64m2_rm_m
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmacc.mask.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
//
vfloat64m2_t test_vfnmacc_vf_f64m2_rm_m(vbool32_t mask, vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfnmacc(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmacc_vv_f64m4_rm_m
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmacc.mask.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
//
vfloat64m4_t test_vfnmacc_vv_f64m4_rm_m(vbool16_t mask, vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfnmacc(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmacc_vf_f64m4_rm_m
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmacc.mask.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
//
vfloat64m4_t test_vfnmacc_vf_f64m4_rm_m(vbool16_t mask, vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfnmacc(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmacc_vv_f64m8_rm_m
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmacc.mask.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
//
vfloat64m8_t test_vfnmacc_vv_f64m8_rm_m(vbool8_t mask, vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfnmacc(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmacc_vf_f64m8_rm_m
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmacc.mask.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
//
vfloat64m8_t test_vfnmacc_vf_f64m8_rm_m(vbool8_t mask, vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfnmacc(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}

clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmadd.c

// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target // REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh \ // RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh \
// RUN: -target-feature +experimental-zvfh -disable-O0-optnone \ // RUN: -target-feature +experimental-zvfh -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ // RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s // RUN: FileCheck --check-prefix=CHECK-RV64 %s
#include <riscv_vector.h> #include <riscv_vector.h>
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmadd_vv_f16mf4 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmadd_vv_f16mf4
// CHECK-RV64-SAME: (<vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK-RV64-SAME: (<vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmadd.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmadd.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
// //
vfloat16mf4_t test_vfnmadd_vv_f16mf4(vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) { vfloat16mf4_t test_vfnmadd_vv_f16mf4(vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfnmadd(vd, vs1, vs2, vl); return __riscv_vfnmadd(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmadd_vf_f16mf4 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmadd_vf_f16mf4
// CHECK-RV64-SAME: (<vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmadd.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmadd.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
// //
vfloat16mf4_t test_vfnmadd_vf_f16mf4(vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) { vfloat16mf4_t test_vfnmadd_vf_f16mf4(vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfnmadd(vd, rs1, vs2, vl); return __riscv_vfnmadd(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmadd_vv_f16mf2 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmadd_vv_f16mf2
// CHECK-RV64-SAME: (<vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmadd.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmadd.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
// //
vfloat16mf2_t test_vfnmadd_vv_f16mf2(vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) { vfloat16mf2_t test_vfnmadd_vv_f16mf2(vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfnmadd(vd, vs1, vs2, vl); return __riscv_vfnmadd(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmadd_vf_f16mf2 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmadd_vf_f16mf2
// CHECK-RV64-SAME: (<vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmadd.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmadd.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
// //
vfloat16mf2_t test_vfnmadd_vf_f16mf2(vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) { vfloat16mf2_t test_vfnmadd_vf_f16mf2(vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfnmadd(vd, rs1, vs2, vl); return __riscv_vfnmadd(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmadd_vv_f16m1 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmadd_vv_f16m1
// CHECK-RV64-SAME: (<vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmadd.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmadd.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
// //
vfloat16m1_t test_vfnmadd_vv_f16m1(vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) { vfloat16m1_t test_vfnmadd_vv_f16m1(vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfnmadd(vd, vs1, vs2, vl); return __riscv_vfnmadd(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmadd_vf_f16m1 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmadd_vf_f16m1
// CHECK-RV64-SAME: (<vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmadd.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmadd.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
// //
vfloat16m1_t test_vfnmadd_vf_f16m1(vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) { vfloat16m1_t test_vfnmadd_vf_f16m1(vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfnmadd(vd, rs1, vs2, vl); return __riscv_vfnmadd(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmadd_vv_f16m2 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmadd_vv_f16m2
// CHECK-RV64-SAME: (<vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmadd.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmadd.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
// //
vfloat16m2_t test_vfnmadd_vv_f16m2(vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) { vfloat16m2_t test_vfnmadd_vv_f16m2(vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfnmadd(vd, vs1, vs2, vl); return __riscv_vfnmadd(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmadd_vf_f16m2 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmadd_vf_f16m2
// CHECK-RV64-SAME: (<vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmadd.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmadd.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
// //
vfloat16m2_t test_vfnmadd_vf_f16m2(vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) { vfloat16m2_t test_vfnmadd_vf_f16m2(vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfnmadd(vd, rs1, vs2, vl); return __riscv_vfnmadd(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmadd_vv_f16m4 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmadd_vv_f16m4
// CHECK-RV64-SAME: (<vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmadd.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmadd.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
// //
vfloat16m4_t test_vfnmadd_vv_f16m4(vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) { vfloat16m4_t test_vfnmadd_vv_f16m4(vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfnmadd(vd, vs1, vs2, vl); return __riscv_vfnmadd(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmadd_vf_f16m4 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmadd_vf_f16m4
// CHECK-RV64-SAME: (<vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmadd.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmadd.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
// //
vfloat16m4_t test_vfnmadd_vf_f16m4(vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) { vfloat16m4_t test_vfnmadd_vf_f16m4(vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfnmadd(vd, rs1, vs2, vl); return __riscv_vfnmadd(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmadd_vv_f16m8 // CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmadd_vv_f16m8
// CHECK-RV64-SAME: (<vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmadd.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmadd.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
// //
vfloat16m8_t test_vfnmadd_vv_f16m8(vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) { vfloat16m8_t test_vfnmadd_vv_f16m8(vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfnmadd(vd, vs1, vs2, vl); return __riscv_vfnmadd(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmadd_vf_f16m8 // CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmadd_vf_f16m8
// CHECK-RV64-SAME: (<vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmadd.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmadd.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
// //
vfloat16m8_t test_vfnmadd_vf_f16m8(vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) { vfloat16m8_t test_vfnmadd_vf_f16m8(vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfnmadd(vd, rs1, vs2, vl); return __riscv_vfnmadd(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmadd_vv_f32mf2 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmadd_vv_f32mf2
// CHECK-RV64-SAME: (<vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmadd.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmadd.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfnmadd_vv_f32mf2(vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) { vfloat32mf2_t test_vfnmadd_vv_f32mf2(vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfnmadd(vd, vs1, vs2, vl); return __riscv_vfnmadd(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmadd_vf_f32mf2 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmadd_vf_f32mf2
// CHECK-RV64-SAME: (<vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmadd.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmadd.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfnmadd_vf_f32mf2(vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) { vfloat32mf2_t test_vfnmadd_vf_f32mf2(vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfnmadd(vd, rs1, vs2, vl); return __riscv_vfnmadd(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmadd_vv_f32m1 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmadd_vv_f32m1
// CHECK-RV64-SAME: (<vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmadd.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmadd.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfnmadd_vv_f32m1(vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) { vfloat32m1_t test_vfnmadd_vv_f32m1(vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfnmadd(vd, vs1, vs2, vl); return __riscv_vfnmadd(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmadd_vf_f32m1 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmadd_vf_f32m1
// CHECK-RV64-SAME: (<vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmadd.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmadd.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfnmadd_vf_f32m1(vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) { vfloat32m1_t test_vfnmadd_vf_f32m1(vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfnmadd(vd, rs1, vs2, vl); return __riscv_vfnmadd(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmadd_vv_f32m2 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmadd_vv_f32m2
// CHECK-RV64-SAME: (<vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmadd.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmadd.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfnmadd_vv_f32m2(vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) { vfloat32m2_t test_vfnmadd_vv_f32m2(vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfnmadd(vd, vs1, vs2, vl); return __riscv_vfnmadd(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmadd_vf_f32m2 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmadd_vf_f32m2
// CHECK-RV64-SAME: (<vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmadd.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmadd.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfnmadd_vf_f32m2(vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) { vfloat32m2_t test_vfnmadd_vf_f32m2(vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfnmadd(vd, rs1, vs2, vl); return __riscv_vfnmadd(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmadd_vv_f32m4 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmadd_vv_f32m4
// CHECK-RV64-SAME: (<vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmadd.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmadd.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfnmadd_vv_f32m4(vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) { vfloat32m4_t test_vfnmadd_vv_f32m4(vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfnmadd(vd, vs1, vs2, vl); return __riscv_vfnmadd(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmadd_vf_f32m4 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmadd_vf_f32m4
// CHECK-RV64-SAME: (<vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmadd.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmadd.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfnmadd_vf_f32m4(vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) { vfloat32m4_t test_vfnmadd_vf_f32m4(vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfnmadd(vd, rs1, vs2, vl); return __riscv_vfnmadd(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmadd_vv_f32m8 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmadd_vv_f32m8
// CHECK-RV64-SAME: (<vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmadd.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmadd.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfnmadd_vv_f32m8(vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) { vfloat32m8_t test_vfnmadd_vv_f32m8(vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfnmadd(vd, vs1, vs2, vl); return __riscv_vfnmadd(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmadd_vf_f32m8 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmadd_vf_f32m8
// CHECK-RV64-SAME: (<vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmadd.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmadd.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfnmadd_vf_f32m8(vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) { vfloat32m8_t test_vfnmadd_vf_f32m8(vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfnmadd(vd, rs1, vs2, vl); return __riscv_vfnmadd(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmadd_vv_f64m1 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmadd_vv_f64m1
// CHECK-RV64-SAME: (<vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmadd.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmadd.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfnmadd_vv_f64m1(vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) { vfloat64m1_t test_vfnmadd_vv_f64m1(vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfnmadd(vd, vs1, vs2, vl); return __riscv_vfnmadd(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmadd_vf_f64m1 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmadd_vf_f64m1
// CHECK-RV64-SAME: (<vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmadd.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmadd.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfnmadd_vf_f64m1(vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) { vfloat64m1_t test_vfnmadd_vf_f64m1(vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfnmadd(vd, rs1, vs2, vl); return __riscv_vfnmadd(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmadd_vv_f64m2 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmadd_vv_f64m2
// CHECK-RV64-SAME: (<vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmadd.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmadd.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfnmadd_vv_f64m2(vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) { vfloat64m2_t test_vfnmadd_vv_f64m2(vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfnmadd(vd, vs1, vs2, vl); return __riscv_vfnmadd(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmadd_vf_f64m2 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmadd_vf_f64m2
// CHECK-RV64-SAME: (<vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmadd.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmadd.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfnmadd_vf_f64m2(vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) { vfloat64m2_t test_vfnmadd_vf_f64m2(vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfnmadd(vd, rs1, vs2, vl); return __riscv_vfnmadd(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmadd_vv_f64m4 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmadd_vv_f64m4
// CHECK-RV64-SAME: (<vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmadd.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmadd.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfnmadd_vv_f64m4(vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) { vfloat64m4_t test_vfnmadd_vv_f64m4(vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfnmadd(vd, vs1, vs2, vl); return __riscv_vfnmadd(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmadd_vf_f64m4 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmadd_vf_f64m4
// CHECK-RV64-SAME: (<vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmadd.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmadd.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfnmadd_vf_f64m4(vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) { vfloat64m4_t test_vfnmadd_vf_f64m4(vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfnmadd(vd, rs1, vs2, vl); return __riscv_vfnmadd(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmadd_vv_f64m8 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmadd_vv_f64m8
// CHECK-RV64-SAME: (<vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmadd.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmadd.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfnmadd_vv_f64m8(vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) { vfloat64m8_t test_vfnmadd_vv_f64m8(vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfnmadd(vd, vs1, vs2, vl); return __riscv_vfnmadd(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmadd_vf_f64m8 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmadd_vf_f64m8
// CHECK-RV64-SAME: (<vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmadd.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmadd.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfnmadd_vf_f64m8(vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) { vfloat64m8_t test_vfnmadd_vf_f64m8(vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfnmadd(vd, rs1, vs2, vl); return __riscv_vfnmadd(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmadd_vv_f16mf4_m // CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmadd_vv_f16mf4_m
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmadd.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmadd.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
// //
vfloat16mf4_t test_vfnmadd_vv_f16mf4_m(vbool64_t mask, vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) { vfloat16mf4_t test_vfnmadd_vv_f16mf4_m(vbool64_t mask, vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfnmadd(mask, vd, vs1, vs2, vl); return __riscv_vfnmadd(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmadd_vf_f16mf4_m // CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmadd_vf_f16mf4_m
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmadd.mask.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmadd.mask.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
// //
vfloat16mf4_t test_vfnmadd_vf_f16mf4_m(vbool64_t mask, vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) { vfloat16mf4_t test_vfnmadd_vf_f16mf4_m(vbool64_t mask, vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfnmadd(mask, vd, rs1, vs2, vl); return __riscv_vfnmadd(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmadd_vv_f16mf2_m // CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmadd_vv_f16mf2_m
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmadd.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmadd.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
// //
vfloat16mf2_t test_vfnmadd_vv_f16mf2_m(vbool32_t mask, vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) { vfloat16mf2_t test_vfnmadd_vv_f16mf2_m(vbool32_t mask, vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfnmadd(mask, vd, vs1, vs2, vl); return __riscv_vfnmadd(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmadd_vf_f16mf2_m // CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmadd_vf_f16mf2_m
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmadd.mask.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmadd.mask.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
// //
vfloat16mf2_t test_vfnmadd_vf_f16mf2_m(vbool32_t mask, vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) { vfloat16mf2_t test_vfnmadd_vf_f16mf2_m(vbool32_t mask, vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfnmadd(mask, vd, rs1, vs2, vl); return __riscv_vfnmadd(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmadd_vv_f16m1_m // CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmadd_vv_f16m1_m
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmadd.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmadd.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
// //
vfloat16m1_t test_vfnmadd_vv_f16m1_m(vbool16_t mask, vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) { vfloat16m1_t test_vfnmadd_vv_f16m1_m(vbool16_t mask, vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfnmadd(mask, vd, vs1, vs2, vl); return __riscv_vfnmadd(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmadd_vf_f16m1_m // CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmadd_vf_f16m1_m
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmadd.mask.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmadd.mask.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
// //
vfloat16m1_t test_vfnmadd_vf_f16m1_m(vbool16_t mask, vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) { vfloat16m1_t test_vfnmadd_vf_f16m1_m(vbool16_t mask, vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfnmadd(mask, vd, rs1, vs2, vl); return __riscv_vfnmadd(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmadd_vv_f16m2_m // CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmadd_vv_f16m2_m
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmadd.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmadd.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
// //
vfloat16m2_t test_vfnmadd_vv_f16m2_m(vbool8_t mask, vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) { vfloat16m2_t test_vfnmadd_vv_f16m2_m(vbool8_t mask, vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfnmadd(mask, vd, vs1, vs2, vl); return __riscv_vfnmadd(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmadd_vf_f16m2_m // CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmadd_vf_f16m2_m
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmadd.mask.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmadd.mask.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
// //
vfloat16m2_t test_vfnmadd_vf_f16m2_m(vbool8_t mask, vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) { vfloat16m2_t test_vfnmadd_vf_f16m2_m(vbool8_t mask, vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfnmadd(mask, vd, rs1, vs2, vl); return __riscv_vfnmadd(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmadd_vv_f16m4_m // CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmadd_vv_f16m4_m
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmadd.mask.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmadd.mask.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
// //
vfloat16m4_t test_vfnmadd_vv_f16m4_m(vbool4_t mask, vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) { vfloat16m4_t test_vfnmadd_vv_f16m4_m(vbool4_t mask, vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfnmadd(mask, vd, vs1, vs2, vl); return __riscv_vfnmadd(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmadd_vf_f16m4_m // CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmadd_vf_f16m4_m
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmadd.mask.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmadd.mask.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
// //
vfloat16m4_t test_vfnmadd_vf_f16m4_m(vbool4_t mask, vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) { vfloat16m4_t test_vfnmadd_vf_f16m4_m(vbool4_t mask, vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfnmadd(mask, vd, rs1, vs2, vl); return __riscv_vfnmadd(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmadd_vv_f16m8_m // CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmadd_vv_f16m8_m
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmadd.mask.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmadd.mask.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
// //
vfloat16m8_t test_vfnmadd_vv_f16m8_m(vbool2_t mask, vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) { vfloat16m8_t test_vfnmadd_vv_f16m8_m(vbool2_t mask, vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfnmadd(mask, vd, vs1, vs2, vl); return __riscv_vfnmadd(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmadd_vf_f16m8_m // CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmadd_vf_f16m8_m
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmadd.mask.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmadd.mask.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
// //
vfloat16m8_t test_vfnmadd_vf_f16m8_m(vbool2_t mask, vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) { vfloat16m8_t test_vfnmadd_vf_f16m8_m(vbool2_t mask, vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfnmadd(mask, vd, rs1, vs2, vl); return __riscv_vfnmadd(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmadd_vv_f32mf2_m // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmadd_vv_f32mf2_m
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmadd.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmadd.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfnmadd_vv_f32mf2_m(vbool64_t mask, vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) { vfloat32mf2_t test_vfnmadd_vv_f32mf2_m(vbool64_t mask, vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfnmadd(mask, vd, vs1, vs2, vl); return __riscv_vfnmadd(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmadd_vf_f32mf2_m // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmadd_vf_f32mf2_m
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmadd.mask.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmadd.mask.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfnmadd_vf_f32mf2_m(vbool64_t mask, vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) { vfloat32mf2_t test_vfnmadd_vf_f32mf2_m(vbool64_t mask, vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfnmadd(mask, vd, rs1, vs2, vl); return __riscv_vfnmadd(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmadd_vv_f32m1_m // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmadd_vv_f32m1_m
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmadd.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmadd.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfnmadd_vv_f32m1_m(vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) { vfloat32m1_t test_vfnmadd_vv_f32m1_m(vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfnmadd(mask, vd, vs1, vs2, vl); return __riscv_vfnmadd(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmadd_vf_f32m1_m // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmadd_vf_f32m1_m
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmadd.mask.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmadd.mask.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfnmadd_vf_f32m1_m(vbool32_t mask, vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) { vfloat32m1_t test_vfnmadd_vf_f32m1_m(vbool32_t mask, vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfnmadd(mask, vd, rs1, vs2, vl); return __riscv_vfnmadd(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmadd_vv_f32m2_m // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmadd_vv_f32m2_m
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmadd.mask.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmadd.mask.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfnmadd_vv_f32m2_m(vbool16_t mask, vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) { vfloat32m2_t test_vfnmadd_vv_f32m2_m(vbool16_t mask, vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfnmadd(mask, vd, vs1, vs2, vl); return __riscv_vfnmadd(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmadd_vf_f32m2_m // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmadd_vf_f32m2_m
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmadd.mask.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmadd.mask.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfnmadd_vf_f32m2_m(vbool16_t mask, vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) { vfloat32m2_t test_vfnmadd_vf_f32m2_m(vbool16_t mask, vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfnmadd(mask, vd, rs1, vs2, vl); return __riscv_vfnmadd(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmadd_vv_f32m4_m // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmadd_vv_f32m4_m
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmadd.mask.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmadd.mask.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfnmadd_vv_f32m4_m(vbool8_t mask, vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) { vfloat32m4_t test_vfnmadd_vv_f32m4_m(vbool8_t mask, vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfnmadd(mask, vd, vs1, vs2, vl); return __riscv_vfnmadd(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmadd_vf_f32m4_m // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmadd_vf_f32m4_m
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmadd.mask.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmadd.mask.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfnmadd_vf_f32m4_m(vbool8_t mask, vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) { vfloat32m4_t test_vfnmadd_vf_f32m4_m(vbool8_t mask, vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfnmadd(mask, vd, rs1, vs2, vl); return __riscv_vfnmadd(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmadd_vv_f32m8_m // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmadd_vv_f32m8_m
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmadd.mask.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmadd.mask.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfnmadd_vv_f32m8_m(vbool4_t mask, vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) { vfloat32m8_t test_vfnmadd_vv_f32m8_m(vbool4_t mask, vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfnmadd(mask, vd, vs1, vs2, vl); return __riscv_vfnmadd(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmadd_vf_f32m8_m // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmadd_vf_f32m8_m
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmadd.mask.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmadd.mask.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfnmadd_vf_f32m8_m(vbool4_t mask, vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) { vfloat32m8_t test_vfnmadd_vf_f32m8_m(vbool4_t mask, vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfnmadd(mask, vd, rs1, vs2, vl); return __riscv_vfnmadd(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmadd_vv_f64m1_m // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmadd_vv_f64m1_m
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmadd.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmadd.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfnmadd_vv_f64m1_m(vbool64_t mask, vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) { vfloat64m1_t test_vfnmadd_vv_f64m1_m(vbool64_t mask, vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfnmadd(mask, vd, vs1, vs2, vl); return __riscv_vfnmadd(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmadd_vf_f64m1_m // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmadd_vf_f64m1_m
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmadd.mask.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmadd.mask.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfnmadd_vf_f64m1_m(vbool64_t mask, vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) { vfloat64m1_t test_vfnmadd_vf_f64m1_m(vbool64_t mask, vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfnmadd(mask, vd, rs1, vs2, vl); return __riscv_vfnmadd(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmadd_vv_f64m2_m // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmadd_vv_f64m2_m
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmadd.mask.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmadd.mask.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfnmadd_vv_f64m2_m(vbool32_t mask, vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) { vfloat64m2_t test_vfnmadd_vv_f64m2_m(vbool32_t mask, vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfnmadd(mask, vd, vs1, vs2, vl); return __riscv_vfnmadd(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmadd_vf_f64m2_m // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmadd_vf_f64m2_m
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmadd.mask.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmadd.mask.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfnmadd_vf_f64m2_m(vbool32_t mask, vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) { vfloat64m2_t test_vfnmadd_vf_f64m2_m(vbool32_t mask, vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfnmadd(mask, vd, rs1, vs2, vl); return __riscv_vfnmadd(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmadd_vv_f64m4_m // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmadd_vv_f64m4_m
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmadd.mask.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmadd.mask.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfnmadd_vv_f64m4_m(vbool16_t mask, vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) { vfloat64m4_t test_vfnmadd_vv_f64m4_m(vbool16_t mask, vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfnmadd(mask, vd, vs1, vs2, vl); return __riscv_vfnmadd(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmadd_vf_f64m4_m // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmadd_vf_f64m4_m
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmadd.mask.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmadd.mask.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfnmadd_vf_f64m4_m(vbool16_t mask, vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) { vfloat64m4_t test_vfnmadd_vf_f64m4_m(vbool16_t mask, vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfnmadd(mask, vd, rs1, vs2, vl); return __riscv_vfnmadd(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmadd_vv_f64m8_m // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmadd_vv_f64m8_m
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmadd.mask.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmadd.mask.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfnmadd_vv_f64m8_m(vbool8_t mask, vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) { vfloat64m8_t test_vfnmadd_vv_f64m8_m(vbool8_t mask, vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfnmadd(mask, vd, vs1, vs2, vl); return __riscv_vfnmadd(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmadd_vf_f64m8_m // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmadd_vf_f64m8_m
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmadd.mask.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmadd.mask.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfnmadd_vf_f64m8_m(vbool8_t mask, vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) { vfloat64m8_t test_vfnmadd_vf_f64m8_m(vbool8_t mask, vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfnmadd(mask, vd, rs1, vs2, vl); return __riscv_vfnmadd(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmadd_vv_f16mf4_rm
// CHECK-RV64-SAME: (<vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmadd.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
//
vfloat16mf4_t test_vfnmadd_vv_f16mf4_rm(vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfnmadd(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmadd_vf_f16mf4_rm
// CHECK-RV64-SAME: (<vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmadd.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
//
vfloat16mf4_t test_vfnmadd_vf_f16mf4_rm(vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfnmadd(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmadd_vv_f16mf2_rm
// CHECK-RV64-SAME: (<vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmadd.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
//
vfloat16mf2_t test_vfnmadd_vv_f16mf2_rm(vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfnmadd(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmadd_vf_f16mf2_rm
// CHECK-RV64-SAME: (<vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmadd.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
//
vfloat16mf2_t test_vfnmadd_vf_f16mf2_rm(vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfnmadd(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmadd_vv_f16m1_rm
// CHECK-RV64-SAME: (<vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmadd.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfnmadd_vv_f16m1_rm(vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfnmadd(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmadd_vf_f16m1_rm
// CHECK-RV64-SAME: (<vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmadd.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfnmadd_vf_f16m1_rm(vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfnmadd(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmadd_vv_f16m2_rm
// CHECK-RV64-SAME: (<vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmadd.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
//
vfloat16m2_t test_vfnmadd_vv_f16m2_rm(vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfnmadd(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmadd_vf_f16m2_rm
// CHECK-RV64-SAME: (<vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmadd.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
//
vfloat16m2_t test_vfnmadd_vf_f16m2_rm(vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfnmadd(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmadd_vv_f16m4_rm
// CHECK-RV64-SAME: (<vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmadd.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
//
vfloat16m4_t test_vfnmadd_vv_f16m4_rm(vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfnmadd(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmadd_vf_f16m4_rm
// CHECK-RV64-SAME: (<vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmadd.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
//
vfloat16m4_t test_vfnmadd_vf_f16m4_rm(vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfnmadd(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmadd_vv_f16m8_rm
// CHECK-RV64-SAME: (<vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmadd.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
//
vfloat16m8_t test_vfnmadd_vv_f16m8_rm(vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfnmadd(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmadd_vf_f16m8_rm
// CHECK-RV64-SAME: (<vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmadd.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
//
vfloat16m8_t test_vfnmadd_vf_f16m8_rm(vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfnmadd(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmadd_vv_f32mf2_rm
// CHECK-RV64-SAME: (<vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmadd.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
//
vfloat32mf2_t test_vfnmadd_vv_f32mf2_rm(vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfnmadd(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmadd_vf_f32mf2_rm
// CHECK-RV64-SAME: (<vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmadd.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
//
vfloat32mf2_t test_vfnmadd_vf_f32mf2_rm(vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfnmadd(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmadd_vv_f32m1_rm
// CHECK-RV64-SAME: (<vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmadd.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfnmadd_vv_f32m1_rm(vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfnmadd(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmadd_vf_f32m1_rm
// CHECK-RV64-SAME: (<vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmadd.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfnmadd_vf_f32m1_rm(vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfnmadd(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmadd_vv_f32m2_rm
// CHECK-RV64-SAME: (<vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmadd.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
//
vfloat32m2_t test_vfnmadd_vv_f32m2_rm(vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfnmadd(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmadd_vf_f32m2_rm
// CHECK-RV64-SAME: (<vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmadd.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
//
vfloat32m2_t test_vfnmadd_vf_f32m2_rm(vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfnmadd(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmadd_vv_f32m4_rm
// CHECK-RV64-SAME: (<vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmadd.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
//
vfloat32m4_t test_vfnmadd_vv_f32m4_rm(vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfnmadd(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmadd_vf_f32m4_rm
// CHECK-RV64-SAME: (<vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmadd.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
//
vfloat32m4_t test_vfnmadd_vf_f32m4_rm(vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfnmadd(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmadd_vv_f32m8_rm
// CHECK-RV64-SAME: (<vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmadd.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
//
vfloat32m8_t test_vfnmadd_vv_f32m8_rm(vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfnmadd(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmadd_vf_f32m8_rm
// CHECK-RV64-SAME: (<vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmadd.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
//
vfloat32m8_t test_vfnmadd_vf_f32m8_rm(vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfnmadd(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmadd_vv_f64m1_rm
// CHECK-RV64-SAME: (<vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmadd.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfnmadd_vv_f64m1_rm(vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfnmadd(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmadd_vf_f64m1_rm
// CHECK-RV64-SAME: (<vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmadd.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfnmadd_vf_f64m1_rm(vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfnmadd(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmadd_vv_f64m2_rm
// CHECK-RV64-SAME: (<vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmadd.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
//
vfloat64m2_t test_vfnmadd_vv_f64m2_rm(vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfnmadd(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmadd_vf_f64m2_rm
// CHECK-RV64-SAME: (<vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmadd.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
//
vfloat64m2_t test_vfnmadd_vf_f64m2_rm(vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfnmadd(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmadd_vv_f64m4_rm
// CHECK-RV64-SAME: (<vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmadd.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
//
vfloat64m4_t test_vfnmadd_vv_f64m4_rm(vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfnmadd(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmadd_vf_f64m4_rm
// CHECK-RV64-SAME: (<vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmadd.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
//
vfloat64m4_t test_vfnmadd_vf_f64m4_rm(vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfnmadd(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmadd_vv_f64m8_rm
// CHECK-RV64-SAME: (<vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmadd.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
//
vfloat64m8_t test_vfnmadd_vv_f64m8_rm(vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfnmadd(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmadd_vf_f64m8_rm
// CHECK-RV64-SAME: (<vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmadd.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
//
vfloat64m8_t test_vfnmadd_vf_f64m8_rm(vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfnmadd(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmadd_vv_f16mf4_rm_m
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmadd.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
//
vfloat16mf4_t test_vfnmadd_vv_f16mf4_rm_m(vbool64_t mask, vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfnmadd(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmadd_vf_f16mf4_rm_m
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmadd.mask.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
//
vfloat16mf4_t test_vfnmadd_vf_f16mf4_rm_m(vbool64_t mask, vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfnmadd(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmadd_vv_f16mf2_rm_m
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmadd.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
//
vfloat16mf2_t test_vfnmadd_vv_f16mf2_rm_m(vbool32_t mask, vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfnmadd(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmadd_vf_f16mf2_rm_m
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmadd.mask.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
//
vfloat16mf2_t test_vfnmadd_vf_f16mf2_rm_m(vbool32_t mask, vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfnmadd(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmadd_vv_f16m1_rm_m
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmadd.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfnmadd_vv_f16m1_rm_m(vbool16_t mask, vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfnmadd(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmadd_vf_f16m1_rm_m
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmadd.mask.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfnmadd_vf_f16m1_rm_m(vbool16_t mask, vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfnmadd(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmadd_vv_f16m2_rm_m
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmadd.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
//
vfloat16m2_t test_vfnmadd_vv_f16m2_rm_m(vbool8_t mask, vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfnmadd(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmadd_vf_f16m2_rm_m
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmadd.mask.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
//
vfloat16m2_t test_vfnmadd_vf_f16m2_rm_m(vbool8_t mask, vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfnmadd(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmadd_vv_f16m4_rm_m
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmadd.mask.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
//
vfloat16m4_t test_vfnmadd_vv_f16m4_rm_m(vbool4_t mask, vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfnmadd(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmadd_vf_f16m4_rm_m
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmadd.mask.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
//
vfloat16m4_t test_vfnmadd_vf_f16m4_rm_m(vbool4_t mask, vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfnmadd(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmadd_vv_f16m8_rm_m
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmadd.mask.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
//
vfloat16m8_t test_vfnmadd_vv_f16m8_rm_m(vbool2_t mask, vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfnmadd(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmadd_vf_f16m8_rm_m
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmadd.mask.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
//
vfloat16m8_t test_vfnmadd_vf_f16m8_rm_m(vbool2_t mask, vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfnmadd(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmadd_vv_f32mf2_rm_m
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmadd.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
//
vfloat32mf2_t test_vfnmadd_vv_f32mf2_rm_m(vbool64_t mask, vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfnmadd(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmadd_vf_f32mf2_rm_m
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmadd.mask.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
//
vfloat32mf2_t test_vfnmadd_vf_f32mf2_rm_m(vbool64_t mask, vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfnmadd(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmadd_vv_f32m1_rm_m
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmadd.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfnmadd_vv_f32m1_rm_m(vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfnmadd(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmadd_vf_f32m1_rm_m
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmadd.mask.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfnmadd_vf_f32m1_rm_m(vbool32_t mask, vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfnmadd(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmadd_vv_f32m2_rm_m
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmadd.mask.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
//
vfloat32m2_t test_vfnmadd_vv_f32m2_rm_m(vbool16_t mask, vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfnmadd(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmadd_vf_f32m2_rm_m
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmadd.mask.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
//
vfloat32m2_t test_vfnmadd_vf_f32m2_rm_m(vbool16_t mask, vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfnmadd(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmadd_vv_f32m4_rm_m
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmadd.mask.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
//
vfloat32m4_t test_vfnmadd_vv_f32m4_rm_m(vbool8_t mask, vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfnmadd(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmadd_vf_f32m4_rm_m
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmadd.mask.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
//
vfloat32m4_t test_vfnmadd_vf_f32m4_rm_m(vbool8_t mask, vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfnmadd(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmadd_vv_f32m8_rm_m
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmadd.mask.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
//
vfloat32m8_t test_vfnmadd_vv_f32m8_rm_m(vbool4_t mask, vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfnmadd(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmadd_vf_f32m8_rm_m
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmadd.mask.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
//
vfloat32m8_t test_vfnmadd_vf_f32m8_rm_m(vbool4_t mask, vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfnmadd(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmadd_vv_f64m1_rm_m
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmadd.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfnmadd_vv_f64m1_rm_m(vbool64_t mask, vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfnmadd(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmadd_vf_f64m1_rm_m
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmadd.mask.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfnmadd_vf_f64m1_rm_m(vbool64_t mask, vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfnmadd(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmadd_vv_f64m2_rm_m
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmadd.mask.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
//
vfloat64m2_t test_vfnmadd_vv_f64m2_rm_m(vbool32_t mask, vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfnmadd(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmadd_vf_f64m2_rm_m
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmadd.mask.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
//
vfloat64m2_t test_vfnmadd_vf_f64m2_rm_m(vbool32_t mask, vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfnmadd(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmadd_vv_f64m4_rm_m
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmadd.mask.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
//
vfloat64m4_t test_vfnmadd_vv_f64m4_rm_m(vbool16_t mask, vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfnmadd(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmadd_vf_f64m4_rm_m
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmadd.mask.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
//
vfloat64m4_t test_vfnmadd_vf_f64m4_rm_m(vbool16_t mask, vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfnmadd(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmadd_vv_f64m8_rm_m
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmadd.mask.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
//
vfloat64m8_t test_vfnmadd_vv_f64m8_rm_m(vbool8_t mask, vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfnmadd(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmadd_vf_f64m8_rm_m
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmadd.mask.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
//
vfloat64m8_t test_vfnmadd_vf_f64m8_rm_m(vbool8_t mask, vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfnmadd(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}

clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmsac.c

// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target // REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh \ // RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh \
// RUN: -target-feature +experimental-zvfh -disable-O0-optnone \ // RUN: -target-feature +experimental-zvfh -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ // RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s // RUN: FileCheck --check-prefix=CHECK-RV64 %s
#include <riscv_vector.h> #include <riscv_vector.h>
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmsac_vv_f16mf4 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmsac_vv_f16mf4
// CHECK-RV64-SAME: (<vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK-RV64-SAME: (<vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmsac.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmsac.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
// //
vfloat16mf4_t test_vfnmsac_vv_f16mf4(vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) { vfloat16mf4_t test_vfnmsac_vv_f16mf4(vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfnmsac(vd, vs1, vs2, vl); return __riscv_vfnmsac(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmsac_vf_f16mf4 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmsac_vf_f16mf4
// CHECK-RV64-SAME: (<vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmsac.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmsac.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
// //
vfloat16mf4_t test_vfnmsac_vf_f16mf4(vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) { vfloat16mf4_t test_vfnmsac_vf_f16mf4(vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfnmsac(vd, rs1, vs2, vl); return __riscv_vfnmsac(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmsac_vv_f16mf2 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmsac_vv_f16mf2
// CHECK-RV64-SAME: (<vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmsac.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmsac.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
// //
vfloat16mf2_t test_vfnmsac_vv_f16mf2(vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) { vfloat16mf2_t test_vfnmsac_vv_f16mf2(vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfnmsac(vd, vs1, vs2, vl); return __riscv_vfnmsac(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmsac_vf_f16mf2 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmsac_vf_f16mf2
// CHECK-RV64-SAME: (<vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmsac.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmsac.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
// //
vfloat16mf2_t test_vfnmsac_vf_f16mf2(vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) { vfloat16mf2_t test_vfnmsac_vf_f16mf2(vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfnmsac(vd, rs1, vs2, vl); return __riscv_vfnmsac(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmsac_vv_f16m1 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmsac_vv_f16m1
// CHECK-RV64-SAME: (<vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmsac.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmsac.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
// //
vfloat16m1_t test_vfnmsac_vv_f16m1(vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) { vfloat16m1_t test_vfnmsac_vv_f16m1(vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfnmsac(vd, vs1, vs2, vl); return __riscv_vfnmsac(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmsac_vf_f16m1 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmsac_vf_f16m1
// CHECK-RV64-SAME: (<vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmsac.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmsac.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
// //
vfloat16m1_t test_vfnmsac_vf_f16m1(vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) { vfloat16m1_t test_vfnmsac_vf_f16m1(vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfnmsac(vd, rs1, vs2, vl); return __riscv_vfnmsac(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmsac_vv_f16m2 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmsac_vv_f16m2
// CHECK-RV64-SAME: (<vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmsac.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmsac.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
// //
vfloat16m2_t test_vfnmsac_vv_f16m2(vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) { vfloat16m2_t test_vfnmsac_vv_f16m2(vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfnmsac(vd, vs1, vs2, vl); return __riscv_vfnmsac(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmsac_vf_f16m2 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmsac_vf_f16m2
// CHECK-RV64-SAME: (<vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmsac.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmsac.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
// //
vfloat16m2_t test_vfnmsac_vf_f16m2(vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) { vfloat16m2_t test_vfnmsac_vf_f16m2(vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfnmsac(vd, rs1, vs2, vl); return __riscv_vfnmsac(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmsac_vv_f16m4 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmsac_vv_f16m4
// CHECK-RV64-SAME: (<vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmsac.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmsac.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
// //
vfloat16m4_t test_vfnmsac_vv_f16m4(vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) { vfloat16m4_t test_vfnmsac_vv_f16m4(vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfnmsac(vd, vs1, vs2, vl); return __riscv_vfnmsac(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmsac_vf_f16m4 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmsac_vf_f16m4
// CHECK-RV64-SAME: (<vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmsac.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmsac.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
// //
vfloat16m4_t test_vfnmsac_vf_f16m4(vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) { vfloat16m4_t test_vfnmsac_vf_f16m4(vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfnmsac(vd, rs1, vs2, vl); return __riscv_vfnmsac(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmsac_vv_f16m8 // CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmsac_vv_f16m8
// CHECK-RV64-SAME: (<vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmsac.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmsac.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
// //
vfloat16m8_t test_vfnmsac_vv_f16m8(vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) { vfloat16m8_t test_vfnmsac_vv_f16m8(vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfnmsac(vd, vs1, vs2, vl); return __riscv_vfnmsac(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmsac_vf_f16m8 // CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmsac_vf_f16m8
// CHECK-RV64-SAME: (<vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmsac.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmsac.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
// //
vfloat16m8_t test_vfnmsac_vf_f16m8(vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) { vfloat16m8_t test_vfnmsac_vf_f16m8(vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfnmsac(vd, rs1, vs2, vl); return __riscv_vfnmsac(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmsac_vv_f32mf2 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmsac_vv_f32mf2
// CHECK-RV64-SAME: (<vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmsac.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmsac.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfnmsac_vv_f32mf2(vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) { vfloat32mf2_t test_vfnmsac_vv_f32mf2(vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfnmsac(vd, vs1, vs2, vl); return __riscv_vfnmsac(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmsac_vf_f32mf2 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmsac_vf_f32mf2
// CHECK-RV64-SAME: (<vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmsac.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmsac.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfnmsac_vf_f32mf2(vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) { vfloat32mf2_t test_vfnmsac_vf_f32mf2(vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfnmsac(vd, rs1, vs2, vl); return __riscv_vfnmsac(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmsac_vv_f32m1 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmsac_vv_f32m1
// CHECK-RV64-SAME: (<vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmsac.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmsac.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfnmsac_vv_f32m1(vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) { vfloat32m1_t test_vfnmsac_vv_f32m1(vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfnmsac(vd, vs1, vs2, vl); return __riscv_vfnmsac(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmsac_vf_f32m1 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmsac_vf_f32m1
// CHECK-RV64-SAME: (<vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmsac.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmsac.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfnmsac_vf_f32m1(vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) { vfloat32m1_t test_vfnmsac_vf_f32m1(vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfnmsac(vd, rs1, vs2, vl); return __riscv_vfnmsac(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmsac_vv_f32m2 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmsac_vv_f32m2
// CHECK-RV64-SAME: (<vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmsac.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmsac.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfnmsac_vv_f32m2(vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) { vfloat32m2_t test_vfnmsac_vv_f32m2(vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfnmsac(vd, vs1, vs2, vl); return __riscv_vfnmsac(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmsac_vf_f32m2 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmsac_vf_f32m2
// CHECK-RV64-SAME: (<vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmsac.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmsac.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfnmsac_vf_f32m2(vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) { vfloat32m2_t test_vfnmsac_vf_f32m2(vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfnmsac(vd, rs1, vs2, vl); return __riscv_vfnmsac(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmsac_vv_f32m4 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmsac_vv_f32m4
// CHECK-RV64-SAME: (<vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmsac.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmsac.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfnmsac_vv_f32m4(vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) { vfloat32m4_t test_vfnmsac_vv_f32m4(vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfnmsac(vd, vs1, vs2, vl); return __riscv_vfnmsac(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmsac_vf_f32m4 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmsac_vf_f32m4
// CHECK-RV64-SAME: (<vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmsac.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmsac.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfnmsac_vf_f32m4(vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) { vfloat32m4_t test_vfnmsac_vf_f32m4(vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfnmsac(vd, rs1, vs2, vl); return __riscv_vfnmsac(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmsac_vv_f32m8 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmsac_vv_f32m8
// CHECK-RV64-SAME: (<vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmsac.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmsac.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfnmsac_vv_f32m8(vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) { vfloat32m8_t test_vfnmsac_vv_f32m8(vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfnmsac(vd, vs1, vs2, vl); return __riscv_vfnmsac(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmsac_vf_f32m8 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmsac_vf_f32m8
// CHECK-RV64-SAME: (<vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmsac.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmsac.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfnmsac_vf_f32m8(vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) { vfloat32m8_t test_vfnmsac_vf_f32m8(vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfnmsac(vd, rs1, vs2, vl); return __riscv_vfnmsac(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmsac_vv_f64m1 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmsac_vv_f64m1
// CHECK-RV64-SAME: (<vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmsac.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmsac.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfnmsac_vv_f64m1(vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) { vfloat64m1_t test_vfnmsac_vv_f64m1(vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfnmsac(vd, vs1, vs2, vl); return __riscv_vfnmsac(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmsac_vf_f64m1 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmsac_vf_f64m1
// CHECK-RV64-SAME: (<vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmsac.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmsac.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfnmsac_vf_f64m1(vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) { vfloat64m1_t test_vfnmsac_vf_f64m1(vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfnmsac(vd, rs1, vs2, vl); return __riscv_vfnmsac(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmsac_vv_f64m2 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmsac_vv_f64m2
// CHECK-RV64-SAME: (<vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmsac.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmsac.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfnmsac_vv_f64m2(vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) { vfloat64m2_t test_vfnmsac_vv_f64m2(vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfnmsac(vd, vs1, vs2, vl); return __riscv_vfnmsac(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmsac_vf_f64m2 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmsac_vf_f64m2
// CHECK-RV64-SAME: (<vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmsac.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmsac.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfnmsac_vf_f64m2(vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) { vfloat64m2_t test_vfnmsac_vf_f64m2(vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfnmsac(vd, rs1, vs2, vl); return __riscv_vfnmsac(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmsac_vv_f64m4 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmsac_vv_f64m4
// CHECK-RV64-SAME: (<vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmsac.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmsac.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfnmsac_vv_f64m4(vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) { vfloat64m4_t test_vfnmsac_vv_f64m4(vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfnmsac(vd, vs1, vs2, vl); return __riscv_vfnmsac(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmsac_vf_f64m4 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmsac_vf_f64m4
// CHECK-RV64-SAME: (<vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmsac.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmsac.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfnmsac_vf_f64m4(vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) { vfloat64m4_t test_vfnmsac_vf_f64m4(vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfnmsac(vd, rs1, vs2, vl); return __riscv_vfnmsac(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmsac_vv_f64m8 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmsac_vv_f64m8
// CHECK-RV64-SAME: (<vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmsac.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmsac.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfnmsac_vv_f64m8(vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) { vfloat64m8_t test_vfnmsac_vv_f64m8(vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfnmsac(vd, vs1, vs2, vl); return __riscv_vfnmsac(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmsac_vf_f64m8 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmsac_vf_f64m8
// CHECK-RV64-SAME: (<vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmsac.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmsac.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfnmsac_vf_f64m8(vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) { vfloat64m8_t test_vfnmsac_vf_f64m8(vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfnmsac(vd, rs1, vs2, vl); return __riscv_vfnmsac(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmsac_vv_f16mf4_m // CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmsac_vv_f16mf4_m
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmsac.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmsac.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
// //
vfloat16mf4_t test_vfnmsac_vv_f16mf4_m(vbool64_t mask, vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) { vfloat16mf4_t test_vfnmsac_vv_f16mf4_m(vbool64_t mask, vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfnmsac(mask, vd, vs1, vs2, vl); return __riscv_vfnmsac(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmsac_vf_f16mf4_m // CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmsac_vf_f16mf4_m
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmsac.mask.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmsac.mask.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
// //
vfloat16mf4_t test_vfnmsac_vf_f16mf4_m(vbool64_t mask, vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) { vfloat16mf4_t test_vfnmsac_vf_f16mf4_m(vbool64_t mask, vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfnmsac(mask, vd, rs1, vs2, vl); return __riscv_vfnmsac(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmsac_vv_f16mf2_m // CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmsac_vv_f16mf2_m
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmsac.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmsac.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
// //
vfloat16mf2_t test_vfnmsac_vv_f16mf2_m(vbool32_t mask, vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) { vfloat16mf2_t test_vfnmsac_vv_f16mf2_m(vbool32_t mask, vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfnmsac(mask, vd, vs1, vs2, vl); return __riscv_vfnmsac(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmsac_vf_f16mf2_m // CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmsac_vf_f16mf2_m
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmsac.mask.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmsac.mask.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
// //
vfloat16mf2_t test_vfnmsac_vf_f16mf2_m(vbool32_t mask, vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) { vfloat16mf2_t test_vfnmsac_vf_f16mf2_m(vbool32_t mask, vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfnmsac(mask, vd, rs1, vs2, vl); return __riscv_vfnmsac(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmsac_vv_f16m1_m // CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmsac_vv_f16m1_m
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmsac.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmsac.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
// //
vfloat16m1_t test_vfnmsac_vv_f16m1_m(vbool16_t mask, vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) { vfloat16m1_t test_vfnmsac_vv_f16m1_m(vbool16_t mask, vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfnmsac(mask, vd, vs1, vs2, vl); return __riscv_vfnmsac(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmsac_vf_f16m1_m // CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmsac_vf_f16m1_m
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmsac.mask.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmsac.mask.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
// //
vfloat16m1_t test_vfnmsac_vf_f16m1_m(vbool16_t mask, vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) { vfloat16m1_t test_vfnmsac_vf_f16m1_m(vbool16_t mask, vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfnmsac(mask, vd, rs1, vs2, vl); return __riscv_vfnmsac(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmsac_vv_f16m2_m // CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmsac_vv_f16m2_m
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmsac.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmsac.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
// //
vfloat16m2_t test_vfnmsac_vv_f16m2_m(vbool8_t mask, vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) { vfloat16m2_t test_vfnmsac_vv_f16m2_m(vbool8_t mask, vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfnmsac(mask, vd, vs1, vs2, vl); return __riscv_vfnmsac(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmsac_vf_f16m2_m // CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmsac_vf_f16m2_m
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmsac.mask.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmsac.mask.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
// //
vfloat16m2_t test_vfnmsac_vf_f16m2_m(vbool8_t mask, vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) { vfloat16m2_t test_vfnmsac_vf_f16m2_m(vbool8_t mask, vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfnmsac(mask, vd, rs1, vs2, vl); return __riscv_vfnmsac(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmsac_vv_f16m4_m // CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmsac_vv_f16m4_m
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmsac.mask.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmsac.mask.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
// //
vfloat16m4_t test_vfnmsac_vv_f16m4_m(vbool4_t mask, vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) { vfloat16m4_t test_vfnmsac_vv_f16m4_m(vbool4_t mask, vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfnmsac(mask, vd, vs1, vs2, vl); return __riscv_vfnmsac(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmsac_vf_f16m4_m // CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmsac_vf_f16m4_m
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmsac.mask.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmsac.mask.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
// //
vfloat16m4_t test_vfnmsac_vf_f16m4_m(vbool4_t mask, vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) { vfloat16m4_t test_vfnmsac_vf_f16m4_m(vbool4_t mask, vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfnmsac(mask, vd, rs1, vs2, vl); return __riscv_vfnmsac(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmsac_vv_f16m8_m // CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmsac_vv_f16m8_m
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmsac.mask.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmsac.mask.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
// //
vfloat16m8_t test_vfnmsac_vv_f16m8_m(vbool2_t mask, vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) { vfloat16m8_t test_vfnmsac_vv_f16m8_m(vbool2_t mask, vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfnmsac(mask, vd, vs1, vs2, vl); return __riscv_vfnmsac(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmsac_vf_f16m8_m // CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmsac_vf_f16m8_m
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmsac.mask.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmsac.mask.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
// //
vfloat16m8_t test_vfnmsac_vf_f16m8_m(vbool2_t mask, vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) { vfloat16m8_t test_vfnmsac_vf_f16m8_m(vbool2_t mask, vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfnmsac(mask, vd, rs1, vs2, vl); return __riscv_vfnmsac(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmsac_vv_f32mf2_m // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmsac_vv_f32mf2_m
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmsac.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmsac.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfnmsac_vv_f32mf2_m(vbool64_t mask, vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) { vfloat32mf2_t test_vfnmsac_vv_f32mf2_m(vbool64_t mask, vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfnmsac(mask, vd, vs1, vs2, vl); return __riscv_vfnmsac(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmsac_vf_f32mf2_m // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmsac_vf_f32mf2_m
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmsac.mask.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmsac.mask.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfnmsac_vf_f32mf2_m(vbool64_t mask, vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) { vfloat32mf2_t test_vfnmsac_vf_f32mf2_m(vbool64_t mask, vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfnmsac(mask, vd, rs1, vs2, vl); return __riscv_vfnmsac(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmsac_vv_f32m1_m // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmsac_vv_f32m1_m
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmsac.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmsac.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfnmsac_vv_f32m1_m(vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) { vfloat32m1_t test_vfnmsac_vv_f32m1_m(vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfnmsac(mask, vd, vs1, vs2, vl); return __riscv_vfnmsac(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmsac_vf_f32m1_m // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmsac_vf_f32m1_m
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmsac.mask.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmsac.mask.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfnmsac_vf_f32m1_m(vbool32_t mask, vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) { vfloat32m1_t test_vfnmsac_vf_f32m1_m(vbool32_t mask, vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfnmsac(mask, vd, rs1, vs2, vl); return __riscv_vfnmsac(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmsac_vv_f32m2_m // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmsac_vv_f32m2_m
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmsac.mask.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmsac.mask.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfnmsac_vv_f32m2_m(vbool16_t mask, vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) { vfloat32m2_t test_vfnmsac_vv_f32m2_m(vbool16_t mask, vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfnmsac(mask, vd, vs1, vs2, vl); return __riscv_vfnmsac(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmsac_vf_f32m2_m // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmsac_vf_f32m2_m
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmsac.mask.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmsac.mask.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfnmsac_vf_f32m2_m(vbool16_t mask, vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) { vfloat32m2_t test_vfnmsac_vf_f32m2_m(vbool16_t mask, vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfnmsac(mask, vd, rs1, vs2, vl); return __riscv_vfnmsac(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmsac_vv_f32m4_m // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmsac_vv_f32m4_m
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmsac.mask.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmsac.mask.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfnmsac_vv_f32m4_m(vbool8_t mask, vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) { vfloat32m4_t test_vfnmsac_vv_f32m4_m(vbool8_t mask, vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfnmsac(mask, vd, vs1, vs2, vl); return __riscv_vfnmsac(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmsac_vf_f32m4_m // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmsac_vf_f32m4_m
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmsac.mask.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmsac.mask.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfnmsac_vf_f32m4_m(vbool8_t mask, vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) { vfloat32m4_t test_vfnmsac_vf_f32m4_m(vbool8_t mask, vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfnmsac(mask, vd, rs1, vs2, vl); return __riscv_vfnmsac(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmsac_vv_f32m8_m // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmsac_vv_f32m8_m
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmsac.mask.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmsac.mask.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfnmsac_vv_f32m8_m(vbool4_t mask, vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) { vfloat32m8_t test_vfnmsac_vv_f32m8_m(vbool4_t mask, vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfnmsac(mask, vd, vs1, vs2, vl); return __riscv_vfnmsac(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmsac_vf_f32m8_m // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmsac_vf_f32m8_m
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmsac.mask.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmsac.mask.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfnmsac_vf_f32m8_m(vbool4_t mask, vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) { vfloat32m8_t test_vfnmsac_vf_f32m8_m(vbool4_t mask, vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfnmsac(mask, vd, rs1, vs2, vl); return __riscv_vfnmsac(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmsac_vv_f64m1_m // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmsac_vv_f64m1_m
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmsac.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmsac.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfnmsac_vv_f64m1_m(vbool64_t mask, vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) { vfloat64m1_t test_vfnmsac_vv_f64m1_m(vbool64_t mask, vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfnmsac(mask, vd, vs1, vs2, vl); return __riscv_vfnmsac(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmsac_vf_f64m1_m // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmsac_vf_f64m1_m
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmsac.mask.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmsac.mask.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfnmsac_vf_f64m1_m(vbool64_t mask, vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) { vfloat64m1_t test_vfnmsac_vf_f64m1_m(vbool64_t mask, vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfnmsac(mask, vd, rs1, vs2, vl); return __riscv_vfnmsac(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmsac_vv_f64m2_m // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmsac_vv_f64m2_m
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmsac.mask.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmsac.mask.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfnmsac_vv_f64m2_m(vbool32_t mask, vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) { vfloat64m2_t test_vfnmsac_vv_f64m2_m(vbool32_t mask, vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfnmsac(mask, vd, vs1, vs2, vl); return __riscv_vfnmsac(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmsac_vf_f64m2_m // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmsac_vf_f64m2_m
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmsac.mask.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmsac.mask.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfnmsac_vf_f64m2_m(vbool32_t mask, vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) { vfloat64m2_t test_vfnmsac_vf_f64m2_m(vbool32_t mask, vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfnmsac(mask, vd, rs1, vs2, vl); return __riscv_vfnmsac(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmsac_vv_f64m4_m // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmsac_vv_f64m4_m
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmsac.mask.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmsac.mask.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfnmsac_vv_f64m4_m(vbool16_t mask, vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) { vfloat64m4_t test_vfnmsac_vv_f64m4_m(vbool16_t mask, vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfnmsac(mask, vd, vs1, vs2, vl); return __riscv_vfnmsac(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmsac_vf_f64m4_m // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmsac_vf_f64m4_m
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmsac.mask.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmsac.mask.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfnmsac_vf_f64m4_m(vbool16_t mask, vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) { vfloat64m4_t test_vfnmsac_vf_f64m4_m(vbool16_t mask, vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfnmsac(mask, vd, rs1, vs2, vl); return __riscv_vfnmsac(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmsac_vv_f64m8_m // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmsac_vv_f64m8_m
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmsac.mask.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmsac.mask.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfnmsac_vv_f64m8_m(vbool8_t mask, vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) { vfloat64m8_t test_vfnmsac_vv_f64m8_m(vbool8_t mask, vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfnmsac(mask, vd, vs1, vs2, vl); return __riscv_vfnmsac(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmsac_vf_f64m8_m // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmsac_vf_f64m8_m
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmsac.mask.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmsac.mask.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfnmsac_vf_f64m8_m(vbool8_t mask, vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) { vfloat64m8_t test_vfnmsac_vf_f64m8_m(vbool8_t mask, vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfnmsac(mask, vd, rs1, vs2, vl); return __riscv_vfnmsac(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmsac_vv_f16mf4_rm
// CHECK-RV64-SAME: (<vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmsac.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
//
vfloat16mf4_t test_vfnmsac_vv_f16mf4_rm(vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfnmsac(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmsac_vf_f16mf4_rm
// CHECK-RV64-SAME: (<vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmsac.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
//
vfloat16mf4_t test_vfnmsac_vf_f16mf4_rm(vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfnmsac(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmsac_vv_f16mf2_rm
// CHECK-RV64-SAME: (<vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmsac.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
//
vfloat16mf2_t test_vfnmsac_vv_f16mf2_rm(vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfnmsac(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmsac_vf_f16mf2_rm
// CHECK-RV64-SAME: (<vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmsac.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
//
vfloat16mf2_t test_vfnmsac_vf_f16mf2_rm(vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfnmsac(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmsac_vv_f16m1_rm
// CHECK-RV64-SAME: (<vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmsac.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfnmsac_vv_f16m1_rm(vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfnmsac(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmsac_vf_f16m1_rm
// CHECK-RV64-SAME: (<vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmsac.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfnmsac_vf_f16m1_rm(vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfnmsac(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmsac_vv_f16m2_rm
// CHECK-RV64-SAME: (<vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmsac.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
//
vfloat16m2_t test_vfnmsac_vv_f16m2_rm(vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfnmsac(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmsac_vf_f16m2_rm
// CHECK-RV64-SAME: (<vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmsac.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
//
vfloat16m2_t test_vfnmsac_vf_f16m2_rm(vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfnmsac(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmsac_vv_f16m4_rm
// CHECK-RV64-SAME: (<vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmsac.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
//
vfloat16m4_t test_vfnmsac_vv_f16m4_rm(vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfnmsac(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmsac_vf_f16m4_rm
// CHECK-RV64-SAME: (<vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmsac.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
//
vfloat16m4_t test_vfnmsac_vf_f16m4_rm(vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfnmsac(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmsac_vv_f16m8_rm
// CHECK-RV64-SAME: (<vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmsac.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
//
vfloat16m8_t test_vfnmsac_vv_f16m8_rm(vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfnmsac(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmsac_vf_f16m8_rm
// CHECK-RV64-SAME: (<vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmsac.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
//
vfloat16m8_t test_vfnmsac_vf_f16m8_rm(vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfnmsac(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmsac_vv_f32mf2_rm
// CHECK-RV64-SAME: (<vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmsac.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
//
vfloat32mf2_t test_vfnmsac_vv_f32mf2_rm(vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfnmsac(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmsac_vf_f32mf2_rm
// CHECK-RV64-SAME: (<vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmsac.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
//
vfloat32mf2_t test_vfnmsac_vf_f32mf2_rm(vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfnmsac(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmsac_vv_f32m1_rm
// CHECK-RV64-SAME: (<vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmsac.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfnmsac_vv_f32m1_rm(vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfnmsac(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmsac_vf_f32m1_rm
// CHECK-RV64-SAME: (<vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmsac.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfnmsac_vf_f32m1_rm(vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfnmsac(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmsac_vv_f32m2_rm
// CHECK-RV64-SAME: (<vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmsac.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
//
vfloat32m2_t test_vfnmsac_vv_f32m2_rm(vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfnmsac(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmsac_vf_f32m2_rm
// CHECK-RV64-SAME: (<vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmsac.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
//
vfloat32m2_t test_vfnmsac_vf_f32m2_rm(vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfnmsac(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmsac_vv_f32m4_rm
// CHECK-RV64-SAME: (<vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmsac.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
//
vfloat32m4_t test_vfnmsac_vv_f32m4_rm(vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfnmsac(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmsac_vf_f32m4_rm
// CHECK-RV64-SAME: (<vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmsac.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
//
vfloat32m4_t test_vfnmsac_vf_f32m4_rm(vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfnmsac(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmsac_vv_f32m8_rm
// CHECK-RV64-SAME: (<vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmsac.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
//
vfloat32m8_t test_vfnmsac_vv_f32m8_rm(vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfnmsac(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmsac_vf_f32m8_rm
// CHECK-RV64-SAME: (<vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmsac.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
//
vfloat32m8_t test_vfnmsac_vf_f32m8_rm(vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfnmsac(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmsac_vv_f64m1_rm
// CHECK-RV64-SAME: (<vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmsac.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfnmsac_vv_f64m1_rm(vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfnmsac(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmsac_vf_f64m1_rm
// CHECK-RV64-SAME: (<vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmsac.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfnmsac_vf_f64m1_rm(vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfnmsac(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmsac_vv_f64m2_rm
// CHECK-RV64-SAME: (<vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmsac.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
//
vfloat64m2_t test_vfnmsac_vv_f64m2_rm(vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfnmsac(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmsac_vf_f64m2_rm
// CHECK-RV64-SAME: (<vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmsac.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
//
vfloat64m2_t test_vfnmsac_vf_f64m2_rm(vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfnmsac(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmsac_vv_f64m4_rm
// CHECK-RV64-SAME: (<vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmsac.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
//
vfloat64m4_t test_vfnmsac_vv_f64m4_rm(vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfnmsac(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmsac_vf_f64m4_rm
// CHECK-RV64-SAME: (<vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmsac.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
//
vfloat64m4_t test_vfnmsac_vf_f64m4_rm(vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfnmsac(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmsac_vv_f64m8_rm
// CHECK-RV64-SAME: (<vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmsac.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
//
vfloat64m8_t test_vfnmsac_vv_f64m8_rm(vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfnmsac(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmsac_vf_f64m8_rm
// CHECK-RV64-SAME: (<vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmsac.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
//
vfloat64m8_t test_vfnmsac_vf_f64m8_rm(vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfnmsac(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmsac_vv_f16mf4_rm_m
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmsac.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
//
vfloat16mf4_t test_vfnmsac_vv_f16mf4_rm_m(vbool64_t mask, vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfnmsac(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmsac_vf_f16mf4_rm_m
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmsac.mask.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
//
vfloat16mf4_t test_vfnmsac_vf_f16mf4_rm_m(vbool64_t mask, vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfnmsac(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmsac_vv_f16mf2_rm_m
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmsac.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
//
vfloat16mf2_t test_vfnmsac_vv_f16mf2_rm_m(vbool32_t mask, vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfnmsac(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmsac_vf_f16mf2_rm_m
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmsac.mask.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
//
vfloat16mf2_t test_vfnmsac_vf_f16mf2_rm_m(vbool32_t mask, vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfnmsac(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmsac_vv_f16m1_rm_m
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmsac.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfnmsac_vv_f16m1_rm_m(vbool16_t mask, vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfnmsac(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmsac_vf_f16m1_rm_m
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmsac.mask.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfnmsac_vf_f16m1_rm_m(vbool16_t mask, vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfnmsac(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmsac_vv_f16m2_rm_m
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmsac.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
//
vfloat16m2_t test_vfnmsac_vv_f16m2_rm_m(vbool8_t mask, vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfnmsac(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmsac_vf_f16m2_rm_m
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmsac.mask.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
//
vfloat16m2_t test_vfnmsac_vf_f16m2_rm_m(vbool8_t mask, vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfnmsac(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmsac_vv_f16m4_rm_m
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmsac.mask.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
//
vfloat16m4_t test_vfnmsac_vv_f16m4_rm_m(vbool4_t mask, vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfnmsac(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmsac_vf_f16m4_rm_m
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmsac.mask.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
//
vfloat16m4_t test_vfnmsac_vf_f16m4_rm_m(vbool4_t mask, vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfnmsac(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmsac_vv_f16m8_rm_m
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmsac.mask.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
//
vfloat16m8_t test_vfnmsac_vv_f16m8_rm_m(vbool2_t mask, vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfnmsac(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmsac_vf_f16m8_rm_m
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmsac.mask.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
//
vfloat16m8_t test_vfnmsac_vf_f16m8_rm_m(vbool2_t mask, vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfnmsac(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmsac_vv_f32mf2_rm_m
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmsac.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
//
vfloat32mf2_t test_vfnmsac_vv_f32mf2_rm_m(vbool64_t mask, vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfnmsac(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmsac_vf_f32mf2_rm_m
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmsac.mask.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
//
vfloat32mf2_t test_vfnmsac_vf_f32mf2_rm_m(vbool64_t mask, vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfnmsac(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmsac_vv_f32m1_rm_m
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmsac.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfnmsac_vv_f32m1_rm_m(vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfnmsac(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmsac_vf_f32m1_rm_m
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmsac.mask.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfnmsac_vf_f32m1_rm_m(vbool32_t mask, vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfnmsac(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmsac_vv_f32m2_rm_m
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmsac.mask.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
//
vfloat32m2_t test_vfnmsac_vv_f32m2_rm_m(vbool16_t mask, vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfnmsac(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmsac_vf_f32m2_rm_m
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmsac.mask.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
//
vfloat32m2_t test_vfnmsac_vf_f32m2_rm_m(vbool16_t mask, vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfnmsac(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmsac_vv_f32m4_rm_m
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmsac.mask.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
//
vfloat32m4_t test_vfnmsac_vv_f32m4_rm_m(vbool8_t mask, vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfnmsac(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmsac_vf_f32m4_rm_m
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmsac.mask.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
//
vfloat32m4_t test_vfnmsac_vf_f32m4_rm_m(vbool8_t mask, vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfnmsac(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmsac_vv_f32m8_rm_m
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmsac.mask.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
//
vfloat32m8_t test_vfnmsac_vv_f32m8_rm_m(vbool4_t mask, vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfnmsac(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmsac_vf_f32m8_rm_m
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmsac.mask.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
//
vfloat32m8_t test_vfnmsac_vf_f32m8_rm_m(vbool4_t mask, vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfnmsac(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmsac_vv_f64m1_rm_m
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmsac.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfnmsac_vv_f64m1_rm_m(vbool64_t mask, vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfnmsac(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmsac_vf_f64m1_rm_m
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmsac.mask.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfnmsac_vf_f64m1_rm_m(vbool64_t mask, vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfnmsac(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmsac_vv_f64m2_rm_m
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmsac.mask.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
//
vfloat64m2_t test_vfnmsac_vv_f64m2_rm_m(vbool32_t mask, vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfnmsac(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmsac_vf_f64m2_rm_m
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmsac.mask.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
//
vfloat64m2_t test_vfnmsac_vf_f64m2_rm_m(vbool32_t mask, vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfnmsac(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmsac_vv_f64m4_rm_m
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmsac.mask.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
//
vfloat64m4_t test_vfnmsac_vv_f64m4_rm_m(vbool16_t mask, vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfnmsac(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmsac_vf_f64m4_rm_m
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmsac.mask.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
//
vfloat64m4_t test_vfnmsac_vf_f64m4_rm_m(vbool16_t mask, vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfnmsac(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmsac_vv_f64m8_rm_m
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmsac.mask.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
//
vfloat64m8_t test_vfnmsac_vv_f64m8_rm_m(vbool8_t mask, vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfnmsac(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmsac_vf_f64m8_rm_m
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmsac.mask.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
//
vfloat64m8_t test_vfnmsac_vf_f64m8_rm_m(vbool8_t mask, vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfnmsac(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}

clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/overloaded/vfnmsub.c

// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target // REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh \ // RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh \
// RUN: -target-feature +experimental-zvfh -disable-O0-optnone \ // RUN: -target-feature +experimental-zvfh -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ // RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s // RUN: FileCheck --check-prefix=CHECK-RV64 %s
#include <riscv_vector.h> #include <riscv_vector.h>
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmsub_vv_f16mf4 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmsub_vv_f16mf4
// CHECK-RV64-SAME: (<vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK-RV64-SAME: (<vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmsub.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmsub.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
// //
vfloat16mf4_t test_vfnmsub_vv_f16mf4(vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) { vfloat16mf4_t test_vfnmsub_vv_f16mf4(vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfnmsub(vd, vs1, vs2, vl); return __riscv_vfnmsub(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmsub_vf_f16mf4 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmsub_vf_f16mf4
// CHECK-RV64-SAME: (<vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmsub.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmsub.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
// //
vfloat16mf4_t test_vfnmsub_vf_f16mf4(vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) { vfloat16mf4_t test_vfnmsub_vf_f16mf4(vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfnmsub(vd, rs1, vs2, vl); return __riscv_vfnmsub(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmsub_vv_f16mf2 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmsub_vv_f16mf2
// CHECK-RV64-SAME: (<vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmsub.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmsub.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
// //
vfloat16mf2_t test_vfnmsub_vv_f16mf2(vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) { vfloat16mf2_t test_vfnmsub_vv_f16mf2(vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfnmsub(vd, vs1, vs2, vl); return __riscv_vfnmsub(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmsub_vf_f16mf2 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmsub_vf_f16mf2
// CHECK-RV64-SAME: (<vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmsub.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmsub.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
// //
vfloat16mf2_t test_vfnmsub_vf_f16mf2(vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) { vfloat16mf2_t test_vfnmsub_vf_f16mf2(vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfnmsub(vd, rs1, vs2, vl); return __riscv_vfnmsub(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmsub_vv_f16m1 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmsub_vv_f16m1
// CHECK-RV64-SAME: (<vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmsub.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmsub.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
// //
vfloat16m1_t test_vfnmsub_vv_f16m1(vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) { vfloat16m1_t test_vfnmsub_vv_f16m1(vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfnmsub(vd, vs1, vs2, vl); return __riscv_vfnmsub(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmsub_vf_f16m1 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmsub_vf_f16m1
// CHECK-RV64-SAME: (<vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmsub.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmsub.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
// //
vfloat16m1_t test_vfnmsub_vf_f16m1(vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) { vfloat16m1_t test_vfnmsub_vf_f16m1(vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfnmsub(vd, rs1, vs2, vl); return __riscv_vfnmsub(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmsub_vv_f16m2 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmsub_vv_f16m2
// CHECK-RV64-SAME: (<vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmsub.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmsub.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
// //
vfloat16m2_t test_vfnmsub_vv_f16m2(vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) { vfloat16m2_t test_vfnmsub_vv_f16m2(vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfnmsub(vd, vs1, vs2, vl); return __riscv_vfnmsub(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmsub_vf_f16m2 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmsub_vf_f16m2
// CHECK-RV64-SAME: (<vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmsub.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmsub.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
// //
vfloat16m2_t test_vfnmsub_vf_f16m2(vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) { vfloat16m2_t test_vfnmsub_vf_f16m2(vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfnmsub(vd, rs1, vs2, vl); return __riscv_vfnmsub(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmsub_vv_f16m4 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmsub_vv_f16m4
// CHECK-RV64-SAME: (<vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmsub.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmsub.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
// //
vfloat16m4_t test_vfnmsub_vv_f16m4(vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) { vfloat16m4_t test_vfnmsub_vv_f16m4(vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfnmsub(vd, vs1, vs2, vl); return __riscv_vfnmsub(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmsub_vf_f16m4 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmsub_vf_f16m4
// CHECK-RV64-SAME: (<vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmsub.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmsub.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
// //
vfloat16m4_t test_vfnmsub_vf_f16m4(vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) { vfloat16m4_t test_vfnmsub_vf_f16m4(vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfnmsub(vd, rs1, vs2, vl); return __riscv_vfnmsub(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmsub_vv_f16m8 // CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmsub_vv_f16m8
// CHECK-RV64-SAME: (<vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmsub.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmsub.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
// //
vfloat16m8_t test_vfnmsub_vv_f16m8(vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) { vfloat16m8_t test_vfnmsub_vv_f16m8(vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfnmsub(vd, vs1, vs2, vl); return __riscv_vfnmsub(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmsub_vf_f16m8 // CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmsub_vf_f16m8
// CHECK-RV64-SAME: (<vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmsub.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmsub.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
// //
vfloat16m8_t test_vfnmsub_vf_f16m8(vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) { vfloat16m8_t test_vfnmsub_vf_f16m8(vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfnmsub(vd, rs1, vs2, vl); return __riscv_vfnmsub(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmsub_vv_f32mf2 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmsub_vv_f32mf2
// CHECK-RV64-SAME: (<vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmsub.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmsub.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfnmsub_vv_f32mf2(vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) { vfloat32mf2_t test_vfnmsub_vv_f32mf2(vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfnmsub(vd, vs1, vs2, vl); return __riscv_vfnmsub(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmsub_vf_f32mf2 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmsub_vf_f32mf2
// CHECK-RV64-SAME: (<vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmsub.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmsub.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfnmsub_vf_f32mf2(vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) { vfloat32mf2_t test_vfnmsub_vf_f32mf2(vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfnmsub(vd, rs1, vs2, vl); return __riscv_vfnmsub(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmsub_vv_f32m1 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmsub_vv_f32m1
// CHECK-RV64-SAME: (<vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmsub.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmsub.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfnmsub_vv_f32m1(vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) { vfloat32m1_t test_vfnmsub_vv_f32m1(vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfnmsub(vd, vs1, vs2, vl); return __riscv_vfnmsub(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmsub_vf_f32m1 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmsub_vf_f32m1
// CHECK-RV64-SAME: (<vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmsub.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmsub.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfnmsub_vf_f32m1(vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) { vfloat32m1_t test_vfnmsub_vf_f32m1(vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfnmsub(vd, rs1, vs2, vl); return __riscv_vfnmsub(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmsub_vv_f32m2 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmsub_vv_f32m2
// CHECK-RV64-SAME: (<vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmsub.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmsub.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfnmsub_vv_f32m2(vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) { vfloat32m2_t test_vfnmsub_vv_f32m2(vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfnmsub(vd, vs1, vs2, vl); return __riscv_vfnmsub(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmsub_vf_f32m2 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmsub_vf_f32m2
// CHECK-RV64-SAME: (<vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmsub.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmsub.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfnmsub_vf_f32m2(vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) { vfloat32m2_t test_vfnmsub_vf_f32m2(vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfnmsub(vd, rs1, vs2, vl); return __riscv_vfnmsub(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmsub_vv_f32m4 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmsub_vv_f32m4
// CHECK-RV64-SAME: (<vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmsub.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmsub.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfnmsub_vv_f32m4(vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) { vfloat32m4_t test_vfnmsub_vv_f32m4(vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfnmsub(vd, vs1, vs2, vl); return __riscv_vfnmsub(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmsub_vf_f32m4 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmsub_vf_f32m4
// CHECK-RV64-SAME: (<vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmsub.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmsub.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfnmsub_vf_f32m4(vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) { vfloat32m4_t test_vfnmsub_vf_f32m4(vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfnmsub(vd, rs1, vs2, vl); return __riscv_vfnmsub(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmsub_vv_f32m8 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmsub_vv_f32m8
// CHECK-RV64-SAME: (<vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmsub.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmsub.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfnmsub_vv_f32m8(vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) { vfloat32m8_t test_vfnmsub_vv_f32m8(vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfnmsub(vd, vs1, vs2, vl); return __riscv_vfnmsub(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmsub_vf_f32m8 // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmsub_vf_f32m8
// CHECK-RV64-SAME: (<vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmsub.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmsub.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfnmsub_vf_f32m8(vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) { vfloat32m8_t test_vfnmsub_vf_f32m8(vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfnmsub(vd, rs1, vs2, vl); return __riscv_vfnmsub(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmsub_vv_f64m1 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmsub_vv_f64m1
// CHECK-RV64-SAME: (<vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmsub.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmsub.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfnmsub_vv_f64m1(vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) { vfloat64m1_t test_vfnmsub_vv_f64m1(vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfnmsub(vd, vs1, vs2, vl); return __riscv_vfnmsub(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmsub_vf_f64m1 // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmsub_vf_f64m1
// CHECK-RV64-SAME: (<vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmsub.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmsub.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfnmsub_vf_f64m1(vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) { vfloat64m1_t test_vfnmsub_vf_f64m1(vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfnmsub(vd, rs1, vs2, vl); return __riscv_vfnmsub(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmsub_vv_f64m2 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmsub_vv_f64m2
// CHECK-RV64-SAME: (<vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmsub.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmsub.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfnmsub_vv_f64m2(vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) { vfloat64m2_t test_vfnmsub_vv_f64m2(vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfnmsub(vd, vs1, vs2, vl); return __riscv_vfnmsub(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmsub_vf_f64m2 // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmsub_vf_f64m2
// CHECK-RV64-SAME: (<vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmsub.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmsub.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfnmsub_vf_f64m2(vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) { vfloat64m2_t test_vfnmsub_vf_f64m2(vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfnmsub(vd, rs1, vs2, vl); return __riscv_vfnmsub(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmsub_vv_f64m4 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmsub_vv_f64m4
// CHECK-RV64-SAME: (<vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmsub.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmsub.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfnmsub_vv_f64m4(vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) { vfloat64m4_t test_vfnmsub_vv_f64m4(vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfnmsub(vd, vs1, vs2, vl); return __riscv_vfnmsub(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmsub_vf_f64m4 // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmsub_vf_f64m4
// CHECK-RV64-SAME: (<vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmsub.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmsub.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfnmsub_vf_f64m4(vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) { vfloat64m4_t test_vfnmsub_vf_f64m4(vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfnmsub(vd, rs1, vs2, vl); return __riscv_vfnmsub(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmsub_vv_f64m8 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmsub_vv_f64m8
// CHECK-RV64-SAME: (<vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmsub.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmsub.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfnmsub_vv_f64m8(vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) { vfloat64m8_t test_vfnmsub_vv_f64m8(vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfnmsub(vd, vs1, vs2, vl); return __riscv_vfnmsub(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmsub_vf_f64m8 // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmsub_vf_f64m8
// CHECK-RV64-SAME: (<vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmsub.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmsub.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfnmsub_vf_f64m8(vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) { vfloat64m8_t test_vfnmsub_vf_f64m8(vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfnmsub(vd, rs1, vs2, vl); return __riscv_vfnmsub(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmsub_vv_f16mf4_m // CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmsub_vv_f16mf4_m
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmsub.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmsub.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
// //
vfloat16mf4_t test_vfnmsub_vv_f16mf4_m(vbool64_t mask, vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) { vfloat16mf4_t test_vfnmsub_vv_f16mf4_m(vbool64_t mask, vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfnmsub(mask, vd, vs1, vs2, vl); return __riscv_vfnmsub(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmsub_vf_f16mf4_m // CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmsub_vf_f16mf4_m
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmsub.mask.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmsub.mask.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
// //
vfloat16mf4_t test_vfnmsub_vf_f16mf4_m(vbool64_t mask, vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) { vfloat16mf4_t test_vfnmsub_vf_f16mf4_m(vbool64_t mask, vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfnmsub(mask, vd, rs1, vs2, vl); return __riscv_vfnmsub(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmsub_vv_f16mf2_m // CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmsub_vv_f16mf2_m
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmsub.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmsub.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
// //
vfloat16mf2_t test_vfnmsub_vv_f16mf2_m(vbool32_t mask, vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) { vfloat16mf2_t test_vfnmsub_vv_f16mf2_m(vbool32_t mask, vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfnmsub(mask, vd, vs1, vs2, vl); return __riscv_vfnmsub(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmsub_vf_f16mf2_m // CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmsub_vf_f16mf2_m
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmsub.mask.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmsub.mask.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
// //
vfloat16mf2_t test_vfnmsub_vf_f16mf2_m(vbool32_t mask, vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) { vfloat16mf2_t test_vfnmsub_vf_f16mf2_m(vbool32_t mask, vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfnmsub(mask, vd, rs1, vs2, vl); return __riscv_vfnmsub(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmsub_vv_f16m1_m // CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmsub_vv_f16m1_m
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmsub.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmsub.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
// //
vfloat16m1_t test_vfnmsub_vv_f16m1_m(vbool16_t mask, vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) { vfloat16m1_t test_vfnmsub_vv_f16m1_m(vbool16_t mask, vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfnmsub(mask, vd, vs1, vs2, vl); return __riscv_vfnmsub(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmsub_vf_f16m1_m // CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmsub_vf_f16m1_m
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmsub.mask.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmsub.mask.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
// //
vfloat16m1_t test_vfnmsub_vf_f16m1_m(vbool16_t mask, vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) { vfloat16m1_t test_vfnmsub_vf_f16m1_m(vbool16_t mask, vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfnmsub(mask, vd, rs1, vs2, vl); return __riscv_vfnmsub(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmsub_vv_f16m2_m // CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmsub_vv_f16m2_m
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmsub.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmsub.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
// //
vfloat16m2_t test_vfnmsub_vv_f16m2_m(vbool8_t mask, vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) { vfloat16m2_t test_vfnmsub_vv_f16m2_m(vbool8_t mask, vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfnmsub(mask, vd, vs1, vs2, vl); return __riscv_vfnmsub(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmsub_vf_f16m2_m // CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmsub_vf_f16m2_m
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmsub.mask.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmsub.mask.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
// //
vfloat16m2_t test_vfnmsub_vf_f16m2_m(vbool8_t mask, vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) { vfloat16m2_t test_vfnmsub_vf_f16m2_m(vbool8_t mask, vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfnmsub(mask, vd, rs1, vs2, vl); return __riscv_vfnmsub(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmsub_vv_f16m4_m // CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmsub_vv_f16m4_m
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmsub.mask.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmsub.mask.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
// //
vfloat16m4_t test_vfnmsub_vv_f16m4_m(vbool4_t mask, vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) { vfloat16m4_t test_vfnmsub_vv_f16m4_m(vbool4_t mask, vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfnmsub(mask, vd, vs1, vs2, vl); return __riscv_vfnmsub(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmsub_vf_f16m4_m // CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmsub_vf_f16m4_m
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmsub.mask.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmsub.mask.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
// //
vfloat16m4_t test_vfnmsub_vf_f16m4_m(vbool4_t mask, vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) { vfloat16m4_t test_vfnmsub_vf_f16m4_m(vbool4_t mask, vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfnmsub(mask, vd, rs1, vs2, vl); return __riscv_vfnmsub(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmsub_vv_f16m8_m // CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmsub_vv_f16m8_m
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmsub.mask.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmsub.mask.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
// //
vfloat16m8_t test_vfnmsub_vv_f16m8_m(vbool2_t mask, vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) { vfloat16m8_t test_vfnmsub_vv_f16m8_m(vbool2_t mask, vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfnmsub(mask, vd, vs1, vs2, vl); return __riscv_vfnmsub(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmsub_vf_f16m8_m // CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmsub_vf_f16m8_m
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmsub.mask.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmsub.mask.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
// //
vfloat16m8_t test_vfnmsub_vf_f16m8_m(vbool2_t mask, vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) { vfloat16m8_t test_vfnmsub_vf_f16m8_m(vbool2_t mask, vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfnmsub(mask, vd, rs1, vs2, vl); return __riscv_vfnmsub(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmsub_vv_f32mf2_m // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmsub_vv_f32mf2_m
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmsub.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmsub.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfnmsub_vv_f32mf2_m(vbool64_t mask, vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) { vfloat32mf2_t test_vfnmsub_vv_f32mf2_m(vbool64_t mask, vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfnmsub(mask, vd, vs1, vs2, vl); return __riscv_vfnmsub(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmsub_vf_f32mf2_m // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmsub_vf_f32mf2_m
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmsub.mask.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmsub.mask.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfnmsub_vf_f32mf2_m(vbool64_t mask, vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) { vfloat32mf2_t test_vfnmsub_vf_f32mf2_m(vbool64_t mask, vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfnmsub(mask, vd, rs1, vs2, vl); return __riscv_vfnmsub(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmsub_vv_f32m1_m // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmsub_vv_f32m1_m
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmsub.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmsub.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfnmsub_vv_f32m1_m(vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) { vfloat32m1_t test_vfnmsub_vv_f32m1_m(vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfnmsub(mask, vd, vs1, vs2, vl); return __riscv_vfnmsub(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmsub_vf_f32m1_m // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmsub_vf_f32m1_m
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmsub.mask.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmsub.mask.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfnmsub_vf_f32m1_m(vbool32_t mask, vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) { vfloat32m1_t test_vfnmsub_vf_f32m1_m(vbool32_t mask, vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfnmsub(mask, vd, rs1, vs2, vl); return __riscv_vfnmsub(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmsub_vv_f32m2_m // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmsub_vv_f32m2_m
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmsub.mask.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmsub.mask.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfnmsub_vv_f32m2_m(vbool16_t mask, vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) { vfloat32m2_t test_vfnmsub_vv_f32m2_m(vbool16_t mask, vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfnmsub(mask, vd, vs1, vs2, vl); return __riscv_vfnmsub(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmsub_vf_f32m2_m // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmsub_vf_f32m2_m
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmsub.mask.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmsub.mask.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfnmsub_vf_f32m2_m(vbool16_t mask, vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) { vfloat32m2_t test_vfnmsub_vf_f32m2_m(vbool16_t mask, vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfnmsub(mask, vd, rs1, vs2, vl); return __riscv_vfnmsub(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmsub_vv_f32m4_m // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmsub_vv_f32m4_m
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmsub.mask.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmsub.mask.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfnmsub_vv_f32m4_m(vbool8_t mask, vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) { vfloat32m4_t test_vfnmsub_vv_f32m4_m(vbool8_t mask, vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfnmsub(mask, vd, vs1, vs2, vl); return __riscv_vfnmsub(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmsub_vf_f32m4_m // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmsub_vf_f32m4_m
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmsub.mask.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmsub.mask.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfnmsub_vf_f32m4_m(vbool8_t mask, vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) { vfloat32m4_t test_vfnmsub_vf_f32m4_m(vbool8_t mask, vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfnmsub(mask, vd, rs1, vs2, vl); return __riscv_vfnmsub(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmsub_vv_f32m8_m // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmsub_vv_f32m8_m
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmsub.mask.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmsub.mask.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfnmsub_vv_f32m8_m(vbool4_t mask, vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) { vfloat32m8_t test_vfnmsub_vv_f32m8_m(vbool4_t mask, vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfnmsub(mask, vd, vs1, vs2, vl); return __riscv_vfnmsub(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmsub_vf_f32m8_m // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmsub_vf_f32m8_m
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmsub.mask.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmsub.mask.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfnmsub_vf_f32m8_m(vbool4_t mask, vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) { vfloat32m8_t test_vfnmsub_vf_f32m8_m(vbool4_t mask, vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfnmsub(mask, vd, rs1, vs2, vl); return __riscv_vfnmsub(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmsub_vv_f64m1_m // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmsub_vv_f64m1_m
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmsub.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmsub.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfnmsub_vv_f64m1_m(vbool64_t mask, vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) { vfloat64m1_t test_vfnmsub_vv_f64m1_m(vbool64_t mask, vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfnmsub(mask, vd, vs1, vs2, vl); return __riscv_vfnmsub(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmsub_vf_f64m1_m // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmsub_vf_f64m1_m
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmsub.mask.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmsub.mask.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfnmsub_vf_f64m1_m(vbool64_t mask, vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) { vfloat64m1_t test_vfnmsub_vf_f64m1_m(vbool64_t mask, vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfnmsub(mask, vd, rs1, vs2, vl); return __riscv_vfnmsub(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmsub_vv_f64m2_m // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmsub_vv_f64m2_m
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmsub.mask.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmsub.mask.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfnmsub_vv_f64m2_m(vbool32_t mask, vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) { vfloat64m2_t test_vfnmsub_vv_f64m2_m(vbool32_t mask, vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfnmsub(mask, vd, vs1, vs2, vl); return __riscv_vfnmsub(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmsub_vf_f64m2_m // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmsub_vf_f64m2_m
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmsub.mask.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmsub.mask.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfnmsub_vf_f64m2_m(vbool32_t mask, vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) { vfloat64m2_t test_vfnmsub_vf_f64m2_m(vbool32_t mask, vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfnmsub(mask, vd, rs1, vs2, vl); return __riscv_vfnmsub(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmsub_vv_f64m4_m // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmsub_vv_f64m4_m
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmsub.mask.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmsub.mask.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfnmsub_vv_f64m4_m(vbool16_t mask, vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) { vfloat64m4_t test_vfnmsub_vv_f64m4_m(vbool16_t mask, vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfnmsub(mask, vd, vs1, vs2, vl); return __riscv_vfnmsub(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmsub_vf_f64m4_m // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmsub_vf_f64m4_m
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmsub.mask.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmsub.mask.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfnmsub_vf_f64m4_m(vbool16_t mask, vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) { vfloat64m4_t test_vfnmsub_vf_f64m4_m(vbool16_t mask, vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfnmsub(mask, vd, rs1, vs2, vl); return __riscv_vfnmsub(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmsub_vv_f64m8_m // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmsub_vv_f64m8_m
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmsub.mask.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmsub.mask.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfnmsub_vv_f64m8_m(vbool8_t mask, vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) { vfloat64m8_t test_vfnmsub_vv_f64m8_m(vbool8_t mask, vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfnmsub(mask, vd, vs1, vs2, vl); return __riscv_vfnmsub(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmsub_vf_f64m8_m // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmsub_vf_f64m8_m
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmsub.mask.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 3) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmsub.mask.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfnmsub_vf_f64m8_m(vbool8_t mask, vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) { vfloat64m8_t test_vfnmsub_vf_f64m8_m(vbool8_t mask, vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfnmsub(mask, vd, rs1, vs2, vl); return __riscv_vfnmsub(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmsub_vv_f16mf4_rm
// CHECK-RV64-SAME: (<vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmsub.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
//
vfloat16mf4_t test_vfnmsub_vv_f16mf4_rm(vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfnmsub(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmsub_vf_f16mf4_rm
// CHECK-RV64-SAME: (<vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmsub.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
//
vfloat16mf4_t test_vfnmsub_vf_f16mf4_rm(vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfnmsub(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmsub_vv_f16mf2_rm
// CHECK-RV64-SAME: (<vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmsub.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
//
vfloat16mf2_t test_vfnmsub_vv_f16mf2_rm(vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfnmsub(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmsub_vf_f16mf2_rm
// CHECK-RV64-SAME: (<vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmsub.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
//
vfloat16mf2_t test_vfnmsub_vf_f16mf2_rm(vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfnmsub(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmsub_vv_f16m1_rm
// CHECK-RV64-SAME: (<vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmsub.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfnmsub_vv_f16m1_rm(vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfnmsub(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmsub_vf_f16m1_rm
// CHECK-RV64-SAME: (<vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmsub.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfnmsub_vf_f16m1_rm(vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfnmsub(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmsub_vv_f16m2_rm
// CHECK-RV64-SAME: (<vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmsub.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
//
vfloat16m2_t test_vfnmsub_vv_f16m2_rm(vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfnmsub(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmsub_vf_f16m2_rm
// CHECK-RV64-SAME: (<vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmsub.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
//
vfloat16m2_t test_vfnmsub_vf_f16m2_rm(vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfnmsub(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmsub_vv_f16m4_rm
// CHECK-RV64-SAME: (<vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmsub.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
//
vfloat16m4_t test_vfnmsub_vv_f16m4_rm(vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfnmsub(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmsub_vf_f16m4_rm
// CHECK-RV64-SAME: (<vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmsub.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
//
vfloat16m4_t test_vfnmsub_vf_f16m4_rm(vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfnmsub(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmsub_vv_f16m8_rm
// CHECK-RV64-SAME: (<vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmsub.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
//
vfloat16m8_t test_vfnmsub_vv_f16m8_rm(vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfnmsub(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmsub_vf_f16m8_rm
// CHECK-RV64-SAME: (<vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmsub.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
//
vfloat16m8_t test_vfnmsub_vf_f16m8_rm(vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfnmsub(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmsub_vv_f32mf2_rm
// CHECK-RV64-SAME: (<vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmsub.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
//
vfloat32mf2_t test_vfnmsub_vv_f32mf2_rm(vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfnmsub(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmsub_vf_f32mf2_rm
// CHECK-RV64-SAME: (<vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmsub.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
//
vfloat32mf2_t test_vfnmsub_vf_f32mf2_rm(vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfnmsub(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmsub_vv_f32m1_rm
// CHECK-RV64-SAME: (<vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmsub.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfnmsub_vv_f32m1_rm(vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfnmsub(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmsub_vf_f32m1_rm
// CHECK-RV64-SAME: (<vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmsub.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfnmsub_vf_f32m1_rm(vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfnmsub(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmsub_vv_f32m2_rm
// CHECK-RV64-SAME: (<vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmsub.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
//
vfloat32m2_t test_vfnmsub_vv_f32m2_rm(vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfnmsub(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmsub_vf_f32m2_rm
// CHECK-RV64-SAME: (<vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmsub.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
//
vfloat32m2_t test_vfnmsub_vf_f32m2_rm(vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfnmsub(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmsub_vv_f32m4_rm
// CHECK-RV64-SAME: (<vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmsub.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
//
vfloat32m4_t test_vfnmsub_vv_f32m4_rm(vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfnmsub(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmsub_vf_f32m4_rm
// CHECK-RV64-SAME: (<vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmsub.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
//
vfloat32m4_t test_vfnmsub_vf_f32m4_rm(vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfnmsub(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmsub_vv_f32m8_rm
// CHECK-RV64-SAME: (<vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmsub.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
//
vfloat32m8_t test_vfnmsub_vv_f32m8_rm(vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfnmsub(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmsub_vf_f32m8_rm
// CHECK-RV64-SAME: (<vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmsub.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
//
vfloat32m8_t test_vfnmsub_vf_f32m8_rm(vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfnmsub(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmsub_vv_f64m1_rm
// CHECK-RV64-SAME: (<vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmsub.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfnmsub_vv_f64m1_rm(vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfnmsub(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmsub_vf_f64m1_rm
// CHECK-RV64-SAME: (<vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmsub.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfnmsub_vf_f64m1_rm(vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfnmsub(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmsub_vv_f64m2_rm
// CHECK-RV64-SAME: (<vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmsub.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
//
vfloat64m2_t test_vfnmsub_vv_f64m2_rm(vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfnmsub(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmsub_vf_f64m2_rm
// CHECK-RV64-SAME: (<vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmsub.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
//
vfloat64m2_t test_vfnmsub_vf_f64m2_rm(vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfnmsub(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmsub_vv_f64m4_rm
// CHECK-RV64-SAME: (<vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmsub.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
//
vfloat64m4_t test_vfnmsub_vv_f64m4_rm(vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfnmsub(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmsub_vf_f64m4_rm
// CHECK-RV64-SAME: (<vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmsub.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
//
vfloat64m4_t test_vfnmsub_vf_f64m4_rm(vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfnmsub(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmsub_vv_f64m8_rm
// CHECK-RV64-SAME: (<vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmsub.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
//
vfloat64m8_t test_vfnmsub_vv_f64m8_rm(vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfnmsub(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmsub_vf_f64m8_rm
// CHECK-RV64-SAME: (<vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmsub.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
//
vfloat64m8_t test_vfnmsub_vf_f64m8_rm(vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfnmsub(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmsub_vv_f16mf4_rm_m
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmsub.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
//
vfloat16mf4_t test_vfnmsub_vv_f16mf4_rm_m(vbool64_t mask, vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfnmsub(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmsub_vf_f16mf4_rm_m
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmsub.mask.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
//
vfloat16mf4_t test_vfnmsub_vf_f16mf4_rm_m(vbool64_t mask, vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfnmsub(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmsub_vv_f16mf2_rm_m
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmsub.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
//
vfloat16mf2_t test_vfnmsub_vv_f16mf2_rm_m(vbool32_t mask, vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfnmsub(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmsub_vf_f16mf2_rm_m
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmsub.mask.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
//
vfloat16mf2_t test_vfnmsub_vf_f16mf2_rm_m(vbool32_t mask, vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfnmsub(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmsub_vv_f16m1_rm_m
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmsub.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfnmsub_vv_f16m1_rm_m(vbool16_t mask, vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfnmsub(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmsub_vf_f16m1_rm_m
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmsub.mask.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfnmsub_vf_f16m1_rm_m(vbool16_t mask, vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfnmsub(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmsub_vv_f16m2_rm_m
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmsub.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
//
vfloat16m2_t test_vfnmsub_vv_f16m2_rm_m(vbool8_t mask, vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfnmsub(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmsub_vf_f16m2_rm_m
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmsub.mask.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
//
vfloat16m2_t test_vfnmsub_vf_f16m2_rm_m(vbool8_t mask, vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfnmsub(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmsub_vv_f16m4_rm_m
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmsub.mask.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
//
vfloat16m4_t test_vfnmsub_vv_f16m4_rm_m(vbool4_t mask, vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfnmsub(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmsub_vf_f16m4_rm_m
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmsub.mask.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
//
vfloat16m4_t test_vfnmsub_vf_f16m4_rm_m(vbool4_t mask, vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfnmsub(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmsub_vv_f16m8_rm_m
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmsub.mask.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
//
vfloat16m8_t test_vfnmsub_vv_f16m8_rm_m(vbool2_t mask, vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfnmsub(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmsub_vf_f16m8_rm_m
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmsub.mask.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
//
vfloat16m8_t test_vfnmsub_vf_f16m8_rm_m(vbool2_t mask, vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfnmsub(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmsub_vv_f32mf2_rm_m
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmsub.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
//
vfloat32mf2_t test_vfnmsub_vv_f32mf2_rm_m(vbool64_t mask, vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfnmsub(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmsub_vf_f32mf2_rm_m
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmsub.mask.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
//
vfloat32mf2_t test_vfnmsub_vf_f32mf2_rm_m(vbool64_t mask, vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfnmsub(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmsub_vv_f32m1_rm_m
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmsub.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfnmsub_vv_f32m1_rm_m(vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfnmsub(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmsub_vf_f32m1_rm_m
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmsub.mask.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfnmsub_vf_f32m1_rm_m(vbool32_t mask, vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfnmsub(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmsub_vv_f32m2_rm_m
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmsub.mask.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
//
vfloat32m2_t test_vfnmsub_vv_f32m2_rm_m(vbool16_t mask, vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfnmsub(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmsub_vf_f32m2_rm_m
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmsub.mask.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
//
vfloat32m2_t test_vfnmsub_vf_f32m2_rm_m(vbool16_t mask, vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfnmsub(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmsub_vv_f32m4_rm_m
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmsub.mask.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
//
vfloat32m4_t test_vfnmsub_vv_f32m4_rm_m(vbool8_t mask, vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfnmsub(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmsub_vf_f32m4_rm_m
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmsub.mask.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
//
vfloat32m4_t test_vfnmsub_vf_f32m4_rm_m(vbool8_t mask, vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfnmsub(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmsub_vv_f32m8_rm_m
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmsub.mask.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
//
vfloat32m8_t test_vfnmsub_vv_f32m8_rm_m(vbool4_t mask, vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfnmsub(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmsub_vf_f32m8_rm_m
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmsub.mask.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
//
vfloat32m8_t test_vfnmsub_vf_f32m8_rm_m(vbool4_t mask, vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfnmsub(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmsub_vv_f64m1_rm_m
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmsub.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfnmsub_vv_f64m1_rm_m(vbool64_t mask, vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfnmsub(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmsub_vf_f64m1_rm_m
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmsub.mask.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfnmsub_vf_f64m1_rm_m(vbool64_t mask, vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfnmsub(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmsub_vv_f64m2_rm_m
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmsub.mask.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
//
vfloat64m2_t test_vfnmsub_vv_f64m2_rm_m(vbool32_t mask, vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfnmsub(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmsub_vf_f64m2_rm_m
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmsub.mask.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
//
vfloat64m2_t test_vfnmsub_vf_f64m2_rm_m(vbool32_t mask, vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfnmsub(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmsub_vv_f64m4_rm_m
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmsub.mask.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
//
vfloat64m4_t test_vfnmsub_vv_f64m4_rm_m(vbool16_t mask, vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfnmsub(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmsub_vf_f64m4_rm_m
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmsub.mask.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
//
vfloat64m4_t test_vfnmsub_vf_f64m4_rm_m(vbool16_t mask, vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfnmsub(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmsub_vv_f64m8_rm_m
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmsub.mask.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
//
vfloat64m8_t test_vfnmsub_vv_f64m8_rm_m(vbool8_t mask, vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfnmsub(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmsub_vf_f64m8_rm_m
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmsub.mask.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 3)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
//
vfloat64m8_t test_vfnmsub_vf_f64m8_rm_m(vbool8_t mask, vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfnmsub(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}

clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmacc.c

// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target // REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh \ // RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh \
// RUN: -target-feature +experimental-zvfh -disable-O0-optnone \ // RUN: -target-feature +experimental-zvfh -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ // RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s // RUN: FileCheck --check-prefix=CHECK-RV64 %s
#include <riscv_vector.h> #include <riscv_vector.h>
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmacc_vv_f16mf4_tu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmacc_vv_f16mf4_tu
// CHECK-RV64-SAME: (<vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK-RV64-SAME: (<vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmacc.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmacc.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
// //
vfloat16mf4_t test_vfmacc_vv_f16mf4_tu(vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) { vfloat16mf4_t test_vfmacc_vv_f16mf4_tu(vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfmacc_vv_f16mf4_tu(vd, vs1, vs2, vl); return __riscv_vfmacc_vv_f16mf4_tu(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmacc_vf_f16mf4_tu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmacc_vf_f16mf4_tu
// CHECK-RV64-SAME: (<vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmacc.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmacc.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
// //
vfloat16mf4_t test_vfmacc_vf_f16mf4_tu(vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) { vfloat16mf4_t test_vfmacc_vf_f16mf4_tu(vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfmacc_vf_f16mf4_tu(vd, rs1, vs2, vl); return __riscv_vfmacc_vf_f16mf4_tu(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmacc_vv_f16mf2_tu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmacc_vv_f16mf2_tu
// CHECK-RV64-SAME: (<vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmacc.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmacc.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
// //
vfloat16mf2_t test_vfmacc_vv_f16mf2_tu(vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) { vfloat16mf2_t test_vfmacc_vv_f16mf2_tu(vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfmacc_vv_f16mf2_tu(vd, vs1, vs2, vl); return __riscv_vfmacc_vv_f16mf2_tu(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmacc_vf_f16mf2_tu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmacc_vf_f16mf2_tu
// CHECK-RV64-SAME: (<vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmacc.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmacc.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
// //
vfloat16mf2_t test_vfmacc_vf_f16mf2_tu(vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) { vfloat16mf2_t test_vfmacc_vf_f16mf2_tu(vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfmacc_vf_f16mf2_tu(vd, rs1, vs2, vl); return __riscv_vfmacc_vf_f16mf2_tu(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmacc_vv_f16m1_tu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmacc_vv_f16m1_tu
// CHECK-RV64-SAME: (<vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmacc.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmacc.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
// //
vfloat16m1_t test_vfmacc_vv_f16m1_tu(vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) { vfloat16m1_t test_vfmacc_vv_f16m1_tu(vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfmacc_vv_f16m1_tu(vd, vs1, vs2, vl); return __riscv_vfmacc_vv_f16m1_tu(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmacc_vf_f16m1_tu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmacc_vf_f16m1_tu
// CHECK-RV64-SAME: (<vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmacc.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmacc.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
// //
vfloat16m1_t test_vfmacc_vf_f16m1_tu(vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) { vfloat16m1_t test_vfmacc_vf_f16m1_tu(vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfmacc_vf_f16m1_tu(vd, rs1, vs2, vl); return __riscv_vfmacc_vf_f16m1_tu(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmacc_vv_f16m2_tu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmacc_vv_f16m2_tu
// CHECK-RV64-SAME: (<vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmacc.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmacc.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
// //
vfloat16m2_t test_vfmacc_vv_f16m2_tu(vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) { vfloat16m2_t test_vfmacc_vv_f16m2_tu(vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfmacc_vv_f16m2_tu(vd, vs1, vs2, vl); return __riscv_vfmacc_vv_f16m2_tu(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmacc_vf_f16m2_tu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmacc_vf_f16m2_tu
// CHECK-RV64-SAME: (<vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmacc.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmacc.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
// //
vfloat16m2_t test_vfmacc_vf_f16m2_tu(vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) { vfloat16m2_t test_vfmacc_vf_f16m2_tu(vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfmacc_vf_f16m2_tu(vd, rs1, vs2, vl); return __riscv_vfmacc_vf_f16m2_tu(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmacc_vv_f16m4_tu // CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmacc_vv_f16m4_tu
// CHECK-RV64-SAME: (<vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmacc.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmacc.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
// //
vfloat16m4_t test_vfmacc_vv_f16m4_tu(vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) { vfloat16m4_t test_vfmacc_vv_f16m4_tu(vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfmacc_vv_f16m4_tu(vd, vs1, vs2, vl); return __riscv_vfmacc_vv_f16m4_tu(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmacc_vf_f16m4_tu // CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmacc_vf_f16m4_tu
// CHECK-RV64-SAME: (<vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmacc.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmacc.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
// //
vfloat16m4_t test_vfmacc_vf_f16m4_tu(vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) { vfloat16m4_t test_vfmacc_vf_f16m4_tu(vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfmacc_vf_f16m4_tu(vd, rs1, vs2, vl); return __riscv_vfmacc_vf_f16m4_tu(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmacc_vv_f16m8_tu // CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmacc_vv_f16m8_tu
// CHECK-RV64-SAME: (<vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmacc.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmacc.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
// //
vfloat16m8_t test_vfmacc_vv_f16m8_tu(vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) { vfloat16m8_t test_vfmacc_vv_f16m8_tu(vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfmacc_vv_f16m8_tu(vd, vs1, vs2, vl); return __riscv_vfmacc_vv_f16m8_tu(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmacc_vf_f16m8_tu // CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmacc_vf_f16m8_tu
// CHECK-RV64-SAME: (<vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmacc.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmacc.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
// //
vfloat16m8_t test_vfmacc_vf_f16m8_tu(vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) { vfloat16m8_t test_vfmacc_vf_f16m8_tu(vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfmacc_vf_f16m8_tu(vd, rs1, vs2, vl); return __riscv_vfmacc_vf_f16m8_tu(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmacc_vv_f32mf2_tu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmacc_vv_f32mf2_tu
// CHECK-RV64-SAME: (<vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmacc.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmacc.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfmacc_vv_f32mf2_tu(vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) { vfloat32mf2_t test_vfmacc_vv_f32mf2_tu(vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfmacc_vv_f32mf2_tu(vd, vs1, vs2, vl); return __riscv_vfmacc_vv_f32mf2_tu(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmacc_vf_f32mf2_tu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmacc_vf_f32mf2_tu
// CHECK-RV64-SAME: (<vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmacc.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmacc.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfmacc_vf_f32mf2_tu(vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) { vfloat32mf2_t test_vfmacc_vf_f32mf2_tu(vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfmacc_vf_f32mf2_tu(vd, rs1, vs2, vl); return __riscv_vfmacc_vf_f32mf2_tu(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmacc_vv_f32m1_tu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmacc_vv_f32m1_tu
// CHECK-RV64-SAME: (<vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmacc.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmacc.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfmacc_vv_f32m1_tu(vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) { vfloat32m1_t test_vfmacc_vv_f32m1_tu(vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfmacc_vv_f32m1_tu(vd, vs1, vs2, vl); return __riscv_vfmacc_vv_f32m1_tu(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmacc_vf_f32m1_tu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmacc_vf_f32m1_tu
// CHECK-RV64-SAME: (<vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmacc.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmacc.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfmacc_vf_f32m1_tu(vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) { vfloat32m1_t test_vfmacc_vf_f32m1_tu(vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfmacc_vf_f32m1_tu(vd, rs1, vs2, vl); return __riscv_vfmacc_vf_f32m1_tu(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmacc_vv_f32m2_tu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmacc_vv_f32m2_tu
// CHECK-RV64-SAME: (<vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmacc.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmacc.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfmacc_vv_f32m2_tu(vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) { vfloat32m2_t test_vfmacc_vv_f32m2_tu(vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfmacc_vv_f32m2_tu(vd, vs1, vs2, vl); return __riscv_vfmacc_vv_f32m2_tu(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmacc_vf_f32m2_tu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmacc_vf_f32m2_tu
// CHECK-RV64-SAME: (<vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmacc.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmacc.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfmacc_vf_f32m2_tu(vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) { vfloat32m2_t test_vfmacc_vf_f32m2_tu(vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfmacc_vf_f32m2_tu(vd, rs1, vs2, vl); return __riscv_vfmacc_vf_f32m2_tu(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmacc_vv_f32m4_tu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmacc_vv_f32m4_tu
// CHECK-RV64-SAME: (<vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmacc.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmacc.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfmacc_vv_f32m4_tu(vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) { vfloat32m4_t test_vfmacc_vv_f32m4_tu(vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfmacc_vv_f32m4_tu(vd, vs1, vs2, vl); return __riscv_vfmacc_vv_f32m4_tu(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmacc_vf_f32m4_tu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmacc_vf_f32m4_tu
// CHECK-RV64-SAME: (<vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmacc.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmacc.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfmacc_vf_f32m4_tu(vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) { vfloat32m4_t test_vfmacc_vf_f32m4_tu(vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfmacc_vf_f32m4_tu(vd, rs1, vs2, vl); return __riscv_vfmacc_vf_f32m4_tu(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmacc_vv_f32m8_tu // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmacc_vv_f32m8_tu
// CHECK-RV64-SAME: (<vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmacc.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmacc.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfmacc_vv_f32m8_tu(vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) { vfloat32m8_t test_vfmacc_vv_f32m8_tu(vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfmacc_vv_f32m8_tu(vd, vs1, vs2, vl); return __riscv_vfmacc_vv_f32m8_tu(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmacc_vf_f32m8_tu // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmacc_vf_f32m8_tu
// CHECK-RV64-SAME: (<vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmacc.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmacc.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfmacc_vf_f32m8_tu(vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) { vfloat32m8_t test_vfmacc_vf_f32m8_tu(vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfmacc_vf_f32m8_tu(vd, rs1, vs2, vl); return __riscv_vfmacc_vf_f32m8_tu(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmacc_vv_f64m1_tu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmacc_vv_f64m1_tu
// CHECK-RV64-SAME: (<vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmacc.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmacc.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfmacc_vv_f64m1_tu(vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) { vfloat64m1_t test_vfmacc_vv_f64m1_tu(vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfmacc_vv_f64m1_tu(vd, vs1, vs2, vl); return __riscv_vfmacc_vv_f64m1_tu(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmacc_vf_f64m1_tu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmacc_vf_f64m1_tu
// CHECK-RV64-SAME: (<vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmacc.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmacc.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfmacc_vf_f64m1_tu(vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) { vfloat64m1_t test_vfmacc_vf_f64m1_tu(vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfmacc_vf_f64m1_tu(vd, rs1, vs2, vl); return __riscv_vfmacc_vf_f64m1_tu(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmacc_vv_f64m2_tu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmacc_vv_f64m2_tu
// CHECK-RV64-SAME: (<vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmacc.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmacc.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfmacc_vv_f64m2_tu(vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) { vfloat64m2_t test_vfmacc_vv_f64m2_tu(vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfmacc_vv_f64m2_tu(vd, vs1, vs2, vl); return __riscv_vfmacc_vv_f64m2_tu(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmacc_vf_f64m2_tu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmacc_vf_f64m2_tu
// CHECK-RV64-SAME: (<vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmacc.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmacc.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfmacc_vf_f64m2_tu(vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) { vfloat64m2_t test_vfmacc_vf_f64m2_tu(vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfmacc_vf_f64m2_tu(vd, rs1, vs2, vl); return __riscv_vfmacc_vf_f64m2_tu(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmacc_vv_f64m4_tu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmacc_vv_f64m4_tu
// CHECK-RV64-SAME: (<vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmacc.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmacc.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfmacc_vv_f64m4_tu(vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) { vfloat64m4_t test_vfmacc_vv_f64m4_tu(vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfmacc_vv_f64m4_tu(vd, vs1, vs2, vl); return __riscv_vfmacc_vv_f64m4_tu(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmacc_vf_f64m4_tu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmacc_vf_f64m4_tu
// CHECK-RV64-SAME: (<vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmacc.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmacc.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfmacc_vf_f64m4_tu(vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) { vfloat64m4_t test_vfmacc_vf_f64m4_tu(vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfmacc_vf_f64m4_tu(vd, rs1, vs2, vl); return __riscv_vfmacc_vf_f64m4_tu(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmacc_vv_f64m8_tu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmacc_vv_f64m8_tu
// CHECK-RV64-SAME: (<vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmacc.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmacc.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfmacc_vv_f64m8_tu(vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) { vfloat64m8_t test_vfmacc_vv_f64m8_tu(vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfmacc_vv_f64m8_tu(vd, vs1, vs2, vl); return __riscv_vfmacc_vv_f64m8_tu(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmacc_vf_f64m8_tu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmacc_vf_f64m8_tu
// CHECK-RV64-SAME: (<vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmacc.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmacc.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfmacc_vf_f64m8_tu(vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) { vfloat64m8_t test_vfmacc_vf_f64m8_tu(vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfmacc_vf_f64m8_tu(vd, rs1, vs2, vl); return __riscv_vfmacc_vf_f64m8_tu(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmacc_vv_f16mf4_tum // CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmacc_vv_f16mf4_tum
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmacc.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmacc.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
// //
vfloat16mf4_t test_vfmacc_vv_f16mf4_tum(vbool64_t mask, vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) { vfloat16mf4_t test_vfmacc_vv_f16mf4_tum(vbool64_t mask, vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfmacc_vv_f16mf4_tum(mask, vd, vs1, vs2, vl); return __riscv_vfmacc_vv_f16mf4_tum(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmacc_vf_f16mf4_tum // CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmacc_vf_f16mf4_tum
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmacc.mask.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmacc.mask.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
// //
vfloat16mf4_t test_vfmacc_vf_f16mf4_tum(vbool64_t mask, vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) { vfloat16mf4_t test_vfmacc_vf_f16mf4_tum(vbool64_t mask, vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfmacc_vf_f16mf4_tum(mask, vd, rs1, vs2, vl); return __riscv_vfmacc_vf_f16mf4_tum(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmacc_vv_f16mf2_tum // CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmacc_vv_f16mf2_tum
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmacc.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmacc.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
// //
vfloat16mf2_t test_vfmacc_vv_f16mf2_tum(vbool32_t mask, vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) { vfloat16mf2_t test_vfmacc_vv_f16mf2_tum(vbool32_t mask, vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfmacc_vv_f16mf2_tum(mask, vd, vs1, vs2, vl); return __riscv_vfmacc_vv_f16mf2_tum(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmacc_vf_f16mf2_tum // CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmacc_vf_f16mf2_tum
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmacc.mask.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmacc.mask.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
// //
vfloat16mf2_t test_vfmacc_vf_f16mf2_tum(vbool32_t mask, vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) { vfloat16mf2_t test_vfmacc_vf_f16mf2_tum(vbool32_t mask, vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfmacc_vf_f16mf2_tum(mask, vd, rs1, vs2, vl); return __riscv_vfmacc_vf_f16mf2_tum(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmacc_vv_f16m1_tum // CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmacc_vv_f16m1_tum
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmacc.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmacc.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
// //
vfloat16m1_t test_vfmacc_vv_f16m1_tum(vbool16_t mask, vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) { vfloat16m1_t test_vfmacc_vv_f16m1_tum(vbool16_t mask, vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfmacc_vv_f16m1_tum(mask, vd, vs1, vs2, vl); return __riscv_vfmacc_vv_f16m1_tum(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmacc_vf_f16m1_tum // CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmacc_vf_f16m1_tum
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmacc.mask.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmacc.mask.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
// //
vfloat16m1_t test_vfmacc_vf_f16m1_tum(vbool16_t mask, vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) { vfloat16m1_t test_vfmacc_vf_f16m1_tum(vbool16_t mask, vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfmacc_vf_f16m1_tum(mask, vd, rs1, vs2, vl); return __riscv_vfmacc_vf_f16m1_tum(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmacc_vv_f16m2_tum // CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmacc_vv_f16m2_tum
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmacc.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmacc.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
// //
vfloat16m2_t test_vfmacc_vv_f16m2_tum(vbool8_t mask, vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) { vfloat16m2_t test_vfmacc_vv_f16m2_tum(vbool8_t mask, vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfmacc_vv_f16m2_tum(mask, vd, vs1, vs2, vl); return __riscv_vfmacc_vv_f16m2_tum(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmacc_vf_f16m2_tum // CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmacc_vf_f16m2_tum
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmacc.mask.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmacc.mask.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
// //
vfloat16m2_t test_vfmacc_vf_f16m2_tum(vbool8_t mask, vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) { vfloat16m2_t test_vfmacc_vf_f16m2_tum(vbool8_t mask, vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfmacc_vf_f16m2_tum(mask, vd, rs1, vs2, vl); return __riscv_vfmacc_vf_f16m2_tum(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmacc_vv_f16m4_tum // CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmacc_vv_f16m4_tum
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmacc.mask.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmacc.mask.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
// //
vfloat16m4_t test_vfmacc_vv_f16m4_tum(vbool4_t mask, vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) { vfloat16m4_t test_vfmacc_vv_f16m4_tum(vbool4_t mask, vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfmacc_vv_f16m4_tum(mask, vd, vs1, vs2, vl); return __riscv_vfmacc_vv_f16m4_tum(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmacc_vf_f16m4_tum // CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmacc_vf_f16m4_tum
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmacc.mask.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmacc.mask.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
// //
vfloat16m4_t test_vfmacc_vf_f16m4_tum(vbool4_t mask, vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) { vfloat16m4_t test_vfmacc_vf_f16m4_tum(vbool4_t mask, vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfmacc_vf_f16m4_tum(mask, vd, rs1, vs2, vl); return __riscv_vfmacc_vf_f16m4_tum(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmacc_vv_f16m8_tum // CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmacc_vv_f16m8_tum
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmacc.mask.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmacc.mask.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
// //
vfloat16m8_t test_vfmacc_vv_f16m8_tum(vbool2_t mask, vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) { vfloat16m8_t test_vfmacc_vv_f16m8_tum(vbool2_t mask, vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfmacc_vv_f16m8_tum(mask, vd, vs1, vs2, vl); return __riscv_vfmacc_vv_f16m8_tum(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmacc_vf_f16m8_tum // CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmacc_vf_f16m8_tum
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmacc.mask.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmacc.mask.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
// //
vfloat16m8_t test_vfmacc_vf_f16m8_tum(vbool2_t mask, vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) { vfloat16m8_t test_vfmacc_vf_f16m8_tum(vbool2_t mask, vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfmacc_vf_f16m8_tum(mask, vd, rs1, vs2, vl); return __riscv_vfmacc_vf_f16m8_tum(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmacc_vv_f32mf2_tum // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmacc_vv_f32mf2_tum
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmacc.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmacc.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfmacc_vv_f32mf2_tum(vbool64_t mask, vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) { vfloat32mf2_t test_vfmacc_vv_f32mf2_tum(vbool64_t mask, vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfmacc_vv_f32mf2_tum(mask, vd, vs1, vs2, vl); return __riscv_vfmacc_vv_f32mf2_tum(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmacc_vf_f32mf2_tum // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmacc_vf_f32mf2_tum
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmacc.mask.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmacc.mask.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfmacc_vf_f32mf2_tum(vbool64_t mask, vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) { vfloat32mf2_t test_vfmacc_vf_f32mf2_tum(vbool64_t mask, vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfmacc_vf_f32mf2_tum(mask, vd, rs1, vs2, vl); return __riscv_vfmacc_vf_f32mf2_tum(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmacc_vv_f32m1_tum // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmacc_vv_f32m1_tum
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmacc.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmacc.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfmacc_vv_f32m1_tum(vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) { vfloat32m1_t test_vfmacc_vv_f32m1_tum(vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfmacc_vv_f32m1_tum(mask, vd, vs1, vs2, vl); return __riscv_vfmacc_vv_f32m1_tum(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmacc_vf_f32m1_tum // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmacc_vf_f32m1_tum
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmacc.mask.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmacc.mask.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfmacc_vf_f32m1_tum(vbool32_t mask, vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) { vfloat32m1_t test_vfmacc_vf_f32m1_tum(vbool32_t mask, vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfmacc_vf_f32m1_tum(mask, vd, rs1, vs2, vl); return __riscv_vfmacc_vf_f32m1_tum(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmacc_vv_f32m2_tum // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmacc_vv_f32m2_tum
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmacc.mask.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmacc.mask.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfmacc_vv_f32m2_tum(vbool16_t mask, vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) { vfloat32m2_t test_vfmacc_vv_f32m2_tum(vbool16_t mask, vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfmacc_vv_f32m2_tum(mask, vd, vs1, vs2, vl); return __riscv_vfmacc_vv_f32m2_tum(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmacc_vf_f32m2_tum // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmacc_vf_f32m2_tum
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmacc.mask.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmacc.mask.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfmacc_vf_f32m2_tum(vbool16_t mask, vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) { vfloat32m2_t test_vfmacc_vf_f32m2_tum(vbool16_t mask, vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfmacc_vf_f32m2_tum(mask, vd, rs1, vs2, vl); return __riscv_vfmacc_vf_f32m2_tum(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmacc_vv_f32m4_tum // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmacc_vv_f32m4_tum
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmacc.mask.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmacc.mask.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfmacc_vv_f32m4_tum(vbool8_t mask, vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) { vfloat32m4_t test_vfmacc_vv_f32m4_tum(vbool8_t mask, vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfmacc_vv_f32m4_tum(mask, vd, vs1, vs2, vl); return __riscv_vfmacc_vv_f32m4_tum(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmacc_vf_f32m4_tum // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmacc_vf_f32m4_tum
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmacc.mask.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmacc.mask.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfmacc_vf_f32m4_tum(vbool8_t mask, vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) { vfloat32m4_t test_vfmacc_vf_f32m4_tum(vbool8_t mask, vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfmacc_vf_f32m4_tum(mask, vd, rs1, vs2, vl); return __riscv_vfmacc_vf_f32m4_tum(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmacc_vv_f32m8_tum // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmacc_vv_f32m8_tum
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmacc.mask.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmacc.mask.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfmacc_vv_f32m8_tum(vbool4_t mask, vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) { vfloat32m8_t test_vfmacc_vv_f32m8_tum(vbool4_t mask, vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfmacc_vv_f32m8_tum(mask, vd, vs1, vs2, vl); return __riscv_vfmacc_vv_f32m8_tum(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmacc_vf_f32m8_tum // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmacc_vf_f32m8_tum
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmacc.mask.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmacc.mask.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfmacc_vf_f32m8_tum(vbool4_t mask, vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) { vfloat32m8_t test_vfmacc_vf_f32m8_tum(vbool4_t mask, vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfmacc_vf_f32m8_tum(mask, vd, rs1, vs2, vl); return __riscv_vfmacc_vf_f32m8_tum(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmacc_vv_f64m1_tum // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmacc_vv_f64m1_tum
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmacc.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmacc.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfmacc_vv_f64m1_tum(vbool64_t mask, vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) { vfloat64m1_t test_vfmacc_vv_f64m1_tum(vbool64_t mask, vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfmacc_vv_f64m1_tum(mask, vd, vs1, vs2, vl); return __riscv_vfmacc_vv_f64m1_tum(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmacc_vf_f64m1_tum // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmacc_vf_f64m1_tum
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmacc.mask.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmacc.mask.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfmacc_vf_f64m1_tum(vbool64_t mask, vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) { vfloat64m1_t test_vfmacc_vf_f64m1_tum(vbool64_t mask, vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfmacc_vf_f64m1_tum(mask, vd, rs1, vs2, vl); return __riscv_vfmacc_vf_f64m1_tum(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmacc_vv_f64m2_tum // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmacc_vv_f64m2_tum
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmacc.mask.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmacc.mask.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfmacc_vv_f64m2_tum(vbool32_t mask, vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) { vfloat64m2_t test_vfmacc_vv_f64m2_tum(vbool32_t mask, vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfmacc_vv_f64m2_tum(mask, vd, vs1, vs2, vl); return __riscv_vfmacc_vv_f64m2_tum(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmacc_vf_f64m2_tum // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmacc_vf_f64m2_tum
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmacc.mask.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmacc.mask.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfmacc_vf_f64m2_tum(vbool32_t mask, vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) { vfloat64m2_t test_vfmacc_vf_f64m2_tum(vbool32_t mask, vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfmacc_vf_f64m2_tum(mask, vd, rs1, vs2, vl); return __riscv_vfmacc_vf_f64m2_tum(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmacc_vv_f64m4_tum // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmacc_vv_f64m4_tum
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmacc.mask.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmacc.mask.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfmacc_vv_f64m4_tum(vbool16_t mask, vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) { vfloat64m4_t test_vfmacc_vv_f64m4_tum(vbool16_t mask, vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfmacc_vv_f64m4_tum(mask, vd, vs1, vs2, vl); return __riscv_vfmacc_vv_f64m4_tum(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmacc_vf_f64m4_tum // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmacc_vf_f64m4_tum
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmacc.mask.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmacc.mask.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfmacc_vf_f64m4_tum(vbool16_t mask, vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) { vfloat64m4_t test_vfmacc_vf_f64m4_tum(vbool16_t mask, vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfmacc_vf_f64m4_tum(mask, vd, rs1, vs2, vl); return __riscv_vfmacc_vf_f64m4_tum(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmacc_vv_f64m8_tum // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmacc_vv_f64m8_tum
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmacc.mask.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmacc.mask.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfmacc_vv_f64m8_tum(vbool8_t mask, vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) { vfloat64m8_t test_vfmacc_vv_f64m8_tum(vbool8_t mask, vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfmacc_vv_f64m8_tum(mask, vd, vs1, vs2, vl); return __riscv_vfmacc_vv_f64m8_tum(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmacc_vf_f64m8_tum // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmacc_vf_f64m8_tum
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmacc.mask.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmacc.mask.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfmacc_vf_f64m8_tum(vbool8_t mask, vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) { vfloat64m8_t test_vfmacc_vf_f64m8_tum(vbool8_t mask, vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfmacc_vf_f64m8_tum(mask, vd, rs1, vs2, vl); return __riscv_vfmacc_vf_f64m8_tum(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmacc_vv_f16mf4_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmacc_vv_f16mf4_tumu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmacc.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmacc.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
// //
vfloat16mf4_t test_vfmacc_vv_f16mf4_tumu(vbool64_t mask, vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) { vfloat16mf4_t test_vfmacc_vv_f16mf4_tumu(vbool64_t mask, vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfmacc_vv_f16mf4_tumu(mask, vd, vs1, vs2, vl); return __riscv_vfmacc_vv_f16mf4_tumu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmacc_vf_f16mf4_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmacc_vf_f16mf4_tumu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmacc.mask.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmacc.mask.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
// //
vfloat16mf4_t test_vfmacc_vf_f16mf4_tumu(vbool64_t mask, vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) { vfloat16mf4_t test_vfmacc_vf_f16mf4_tumu(vbool64_t mask, vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfmacc_vf_f16mf4_tumu(mask, vd, rs1, vs2, vl); return __riscv_vfmacc_vf_f16mf4_tumu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmacc_vv_f16mf2_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmacc_vv_f16mf2_tumu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmacc.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmacc.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
// //
vfloat16mf2_t test_vfmacc_vv_f16mf2_tumu(vbool32_t mask, vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) { vfloat16mf2_t test_vfmacc_vv_f16mf2_tumu(vbool32_t mask, vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfmacc_vv_f16mf2_tumu(mask, vd, vs1, vs2, vl); return __riscv_vfmacc_vv_f16mf2_tumu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmacc_vf_f16mf2_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmacc_vf_f16mf2_tumu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmacc.mask.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmacc.mask.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
// //
vfloat16mf2_t test_vfmacc_vf_f16mf2_tumu(vbool32_t mask, vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) { vfloat16mf2_t test_vfmacc_vf_f16mf2_tumu(vbool32_t mask, vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfmacc_vf_f16mf2_tumu(mask, vd, rs1, vs2, vl); return __riscv_vfmacc_vf_f16mf2_tumu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmacc_vv_f16m1_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmacc_vv_f16m1_tumu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmacc.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmacc.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
// //
vfloat16m1_t test_vfmacc_vv_f16m1_tumu(vbool16_t mask, vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) { vfloat16m1_t test_vfmacc_vv_f16m1_tumu(vbool16_t mask, vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfmacc_vv_f16m1_tumu(mask, vd, vs1, vs2, vl); return __riscv_vfmacc_vv_f16m1_tumu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmacc_vf_f16m1_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmacc_vf_f16m1_tumu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmacc.mask.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmacc.mask.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
// //
vfloat16m1_t test_vfmacc_vf_f16m1_tumu(vbool16_t mask, vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) { vfloat16m1_t test_vfmacc_vf_f16m1_tumu(vbool16_t mask, vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfmacc_vf_f16m1_tumu(mask, vd, rs1, vs2, vl); return __riscv_vfmacc_vf_f16m1_tumu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmacc_vv_f16m2_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmacc_vv_f16m2_tumu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmacc.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmacc.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
// //
vfloat16m2_t test_vfmacc_vv_f16m2_tumu(vbool8_t mask, vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) { vfloat16m2_t test_vfmacc_vv_f16m2_tumu(vbool8_t mask, vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfmacc_vv_f16m2_tumu(mask, vd, vs1, vs2, vl); return __riscv_vfmacc_vv_f16m2_tumu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmacc_vf_f16m2_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmacc_vf_f16m2_tumu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmacc.mask.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmacc.mask.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
// //
vfloat16m2_t test_vfmacc_vf_f16m2_tumu(vbool8_t mask, vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) { vfloat16m2_t test_vfmacc_vf_f16m2_tumu(vbool8_t mask, vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfmacc_vf_f16m2_tumu(mask, vd, rs1, vs2, vl); return __riscv_vfmacc_vf_f16m2_tumu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmacc_vv_f16m4_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmacc_vv_f16m4_tumu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmacc.mask.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmacc.mask.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
// //
vfloat16m4_t test_vfmacc_vv_f16m4_tumu(vbool4_t mask, vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) { vfloat16m4_t test_vfmacc_vv_f16m4_tumu(vbool4_t mask, vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfmacc_vv_f16m4_tumu(mask, vd, vs1, vs2, vl); return __riscv_vfmacc_vv_f16m4_tumu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmacc_vf_f16m4_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmacc_vf_f16m4_tumu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmacc.mask.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmacc.mask.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
// //
vfloat16m4_t test_vfmacc_vf_f16m4_tumu(vbool4_t mask, vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) { vfloat16m4_t test_vfmacc_vf_f16m4_tumu(vbool4_t mask, vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfmacc_vf_f16m4_tumu(mask, vd, rs1, vs2, vl); return __riscv_vfmacc_vf_f16m4_tumu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmacc_vv_f16m8_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmacc_vv_f16m8_tumu
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmacc.mask.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmacc.mask.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
// //
vfloat16m8_t test_vfmacc_vv_f16m8_tumu(vbool2_t mask, vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) { vfloat16m8_t test_vfmacc_vv_f16m8_tumu(vbool2_t mask, vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfmacc_vv_f16m8_tumu(mask, vd, vs1, vs2, vl); return __riscv_vfmacc_vv_f16m8_tumu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmacc_vf_f16m8_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmacc_vf_f16m8_tumu
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmacc.mask.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmacc.mask.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
// //
vfloat16m8_t test_vfmacc_vf_f16m8_tumu(vbool2_t mask, vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) { vfloat16m8_t test_vfmacc_vf_f16m8_tumu(vbool2_t mask, vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfmacc_vf_f16m8_tumu(mask, vd, rs1, vs2, vl); return __riscv_vfmacc_vf_f16m8_tumu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmacc_vv_f32mf2_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmacc_vv_f32mf2_tumu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmacc.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmacc.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfmacc_vv_f32mf2_tumu(vbool64_t mask, vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) { vfloat32mf2_t test_vfmacc_vv_f32mf2_tumu(vbool64_t mask, vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfmacc_vv_f32mf2_tumu(mask, vd, vs1, vs2, vl); return __riscv_vfmacc_vv_f32mf2_tumu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmacc_vf_f32mf2_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmacc_vf_f32mf2_tumu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmacc.mask.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmacc.mask.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfmacc_vf_f32mf2_tumu(vbool64_t mask, vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) { vfloat32mf2_t test_vfmacc_vf_f32mf2_tumu(vbool64_t mask, vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfmacc_vf_f32mf2_tumu(mask, vd, rs1, vs2, vl); return __riscv_vfmacc_vf_f32mf2_tumu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmacc_vv_f32m1_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmacc_vv_f32m1_tumu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmacc.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmacc.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfmacc_vv_f32m1_tumu(vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) { vfloat32m1_t test_vfmacc_vv_f32m1_tumu(vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfmacc_vv_f32m1_tumu(mask, vd, vs1, vs2, vl); return __riscv_vfmacc_vv_f32m1_tumu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmacc_vf_f32m1_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmacc_vf_f32m1_tumu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmacc.mask.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmacc.mask.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfmacc_vf_f32m1_tumu(vbool32_t mask, vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) { vfloat32m1_t test_vfmacc_vf_f32m1_tumu(vbool32_t mask, vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfmacc_vf_f32m1_tumu(mask, vd, rs1, vs2, vl); return __riscv_vfmacc_vf_f32m1_tumu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmacc_vv_f32m2_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmacc_vv_f32m2_tumu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmacc.mask.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmacc.mask.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfmacc_vv_f32m2_tumu(vbool16_t mask, vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) { vfloat32m2_t test_vfmacc_vv_f32m2_tumu(vbool16_t mask, vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfmacc_vv_f32m2_tumu(mask, vd, vs1, vs2, vl); return __riscv_vfmacc_vv_f32m2_tumu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmacc_vf_f32m2_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmacc_vf_f32m2_tumu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmacc.mask.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmacc.mask.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfmacc_vf_f32m2_tumu(vbool16_t mask, vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) { vfloat32m2_t test_vfmacc_vf_f32m2_tumu(vbool16_t mask, vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfmacc_vf_f32m2_tumu(mask, vd, rs1, vs2, vl); return __riscv_vfmacc_vf_f32m2_tumu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmacc_vv_f32m4_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmacc_vv_f32m4_tumu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmacc.mask.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmacc.mask.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfmacc_vv_f32m4_tumu(vbool8_t mask, vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) { vfloat32m4_t test_vfmacc_vv_f32m4_tumu(vbool8_t mask, vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfmacc_vv_f32m4_tumu(mask, vd, vs1, vs2, vl); return __riscv_vfmacc_vv_f32m4_tumu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmacc_vf_f32m4_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmacc_vf_f32m4_tumu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmacc.mask.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmacc.mask.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfmacc_vf_f32m4_tumu(vbool8_t mask, vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) { vfloat32m4_t test_vfmacc_vf_f32m4_tumu(vbool8_t mask, vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfmacc_vf_f32m4_tumu(mask, vd, rs1, vs2, vl); return __riscv_vfmacc_vf_f32m4_tumu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmacc_vv_f32m8_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmacc_vv_f32m8_tumu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmacc.mask.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmacc.mask.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfmacc_vv_f32m8_tumu(vbool4_t mask, vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) { vfloat32m8_t test_vfmacc_vv_f32m8_tumu(vbool4_t mask, vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfmacc_vv_f32m8_tumu(mask, vd, vs1, vs2, vl); return __riscv_vfmacc_vv_f32m8_tumu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmacc_vf_f32m8_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmacc_vf_f32m8_tumu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmacc.mask.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmacc.mask.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfmacc_vf_f32m8_tumu(vbool4_t mask, vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) { vfloat32m8_t test_vfmacc_vf_f32m8_tumu(vbool4_t mask, vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfmacc_vf_f32m8_tumu(mask, vd, rs1, vs2, vl); return __riscv_vfmacc_vf_f32m8_tumu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmacc_vv_f64m1_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmacc_vv_f64m1_tumu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmacc.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmacc.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfmacc_vv_f64m1_tumu(vbool64_t mask, vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) { vfloat64m1_t test_vfmacc_vv_f64m1_tumu(vbool64_t mask, vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfmacc_vv_f64m1_tumu(mask, vd, vs1, vs2, vl); return __riscv_vfmacc_vv_f64m1_tumu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmacc_vf_f64m1_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmacc_vf_f64m1_tumu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmacc.mask.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmacc.mask.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfmacc_vf_f64m1_tumu(vbool64_t mask, vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) { vfloat64m1_t test_vfmacc_vf_f64m1_tumu(vbool64_t mask, vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfmacc_vf_f64m1_tumu(mask, vd, rs1, vs2, vl); return __riscv_vfmacc_vf_f64m1_tumu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmacc_vv_f64m2_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmacc_vv_f64m2_tumu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmacc.mask.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmacc.mask.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfmacc_vv_f64m2_tumu(vbool32_t mask, vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) { vfloat64m2_t test_vfmacc_vv_f64m2_tumu(vbool32_t mask, vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfmacc_vv_f64m2_tumu(mask, vd, vs1, vs2, vl); return __riscv_vfmacc_vv_f64m2_tumu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmacc_vf_f64m2_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmacc_vf_f64m2_tumu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmacc.mask.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmacc.mask.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfmacc_vf_f64m2_tumu(vbool32_t mask, vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) { vfloat64m2_t test_vfmacc_vf_f64m2_tumu(vbool32_t mask, vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfmacc_vf_f64m2_tumu(mask, vd, rs1, vs2, vl); return __riscv_vfmacc_vf_f64m2_tumu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmacc_vv_f64m4_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmacc_vv_f64m4_tumu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmacc.mask.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmacc.mask.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfmacc_vv_f64m4_tumu(vbool16_t mask, vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) { vfloat64m4_t test_vfmacc_vv_f64m4_tumu(vbool16_t mask, vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfmacc_vv_f64m4_tumu(mask, vd, vs1, vs2, vl); return __riscv_vfmacc_vv_f64m4_tumu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmacc_vf_f64m4_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmacc_vf_f64m4_tumu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmacc.mask.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmacc.mask.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfmacc_vf_f64m4_tumu(vbool16_t mask, vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) { vfloat64m4_t test_vfmacc_vf_f64m4_tumu(vbool16_t mask, vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfmacc_vf_f64m4_tumu(mask, vd, rs1, vs2, vl); return __riscv_vfmacc_vf_f64m4_tumu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmacc_vv_f64m8_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmacc_vv_f64m8_tumu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmacc.mask.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmacc.mask.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfmacc_vv_f64m8_tumu(vbool8_t mask, vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) { vfloat64m8_t test_vfmacc_vv_f64m8_tumu(vbool8_t mask, vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfmacc_vv_f64m8_tumu(mask, vd, vs1, vs2, vl); return __riscv_vfmacc_vv_f64m8_tumu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmacc_vf_f64m8_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmacc_vf_f64m8_tumu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmacc.mask.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmacc.mask.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfmacc_vf_f64m8_tumu(vbool8_t mask, vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) { vfloat64m8_t test_vfmacc_vf_f64m8_tumu(vbool8_t mask, vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfmacc_vf_f64m8_tumu(mask, vd, rs1, vs2, vl); return __riscv_vfmacc_vf_f64m8_tumu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmacc_vv_f16mf4_mu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmacc_vv_f16mf4_mu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmacc.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmacc.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
// //
vfloat16mf4_t test_vfmacc_vv_f16mf4_mu(vbool64_t mask, vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) { vfloat16mf4_t test_vfmacc_vv_f16mf4_mu(vbool64_t mask, vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfmacc_vv_f16mf4_mu(mask, vd, vs1, vs2, vl); return __riscv_vfmacc_vv_f16mf4_mu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmacc_vf_f16mf4_mu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmacc_vf_f16mf4_mu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmacc.mask.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmacc.mask.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
// //
vfloat16mf4_t test_vfmacc_vf_f16mf4_mu(vbool64_t mask, vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) { vfloat16mf4_t test_vfmacc_vf_f16mf4_mu(vbool64_t mask, vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfmacc_vf_f16mf4_mu(mask, vd, rs1, vs2, vl); return __riscv_vfmacc_vf_f16mf4_mu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmacc_vv_f16mf2_mu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmacc_vv_f16mf2_mu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmacc.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmacc.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
// //
vfloat16mf2_t test_vfmacc_vv_f16mf2_mu(vbool32_t mask, vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) { vfloat16mf2_t test_vfmacc_vv_f16mf2_mu(vbool32_t mask, vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfmacc_vv_f16mf2_mu(mask, vd, vs1, vs2, vl); return __riscv_vfmacc_vv_f16mf2_mu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmacc_vf_f16mf2_mu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmacc_vf_f16mf2_mu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmacc.mask.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmacc.mask.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
// //
vfloat16mf2_t test_vfmacc_vf_f16mf2_mu(vbool32_t mask, vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) { vfloat16mf2_t test_vfmacc_vf_f16mf2_mu(vbool32_t mask, vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfmacc_vf_f16mf2_mu(mask, vd, rs1, vs2, vl); return __riscv_vfmacc_vf_f16mf2_mu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmacc_vv_f16m1_mu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmacc_vv_f16m1_mu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmacc.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmacc.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
// //
vfloat16m1_t test_vfmacc_vv_f16m1_mu(vbool16_t mask, vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) { vfloat16m1_t test_vfmacc_vv_f16m1_mu(vbool16_t mask, vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfmacc_vv_f16m1_mu(mask, vd, vs1, vs2, vl); return __riscv_vfmacc_vv_f16m1_mu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmacc_vf_f16m1_mu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmacc_vf_f16m1_mu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmacc.mask.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmacc.mask.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
// //
vfloat16m1_t test_vfmacc_vf_f16m1_mu(vbool16_t mask, vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) { vfloat16m1_t test_vfmacc_vf_f16m1_mu(vbool16_t mask, vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfmacc_vf_f16m1_mu(mask, vd, rs1, vs2, vl); return __riscv_vfmacc_vf_f16m1_mu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmacc_vv_f16m2_mu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmacc_vv_f16m2_mu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmacc.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmacc.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
// //
vfloat16m2_t test_vfmacc_vv_f16m2_mu(vbool8_t mask, vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) { vfloat16m2_t test_vfmacc_vv_f16m2_mu(vbool8_t mask, vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfmacc_vv_f16m2_mu(mask, vd, vs1, vs2, vl); return __riscv_vfmacc_vv_f16m2_mu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmacc_vf_f16m2_mu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmacc_vf_f16m2_mu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmacc.mask.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmacc.mask.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
// //
vfloat16m2_t test_vfmacc_vf_f16m2_mu(vbool8_t mask, vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) { vfloat16m2_t test_vfmacc_vf_f16m2_mu(vbool8_t mask, vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfmacc_vf_f16m2_mu(mask, vd, rs1, vs2, vl); return __riscv_vfmacc_vf_f16m2_mu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmacc_vv_f16m4_mu // CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmacc_vv_f16m4_mu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmacc.mask.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmacc.mask.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
// //
vfloat16m4_t test_vfmacc_vv_f16m4_mu(vbool4_t mask, vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) { vfloat16m4_t test_vfmacc_vv_f16m4_mu(vbool4_t mask, vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfmacc_vv_f16m4_mu(mask, vd, vs1, vs2, vl); return __riscv_vfmacc_vv_f16m4_mu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmacc_vf_f16m4_mu // CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmacc_vf_f16m4_mu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmacc.mask.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmacc.mask.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
// //
vfloat16m4_t test_vfmacc_vf_f16m4_mu(vbool4_t mask, vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) { vfloat16m4_t test_vfmacc_vf_f16m4_mu(vbool4_t mask, vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfmacc_vf_f16m4_mu(mask, vd, rs1, vs2, vl); return __riscv_vfmacc_vf_f16m4_mu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmacc_vv_f16m8_mu // CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmacc_vv_f16m8_mu
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmacc.mask.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmacc.mask.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
// //
vfloat16m8_t test_vfmacc_vv_f16m8_mu(vbool2_t mask, vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) { vfloat16m8_t test_vfmacc_vv_f16m8_mu(vbool2_t mask, vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfmacc_vv_f16m8_mu(mask, vd, vs1, vs2, vl); return __riscv_vfmacc_vv_f16m8_mu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmacc_vf_f16m8_mu // CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmacc_vf_f16m8_mu
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmacc.mask.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmacc.mask.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
// //
vfloat16m8_t test_vfmacc_vf_f16m8_mu(vbool2_t mask, vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) { vfloat16m8_t test_vfmacc_vf_f16m8_mu(vbool2_t mask, vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfmacc_vf_f16m8_mu(mask, vd, rs1, vs2, vl); return __riscv_vfmacc_vf_f16m8_mu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmacc_vv_f32mf2_mu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmacc_vv_f32mf2_mu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmacc.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmacc.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfmacc_vv_f32mf2_mu(vbool64_t mask, vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) { vfloat32mf2_t test_vfmacc_vv_f32mf2_mu(vbool64_t mask, vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfmacc_vv_f32mf2_mu(mask, vd, vs1, vs2, vl); return __riscv_vfmacc_vv_f32mf2_mu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmacc_vf_f32mf2_mu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmacc_vf_f32mf2_mu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmacc.mask.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmacc.mask.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfmacc_vf_f32mf2_mu(vbool64_t mask, vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) { vfloat32mf2_t test_vfmacc_vf_f32mf2_mu(vbool64_t mask, vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfmacc_vf_f32mf2_mu(mask, vd, rs1, vs2, vl); return __riscv_vfmacc_vf_f32mf2_mu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmacc_vv_f32m1_mu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmacc_vv_f32m1_mu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmacc.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmacc.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfmacc_vv_f32m1_mu(vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) { vfloat32m1_t test_vfmacc_vv_f32m1_mu(vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfmacc_vv_f32m1_mu(mask, vd, vs1, vs2, vl); return __riscv_vfmacc_vv_f32m1_mu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmacc_vf_f32m1_mu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmacc_vf_f32m1_mu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmacc.mask.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmacc.mask.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfmacc_vf_f32m1_mu(vbool32_t mask, vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) { vfloat32m1_t test_vfmacc_vf_f32m1_mu(vbool32_t mask, vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfmacc_vf_f32m1_mu(mask, vd, rs1, vs2, vl); return __riscv_vfmacc_vf_f32m1_mu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmacc_vv_f32m2_mu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmacc_vv_f32m2_mu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmacc.mask.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmacc.mask.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfmacc_vv_f32m2_mu(vbool16_t mask, vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) { vfloat32m2_t test_vfmacc_vv_f32m2_mu(vbool16_t mask, vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfmacc_vv_f32m2_mu(mask, vd, vs1, vs2, vl); return __riscv_vfmacc_vv_f32m2_mu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmacc_vf_f32m2_mu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmacc_vf_f32m2_mu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmacc.mask.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmacc.mask.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfmacc_vf_f32m2_mu(vbool16_t mask, vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) { vfloat32m2_t test_vfmacc_vf_f32m2_mu(vbool16_t mask, vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfmacc_vf_f32m2_mu(mask, vd, rs1, vs2, vl); return __riscv_vfmacc_vf_f32m2_mu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmacc_vv_f32m4_mu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmacc_vv_f32m4_mu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmacc.mask.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmacc.mask.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfmacc_vv_f32m4_mu(vbool8_t mask, vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) { vfloat32m4_t test_vfmacc_vv_f32m4_mu(vbool8_t mask, vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfmacc_vv_f32m4_mu(mask, vd, vs1, vs2, vl); return __riscv_vfmacc_vv_f32m4_mu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmacc_vf_f32m4_mu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmacc_vf_f32m4_mu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmacc.mask.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmacc.mask.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfmacc_vf_f32m4_mu(vbool8_t mask, vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) { vfloat32m4_t test_vfmacc_vf_f32m4_mu(vbool8_t mask, vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfmacc_vf_f32m4_mu(mask, vd, rs1, vs2, vl); return __riscv_vfmacc_vf_f32m4_mu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmacc_vv_f32m8_mu // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmacc_vv_f32m8_mu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmacc.mask.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmacc.mask.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfmacc_vv_f32m8_mu(vbool4_t mask, vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) { vfloat32m8_t test_vfmacc_vv_f32m8_mu(vbool4_t mask, vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfmacc_vv_f32m8_mu(mask, vd, vs1, vs2, vl); return __riscv_vfmacc_vv_f32m8_mu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmacc_vf_f32m8_mu // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmacc_vf_f32m8_mu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmacc.mask.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmacc.mask.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfmacc_vf_f32m8_mu(vbool4_t mask, vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) { vfloat32m8_t test_vfmacc_vf_f32m8_mu(vbool4_t mask, vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfmacc_vf_f32m8_mu(mask, vd, rs1, vs2, vl); return __riscv_vfmacc_vf_f32m8_mu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmacc_vv_f64m1_mu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmacc_vv_f64m1_mu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmacc.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmacc.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfmacc_vv_f64m1_mu(vbool64_t mask, vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) { vfloat64m1_t test_vfmacc_vv_f64m1_mu(vbool64_t mask, vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfmacc_vv_f64m1_mu(mask, vd, vs1, vs2, vl); return __riscv_vfmacc_vv_f64m1_mu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmacc_vf_f64m1_mu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmacc_vf_f64m1_mu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmacc.mask.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmacc.mask.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfmacc_vf_f64m1_mu(vbool64_t mask, vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) { vfloat64m1_t test_vfmacc_vf_f64m1_mu(vbool64_t mask, vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfmacc_vf_f64m1_mu(mask, vd, rs1, vs2, vl); return __riscv_vfmacc_vf_f64m1_mu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmacc_vv_f64m2_mu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmacc_vv_f64m2_mu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmacc.mask.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmacc.mask.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfmacc_vv_f64m2_mu(vbool32_t mask, vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) { vfloat64m2_t test_vfmacc_vv_f64m2_mu(vbool32_t mask, vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfmacc_vv_f64m2_mu(mask, vd, vs1, vs2, vl); return __riscv_vfmacc_vv_f64m2_mu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmacc_vf_f64m2_mu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmacc_vf_f64m2_mu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmacc.mask.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmacc.mask.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfmacc_vf_f64m2_mu(vbool32_t mask, vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) { vfloat64m2_t test_vfmacc_vf_f64m2_mu(vbool32_t mask, vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfmacc_vf_f64m2_mu(mask, vd, rs1, vs2, vl); return __riscv_vfmacc_vf_f64m2_mu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmacc_vv_f64m4_mu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmacc_vv_f64m4_mu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmacc.mask.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmacc.mask.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfmacc_vv_f64m4_mu(vbool16_t mask, vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) { vfloat64m4_t test_vfmacc_vv_f64m4_mu(vbool16_t mask, vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfmacc_vv_f64m4_mu(mask, vd, vs1, vs2, vl); return __riscv_vfmacc_vv_f64m4_mu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmacc_vf_f64m4_mu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmacc_vf_f64m4_mu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmacc.mask.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmacc.mask.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfmacc_vf_f64m4_mu(vbool16_t mask, vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) { vfloat64m4_t test_vfmacc_vf_f64m4_mu(vbool16_t mask, vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfmacc_vf_f64m4_mu(mask, vd, rs1, vs2, vl); return __riscv_vfmacc_vf_f64m4_mu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmacc_vv_f64m8_mu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmacc_vv_f64m8_mu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmacc.mask.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmacc.mask.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfmacc_vv_f64m8_mu(vbool8_t mask, vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) { vfloat64m8_t test_vfmacc_vv_f64m8_mu(vbool8_t mask, vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfmacc_vv_f64m8_mu(mask, vd, vs1, vs2, vl); return __riscv_vfmacc_vv_f64m8_mu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmacc_vf_f64m8_mu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmacc_vf_f64m8_mu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmacc.mask.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmacc.mask.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfmacc_vf_f64m8_mu(vbool8_t mask, vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) { vfloat64m8_t test_vfmacc_vf_f64m8_mu(vbool8_t mask, vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfmacc_vf_f64m8_mu(mask, vd, rs1, vs2, vl); return __riscv_vfmacc_vf_f64m8_mu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmacc_vv_f16mf4_rm_tu
// CHECK-RV64-SAME: (<vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmacc.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
//
vfloat16mf4_t test_vfmacc_vv_f16mf4_rm_tu(vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfmacc_vv_f16mf4_rm_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmacc_vf_f16mf4_rm_tu
// CHECK-RV64-SAME: (<vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmacc.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
//
vfloat16mf4_t test_vfmacc_vf_f16mf4_rm_tu(vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfmacc_vf_f16mf4_rm_tu(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmacc_vv_f16mf2_rm_tu
// CHECK-RV64-SAME: (<vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmacc.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
//
vfloat16mf2_t test_vfmacc_vv_f16mf2_rm_tu(vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfmacc_vv_f16mf2_rm_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmacc_vf_f16mf2_rm_tu
// CHECK-RV64-SAME: (<vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmacc.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
//
vfloat16mf2_t test_vfmacc_vf_f16mf2_rm_tu(vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfmacc_vf_f16mf2_rm_tu(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmacc_vv_f16m1_rm_tu
// CHECK-RV64-SAME: (<vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmacc.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfmacc_vv_f16m1_rm_tu(vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfmacc_vv_f16m1_rm_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmacc_vf_f16m1_rm_tu
// CHECK-RV64-SAME: (<vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmacc.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfmacc_vf_f16m1_rm_tu(vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfmacc_vf_f16m1_rm_tu(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmacc_vv_f16m2_rm_tu
// CHECK-RV64-SAME: (<vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmacc.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
//
vfloat16m2_t test_vfmacc_vv_f16m2_rm_tu(vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfmacc_vv_f16m2_rm_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmacc_vf_f16m2_rm_tu
// CHECK-RV64-SAME: (<vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmacc.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
//
vfloat16m2_t test_vfmacc_vf_f16m2_rm_tu(vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfmacc_vf_f16m2_rm_tu(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmacc_vv_f16m4_rm_tu
// CHECK-RV64-SAME: (<vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmacc.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
//
vfloat16m4_t test_vfmacc_vv_f16m4_rm_tu(vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfmacc_vv_f16m4_rm_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmacc_vf_f16m4_rm_tu
// CHECK-RV64-SAME: (<vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmacc.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
//
vfloat16m4_t test_vfmacc_vf_f16m4_rm_tu(vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfmacc_vf_f16m4_rm_tu(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmacc_vv_f16m8_rm_tu
// CHECK-RV64-SAME: (<vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmacc.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
//
vfloat16m8_t test_vfmacc_vv_f16m8_rm_tu(vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfmacc_vv_f16m8_rm_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmacc_vf_f16m8_rm_tu
// CHECK-RV64-SAME: (<vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmacc.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
//
vfloat16m8_t test_vfmacc_vf_f16m8_rm_tu(vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfmacc_vf_f16m8_rm_tu(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmacc_vv_f32mf2_rm_tu
// CHECK-RV64-SAME: (<vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmacc.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
//
vfloat32mf2_t test_vfmacc_vv_f32mf2_rm_tu(vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfmacc_vv_f32mf2_rm_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmacc_vf_f32mf2_rm_tu
// CHECK-RV64-SAME: (<vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmacc.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
//
vfloat32mf2_t test_vfmacc_vf_f32mf2_rm_tu(vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfmacc_vf_f32mf2_rm_tu(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmacc_vv_f32m1_rm_tu
// CHECK-RV64-SAME: (<vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmacc.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfmacc_vv_f32m1_rm_tu(vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfmacc_vv_f32m1_rm_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmacc_vf_f32m1_rm_tu
// CHECK-RV64-SAME: (<vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmacc.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfmacc_vf_f32m1_rm_tu(vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfmacc_vf_f32m1_rm_tu(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmacc_vv_f32m2_rm_tu
// CHECK-RV64-SAME: (<vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmacc.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
//
vfloat32m2_t test_vfmacc_vv_f32m2_rm_tu(vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfmacc_vv_f32m2_rm_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmacc_vf_f32m2_rm_tu
// CHECK-RV64-SAME: (<vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmacc.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
//
vfloat32m2_t test_vfmacc_vf_f32m2_rm_tu(vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfmacc_vf_f32m2_rm_tu(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmacc_vv_f32m4_rm_tu
// CHECK-RV64-SAME: (<vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmacc.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
//
vfloat32m4_t test_vfmacc_vv_f32m4_rm_tu(vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfmacc_vv_f32m4_rm_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmacc_vf_f32m4_rm_tu
// CHECK-RV64-SAME: (<vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmacc.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
//
vfloat32m4_t test_vfmacc_vf_f32m4_rm_tu(vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfmacc_vf_f32m4_rm_tu(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmacc_vv_f32m8_rm_tu
// CHECK-RV64-SAME: (<vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmacc.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
//
vfloat32m8_t test_vfmacc_vv_f32m8_rm_tu(vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfmacc_vv_f32m8_rm_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmacc_vf_f32m8_rm_tu
// CHECK-RV64-SAME: (<vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmacc.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
//
vfloat32m8_t test_vfmacc_vf_f32m8_rm_tu(vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfmacc_vf_f32m8_rm_tu(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmacc_vv_f64m1_rm_tu
// CHECK-RV64-SAME: (<vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmacc.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfmacc_vv_f64m1_rm_tu(vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfmacc_vv_f64m1_rm_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmacc_vf_f64m1_rm_tu
// CHECK-RV64-SAME: (<vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmacc.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfmacc_vf_f64m1_rm_tu(vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfmacc_vf_f64m1_rm_tu(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmacc_vv_f64m2_rm_tu
// CHECK-RV64-SAME: (<vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmacc.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
//
vfloat64m2_t test_vfmacc_vv_f64m2_rm_tu(vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfmacc_vv_f64m2_rm_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmacc_vf_f64m2_rm_tu
// CHECK-RV64-SAME: (<vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmacc.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
//
vfloat64m2_t test_vfmacc_vf_f64m2_rm_tu(vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfmacc_vf_f64m2_rm_tu(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmacc_vv_f64m4_rm_tu
// CHECK-RV64-SAME: (<vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmacc.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
//
vfloat64m4_t test_vfmacc_vv_f64m4_rm_tu(vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfmacc_vv_f64m4_rm_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmacc_vf_f64m4_rm_tu
// CHECK-RV64-SAME: (<vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmacc.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
//
vfloat64m4_t test_vfmacc_vf_f64m4_rm_tu(vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfmacc_vf_f64m4_rm_tu(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmacc_vv_f64m8_rm_tu
// CHECK-RV64-SAME: (<vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmacc.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
//
vfloat64m8_t test_vfmacc_vv_f64m8_rm_tu(vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfmacc_vv_f64m8_rm_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmacc_vf_f64m8_rm_tu
// CHECK-RV64-SAME: (<vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmacc.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
//
vfloat64m8_t test_vfmacc_vf_f64m8_rm_tu(vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfmacc_vf_f64m8_rm_tu(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmacc_vv_f16mf4_rm_tum
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmacc.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
//
vfloat16mf4_t test_vfmacc_vv_f16mf4_rm_tum(vbool64_t mask, vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfmacc_vv_f16mf4_rm_tum(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmacc_vf_f16mf4_rm_tum
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmacc.mask.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
//
vfloat16mf4_t test_vfmacc_vf_f16mf4_rm_tum(vbool64_t mask, vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfmacc_vf_f16mf4_rm_tum(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmacc_vv_f16mf2_rm_tum
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmacc.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
//
vfloat16mf2_t test_vfmacc_vv_f16mf2_rm_tum(vbool32_t mask, vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfmacc_vv_f16mf2_rm_tum(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmacc_vf_f16mf2_rm_tum
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmacc.mask.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
//
vfloat16mf2_t test_vfmacc_vf_f16mf2_rm_tum(vbool32_t mask, vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfmacc_vf_f16mf2_rm_tum(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmacc_vv_f16m1_rm_tum
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmacc.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfmacc_vv_f16m1_rm_tum(vbool16_t mask, vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfmacc_vv_f16m1_rm_tum(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmacc_vf_f16m1_rm_tum
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmacc.mask.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfmacc_vf_f16m1_rm_tum(vbool16_t mask, vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfmacc_vf_f16m1_rm_tum(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmacc_vv_f16m2_rm_tum
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmacc.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
//
vfloat16m2_t test_vfmacc_vv_f16m2_rm_tum(vbool8_t mask, vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfmacc_vv_f16m2_rm_tum(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmacc_vf_f16m2_rm_tum
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmacc.mask.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
//
vfloat16m2_t test_vfmacc_vf_f16m2_rm_tum(vbool8_t mask, vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfmacc_vf_f16m2_rm_tum(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmacc_vv_f16m4_rm_tum
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmacc.mask.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
//
vfloat16m4_t test_vfmacc_vv_f16m4_rm_tum(vbool4_t mask, vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfmacc_vv_f16m4_rm_tum(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmacc_vf_f16m4_rm_tum
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmacc.mask.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
//
vfloat16m4_t test_vfmacc_vf_f16m4_rm_tum(vbool4_t mask, vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfmacc_vf_f16m4_rm_tum(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmacc_vv_f16m8_rm_tum
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmacc.mask.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
//
vfloat16m8_t test_vfmacc_vv_f16m8_rm_tum(vbool2_t mask, vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfmacc_vv_f16m8_rm_tum(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmacc_vf_f16m8_rm_tum
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmacc.mask.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
//
vfloat16m8_t test_vfmacc_vf_f16m8_rm_tum(vbool2_t mask, vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfmacc_vf_f16m8_rm_tum(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmacc_vv_f32mf2_rm_tum
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmacc.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
//
vfloat32mf2_t test_vfmacc_vv_f32mf2_rm_tum(vbool64_t mask, vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfmacc_vv_f32mf2_rm_tum(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmacc_vf_f32mf2_rm_tum
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmacc.mask.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
//
vfloat32mf2_t test_vfmacc_vf_f32mf2_rm_tum(vbool64_t mask, vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfmacc_vf_f32mf2_rm_tum(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmacc_vv_f32m1_rm_tum
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmacc.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfmacc_vv_f32m1_rm_tum(vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfmacc_vv_f32m1_rm_tum(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmacc_vf_f32m1_rm_tum
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmacc.mask.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfmacc_vf_f32m1_rm_tum(vbool32_t mask, vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfmacc_vf_f32m1_rm_tum(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmacc_vv_f32m2_rm_tum
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmacc.mask.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
//
vfloat32m2_t test_vfmacc_vv_f32m2_rm_tum(vbool16_t mask, vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfmacc_vv_f32m2_rm_tum(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmacc_vf_f32m2_rm_tum
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmacc.mask.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
//
vfloat32m2_t test_vfmacc_vf_f32m2_rm_tum(vbool16_t mask, vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfmacc_vf_f32m2_rm_tum(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmacc_vv_f32m4_rm_tum
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmacc.mask.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
//
vfloat32m4_t test_vfmacc_vv_f32m4_rm_tum(vbool8_t mask, vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfmacc_vv_f32m4_rm_tum(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmacc_vf_f32m4_rm_tum
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmacc.mask.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
//
vfloat32m4_t test_vfmacc_vf_f32m4_rm_tum(vbool8_t mask, vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfmacc_vf_f32m4_rm_tum(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmacc_vv_f32m8_rm_tum
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmacc.mask.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
//
vfloat32m8_t test_vfmacc_vv_f32m8_rm_tum(vbool4_t mask, vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfmacc_vv_f32m8_rm_tum(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmacc_vf_f32m8_rm_tum
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmacc.mask.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
//
vfloat32m8_t test_vfmacc_vf_f32m8_rm_tum(vbool4_t mask, vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfmacc_vf_f32m8_rm_tum(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmacc_vv_f64m1_rm_tum
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmacc.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfmacc_vv_f64m1_rm_tum(vbool64_t mask, vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfmacc_vv_f64m1_rm_tum(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmacc_vf_f64m1_rm_tum
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmacc.mask.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfmacc_vf_f64m1_rm_tum(vbool64_t mask, vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfmacc_vf_f64m1_rm_tum(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmacc_vv_f64m2_rm_tum
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmacc.mask.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
//
vfloat64m2_t test_vfmacc_vv_f64m2_rm_tum(vbool32_t mask, vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfmacc_vv_f64m2_rm_tum(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmacc_vf_f64m2_rm_tum
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmacc.mask.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
//
vfloat64m2_t test_vfmacc_vf_f64m2_rm_tum(vbool32_t mask, vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfmacc_vf_f64m2_rm_tum(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmacc_vv_f64m4_rm_tum
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmacc.mask.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
//
vfloat64m4_t test_vfmacc_vv_f64m4_rm_tum(vbool16_t mask, vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfmacc_vv_f64m4_rm_tum(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmacc_vf_f64m4_rm_tum
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmacc.mask.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
//
vfloat64m4_t test_vfmacc_vf_f64m4_rm_tum(vbool16_t mask, vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfmacc_vf_f64m4_rm_tum(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmacc_vv_f64m8_rm_tum
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmacc.mask.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
//
vfloat64m8_t test_vfmacc_vv_f64m8_rm_tum(vbool8_t mask, vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfmacc_vv_f64m8_rm_tum(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmacc_vf_f64m8_rm_tum
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmacc.mask.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
//
vfloat64m8_t test_vfmacc_vf_f64m8_rm_tum(vbool8_t mask, vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfmacc_vf_f64m8_rm_tum(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmacc_vv_f16mf4_rm_tumu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmacc.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
//
vfloat16mf4_t test_vfmacc_vv_f16mf4_rm_tumu(vbool64_t mask, vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfmacc_vv_f16mf4_rm_tumu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmacc_vf_f16mf4_rm_tumu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmacc.mask.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
//
vfloat16mf4_t test_vfmacc_vf_f16mf4_rm_tumu(vbool64_t mask, vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfmacc_vf_f16mf4_rm_tumu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmacc_vv_f16mf2_rm_tumu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmacc.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
//
vfloat16mf2_t test_vfmacc_vv_f16mf2_rm_tumu(vbool32_t mask, vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfmacc_vv_f16mf2_rm_tumu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmacc_vf_f16mf2_rm_tumu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmacc.mask.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
//
vfloat16mf2_t test_vfmacc_vf_f16mf2_rm_tumu(vbool32_t mask, vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfmacc_vf_f16mf2_rm_tumu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmacc_vv_f16m1_rm_tumu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmacc.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfmacc_vv_f16m1_rm_tumu(vbool16_t mask, vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfmacc_vv_f16m1_rm_tumu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmacc_vf_f16m1_rm_tumu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmacc.mask.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfmacc_vf_f16m1_rm_tumu(vbool16_t mask, vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfmacc_vf_f16m1_rm_tumu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmacc_vv_f16m2_rm_tumu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmacc.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
//
vfloat16m2_t test_vfmacc_vv_f16m2_rm_tumu(vbool8_t mask, vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfmacc_vv_f16m2_rm_tumu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmacc_vf_f16m2_rm_tumu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmacc.mask.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
//
vfloat16m2_t test_vfmacc_vf_f16m2_rm_tumu(vbool8_t mask, vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfmacc_vf_f16m2_rm_tumu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmacc_vv_f16m4_rm_tumu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmacc.mask.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
//
vfloat16m4_t test_vfmacc_vv_f16m4_rm_tumu(vbool4_t mask, vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfmacc_vv_f16m4_rm_tumu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmacc_vf_f16m4_rm_tumu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmacc.mask.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
//
vfloat16m4_t test_vfmacc_vf_f16m4_rm_tumu(vbool4_t mask, vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfmacc_vf_f16m4_rm_tumu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmacc_vv_f16m8_rm_tumu
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmacc.mask.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
//
vfloat16m8_t test_vfmacc_vv_f16m8_rm_tumu(vbool2_t mask, vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfmacc_vv_f16m8_rm_tumu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmacc_vf_f16m8_rm_tumu
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmacc.mask.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
//
vfloat16m8_t test_vfmacc_vf_f16m8_rm_tumu(vbool2_t mask, vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfmacc_vf_f16m8_rm_tumu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmacc_vv_f32mf2_rm_tumu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmacc.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
//
vfloat32mf2_t test_vfmacc_vv_f32mf2_rm_tumu(vbool64_t mask, vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfmacc_vv_f32mf2_rm_tumu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmacc_vf_f32mf2_rm_tumu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmacc.mask.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
//
vfloat32mf2_t test_vfmacc_vf_f32mf2_rm_tumu(vbool64_t mask, vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfmacc_vf_f32mf2_rm_tumu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmacc_vv_f32m1_rm_tumu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmacc.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfmacc_vv_f32m1_rm_tumu(vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfmacc_vv_f32m1_rm_tumu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmacc_vf_f32m1_rm_tumu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmacc.mask.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfmacc_vf_f32m1_rm_tumu(vbool32_t mask, vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfmacc_vf_f32m1_rm_tumu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmacc_vv_f32m2_rm_tumu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmacc.mask.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
//
vfloat32m2_t test_vfmacc_vv_f32m2_rm_tumu(vbool16_t mask, vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfmacc_vv_f32m2_rm_tumu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmacc_vf_f32m2_rm_tumu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmacc.mask.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
//
vfloat32m2_t test_vfmacc_vf_f32m2_rm_tumu(vbool16_t mask, vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfmacc_vf_f32m2_rm_tumu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmacc_vv_f32m4_rm_tumu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmacc.mask.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
//
vfloat32m4_t test_vfmacc_vv_f32m4_rm_tumu(vbool8_t mask, vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfmacc_vv_f32m4_rm_tumu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmacc_vf_f32m4_rm_tumu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmacc.mask.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
//
vfloat32m4_t test_vfmacc_vf_f32m4_rm_tumu(vbool8_t mask, vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfmacc_vf_f32m4_rm_tumu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmacc_vv_f32m8_rm_tumu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmacc.mask.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
//
vfloat32m8_t test_vfmacc_vv_f32m8_rm_tumu(vbool4_t mask, vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfmacc_vv_f32m8_rm_tumu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmacc_vf_f32m8_rm_tumu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmacc.mask.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
//
vfloat32m8_t test_vfmacc_vf_f32m8_rm_tumu(vbool4_t mask, vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfmacc_vf_f32m8_rm_tumu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmacc_vv_f64m1_rm_tumu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmacc.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfmacc_vv_f64m1_rm_tumu(vbool64_t mask, vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfmacc_vv_f64m1_rm_tumu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmacc_vf_f64m1_rm_tumu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmacc.mask.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfmacc_vf_f64m1_rm_tumu(vbool64_t mask, vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfmacc_vf_f64m1_rm_tumu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmacc_vv_f64m2_rm_tumu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmacc.mask.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
//
vfloat64m2_t test_vfmacc_vv_f64m2_rm_tumu(vbool32_t mask, vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfmacc_vv_f64m2_rm_tumu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmacc_vf_f64m2_rm_tumu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmacc.mask.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
//
vfloat64m2_t test_vfmacc_vf_f64m2_rm_tumu(vbool32_t mask, vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfmacc_vf_f64m2_rm_tumu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmacc_vv_f64m4_rm_tumu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmacc.mask.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
//
vfloat64m4_t test_vfmacc_vv_f64m4_rm_tumu(vbool16_t mask, vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfmacc_vv_f64m4_rm_tumu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmacc_vf_f64m4_rm_tumu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmacc.mask.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
//
vfloat64m4_t test_vfmacc_vf_f64m4_rm_tumu(vbool16_t mask, vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfmacc_vf_f64m4_rm_tumu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmacc_vv_f64m8_rm_tumu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmacc.mask.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
//
vfloat64m8_t test_vfmacc_vv_f64m8_rm_tumu(vbool8_t mask, vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfmacc_vv_f64m8_rm_tumu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmacc_vf_f64m8_rm_tumu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmacc.mask.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
//
vfloat64m8_t test_vfmacc_vf_f64m8_rm_tumu(vbool8_t mask, vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfmacc_vf_f64m8_rm_tumu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmacc_vv_f16mf4_rm_mu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmacc.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
//
vfloat16mf4_t test_vfmacc_vv_f16mf4_rm_mu(vbool64_t mask, vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfmacc_vv_f16mf4_rm_mu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmacc_vf_f16mf4_rm_mu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmacc.mask.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
//
vfloat16mf4_t test_vfmacc_vf_f16mf4_rm_mu(vbool64_t mask, vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfmacc_vf_f16mf4_rm_mu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmacc_vv_f16mf2_rm_mu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmacc.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
//
vfloat16mf2_t test_vfmacc_vv_f16mf2_rm_mu(vbool32_t mask, vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfmacc_vv_f16mf2_rm_mu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmacc_vf_f16mf2_rm_mu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmacc.mask.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
//
vfloat16mf2_t test_vfmacc_vf_f16mf2_rm_mu(vbool32_t mask, vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfmacc_vf_f16mf2_rm_mu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmacc_vv_f16m1_rm_mu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmacc.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfmacc_vv_f16m1_rm_mu(vbool16_t mask, vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfmacc_vv_f16m1_rm_mu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmacc_vf_f16m1_rm_mu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmacc.mask.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfmacc_vf_f16m1_rm_mu(vbool16_t mask, vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfmacc_vf_f16m1_rm_mu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmacc_vv_f16m2_rm_mu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmacc.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
//
vfloat16m2_t test_vfmacc_vv_f16m2_rm_mu(vbool8_t mask, vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfmacc_vv_f16m2_rm_mu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmacc_vf_f16m2_rm_mu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmacc.mask.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
//
vfloat16m2_t test_vfmacc_vf_f16m2_rm_mu(vbool8_t mask, vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfmacc_vf_f16m2_rm_mu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmacc_vv_f16m4_rm_mu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmacc.mask.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
//
vfloat16m4_t test_vfmacc_vv_f16m4_rm_mu(vbool4_t mask, vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfmacc_vv_f16m4_rm_mu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmacc_vf_f16m4_rm_mu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmacc.mask.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
//
vfloat16m4_t test_vfmacc_vf_f16m4_rm_mu(vbool4_t mask, vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfmacc_vf_f16m4_rm_mu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmacc_vv_f16m8_rm_mu
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmacc.mask.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
//
vfloat16m8_t test_vfmacc_vv_f16m8_rm_mu(vbool2_t mask, vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfmacc_vv_f16m8_rm_mu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmacc_vf_f16m8_rm_mu
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmacc.mask.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
//
vfloat16m8_t test_vfmacc_vf_f16m8_rm_mu(vbool2_t mask, vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfmacc_vf_f16m8_rm_mu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmacc_vv_f32mf2_rm_mu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmacc.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
//
vfloat32mf2_t test_vfmacc_vv_f32mf2_rm_mu(vbool64_t mask, vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfmacc_vv_f32mf2_rm_mu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmacc_vf_f32mf2_rm_mu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmacc.mask.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
//
vfloat32mf2_t test_vfmacc_vf_f32mf2_rm_mu(vbool64_t mask, vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfmacc_vf_f32mf2_rm_mu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmacc_vv_f32m1_rm_mu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmacc.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfmacc_vv_f32m1_rm_mu(vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfmacc_vv_f32m1_rm_mu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmacc_vf_f32m1_rm_mu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmacc.mask.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfmacc_vf_f32m1_rm_mu(vbool32_t mask, vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfmacc_vf_f32m1_rm_mu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmacc_vv_f32m2_rm_mu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmacc.mask.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
//
vfloat32m2_t test_vfmacc_vv_f32m2_rm_mu(vbool16_t mask, vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfmacc_vv_f32m2_rm_mu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmacc_vf_f32m2_rm_mu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmacc.mask.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
//
vfloat32m2_t test_vfmacc_vf_f32m2_rm_mu(vbool16_t mask, vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfmacc_vf_f32m2_rm_mu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmacc_vv_f32m4_rm_mu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmacc.mask.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
//
vfloat32m4_t test_vfmacc_vv_f32m4_rm_mu(vbool8_t mask, vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfmacc_vv_f32m4_rm_mu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmacc_vf_f32m4_rm_mu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmacc.mask.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
//
vfloat32m4_t test_vfmacc_vf_f32m4_rm_mu(vbool8_t mask, vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfmacc_vf_f32m4_rm_mu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmacc_vv_f32m8_rm_mu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmacc.mask.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
//
vfloat32m8_t test_vfmacc_vv_f32m8_rm_mu(vbool4_t mask, vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfmacc_vv_f32m8_rm_mu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmacc_vf_f32m8_rm_mu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmacc.mask.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
//
vfloat32m8_t test_vfmacc_vf_f32m8_rm_mu(vbool4_t mask, vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfmacc_vf_f32m8_rm_mu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmacc_vv_f64m1_rm_mu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmacc.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfmacc_vv_f64m1_rm_mu(vbool64_t mask, vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfmacc_vv_f64m1_rm_mu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmacc_vf_f64m1_rm_mu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmacc.mask.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfmacc_vf_f64m1_rm_mu(vbool64_t mask, vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfmacc_vf_f64m1_rm_mu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmacc_vv_f64m2_rm_mu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmacc.mask.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
//
vfloat64m2_t test_vfmacc_vv_f64m2_rm_mu(vbool32_t mask, vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfmacc_vv_f64m2_rm_mu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmacc_vf_f64m2_rm_mu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmacc.mask.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
//
vfloat64m2_t test_vfmacc_vf_f64m2_rm_mu(vbool32_t mask, vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfmacc_vf_f64m2_rm_mu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmacc_vv_f64m4_rm_mu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmacc.mask.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
//
vfloat64m4_t test_vfmacc_vv_f64m4_rm_mu(vbool16_t mask, vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfmacc_vv_f64m4_rm_mu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmacc_vf_f64m4_rm_mu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmacc.mask.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
//
vfloat64m4_t test_vfmacc_vf_f64m4_rm_mu(vbool16_t mask, vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfmacc_vf_f64m4_rm_mu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmacc_vv_f64m8_rm_mu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmacc.mask.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
//
vfloat64m8_t test_vfmacc_vv_f64m8_rm_mu(vbool8_t mask, vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfmacc_vv_f64m8_rm_mu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmacc_vf_f64m8_rm_mu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmacc.mask.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
//
vfloat64m8_t test_vfmacc_vf_f64m8_rm_mu(vbool8_t mask, vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfmacc_vf_f64m8_rm_mu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}

clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmadd.c

// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target // REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh \ // RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh \
// RUN: -target-feature +experimental-zvfh -disable-O0-optnone \ // RUN: -target-feature +experimental-zvfh -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ // RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s // RUN: FileCheck --check-prefix=CHECK-RV64 %s
#include <riscv_vector.h> #include <riscv_vector.h>
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmadd_vv_f16mf4_tu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmadd_vv_f16mf4_tu
// CHECK-RV64-SAME: (<vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK-RV64-SAME: (<vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmadd.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmadd.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
// //
vfloat16mf4_t test_vfmadd_vv_f16mf4_tu(vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) { vfloat16mf4_t test_vfmadd_vv_f16mf4_tu(vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfmadd_vv_f16mf4_tu(vd, vs1, vs2, vl); return __riscv_vfmadd_vv_f16mf4_tu(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmadd_vf_f16mf4_tu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmadd_vf_f16mf4_tu
// CHECK-RV64-SAME: (<vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmadd.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmadd.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
// //
vfloat16mf4_t test_vfmadd_vf_f16mf4_tu(vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) { vfloat16mf4_t test_vfmadd_vf_f16mf4_tu(vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfmadd_vf_f16mf4_tu(vd, rs1, vs2, vl); return __riscv_vfmadd_vf_f16mf4_tu(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmadd_vv_f16mf2_tu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmadd_vv_f16mf2_tu
// CHECK-RV64-SAME: (<vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmadd.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmadd.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
// //
vfloat16mf2_t test_vfmadd_vv_f16mf2_tu(vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) { vfloat16mf2_t test_vfmadd_vv_f16mf2_tu(vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfmadd_vv_f16mf2_tu(vd, vs1, vs2, vl); return __riscv_vfmadd_vv_f16mf2_tu(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmadd_vf_f16mf2_tu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmadd_vf_f16mf2_tu
// CHECK-RV64-SAME: (<vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmadd.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmadd.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
// //
vfloat16mf2_t test_vfmadd_vf_f16mf2_tu(vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) { vfloat16mf2_t test_vfmadd_vf_f16mf2_tu(vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfmadd_vf_f16mf2_tu(vd, rs1, vs2, vl); return __riscv_vfmadd_vf_f16mf2_tu(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmadd_vv_f16m1_tu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmadd_vv_f16m1_tu
// CHECK-RV64-SAME: (<vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmadd.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmadd.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
// //
vfloat16m1_t test_vfmadd_vv_f16m1_tu(vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) { vfloat16m1_t test_vfmadd_vv_f16m1_tu(vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfmadd_vv_f16m1_tu(vd, vs1, vs2, vl); return __riscv_vfmadd_vv_f16m1_tu(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmadd_vf_f16m1_tu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmadd_vf_f16m1_tu
// CHECK-RV64-SAME: (<vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmadd.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmadd.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
// //
vfloat16m1_t test_vfmadd_vf_f16m1_tu(vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) { vfloat16m1_t test_vfmadd_vf_f16m1_tu(vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfmadd_vf_f16m1_tu(vd, rs1, vs2, vl); return __riscv_vfmadd_vf_f16m1_tu(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmadd_vv_f16m2_tu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmadd_vv_f16m2_tu
// CHECK-RV64-SAME: (<vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmadd.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmadd.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
// //
vfloat16m2_t test_vfmadd_vv_f16m2_tu(vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) { vfloat16m2_t test_vfmadd_vv_f16m2_tu(vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfmadd_vv_f16m2_tu(vd, vs1, vs2, vl); return __riscv_vfmadd_vv_f16m2_tu(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmadd_vf_f16m2_tu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmadd_vf_f16m2_tu
// CHECK-RV64-SAME: (<vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmadd.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmadd.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
// //
vfloat16m2_t test_vfmadd_vf_f16m2_tu(vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) { vfloat16m2_t test_vfmadd_vf_f16m2_tu(vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfmadd_vf_f16m2_tu(vd, rs1, vs2, vl); return __riscv_vfmadd_vf_f16m2_tu(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmadd_vv_f16m4_tu // CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmadd_vv_f16m4_tu
// CHECK-RV64-SAME: (<vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmadd.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmadd.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
// //
vfloat16m4_t test_vfmadd_vv_f16m4_tu(vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) { vfloat16m4_t test_vfmadd_vv_f16m4_tu(vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfmadd_vv_f16m4_tu(vd, vs1, vs2, vl); return __riscv_vfmadd_vv_f16m4_tu(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmadd_vf_f16m4_tu // CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmadd_vf_f16m4_tu
// CHECK-RV64-SAME: (<vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmadd.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmadd.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
// //
vfloat16m4_t test_vfmadd_vf_f16m4_tu(vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) { vfloat16m4_t test_vfmadd_vf_f16m4_tu(vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfmadd_vf_f16m4_tu(vd, rs1, vs2, vl); return __riscv_vfmadd_vf_f16m4_tu(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmadd_vv_f16m8_tu // CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmadd_vv_f16m8_tu
// CHECK-RV64-SAME: (<vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmadd.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmadd.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
// //
vfloat16m8_t test_vfmadd_vv_f16m8_tu(vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) { vfloat16m8_t test_vfmadd_vv_f16m8_tu(vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfmadd_vv_f16m8_tu(vd, vs1, vs2, vl); return __riscv_vfmadd_vv_f16m8_tu(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmadd_vf_f16m8_tu // CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmadd_vf_f16m8_tu
// CHECK-RV64-SAME: (<vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmadd.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmadd.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
// //
vfloat16m8_t test_vfmadd_vf_f16m8_tu(vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) { vfloat16m8_t test_vfmadd_vf_f16m8_tu(vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfmadd_vf_f16m8_tu(vd, rs1, vs2, vl); return __riscv_vfmadd_vf_f16m8_tu(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmadd_vv_f32mf2_tu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmadd_vv_f32mf2_tu
// CHECK-RV64-SAME: (<vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmadd.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmadd.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfmadd_vv_f32mf2_tu(vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) { vfloat32mf2_t test_vfmadd_vv_f32mf2_tu(vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfmadd_vv_f32mf2_tu(vd, vs1, vs2, vl); return __riscv_vfmadd_vv_f32mf2_tu(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmadd_vf_f32mf2_tu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmadd_vf_f32mf2_tu
// CHECK-RV64-SAME: (<vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmadd.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmadd.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfmadd_vf_f32mf2_tu(vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) { vfloat32mf2_t test_vfmadd_vf_f32mf2_tu(vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfmadd_vf_f32mf2_tu(vd, rs1, vs2, vl); return __riscv_vfmadd_vf_f32mf2_tu(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmadd_vv_f32m1_tu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmadd_vv_f32m1_tu
// CHECK-RV64-SAME: (<vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmadd.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmadd.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfmadd_vv_f32m1_tu(vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) { vfloat32m1_t test_vfmadd_vv_f32m1_tu(vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfmadd_vv_f32m1_tu(vd, vs1, vs2, vl); return __riscv_vfmadd_vv_f32m1_tu(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmadd_vf_f32m1_tu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmadd_vf_f32m1_tu
// CHECK-RV64-SAME: (<vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmadd.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmadd.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfmadd_vf_f32m1_tu(vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) { vfloat32m1_t test_vfmadd_vf_f32m1_tu(vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfmadd_vf_f32m1_tu(vd, rs1, vs2, vl); return __riscv_vfmadd_vf_f32m1_tu(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmadd_vv_f32m2_tu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmadd_vv_f32m2_tu
// CHECK-RV64-SAME: (<vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmadd.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmadd.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfmadd_vv_f32m2_tu(vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) { vfloat32m2_t test_vfmadd_vv_f32m2_tu(vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfmadd_vv_f32m2_tu(vd, vs1, vs2, vl); return __riscv_vfmadd_vv_f32m2_tu(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmadd_vf_f32m2_tu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmadd_vf_f32m2_tu
// CHECK-RV64-SAME: (<vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmadd.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmadd.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfmadd_vf_f32m2_tu(vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) { vfloat32m2_t test_vfmadd_vf_f32m2_tu(vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfmadd_vf_f32m2_tu(vd, rs1, vs2, vl); return __riscv_vfmadd_vf_f32m2_tu(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmadd_vv_f32m4_tu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmadd_vv_f32m4_tu
// CHECK-RV64-SAME: (<vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmadd.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmadd.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfmadd_vv_f32m4_tu(vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) { vfloat32m4_t test_vfmadd_vv_f32m4_tu(vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfmadd_vv_f32m4_tu(vd, vs1, vs2, vl); return __riscv_vfmadd_vv_f32m4_tu(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmadd_vf_f32m4_tu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmadd_vf_f32m4_tu
// CHECK-RV64-SAME: (<vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmadd.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmadd.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfmadd_vf_f32m4_tu(vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) { vfloat32m4_t test_vfmadd_vf_f32m4_tu(vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfmadd_vf_f32m4_tu(vd, rs1, vs2, vl); return __riscv_vfmadd_vf_f32m4_tu(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmadd_vv_f32m8_tu // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmadd_vv_f32m8_tu
// CHECK-RV64-SAME: (<vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmadd.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmadd.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfmadd_vv_f32m8_tu(vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) { vfloat32m8_t test_vfmadd_vv_f32m8_tu(vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfmadd_vv_f32m8_tu(vd, vs1, vs2, vl); return __riscv_vfmadd_vv_f32m8_tu(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmadd_vf_f32m8_tu // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmadd_vf_f32m8_tu
// CHECK-RV64-SAME: (<vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmadd.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmadd.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfmadd_vf_f32m8_tu(vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) { vfloat32m8_t test_vfmadd_vf_f32m8_tu(vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfmadd_vf_f32m8_tu(vd, rs1, vs2, vl); return __riscv_vfmadd_vf_f32m8_tu(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmadd_vv_f64m1_tu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmadd_vv_f64m1_tu
// CHECK-RV64-SAME: (<vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmadd.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmadd.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfmadd_vv_f64m1_tu(vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) { vfloat64m1_t test_vfmadd_vv_f64m1_tu(vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfmadd_vv_f64m1_tu(vd, vs1, vs2, vl); return __riscv_vfmadd_vv_f64m1_tu(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmadd_vf_f64m1_tu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmadd_vf_f64m1_tu
// CHECK-RV64-SAME: (<vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmadd.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmadd.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfmadd_vf_f64m1_tu(vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) { vfloat64m1_t test_vfmadd_vf_f64m1_tu(vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfmadd_vf_f64m1_tu(vd, rs1, vs2, vl); return __riscv_vfmadd_vf_f64m1_tu(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmadd_vv_f64m2_tu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmadd_vv_f64m2_tu
// CHECK-RV64-SAME: (<vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmadd.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmadd.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfmadd_vv_f64m2_tu(vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) { vfloat64m2_t test_vfmadd_vv_f64m2_tu(vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfmadd_vv_f64m2_tu(vd, vs1, vs2, vl); return __riscv_vfmadd_vv_f64m2_tu(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmadd_vf_f64m2_tu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmadd_vf_f64m2_tu
// CHECK-RV64-SAME: (<vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmadd.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmadd.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfmadd_vf_f64m2_tu(vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) { vfloat64m2_t test_vfmadd_vf_f64m2_tu(vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfmadd_vf_f64m2_tu(vd, rs1, vs2, vl); return __riscv_vfmadd_vf_f64m2_tu(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmadd_vv_f64m4_tu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmadd_vv_f64m4_tu
// CHECK-RV64-SAME: (<vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmadd.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmadd.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfmadd_vv_f64m4_tu(vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) { vfloat64m4_t test_vfmadd_vv_f64m4_tu(vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfmadd_vv_f64m4_tu(vd, vs1, vs2, vl); return __riscv_vfmadd_vv_f64m4_tu(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmadd_vf_f64m4_tu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmadd_vf_f64m4_tu
// CHECK-RV64-SAME: (<vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmadd.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmadd.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfmadd_vf_f64m4_tu(vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) { vfloat64m4_t test_vfmadd_vf_f64m4_tu(vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfmadd_vf_f64m4_tu(vd, rs1, vs2, vl); return __riscv_vfmadd_vf_f64m4_tu(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmadd_vv_f64m8_tu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmadd_vv_f64m8_tu
// CHECK-RV64-SAME: (<vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmadd.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmadd.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfmadd_vv_f64m8_tu(vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) { vfloat64m8_t test_vfmadd_vv_f64m8_tu(vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfmadd_vv_f64m8_tu(vd, vs1, vs2, vl); return __riscv_vfmadd_vv_f64m8_tu(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmadd_vf_f64m8_tu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmadd_vf_f64m8_tu
// CHECK-RV64-SAME: (<vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmadd.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmadd.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfmadd_vf_f64m8_tu(vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) { vfloat64m8_t test_vfmadd_vf_f64m8_tu(vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfmadd_vf_f64m8_tu(vd, rs1, vs2, vl); return __riscv_vfmadd_vf_f64m8_tu(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmadd_vv_f16mf4_tum // CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmadd_vv_f16mf4_tum
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmadd.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmadd.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
// //
vfloat16mf4_t test_vfmadd_vv_f16mf4_tum(vbool64_t mask, vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) { vfloat16mf4_t test_vfmadd_vv_f16mf4_tum(vbool64_t mask, vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfmadd_vv_f16mf4_tum(mask, vd, vs1, vs2, vl); return __riscv_vfmadd_vv_f16mf4_tum(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmadd_vf_f16mf4_tum // CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmadd_vf_f16mf4_tum
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmadd.mask.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmadd.mask.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
// //
vfloat16mf4_t test_vfmadd_vf_f16mf4_tum(vbool64_t mask, vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) { vfloat16mf4_t test_vfmadd_vf_f16mf4_tum(vbool64_t mask, vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfmadd_vf_f16mf4_tum(mask, vd, rs1, vs2, vl); return __riscv_vfmadd_vf_f16mf4_tum(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmadd_vv_f16mf2_tum // CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmadd_vv_f16mf2_tum
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmadd.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmadd.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
// //
vfloat16mf2_t test_vfmadd_vv_f16mf2_tum(vbool32_t mask, vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) { vfloat16mf2_t test_vfmadd_vv_f16mf2_tum(vbool32_t mask, vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfmadd_vv_f16mf2_tum(mask, vd, vs1, vs2, vl); return __riscv_vfmadd_vv_f16mf2_tum(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmadd_vf_f16mf2_tum // CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmadd_vf_f16mf2_tum
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmadd.mask.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmadd.mask.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
// //
vfloat16mf2_t test_vfmadd_vf_f16mf2_tum(vbool32_t mask, vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) { vfloat16mf2_t test_vfmadd_vf_f16mf2_tum(vbool32_t mask, vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfmadd_vf_f16mf2_tum(mask, vd, rs1, vs2, vl); return __riscv_vfmadd_vf_f16mf2_tum(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmadd_vv_f16m1_tum // CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmadd_vv_f16m1_tum
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmadd.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmadd.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
// //
vfloat16m1_t test_vfmadd_vv_f16m1_tum(vbool16_t mask, vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) { vfloat16m1_t test_vfmadd_vv_f16m1_tum(vbool16_t mask, vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfmadd_vv_f16m1_tum(mask, vd, vs1, vs2, vl); return __riscv_vfmadd_vv_f16m1_tum(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmadd_vf_f16m1_tum // CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmadd_vf_f16m1_tum
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmadd.mask.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmadd.mask.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
// //
vfloat16m1_t test_vfmadd_vf_f16m1_tum(vbool16_t mask, vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) { vfloat16m1_t test_vfmadd_vf_f16m1_tum(vbool16_t mask, vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfmadd_vf_f16m1_tum(mask, vd, rs1, vs2, vl); return __riscv_vfmadd_vf_f16m1_tum(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmadd_vv_f16m2_tum // CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmadd_vv_f16m2_tum
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmadd.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmadd.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
// //
vfloat16m2_t test_vfmadd_vv_f16m2_tum(vbool8_t mask, vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) { vfloat16m2_t test_vfmadd_vv_f16m2_tum(vbool8_t mask, vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfmadd_vv_f16m2_tum(mask, vd, vs1, vs2, vl); return __riscv_vfmadd_vv_f16m2_tum(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmadd_vf_f16m2_tum // CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmadd_vf_f16m2_tum
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmadd.mask.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmadd.mask.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
// //
vfloat16m2_t test_vfmadd_vf_f16m2_tum(vbool8_t mask, vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) { vfloat16m2_t test_vfmadd_vf_f16m2_tum(vbool8_t mask, vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfmadd_vf_f16m2_tum(mask, vd, rs1, vs2, vl); return __riscv_vfmadd_vf_f16m2_tum(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmadd_vv_f16m4_tum // CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmadd_vv_f16m4_tum
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmadd.mask.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmadd.mask.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
// //
vfloat16m4_t test_vfmadd_vv_f16m4_tum(vbool4_t mask, vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) { vfloat16m4_t test_vfmadd_vv_f16m4_tum(vbool4_t mask, vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfmadd_vv_f16m4_tum(mask, vd, vs1, vs2, vl); return __riscv_vfmadd_vv_f16m4_tum(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmadd_vf_f16m4_tum // CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmadd_vf_f16m4_tum
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmadd.mask.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmadd.mask.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
// //
vfloat16m4_t test_vfmadd_vf_f16m4_tum(vbool4_t mask, vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) { vfloat16m4_t test_vfmadd_vf_f16m4_tum(vbool4_t mask, vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfmadd_vf_f16m4_tum(mask, vd, rs1, vs2, vl); return __riscv_vfmadd_vf_f16m4_tum(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmadd_vv_f16m8_tum // CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmadd_vv_f16m8_tum
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmadd.mask.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmadd.mask.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
// //
vfloat16m8_t test_vfmadd_vv_f16m8_tum(vbool2_t mask, vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) { vfloat16m8_t test_vfmadd_vv_f16m8_tum(vbool2_t mask, vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfmadd_vv_f16m8_tum(mask, vd, vs1, vs2, vl); return __riscv_vfmadd_vv_f16m8_tum(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmadd_vf_f16m8_tum // CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmadd_vf_f16m8_tum
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmadd.mask.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmadd.mask.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
// //
vfloat16m8_t test_vfmadd_vf_f16m8_tum(vbool2_t mask, vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) { vfloat16m8_t test_vfmadd_vf_f16m8_tum(vbool2_t mask, vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfmadd_vf_f16m8_tum(mask, vd, rs1, vs2, vl); return __riscv_vfmadd_vf_f16m8_tum(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmadd_vv_f32mf2_tum // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmadd_vv_f32mf2_tum
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmadd.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmadd.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfmadd_vv_f32mf2_tum(vbool64_t mask, vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) { vfloat32mf2_t test_vfmadd_vv_f32mf2_tum(vbool64_t mask, vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfmadd_vv_f32mf2_tum(mask, vd, vs1, vs2, vl); return __riscv_vfmadd_vv_f32mf2_tum(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmadd_vf_f32mf2_tum // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmadd_vf_f32mf2_tum
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmadd.mask.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmadd.mask.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfmadd_vf_f32mf2_tum(vbool64_t mask, vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) { vfloat32mf2_t test_vfmadd_vf_f32mf2_tum(vbool64_t mask, vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfmadd_vf_f32mf2_tum(mask, vd, rs1, vs2, vl); return __riscv_vfmadd_vf_f32mf2_tum(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmadd_vv_f32m1_tum // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmadd_vv_f32m1_tum
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmadd.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmadd.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfmadd_vv_f32m1_tum(vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) { vfloat32m1_t test_vfmadd_vv_f32m1_tum(vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfmadd_vv_f32m1_tum(mask, vd, vs1, vs2, vl); return __riscv_vfmadd_vv_f32m1_tum(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmadd_vf_f32m1_tum // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmadd_vf_f32m1_tum
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmadd.mask.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmadd.mask.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfmadd_vf_f32m1_tum(vbool32_t mask, vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) { vfloat32m1_t test_vfmadd_vf_f32m1_tum(vbool32_t mask, vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfmadd_vf_f32m1_tum(mask, vd, rs1, vs2, vl); return __riscv_vfmadd_vf_f32m1_tum(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmadd_vv_f32m2_tum // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmadd_vv_f32m2_tum
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmadd.mask.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmadd.mask.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfmadd_vv_f32m2_tum(vbool16_t mask, vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) { vfloat32m2_t test_vfmadd_vv_f32m2_tum(vbool16_t mask, vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfmadd_vv_f32m2_tum(mask, vd, vs1, vs2, vl); return __riscv_vfmadd_vv_f32m2_tum(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmadd_vf_f32m2_tum // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmadd_vf_f32m2_tum
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmadd.mask.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmadd.mask.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfmadd_vf_f32m2_tum(vbool16_t mask, vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) { vfloat32m2_t test_vfmadd_vf_f32m2_tum(vbool16_t mask, vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfmadd_vf_f32m2_tum(mask, vd, rs1, vs2, vl); return __riscv_vfmadd_vf_f32m2_tum(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmadd_vv_f32m4_tum // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmadd_vv_f32m4_tum
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmadd.mask.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmadd.mask.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfmadd_vv_f32m4_tum(vbool8_t mask, vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) { vfloat32m4_t test_vfmadd_vv_f32m4_tum(vbool8_t mask, vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfmadd_vv_f32m4_tum(mask, vd, vs1, vs2, vl); return __riscv_vfmadd_vv_f32m4_tum(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmadd_vf_f32m4_tum // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmadd_vf_f32m4_tum
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmadd.mask.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmadd.mask.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfmadd_vf_f32m4_tum(vbool8_t mask, vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) { vfloat32m4_t test_vfmadd_vf_f32m4_tum(vbool8_t mask, vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfmadd_vf_f32m4_tum(mask, vd, rs1, vs2, vl); return __riscv_vfmadd_vf_f32m4_tum(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmadd_vv_f32m8_tum // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmadd_vv_f32m8_tum
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmadd.mask.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmadd.mask.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfmadd_vv_f32m8_tum(vbool4_t mask, vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) { vfloat32m8_t test_vfmadd_vv_f32m8_tum(vbool4_t mask, vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfmadd_vv_f32m8_tum(mask, vd, vs1, vs2, vl); return __riscv_vfmadd_vv_f32m8_tum(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmadd_vf_f32m8_tum // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmadd_vf_f32m8_tum
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmadd.mask.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmadd.mask.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfmadd_vf_f32m8_tum(vbool4_t mask, vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) { vfloat32m8_t test_vfmadd_vf_f32m8_tum(vbool4_t mask, vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfmadd_vf_f32m8_tum(mask, vd, rs1, vs2, vl); return __riscv_vfmadd_vf_f32m8_tum(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmadd_vv_f64m1_tum // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmadd_vv_f64m1_tum
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmadd.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmadd.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfmadd_vv_f64m1_tum(vbool64_t mask, vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) { vfloat64m1_t test_vfmadd_vv_f64m1_tum(vbool64_t mask, vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfmadd_vv_f64m1_tum(mask, vd, vs1, vs2, vl); return __riscv_vfmadd_vv_f64m1_tum(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmadd_vf_f64m1_tum // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmadd_vf_f64m1_tum
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmadd.mask.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmadd.mask.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfmadd_vf_f64m1_tum(vbool64_t mask, vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) { vfloat64m1_t test_vfmadd_vf_f64m1_tum(vbool64_t mask, vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfmadd_vf_f64m1_tum(mask, vd, rs1, vs2, vl); return __riscv_vfmadd_vf_f64m1_tum(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmadd_vv_f64m2_tum // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmadd_vv_f64m2_tum
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmadd.mask.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmadd.mask.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfmadd_vv_f64m2_tum(vbool32_t mask, vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) { vfloat64m2_t test_vfmadd_vv_f64m2_tum(vbool32_t mask, vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfmadd_vv_f64m2_tum(mask, vd, vs1, vs2, vl); return __riscv_vfmadd_vv_f64m2_tum(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmadd_vf_f64m2_tum // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmadd_vf_f64m2_tum
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmadd.mask.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmadd.mask.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfmadd_vf_f64m2_tum(vbool32_t mask, vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) { vfloat64m2_t test_vfmadd_vf_f64m2_tum(vbool32_t mask, vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfmadd_vf_f64m2_tum(mask, vd, rs1, vs2, vl); return __riscv_vfmadd_vf_f64m2_tum(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmadd_vv_f64m4_tum // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmadd_vv_f64m4_tum
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmadd.mask.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmadd.mask.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfmadd_vv_f64m4_tum(vbool16_t mask, vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) { vfloat64m4_t test_vfmadd_vv_f64m4_tum(vbool16_t mask, vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfmadd_vv_f64m4_tum(mask, vd, vs1, vs2, vl); return __riscv_vfmadd_vv_f64m4_tum(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmadd_vf_f64m4_tum // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmadd_vf_f64m4_tum
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmadd.mask.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmadd.mask.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfmadd_vf_f64m4_tum(vbool16_t mask, vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) { vfloat64m4_t test_vfmadd_vf_f64m4_tum(vbool16_t mask, vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfmadd_vf_f64m4_tum(mask, vd, rs1, vs2, vl); return __riscv_vfmadd_vf_f64m4_tum(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmadd_vv_f64m8_tum // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmadd_vv_f64m8_tum
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmadd.mask.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmadd.mask.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfmadd_vv_f64m8_tum(vbool8_t mask, vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) { vfloat64m8_t test_vfmadd_vv_f64m8_tum(vbool8_t mask, vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfmadd_vv_f64m8_tum(mask, vd, vs1, vs2, vl); return __riscv_vfmadd_vv_f64m8_tum(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmadd_vf_f64m8_tum // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmadd_vf_f64m8_tum
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmadd.mask.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmadd.mask.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfmadd_vf_f64m8_tum(vbool8_t mask, vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) { vfloat64m8_t test_vfmadd_vf_f64m8_tum(vbool8_t mask, vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfmadd_vf_f64m8_tum(mask, vd, rs1, vs2, vl); return __riscv_vfmadd_vf_f64m8_tum(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmadd_vv_f16mf4_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmadd_vv_f16mf4_tumu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmadd.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmadd.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
// //
vfloat16mf4_t test_vfmadd_vv_f16mf4_tumu(vbool64_t mask, vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) { vfloat16mf4_t test_vfmadd_vv_f16mf4_tumu(vbool64_t mask, vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfmadd_vv_f16mf4_tumu(mask, vd, vs1, vs2, vl); return __riscv_vfmadd_vv_f16mf4_tumu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmadd_vf_f16mf4_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmadd_vf_f16mf4_tumu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmadd.mask.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmadd.mask.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
// //
vfloat16mf4_t test_vfmadd_vf_f16mf4_tumu(vbool64_t mask, vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) { vfloat16mf4_t test_vfmadd_vf_f16mf4_tumu(vbool64_t mask, vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfmadd_vf_f16mf4_tumu(mask, vd, rs1, vs2, vl); return __riscv_vfmadd_vf_f16mf4_tumu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmadd_vv_f16mf2_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmadd_vv_f16mf2_tumu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmadd.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmadd.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
// //
vfloat16mf2_t test_vfmadd_vv_f16mf2_tumu(vbool32_t mask, vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) { vfloat16mf2_t test_vfmadd_vv_f16mf2_tumu(vbool32_t mask, vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfmadd_vv_f16mf2_tumu(mask, vd, vs1, vs2, vl); return __riscv_vfmadd_vv_f16mf2_tumu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmadd_vf_f16mf2_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmadd_vf_f16mf2_tumu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmadd.mask.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmadd.mask.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
// //
vfloat16mf2_t test_vfmadd_vf_f16mf2_tumu(vbool32_t mask, vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) { vfloat16mf2_t test_vfmadd_vf_f16mf2_tumu(vbool32_t mask, vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfmadd_vf_f16mf2_tumu(mask, vd, rs1, vs2, vl); return __riscv_vfmadd_vf_f16mf2_tumu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmadd_vv_f16m1_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmadd_vv_f16m1_tumu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmadd.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmadd.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
// //
vfloat16m1_t test_vfmadd_vv_f16m1_tumu(vbool16_t mask, vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) { vfloat16m1_t test_vfmadd_vv_f16m1_tumu(vbool16_t mask, vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfmadd_vv_f16m1_tumu(mask, vd, vs1, vs2, vl); return __riscv_vfmadd_vv_f16m1_tumu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmadd_vf_f16m1_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmadd_vf_f16m1_tumu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmadd.mask.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmadd.mask.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
// //
vfloat16m1_t test_vfmadd_vf_f16m1_tumu(vbool16_t mask, vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) { vfloat16m1_t test_vfmadd_vf_f16m1_tumu(vbool16_t mask, vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfmadd_vf_f16m1_tumu(mask, vd, rs1, vs2, vl); return __riscv_vfmadd_vf_f16m1_tumu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmadd_vv_f16m2_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmadd_vv_f16m2_tumu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmadd.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmadd.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
// //
vfloat16m2_t test_vfmadd_vv_f16m2_tumu(vbool8_t mask, vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) { vfloat16m2_t test_vfmadd_vv_f16m2_tumu(vbool8_t mask, vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfmadd_vv_f16m2_tumu(mask, vd, vs1, vs2, vl); return __riscv_vfmadd_vv_f16m2_tumu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmadd_vf_f16m2_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmadd_vf_f16m2_tumu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmadd.mask.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmadd.mask.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
// //
vfloat16m2_t test_vfmadd_vf_f16m2_tumu(vbool8_t mask, vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) { vfloat16m2_t test_vfmadd_vf_f16m2_tumu(vbool8_t mask, vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfmadd_vf_f16m2_tumu(mask, vd, rs1, vs2, vl); return __riscv_vfmadd_vf_f16m2_tumu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmadd_vv_f16m4_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmadd_vv_f16m4_tumu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmadd.mask.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmadd.mask.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
// //
vfloat16m4_t test_vfmadd_vv_f16m4_tumu(vbool4_t mask, vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) { vfloat16m4_t test_vfmadd_vv_f16m4_tumu(vbool4_t mask, vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfmadd_vv_f16m4_tumu(mask, vd, vs1, vs2, vl); return __riscv_vfmadd_vv_f16m4_tumu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmadd_vf_f16m4_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmadd_vf_f16m4_tumu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmadd.mask.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmadd.mask.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
// //
vfloat16m4_t test_vfmadd_vf_f16m4_tumu(vbool4_t mask, vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) { vfloat16m4_t test_vfmadd_vf_f16m4_tumu(vbool4_t mask, vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfmadd_vf_f16m4_tumu(mask, vd, rs1, vs2, vl); return __riscv_vfmadd_vf_f16m4_tumu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmadd_vv_f16m8_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmadd_vv_f16m8_tumu
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmadd.mask.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmadd.mask.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
// //
vfloat16m8_t test_vfmadd_vv_f16m8_tumu(vbool2_t mask, vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) { vfloat16m8_t test_vfmadd_vv_f16m8_tumu(vbool2_t mask, vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfmadd_vv_f16m8_tumu(mask, vd, vs1, vs2, vl); return __riscv_vfmadd_vv_f16m8_tumu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmadd_vf_f16m8_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmadd_vf_f16m8_tumu
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmadd.mask.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmadd.mask.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
// //
vfloat16m8_t test_vfmadd_vf_f16m8_tumu(vbool2_t mask, vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) { vfloat16m8_t test_vfmadd_vf_f16m8_tumu(vbool2_t mask, vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfmadd_vf_f16m8_tumu(mask, vd, rs1, vs2, vl); return __riscv_vfmadd_vf_f16m8_tumu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmadd_vv_f32mf2_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmadd_vv_f32mf2_tumu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmadd.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmadd.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfmadd_vv_f32mf2_tumu(vbool64_t mask, vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) { vfloat32mf2_t test_vfmadd_vv_f32mf2_tumu(vbool64_t mask, vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfmadd_vv_f32mf2_tumu(mask, vd, vs1, vs2, vl); return __riscv_vfmadd_vv_f32mf2_tumu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmadd_vf_f32mf2_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmadd_vf_f32mf2_tumu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmadd.mask.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmadd.mask.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfmadd_vf_f32mf2_tumu(vbool64_t mask, vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) { vfloat32mf2_t test_vfmadd_vf_f32mf2_tumu(vbool64_t mask, vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfmadd_vf_f32mf2_tumu(mask, vd, rs1, vs2, vl); return __riscv_vfmadd_vf_f32mf2_tumu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmadd_vv_f32m1_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmadd_vv_f32m1_tumu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmadd.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmadd.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfmadd_vv_f32m1_tumu(vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) { vfloat32m1_t test_vfmadd_vv_f32m1_tumu(vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfmadd_vv_f32m1_tumu(mask, vd, vs1, vs2, vl); return __riscv_vfmadd_vv_f32m1_tumu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmadd_vf_f32m1_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmadd_vf_f32m1_tumu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmadd.mask.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmadd.mask.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfmadd_vf_f32m1_tumu(vbool32_t mask, vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) { vfloat32m1_t test_vfmadd_vf_f32m1_tumu(vbool32_t mask, vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfmadd_vf_f32m1_tumu(mask, vd, rs1, vs2, vl); return __riscv_vfmadd_vf_f32m1_tumu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmadd_vv_f32m2_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmadd_vv_f32m2_tumu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmadd.mask.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmadd.mask.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfmadd_vv_f32m2_tumu(vbool16_t mask, vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) { vfloat32m2_t test_vfmadd_vv_f32m2_tumu(vbool16_t mask, vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfmadd_vv_f32m2_tumu(mask, vd, vs1, vs2, vl); return __riscv_vfmadd_vv_f32m2_tumu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmadd_vf_f32m2_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmadd_vf_f32m2_tumu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmadd.mask.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmadd.mask.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfmadd_vf_f32m2_tumu(vbool16_t mask, vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) { vfloat32m2_t test_vfmadd_vf_f32m2_tumu(vbool16_t mask, vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfmadd_vf_f32m2_tumu(mask, vd, rs1, vs2, vl); return __riscv_vfmadd_vf_f32m2_tumu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmadd_vv_f32m4_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmadd_vv_f32m4_tumu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmadd.mask.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmadd.mask.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfmadd_vv_f32m4_tumu(vbool8_t mask, vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) { vfloat32m4_t test_vfmadd_vv_f32m4_tumu(vbool8_t mask, vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfmadd_vv_f32m4_tumu(mask, vd, vs1, vs2, vl); return __riscv_vfmadd_vv_f32m4_tumu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmadd_vf_f32m4_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmadd_vf_f32m4_tumu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmadd.mask.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmadd.mask.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfmadd_vf_f32m4_tumu(vbool8_t mask, vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) { vfloat32m4_t test_vfmadd_vf_f32m4_tumu(vbool8_t mask, vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfmadd_vf_f32m4_tumu(mask, vd, rs1, vs2, vl); return __riscv_vfmadd_vf_f32m4_tumu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmadd_vv_f32m8_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmadd_vv_f32m8_tumu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmadd.mask.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmadd.mask.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfmadd_vv_f32m8_tumu(vbool4_t mask, vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) { vfloat32m8_t test_vfmadd_vv_f32m8_tumu(vbool4_t mask, vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfmadd_vv_f32m8_tumu(mask, vd, vs1, vs2, vl); return __riscv_vfmadd_vv_f32m8_tumu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmadd_vf_f32m8_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmadd_vf_f32m8_tumu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmadd.mask.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmadd.mask.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfmadd_vf_f32m8_tumu(vbool4_t mask, vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) { vfloat32m8_t test_vfmadd_vf_f32m8_tumu(vbool4_t mask, vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfmadd_vf_f32m8_tumu(mask, vd, rs1, vs2, vl); return __riscv_vfmadd_vf_f32m8_tumu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmadd_vv_f64m1_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmadd_vv_f64m1_tumu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmadd.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmadd.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfmadd_vv_f64m1_tumu(vbool64_t mask, vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) { vfloat64m1_t test_vfmadd_vv_f64m1_tumu(vbool64_t mask, vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfmadd_vv_f64m1_tumu(mask, vd, vs1, vs2, vl); return __riscv_vfmadd_vv_f64m1_tumu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmadd_vf_f64m1_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmadd_vf_f64m1_tumu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmadd.mask.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmadd.mask.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfmadd_vf_f64m1_tumu(vbool64_t mask, vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) { vfloat64m1_t test_vfmadd_vf_f64m1_tumu(vbool64_t mask, vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfmadd_vf_f64m1_tumu(mask, vd, rs1, vs2, vl); return __riscv_vfmadd_vf_f64m1_tumu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmadd_vv_f64m2_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmadd_vv_f64m2_tumu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmadd.mask.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmadd.mask.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfmadd_vv_f64m2_tumu(vbool32_t mask, vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) { vfloat64m2_t test_vfmadd_vv_f64m2_tumu(vbool32_t mask, vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfmadd_vv_f64m2_tumu(mask, vd, vs1, vs2, vl); return __riscv_vfmadd_vv_f64m2_tumu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmadd_vf_f64m2_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmadd_vf_f64m2_tumu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmadd.mask.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmadd.mask.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfmadd_vf_f64m2_tumu(vbool32_t mask, vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) { vfloat64m2_t test_vfmadd_vf_f64m2_tumu(vbool32_t mask, vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfmadd_vf_f64m2_tumu(mask, vd, rs1, vs2, vl); return __riscv_vfmadd_vf_f64m2_tumu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmadd_vv_f64m4_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmadd_vv_f64m4_tumu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmadd.mask.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmadd.mask.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfmadd_vv_f64m4_tumu(vbool16_t mask, vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) { vfloat64m4_t test_vfmadd_vv_f64m4_tumu(vbool16_t mask, vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfmadd_vv_f64m4_tumu(mask, vd, vs1, vs2, vl); return __riscv_vfmadd_vv_f64m4_tumu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmadd_vf_f64m4_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmadd_vf_f64m4_tumu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmadd.mask.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmadd.mask.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfmadd_vf_f64m4_tumu(vbool16_t mask, vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) { vfloat64m4_t test_vfmadd_vf_f64m4_tumu(vbool16_t mask, vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfmadd_vf_f64m4_tumu(mask, vd, rs1, vs2, vl); return __riscv_vfmadd_vf_f64m4_tumu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmadd_vv_f64m8_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmadd_vv_f64m8_tumu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmadd.mask.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmadd.mask.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfmadd_vv_f64m8_tumu(vbool8_t mask, vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) { vfloat64m8_t test_vfmadd_vv_f64m8_tumu(vbool8_t mask, vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfmadd_vv_f64m8_tumu(mask, vd, vs1, vs2, vl); return __riscv_vfmadd_vv_f64m8_tumu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmadd_vf_f64m8_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmadd_vf_f64m8_tumu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmadd.mask.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmadd.mask.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfmadd_vf_f64m8_tumu(vbool8_t mask, vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) { vfloat64m8_t test_vfmadd_vf_f64m8_tumu(vbool8_t mask, vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfmadd_vf_f64m8_tumu(mask, vd, rs1, vs2, vl); return __riscv_vfmadd_vf_f64m8_tumu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmadd_vv_f16mf4_mu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmadd_vv_f16mf4_mu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmadd.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmadd.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
// //
vfloat16mf4_t test_vfmadd_vv_f16mf4_mu(vbool64_t mask, vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) { vfloat16mf4_t test_vfmadd_vv_f16mf4_mu(vbool64_t mask, vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfmadd_vv_f16mf4_mu(mask, vd, vs1, vs2, vl); return __riscv_vfmadd_vv_f16mf4_mu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmadd_vf_f16mf4_mu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmadd_vf_f16mf4_mu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmadd.mask.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmadd.mask.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
// //
vfloat16mf4_t test_vfmadd_vf_f16mf4_mu(vbool64_t mask, vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) { vfloat16mf4_t test_vfmadd_vf_f16mf4_mu(vbool64_t mask, vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfmadd_vf_f16mf4_mu(mask, vd, rs1, vs2, vl); return __riscv_vfmadd_vf_f16mf4_mu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmadd_vv_f16mf2_mu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmadd_vv_f16mf2_mu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmadd.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmadd.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
// //
vfloat16mf2_t test_vfmadd_vv_f16mf2_mu(vbool32_t mask, vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) { vfloat16mf2_t test_vfmadd_vv_f16mf2_mu(vbool32_t mask, vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfmadd_vv_f16mf2_mu(mask, vd, vs1, vs2, vl); return __riscv_vfmadd_vv_f16mf2_mu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmadd_vf_f16mf2_mu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmadd_vf_f16mf2_mu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmadd.mask.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmadd.mask.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
// //
vfloat16mf2_t test_vfmadd_vf_f16mf2_mu(vbool32_t mask, vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) { vfloat16mf2_t test_vfmadd_vf_f16mf2_mu(vbool32_t mask, vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfmadd_vf_f16mf2_mu(mask, vd, rs1, vs2, vl); return __riscv_vfmadd_vf_f16mf2_mu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmadd_vv_f16m1_mu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmadd_vv_f16m1_mu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmadd.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmadd.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
// //
vfloat16m1_t test_vfmadd_vv_f16m1_mu(vbool16_t mask, vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) { vfloat16m1_t test_vfmadd_vv_f16m1_mu(vbool16_t mask, vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfmadd_vv_f16m1_mu(mask, vd, vs1, vs2, vl); return __riscv_vfmadd_vv_f16m1_mu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmadd_vf_f16m1_mu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmadd_vf_f16m1_mu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmadd.mask.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmadd.mask.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
// //
vfloat16m1_t test_vfmadd_vf_f16m1_mu(vbool16_t mask, vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) { vfloat16m1_t test_vfmadd_vf_f16m1_mu(vbool16_t mask, vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfmadd_vf_f16m1_mu(mask, vd, rs1, vs2, vl); return __riscv_vfmadd_vf_f16m1_mu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmadd_vv_f16m2_mu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmadd_vv_f16m2_mu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmadd.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmadd.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
// //
vfloat16m2_t test_vfmadd_vv_f16m2_mu(vbool8_t mask, vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) { vfloat16m2_t test_vfmadd_vv_f16m2_mu(vbool8_t mask, vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfmadd_vv_f16m2_mu(mask, vd, vs1, vs2, vl); return __riscv_vfmadd_vv_f16m2_mu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmadd_vf_f16m2_mu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmadd_vf_f16m2_mu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmadd.mask.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmadd.mask.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
// //
vfloat16m2_t test_vfmadd_vf_f16m2_mu(vbool8_t mask, vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) { vfloat16m2_t test_vfmadd_vf_f16m2_mu(vbool8_t mask, vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfmadd_vf_f16m2_mu(mask, vd, rs1, vs2, vl); return __riscv_vfmadd_vf_f16m2_mu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmadd_vv_f16m4_mu // CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmadd_vv_f16m4_mu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmadd.mask.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmadd.mask.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
// //
vfloat16m4_t test_vfmadd_vv_f16m4_mu(vbool4_t mask, vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) { vfloat16m4_t test_vfmadd_vv_f16m4_mu(vbool4_t mask, vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfmadd_vv_f16m4_mu(mask, vd, vs1, vs2, vl); return __riscv_vfmadd_vv_f16m4_mu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmadd_vf_f16m4_mu // CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmadd_vf_f16m4_mu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmadd.mask.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmadd.mask.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
// //
vfloat16m4_t test_vfmadd_vf_f16m4_mu(vbool4_t mask, vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) { vfloat16m4_t test_vfmadd_vf_f16m4_mu(vbool4_t mask, vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfmadd_vf_f16m4_mu(mask, vd, rs1, vs2, vl); return __riscv_vfmadd_vf_f16m4_mu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmadd_vv_f16m8_mu // CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmadd_vv_f16m8_mu
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmadd.mask.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmadd.mask.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
// //
vfloat16m8_t test_vfmadd_vv_f16m8_mu(vbool2_t mask, vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) { vfloat16m8_t test_vfmadd_vv_f16m8_mu(vbool2_t mask, vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfmadd_vv_f16m8_mu(mask, vd, vs1, vs2, vl); return __riscv_vfmadd_vv_f16m8_mu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmadd_vf_f16m8_mu // CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmadd_vf_f16m8_mu
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmadd.mask.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmadd.mask.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
// //
vfloat16m8_t test_vfmadd_vf_f16m8_mu(vbool2_t mask, vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) { vfloat16m8_t test_vfmadd_vf_f16m8_mu(vbool2_t mask, vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfmadd_vf_f16m8_mu(mask, vd, rs1, vs2, vl); return __riscv_vfmadd_vf_f16m8_mu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmadd_vv_f32mf2_mu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmadd_vv_f32mf2_mu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmadd.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmadd.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfmadd_vv_f32mf2_mu(vbool64_t mask, vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) { vfloat32mf2_t test_vfmadd_vv_f32mf2_mu(vbool64_t mask, vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfmadd_vv_f32mf2_mu(mask, vd, vs1, vs2, vl); return __riscv_vfmadd_vv_f32mf2_mu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmadd_vf_f32mf2_mu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmadd_vf_f32mf2_mu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmadd.mask.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmadd.mask.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfmadd_vf_f32mf2_mu(vbool64_t mask, vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) { vfloat32mf2_t test_vfmadd_vf_f32mf2_mu(vbool64_t mask, vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfmadd_vf_f32mf2_mu(mask, vd, rs1, vs2, vl); return __riscv_vfmadd_vf_f32mf2_mu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmadd_vv_f32m1_mu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmadd_vv_f32m1_mu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmadd.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmadd.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfmadd_vv_f32m1_mu(vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) { vfloat32m1_t test_vfmadd_vv_f32m1_mu(vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfmadd_vv_f32m1_mu(mask, vd, vs1, vs2, vl); return __riscv_vfmadd_vv_f32m1_mu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmadd_vf_f32m1_mu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmadd_vf_f32m1_mu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmadd.mask.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmadd.mask.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfmadd_vf_f32m1_mu(vbool32_t mask, vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) { vfloat32m1_t test_vfmadd_vf_f32m1_mu(vbool32_t mask, vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfmadd_vf_f32m1_mu(mask, vd, rs1, vs2, vl); return __riscv_vfmadd_vf_f32m1_mu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmadd_vv_f32m2_mu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmadd_vv_f32m2_mu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmadd.mask.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmadd.mask.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfmadd_vv_f32m2_mu(vbool16_t mask, vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) { vfloat32m2_t test_vfmadd_vv_f32m2_mu(vbool16_t mask, vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfmadd_vv_f32m2_mu(mask, vd, vs1, vs2, vl); return __riscv_vfmadd_vv_f32m2_mu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmadd_vf_f32m2_mu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmadd_vf_f32m2_mu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmadd.mask.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmadd.mask.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfmadd_vf_f32m2_mu(vbool16_t mask, vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) { vfloat32m2_t test_vfmadd_vf_f32m2_mu(vbool16_t mask, vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfmadd_vf_f32m2_mu(mask, vd, rs1, vs2, vl); return __riscv_vfmadd_vf_f32m2_mu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmadd_vv_f32m4_mu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmadd_vv_f32m4_mu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmadd.mask.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmadd.mask.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfmadd_vv_f32m4_mu(vbool8_t mask, vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) { vfloat32m4_t test_vfmadd_vv_f32m4_mu(vbool8_t mask, vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfmadd_vv_f32m4_mu(mask, vd, vs1, vs2, vl); return __riscv_vfmadd_vv_f32m4_mu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmadd_vf_f32m4_mu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmadd_vf_f32m4_mu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmadd.mask.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmadd.mask.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfmadd_vf_f32m4_mu(vbool8_t mask, vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) { vfloat32m4_t test_vfmadd_vf_f32m4_mu(vbool8_t mask, vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfmadd_vf_f32m4_mu(mask, vd, rs1, vs2, vl); return __riscv_vfmadd_vf_f32m4_mu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmadd_vv_f32m8_mu // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmadd_vv_f32m8_mu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmadd.mask.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmadd.mask.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfmadd_vv_f32m8_mu(vbool4_t mask, vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) { vfloat32m8_t test_vfmadd_vv_f32m8_mu(vbool4_t mask, vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfmadd_vv_f32m8_mu(mask, vd, vs1, vs2, vl); return __riscv_vfmadd_vv_f32m8_mu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmadd_vf_f32m8_mu // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmadd_vf_f32m8_mu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmadd.mask.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmadd.mask.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfmadd_vf_f32m8_mu(vbool4_t mask, vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) { vfloat32m8_t test_vfmadd_vf_f32m8_mu(vbool4_t mask, vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfmadd_vf_f32m8_mu(mask, vd, rs1, vs2, vl); return __riscv_vfmadd_vf_f32m8_mu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmadd_vv_f64m1_mu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmadd_vv_f64m1_mu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmadd.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmadd.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfmadd_vv_f64m1_mu(vbool64_t mask, vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) { vfloat64m1_t test_vfmadd_vv_f64m1_mu(vbool64_t mask, vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfmadd_vv_f64m1_mu(mask, vd, vs1, vs2, vl); return __riscv_vfmadd_vv_f64m1_mu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmadd_vf_f64m1_mu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmadd_vf_f64m1_mu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmadd.mask.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmadd.mask.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfmadd_vf_f64m1_mu(vbool64_t mask, vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) { vfloat64m1_t test_vfmadd_vf_f64m1_mu(vbool64_t mask, vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfmadd_vf_f64m1_mu(mask, vd, rs1, vs2, vl); return __riscv_vfmadd_vf_f64m1_mu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmadd_vv_f64m2_mu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmadd_vv_f64m2_mu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmadd.mask.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmadd.mask.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfmadd_vv_f64m2_mu(vbool32_t mask, vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) { vfloat64m2_t test_vfmadd_vv_f64m2_mu(vbool32_t mask, vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfmadd_vv_f64m2_mu(mask, vd, vs1, vs2, vl); return __riscv_vfmadd_vv_f64m2_mu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmadd_vf_f64m2_mu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmadd_vf_f64m2_mu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmadd.mask.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmadd.mask.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfmadd_vf_f64m2_mu(vbool32_t mask, vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) { vfloat64m2_t test_vfmadd_vf_f64m2_mu(vbool32_t mask, vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfmadd_vf_f64m2_mu(mask, vd, rs1, vs2, vl); return __riscv_vfmadd_vf_f64m2_mu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmadd_vv_f64m4_mu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmadd_vv_f64m4_mu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmadd.mask.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmadd.mask.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfmadd_vv_f64m4_mu(vbool16_t mask, vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) { vfloat64m4_t test_vfmadd_vv_f64m4_mu(vbool16_t mask, vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfmadd_vv_f64m4_mu(mask, vd, vs1, vs2, vl); return __riscv_vfmadd_vv_f64m4_mu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmadd_vf_f64m4_mu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmadd_vf_f64m4_mu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmadd.mask.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmadd.mask.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfmadd_vf_f64m4_mu(vbool16_t mask, vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) { vfloat64m4_t test_vfmadd_vf_f64m4_mu(vbool16_t mask, vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfmadd_vf_f64m4_mu(mask, vd, rs1, vs2, vl); return __riscv_vfmadd_vf_f64m4_mu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmadd_vv_f64m8_mu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmadd_vv_f64m8_mu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmadd.mask.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmadd.mask.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfmadd_vv_f64m8_mu(vbool8_t mask, vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) { vfloat64m8_t test_vfmadd_vv_f64m8_mu(vbool8_t mask, vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfmadd_vv_f64m8_mu(mask, vd, vs1, vs2, vl); return __riscv_vfmadd_vv_f64m8_mu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmadd_vf_f64m8_mu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmadd_vf_f64m8_mu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmadd.mask.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmadd.mask.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfmadd_vf_f64m8_mu(vbool8_t mask, vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) { vfloat64m8_t test_vfmadd_vf_f64m8_mu(vbool8_t mask, vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfmadd_vf_f64m8_mu(mask, vd, rs1, vs2, vl); return __riscv_vfmadd_vf_f64m8_mu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmadd_vv_f16mf4_rm_tu
// CHECK-RV64-SAME: (<vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmadd.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
//
vfloat16mf4_t test_vfmadd_vv_f16mf4_rm_tu(vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfmadd_vv_f16mf4_rm_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmadd_vf_f16mf4_rm_tu
// CHECK-RV64-SAME: (<vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmadd.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
//
vfloat16mf4_t test_vfmadd_vf_f16mf4_rm_tu(vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfmadd_vf_f16mf4_rm_tu(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmadd_vv_f16mf2_rm_tu
// CHECK-RV64-SAME: (<vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmadd.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
//
vfloat16mf2_t test_vfmadd_vv_f16mf2_rm_tu(vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfmadd_vv_f16mf2_rm_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmadd_vf_f16mf2_rm_tu
// CHECK-RV64-SAME: (<vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmadd.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
//
vfloat16mf2_t test_vfmadd_vf_f16mf2_rm_tu(vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfmadd_vf_f16mf2_rm_tu(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmadd_vv_f16m1_rm_tu
// CHECK-RV64-SAME: (<vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmadd.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfmadd_vv_f16m1_rm_tu(vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfmadd_vv_f16m1_rm_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmadd_vf_f16m1_rm_tu
// CHECK-RV64-SAME: (<vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmadd.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfmadd_vf_f16m1_rm_tu(vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfmadd_vf_f16m1_rm_tu(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmadd_vv_f16m2_rm_tu
// CHECK-RV64-SAME: (<vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmadd.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
//
vfloat16m2_t test_vfmadd_vv_f16m2_rm_tu(vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfmadd_vv_f16m2_rm_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmadd_vf_f16m2_rm_tu
// CHECK-RV64-SAME: (<vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmadd.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
//
vfloat16m2_t test_vfmadd_vf_f16m2_rm_tu(vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfmadd_vf_f16m2_rm_tu(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmadd_vv_f16m4_rm_tu
// CHECK-RV64-SAME: (<vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmadd.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
//
vfloat16m4_t test_vfmadd_vv_f16m4_rm_tu(vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfmadd_vv_f16m4_rm_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmadd_vf_f16m4_rm_tu
// CHECK-RV64-SAME: (<vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmadd.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
//
vfloat16m4_t test_vfmadd_vf_f16m4_rm_tu(vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfmadd_vf_f16m4_rm_tu(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmadd_vv_f16m8_rm_tu
// CHECK-RV64-SAME: (<vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmadd.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
//
vfloat16m8_t test_vfmadd_vv_f16m8_rm_tu(vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfmadd_vv_f16m8_rm_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmadd_vf_f16m8_rm_tu
// CHECK-RV64-SAME: (<vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmadd.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
//
vfloat16m8_t test_vfmadd_vf_f16m8_rm_tu(vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfmadd_vf_f16m8_rm_tu(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmadd_vv_f32mf2_rm_tu
// CHECK-RV64-SAME: (<vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmadd.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
//
vfloat32mf2_t test_vfmadd_vv_f32mf2_rm_tu(vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfmadd_vv_f32mf2_rm_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmadd_vf_f32mf2_rm_tu
// CHECK-RV64-SAME: (<vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmadd.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
//
vfloat32mf2_t test_vfmadd_vf_f32mf2_rm_tu(vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfmadd_vf_f32mf2_rm_tu(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmadd_vv_f32m1_rm_tu
// CHECK-RV64-SAME: (<vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmadd.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfmadd_vv_f32m1_rm_tu(vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfmadd_vv_f32m1_rm_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmadd_vf_f32m1_rm_tu
// CHECK-RV64-SAME: (<vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmadd.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfmadd_vf_f32m1_rm_tu(vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfmadd_vf_f32m1_rm_tu(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmadd_vv_f32m2_rm_tu
// CHECK-RV64-SAME: (<vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmadd.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
//
vfloat32m2_t test_vfmadd_vv_f32m2_rm_tu(vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfmadd_vv_f32m2_rm_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmadd_vf_f32m2_rm_tu
// CHECK-RV64-SAME: (<vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmadd.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
//
vfloat32m2_t test_vfmadd_vf_f32m2_rm_tu(vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfmadd_vf_f32m2_rm_tu(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmadd_vv_f32m4_rm_tu
// CHECK-RV64-SAME: (<vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmadd.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
//
vfloat32m4_t test_vfmadd_vv_f32m4_rm_tu(vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfmadd_vv_f32m4_rm_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmadd_vf_f32m4_rm_tu
// CHECK-RV64-SAME: (<vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmadd.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
//
vfloat32m4_t test_vfmadd_vf_f32m4_rm_tu(vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfmadd_vf_f32m4_rm_tu(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmadd_vv_f32m8_rm_tu
// CHECK-RV64-SAME: (<vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmadd.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
//
vfloat32m8_t test_vfmadd_vv_f32m8_rm_tu(vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfmadd_vv_f32m8_rm_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmadd_vf_f32m8_rm_tu
// CHECK-RV64-SAME: (<vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmadd.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
//
vfloat32m8_t test_vfmadd_vf_f32m8_rm_tu(vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfmadd_vf_f32m8_rm_tu(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmadd_vv_f64m1_rm_tu
// CHECK-RV64-SAME: (<vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmadd.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfmadd_vv_f64m1_rm_tu(vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfmadd_vv_f64m1_rm_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmadd_vf_f64m1_rm_tu
// CHECK-RV64-SAME: (<vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmadd.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfmadd_vf_f64m1_rm_tu(vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfmadd_vf_f64m1_rm_tu(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmadd_vv_f64m2_rm_tu
// CHECK-RV64-SAME: (<vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmadd.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
//
vfloat64m2_t test_vfmadd_vv_f64m2_rm_tu(vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfmadd_vv_f64m2_rm_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmadd_vf_f64m2_rm_tu
// CHECK-RV64-SAME: (<vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmadd.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
//
vfloat64m2_t test_vfmadd_vf_f64m2_rm_tu(vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfmadd_vf_f64m2_rm_tu(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmadd_vv_f64m4_rm_tu
// CHECK-RV64-SAME: (<vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmadd.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
//
vfloat64m4_t test_vfmadd_vv_f64m4_rm_tu(vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfmadd_vv_f64m4_rm_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmadd_vf_f64m4_rm_tu
// CHECK-RV64-SAME: (<vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmadd.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
//
vfloat64m4_t test_vfmadd_vf_f64m4_rm_tu(vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfmadd_vf_f64m4_rm_tu(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmadd_vv_f64m8_rm_tu
// CHECK-RV64-SAME: (<vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmadd.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
//
vfloat64m8_t test_vfmadd_vv_f64m8_rm_tu(vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfmadd_vv_f64m8_rm_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmadd_vf_f64m8_rm_tu
// CHECK-RV64-SAME: (<vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmadd.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
//
vfloat64m8_t test_vfmadd_vf_f64m8_rm_tu(vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfmadd_vf_f64m8_rm_tu(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmadd_vv_f16mf4_rm_tum
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmadd.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
//
vfloat16mf4_t test_vfmadd_vv_f16mf4_rm_tum(vbool64_t mask, vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfmadd_vv_f16mf4_rm_tum(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmadd_vf_f16mf4_rm_tum
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmadd.mask.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
//
vfloat16mf4_t test_vfmadd_vf_f16mf4_rm_tum(vbool64_t mask, vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfmadd_vf_f16mf4_rm_tum(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmadd_vv_f16mf2_rm_tum
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmadd.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
//
vfloat16mf2_t test_vfmadd_vv_f16mf2_rm_tum(vbool32_t mask, vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfmadd_vv_f16mf2_rm_tum(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmadd_vf_f16mf2_rm_tum
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmadd.mask.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
//
vfloat16mf2_t test_vfmadd_vf_f16mf2_rm_tum(vbool32_t mask, vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfmadd_vf_f16mf2_rm_tum(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmadd_vv_f16m1_rm_tum
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmadd.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfmadd_vv_f16m1_rm_tum(vbool16_t mask, vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfmadd_vv_f16m1_rm_tum(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmadd_vf_f16m1_rm_tum
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmadd.mask.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfmadd_vf_f16m1_rm_tum(vbool16_t mask, vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfmadd_vf_f16m1_rm_tum(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmadd_vv_f16m2_rm_tum
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmadd.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
//
vfloat16m2_t test_vfmadd_vv_f16m2_rm_tum(vbool8_t mask, vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfmadd_vv_f16m2_rm_tum(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmadd_vf_f16m2_rm_tum
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmadd.mask.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
//
vfloat16m2_t test_vfmadd_vf_f16m2_rm_tum(vbool8_t mask, vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfmadd_vf_f16m2_rm_tum(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmadd_vv_f16m4_rm_tum
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmadd.mask.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
//
vfloat16m4_t test_vfmadd_vv_f16m4_rm_tum(vbool4_t mask, vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfmadd_vv_f16m4_rm_tum(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmadd_vf_f16m4_rm_tum
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmadd.mask.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
//
vfloat16m4_t test_vfmadd_vf_f16m4_rm_tum(vbool4_t mask, vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfmadd_vf_f16m4_rm_tum(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmadd_vv_f16m8_rm_tum
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmadd.mask.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
//
vfloat16m8_t test_vfmadd_vv_f16m8_rm_tum(vbool2_t mask, vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfmadd_vv_f16m8_rm_tum(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmadd_vf_f16m8_rm_tum
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmadd.mask.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
//
vfloat16m8_t test_vfmadd_vf_f16m8_rm_tum(vbool2_t mask, vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfmadd_vf_f16m8_rm_tum(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmadd_vv_f32mf2_rm_tum
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmadd.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
//
vfloat32mf2_t test_vfmadd_vv_f32mf2_rm_tum(vbool64_t mask, vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfmadd_vv_f32mf2_rm_tum(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmadd_vf_f32mf2_rm_tum
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmadd.mask.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
//
vfloat32mf2_t test_vfmadd_vf_f32mf2_rm_tum(vbool64_t mask, vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfmadd_vf_f32mf2_rm_tum(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmadd_vv_f32m1_rm_tum
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmadd.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfmadd_vv_f32m1_rm_tum(vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfmadd_vv_f32m1_rm_tum(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmadd_vf_f32m1_rm_tum
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmadd.mask.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfmadd_vf_f32m1_rm_tum(vbool32_t mask, vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfmadd_vf_f32m1_rm_tum(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmadd_vv_f32m2_rm_tum
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmadd.mask.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
//
vfloat32m2_t test_vfmadd_vv_f32m2_rm_tum(vbool16_t mask, vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfmadd_vv_f32m2_rm_tum(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmadd_vf_f32m2_rm_tum
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmadd.mask.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
//
vfloat32m2_t test_vfmadd_vf_f32m2_rm_tum(vbool16_t mask, vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfmadd_vf_f32m2_rm_tum(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmadd_vv_f32m4_rm_tum
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmadd.mask.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
//
vfloat32m4_t test_vfmadd_vv_f32m4_rm_tum(vbool8_t mask, vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfmadd_vv_f32m4_rm_tum(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmadd_vf_f32m4_rm_tum
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmadd.mask.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
//
vfloat32m4_t test_vfmadd_vf_f32m4_rm_tum(vbool8_t mask, vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfmadd_vf_f32m4_rm_tum(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmadd_vv_f32m8_rm_tum
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmadd.mask.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
//
vfloat32m8_t test_vfmadd_vv_f32m8_rm_tum(vbool4_t mask, vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfmadd_vv_f32m8_rm_tum(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmadd_vf_f32m8_rm_tum
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmadd.mask.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
//
vfloat32m8_t test_vfmadd_vf_f32m8_rm_tum(vbool4_t mask, vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfmadd_vf_f32m8_rm_tum(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmadd_vv_f64m1_rm_tum
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmadd.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfmadd_vv_f64m1_rm_tum(vbool64_t mask, vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfmadd_vv_f64m1_rm_tum(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmadd_vf_f64m1_rm_tum
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmadd.mask.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfmadd_vf_f64m1_rm_tum(vbool64_t mask, vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfmadd_vf_f64m1_rm_tum(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmadd_vv_f64m2_rm_tum
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmadd.mask.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
//
vfloat64m2_t test_vfmadd_vv_f64m2_rm_tum(vbool32_t mask, vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfmadd_vv_f64m2_rm_tum(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmadd_vf_f64m2_rm_tum
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmadd.mask.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
//
vfloat64m2_t test_vfmadd_vf_f64m2_rm_tum(vbool32_t mask, vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfmadd_vf_f64m2_rm_tum(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmadd_vv_f64m4_rm_tum
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmadd.mask.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
//
vfloat64m4_t test_vfmadd_vv_f64m4_rm_tum(vbool16_t mask, vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfmadd_vv_f64m4_rm_tum(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmadd_vf_f64m4_rm_tum
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmadd.mask.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
//
vfloat64m4_t test_vfmadd_vf_f64m4_rm_tum(vbool16_t mask, vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfmadd_vf_f64m4_rm_tum(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmadd_vv_f64m8_rm_tum
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmadd.mask.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
//
vfloat64m8_t test_vfmadd_vv_f64m8_rm_tum(vbool8_t mask, vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfmadd_vv_f64m8_rm_tum(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmadd_vf_f64m8_rm_tum
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmadd.mask.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
//
vfloat64m8_t test_vfmadd_vf_f64m8_rm_tum(vbool8_t mask, vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfmadd_vf_f64m8_rm_tum(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmadd_vv_f16mf4_rm_tumu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmadd.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
//
vfloat16mf4_t test_vfmadd_vv_f16mf4_rm_tumu(vbool64_t mask, vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfmadd_vv_f16mf4_rm_tumu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmadd_vf_f16mf4_rm_tumu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmadd.mask.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
//
vfloat16mf4_t test_vfmadd_vf_f16mf4_rm_tumu(vbool64_t mask, vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfmadd_vf_f16mf4_rm_tumu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmadd_vv_f16mf2_rm_tumu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmadd.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
//
vfloat16mf2_t test_vfmadd_vv_f16mf2_rm_tumu(vbool32_t mask, vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfmadd_vv_f16mf2_rm_tumu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmadd_vf_f16mf2_rm_tumu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmadd.mask.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
//
vfloat16mf2_t test_vfmadd_vf_f16mf2_rm_tumu(vbool32_t mask, vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfmadd_vf_f16mf2_rm_tumu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmadd_vv_f16m1_rm_tumu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmadd.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfmadd_vv_f16m1_rm_tumu(vbool16_t mask, vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfmadd_vv_f16m1_rm_tumu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmadd_vf_f16m1_rm_tumu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmadd.mask.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfmadd_vf_f16m1_rm_tumu(vbool16_t mask, vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfmadd_vf_f16m1_rm_tumu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmadd_vv_f16m2_rm_tumu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmadd.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
//
vfloat16m2_t test_vfmadd_vv_f16m2_rm_tumu(vbool8_t mask, vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfmadd_vv_f16m2_rm_tumu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmadd_vf_f16m2_rm_tumu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmadd.mask.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
//
vfloat16m2_t test_vfmadd_vf_f16m2_rm_tumu(vbool8_t mask, vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfmadd_vf_f16m2_rm_tumu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmadd_vv_f16m4_rm_tumu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmadd.mask.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
//
vfloat16m4_t test_vfmadd_vv_f16m4_rm_tumu(vbool4_t mask, vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfmadd_vv_f16m4_rm_tumu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmadd_vf_f16m4_rm_tumu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmadd.mask.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
//
vfloat16m4_t test_vfmadd_vf_f16m4_rm_tumu(vbool4_t mask, vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfmadd_vf_f16m4_rm_tumu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmadd_vv_f16m8_rm_tumu
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmadd.mask.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
//
vfloat16m8_t test_vfmadd_vv_f16m8_rm_tumu(vbool2_t mask, vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfmadd_vv_f16m8_rm_tumu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmadd_vf_f16m8_rm_tumu
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmadd.mask.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
//
vfloat16m8_t test_vfmadd_vf_f16m8_rm_tumu(vbool2_t mask, vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfmadd_vf_f16m8_rm_tumu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmadd_vv_f32mf2_rm_tumu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmadd.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
//
vfloat32mf2_t test_vfmadd_vv_f32mf2_rm_tumu(vbool64_t mask, vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfmadd_vv_f32mf2_rm_tumu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmadd_vf_f32mf2_rm_tumu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmadd.mask.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
//
vfloat32mf2_t test_vfmadd_vf_f32mf2_rm_tumu(vbool64_t mask, vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfmadd_vf_f32mf2_rm_tumu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmadd_vv_f32m1_rm_tumu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmadd.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfmadd_vv_f32m1_rm_tumu(vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfmadd_vv_f32m1_rm_tumu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmadd_vf_f32m1_rm_tumu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmadd.mask.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfmadd_vf_f32m1_rm_tumu(vbool32_t mask, vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfmadd_vf_f32m1_rm_tumu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmadd_vv_f32m2_rm_tumu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmadd.mask.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
//
vfloat32m2_t test_vfmadd_vv_f32m2_rm_tumu(vbool16_t mask, vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfmadd_vv_f32m2_rm_tumu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmadd_vf_f32m2_rm_tumu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmadd.mask.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
//
vfloat32m2_t test_vfmadd_vf_f32m2_rm_tumu(vbool16_t mask, vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfmadd_vf_f32m2_rm_tumu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmadd_vv_f32m4_rm_tumu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmadd.mask.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
//
vfloat32m4_t test_vfmadd_vv_f32m4_rm_tumu(vbool8_t mask, vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfmadd_vv_f32m4_rm_tumu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmadd_vf_f32m4_rm_tumu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmadd.mask.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
//
vfloat32m4_t test_vfmadd_vf_f32m4_rm_tumu(vbool8_t mask, vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfmadd_vf_f32m4_rm_tumu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmadd_vv_f32m8_rm_tumu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmadd.mask.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
//
vfloat32m8_t test_vfmadd_vv_f32m8_rm_tumu(vbool4_t mask, vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfmadd_vv_f32m8_rm_tumu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmadd_vf_f32m8_rm_tumu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmadd.mask.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
//
vfloat32m8_t test_vfmadd_vf_f32m8_rm_tumu(vbool4_t mask, vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfmadd_vf_f32m8_rm_tumu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmadd_vv_f64m1_rm_tumu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmadd.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfmadd_vv_f64m1_rm_tumu(vbool64_t mask, vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfmadd_vv_f64m1_rm_tumu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmadd_vf_f64m1_rm_tumu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmadd.mask.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfmadd_vf_f64m1_rm_tumu(vbool64_t mask, vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfmadd_vf_f64m1_rm_tumu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmadd_vv_f64m2_rm_tumu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmadd.mask.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
//
vfloat64m2_t test_vfmadd_vv_f64m2_rm_tumu(vbool32_t mask, vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfmadd_vv_f64m2_rm_tumu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmadd_vf_f64m2_rm_tumu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmadd.mask.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
//
vfloat64m2_t test_vfmadd_vf_f64m2_rm_tumu(vbool32_t mask, vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfmadd_vf_f64m2_rm_tumu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmadd_vv_f64m4_rm_tumu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmadd.mask.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
//
vfloat64m4_t test_vfmadd_vv_f64m4_rm_tumu(vbool16_t mask, vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfmadd_vv_f64m4_rm_tumu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmadd_vf_f64m4_rm_tumu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmadd.mask.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
//
vfloat64m4_t test_vfmadd_vf_f64m4_rm_tumu(vbool16_t mask, vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfmadd_vf_f64m4_rm_tumu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmadd_vv_f64m8_rm_tumu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmadd.mask.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
//
vfloat64m8_t test_vfmadd_vv_f64m8_rm_tumu(vbool8_t mask, vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfmadd_vv_f64m8_rm_tumu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmadd_vf_f64m8_rm_tumu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmadd.mask.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
//
vfloat64m8_t test_vfmadd_vf_f64m8_rm_tumu(vbool8_t mask, vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfmadd_vf_f64m8_rm_tumu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmadd_vv_f16mf4_rm_mu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmadd.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
//
vfloat16mf4_t test_vfmadd_vv_f16mf4_rm_mu(vbool64_t mask, vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfmadd_vv_f16mf4_rm_mu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmadd_vf_f16mf4_rm_mu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmadd.mask.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
//
vfloat16mf4_t test_vfmadd_vf_f16mf4_rm_mu(vbool64_t mask, vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfmadd_vf_f16mf4_rm_mu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmadd_vv_f16mf2_rm_mu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmadd.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
//
vfloat16mf2_t test_vfmadd_vv_f16mf2_rm_mu(vbool32_t mask, vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfmadd_vv_f16mf2_rm_mu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmadd_vf_f16mf2_rm_mu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmadd.mask.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
//
vfloat16mf2_t test_vfmadd_vf_f16mf2_rm_mu(vbool32_t mask, vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfmadd_vf_f16mf2_rm_mu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmadd_vv_f16m1_rm_mu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmadd.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfmadd_vv_f16m1_rm_mu(vbool16_t mask, vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfmadd_vv_f16m1_rm_mu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmadd_vf_f16m1_rm_mu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmadd.mask.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfmadd_vf_f16m1_rm_mu(vbool16_t mask, vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfmadd_vf_f16m1_rm_mu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmadd_vv_f16m2_rm_mu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmadd.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
//
vfloat16m2_t test_vfmadd_vv_f16m2_rm_mu(vbool8_t mask, vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfmadd_vv_f16m2_rm_mu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmadd_vf_f16m2_rm_mu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmadd.mask.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
//
vfloat16m2_t test_vfmadd_vf_f16m2_rm_mu(vbool8_t mask, vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfmadd_vf_f16m2_rm_mu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmadd_vv_f16m4_rm_mu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmadd.mask.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
//
vfloat16m4_t test_vfmadd_vv_f16m4_rm_mu(vbool4_t mask, vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfmadd_vv_f16m4_rm_mu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmadd_vf_f16m4_rm_mu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmadd.mask.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
//
vfloat16m4_t test_vfmadd_vf_f16m4_rm_mu(vbool4_t mask, vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfmadd_vf_f16m4_rm_mu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmadd_vv_f16m8_rm_mu
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmadd.mask.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
//
vfloat16m8_t test_vfmadd_vv_f16m8_rm_mu(vbool2_t mask, vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfmadd_vv_f16m8_rm_mu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmadd_vf_f16m8_rm_mu
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmadd.mask.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
//
vfloat16m8_t test_vfmadd_vf_f16m8_rm_mu(vbool2_t mask, vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfmadd_vf_f16m8_rm_mu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmadd_vv_f32mf2_rm_mu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmadd.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
//
vfloat32mf2_t test_vfmadd_vv_f32mf2_rm_mu(vbool64_t mask, vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfmadd_vv_f32mf2_rm_mu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmadd_vf_f32mf2_rm_mu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmadd.mask.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
//
vfloat32mf2_t test_vfmadd_vf_f32mf2_rm_mu(vbool64_t mask, vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfmadd_vf_f32mf2_rm_mu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmadd_vv_f32m1_rm_mu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmadd.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfmadd_vv_f32m1_rm_mu(vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfmadd_vv_f32m1_rm_mu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmadd_vf_f32m1_rm_mu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmadd.mask.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfmadd_vf_f32m1_rm_mu(vbool32_t mask, vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfmadd_vf_f32m1_rm_mu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmadd_vv_f32m2_rm_mu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmadd.mask.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
//
vfloat32m2_t test_vfmadd_vv_f32m2_rm_mu(vbool16_t mask, vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfmadd_vv_f32m2_rm_mu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmadd_vf_f32m2_rm_mu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmadd.mask.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
//
vfloat32m2_t test_vfmadd_vf_f32m2_rm_mu(vbool16_t mask, vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfmadd_vf_f32m2_rm_mu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmadd_vv_f32m4_rm_mu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmadd.mask.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
//
vfloat32m4_t test_vfmadd_vv_f32m4_rm_mu(vbool8_t mask, vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfmadd_vv_f32m4_rm_mu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmadd_vf_f32m4_rm_mu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmadd.mask.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
//
vfloat32m4_t test_vfmadd_vf_f32m4_rm_mu(vbool8_t mask, vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfmadd_vf_f32m4_rm_mu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmadd_vv_f32m8_rm_mu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmadd.mask.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
//
vfloat32m8_t test_vfmadd_vv_f32m8_rm_mu(vbool4_t mask, vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfmadd_vv_f32m8_rm_mu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmadd_vf_f32m8_rm_mu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmadd.mask.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
//
vfloat32m8_t test_vfmadd_vf_f32m8_rm_mu(vbool4_t mask, vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfmadd_vf_f32m8_rm_mu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmadd_vv_f64m1_rm_mu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmadd.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfmadd_vv_f64m1_rm_mu(vbool64_t mask, vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfmadd_vv_f64m1_rm_mu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmadd_vf_f64m1_rm_mu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmadd.mask.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfmadd_vf_f64m1_rm_mu(vbool64_t mask, vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfmadd_vf_f64m1_rm_mu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmadd_vv_f64m2_rm_mu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmadd.mask.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
//
vfloat64m2_t test_vfmadd_vv_f64m2_rm_mu(vbool32_t mask, vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfmadd_vv_f64m2_rm_mu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmadd_vf_f64m2_rm_mu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmadd.mask.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
//
vfloat64m2_t test_vfmadd_vf_f64m2_rm_mu(vbool32_t mask, vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfmadd_vf_f64m2_rm_mu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmadd_vv_f64m4_rm_mu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmadd.mask.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
//
vfloat64m4_t test_vfmadd_vv_f64m4_rm_mu(vbool16_t mask, vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfmadd_vv_f64m4_rm_mu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmadd_vf_f64m4_rm_mu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmadd.mask.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
//
vfloat64m4_t test_vfmadd_vf_f64m4_rm_mu(vbool16_t mask, vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfmadd_vf_f64m4_rm_mu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmadd_vv_f64m8_rm_mu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmadd.mask.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
//
vfloat64m8_t test_vfmadd_vv_f64m8_rm_mu(vbool8_t mask, vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfmadd_vv_f64m8_rm_mu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmadd_vf_f64m8_rm_mu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmadd.mask.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
//
vfloat64m8_t test_vfmadd_vf_f64m8_rm_mu(vbool8_t mask, vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfmadd_vf_f64m8_rm_mu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}

clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmsac.c

// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target // REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh \ // RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh \
// RUN: -target-feature +experimental-zvfh -disable-O0-optnone \ // RUN: -target-feature +experimental-zvfh -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ // RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s // RUN: FileCheck --check-prefix=CHECK-RV64 %s
#include <riscv_vector.h> #include <riscv_vector.h>
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmsac_vv_f16mf4_tu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmsac_vv_f16mf4_tu
// CHECK-RV64-SAME: (<vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK-RV64-SAME: (<vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmsac.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmsac.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
// //
vfloat16mf4_t test_vfmsac_vv_f16mf4_tu(vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) { vfloat16mf4_t test_vfmsac_vv_f16mf4_tu(vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfmsac_vv_f16mf4_tu(vd, vs1, vs2, vl); return __riscv_vfmsac_vv_f16mf4_tu(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmsac_vf_f16mf4_tu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmsac_vf_f16mf4_tu
// CHECK-RV64-SAME: (<vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmsac.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmsac.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
// //
vfloat16mf4_t test_vfmsac_vf_f16mf4_tu(vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) { vfloat16mf4_t test_vfmsac_vf_f16mf4_tu(vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfmsac_vf_f16mf4_tu(vd, rs1, vs2, vl); return __riscv_vfmsac_vf_f16mf4_tu(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmsac_vv_f16mf2_tu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmsac_vv_f16mf2_tu
// CHECK-RV64-SAME: (<vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmsac.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmsac.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
// //
vfloat16mf2_t test_vfmsac_vv_f16mf2_tu(vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) { vfloat16mf2_t test_vfmsac_vv_f16mf2_tu(vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfmsac_vv_f16mf2_tu(vd, vs1, vs2, vl); return __riscv_vfmsac_vv_f16mf2_tu(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmsac_vf_f16mf2_tu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmsac_vf_f16mf2_tu
// CHECK-RV64-SAME: (<vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmsac.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmsac.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
// //
vfloat16mf2_t test_vfmsac_vf_f16mf2_tu(vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) { vfloat16mf2_t test_vfmsac_vf_f16mf2_tu(vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfmsac_vf_f16mf2_tu(vd, rs1, vs2, vl); return __riscv_vfmsac_vf_f16mf2_tu(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmsac_vv_f16m1_tu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmsac_vv_f16m1_tu
// CHECK-RV64-SAME: (<vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmsac.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmsac.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
// //
vfloat16m1_t test_vfmsac_vv_f16m1_tu(vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) { vfloat16m1_t test_vfmsac_vv_f16m1_tu(vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfmsac_vv_f16m1_tu(vd, vs1, vs2, vl); return __riscv_vfmsac_vv_f16m1_tu(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmsac_vf_f16m1_tu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmsac_vf_f16m1_tu
// CHECK-RV64-SAME: (<vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmsac.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmsac.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
// //
vfloat16m1_t test_vfmsac_vf_f16m1_tu(vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) { vfloat16m1_t test_vfmsac_vf_f16m1_tu(vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfmsac_vf_f16m1_tu(vd, rs1, vs2, vl); return __riscv_vfmsac_vf_f16m1_tu(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmsac_vv_f16m2_tu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmsac_vv_f16m2_tu
// CHECK-RV64-SAME: (<vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmsac.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmsac.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
// //
vfloat16m2_t test_vfmsac_vv_f16m2_tu(vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) { vfloat16m2_t test_vfmsac_vv_f16m2_tu(vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfmsac_vv_f16m2_tu(vd, vs1, vs2, vl); return __riscv_vfmsac_vv_f16m2_tu(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmsac_vf_f16m2_tu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmsac_vf_f16m2_tu
// CHECK-RV64-SAME: (<vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmsac.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmsac.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
// //
vfloat16m2_t test_vfmsac_vf_f16m2_tu(vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) { vfloat16m2_t test_vfmsac_vf_f16m2_tu(vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfmsac_vf_f16m2_tu(vd, rs1, vs2, vl); return __riscv_vfmsac_vf_f16m2_tu(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmsac_vv_f16m4_tu // CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmsac_vv_f16m4_tu
// CHECK-RV64-SAME: (<vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmsac.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmsac.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
// //
vfloat16m4_t test_vfmsac_vv_f16m4_tu(vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) { vfloat16m4_t test_vfmsac_vv_f16m4_tu(vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfmsac_vv_f16m4_tu(vd, vs1, vs2, vl); return __riscv_vfmsac_vv_f16m4_tu(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmsac_vf_f16m4_tu // CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmsac_vf_f16m4_tu
// CHECK-RV64-SAME: (<vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmsac.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmsac.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
// //
vfloat16m4_t test_vfmsac_vf_f16m4_tu(vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) { vfloat16m4_t test_vfmsac_vf_f16m4_tu(vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfmsac_vf_f16m4_tu(vd, rs1, vs2, vl); return __riscv_vfmsac_vf_f16m4_tu(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmsac_vv_f16m8_tu // CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmsac_vv_f16m8_tu
// CHECK-RV64-SAME: (<vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmsac.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmsac.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
// //
vfloat16m8_t test_vfmsac_vv_f16m8_tu(vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) { vfloat16m8_t test_vfmsac_vv_f16m8_tu(vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfmsac_vv_f16m8_tu(vd, vs1, vs2, vl); return __riscv_vfmsac_vv_f16m8_tu(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmsac_vf_f16m8_tu // CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmsac_vf_f16m8_tu
// CHECK-RV64-SAME: (<vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmsac.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmsac.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
// //
vfloat16m8_t test_vfmsac_vf_f16m8_tu(vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) { vfloat16m8_t test_vfmsac_vf_f16m8_tu(vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfmsac_vf_f16m8_tu(vd, rs1, vs2, vl); return __riscv_vfmsac_vf_f16m8_tu(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmsac_vv_f32mf2_tu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmsac_vv_f32mf2_tu
// CHECK-RV64-SAME: (<vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmsac.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmsac.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfmsac_vv_f32mf2_tu(vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) { vfloat32mf2_t test_vfmsac_vv_f32mf2_tu(vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfmsac_vv_f32mf2_tu(vd, vs1, vs2, vl); return __riscv_vfmsac_vv_f32mf2_tu(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmsac_vf_f32mf2_tu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmsac_vf_f32mf2_tu
// CHECK-RV64-SAME: (<vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmsac.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmsac.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfmsac_vf_f32mf2_tu(vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) { vfloat32mf2_t test_vfmsac_vf_f32mf2_tu(vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfmsac_vf_f32mf2_tu(vd, rs1, vs2, vl); return __riscv_vfmsac_vf_f32mf2_tu(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmsac_vv_f32m1_tu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmsac_vv_f32m1_tu
// CHECK-RV64-SAME: (<vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmsac.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmsac.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfmsac_vv_f32m1_tu(vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) { vfloat32m1_t test_vfmsac_vv_f32m1_tu(vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfmsac_vv_f32m1_tu(vd, vs1, vs2, vl); return __riscv_vfmsac_vv_f32m1_tu(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmsac_vf_f32m1_tu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmsac_vf_f32m1_tu
// CHECK-RV64-SAME: (<vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmsac.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmsac.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfmsac_vf_f32m1_tu(vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) { vfloat32m1_t test_vfmsac_vf_f32m1_tu(vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfmsac_vf_f32m1_tu(vd, rs1, vs2, vl); return __riscv_vfmsac_vf_f32m1_tu(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmsac_vv_f32m2_tu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmsac_vv_f32m2_tu
// CHECK-RV64-SAME: (<vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmsac.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmsac.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfmsac_vv_f32m2_tu(vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) { vfloat32m2_t test_vfmsac_vv_f32m2_tu(vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfmsac_vv_f32m2_tu(vd, vs1, vs2, vl); return __riscv_vfmsac_vv_f32m2_tu(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmsac_vf_f32m2_tu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmsac_vf_f32m2_tu
// CHECK-RV64-SAME: (<vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmsac.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmsac.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfmsac_vf_f32m2_tu(vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) { vfloat32m2_t test_vfmsac_vf_f32m2_tu(vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfmsac_vf_f32m2_tu(vd, rs1, vs2, vl); return __riscv_vfmsac_vf_f32m2_tu(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmsac_vv_f32m4_tu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmsac_vv_f32m4_tu
// CHECK-RV64-SAME: (<vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmsac.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmsac.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfmsac_vv_f32m4_tu(vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) { vfloat32m4_t test_vfmsac_vv_f32m4_tu(vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfmsac_vv_f32m4_tu(vd, vs1, vs2, vl); return __riscv_vfmsac_vv_f32m4_tu(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmsac_vf_f32m4_tu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmsac_vf_f32m4_tu
// CHECK-RV64-SAME: (<vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmsac.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmsac.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfmsac_vf_f32m4_tu(vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) { vfloat32m4_t test_vfmsac_vf_f32m4_tu(vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfmsac_vf_f32m4_tu(vd, rs1, vs2, vl); return __riscv_vfmsac_vf_f32m4_tu(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmsac_vv_f32m8_tu // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmsac_vv_f32m8_tu
// CHECK-RV64-SAME: (<vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmsac.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmsac.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfmsac_vv_f32m8_tu(vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) { vfloat32m8_t test_vfmsac_vv_f32m8_tu(vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfmsac_vv_f32m8_tu(vd, vs1, vs2, vl); return __riscv_vfmsac_vv_f32m8_tu(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmsac_vf_f32m8_tu // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmsac_vf_f32m8_tu
// CHECK-RV64-SAME: (<vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmsac.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmsac.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfmsac_vf_f32m8_tu(vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) { vfloat32m8_t test_vfmsac_vf_f32m8_tu(vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfmsac_vf_f32m8_tu(vd, rs1, vs2, vl); return __riscv_vfmsac_vf_f32m8_tu(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmsac_vv_f64m1_tu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmsac_vv_f64m1_tu
// CHECK-RV64-SAME: (<vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmsac.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmsac.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfmsac_vv_f64m1_tu(vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) { vfloat64m1_t test_vfmsac_vv_f64m1_tu(vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfmsac_vv_f64m1_tu(vd, vs1, vs2, vl); return __riscv_vfmsac_vv_f64m1_tu(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmsac_vf_f64m1_tu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmsac_vf_f64m1_tu
// CHECK-RV64-SAME: (<vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmsac.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmsac.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfmsac_vf_f64m1_tu(vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) { vfloat64m1_t test_vfmsac_vf_f64m1_tu(vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfmsac_vf_f64m1_tu(vd, rs1, vs2, vl); return __riscv_vfmsac_vf_f64m1_tu(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmsac_vv_f64m2_tu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmsac_vv_f64m2_tu
// CHECK-RV64-SAME: (<vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmsac.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmsac.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfmsac_vv_f64m2_tu(vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) { vfloat64m2_t test_vfmsac_vv_f64m2_tu(vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfmsac_vv_f64m2_tu(vd, vs1, vs2, vl); return __riscv_vfmsac_vv_f64m2_tu(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmsac_vf_f64m2_tu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmsac_vf_f64m2_tu
// CHECK-RV64-SAME: (<vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmsac.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmsac.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfmsac_vf_f64m2_tu(vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) { vfloat64m2_t test_vfmsac_vf_f64m2_tu(vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfmsac_vf_f64m2_tu(vd, rs1, vs2, vl); return __riscv_vfmsac_vf_f64m2_tu(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmsac_vv_f64m4_tu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmsac_vv_f64m4_tu
// CHECK-RV64-SAME: (<vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmsac.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmsac.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfmsac_vv_f64m4_tu(vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) { vfloat64m4_t test_vfmsac_vv_f64m4_tu(vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfmsac_vv_f64m4_tu(vd, vs1, vs2, vl); return __riscv_vfmsac_vv_f64m4_tu(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmsac_vf_f64m4_tu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmsac_vf_f64m4_tu
// CHECK-RV64-SAME: (<vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmsac.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmsac.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfmsac_vf_f64m4_tu(vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) { vfloat64m4_t test_vfmsac_vf_f64m4_tu(vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfmsac_vf_f64m4_tu(vd, rs1, vs2, vl); return __riscv_vfmsac_vf_f64m4_tu(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmsac_vv_f64m8_tu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmsac_vv_f64m8_tu
// CHECK-RV64-SAME: (<vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmsac.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmsac.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfmsac_vv_f64m8_tu(vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) { vfloat64m8_t test_vfmsac_vv_f64m8_tu(vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfmsac_vv_f64m8_tu(vd, vs1, vs2, vl); return __riscv_vfmsac_vv_f64m8_tu(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmsac_vf_f64m8_tu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmsac_vf_f64m8_tu
// CHECK-RV64-SAME: (<vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmsac.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmsac.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfmsac_vf_f64m8_tu(vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) { vfloat64m8_t test_vfmsac_vf_f64m8_tu(vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfmsac_vf_f64m8_tu(vd, rs1, vs2, vl); return __riscv_vfmsac_vf_f64m8_tu(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmsac_vv_f16mf4_tum // CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmsac_vv_f16mf4_tum
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmsac.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmsac.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
// //
vfloat16mf4_t test_vfmsac_vv_f16mf4_tum(vbool64_t mask, vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) { vfloat16mf4_t test_vfmsac_vv_f16mf4_tum(vbool64_t mask, vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfmsac_vv_f16mf4_tum(mask, vd, vs1, vs2, vl); return __riscv_vfmsac_vv_f16mf4_tum(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmsac_vf_f16mf4_tum // CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmsac_vf_f16mf4_tum
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmsac.mask.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmsac.mask.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
// //
vfloat16mf4_t test_vfmsac_vf_f16mf4_tum(vbool64_t mask, vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) { vfloat16mf4_t test_vfmsac_vf_f16mf4_tum(vbool64_t mask, vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfmsac_vf_f16mf4_tum(mask, vd, rs1, vs2, vl); return __riscv_vfmsac_vf_f16mf4_tum(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmsac_vv_f16mf2_tum // CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmsac_vv_f16mf2_tum
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmsac.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmsac.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
// //
vfloat16mf2_t test_vfmsac_vv_f16mf2_tum(vbool32_t mask, vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) { vfloat16mf2_t test_vfmsac_vv_f16mf2_tum(vbool32_t mask, vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfmsac_vv_f16mf2_tum(mask, vd, vs1, vs2, vl); return __riscv_vfmsac_vv_f16mf2_tum(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmsac_vf_f16mf2_tum // CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmsac_vf_f16mf2_tum
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmsac.mask.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmsac.mask.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
// //
vfloat16mf2_t test_vfmsac_vf_f16mf2_tum(vbool32_t mask, vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) { vfloat16mf2_t test_vfmsac_vf_f16mf2_tum(vbool32_t mask, vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfmsac_vf_f16mf2_tum(mask, vd, rs1, vs2, vl); return __riscv_vfmsac_vf_f16mf2_tum(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmsac_vv_f16m1_tum // CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmsac_vv_f16m1_tum
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmsac.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmsac.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
// //
vfloat16m1_t test_vfmsac_vv_f16m1_tum(vbool16_t mask, vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) { vfloat16m1_t test_vfmsac_vv_f16m1_tum(vbool16_t mask, vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfmsac_vv_f16m1_tum(mask, vd, vs1, vs2, vl); return __riscv_vfmsac_vv_f16m1_tum(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmsac_vf_f16m1_tum // CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmsac_vf_f16m1_tum
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmsac.mask.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmsac.mask.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
// //
vfloat16m1_t test_vfmsac_vf_f16m1_tum(vbool16_t mask, vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) { vfloat16m1_t test_vfmsac_vf_f16m1_tum(vbool16_t mask, vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfmsac_vf_f16m1_tum(mask, vd, rs1, vs2, vl); return __riscv_vfmsac_vf_f16m1_tum(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmsac_vv_f16m2_tum // CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmsac_vv_f16m2_tum
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmsac.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmsac.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
// //
vfloat16m2_t test_vfmsac_vv_f16m2_tum(vbool8_t mask, vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) { vfloat16m2_t test_vfmsac_vv_f16m2_tum(vbool8_t mask, vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfmsac_vv_f16m2_tum(mask, vd, vs1, vs2, vl); return __riscv_vfmsac_vv_f16m2_tum(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmsac_vf_f16m2_tum // CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmsac_vf_f16m2_tum
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmsac.mask.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmsac.mask.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
// //
vfloat16m2_t test_vfmsac_vf_f16m2_tum(vbool8_t mask, vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) { vfloat16m2_t test_vfmsac_vf_f16m2_tum(vbool8_t mask, vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfmsac_vf_f16m2_tum(mask, vd, rs1, vs2, vl); return __riscv_vfmsac_vf_f16m2_tum(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmsac_vv_f16m4_tum // CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmsac_vv_f16m4_tum
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmsac.mask.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmsac.mask.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
// //
vfloat16m4_t test_vfmsac_vv_f16m4_tum(vbool4_t mask, vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) { vfloat16m4_t test_vfmsac_vv_f16m4_tum(vbool4_t mask, vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfmsac_vv_f16m4_tum(mask, vd, vs1, vs2, vl); return __riscv_vfmsac_vv_f16m4_tum(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmsac_vf_f16m4_tum // CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmsac_vf_f16m4_tum
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmsac.mask.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmsac.mask.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
// //
vfloat16m4_t test_vfmsac_vf_f16m4_tum(vbool4_t mask, vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) { vfloat16m4_t test_vfmsac_vf_f16m4_tum(vbool4_t mask, vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfmsac_vf_f16m4_tum(mask, vd, rs1, vs2, vl); return __riscv_vfmsac_vf_f16m4_tum(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmsac_vv_f16m8_tum // CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmsac_vv_f16m8_tum
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmsac.mask.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmsac.mask.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
// //
vfloat16m8_t test_vfmsac_vv_f16m8_tum(vbool2_t mask, vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) { vfloat16m8_t test_vfmsac_vv_f16m8_tum(vbool2_t mask, vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfmsac_vv_f16m8_tum(mask, vd, vs1, vs2, vl); return __riscv_vfmsac_vv_f16m8_tum(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmsac_vf_f16m8_tum // CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmsac_vf_f16m8_tum
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmsac.mask.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmsac.mask.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
// //
vfloat16m8_t test_vfmsac_vf_f16m8_tum(vbool2_t mask, vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) { vfloat16m8_t test_vfmsac_vf_f16m8_tum(vbool2_t mask, vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfmsac_vf_f16m8_tum(mask, vd, rs1, vs2, vl); return __riscv_vfmsac_vf_f16m8_tum(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmsac_vv_f32mf2_tum // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmsac_vv_f32mf2_tum
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmsac.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmsac.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfmsac_vv_f32mf2_tum(vbool64_t mask, vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) { vfloat32mf2_t test_vfmsac_vv_f32mf2_tum(vbool64_t mask, vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfmsac_vv_f32mf2_tum(mask, vd, vs1, vs2, vl); return __riscv_vfmsac_vv_f32mf2_tum(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmsac_vf_f32mf2_tum // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmsac_vf_f32mf2_tum
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmsac.mask.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmsac.mask.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfmsac_vf_f32mf2_tum(vbool64_t mask, vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) { vfloat32mf2_t test_vfmsac_vf_f32mf2_tum(vbool64_t mask, vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfmsac_vf_f32mf2_tum(mask, vd, rs1, vs2, vl); return __riscv_vfmsac_vf_f32mf2_tum(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmsac_vv_f32m1_tum // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmsac_vv_f32m1_tum
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmsac.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmsac.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfmsac_vv_f32m1_tum(vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) { vfloat32m1_t test_vfmsac_vv_f32m1_tum(vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfmsac_vv_f32m1_tum(mask, vd, vs1, vs2, vl); return __riscv_vfmsac_vv_f32m1_tum(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmsac_vf_f32m1_tum // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmsac_vf_f32m1_tum
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmsac.mask.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmsac.mask.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfmsac_vf_f32m1_tum(vbool32_t mask, vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) { vfloat32m1_t test_vfmsac_vf_f32m1_tum(vbool32_t mask, vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfmsac_vf_f32m1_tum(mask, vd, rs1, vs2, vl); return __riscv_vfmsac_vf_f32m1_tum(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmsac_vv_f32m2_tum // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmsac_vv_f32m2_tum
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmsac.mask.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmsac.mask.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfmsac_vv_f32m2_tum(vbool16_t mask, vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) { vfloat32m2_t test_vfmsac_vv_f32m2_tum(vbool16_t mask, vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfmsac_vv_f32m2_tum(mask, vd, vs1, vs2, vl); return __riscv_vfmsac_vv_f32m2_tum(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmsac_vf_f32m2_tum // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmsac_vf_f32m2_tum
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmsac.mask.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmsac.mask.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfmsac_vf_f32m2_tum(vbool16_t mask, vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) { vfloat32m2_t test_vfmsac_vf_f32m2_tum(vbool16_t mask, vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfmsac_vf_f32m2_tum(mask, vd, rs1, vs2, vl); return __riscv_vfmsac_vf_f32m2_tum(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmsac_vv_f32m4_tum // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmsac_vv_f32m4_tum
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmsac.mask.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmsac.mask.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfmsac_vv_f32m4_tum(vbool8_t mask, vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) { vfloat32m4_t test_vfmsac_vv_f32m4_tum(vbool8_t mask, vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfmsac_vv_f32m4_tum(mask, vd, vs1, vs2, vl); return __riscv_vfmsac_vv_f32m4_tum(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmsac_vf_f32m4_tum // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmsac_vf_f32m4_tum
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmsac.mask.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmsac.mask.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfmsac_vf_f32m4_tum(vbool8_t mask, vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) { vfloat32m4_t test_vfmsac_vf_f32m4_tum(vbool8_t mask, vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfmsac_vf_f32m4_tum(mask, vd, rs1, vs2, vl); return __riscv_vfmsac_vf_f32m4_tum(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmsac_vv_f32m8_tum // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmsac_vv_f32m8_tum
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmsac.mask.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmsac.mask.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfmsac_vv_f32m8_tum(vbool4_t mask, vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) { vfloat32m8_t test_vfmsac_vv_f32m8_tum(vbool4_t mask, vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfmsac_vv_f32m8_tum(mask, vd, vs1, vs2, vl); return __riscv_vfmsac_vv_f32m8_tum(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmsac_vf_f32m8_tum // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmsac_vf_f32m8_tum
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmsac.mask.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmsac.mask.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfmsac_vf_f32m8_tum(vbool4_t mask, vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) { vfloat32m8_t test_vfmsac_vf_f32m8_tum(vbool4_t mask, vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfmsac_vf_f32m8_tum(mask, vd, rs1, vs2, vl); return __riscv_vfmsac_vf_f32m8_tum(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmsac_vv_f64m1_tum // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmsac_vv_f64m1_tum
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmsac.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmsac.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfmsac_vv_f64m1_tum(vbool64_t mask, vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) { vfloat64m1_t test_vfmsac_vv_f64m1_tum(vbool64_t mask, vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfmsac_vv_f64m1_tum(mask, vd, vs1, vs2, vl); return __riscv_vfmsac_vv_f64m1_tum(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmsac_vf_f64m1_tum // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmsac_vf_f64m1_tum
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmsac.mask.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmsac.mask.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfmsac_vf_f64m1_tum(vbool64_t mask, vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) { vfloat64m1_t test_vfmsac_vf_f64m1_tum(vbool64_t mask, vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfmsac_vf_f64m1_tum(mask, vd, rs1, vs2, vl); return __riscv_vfmsac_vf_f64m1_tum(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmsac_vv_f64m2_tum // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmsac_vv_f64m2_tum
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmsac.mask.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmsac.mask.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfmsac_vv_f64m2_tum(vbool32_t mask, vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) { vfloat64m2_t test_vfmsac_vv_f64m2_tum(vbool32_t mask, vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfmsac_vv_f64m2_tum(mask, vd, vs1, vs2, vl); return __riscv_vfmsac_vv_f64m2_tum(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmsac_vf_f64m2_tum // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmsac_vf_f64m2_tum
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmsac.mask.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmsac.mask.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfmsac_vf_f64m2_tum(vbool32_t mask, vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) { vfloat64m2_t test_vfmsac_vf_f64m2_tum(vbool32_t mask, vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfmsac_vf_f64m2_tum(mask, vd, rs1, vs2, vl); return __riscv_vfmsac_vf_f64m2_tum(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmsac_vv_f64m4_tum // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmsac_vv_f64m4_tum
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmsac.mask.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmsac.mask.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfmsac_vv_f64m4_tum(vbool16_t mask, vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) { vfloat64m4_t test_vfmsac_vv_f64m4_tum(vbool16_t mask, vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfmsac_vv_f64m4_tum(mask, vd, vs1, vs2, vl); return __riscv_vfmsac_vv_f64m4_tum(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmsac_vf_f64m4_tum // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmsac_vf_f64m4_tum
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmsac.mask.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmsac.mask.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfmsac_vf_f64m4_tum(vbool16_t mask, vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) { vfloat64m4_t test_vfmsac_vf_f64m4_tum(vbool16_t mask, vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfmsac_vf_f64m4_tum(mask, vd, rs1, vs2, vl); return __riscv_vfmsac_vf_f64m4_tum(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmsac_vv_f64m8_tum // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmsac_vv_f64m8_tum
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmsac.mask.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmsac.mask.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfmsac_vv_f64m8_tum(vbool8_t mask, vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) { vfloat64m8_t test_vfmsac_vv_f64m8_tum(vbool8_t mask, vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfmsac_vv_f64m8_tum(mask, vd, vs1, vs2, vl); return __riscv_vfmsac_vv_f64m8_tum(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmsac_vf_f64m8_tum // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmsac_vf_f64m8_tum
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmsac.mask.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmsac.mask.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfmsac_vf_f64m8_tum(vbool8_t mask, vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) { vfloat64m8_t test_vfmsac_vf_f64m8_tum(vbool8_t mask, vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfmsac_vf_f64m8_tum(mask, vd, rs1, vs2, vl); return __riscv_vfmsac_vf_f64m8_tum(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmsac_vv_f16mf4_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmsac_vv_f16mf4_tumu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmsac.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmsac.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
// //
vfloat16mf4_t test_vfmsac_vv_f16mf4_tumu(vbool64_t mask, vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) { vfloat16mf4_t test_vfmsac_vv_f16mf4_tumu(vbool64_t mask, vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfmsac_vv_f16mf4_tumu(mask, vd, vs1, vs2, vl); return __riscv_vfmsac_vv_f16mf4_tumu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmsac_vf_f16mf4_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmsac_vf_f16mf4_tumu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmsac.mask.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmsac.mask.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
// //
vfloat16mf4_t test_vfmsac_vf_f16mf4_tumu(vbool64_t mask, vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) { vfloat16mf4_t test_vfmsac_vf_f16mf4_tumu(vbool64_t mask, vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfmsac_vf_f16mf4_tumu(mask, vd, rs1, vs2, vl); return __riscv_vfmsac_vf_f16mf4_tumu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmsac_vv_f16mf2_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmsac_vv_f16mf2_tumu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmsac.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmsac.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
// //
vfloat16mf2_t test_vfmsac_vv_f16mf2_tumu(vbool32_t mask, vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) { vfloat16mf2_t test_vfmsac_vv_f16mf2_tumu(vbool32_t mask, vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfmsac_vv_f16mf2_tumu(mask, vd, vs1, vs2, vl); return __riscv_vfmsac_vv_f16mf2_tumu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmsac_vf_f16mf2_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmsac_vf_f16mf2_tumu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmsac.mask.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmsac.mask.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
// //
vfloat16mf2_t test_vfmsac_vf_f16mf2_tumu(vbool32_t mask, vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) { vfloat16mf2_t test_vfmsac_vf_f16mf2_tumu(vbool32_t mask, vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfmsac_vf_f16mf2_tumu(mask, vd, rs1, vs2, vl); return __riscv_vfmsac_vf_f16mf2_tumu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmsac_vv_f16m1_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmsac_vv_f16m1_tumu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmsac.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmsac.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
// //
vfloat16m1_t test_vfmsac_vv_f16m1_tumu(vbool16_t mask, vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) { vfloat16m1_t test_vfmsac_vv_f16m1_tumu(vbool16_t mask, vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfmsac_vv_f16m1_tumu(mask, vd, vs1, vs2, vl); return __riscv_vfmsac_vv_f16m1_tumu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmsac_vf_f16m1_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmsac_vf_f16m1_tumu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmsac.mask.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmsac.mask.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
// //
vfloat16m1_t test_vfmsac_vf_f16m1_tumu(vbool16_t mask, vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) { vfloat16m1_t test_vfmsac_vf_f16m1_tumu(vbool16_t mask, vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfmsac_vf_f16m1_tumu(mask, vd, rs1, vs2, vl); return __riscv_vfmsac_vf_f16m1_tumu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmsac_vv_f16m2_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmsac_vv_f16m2_tumu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmsac.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmsac.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
// //
vfloat16m2_t test_vfmsac_vv_f16m2_tumu(vbool8_t mask, vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) { vfloat16m2_t test_vfmsac_vv_f16m2_tumu(vbool8_t mask, vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfmsac_vv_f16m2_tumu(mask, vd, vs1, vs2, vl); return __riscv_vfmsac_vv_f16m2_tumu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmsac_vf_f16m2_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmsac_vf_f16m2_tumu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmsac.mask.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmsac.mask.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
// //
vfloat16m2_t test_vfmsac_vf_f16m2_tumu(vbool8_t mask, vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) { vfloat16m2_t test_vfmsac_vf_f16m2_tumu(vbool8_t mask, vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfmsac_vf_f16m2_tumu(mask, vd, rs1, vs2, vl); return __riscv_vfmsac_vf_f16m2_tumu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmsac_vv_f16m4_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmsac_vv_f16m4_tumu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmsac.mask.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmsac.mask.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
// //
vfloat16m4_t test_vfmsac_vv_f16m4_tumu(vbool4_t mask, vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) { vfloat16m4_t test_vfmsac_vv_f16m4_tumu(vbool4_t mask, vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfmsac_vv_f16m4_tumu(mask, vd, vs1, vs2, vl); return __riscv_vfmsac_vv_f16m4_tumu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmsac_vf_f16m4_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmsac_vf_f16m4_tumu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmsac.mask.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmsac.mask.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
// //
vfloat16m4_t test_vfmsac_vf_f16m4_tumu(vbool4_t mask, vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) { vfloat16m4_t test_vfmsac_vf_f16m4_tumu(vbool4_t mask, vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfmsac_vf_f16m4_tumu(mask, vd, rs1, vs2, vl); return __riscv_vfmsac_vf_f16m4_tumu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmsac_vv_f16m8_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmsac_vv_f16m8_tumu
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmsac.mask.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmsac.mask.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
// //
vfloat16m8_t test_vfmsac_vv_f16m8_tumu(vbool2_t mask, vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) { vfloat16m8_t test_vfmsac_vv_f16m8_tumu(vbool2_t mask, vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfmsac_vv_f16m8_tumu(mask, vd, vs1, vs2, vl); return __riscv_vfmsac_vv_f16m8_tumu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmsac_vf_f16m8_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmsac_vf_f16m8_tumu
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmsac.mask.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmsac.mask.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
// //
vfloat16m8_t test_vfmsac_vf_f16m8_tumu(vbool2_t mask, vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) { vfloat16m8_t test_vfmsac_vf_f16m8_tumu(vbool2_t mask, vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfmsac_vf_f16m8_tumu(mask, vd, rs1, vs2, vl); return __riscv_vfmsac_vf_f16m8_tumu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmsac_vv_f32mf2_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmsac_vv_f32mf2_tumu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmsac.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmsac.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfmsac_vv_f32mf2_tumu(vbool64_t mask, vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) { vfloat32mf2_t test_vfmsac_vv_f32mf2_tumu(vbool64_t mask, vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfmsac_vv_f32mf2_tumu(mask, vd, vs1, vs2, vl); return __riscv_vfmsac_vv_f32mf2_tumu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmsac_vf_f32mf2_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmsac_vf_f32mf2_tumu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmsac.mask.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmsac.mask.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfmsac_vf_f32mf2_tumu(vbool64_t mask, vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) { vfloat32mf2_t test_vfmsac_vf_f32mf2_tumu(vbool64_t mask, vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfmsac_vf_f32mf2_tumu(mask, vd, rs1, vs2, vl); return __riscv_vfmsac_vf_f32mf2_tumu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmsac_vv_f32m1_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmsac_vv_f32m1_tumu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmsac.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmsac.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfmsac_vv_f32m1_tumu(vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) { vfloat32m1_t test_vfmsac_vv_f32m1_tumu(vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfmsac_vv_f32m1_tumu(mask, vd, vs1, vs2, vl); return __riscv_vfmsac_vv_f32m1_tumu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmsac_vf_f32m1_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmsac_vf_f32m1_tumu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmsac.mask.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmsac.mask.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfmsac_vf_f32m1_tumu(vbool32_t mask, vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) { vfloat32m1_t test_vfmsac_vf_f32m1_tumu(vbool32_t mask, vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfmsac_vf_f32m1_tumu(mask, vd, rs1, vs2, vl); return __riscv_vfmsac_vf_f32m1_tumu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmsac_vv_f32m2_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmsac_vv_f32m2_tumu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmsac.mask.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmsac.mask.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfmsac_vv_f32m2_tumu(vbool16_t mask, vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) { vfloat32m2_t test_vfmsac_vv_f32m2_tumu(vbool16_t mask, vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfmsac_vv_f32m2_tumu(mask, vd, vs1, vs2, vl); return __riscv_vfmsac_vv_f32m2_tumu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmsac_vf_f32m2_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmsac_vf_f32m2_tumu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmsac.mask.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmsac.mask.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfmsac_vf_f32m2_tumu(vbool16_t mask, vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) { vfloat32m2_t test_vfmsac_vf_f32m2_tumu(vbool16_t mask, vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfmsac_vf_f32m2_tumu(mask, vd, rs1, vs2, vl); return __riscv_vfmsac_vf_f32m2_tumu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmsac_vv_f32m4_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmsac_vv_f32m4_tumu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmsac.mask.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmsac.mask.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfmsac_vv_f32m4_tumu(vbool8_t mask, vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) { vfloat32m4_t test_vfmsac_vv_f32m4_tumu(vbool8_t mask, vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfmsac_vv_f32m4_tumu(mask, vd, vs1, vs2, vl); return __riscv_vfmsac_vv_f32m4_tumu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmsac_vf_f32m4_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmsac_vf_f32m4_tumu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmsac.mask.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmsac.mask.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfmsac_vf_f32m4_tumu(vbool8_t mask, vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) { vfloat32m4_t test_vfmsac_vf_f32m4_tumu(vbool8_t mask, vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfmsac_vf_f32m4_tumu(mask, vd, rs1, vs2, vl); return __riscv_vfmsac_vf_f32m4_tumu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmsac_vv_f32m8_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmsac_vv_f32m8_tumu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmsac.mask.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmsac.mask.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfmsac_vv_f32m8_tumu(vbool4_t mask, vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) { vfloat32m8_t test_vfmsac_vv_f32m8_tumu(vbool4_t mask, vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfmsac_vv_f32m8_tumu(mask, vd, vs1, vs2, vl); return __riscv_vfmsac_vv_f32m8_tumu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmsac_vf_f32m8_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmsac_vf_f32m8_tumu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmsac.mask.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmsac.mask.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfmsac_vf_f32m8_tumu(vbool4_t mask, vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) { vfloat32m8_t test_vfmsac_vf_f32m8_tumu(vbool4_t mask, vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfmsac_vf_f32m8_tumu(mask, vd, rs1, vs2, vl); return __riscv_vfmsac_vf_f32m8_tumu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmsac_vv_f64m1_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmsac_vv_f64m1_tumu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmsac.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmsac.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfmsac_vv_f64m1_tumu(vbool64_t mask, vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) { vfloat64m1_t test_vfmsac_vv_f64m1_tumu(vbool64_t mask, vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfmsac_vv_f64m1_tumu(mask, vd, vs1, vs2, vl); return __riscv_vfmsac_vv_f64m1_tumu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmsac_vf_f64m1_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmsac_vf_f64m1_tumu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmsac.mask.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmsac.mask.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfmsac_vf_f64m1_tumu(vbool64_t mask, vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) { vfloat64m1_t test_vfmsac_vf_f64m1_tumu(vbool64_t mask, vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfmsac_vf_f64m1_tumu(mask, vd, rs1, vs2, vl); return __riscv_vfmsac_vf_f64m1_tumu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmsac_vv_f64m2_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmsac_vv_f64m2_tumu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmsac.mask.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmsac.mask.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfmsac_vv_f64m2_tumu(vbool32_t mask, vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) { vfloat64m2_t test_vfmsac_vv_f64m2_tumu(vbool32_t mask, vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfmsac_vv_f64m2_tumu(mask, vd, vs1, vs2, vl); return __riscv_vfmsac_vv_f64m2_tumu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmsac_vf_f64m2_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmsac_vf_f64m2_tumu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmsac.mask.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmsac.mask.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfmsac_vf_f64m2_tumu(vbool32_t mask, vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) { vfloat64m2_t test_vfmsac_vf_f64m2_tumu(vbool32_t mask, vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfmsac_vf_f64m2_tumu(mask, vd, rs1, vs2, vl); return __riscv_vfmsac_vf_f64m2_tumu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmsac_vv_f64m4_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmsac_vv_f64m4_tumu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmsac.mask.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmsac.mask.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfmsac_vv_f64m4_tumu(vbool16_t mask, vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) { vfloat64m4_t test_vfmsac_vv_f64m4_tumu(vbool16_t mask, vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfmsac_vv_f64m4_tumu(mask, vd, vs1, vs2, vl); return __riscv_vfmsac_vv_f64m4_tumu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmsac_vf_f64m4_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmsac_vf_f64m4_tumu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmsac.mask.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmsac.mask.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfmsac_vf_f64m4_tumu(vbool16_t mask, vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) { vfloat64m4_t test_vfmsac_vf_f64m4_tumu(vbool16_t mask, vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfmsac_vf_f64m4_tumu(mask, vd, rs1, vs2, vl); return __riscv_vfmsac_vf_f64m4_tumu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmsac_vv_f64m8_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmsac_vv_f64m8_tumu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmsac.mask.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmsac.mask.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfmsac_vv_f64m8_tumu(vbool8_t mask, vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) { vfloat64m8_t test_vfmsac_vv_f64m8_tumu(vbool8_t mask, vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfmsac_vv_f64m8_tumu(mask, vd, vs1, vs2, vl); return __riscv_vfmsac_vv_f64m8_tumu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmsac_vf_f64m8_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmsac_vf_f64m8_tumu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmsac.mask.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmsac.mask.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfmsac_vf_f64m8_tumu(vbool8_t mask, vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) { vfloat64m8_t test_vfmsac_vf_f64m8_tumu(vbool8_t mask, vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfmsac_vf_f64m8_tumu(mask, vd, rs1, vs2, vl); return __riscv_vfmsac_vf_f64m8_tumu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmsac_vv_f16mf4_mu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmsac_vv_f16mf4_mu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmsac.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmsac.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
// //
vfloat16mf4_t test_vfmsac_vv_f16mf4_mu(vbool64_t mask, vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) { vfloat16mf4_t test_vfmsac_vv_f16mf4_mu(vbool64_t mask, vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfmsac_vv_f16mf4_mu(mask, vd, vs1, vs2, vl); return __riscv_vfmsac_vv_f16mf4_mu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmsac_vf_f16mf4_mu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmsac_vf_f16mf4_mu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmsac.mask.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmsac.mask.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
// //
vfloat16mf4_t test_vfmsac_vf_f16mf4_mu(vbool64_t mask, vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) { vfloat16mf4_t test_vfmsac_vf_f16mf4_mu(vbool64_t mask, vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfmsac_vf_f16mf4_mu(mask, vd, rs1, vs2, vl); return __riscv_vfmsac_vf_f16mf4_mu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmsac_vv_f16mf2_mu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmsac_vv_f16mf2_mu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmsac.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmsac.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
// //
vfloat16mf2_t test_vfmsac_vv_f16mf2_mu(vbool32_t mask, vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) { vfloat16mf2_t test_vfmsac_vv_f16mf2_mu(vbool32_t mask, vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfmsac_vv_f16mf2_mu(mask, vd, vs1, vs2, vl); return __riscv_vfmsac_vv_f16mf2_mu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmsac_vf_f16mf2_mu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmsac_vf_f16mf2_mu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmsac.mask.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmsac.mask.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
// //
vfloat16mf2_t test_vfmsac_vf_f16mf2_mu(vbool32_t mask, vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) { vfloat16mf2_t test_vfmsac_vf_f16mf2_mu(vbool32_t mask, vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfmsac_vf_f16mf2_mu(mask, vd, rs1, vs2, vl); return __riscv_vfmsac_vf_f16mf2_mu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmsac_vv_f16m1_mu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmsac_vv_f16m1_mu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmsac.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmsac.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
// //
vfloat16m1_t test_vfmsac_vv_f16m1_mu(vbool16_t mask, vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) { vfloat16m1_t test_vfmsac_vv_f16m1_mu(vbool16_t mask, vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfmsac_vv_f16m1_mu(mask, vd, vs1, vs2, vl); return __riscv_vfmsac_vv_f16m1_mu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmsac_vf_f16m1_mu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmsac_vf_f16m1_mu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmsac.mask.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmsac.mask.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
// //
vfloat16m1_t test_vfmsac_vf_f16m1_mu(vbool16_t mask, vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) { vfloat16m1_t test_vfmsac_vf_f16m1_mu(vbool16_t mask, vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfmsac_vf_f16m1_mu(mask, vd, rs1, vs2, vl); return __riscv_vfmsac_vf_f16m1_mu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmsac_vv_f16m2_mu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmsac_vv_f16m2_mu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmsac.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmsac.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
// //
vfloat16m2_t test_vfmsac_vv_f16m2_mu(vbool8_t mask, vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) { vfloat16m2_t test_vfmsac_vv_f16m2_mu(vbool8_t mask, vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfmsac_vv_f16m2_mu(mask, vd, vs1, vs2, vl); return __riscv_vfmsac_vv_f16m2_mu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmsac_vf_f16m2_mu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmsac_vf_f16m2_mu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmsac.mask.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmsac.mask.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
// //
vfloat16m2_t test_vfmsac_vf_f16m2_mu(vbool8_t mask, vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) { vfloat16m2_t test_vfmsac_vf_f16m2_mu(vbool8_t mask, vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfmsac_vf_f16m2_mu(mask, vd, rs1, vs2, vl); return __riscv_vfmsac_vf_f16m2_mu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmsac_vv_f16m4_mu // CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmsac_vv_f16m4_mu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmsac.mask.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmsac.mask.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
// //
vfloat16m4_t test_vfmsac_vv_f16m4_mu(vbool4_t mask, vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) { vfloat16m4_t test_vfmsac_vv_f16m4_mu(vbool4_t mask, vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfmsac_vv_f16m4_mu(mask, vd, vs1, vs2, vl); return __riscv_vfmsac_vv_f16m4_mu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmsac_vf_f16m4_mu // CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmsac_vf_f16m4_mu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmsac.mask.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmsac.mask.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
// //
vfloat16m4_t test_vfmsac_vf_f16m4_mu(vbool4_t mask, vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) { vfloat16m4_t test_vfmsac_vf_f16m4_mu(vbool4_t mask, vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfmsac_vf_f16m4_mu(mask, vd, rs1, vs2, vl); return __riscv_vfmsac_vf_f16m4_mu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmsac_vv_f16m8_mu // CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmsac_vv_f16m8_mu
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmsac.mask.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmsac.mask.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
// //
vfloat16m8_t test_vfmsac_vv_f16m8_mu(vbool2_t mask, vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) { vfloat16m8_t test_vfmsac_vv_f16m8_mu(vbool2_t mask, vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfmsac_vv_f16m8_mu(mask, vd, vs1, vs2, vl); return __riscv_vfmsac_vv_f16m8_mu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmsac_vf_f16m8_mu // CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmsac_vf_f16m8_mu
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmsac.mask.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmsac.mask.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
// //
vfloat16m8_t test_vfmsac_vf_f16m8_mu(vbool2_t mask, vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) { vfloat16m8_t test_vfmsac_vf_f16m8_mu(vbool2_t mask, vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfmsac_vf_f16m8_mu(mask, vd, rs1, vs2, vl); return __riscv_vfmsac_vf_f16m8_mu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmsac_vv_f32mf2_mu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmsac_vv_f32mf2_mu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmsac.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmsac.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfmsac_vv_f32mf2_mu(vbool64_t mask, vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) { vfloat32mf2_t test_vfmsac_vv_f32mf2_mu(vbool64_t mask, vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfmsac_vv_f32mf2_mu(mask, vd, vs1, vs2, vl); return __riscv_vfmsac_vv_f32mf2_mu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmsac_vf_f32mf2_mu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmsac_vf_f32mf2_mu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmsac.mask.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmsac.mask.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfmsac_vf_f32mf2_mu(vbool64_t mask, vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) { vfloat32mf2_t test_vfmsac_vf_f32mf2_mu(vbool64_t mask, vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfmsac_vf_f32mf2_mu(mask, vd, rs1, vs2, vl); return __riscv_vfmsac_vf_f32mf2_mu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmsac_vv_f32m1_mu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmsac_vv_f32m1_mu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmsac.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmsac.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfmsac_vv_f32m1_mu(vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) { vfloat32m1_t test_vfmsac_vv_f32m1_mu(vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfmsac_vv_f32m1_mu(mask, vd, vs1, vs2, vl); return __riscv_vfmsac_vv_f32m1_mu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmsac_vf_f32m1_mu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmsac_vf_f32m1_mu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmsac.mask.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmsac.mask.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfmsac_vf_f32m1_mu(vbool32_t mask, vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) { vfloat32m1_t test_vfmsac_vf_f32m1_mu(vbool32_t mask, vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfmsac_vf_f32m1_mu(mask, vd, rs1, vs2, vl); return __riscv_vfmsac_vf_f32m1_mu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmsac_vv_f32m2_mu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmsac_vv_f32m2_mu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmsac.mask.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmsac.mask.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfmsac_vv_f32m2_mu(vbool16_t mask, vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) { vfloat32m2_t test_vfmsac_vv_f32m2_mu(vbool16_t mask, vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfmsac_vv_f32m2_mu(mask, vd, vs1, vs2, vl); return __riscv_vfmsac_vv_f32m2_mu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmsac_vf_f32m2_mu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmsac_vf_f32m2_mu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmsac.mask.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmsac.mask.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfmsac_vf_f32m2_mu(vbool16_t mask, vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) { vfloat32m2_t test_vfmsac_vf_f32m2_mu(vbool16_t mask, vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfmsac_vf_f32m2_mu(mask, vd, rs1, vs2, vl); return __riscv_vfmsac_vf_f32m2_mu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmsac_vv_f32m4_mu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmsac_vv_f32m4_mu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmsac.mask.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmsac.mask.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfmsac_vv_f32m4_mu(vbool8_t mask, vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) { vfloat32m4_t test_vfmsac_vv_f32m4_mu(vbool8_t mask, vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfmsac_vv_f32m4_mu(mask, vd, vs1, vs2, vl); return __riscv_vfmsac_vv_f32m4_mu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmsac_vf_f32m4_mu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmsac_vf_f32m4_mu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmsac.mask.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmsac.mask.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfmsac_vf_f32m4_mu(vbool8_t mask, vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) { vfloat32m4_t test_vfmsac_vf_f32m4_mu(vbool8_t mask, vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfmsac_vf_f32m4_mu(mask, vd, rs1, vs2, vl); return __riscv_vfmsac_vf_f32m4_mu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmsac_vv_f32m8_mu // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmsac_vv_f32m8_mu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmsac.mask.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmsac.mask.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfmsac_vv_f32m8_mu(vbool4_t mask, vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) { vfloat32m8_t test_vfmsac_vv_f32m8_mu(vbool4_t mask, vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfmsac_vv_f32m8_mu(mask, vd, vs1, vs2, vl); return __riscv_vfmsac_vv_f32m8_mu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmsac_vf_f32m8_mu // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmsac_vf_f32m8_mu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmsac.mask.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmsac.mask.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfmsac_vf_f32m8_mu(vbool4_t mask, vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) { vfloat32m8_t test_vfmsac_vf_f32m8_mu(vbool4_t mask, vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfmsac_vf_f32m8_mu(mask, vd, rs1, vs2, vl); return __riscv_vfmsac_vf_f32m8_mu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmsac_vv_f64m1_mu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmsac_vv_f64m1_mu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmsac.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmsac.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfmsac_vv_f64m1_mu(vbool64_t mask, vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) { vfloat64m1_t test_vfmsac_vv_f64m1_mu(vbool64_t mask, vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfmsac_vv_f64m1_mu(mask, vd, vs1, vs2, vl); return __riscv_vfmsac_vv_f64m1_mu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmsac_vf_f64m1_mu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmsac_vf_f64m1_mu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmsac.mask.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmsac.mask.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfmsac_vf_f64m1_mu(vbool64_t mask, vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) { vfloat64m1_t test_vfmsac_vf_f64m1_mu(vbool64_t mask, vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfmsac_vf_f64m1_mu(mask, vd, rs1, vs2, vl); return __riscv_vfmsac_vf_f64m1_mu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmsac_vv_f64m2_mu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmsac_vv_f64m2_mu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmsac.mask.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmsac.mask.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfmsac_vv_f64m2_mu(vbool32_t mask, vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) { vfloat64m2_t test_vfmsac_vv_f64m2_mu(vbool32_t mask, vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfmsac_vv_f64m2_mu(mask, vd, vs1, vs2, vl); return __riscv_vfmsac_vv_f64m2_mu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmsac_vf_f64m2_mu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmsac_vf_f64m2_mu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmsac.mask.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmsac.mask.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfmsac_vf_f64m2_mu(vbool32_t mask, vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) { vfloat64m2_t test_vfmsac_vf_f64m2_mu(vbool32_t mask, vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfmsac_vf_f64m2_mu(mask, vd, rs1, vs2, vl); return __riscv_vfmsac_vf_f64m2_mu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmsac_vv_f64m4_mu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmsac_vv_f64m4_mu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmsac.mask.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmsac.mask.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfmsac_vv_f64m4_mu(vbool16_t mask, vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) { vfloat64m4_t test_vfmsac_vv_f64m4_mu(vbool16_t mask, vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfmsac_vv_f64m4_mu(mask, vd, vs1, vs2, vl); return __riscv_vfmsac_vv_f64m4_mu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmsac_vf_f64m4_mu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmsac_vf_f64m4_mu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmsac.mask.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmsac.mask.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfmsac_vf_f64m4_mu(vbool16_t mask, vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) { vfloat64m4_t test_vfmsac_vf_f64m4_mu(vbool16_t mask, vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfmsac_vf_f64m4_mu(mask, vd, rs1, vs2, vl); return __riscv_vfmsac_vf_f64m4_mu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmsac_vv_f64m8_mu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmsac_vv_f64m8_mu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmsac.mask.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmsac.mask.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfmsac_vv_f64m8_mu(vbool8_t mask, vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) { vfloat64m8_t test_vfmsac_vv_f64m8_mu(vbool8_t mask, vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfmsac_vv_f64m8_mu(mask, vd, vs1, vs2, vl); return __riscv_vfmsac_vv_f64m8_mu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmsac_vf_f64m8_mu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmsac_vf_f64m8_mu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmsac.mask.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmsac.mask.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfmsac_vf_f64m8_mu(vbool8_t mask, vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) { vfloat64m8_t test_vfmsac_vf_f64m8_mu(vbool8_t mask, vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfmsac_vf_f64m8_mu(mask, vd, rs1, vs2, vl); return __riscv_vfmsac_vf_f64m8_mu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmsac_vv_f16mf4_rm_tu
// CHECK-RV64-SAME: (<vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmsac.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
//
vfloat16mf4_t test_vfmsac_vv_f16mf4_rm_tu(vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfmsac_vv_f16mf4_rm_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmsac_vf_f16mf4_rm_tu
// CHECK-RV64-SAME: (<vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmsac.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
//
vfloat16mf4_t test_vfmsac_vf_f16mf4_rm_tu(vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfmsac_vf_f16mf4_rm_tu(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmsac_vv_f16mf2_rm_tu
// CHECK-RV64-SAME: (<vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmsac.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
//
vfloat16mf2_t test_vfmsac_vv_f16mf2_rm_tu(vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfmsac_vv_f16mf2_rm_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmsac_vf_f16mf2_rm_tu
// CHECK-RV64-SAME: (<vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmsac.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
//
vfloat16mf2_t test_vfmsac_vf_f16mf2_rm_tu(vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfmsac_vf_f16mf2_rm_tu(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmsac_vv_f16m1_rm_tu
// CHECK-RV64-SAME: (<vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmsac.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfmsac_vv_f16m1_rm_tu(vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfmsac_vv_f16m1_rm_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmsac_vf_f16m1_rm_tu
// CHECK-RV64-SAME: (<vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmsac.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfmsac_vf_f16m1_rm_tu(vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfmsac_vf_f16m1_rm_tu(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmsac_vv_f16m2_rm_tu
// CHECK-RV64-SAME: (<vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmsac.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
//
vfloat16m2_t test_vfmsac_vv_f16m2_rm_tu(vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfmsac_vv_f16m2_rm_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmsac_vf_f16m2_rm_tu
// CHECK-RV64-SAME: (<vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmsac.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
//
vfloat16m2_t test_vfmsac_vf_f16m2_rm_tu(vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfmsac_vf_f16m2_rm_tu(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmsac_vv_f16m4_rm_tu
// CHECK-RV64-SAME: (<vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmsac.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
//
vfloat16m4_t test_vfmsac_vv_f16m4_rm_tu(vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfmsac_vv_f16m4_rm_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmsac_vf_f16m4_rm_tu
// CHECK-RV64-SAME: (<vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmsac.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
//
vfloat16m4_t test_vfmsac_vf_f16m4_rm_tu(vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfmsac_vf_f16m4_rm_tu(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmsac_vv_f16m8_rm_tu
// CHECK-RV64-SAME: (<vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmsac.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
//
vfloat16m8_t test_vfmsac_vv_f16m8_rm_tu(vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfmsac_vv_f16m8_rm_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmsac_vf_f16m8_rm_tu
// CHECK-RV64-SAME: (<vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmsac.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
//
vfloat16m8_t test_vfmsac_vf_f16m8_rm_tu(vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfmsac_vf_f16m8_rm_tu(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmsac_vv_f32mf2_rm_tu
// CHECK-RV64-SAME: (<vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmsac.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
//
vfloat32mf2_t test_vfmsac_vv_f32mf2_rm_tu(vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfmsac_vv_f32mf2_rm_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmsac_vf_f32mf2_rm_tu
// CHECK-RV64-SAME: (<vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmsac.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
//
vfloat32mf2_t test_vfmsac_vf_f32mf2_rm_tu(vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfmsac_vf_f32mf2_rm_tu(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmsac_vv_f32m1_rm_tu
// CHECK-RV64-SAME: (<vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmsac.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfmsac_vv_f32m1_rm_tu(vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfmsac_vv_f32m1_rm_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmsac_vf_f32m1_rm_tu
// CHECK-RV64-SAME: (<vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmsac.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfmsac_vf_f32m1_rm_tu(vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfmsac_vf_f32m1_rm_tu(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmsac_vv_f32m2_rm_tu
// CHECK-RV64-SAME: (<vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmsac.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
//
vfloat32m2_t test_vfmsac_vv_f32m2_rm_tu(vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfmsac_vv_f32m2_rm_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmsac_vf_f32m2_rm_tu
// CHECK-RV64-SAME: (<vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmsac.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
//
vfloat32m2_t test_vfmsac_vf_f32m2_rm_tu(vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfmsac_vf_f32m2_rm_tu(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmsac_vv_f32m4_rm_tu
// CHECK-RV64-SAME: (<vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmsac.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
//
vfloat32m4_t test_vfmsac_vv_f32m4_rm_tu(vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfmsac_vv_f32m4_rm_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmsac_vf_f32m4_rm_tu
// CHECK-RV64-SAME: (<vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmsac.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
//
vfloat32m4_t test_vfmsac_vf_f32m4_rm_tu(vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfmsac_vf_f32m4_rm_tu(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmsac_vv_f32m8_rm_tu
// CHECK-RV64-SAME: (<vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmsac.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
//
vfloat32m8_t test_vfmsac_vv_f32m8_rm_tu(vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfmsac_vv_f32m8_rm_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmsac_vf_f32m8_rm_tu
// CHECK-RV64-SAME: (<vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmsac.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
//
vfloat32m8_t test_vfmsac_vf_f32m8_rm_tu(vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfmsac_vf_f32m8_rm_tu(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmsac_vv_f64m1_rm_tu
// CHECK-RV64-SAME: (<vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmsac.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfmsac_vv_f64m1_rm_tu(vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfmsac_vv_f64m1_rm_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmsac_vf_f64m1_rm_tu
// CHECK-RV64-SAME: (<vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmsac.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfmsac_vf_f64m1_rm_tu(vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfmsac_vf_f64m1_rm_tu(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmsac_vv_f64m2_rm_tu
// CHECK-RV64-SAME: (<vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmsac.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
//
vfloat64m2_t test_vfmsac_vv_f64m2_rm_tu(vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfmsac_vv_f64m2_rm_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmsac_vf_f64m2_rm_tu
// CHECK-RV64-SAME: (<vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmsac.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
//
vfloat64m2_t test_vfmsac_vf_f64m2_rm_tu(vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfmsac_vf_f64m2_rm_tu(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmsac_vv_f64m4_rm_tu
// CHECK-RV64-SAME: (<vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmsac.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
//
vfloat64m4_t test_vfmsac_vv_f64m4_rm_tu(vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfmsac_vv_f64m4_rm_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmsac_vf_f64m4_rm_tu
// CHECK-RV64-SAME: (<vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmsac.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
//
vfloat64m4_t test_vfmsac_vf_f64m4_rm_tu(vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfmsac_vf_f64m4_rm_tu(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmsac_vv_f64m8_rm_tu
// CHECK-RV64-SAME: (<vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmsac.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
//
vfloat64m8_t test_vfmsac_vv_f64m8_rm_tu(vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfmsac_vv_f64m8_rm_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmsac_vf_f64m8_rm_tu
// CHECK-RV64-SAME: (<vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmsac.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
//
vfloat64m8_t test_vfmsac_vf_f64m8_rm_tu(vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfmsac_vf_f64m8_rm_tu(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmsac_vv_f16mf4_rm_tum
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmsac.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
//
vfloat16mf4_t test_vfmsac_vv_f16mf4_rm_tum(vbool64_t mask, vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfmsac_vv_f16mf4_rm_tum(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmsac_vf_f16mf4_rm_tum
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmsac.mask.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
//
vfloat16mf4_t test_vfmsac_vf_f16mf4_rm_tum(vbool64_t mask, vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfmsac_vf_f16mf4_rm_tum(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmsac_vv_f16mf2_rm_tum
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmsac.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
//
vfloat16mf2_t test_vfmsac_vv_f16mf2_rm_tum(vbool32_t mask, vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfmsac_vv_f16mf2_rm_tum(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmsac_vf_f16mf2_rm_tum
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmsac.mask.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
//
vfloat16mf2_t test_vfmsac_vf_f16mf2_rm_tum(vbool32_t mask, vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfmsac_vf_f16mf2_rm_tum(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmsac_vv_f16m1_rm_tum
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmsac.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfmsac_vv_f16m1_rm_tum(vbool16_t mask, vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfmsac_vv_f16m1_rm_tum(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmsac_vf_f16m1_rm_tum
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmsac.mask.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfmsac_vf_f16m1_rm_tum(vbool16_t mask, vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfmsac_vf_f16m1_rm_tum(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmsac_vv_f16m2_rm_tum
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmsac.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
//
vfloat16m2_t test_vfmsac_vv_f16m2_rm_tum(vbool8_t mask, vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfmsac_vv_f16m2_rm_tum(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmsac_vf_f16m2_rm_tum
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmsac.mask.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
//
vfloat16m2_t test_vfmsac_vf_f16m2_rm_tum(vbool8_t mask, vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfmsac_vf_f16m2_rm_tum(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmsac_vv_f16m4_rm_tum
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmsac.mask.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
//
vfloat16m4_t test_vfmsac_vv_f16m4_rm_tum(vbool4_t mask, vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfmsac_vv_f16m4_rm_tum(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmsac_vf_f16m4_rm_tum
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmsac.mask.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
//
vfloat16m4_t test_vfmsac_vf_f16m4_rm_tum(vbool4_t mask, vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfmsac_vf_f16m4_rm_tum(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmsac_vv_f16m8_rm_tum
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmsac.mask.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
//
vfloat16m8_t test_vfmsac_vv_f16m8_rm_tum(vbool2_t mask, vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfmsac_vv_f16m8_rm_tum(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmsac_vf_f16m8_rm_tum
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmsac.mask.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
//
vfloat16m8_t test_vfmsac_vf_f16m8_rm_tum(vbool2_t mask, vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfmsac_vf_f16m8_rm_tum(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmsac_vv_f32mf2_rm_tum
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmsac.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
//
vfloat32mf2_t test_vfmsac_vv_f32mf2_rm_tum(vbool64_t mask, vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfmsac_vv_f32mf2_rm_tum(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmsac_vf_f32mf2_rm_tum
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmsac.mask.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
//
vfloat32mf2_t test_vfmsac_vf_f32mf2_rm_tum(vbool64_t mask, vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfmsac_vf_f32mf2_rm_tum(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmsac_vv_f32m1_rm_tum
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmsac.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfmsac_vv_f32m1_rm_tum(vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfmsac_vv_f32m1_rm_tum(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmsac_vf_f32m1_rm_tum
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmsac.mask.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfmsac_vf_f32m1_rm_tum(vbool32_t mask, vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfmsac_vf_f32m1_rm_tum(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmsac_vv_f32m2_rm_tum
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmsac.mask.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
//
vfloat32m2_t test_vfmsac_vv_f32m2_rm_tum(vbool16_t mask, vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfmsac_vv_f32m2_rm_tum(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmsac_vf_f32m2_rm_tum
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmsac.mask.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
//
vfloat32m2_t test_vfmsac_vf_f32m2_rm_tum(vbool16_t mask, vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfmsac_vf_f32m2_rm_tum(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmsac_vv_f32m4_rm_tum
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmsac.mask.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
//
vfloat32m4_t test_vfmsac_vv_f32m4_rm_tum(vbool8_t mask, vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfmsac_vv_f32m4_rm_tum(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmsac_vf_f32m4_rm_tum
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmsac.mask.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
//
vfloat32m4_t test_vfmsac_vf_f32m4_rm_tum(vbool8_t mask, vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfmsac_vf_f32m4_rm_tum(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmsac_vv_f32m8_rm_tum
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmsac.mask.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
//
vfloat32m8_t test_vfmsac_vv_f32m8_rm_tum(vbool4_t mask, vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfmsac_vv_f32m8_rm_tum(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmsac_vf_f32m8_rm_tum
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmsac.mask.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
//
vfloat32m8_t test_vfmsac_vf_f32m8_rm_tum(vbool4_t mask, vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfmsac_vf_f32m8_rm_tum(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmsac_vv_f64m1_rm_tum
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmsac.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfmsac_vv_f64m1_rm_tum(vbool64_t mask, vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfmsac_vv_f64m1_rm_tum(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmsac_vf_f64m1_rm_tum
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmsac.mask.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfmsac_vf_f64m1_rm_tum(vbool64_t mask, vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfmsac_vf_f64m1_rm_tum(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmsac_vv_f64m2_rm_tum
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmsac.mask.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
//
vfloat64m2_t test_vfmsac_vv_f64m2_rm_tum(vbool32_t mask, vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfmsac_vv_f64m2_rm_tum(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmsac_vf_f64m2_rm_tum
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmsac.mask.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
//
vfloat64m2_t test_vfmsac_vf_f64m2_rm_tum(vbool32_t mask, vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfmsac_vf_f64m2_rm_tum(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmsac_vv_f64m4_rm_tum
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmsac.mask.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
//
vfloat64m4_t test_vfmsac_vv_f64m4_rm_tum(vbool16_t mask, vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfmsac_vv_f64m4_rm_tum(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmsac_vf_f64m4_rm_tum
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmsac.mask.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
//
vfloat64m4_t test_vfmsac_vf_f64m4_rm_tum(vbool16_t mask, vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfmsac_vf_f64m4_rm_tum(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmsac_vv_f64m8_rm_tum
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmsac.mask.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
//
vfloat64m8_t test_vfmsac_vv_f64m8_rm_tum(vbool8_t mask, vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfmsac_vv_f64m8_rm_tum(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmsac_vf_f64m8_rm_tum
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmsac.mask.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
//
vfloat64m8_t test_vfmsac_vf_f64m8_rm_tum(vbool8_t mask, vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfmsac_vf_f64m8_rm_tum(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmsac_vv_f16mf4_rm_tumu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmsac.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
//
vfloat16mf4_t test_vfmsac_vv_f16mf4_rm_tumu(vbool64_t mask, vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfmsac_vv_f16mf4_rm_tumu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmsac_vf_f16mf4_rm_tumu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmsac.mask.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
//
vfloat16mf4_t test_vfmsac_vf_f16mf4_rm_tumu(vbool64_t mask, vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfmsac_vf_f16mf4_rm_tumu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmsac_vv_f16mf2_rm_tumu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmsac.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
//
vfloat16mf2_t test_vfmsac_vv_f16mf2_rm_tumu(vbool32_t mask, vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfmsac_vv_f16mf2_rm_tumu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmsac_vf_f16mf2_rm_tumu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmsac.mask.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
//
vfloat16mf2_t test_vfmsac_vf_f16mf2_rm_tumu(vbool32_t mask, vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfmsac_vf_f16mf2_rm_tumu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmsac_vv_f16m1_rm_tumu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmsac.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfmsac_vv_f16m1_rm_tumu(vbool16_t mask, vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfmsac_vv_f16m1_rm_tumu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmsac_vf_f16m1_rm_tumu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmsac.mask.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfmsac_vf_f16m1_rm_tumu(vbool16_t mask, vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfmsac_vf_f16m1_rm_tumu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmsac_vv_f16m2_rm_tumu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmsac.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
//
vfloat16m2_t test_vfmsac_vv_f16m2_rm_tumu(vbool8_t mask, vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfmsac_vv_f16m2_rm_tumu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmsac_vf_f16m2_rm_tumu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmsac.mask.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
//
vfloat16m2_t test_vfmsac_vf_f16m2_rm_tumu(vbool8_t mask, vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfmsac_vf_f16m2_rm_tumu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmsac_vv_f16m4_rm_tumu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmsac.mask.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
//
vfloat16m4_t test_vfmsac_vv_f16m4_rm_tumu(vbool4_t mask, vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfmsac_vv_f16m4_rm_tumu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmsac_vf_f16m4_rm_tumu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmsac.mask.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
//
vfloat16m4_t test_vfmsac_vf_f16m4_rm_tumu(vbool4_t mask, vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfmsac_vf_f16m4_rm_tumu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmsac_vv_f16m8_rm_tumu
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmsac.mask.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
//
vfloat16m8_t test_vfmsac_vv_f16m8_rm_tumu(vbool2_t mask, vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfmsac_vv_f16m8_rm_tumu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmsac_vf_f16m8_rm_tumu
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmsac.mask.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
//
vfloat16m8_t test_vfmsac_vf_f16m8_rm_tumu(vbool2_t mask, vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfmsac_vf_f16m8_rm_tumu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmsac_vv_f32mf2_rm_tumu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmsac.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
//
vfloat32mf2_t test_vfmsac_vv_f32mf2_rm_tumu(vbool64_t mask, vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfmsac_vv_f32mf2_rm_tumu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmsac_vf_f32mf2_rm_tumu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmsac.mask.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
//
vfloat32mf2_t test_vfmsac_vf_f32mf2_rm_tumu(vbool64_t mask, vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfmsac_vf_f32mf2_rm_tumu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmsac_vv_f32m1_rm_tumu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmsac.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfmsac_vv_f32m1_rm_tumu(vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfmsac_vv_f32m1_rm_tumu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmsac_vf_f32m1_rm_tumu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmsac.mask.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfmsac_vf_f32m1_rm_tumu(vbool32_t mask, vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfmsac_vf_f32m1_rm_tumu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmsac_vv_f32m2_rm_tumu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmsac.mask.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
//
vfloat32m2_t test_vfmsac_vv_f32m2_rm_tumu(vbool16_t mask, vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfmsac_vv_f32m2_rm_tumu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmsac_vf_f32m2_rm_tumu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmsac.mask.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
//
vfloat32m2_t test_vfmsac_vf_f32m2_rm_tumu(vbool16_t mask, vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfmsac_vf_f32m2_rm_tumu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmsac_vv_f32m4_rm_tumu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmsac.mask.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
//
vfloat32m4_t test_vfmsac_vv_f32m4_rm_tumu(vbool8_t mask, vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfmsac_vv_f32m4_rm_tumu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmsac_vf_f32m4_rm_tumu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmsac.mask.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
//
vfloat32m4_t test_vfmsac_vf_f32m4_rm_tumu(vbool8_t mask, vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfmsac_vf_f32m4_rm_tumu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmsac_vv_f32m8_rm_tumu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmsac.mask.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
//
vfloat32m8_t test_vfmsac_vv_f32m8_rm_tumu(vbool4_t mask, vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfmsac_vv_f32m8_rm_tumu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmsac_vf_f32m8_rm_tumu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmsac.mask.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
//
vfloat32m8_t test_vfmsac_vf_f32m8_rm_tumu(vbool4_t mask, vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfmsac_vf_f32m8_rm_tumu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmsac_vv_f64m1_rm_tumu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmsac.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfmsac_vv_f64m1_rm_tumu(vbool64_t mask, vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfmsac_vv_f64m1_rm_tumu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmsac_vf_f64m1_rm_tumu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmsac.mask.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfmsac_vf_f64m1_rm_tumu(vbool64_t mask, vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfmsac_vf_f64m1_rm_tumu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmsac_vv_f64m2_rm_tumu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmsac.mask.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
//
vfloat64m2_t test_vfmsac_vv_f64m2_rm_tumu(vbool32_t mask, vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfmsac_vv_f64m2_rm_tumu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmsac_vf_f64m2_rm_tumu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmsac.mask.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
//
vfloat64m2_t test_vfmsac_vf_f64m2_rm_tumu(vbool32_t mask, vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfmsac_vf_f64m2_rm_tumu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmsac_vv_f64m4_rm_tumu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmsac.mask.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
//
vfloat64m4_t test_vfmsac_vv_f64m4_rm_tumu(vbool16_t mask, vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfmsac_vv_f64m4_rm_tumu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmsac_vf_f64m4_rm_tumu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmsac.mask.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
//
vfloat64m4_t test_vfmsac_vf_f64m4_rm_tumu(vbool16_t mask, vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfmsac_vf_f64m4_rm_tumu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmsac_vv_f64m8_rm_tumu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmsac.mask.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
//
vfloat64m8_t test_vfmsac_vv_f64m8_rm_tumu(vbool8_t mask, vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfmsac_vv_f64m8_rm_tumu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmsac_vf_f64m8_rm_tumu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmsac.mask.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
//
vfloat64m8_t test_vfmsac_vf_f64m8_rm_tumu(vbool8_t mask, vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfmsac_vf_f64m8_rm_tumu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmsac_vv_f16mf4_rm_mu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmsac.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
//
vfloat16mf4_t test_vfmsac_vv_f16mf4_rm_mu(vbool64_t mask, vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfmsac_vv_f16mf4_rm_mu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmsac_vf_f16mf4_rm_mu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmsac.mask.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
//
vfloat16mf4_t test_vfmsac_vf_f16mf4_rm_mu(vbool64_t mask, vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfmsac_vf_f16mf4_rm_mu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmsac_vv_f16mf2_rm_mu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmsac.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
//
vfloat16mf2_t test_vfmsac_vv_f16mf2_rm_mu(vbool32_t mask, vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfmsac_vv_f16mf2_rm_mu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmsac_vf_f16mf2_rm_mu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmsac.mask.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
//
vfloat16mf2_t test_vfmsac_vf_f16mf2_rm_mu(vbool32_t mask, vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfmsac_vf_f16mf2_rm_mu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmsac_vv_f16m1_rm_mu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmsac.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfmsac_vv_f16m1_rm_mu(vbool16_t mask, vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfmsac_vv_f16m1_rm_mu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmsac_vf_f16m1_rm_mu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmsac.mask.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfmsac_vf_f16m1_rm_mu(vbool16_t mask, vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfmsac_vf_f16m1_rm_mu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmsac_vv_f16m2_rm_mu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmsac.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
//
vfloat16m2_t test_vfmsac_vv_f16m2_rm_mu(vbool8_t mask, vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfmsac_vv_f16m2_rm_mu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmsac_vf_f16m2_rm_mu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmsac.mask.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
//
vfloat16m2_t test_vfmsac_vf_f16m2_rm_mu(vbool8_t mask, vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfmsac_vf_f16m2_rm_mu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmsac_vv_f16m4_rm_mu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmsac.mask.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
//
vfloat16m4_t test_vfmsac_vv_f16m4_rm_mu(vbool4_t mask, vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfmsac_vv_f16m4_rm_mu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmsac_vf_f16m4_rm_mu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmsac.mask.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
//
vfloat16m4_t test_vfmsac_vf_f16m4_rm_mu(vbool4_t mask, vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfmsac_vf_f16m4_rm_mu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmsac_vv_f16m8_rm_mu
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmsac.mask.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
//
vfloat16m8_t test_vfmsac_vv_f16m8_rm_mu(vbool2_t mask, vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfmsac_vv_f16m8_rm_mu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmsac_vf_f16m8_rm_mu
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmsac.mask.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
//
vfloat16m8_t test_vfmsac_vf_f16m8_rm_mu(vbool2_t mask, vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfmsac_vf_f16m8_rm_mu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmsac_vv_f32mf2_rm_mu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmsac.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
//
vfloat32mf2_t test_vfmsac_vv_f32mf2_rm_mu(vbool64_t mask, vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfmsac_vv_f32mf2_rm_mu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmsac_vf_f32mf2_rm_mu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmsac.mask.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
//
vfloat32mf2_t test_vfmsac_vf_f32mf2_rm_mu(vbool64_t mask, vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfmsac_vf_f32mf2_rm_mu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmsac_vv_f32m1_rm_mu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmsac.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfmsac_vv_f32m1_rm_mu(vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfmsac_vv_f32m1_rm_mu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmsac_vf_f32m1_rm_mu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmsac.mask.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfmsac_vf_f32m1_rm_mu(vbool32_t mask, vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfmsac_vf_f32m1_rm_mu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmsac_vv_f32m2_rm_mu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmsac.mask.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
//
vfloat32m2_t test_vfmsac_vv_f32m2_rm_mu(vbool16_t mask, vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfmsac_vv_f32m2_rm_mu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmsac_vf_f32m2_rm_mu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmsac.mask.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
//
vfloat32m2_t test_vfmsac_vf_f32m2_rm_mu(vbool16_t mask, vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfmsac_vf_f32m2_rm_mu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmsac_vv_f32m4_rm_mu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmsac.mask.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
//
vfloat32m4_t test_vfmsac_vv_f32m4_rm_mu(vbool8_t mask, vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfmsac_vv_f32m4_rm_mu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmsac_vf_f32m4_rm_mu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmsac.mask.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
//
vfloat32m4_t test_vfmsac_vf_f32m4_rm_mu(vbool8_t mask, vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfmsac_vf_f32m4_rm_mu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmsac_vv_f32m8_rm_mu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmsac.mask.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
//
vfloat32m8_t test_vfmsac_vv_f32m8_rm_mu(vbool4_t mask, vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfmsac_vv_f32m8_rm_mu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmsac_vf_f32m8_rm_mu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmsac.mask.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
//
vfloat32m8_t test_vfmsac_vf_f32m8_rm_mu(vbool4_t mask, vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfmsac_vf_f32m8_rm_mu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmsac_vv_f64m1_rm_mu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmsac.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfmsac_vv_f64m1_rm_mu(vbool64_t mask, vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfmsac_vv_f64m1_rm_mu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmsac_vf_f64m1_rm_mu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmsac.mask.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfmsac_vf_f64m1_rm_mu(vbool64_t mask, vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfmsac_vf_f64m1_rm_mu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmsac_vv_f64m2_rm_mu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmsac.mask.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
//
vfloat64m2_t test_vfmsac_vv_f64m2_rm_mu(vbool32_t mask, vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfmsac_vv_f64m2_rm_mu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmsac_vf_f64m2_rm_mu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmsac.mask.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
//
vfloat64m2_t test_vfmsac_vf_f64m2_rm_mu(vbool32_t mask, vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfmsac_vf_f64m2_rm_mu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmsac_vv_f64m4_rm_mu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmsac.mask.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
//
vfloat64m4_t test_vfmsac_vv_f64m4_rm_mu(vbool16_t mask, vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfmsac_vv_f64m4_rm_mu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmsac_vf_f64m4_rm_mu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmsac.mask.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
//
vfloat64m4_t test_vfmsac_vf_f64m4_rm_mu(vbool16_t mask, vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfmsac_vf_f64m4_rm_mu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmsac_vv_f64m8_rm_mu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmsac.mask.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
//
vfloat64m8_t test_vfmsac_vv_f64m8_rm_mu(vbool8_t mask, vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfmsac_vv_f64m8_rm_mu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmsac_vf_f64m8_rm_mu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmsac.mask.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
//
vfloat64m8_t test_vfmsac_vf_f64m8_rm_mu(vbool8_t mask, vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfmsac_vf_f64m8_rm_mu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}

clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfmsub.c

// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target // REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh \ // RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh \
// RUN: -target-feature +experimental-zvfh -disable-O0-optnone \ // RUN: -target-feature +experimental-zvfh -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ // RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s // RUN: FileCheck --check-prefix=CHECK-RV64 %s
#include <riscv_vector.h> #include <riscv_vector.h>
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmsub_vv_f16mf4_tu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmsub_vv_f16mf4_tu
// CHECK-RV64-SAME: (<vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK-RV64-SAME: (<vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmsub.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmsub.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
// //
vfloat16mf4_t test_vfmsub_vv_f16mf4_tu(vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) { vfloat16mf4_t test_vfmsub_vv_f16mf4_tu(vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfmsub_vv_f16mf4_tu(vd, vs1, vs2, vl); return __riscv_vfmsub_vv_f16mf4_tu(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmsub_vf_f16mf4_tu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmsub_vf_f16mf4_tu
// CHECK-RV64-SAME: (<vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmsub.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmsub.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
// //
vfloat16mf4_t test_vfmsub_vf_f16mf4_tu(vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) { vfloat16mf4_t test_vfmsub_vf_f16mf4_tu(vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfmsub_vf_f16mf4_tu(vd, rs1, vs2, vl); return __riscv_vfmsub_vf_f16mf4_tu(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmsub_vv_f16mf2_tu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmsub_vv_f16mf2_tu
// CHECK-RV64-SAME: (<vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmsub.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmsub.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
// //
vfloat16mf2_t test_vfmsub_vv_f16mf2_tu(vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) { vfloat16mf2_t test_vfmsub_vv_f16mf2_tu(vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfmsub_vv_f16mf2_tu(vd, vs1, vs2, vl); return __riscv_vfmsub_vv_f16mf2_tu(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmsub_vf_f16mf2_tu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmsub_vf_f16mf2_tu
// CHECK-RV64-SAME: (<vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmsub.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmsub.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
// //
vfloat16mf2_t test_vfmsub_vf_f16mf2_tu(vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) { vfloat16mf2_t test_vfmsub_vf_f16mf2_tu(vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfmsub_vf_f16mf2_tu(vd, rs1, vs2, vl); return __riscv_vfmsub_vf_f16mf2_tu(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmsub_vv_f16m1_tu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmsub_vv_f16m1_tu
// CHECK-RV64-SAME: (<vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmsub.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmsub.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
// //
vfloat16m1_t test_vfmsub_vv_f16m1_tu(vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) { vfloat16m1_t test_vfmsub_vv_f16m1_tu(vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfmsub_vv_f16m1_tu(vd, vs1, vs2, vl); return __riscv_vfmsub_vv_f16m1_tu(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmsub_vf_f16m1_tu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmsub_vf_f16m1_tu
// CHECK-RV64-SAME: (<vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmsub.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmsub.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
// //
vfloat16m1_t test_vfmsub_vf_f16m1_tu(vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) { vfloat16m1_t test_vfmsub_vf_f16m1_tu(vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfmsub_vf_f16m1_tu(vd, rs1, vs2, vl); return __riscv_vfmsub_vf_f16m1_tu(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmsub_vv_f16m2_tu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmsub_vv_f16m2_tu
// CHECK-RV64-SAME: (<vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmsub.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmsub.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
// //
vfloat16m2_t test_vfmsub_vv_f16m2_tu(vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) { vfloat16m2_t test_vfmsub_vv_f16m2_tu(vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfmsub_vv_f16m2_tu(vd, vs1, vs2, vl); return __riscv_vfmsub_vv_f16m2_tu(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmsub_vf_f16m2_tu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmsub_vf_f16m2_tu
// CHECK-RV64-SAME: (<vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmsub.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmsub.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
// //
vfloat16m2_t test_vfmsub_vf_f16m2_tu(vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) { vfloat16m2_t test_vfmsub_vf_f16m2_tu(vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfmsub_vf_f16m2_tu(vd, rs1, vs2, vl); return __riscv_vfmsub_vf_f16m2_tu(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmsub_vv_f16m4_tu // CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmsub_vv_f16m4_tu
// CHECK-RV64-SAME: (<vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmsub.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmsub.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
// //
vfloat16m4_t test_vfmsub_vv_f16m4_tu(vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) { vfloat16m4_t test_vfmsub_vv_f16m4_tu(vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfmsub_vv_f16m4_tu(vd, vs1, vs2, vl); return __riscv_vfmsub_vv_f16m4_tu(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmsub_vf_f16m4_tu // CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmsub_vf_f16m4_tu
// CHECK-RV64-SAME: (<vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmsub.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmsub.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
// //
vfloat16m4_t test_vfmsub_vf_f16m4_tu(vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) { vfloat16m4_t test_vfmsub_vf_f16m4_tu(vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfmsub_vf_f16m4_tu(vd, rs1, vs2, vl); return __riscv_vfmsub_vf_f16m4_tu(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmsub_vv_f16m8_tu // CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmsub_vv_f16m8_tu
// CHECK-RV64-SAME: (<vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmsub.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmsub.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
// //
vfloat16m8_t test_vfmsub_vv_f16m8_tu(vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) { vfloat16m8_t test_vfmsub_vv_f16m8_tu(vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfmsub_vv_f16m8_tu(vd, vs1, vs2, vl); return __riscv_vfmsub_vv_f16m8_tu(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmsub_vf_f16m8_tu // CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmsub_vf_f16m8_tu
// CHECK-RV64-SAME: (<vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmsub.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmsub.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
// //
vfloat16m8_t test_vfmsub_vf_f16m8_tu(vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) { vfloat16m8_t test_vfmsub_vf_f16m8_tu(vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfmsub_vf_f16m8_tu(vd, rs1, vs2, vl); return __riscv_vfmsub_vf_f16m8_tu(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmsub_vv_f32mf2_tu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmsub_vv_f32mf2_tu
// CHECK-RV64-SAME: (<vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmsub.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmsub.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfmsub_vv_f32mf2_tu(vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) { vfloat32mf2_t test_vfmsub_vv_f32mf2_tu(vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfmsub_vv_f32mf2_tu(vd, vs1, vs2, vl); return __riscv_vfmsub_vv_f32mf2_tu(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmsub_vf_f32mf2_tu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmsub_vf_f32mf2_tu
// CHECK-RV64-SAME: (<vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmsub.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmsub.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfmsub_vf_f32mf2_tu(vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) { vfloat32mf2_t test_vfmsub_vf_f32mf2_tu(vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfmsub_vf_f32mf2_tu(vd, rs1, vs2, vl); return __riscv_vfmsub_vf_f32mf2_tu(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmsub_vv_f32m1_tu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmsub_vv_f32m1_tu
// CHECK-RV64-SAME: (<vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmsub.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmsub.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfmsub_vv_f32m1_tu(vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) { vfloat32m1_t test_vfmsub_vv_f32m1_tu(vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfmsub_vv_f32m1_tu(vd, vs1, vs2, vl); return __riscv_vfmsub_vv_f32m1_tu(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmsub_vf_f32m1_tu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmsub_vf_f32m1_tu
// CHECK-RV64-SAME: (<vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmsub.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmsub.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfmsub_vf_f32m1_tu(vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) { vfloat32m1_t test_vfmsub_vf_f32m1_tu(vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfmsub_vf_f32m1_tu(vd, rs1, vs2, vl); return __riscv_vfmsub_vf_f32m1_tu(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmsub_vv_f32m2_tu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmsub_vv_f32m2_tu
// CHECK-RV64-SAME: (<vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmsub.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmsub.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfmsub_vv_f32m2_tu(vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) { vfloat32m2_t test_vfmsub_vv_f32m2_tu(vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfmsub_vv_f32m2_tu(vd, vs1, vs2, vl); return __riscv_vfmsub_vv_f32m2_tu(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmsub_vf_f32m2_tu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmsub_vf_f32m2_tu
// CHECK-RV64-SAME: (<vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmsub.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmsub.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfmsub_vf_f32m2_tu(vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) { vfloat32m2_t test_vfmsub_vf_f32m2_tu(vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfmsub_vf_f32m2_tu(vd, rs1, vs2, vl); return __riscv_vfmsub_vf_f32m2_tu(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmsub_vv_f32m4_tu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmsub_vv_f32m4_tu
// CHECK-RV64-SAME: (<vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmsub.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmsub.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfmsub_vv_f32m4_tu(vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) { vfloat32m4_t test_vfmsub_vv_f32m4_tu(vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfmsub_vv_f32m4_tu(vd, vs1, vs2, vl); return __riscv_vfmsub_vv_f32m4_tu(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmsub_vf_f32m4_tu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmsub_vf_f32m4_tu
// CHECK-RV64-SAME: (<vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmsub.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmsub.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfmsub_vf_f32m4_tu(vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) { vfloat32m4_t test_vfmsub_vf_f32m4_tu(vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfmsub_vf_f32m4_tu(vd, rs1, vs2, vl); return __riscv_vfmsub_vf_f32m4_tu(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmsub_vv_f32m8_tu // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmsub_vv_f32m8_tu
// CHECK-RV64-SAME: (<vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmsub.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmsub.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfmsub_vv_f32m8_tu(vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) { vfloat32m8_t test_vfmsub_vv_f32m8_tu(vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfmsub_vv_f32m8_tu(vd, vs1, vs2, vl); return __riscv_vfmsub_vv_f32m8_tu(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmsub_vf_f32m8_tu // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmsub_vf_f32m8_tu
// CHECK-RV64-SAME: (<vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmsub.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmsub.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfmsub_vf_f32m8_tu(vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) { vfloat32m8_t test_vfmsub_vf_f32m8_tu(vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfmsub_vf_f32m8_tu(vd, rs1, vs2, vl); return __riscv_vfmsub_vf_f32m8_tu(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmsub_vv_f64m1_tu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmsub_vv_f64m1_tu
// CHECK-RV64-SAME: (<vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmsub.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmsub.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfmsub_vv_f64m1_tu(vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) { vfloat64m1_t test_vfmsub_vv_f64m1_tu(vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfmsub_vv_f64m1_tu(vd, vs1, vs2, vl); return __riscv_vfmsub_vv_f64m1_tu(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmsub_vf_f64m1_tu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmsub_vf_f64m1_tu
// CHECK-RV64-SAME: (<vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmsub.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmsub.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfmsub_vf_f64m1_tu(vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) { vfloat64m1_t test_vfmsub_vf_f64m1_tu(vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfmsub_vf_f64m1_tu(vd, rs1, vs2, vl); return __riscv_vfmsub_vf_f64m1_tu(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmsub_vv_f64m2_tu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmsub_vv_f64m2_tu
// CHECK-RV64-SAME: (<vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmsub.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmsub.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfmsub_vv_f64m2_tu(vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) { vfloat64m2_t test_vfmsub_vv_f64m2_tu(vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfmsub_vv_f64m2_tu(vd, vs1, vs2, vl); return __riscv_vfmsub_vv_f64m2_tu(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmsub_vf_f64m2_tu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmsub_vf_f64m2_tu
// CHECK-RV64-SAME: (<vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmsub.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmsub.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfmsub_vf_f64m2_tu(vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) { vfloat64m2_t test_vfmsub_vf_f64m2_tu(vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfmsub_vf_f64m2_tu(vd, rs1, vs2, vl); return __riscv_vfmsub_vf_f64m2_tu(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmsub_vv_f64m4_tu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmsub_vv_f64m4_tu
// CHECK-RV64-SAME: (<vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmsub.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmsub.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfmsub_vv_f64m4_tu(vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) { vfloat64m4_t test_vfmsub_vv_f64m4_tu(vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfmsub_vv_f64m4_tu(vd, vs1, vs2, vl); return __riscv_vfmsub_vv_f64m4_tu(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmsub_vf_f64m4_tu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmsub_vf_f64m4_tu
// CHECK-RV64-SAME: (<vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmsub.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmsub.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfmsub_vf_f64m4_tu(vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) { vfloat64m4_t test_vfmsub_vf_f64m4_tu(vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfmsub_vf_f64m4_tu(vd, rs1, vs2, vl); return __riscv_vfmsub_vf_f64m4_tu(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmsub_vv_f64m8_tu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmsub_vv_f64m8_tu
// CHECK-RV64-SAME: (<vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmsub.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmsub.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfmsub_vv_f64m8_tu(vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) { vfloat64m8_t test_vfmsub_vv_f64m8_tu(vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfmsub_vv_f64m8_tu(vd, vs1, vs2, vl); return __riscv_vfmsub_vv_f64m8_tu(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmsub_vf_f64m8_tu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmsub_vf_f64m8_tu
// CHECK-RV64-SAME: (<vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmsub.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmsub.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfmsub_vf_f64m8_tu(vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) { vfloat64m8_t test_vfmsub_vf_f64m8_tu(vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfmsub_vf_f64m8_tu(vd, rs1, vs2, vl); return __riscv_vfmsub_vf_f64m8_tu(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmsub_vv_f16mf4_tum // CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmsub_vv_f16mf4_tum
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmsub.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmsub.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
// //
vfloat16mf4_t test_vfmsub_vv_f16mf4_tum(vbool64_t mask, vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) { vfloat16mf4_t test_vfmsub_vv_f16mf4_tum(vbool64_t mask, vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfmsub_vv_f16mf4_tum(mask, vd, vs1, vs2, vl); return __riscv_vfmsub_vv_f16mf4_tum(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmsub_vf_f16mf4_tum // CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmsub_vf_f16mf4_tum
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmsub.mask.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmsub.mask.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
// //
vfloat16mf4_t test_vfmsub_vf_f16mf4_tum(vbool64_t mask, vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) { vfloat16mf4_t test_vfmsub_vf_f16mf4_tum(vbool64_t mask, vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfmsub_vf_f16mf4_tum(mask, vd, rs1, vs2, vl); return __riscv_vfmsub_vf_f16mf4_tum(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmsub_vv_f16mf2_tum // CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmsub_vv_f16mf2_tum
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmsub.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmsub.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
// //
vfloat16mf2_t test_vfmsub_vv_f16mf2_tum(vbool32_t mask, vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) { vfloat16mf2_t test_vfmsub_vv_f16mf2_tum(vbool32_t mask, vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfmsub_vv_f16mf2_tum(mask, vd, vs1, vs2, vl); return __riscv_vfmsub_vv_f16mf2_tum(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmsub_vf_f16mf2_tum // CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmsub_vf_f16mf2_tum
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmsub.mask.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmsub.mask.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
// //
vfloat16mf2_t test_vfmsub_vf_f16mf2_tum(vbool32_t mask, vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) { vfloat16mf2_t test_vfmsub_vf_f16mf2_tum(vbool32_t mask, vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfmsub_vf_f16mf2_tum(mask, vd, rs1, vs2, vl); return __riscv_vfmsub_vf_f16mf2_tum(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmsub_vv_f16m1_tum // CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmsub_vv_f16m1_tum
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmsub.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmsub.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
// //
vfloat16m1_t test_vfmsub_vv_f16m1_tum(vbool16_t mask, vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) { vfloat16m1_t test_vfmsub_vv_f16m1_tum(vbool16_t mask, vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfmsub_vv_f16m1_tum(mask, vd, vs1, vs2, vl); return __riscv_vfmsub_vv_f16m1_tum(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmsub_vf_f16m1_tum // CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmsub_vf_f16m1_tum
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmsub.mask.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmsub.mask.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
// //
vfloat16m1_t test_vfmsub_vf_f16m1_tum(vbool16_t mask, vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) { vfloat16m1_t test_vfmsub_vf_f16m1_tum(vbool16_t mask, vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfmsub_vf_f16m1_tum(mask, vd, rs1, vs2, vl); return __riscv_vfmsub_vf_f16m1_tum(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmsub_vv_f16m2_tum // CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmsub_vv_f16m2_tum
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmsub.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmsub.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
// //
vfloat16m2_t test_vfmsub_vv_f16m2_tum(vbool8_t mask, vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) { vfloat16m2_t test_vfmsub_vv_f16m2_tum(vbool8_t mask, vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfmsub_vv_f16m2_tum(mask, vd, vs1, vs2, vl); return __riscv_vfmsub_vv_f16m2_tum(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmsub_vf_f16m2_tum // CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmsub_vf_f16m2_tum
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmsub.mask.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmsub.mask.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
// //
vfloat16m2_t test_vfmsub_vf_f16m2_tum(vbool8_t mask, vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) { vfloat16m2_t test_vfmsub_vf_f16m2_tum(vbool8_t mask, vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfmsub_vf_f16m2_tum(mask, vd, rs1, vs2, vl); return __riscv_vfmsub_vf_f16m2_tum(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmsub_vv_f16m4_tum // CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmsub_vv_f16m4_tum
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmsub.mask.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmsub.mask.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
// //
vfloat16m4_t test_vfmsub_vv_f16m4_tum(vbool4_t mask, vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) { vfloat16m4_t test_vfmsub_vv_f16m4_tum(vbool4_t mask, vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfmsub_vv_f16m4_tum(mask, vd, vs1, vs2, vl); return __riscv_vfmsub_vv_f16m4_tum(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmsub_vf_f16m4_tum // CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmsub_vf_f16m4_tum
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmsub.mask.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmsub.mask.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
// //
vfloat16m4_t test_vfmsub_vf_f16m4_tum(vbool4_t mask, vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) { vfloat16m4_t test_vfmsub_vf_f16m4_tum(vbool4_t mask, vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfmsub_vf_f16m4_tum(mask, vd, rs1, vs2, vl); return __riscv_vfmsub_vf_f16m4_tum(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmsub_vv_f16m8_tum // CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmsub_vv_f16m8_tum
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmsub.mask.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmsub.mask.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
// //
vfloat16m8_t test_vfmsub_vv_f16m8_tum(vbool2_t mask, vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) { vfloat16m8_t test_vfmsub_vv_f16m8_tum(vbool2_t mask, vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfmsub_vv_f16m8_tum(mask, vd, vs1, vs2, vl); return __riscv_vfmsub_vv_f16m8_tum(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmsub_vf_f16m8_tum // CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmsub_vf_f16m8_tum
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmsub.mask.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmsub.mask.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
// //
vfloat16m8_t test_vfmsub_vf_f16m8_tum(vbool2_t mask, vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) { vfloat16m8_t test_vfmsub_vf_f16m8_tum(vbool2_t mask, vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfmsub_vf_f16m8_tum(mask, vd, rs1, vs2, vl); return __riscv_vfmsub_vf_f16m8_tum(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmsub_vv_f32mf2_tum // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmsub_vv_f32mf2_tum
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmsub.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmsub.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfmsub_vv_f32mf2_tum(vbool64_t mask, vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) { vfloat32mf2_t test_vfmsub_vv_f32mf2_tum(vbool64_t mask, vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfmsub_vv_f32mf2_tum(mask, vd, vs1, vs2, vl); return __riscv_vfmsub_vv_f32mf2_tum(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmsub_vf_f32mf2_tum // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmsub_vf_f32mf2_tum
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmsub.mask.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmsub.mask.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfmsub_vf_f32mf2_tum(vbool64_t mask, vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) { vfloat32mf2_t test_vfmsub_vf_f32mf2_tum(vbool64_t mask, vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfmsub_vf_f32mf2_tum(mask, vd, rs1, vs2, vl); return __riscv_vfmsub_vf_f32mf2_tum(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmsub_vv_f32m1_tum // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmsub_vv_f32m1_tum
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmsub.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmsub.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfmsub_vv_f32m1_tum(vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) { vfloat32m1_t test_vfmsub_vv_f32m1_tum(vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfmsub_vv_f32m1_tum(mask, vd, vs1, vs2, vl); return __riscv_vfmsub_vv_f32m1_tum(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmsub_vf_f32m1_tum // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmsub_vf_f32m1_tum
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmsub.mask.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmsub.mask.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfmsub_vf_f32m1_tum(vbool32_t mask, vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) { vfloat32m1_t test_vfmsub_vf_f32m1_tum(vbool32_t mask, vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfmsub_vf_f32m1_tum(mask, vd, rs1, vs2, vl); return __riscv_vfmsub_vf_f32m1_tum(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmsub_vv_f32m2_tum // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmsub_vv_f32m2_tum
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmsub.mask.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmsub.mask.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfmsub_vv_f32m2_tum(vbool16_t mask, vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) { vfloat32m2_t test_vfmsub_vv_f32m2_tum(vbool16_t mask, vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfmsub_vv_f32m2_tum(mask, vd, vs1, vs2, vl); return __riscv_vfmsub_vv_f32m2_tum(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmsub_vf_f32m2_tum // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmsub_vf_f32m2_tum
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmsub.mask.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmsub.mask.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfmsub_vf_f32m2_tum(vbool16_t mask, vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) { vfloat32m2_t test_vfmsub_vf_f32m2_tum(vbool16_t mask, vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfmsub_vf_f32m2_tum(mask, vd, rs1, vs2, vl); return __riscv_vfmsub_vf_f32m2_tum(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmsub_vv_f32m4_tum // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmsub_vv_f32m4_tum
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmsub.mask.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmsub.mask.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfmsub_vv_f32m4_tum(vbool8_t mask, vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) { vfloat32m4_t test_vfmsub_vv_f32m4_tum(vbool8_t mask, vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfmsub_vv_f32m4_tum(mask, vd, vs1, vs2, vl); return __riscv_vfmsub_vv_f32m4_tum(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmsub_vf_f32m4_tum // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmsub_vf_f32m4_tum
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmsub.mask.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmsub.mask.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfmsub_vf_f32m4_tum(vbool8_t mask, vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) { vfloat32m4_t test_vfmsub_vf_f32m4_tum(vbool8_t mask, vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfmsub_vf_f32m4_tum(mask, vd, rs1, vs2, vl); return __riscv_vfmsub_vf_f32m4_tum(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmsub_vv_f32m8_tum // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmsub_vv_f32m8_tum
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmsub.mask.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmsub.mask.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfmsub_vv_f32m8_tum(vbool4_t mask, vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) { vfloat32m8_t test_vfmsub_vv_f32m8_tum(vbool4_t mask, vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfmsub_vv_f32m8_tum(mask, vd, vs1, vs2, vl); return __riscv_vfmsub_vv_f32m8_tum(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmsub_vf_f32m8_tum // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmsub_vf_f32m8_tum
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmsub.mask.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmsub.mask.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfmsub_vf_f32m8_tum(vbool4_t mask, vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) { vfloat32m8_t test_vfmsub_vf_f32m8_tum(vbool4_t mask, vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfmsub_vf_f32m8_tum(mask, vd, rs1, vs2, vl); return __riscv_vfmsub_vf_f32m8_tum(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmsub_vv_f64m1_tum // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmsub_vv_f64m1_tum
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmsub.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmsub.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfmsub_vv_f64m1_tum(vbool64_t mask, vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) { vfloat64m1_t test_vfmsub_vv_f64m1_tum(vbool64_t mask, vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfmsub_vv_f64m1_tum(mask, vd, vs1, vs2, vl); return __riscv_vfmsub_vv_f64m1_tum(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmsub_vf_f64m1_tum // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmsub_vf_f64m1_tum
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmsub.mask.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmsub.mask.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfmsub_vf_f64m1_tum(vbool64_t mask, vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) { vfloat64m1_t test_vfmsub_vf_f64m1_tum(vbool64_t mask, vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfmsub_vf_f64m1_tum(mask, vd, rs1, vs2, vl); return __riscv_vfmsub_vf_f64m1_tum(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmsub_vv_f64m2_tum // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmsub_vv_f64m2_tum
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmsub.mask.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmsub.mask.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfmsub_vv_f64m2_tum(vbool32_t mask, vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) { vfloat64m2_t test_vfmsub_vv_f64m2_tum(vbool32_t mask, vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfmsub_vv_f64m2_tum(mask, vd, vs1, vs2, vl); return __riscv_vfmsub_vv_f64m2_tum(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmsub_vf_f64m2_tum // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmsub_vf_f64m2_tum
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmsub.mask.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmsub.mask.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfmsub_vf_f64m2_tum(vbool32_t mask, vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) { vfloat64m2_t test_vfmsub_vf_f64m2_tum(vbool32_t mask, vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfmsub_vf_f64m2_tum(mask, vd, rs1, vs2, vl); return __riscv_vfmsub_vf_f64m2_tum(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmsub_vv_f64m4_tum // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmsub_vv_f64m4_tum
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmsub.mask.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmsub.mask.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfmsub_vv_f64m4_tum(vbool16_t mask, vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) { vfloat64m4_t test_vfmsub_vv_f64m4_tum(vbool16_t mask, vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfmsub_vv_f64m4_tum(mask, vd, vs1, vs2, vl); return __riscv_vfmsub_vv_f64m4_tum(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmsub_vf_f64m4_tum // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmsub_vf_f64m4_tum
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmsub.mask.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmsub.mask.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfmsub_vf_f64m4_tum(vbool16_t mask, vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) { vfloat64m4_t test_vfmsub_vf_f64m4_tum(vbool16_t mask, vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfmsub_vf_f64m4_tum(mask, vd, rs1, vs2, vl); return __riscv_vfmsub_vf_f64m4_tum(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmsub_vv_f64m8_tum // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmsub_vv_f64m8_tum
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmsub.mask.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmsub.mask.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfmsub_vv_f64m8_tum(vbool8_t mask, vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) { vfloat64m8_t test_vfmsub_vv_f64m8_tum(vbool8_t mask, vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfmsub_vv_f64m8_tum(mask, vd, vs1, vs2, vl); return __riscv_vfmsub_vv_f64m8_tum(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmsub_vf_f64m8_tum // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmsub_vf_f64m8_tum
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmsub.mask.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmsub.mask.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfmsub_vf_f64m8_tum(vbool8_t mask, vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) { vfloat64m8_t test_vfmsub_vf_f64m8_tum(vbool8_t mask, vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfmsub_vf_f64m8_tum(mask, vd, rs1, vs2, vl); return __riscv_vfmsub_vf_f64m8_tum(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmsub_vv_f16mf4_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmsub_vv_f16mf4_tumu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmsub.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmsub.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
// //
vfloat16mf4_t test_vfmsub_vv_f16mf4_tumu(vbool64_t mask, vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) { vfloat16mf4_t test_vfmsub_vv_f16mf4_tumu(vbool64_t mask, vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfmsub_vv_f16mf4_tumu(mask, vd, vs1, vs2, vl); return __riscv_vfmsub_vv_f16mf4_tumu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmsub_vf_f16mf4_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmsub_vf_f16mf4_tumu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmsub.mask.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmsub.mask.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
// //
vfloat16mf4_t test_vfmsub_vf_f16mf4_tumu(vbool64_t mask, vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) { vfloat16mf4_t test_vfmsub_vf_f16mf4_tumu(vbool64_t mask, vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfmsub_vf_f16mf4_tumu(mask, vd, rs1, vs2, vl); return __riscv_vfmsub_vf_f16mf4_tumu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmsub_vv_f16mf2_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmsub_vv_f16mf2_tumu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmsub.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmsub.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
// //
vfloat16mf2_t test_vfmsub_vv_f16mf2_tumu(vbool32_t mask, vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) { vfloat16mf2_t test_vfmsub_vv_f16mf2_tumu(vbool32_t mask, vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfmsub_vv_f16mf2_tumu(mask, vd, vs1, vs2, vl); return __riscv_vfmsub_vv_f16mf2_tumu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmsub_vf_f16mf2_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmsub_vf_f16mf2_tumu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmsub.mask.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmsub.mask.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
// //
vfloat16mf2_t test_vfmsub_vf_f16mf2_tumu(vbool32_t mask, vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) { vfloat16mf2_t test_vfmsub_vf_f16mf2_tumu(vbool32_t mask, vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfmsub_vf_f16mf2_tumu(mask, vd, rs1, vs2, vl); return __riscv_vfmsub_vf_f16mf2_tumu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmsub_vv_f16m1_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmsub_vv_f16m1_tumu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmsub.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmsub.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
// //
vfloat16m1_t test_vfmsub_vv_f16m1_tumu(vbool16_t mask, vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) { vfloat16m1_t test_vfmsub_vv_f16m1_tumu(vbool16_t mask, vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfmsub_vv_f16m1_tumu(mask, vd, vs1, vs2, vl); return __riscv_vfmsub_vv_f16m1_tumu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmsub_vf_f16m1_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmsub_vf_f16m1_tumu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmsub.mask.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmsub.mask.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
// //
vfloat16m1_t test_vfmsub_vf_f16m1_tumu(vbool16_t mask, vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) { vfloat16m1_t test_vfmsub_vf_f16m1_tumu(vbool16_t mask, vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfmsub_vf_f16m1_tumu(mask, vd, rs1, vs2, vl); return __riscv_vfmsub_vf_f16m1_tumu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmsub_vv_f16m2_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmsub_vv_f16m2_tumu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmsub.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmsub.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
// //
vfloat16m2_t test_vfmsub_vv_f16m2_tumu(vbool8_t mask, vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) { vfloat16m2_t test_vfmsub_vv_f16m2_tumu(vbool8_t mask, vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfmsub_vv_f16m2_tumu(mask, vd, vs1, vs2, vl); return __riscv_vfmsub_vv_f16m2_tumu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmsub_vf_f16m2_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmsub_vf_f16m2_tumu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmsub.mask.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmsub.mask.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
// //
vfloat16m2_t test_vfmsub_vf_f16m2_tumu(vbool8_t mask, vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) { vfloat16m2_t test_vfmsub_vf_f16m2_tumu(vbool8_t mask, vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfmsub_vf_f16m2_tumu(mask, vd, rs1, vs2, vl); return __riscv_vfmsub_vf_f16m2_tumu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmsub_vv_f16m4_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmsub_vv_f16m4_tumu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmsub.mask.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmsub.mask.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
// //
vfloat16m4_t test_vfmsub_vv_f16m4_tumu(vbool4_t mask, vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) { vfloat16m4_t test_vfmsub_vv_f16m4_tumu(vbool4_t mask, vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfmsub_vv_f16m4_tumu(mask, vd, vs1, vs2, vl); return __riscv_vfmsub_vv_f16m4_tumu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmsub_vf_f16m4_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmsub_vf_f16m4_tumu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmsub.mask.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmsub.mask.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
// //
vfloat16m4_t test_vfmsub_vf_f16m4_tumu(vbool4_t mask, vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) { vfloat16m4_t test_vfmsub_vf_f16m4_tumu(vbool4_t mask, vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfmsub_vf_f16m4_tumu(mask, vd, rs1, vs2, vl); return __riscv_vfmsub_vf_f16m4_tumu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmsub_vv_f16m8_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmsub_vv_f16m8_tumu
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmsub.mask.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmsub.mask.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
// //
vfloat16m8_t test_vfmsub_vv_f16m8_tumu(vbool2_t mask, vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) { vfloat16m8_t test_vfmsub_vv_f16m8_tumu(vbool2_t mask, vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfmsub_vv_f16m8_tumu(mask, vd, vs1, vs2, vl); return __riscv_vfmsub_vv_f16m8_tumu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmsub_vf_f16m8_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmsub_vf_f16m8_tumu
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmsub.mask.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmsub.mask.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
// //
vfloat16m8_t test_vfmsub_vf_f16m8_tumu(vbool2_t mask, vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) { vfloat16m8_t test_vfmsub_vf_f16m8_tumu(vbool2_t mask, vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfmsub_vf_f16m8_tumu(mask, vd, rs1, vs2, vl); return __riscv_vfmsub_vf_f16m8_tumu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmsub_vv_f32mf2_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmsub_vv_f32mf2_tumu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmsub.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmsub.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfmsub_vv_f32mf2_tumu(vbool64_t mask, vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) { vfloat32mf2_t test_vfmsub_vv_f32mf2_tumu(vbool64_t mask, vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfmsub_vv_f32mf2_tumu(mask, vd, vs1, vs2, vl); return __riscv_vfmsub_vv_f32mf2_tumu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmsub_vf_f32mf2_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmsub_vf_f32mf2_tumu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmsub.mask.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmsub.mask.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfmsub_vf_f32mf2_tumu(vbool64_t mask, vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) { vfloat32mf2_t test_vfmsub_vf_f32mf2_tumu(vbool64_t mask, vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfmsub_vf_f32mf2_tumu(mask, vd, rs1, vs2, vl); return __riscv_vfmsub_vf_f32mf2_tumu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmsub_vv_f32m1_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmsub_vv_f32m1_tumu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmsub.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmsub.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfmsub_vv_f32m1_tumu(vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) { vfloat32m1_t test_vfmsub_vv_f32m1_tumu(vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfmsub_vv_f32m1_tumu(mask, vd, vs1, vs2, vl); return __riscv_vfmsub_vv_f32m1_tumu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmsub_vf_f32m1_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmsub_vf_f32m1_tumu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmsub.mask.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmsub.mask.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfmsub_vf_f32m1_tumu(vbool32_t mask, vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) { vfloat32m1_t test_vfmsub_vf_f32m1_tumu(vbool32_t mask, vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfmsub_vf_f32m1_tumu(mask, vd, rs1, vs2, vl); return __riscv_vfmsub_vf_f32m1_tumu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmsub_vv_f32m2_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmsub_vv_f32m2_tumu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmsub.mask.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmsub.mask.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfmsub_vv_f32m2_tumu(vbool16_t mask, vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) { vfloat32m2_t test_vfmsub_vv_f32m2_tumu(vbool16_t mask, vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfmsub_vv_f32m2_tumu(mask, vd, vs1, vs2, vl); return __riscv_vfmsub_vv_f32m2_tumu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmsub_vf_f32m2_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmsub_vf_f32m2_tumu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmsub.mask.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmsub.mask.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfmsub_vf_f32m2_tumu(vbool16_t mask, vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) { vfloat32m2_t test_vfmsub_vf_f32m2_tumu(vbool16_t mask, vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfmsub_vf_f32m2_tumu(mask, vd, rs1, vs2, vl); return __riscv_vfmsub_vf_f32m2_tumu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmsub_vv_f32m4_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmsub_vv_f32m4_tumu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmsub.mask.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmsub.mask.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfmsub_vv_f32m4_tumu(vbool8_t mask, vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) { vfloat32m4_t test_vfmsub_vv_f32m4_tumu(vbool8_t mask, vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfmsub_vv_f32m4_tumu(mask, vd, vs1, vs2, vl); return __riscv_vfmsub_vv_f32m4_tumu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmsub_vf_f32m4_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmsub_vf_f32m4_tumu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmsub.mask.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmsub.mask.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfmsub_vf_f32m4_tumu(vbool8_t mask, vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) { vfloat32m4_t test_vfmsub_vf_f32m4_tumu(vbool8_t mask, vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfmsub_vf_f32m4_tumu(mask, vd, rs1, vs2, vl); return __riscv_vfmsub_vf_f32m4_tumu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmsub_vv_f32m8_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmsub_vv_f32m8_tumu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmsub.mask.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmsub.mask.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfmsub_vv_f32m8_tumu(vbool4_t mask, vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) { vfloat32m8_t test_vfmsub_vv_f32m8_tumu(vbool4_t mask, vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfmsub_vv_f32m8_tumu(mask, vd, vs1, vs2, vl); return __riscv_vfmsub_vv_f32m8_tumu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmsub_vf_f32m8_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmsub_vf_f32m8_tumu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmsub.mask.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmsub.mask.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfmsub_vf_f32m8_tumu(vbool4_t mask, vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) { vfloat32m8_t test_vfmsub_vf_f32m8_tumu(vbool4_t mask, vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfmsub_vf_f32m8_tumu(mask, vd, rs1, vs2, vl); return __riscv_vfmsub_vf_f32m8_tumu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmsub_vv_f64m1_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmsub_vv_f64m1_tumu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmsub.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmsub.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfmsub_vv_f64m1_tumu(vbool64_t mask, vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) { vfloat64m1_t test_vfmsub_vv_f64m1_tumu(vbool64_t mask, vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfmsub_vv_f64m1_tumu(mask, vd, vs1, vs2, vl); return __riscv_vfmsub_vv_f64m1_tumu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmsub_vf_f64m1_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmsub_vf_f64m1_tumu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmsub.mask.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmsub.mask.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfmsub_vf_f64m1_tumu(vbool64_t mask, vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) { vfloat64m1_t test_vfmsub_vf_f64m1_tumu(vbool64_t mask, vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfmsub_vf_f64m1_tumu(mask, vd, rs1, vs2, vl); return __riscv_vfmsub_vf_f64m1_tumu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmsub_vv_f64m2_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmsub_vv_f64m2_tumu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmsub.mask.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmsub.mask.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfmsub_vv_f64m2_tumu(vbool32_t mask, vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) { vfloat64m2_t test_vfmsub_vv_f64m2_tumu(vbool32_t mask, vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfmsub_vv_f64m2_tumu(mask, vd, vs1, vs2, vl); return __riscv_vfmsub_vv_f64m2_tumu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmsub_vf_f64m2_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmsub_vf_f64m2_tumu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmsub.mask.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmsub.mask.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfmsub_vf_f64m2_tumu(vbool32_t mask, vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) { vfloat64m2_t test_vfmsub_vf_f64m2_tumu(vbool32_t mask, vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfmsub_vf_f64m2_tumu(mask, vd, rs1, vs2, vl); return __riscv_vfmsub_vf_f64m2_tumu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmsub_vv_f64m4_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmsub_vv_f64m4_tumu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmsub.mask.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmsub.mask.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfmsub_vv_f64m4_tumu(vbool16_t mask, vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) { vfloat64m4_t test_vfmsub_vv_f64m4_tumu(vbool16_t mask, vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfmsub_vv_f64m4_tumu(mask, vd, vs1, vs2, vl); return __riscv_vfmsub_vv_f64m4_tumu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmsub_vf_f64m4_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmsub_vf_f64m4_tumu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmsub.mask.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmsub.mask.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfmsub_vf_f64m4_tumu(vbool16_t mask, vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) { vfloat64m4_t test_vfmsub_vf_f64m4_tumu(vbool16_t mask, vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfmsub_vf_f64m4_tumu(mask, vd, rs1, vs2, vl); return __riscv_vfmsub_vf_f64m4_tumu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmsub_vv_f64m8_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmsub_vv_f64m8_tumu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmsub.mask.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmsub.mask.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfmsub_vv_f64m8_tumu(vbool8_t mask, vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) { vfloat64m8_t test_vfmsub_vv_f64m8_tumu(vbool8_t mask, vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfmsub_vv_f64m8_tumu(mask, vd, vs1, vs2, vl); return __riscv_vfmsub_vv_f64m8_tumu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmsub_vf_f64m8_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmsub_vf_f64m8_tumu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmsub.mask.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmsub.mask.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfmsub_vf_f64m8_tumu(vbool8_t mask, vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) { vfloat64m8_t test_vfmsub_vf_f64m8_tumu(vbool8_t mask, vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfmsub_vf_f64m8_tumu(mask, vd, rs1, vs2, vl); return __riscv_vfmsub_vf_f64m8_tumu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmsub_vv_f16mf4_mu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmsub_vv_f16mf4_mu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmsub.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmsub.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
// //
vfloat16mf4_t test_vfmsub_vv_f16mf4_mu(vbool64_t mask, vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) { vfloat16mf4_t test_vfmsub_vv_f16mf4_mu(vbool64_t mask, vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfmsub_vv_f16mf4_mu(mask, vd, vs1, vs2, vl); return __riscv_vfmsub_vv_f16mf4_mu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmsub_vf_f16mf4_mu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmsub_vf_f16mf4_mu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmsub.mask.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmsub.mask.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
// //
vfloat16mf4_t test_vfmsub_vf_f16mf4_mu(vbool64_t mask, vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) { vfloat16mf4_t test_vfmsub_vf_f16mf4_mu(vbool64_t mask, vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfmsub_vf_f16mf4_mu(mask, vd, rs1, vs2, vl); return __riscv_vfmsub_vf_f16mf4_mu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmsub_vv_f16mf2_mu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmsub_vv_f16mf2_mu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmsub.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmsub.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
// //
vfloat16mf2_t test_vfmsub_vv_f16mf2_mu(vbool32_t mask, vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) { vfloat16mf2_t test_vfmsub_vv_f16mf2_mu(vbool32_t mask, vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfmsub_vv_f16mf2_mu(mask, vd, vs1, vs2, vl); return __riscv_vfmsub_vv_f16mf2_mu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmsub_vf_f16mf2_mu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmsub_vf_f16mf2_mu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmsub.mask.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmsub.mask.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
// //
vfloat16mf2_t test_vfmsub_vf_f16mf2_mu(vbool32_t mask, vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) { vfloat16mf2_t test_vfmsub_vf_f16mf2_mu(vbool32_t mask, vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfmsub_vf_f16mf2_mu(mask, vd, rs1, vs2, vl); return __riscv_vfmsub_vf_f16mf2_mu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmsub_vv_f16m1_mu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmsub_vv_f16m1_mu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmsub.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmsub.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
// //
vfloat16m1_t test_vfmsub_vv_f16m1_mu(vbool16_t mask, vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) { vfloat16m1_t test_vfmsub_vv_f16m1_mu(vbool16_t mask, vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfmsub_vv_f16m1_mu(mask, vd, vs1, vs2, vl); return __riscv_vfmsub_vv_f16m1_mu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmsub_vf_f16m1_mu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmsub_vf_f16m1_mu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmsub.mask.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmsub.mask.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
// //
vfloat16m1_t test_vfmsub_vf_f16m1_mu(vbool16_t mask, vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) { vfloat16m1_t test_vfmsub_vf_f16m1_mu(vbool16_t mask, vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfmsub_vf_f16m1_mu(mask, vd, rs1, vs2, vl); return __riscv_vfmsub_vf_f16m1_mu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmsub_vv_f16m2_mu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmsub_vv_f16m2_mu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmsub.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmsub.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
// //
vfloat16m2_t test_vfmsub_vv_f16m2_mu(vbool8_t mask, vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) { vfloat16m2_t test_vfmsub_vv_f16m2_mu(vbool8_t mask, vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfmsub_vv_f16m2_mu(mask, vd, vs1, vs2, vl); return __riscv_vfmsub_vv_f16m2_mu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmsub_vf_f16m2_mu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmsub_vf_f16m2_mu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmsub.mask.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmsub.mask.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
// //
vfloat16m2_t test_vfmsub_vf_f16m2_mu(vbool8_t mask, vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) { vfloat16m2_t test_vfmsub_vf_f16m2_mu(vbool8_t mask, vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfmsub_vf_f16m2_mu(mask, vd, rs1, vs2, vl); return __riscv_vfmsub_vf_f16m2_mu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmsub_vv_f16m4_mu // CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmsub_vv_f16m4_mu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmsub.mask.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmsub.mask.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
// //
vfloat16m4_t test_vfmsub_vv_f16m4_mu(vbool4_t mask, vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) { vfloat16m4_t test_vfmsub_vv_f16m4_mu(vbool4_t mask, vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfmsub_vv_f16m4_mu(mask, vd, vs1, vs2, vl); return __riscv_vfmsub_vv_f16m4_mu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmsub_vf_f16m4_mu // CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmsub_vf_f16m4_mu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmsub.mask.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmsub.mask.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
// //
vfloat16m4_t test_vfmsub_vf_f16m4_mu(vbool4_t mask, vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) { vfloat16m4_t test_vfmsub_vf_f16m4_mu(vbool4_t mask, vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfmsub_vf_f16m4_mu(mask, vd, rs1, vs2, vl); return __riscv_vfmsub_vf_f16m4_mu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmsub_vv_f16m8_mu // CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmsub_vv_f16m8_mu
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmsub.mask.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmsub.mask.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
// //
vfloat16m8_t test_vfmsub_vv_f16m8_mu(vbool2_t mask, vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) { vfloat16m8_t test_vfmsub_vv_f16m8_mu(vbool2_t mask, vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfmsub_vv_f16m8_mu(mask, vd, vs1, vs2, vl); return __riscv_vfmsub_vv_f16m8_mu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmsub_vf_f16m8_mu // CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmsub_vf_f16m8_mu
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmsub.mask.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmsub.mask.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
// //
vfloat16m8_t test_vfmsub_vf_f16m8_mu(vbool2_t mask, vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) { vfloat16m8_t test_vfmsub_vf_f16m8_mu(vbool2_t mask, vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfmsub_vf_f16m8_mu(mask, vd, rs1, vs2, vl); return __riscv_vfmsub_vf_f16m8_mu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmsub_vv_f32mf2_mu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmsub_vv_f32mf2_mu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmsub.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmsub.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfmsub_vv_f32mf2_mu(vbool64_t mask, vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) { vfloat32mf2_t test_vfmsub_vv_f32mf2_mu(vbool64_t mask, vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfmsub_vv_f32mf2_mu(mask, vd, vs1, vs2, vl); return __riscv_vfmsub_vv_f32mf2_mu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmsub_vf_f32mf2_mu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmsub_vf_f32mf2_mu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmsub.mask.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmsub.mask.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfmsub_vf_f32mf2_mu(vbool64_t mask, vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) { vfloat32mf2_t test_vfmsub_vf_f32mf2_mu(vbool64_t mask, vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfmsub_vf_f32mf2_mu(mask, vd, rs1, vs2, vl); return __riscv_vfmsub_vf_f32mf2_mu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmsub_vv_f32m1_mu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmsub_vv_f32m1_mu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmsub.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmsub.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfmsub_vv_f32m1_mu(vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) { vfloat32m1_t test_vfmsub_vv_f32m1_mu(vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfmsub_vv_f32m1_mu(mask, vd, vs1, vs2, vl); return __riscv_vfmsub_vv_f32m1_mu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmsub_vf_f32m1_mu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmsub_vf_f32m1_mu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmsub.mask.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmsub.mask.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfmsub_vf_f32m1_mu(vbool32_t mask, vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) { vfloat32m1_t test_vfmsub_vf_f32m1_mu(vbool32_t mask, vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfmsub_vf_f32m1_mu(mask, vd, rs1, vs2, vl); return __riscv_vfmsub_vf_f32m1_mu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmsub_vv_f32m2_mu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmsub_vv_f32m2_mu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmsub.mask.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmsub.mask.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfmsub_vv_f32m2_mu(vbool16_t mask, vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) { vfloat32m2_t test_vfmsub_vv_f32m2_mu(vbool16_t mask, vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfmsub_vv_f32m2_mu(mask, vd, vs1, vs2, vl); return __riscv_vfmsub_vv_f32m2_mu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmsub_vf_f32m2_mu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmsub_vf_f32m2_mu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmsub.mask.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmsub.mask.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfmsub_vf_f32m2_mu(vbool16_t mask, vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) { vfloat32m2_t test_vfmsub_vf_f32m2_mu(vbool16_t mask, vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfmsub_vf_f32m2_mu(mask, vd, rs1, vs2, vl); return __riscv_vfmsub_vf_f32m2_mu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmsub_vv_f32m4_mu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmsub_vv_f32m4_mu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmsub.mask.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmsub.mask.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfmsub_vv_f32m4_mu(vbool8_t mask, vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) { vfloat32m4_t test_vfmsub_vv_f32m4_mu(vbool8_t mask, vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfmsub_vv_f32m4_mu(mask, vd, vs1, vs2, vl); return __riscv_vfmsub_vv_f32m4_mu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmsub_vf_f32m4_mu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmsub_vf_f32m4_mu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmsub.mask.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmsub.mask.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfmsub_vf_f32m4_mu(vbool8_t mask, vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) { vfloat32m4_t test_vfmsub_vf_f32m4_mu(vbool8_t mask, vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfmsub_vf_f32m4_mu(mask, vd, rs1, vs2, vl); return __riscv_vfmsub_vf_f32m4_mu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmsub_vv_f32m8_mu // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmsub_vv_f32m8_mu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmsub.mask.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmsub.mask.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfmsub_vv_f32m8_mu(vbool4_t mask, vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) { vfloat32m8_t test_vfmsub_vv_f32m8_mu(vbool4_t mask, vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfmsub_vv_f32m8_mu(mask, vd, vs1, vs2, vl); return __riscv_vfmsub_vv_f32m8_mu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmsub_vf_f32m8_mu // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmsub_vf_f32m8_mu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmsub.mask.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmsub.mask.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfmsub_vf_f32m8_mu(vbool4_t mask, vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) { vfloat32m8_t test_vfmsub_vf_f32m8_mu(vbool4_t mask, vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfmsub_vf_f32m8_mu(mask, vd, rs1, vs2, vl); return __riscv_vfmsub_vf_f32m8_mu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmsub_vv_f64m1_mu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmsub_vv_f64m1_mu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmsub.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmsub.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfmsub_vv_f64m1_mu(vbool64_t mask, vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) { vfloat64m1_t test_vfmsub_vv_f64m1_mu(vbool64_t mask, vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfmsub_vv_f64m1_mu(mask, vd, vs1, vs2, vl); return __riscv_vfmsub_vv_f64m1_mu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmsub_vf_f64m1_mu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmsub_vf_f64m1_mu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmsub.mask.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmsub.mask.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfmsub_vf_f64m1_mu(vbool64_t mask, vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) { vfloat64m1_t test_vfmsub_vf_f64m1_mu(vbool64_t mask, vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfmsub_vf_f64m1_mu(mask, vd, rs1, vs2, vl); return __riscv_vfmsub_vf_f64m1_mu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmsub_vv_f64m2_mu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmsub_vv_f64m2_mu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmsub.mask.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmsub.mask.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfmsub_vv_f64m2_mu(vbool32_t mask, vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) { vfloat64m2_t test_vfmsub_vv_f64m2_mu(vbool32_t mask, vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfmsub_vv_f64m2_mu(mask, vd, vs1, vs2, vl); return __riscv_vfmsub_vv_f64m2_mu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmsub_vf_f64m2_mu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmsub_vf_f64m2_mu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmsub.mask.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmsub.mask.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfmsub_vf_f64m2_mu(vbool32_t mask, vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) { vfloat64m2_t test_vfmsub_vf_f64m2_mu(vbool32_t mask, vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfmsub_vf_f64m2_mu(mask, vd, rs1, vs2, vl); return __riscv_vfmsub_vf_f64m2_mu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmsub_vv_f64m4_mu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmsub_vv_f64m4_mu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmsub.mask.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmsub.mask.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfmsub_vv_f64m4_mu(vbool16_t mask, vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) { vfloat64m4_t test_vfmsub_vv_f64m4_mu(vbool16_t mask, vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfmsub_vv_f64m4_mu(mask, vd, vs1, vs2, vl); return __riscv_vfmsub_vv_f64m4_mu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmsub_vf_f64m4_mu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmsub_vf_f64m4_mu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmsub.mask.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmsub.mask.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfmsub_vf_f64m4_mu(vbool16_t mask, vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) { vfloat64m4_t test_vfmsub_vf_f64m4_mu(vbool16_t mask, vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfmsub_vf_f64m4_mu(mask, vd, rs1, vs2, vl); return __riscv_vfmsub_vf_f64m4_mu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmsub_vv_f64m8_mu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmsub_vv_f64m8_mu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmsub.mask.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmsub.mask.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfmsub_vv_f64m8_mu(vbool8_t mask, vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) { vfloat64m8_t test_vfmsub_vv_f64m8_mu(vbool8_t mask, vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfmsub_vv_f64m8_mu(mask, vd, vs1, vs2, vl); return __riscv_vfmsub_vv_f64m8_mu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmsub_vf_f64m8_mu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmsub_vf_f64m8_mu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmsub.mask.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmsub.mask.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfmsub_vf_f64m8_mu(vbool8_t mask, vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) { vfloat64m8_t test_vfmsub_vf_f64m8_mu(vbool8_t mask, vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfmsub_vf_f64m8_mu(mask, vd, rs1, vs2, vl); return __riscv_vfmsub_vf_f64m8_mu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmsub_vv_f16mf4_rm_tu
// CHECK-RV64-SAME: (<vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmsub.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
//
vfloat16mf4_t test_vfmsub_vv_f16mf4_rm_tu(vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfmsub_vv_f16mf4_rm_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmsub_vf_f16mf4_rm_tu
// CHECK-RV64-SAME: (<vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmsub.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
//
vfloat16mf4_t test_vfmsub_vf_f16mf4_rm_tu(vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfmsub_vf_f16mf4_rm_tu(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmsub_vv_f16mf2_rm_tu
// CHECK-RV64-SAME: (<vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmsub.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
//
vfloat16mf2_t test_vfmsub_vv_f16mf2_rm_tu(vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfmsub_vv_f16mf2_rm_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmsub_vf_f16mf2_rm_tu
// CHECK-RV64-SAME: (<vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmsub.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
//
vfloat16mf2_t test_vfmsub_vf_f16mf2_rm_tu(vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfmsub_vf_f16mf2_rm_tu(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmsub_vv_f16m1_rm_tu
// CHECK-RV64-SAME: (<vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmsub.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfmsub_vv_f16m1_rm_tu(vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfmsub_vv_f16m1_rm_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmsub_vf_f16m1_rm_tu
// CHECK-RV64-SAME: (<vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmsub.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfmsub_vf_f16m1_rm_tu(vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfmsub_vf_f16m1_rm_tu(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmsub_vv_f16m2_rm_tu
// CHECK-RV64-SAME: (<vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmsub.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
//
vfloat16m2_t test_vfmsub_vv_f16m2_rm_tu(vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfmsub_vv_f16m2_rm_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmsub_vf_f16m2_rm_tu
// CHECK-RV64-SAME: (<vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmsub.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
//
vfloat16m2_t test_vfmsub_vf_f16m2_rm_tu(vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfmsub_vf_f16m2_rm_tu(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmsub_vv_f16m4_rm_tu
// CHECK-RV64-SAME: (<vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmsub.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
//
vfloat16m4_t test_vfmsub_vv_f16m4_rm_tu(vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfmsub_vv_f16m4_rm_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmsub_vf_f16m4_rm_tu
// CHECK-RV64-SAME: (<vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmsub.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
//
vfloat16m4_t test_vfmsub_vf_f16m4_rm_tu(vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfmsub_vf_f16m4_rm_tu(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmsub_vv_f16m8_rm_tu
// CHECK-RV64-SAME: (<vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmsub.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
//
vfloat16m8_t test_vfmsub_vv_f16m8_rm_tu(vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfmsub_vv_f16m8_rm_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmsub_vf_f16m8_rm_tu
// CHECK-RV64-SAME: (<vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmsub.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
//
vfloat16m8_t test_vfmsub_vf_f16m8_rm_tu(vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfmsub_vf_f16m8_rm_tu(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmsub_vv_f32mf2_rm_tu
// CHECK-RV64-SAME: (<vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmsub.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
//
vfloat32mf2_t test_vfmsub_vv_f32mf2_rm_tu(vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfmsub_vv_f32mf2_rm_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmsub_vf_f32mf2_rm_tu
// CHECK-RV64-SAME: (<vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmsub.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
//
vfloat32mf2_t test_vfmsub_vf_f32mf2_rm_tu(vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfmsub_vf_f32mf2_rm_tu(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmsub_vv_f32m1_rm_tu
// CHECK-RV64-SAME: (<vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmsub.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfmsub_vv_f32m1_rm_tu(vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfmsub_vv_f32m1_rm_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmsub_vf_f32m1_rm_tu
// CHECK-RV64-SAME: (<vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmsub.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfmsub_vf_f32m1_rm_tu(vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfmsub_vf_f32m1_rm_tu(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmsub_vv_f32m2_rm_tu
// CHECK-RV64-SAME: (<vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmsub.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
//
vfloat32m2_t test_vfmsub_vv_f32m2_rm_tu(vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfmsub_vv_f32m2_rm_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmsub_vf_f32m2_rm_tu
// CHECK-RV64-SAME: (<vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmsub.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
//
vfloat32m2_t test_vfmsub_vf_f32m2_rm_tu(vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfmsub_vf_f32m2_rm_tu(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmsub_vv_f32m4_rm_tu
// CHECK-RV64-SAME: (<vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmsub.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
//
vfloat32m4_t test_vfmsub_vv_f32m4_rm_tu(vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfmsub_vv_f32m4_rm_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmsub_vf_f32m4_rm_tu
// CHECK-RV64-SAME: (<vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmsub.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
//
vfloat32m4_t test_vfmsub_vf_f32m4_rm_tu(vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfmsub_vf_f32m4_rm_tu(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmsub_vv_f32m8_rm_tu
// CHECK-RV64-SAME: (<vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmsub.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
//
vfloat32m8_t test_vfmsub_vv_f32m8_rm_tu(vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfmsub_vv_f32m8_rm_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmsub_vf_f32m8_rm_tu
// CHECK-RV64-SAME: (<vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmsub.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
//
vfloat32m8_t test_vfmsub_vf_f32m8_rm_tu(vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfmsub_vf_f32m8_rm_tu(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmsub_vv_f64m1_rm_tu
// CHECK-RV64-SAME: (<vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmsub.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfmsub_vv_f64m1_rm_tu(vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfmsub_vv_f64m1_rm_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmsub_vf_f64m1_rm_tu
// CHECK-RV64-SAME: (<vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmsub.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfmsub_vf_f64m1_rm_tu(vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfmsub_vf_f64m1_rm_tu(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmsub_vv_f64m2_rm_tu
// CHECK-RV64-SAME: (<vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmsub.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
//
vfloat64m2_t test_vfmsub_vv_f64m2_rm_tu(vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfmsub_vv_f64m2_rm_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmsub_vf_f64m2_rm_tu
// CHECK-RV64-SAME: (<vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmsub.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
//
vfloat64m2_t test_vfmsub_vf_f64m2_rm_tu(vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfmsub_vf_f64m2_rm_tu(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmsub_vv_f64m4_rm_tu
// CHECK-RV64-SAME: (<vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmsub.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
//
vfloat64m4_t test_vfmsub_vv_f64m4_rm_tu(vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfmsub_vv_f64m4_rm_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmsub_vf_f64m4_rm_tu
// CHECK-RV64-SAME: (<vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmsub.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
//
vfloat64m4_t test_vfmsub_vf_f64m4_rm_tu(vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfmsub_vf_f64m4_rm_tu(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmsub_vv_f64m8_rm_tu
// CHECK-RV64-SAME: (<vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmsub.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
//
vfloat64m8_t test_vfmsub_vv_f64m8_rm_tu(vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfmsub_vv_f64m8_rm_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmsub_vf_f64m8_rm_tu
// CHECK-RV64-SAME: (<vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmsub.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
//
vfloat64m8_t test_vfmsub_vf_f64m8_rm_tu(vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfmsub_vf_f64m8_rm_tu(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmsub_vv_f16mf4_rm_tum
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmsub.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
//
vfloat16mf4_t test_vfmsub_vv_f16mf4_rm_tum(vbool64_t mask, vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfmsub_vv_f16mf4_rm_tum(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmsub_vf_f16mf4_rm_tum
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmsub.mask.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
//
vfloat16mf4_t test_vfmsub_vf_f16mf4_rm_tum(vbool64_t mask, vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfmsub_vf_f16mf4_rm_tum(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmsub_vv_f16mf2_rm_tum
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmsub.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
//
vfloat16mf2_t test_vfmsub_vv_f16mf2_rm_tum(vbool32_t mask, vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfmsub_vv_f16mf2_rm_tum(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmsub_vf_f16mf2_rm_tum
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmsub.mask.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
//
vfloat16mf2_t test_vfmsub_vf_f16mf2_rm_tum(vbool32_t mask, vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfmsub_vf_f16mf2_rm_tum(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmsub_vv_f16m1_rm_tum
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmsub.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfmsub_vv_f16m1_rm_tum(vbool16_t mask, vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfmsub_vv_f16m1_rm_tum(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmsub_vf_f16m1_rm_tum
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmsub.mask.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfmsub_vf_f16m1_rm_tum(vbool16_t mask, vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfmsub_vf_f16m1_rm_tum(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmsub_vv_f16m2_rm_tum
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmsub.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
//
vfloat16m2_t test_vfmsub_vv_f16m2_rm_tum(vbool8_t mask, vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfmsub_vv_f16m2_rm_tum(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmsub_vf_f16m2_rm_tum
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmsub.mask.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
//
vfloat16m2_t test_vfmsub_vf_f16m2_rm_tum(vbool8_t mask, vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfmsub_vf_f16m2_rm_tum(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmsub_vv_f16m4_rm_tum
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmsub.mask.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
//
vfloat16m4_t test_vfmsub_vv_f16m4_rm_tum(vbool4_t mask, vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfmsub_vv_f16m4_rm_tum(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmsub_vf_f16m4_rm_tum
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmsub.mask.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
//
vfloat16m4_t test_vfmsub_vf_f16m4_rm_tum(vbool4_t mask, vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfmsub_vf_f16m4_rm_tum(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmsub_vv_f16m8_rm_tum
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmsub.mask.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
//
vfloat16m8_t test_vfmsub_vv_f16m8_rm_tum(vbool2_t mask, vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfmsub_vv_f16m8_rm_tum(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmsub_vf_f16m8_rm_tum
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmsub.mask.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
//
vfloat16m8_t test_vfmsub_vf_f16m8_rm_tum(vbool2_t mask, vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfmsub_vf_f16m8_rm_tum(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmsub_vv_f32mf2_rm_tum
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmsub.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
//
vfloat32mf2_t test_vfmsub_vv_f32mf2_rm_tum(vbool64_t mask, vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfmsub_vv_f32mf2_rm_tum(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmsub_vf_f32mf2_rm_tum
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmsub.mask.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
//
vfloat32mf2_t test_vfmsub_vf_f32mf2_rm_tum(vbool64_t mask, vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfmsub_vf_f32mf2_rm_tum(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmsub_vv_f32m1_rm_tum
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmsub.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfmsub_vv_f32m1_rm_tum(vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfmsub_vv_f32m1_rm_tum(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmsub_vf_f32m1_rm_tum
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmsub.mask.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfmsub_vf_f32m1_rm_tum(vbool32_t mask, vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfmsub_vf_f32m1_rm_tum(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmsub_vv_f32m2_rm_tum
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmsub.mask.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
//
vfloat32m2_t test_vfmsub_vv_f32m2_rm_tum(vbool16_t mask, vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfmsub_vv_f32m2_rm_tum(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmsub_vf_f32m2_rm_tum
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmsub.mask.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
//
vfloat32m2_t test_vfmsub_vf_f32m2_rm_tum(vbool16_t mask, vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfmsub_vf_f32m2_rm_tum(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmsub_vv_f32m4_rm_tum
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmsub.mask.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
//
vfloat32m4_t test_vfmsub_vv_f32m4_rm_tum(vbool8_t mask, vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfmsub_vv_f32m4_rm_tum(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmsub_vf_f32m4_rm_tum
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmsub.mask.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
//
vfloat32m4_t test_vfmsub_vf_f32m4_rm_tum(vbool8_t mask, vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfmsub_vf_f32m4_rm_tum(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmsub_vv_f32m8_rm_tum
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmsub.mask.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
//
vfloat32m8_t test_vfmsub_vv_f32m8_rm_tum(vbool4_t mask, vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfmsub_vv_f32m8_rm_tum(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmsub_vf_f32m8_rm_tum
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmsub.mask.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
//
vfloat32m8_t test_vfmsub_vf_f32m8_rm_tum(vbool4_t mask, vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfmsub_vf_f32m8_rm_tum(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmsub_vv_f64m1_rm_tum
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmsub.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfmsub_vv_f64m1_rm_tum(vbool64_t mask, vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfmsub_vv_f64m1_rm_tum(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmsub_vf_f64m1_rm_tum
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmsub.mask.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfmsub_vf_f64m1_rm_tum(vbool64_t mask, vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfmsub_vf_f64m1_rm_tum(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmsub_vv_f64m2_rm_tum
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmsub.mask.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
//
vfloat64m2_t test_vfmsub_vv_f64m2_rm_tum(vbool32_t mask, vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfmsub_vv_f64m2_rm_tum(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmsub_vf_f64m2_rm_tum
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmsub.mask.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
//
vfloat64m2_t test_vfmsub_vf_f64m2_rm_tum(vbool32_t mask, vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfmsub_vf_f64m2_rm_tum(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmsub_vv_f64m4_rm_tum
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmsub.mask.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
//
vfloat64m4_t test_vfmsub_vv_f64m4_rm_tum(vbool16_t mask, vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfmsub_vv_f64m4_rm_tum(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmsub_vf_f64m4_rm_tum
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmsub.mask.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
//
vfloat64m4_t test_vfmsub_vf_f64m4_rm_tum(vbool16_t mask, vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfmsub_vf_f64m4_rm_tum(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmsub_vv_f64m8_rm_tum
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmsub.mask.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
//
vfloat64m8_t test_vfmsub_vv_f64m8_rm_tum(vbool8_t mask, vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfmsub_vv_f64m8_rm_tum(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmsub_vf_f64m8_rm_tum
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmsub.mask.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
//
vfloat64m8_t test_vfmsub_vf_f64m8_rm_tum(vbool8_t mask, vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfmsub_vf_f64m8_rm_tum(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmsub_vv_f16mf4_rm_tumu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmsub.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
//
vfloat16mf4_t test_vfmsub_vv_f16mf4_rm_tumu(vbool64_t mask, vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfmsub_vv_f16mf4_rm_tumu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmsub_vf_f16mf4_rm_tumu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmsub.mask.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
//
vfloat16mf4_t test_vfmsub_vf_f16mf4_rm_tumu(vbool64_t mask, vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfmsub_vf_f16mf4_rm_tumu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmsub_vv_f16mf2_rm_tumu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmsub.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
//
vfloat16mf2_t test_vfmsub_vv_f16mf2_rm_tumu(vbool32_t mask, vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfmsub_vv_f16mf2_rm_tumu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmsub_vf_f16mf2_rm_tumu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmsub.mask.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
//
vfloat16mf2_t test_vfmsub_vf_f16mf2_rm_tumu(vbool32_t mask, vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfmsub_vf_f16mf2_rm_tumu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmsub_vv_f16m1_rm_tumu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmsub.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfmsub_vv_f16m1_rm_tumu(vbool16_t mask, vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfmsub_vv_f16m1_rm_tumu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmsub_vf_f16m1_rm_tumu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmsub.mask.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfmsub_vf_f16m1_rm_tumu(vbool16_t mask, vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfmsub_vf_f16m1_rm_tumu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmsub_vv_f16m2_rm_tumu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmsub.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
//
vfloat16m2_t test_vfmsub_vv_f16m2_rm_tumu(vbool8_t mask, vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfmsub_vv_f16m2_rm_tumu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmsub_vf_f16m2_rm_tumu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmsub.mask.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
//
vfloat16m2_t test_vfmsub_vf_f16m2_rm_tumu(vbool8_t mask, vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfmsub_vf_f16m2_rm_tumu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmsub_vv_f16m4_rm_tumu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmsub.mask.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
//
vfloat16m4_t test_vfmsub_vv_f16m4_rm_tumu(vbool4_t mask, vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfmsub_vv_f16m4_rm_tumu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmsub_vf_f16m4_rm_tumu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmsub.mask.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
//
vfloat16m4_t test_vfmsub_vf_f16m4_rm_tumu(vbool4_t mask, vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfmsub_vf_f16m4_rm_tumu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmsub_vv_f16m8_rm_tumu
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmsub.mask.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
//
vfloat16m8_t test_vfmsub_vv_f16m8_rm_tumu(vbool2_t mask, vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfmsub_vv_f16m8_rm_tumu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmsub_vf_f16m8_rm_tumu
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmsub.mask.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
//
vfloat16m8_t test_vfmsub_vf_f16m8_rm_tumu(vbool2_t mask, vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfmsub_vf_f16m8_rm_tumu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmsub_vv_f32mf2_rm_tumu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmsub.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
//
vfloat32mf2_t test_vfmsub_vv_f32mf2_rm_tumu(vbool64_t mask, vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfmsub_vv_f32mf2_rm_tumu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmsub_vf_f32mf2_rm_tumu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmsub.mask.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
//
vfloat32mf2_t test_vfmsub_vf_f32mf2_rm_tumu(vbool64_t mask, vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfmsub_vf_f32mf2_rm_tumu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmsub_vv_f32m1_rm_tumu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmsub.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfmsub_vv_f32m1_rm_tumu(vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfmsub_vv_f32m1_rm_tumu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmsub_vf_f32m1_rm_tumu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmsub.mask.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfmsub_vf_f32m1_rm_tumu(vbool32_t mask, vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfmsub_vf_f32m1_rm_tumu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmsub_vv_f32m2_rm_tumu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmsub.mask.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
//
vfloat32m2_t test_vfmsub_vv_f32m2_rm_tumu(vbool16_t mask, vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfmsub_vv_f32m2_rm_tumu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmsub_vf_f32m2_rm_tumu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmsub.mask.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
//
vfloat32m2_t test_vfmsub_vf_f32m2_rm_tumu(vbool16_t mask, vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfmsub_vf_f32m2_rm_tumu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmsub_vv_f32m4_rm_tumu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmsub.mask.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
//
vfloat32m4_t test_vfmsub_vv_f32m4_rm_tumu(vbool8_t mask, vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfmsub_vv_f32m4_rm_tumu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmsub_vf_f32m4_rm_tumu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmsub.mask.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
//
vfloat32m4_t test_vfmsub_vf_f32m4_rm_tumu(vbool8_t mask, vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfmsub_vf_f32m4_rm_tumu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmsub_vv_f32m8_rm_tumu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmsub.mask.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
//
vfloat32m8_t test_vfmsub_vv_f32m8_rm_tumu(vbool4_t mask, vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfmsub_vv_f32m8_rm_tumu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmsub_vf_f32m8_rm_tumu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmsub.mask.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
//
vfloat32m8_t test_vfmsub_vf_f32m8_rm_tumu(vbool4_t mask, vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfmsub_vf_f32m8_rm_tumu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmsub_vv_f64m1_rm_tumu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmsub.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfmsub_vv_f64m1_rm_tumu(vbool64_t mask, vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfmsub_vv_f64m1_rm_tumu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmsub_vf_f64m1_rm_tumu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmsub.mask.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfmsub_vf_f64m1_rm_tumu(vbool64_t mask, vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfmsub_vf_f64m1_rm_tumu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmsub_vv_f64m2_rm_tumu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmsub.mask.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
//
vfloat64m2_t test_vfmsub_vv_f64m2_rm_tumu(vbool32_t mask, vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfmsub_vv_f64m2_rm_tumu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmsub_vf_f64m2_rm_tumu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmsub.mask.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
//
vfloat64m2_t test_vfmsub_vf_f64m2_rm_tumu(vbool32_t mask, vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfmsub_vf_f64m2_rm_tumu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmsub_vv_f64m4_rm_tumu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmsub.mask.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
//
vfloat64m4_t test_vfmsub_vv_f64m4_rm_tumu(vbool16_t mask, vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfmsub_vv_f64m4_rm_tumu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmsub_vf_f64m4_rm_tumu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmsub.mask.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
//
vfloat64m4_t test_vfmsub_vf_f64m4_rm_tumu(vbool16_t mask, vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfmsub_vf_f64m4_rm_tumu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmsub_vv_f64m8_rm_tumu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmsub.mask.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
//
vfloat64m8_t test_vfmsub_vv_f64m8_rm_tumu(vbool8_t mask, vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfmsub_vv_f64m8_rm_tumu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmsub_vf_f64m8_rm_tumu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmsub.mask.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
//
vfloat64m8_t test_vfmsub_vf_f64m8_rm_tumu(vbool8_t mask, vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfmsub_vf_f64m8_rm_tumu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmsub_vv_f16mf4_rm_mu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmsub.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
//
vfloat16mf4_t test_vfmsub_vv_f16mf4_rm_mu(vbool64_t mask, vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfmsub_vv_f16mf4_rm_mu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmsub_vf_f16mf4_rm_mu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmsub.mask.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
//
vfloat16mf4_t test_vfmsub_vf_f16mf4_rm_mu(vbool64_t mask, vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfmsub_vf_f16mf4_rm_mu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmsub_vv_f16mf2_rm_mu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmsub.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
//
vfloat16mf2_t test_vfmsub_vv_f16mf2_rm_mu(vbool32_t mask, vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfmsub_vv_f16mf2_rm_mu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmsub_vf_f16mf2_rm_mu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmsub.mask.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
//
vfloat16mf2_t test_vfmsub_vf_f16mf2_rm_mu(vbool32_t mask, vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfmsub_vf_f16mf2_rm_mu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmsub_vv_f16m1_rm_mu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmsub.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfmsub_vv_f16m1_rm_mu(vbool16_t mask, vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfmsub_vv_f16m1_rm_mu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmsub_vf_f16m1_rm_mu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmsub.mask.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfmsub_vf_f16m1_rm_mu(vbool16_t mask, vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfmsub_vf_f16m1_rm_mu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmsub_vv_f16m2_rm_mu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmsub.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
//
vfloat16m2_t test_vfmsub_vv_f16m2_rm_mu(vbool8_t mask, vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfmsub_vv_f16m2_rm_mu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmsub_vf_f16m2_rm_mu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmsub.mask.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
//
vfloat16m2_t test_vfmsub_vf_f16m2_rm_mu(vbool8_t mask, vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfmsub_vf_f16m2_rm_mu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmsub_vv_f16m4_rm_mu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmsub.mask.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
//
vfloat16m4_t test_vfmsub_vv_f16m4_rm_mu(vbool4_t mask, vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfmsub_vv_f16m4_rm_mu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmsub_vf_f16m4_rm_mu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmsub.mask.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
//
vfloat16m4_t test_vfmsub_vf_f16m4_rm_mu(vbool4_t mask, vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfmsub_vf_f16m4_rm_mu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmsub_vv_f16m8_rm_mu
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmsub.mask.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
//
vfloat16m8_t test_vfmsub_vv_f16m8_rm_mu(vbool2_t mask, vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfmsub_vv_f16m8_rm_mu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmsub_vf_f16m8_rm_mu
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmsub.mask.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
//
vfloat16m8_t test_vfmsub_vf_f16m8_rm_mu(vbool2_t mask, vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfmsub_vf_f16m8_rm_mu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmsub_vv_f32mf2_rm_mu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmsub.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
//
vfloat32mf2_t test_vfmsub_vv_f32mf2_rm_mu(vbool64_t mask, vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfmsub_vv_f32mf2_rm_mu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmsub_vf_f32mf2_rm_mu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmsub.mask.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
//
vfloat32mf2_t test_vfmsub_vf_f32mf2_rm_mu(vbool64_t mask, vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfmsub_vf_f32mf2_rm_mu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmsub_vv_f32m1_rm_mu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmsub.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfmsub_vv_f32m1_rm_mu(vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfmsub_vv_f32m1_rm_mu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmsub_vf_f32m1_rm_mu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmsub.mask.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfmsub_vf_f32m1_rm_mu(vbool32_t mask, vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfmsub_vf_f32m1_rm_mu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmsub_vv_f32m2_rm_mu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmsub.mask.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
//
vfloat32m2_t test_vfmsub_vv_f32m2_rm_mu(vbool16_t mask, vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfmsub_vv_f32m2_rm_mu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmsub_vf_f32m2_rm_mu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmsub.mask.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
//
vfloat32m2_t test_vfmsub_vf_f32m2_rm_mu(vbool16_t mask, vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfmsub_vf_f32m2_rm_mu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmsub_vv_f32m4_rm_mu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmsub.mask.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
//
vfloat32m4_t test_vfmsub_vv_f32m4_rm_mu(vbool8_t mask, vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfmsub_vv_f32m4_rm_mu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmsub_vf_f32m4_rm_mu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmsub.mask.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
//
vfloat32m4_t test_vfmsub_vf_f32m4_rm_mu(vbool8_t mask, vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfmsub_vf_f32m4_rm_mu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmsub_vv_f32m8_rm_mu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmsub.mask.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
//
vfloat32m8_t test_vfmsub_vv_f32m8_rm_mu(vbool4_t mask, vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfmsub_vv_f32m8_rm_mu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmsub_vf_f32m8_rm_mu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmsub.mask.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
//
vfloat32m8_t test_vfmsub_vf_f32m8_rm_mu(vbool4_t mask, vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfmsub_vf_f32m8_rm_mu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmsub_vv_f64m1_rm_mu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmsub.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfmsub_vv_f64m1_rm_mu(vbool64_t mask, vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfmsub_vv_f64m1_rm_mu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmsub_vf_f64m1_rm_mu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmsub.mask.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfmsub_vf_f64m1_rm_mu(vbool64_t mask, vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfmsub_vf_f64m1_rm_mu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmsub_vv_f64m2_rm_mu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmsub.mask.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
//
vfloat64m2_t test_vfmsub_vv_f64m2_rm_mu(vbool32_t mask, vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfmsub_vv_f64m2_rm_mu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmsub_vf_f64m2_rm_mu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmsub.mask.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
//
vfloat64m2_t test_vfmsub_vf_f64m2_rm_mu(vbool32_t mask, vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfmsub_vf_f64m2_rm_mu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmsub_vv_f64m4_rm_mu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmsub.mask.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
//
vfloat64m4_t test_vfmsub_vv_f64m4_rm_mu(vbool16_t mask, vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfmsub_vv_f64m4_rm_mu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmsub_vf_f64m4_rm_mu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmsub.mask.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
//
vfloat64m4_t test_vfmsub_vf_f64m4_rm_mu(vbool16_t mask, vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfmsub_vf_f64m4_rm_mu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmsub_vv_f64m8_rm_mu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmsub.mask.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
//
vfloat64m8_t test_vfmsub_vv_f64m8_rm_mu(vbool8_t mask, vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfmsub_vv_f64m8_rm_mu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmsub_vf_f64m8_rm_mu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmsub.mask.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
//
vfloat64m8_t test_vfmsub_vf_f64m8_rm_mu(vbool8_t mask, vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfmsub_vf_f64m8_rm_mu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}

clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmacc.c

// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target // REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh \ // RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh \
// RUN: -target-feature +experimental-zvfh -disable-O0-optnone \ // RUN: -target-feature +experimental-zvfh -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ // RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s // RUN: FileCheck --check-prefix=CHECK-RV64 %s
#include <riscv_vector.h> #include <riscv_vector.h>
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmacc_vv_f16mf4_tu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmacc_vv_f16mf4_tu
// CHECK-RV64-SAME: (<vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK-RV64-SAME: (<vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmacc.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmacc.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
// //
vfloat16mf4_t test_vfnmacc_vv_f16mf4_tu(vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) { vfloat16mf4_t test_vfnmacc_vv_f16mf4_tu(vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfnmacc_vv_f16mf4_tu(vd, vs1, vs2, vl); return __riscv_vfnmacc_vv_f16mf4_tu(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmacc_vf_f16mf4_tu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmacc_vf_f16mf4_tu
// CHECK-RV64-SAME: (<vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmacc.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmacc.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
// //
vfloat16mf4_t test_vfnmacc_vf_f16mf4_tu(vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) { vfloat16mf4_t test_vfnmacc_vf_f16mf4_tu(vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfnmacc_vf_f16mf4_tu(vd, rs1, vs2, vl); return __riscv_vfnmacc_vf_f16mf4_tu(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmacc_vv_f16mf2_tu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmacc_vv_f16mf2_tu
// CHECK-RV64-SAME: (<vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmacc.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmacc.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
// //
vfloat16mf2_t test_vfnmacc_vv_f16mf2_tu(vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) { vfloat16mf2_t test_vfnmacc_vv_f16mf2_tu(vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfnmacc_vv_f16mf2_tu(vd, vs1, vs2, vl); return __riscv_vfnmacc_vv_f16mf2_tu(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmacc_vf_f16mf2_tu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmacc_vf_f16mf2_tu
// CHECK-RV64-SAME: (<vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmacc.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmacc.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
// //
vfloat16mf2_t test_vfnmacc_vf_f16mf2_tu(vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) { vfloat16mf2_t test_vfnmacc_vf_f16mf2_tu(vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfnmacc_vf_f16mf2_tu(vd, rs1, vs2, vl); return __riscv_vfnmacc_vf_f16mf2_tu(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmacc_vv_f16m1_tu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmacc_vv_f16m1_tu
// CHECK-RV64-SAME: (<vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmacc.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmacc.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
// //
vfloat16m1_t test_vfnmacc_vv_f16m1_tu(vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) { vfloat16m1_t test_vfnmacc_vv_f16m1_tu(vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfnmacc_vv_f16m1_tu(vd, vs1, vs2, vl); return __riscv_vfnmacc_vv_f16m1_tu(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmacc_vf_f16m1_tu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmacc_vf_f16m1_tu
// CHECK-RV64-SAME: (<vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmacc.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmacc.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
// //
vfloat16m1_t test_vfnmacc_vf_f16m1_tu(vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) { vfloat16m1_t test_vfnmacc_vf_f16m1_tu(vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfnmacc_vf_f16m1_tu(vd, rs1, vs2, vl); return __riscv_vfnmacc_vf_f16m1_tu(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmacc_vv_f16m2_tu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmacc_vv_f16m2_tu
// CHECK-RV64-SAME: (<vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmacc.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmacc.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
// //
vfloat16m2_t test_vfnmacc_vv_f16m2_tu(vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) { vfloat16m2_t test_vfnmacc_vv_f16m2_tu(vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfnmacc_vv_f16m2_tu(vd, vs1, vs2, vl); return __riscv_vfnmacc_vv_f16m2_tu(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmacc_vf_f16m2_tu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmacc_vf_f16m2_tu
// CHECK-RV64-SAME: (<vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmacc.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmacc.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
// //
vfloat16m2_t test_vfnmacc_vf_f16m2_tu(vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) { vfloat16m2_t test_vfnmacc_vf_f16m2_tu(vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfnmacc_vf_f16m2_tu(vd, rs1, vs2, vl); return __riscv_vfnmacc_vf_f16m2_tu(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmacc_vv_f16m4_tu // CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmacc_vv_f16m4_tu
// CHECK-RV64-SAME: (<vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmacc.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmacc.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
// //
vfloat16m4_t test_vfnmacc_vv_f16m4_tu(vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) { vfloat16m4_t test_vfnmacc_vv_f16m4_tu(vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfnmacc_vv_f16m4_tu(vd, vs1, vs2, vl); return __riscv_vfnmacc_vv_f16m4_tu(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmacc_vf_f16m4_tu // CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmacc_vf_f16m4_tu
// CHECK-RV64-SAME: (<vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmacc.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmacc.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
// //
vfloat16m4_t test_vfnmacc_vf_f16m4_tu(vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) { vfloat16m4_t test_vfnmacc_vf_f16m4_tu(vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfnmacc_vf_f16m4_tu(vd, rs1, vs2, vl); return __riscv_vfnmacc_vf_f16m4_tu(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmacc_vv_f16m8_tu // CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmacc_vv_f16m8_tu
// CHECK-RV64-SAME: (<vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmacc.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmacc.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
// //
vfloat16m8_t test_vfnmacc_vv_f16m8_tu(vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) { vfloat16m8_t test_vfnmacc_vv_f16m8_tu(vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfnmacc_vv_f16m8_tu(vd, vs1, vs2, vl); return __riscv_vfnmacc_vv_f16m8_tu(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmacc_vf_f16m8_tu // CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmacc_vf_f16m8_tu
// CHECK-RV64-SAME: (<vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmacc.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmacc.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
// //
vfloat16m8_t test_vfnmacc_vf_f16m8_tu(vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) { vfloat16m8_t test_vfnmacc_vf_f16m8_tu(vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfnmacc_vf_f16m8_tu(vd, rs1, vs2, vl); return __riscv_vfnmacc_vf_f16m8_tu(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmacc_vv_f32mf2_tu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmacc_vv_f32mf2_tu
// CHECK-RV64-SAME: (<vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmacc.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmacc.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfnmacc_vv_f32mf2_tu(vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) { vfloat32mf2_t test_vfnmacc_vv_f32mf2_tu(vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfnmacc_vv_f32mf2_tu(vd, vs1, vs2, vl); return __riscv_vfnmacc_vv_f32mf2_tu(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmacc_vf_f32mf2_tu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmacc_vf_f32mf2_tu
// CHECK-RV64-SAME: (<vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmacc.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmacc.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfnmacc_vf_f32mf2_tu(vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) { vfloat32mf2_t test_vfnmacc_vf_f32mf2_tu(vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfnmacc_vf_f32mf2_tu(vd, rs1, vs2, vl); return __riscv_vfnmacc_vf_f32mf2_tu(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmacc_vv_f32m1_tu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmacc_vv_f32m1_tu
// CHECK-RV64-SAME: (<vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmacc.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmacc.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfnmacc_vv_f32m1_tu(vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) { vfloat32m1_t test_vfnmacc_vv_f32m1_tu(vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfnmacc_vv_f32m1_tu(vd, vs1, vs2, vl); return __riscv_vfnmacc_vv_f32m1_tu(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmacc_vf_f32m1_tu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmacc_vf_f32m1_tu
// CHECK-RV64-SAME: (<vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmacc.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmacc.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfnmacc_vf_f32m1_tu(vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) { vfloat32m1_t test_vfnmacc_vf_f32m1_tu(vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfnmacc_vf_f32m1_tu(vd, rs1, vs2, vl); return __riscv_vfnmacc_vf_f32m1_tu(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmacc_vv_f32m2_tu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmacc_vv_f32m2_tu
// CHECK-RV64-SAME: (<vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmacc.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmacc.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfnmacc_vv_f32m2_tu(vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) { vfloat32m2_t test_vfnmacc_vv_f32m2_tu(vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfnmacc_vv_f32m2_tu(vd, vs1, vs2, vl); return __riscv_vfnmacc_vv_f32m2_tu(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmacc_vf_f32m2_tu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmacc_vf_f32m2_tu
// CHECK-RV64-SAME: (<vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmacc.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmacc.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfnmacc_vf_f32m2_tu(vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) { vfloat32m2_t test_vfnmacc_vf_f32m2_tu(vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfnmacc_vf_f32m2_tu(vd, rs1, vs2, vl); return __riscv_vfnmacc_vf_f32m2_tu(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmacc_vv_f32m4_tu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmacc_vv_f32m4_tu
// CHECK-RV64-SAME: (<vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmacc.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmacc.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfnmacc_vv_f32m4_tu(vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) { vfloat32m4_t test_vfnmacc_vv_f32m4_tu(vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfnmacc_vv_f32m4_tu(vd, vs1, vs2, vl); return __riscv_vfnmacc_vv_f32m4_tu(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmacc_vf_f32m4_tu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmacc_vf_f32m4_tu
// CHECK-RV64-SAME: (<vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmacc.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmacc.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfnmacc_vf_f32m4_tu(vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) { vfloat32m4_t test_vfnmacc_vf_f32m4_tu(vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfnmacc_vf_f32m4_tu(vd, rs1, vs2, vl); return __riscv_vfnmacc_vf_f32m4_tu(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmacc_vv_f32m8_tu // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmacc_vv_f32m8_tu
// CHECK-RV64-SAME: (<vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmacc.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmacc.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfnmacc_vv_f32m8_tu(vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) { vfloat32m8_t test_vfnmacc_vv_f32m8_tu(vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfnmacc_vv_f32m8_tu(vd, vs1, vs2, vl); return __riscv_vfnmacc_vv_f32m8_tu(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmacc_vf_f32m8_tu // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmacc_vf_f32m8_tu
// CHECK-RV64-SAME: (<vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmacc.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmacc.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfnmacc_vf_f32m8_tu(vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) { vfloat32m8_t test_vfnmacc_vf_f32m8_tu(vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfnmacc_vf_f32m8_tu(vd, rs1, vs2, vl); return __riscv_vfnmacc_vf_f32m8_tu(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmacc_vv_f64m1_tu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmacc_vv_f64m1_tu
// CHECK-RV64-SAME: (<vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmacc.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmacc.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfnmacc_vv_f64m1_tu(vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) { vfloat64m1_t test_vfnmacc_vv_f64m1_tu(vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfnmacc_vv_f64m1_tu(vd, vs1, vs2, vl); return __riscv_vfnmacc_vv_f64m1_tu(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmacc_vf_f64m1_tu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmacc_vf_f64m1_tu
// CHECK-RV64-SAME: (<vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmacc.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmacc.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfnmacc_vf_f64m1_tu(vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) { vfloat64m1_t test_vfnmacc_vf_f64m1_tu(vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfnmacc_vf_f64m1_tu(vd, rs1, vs2, vl); return __riscv_vfnmacc_vf_f64m1_tu(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmacc_vv_f64m2_tu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmacc_vv_f64m2_tu
// CHECK-RV64-SAME: (<vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmacc.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmacc.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfnmacc_vv_f64m2_tu(vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) { vfloat64m2_t test_vfnmacc_vv_f64m2_tu(vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfnmacc_vv_f64m2_tu(vd, vs1, vs2, vl); return __riscv_vfnmacc_vv_f64m2_tu(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmacc_vf_f64m2_tu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmacc_vf_f64m2_tu
// CHECK-RV64-SAME: (<vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmacc.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmacc.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfnmacc_vf_f64m2_tu(vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) { vfloat64m2_t test_vfnmacc_vf_f64m2_tu(vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfnmacc_vf_f64m2_tu(vd, rs1, vs2, vl); return __riscv_vfnmacc_vf_f64m2_tu(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmacc_vv_f64m4_tu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmacc_vv_f64m4_tu
// CHECK-RV64-SAME: (<vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmacc.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmacc.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfnmacc_vv_f64m4_tu(vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) { vfloat64m4_t test_vfnmacc_vv_f64m4_tu(vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfnmacc_vv_f64m4_tu(vd, vs1, vs2, vl); return __riscv_vfnmacc_vv_f64m4_tu(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmacc_vf_f64m4_tu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmacc_vf_f64m4_tu
// CHECK-RV64-SAME: (<vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmacc.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmacc.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfnmacc_vf_f64m4_tu(vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) { vfloat64m4_t test_vfnmacc_vf_f64m4_tu(vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfnmacc_vf_f64m4_tu(vd, rs1, vs2, vl); return __riscv_vfnmacc_vf_f64m4_tu(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmacc_vv_f64m8_tu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmacc_vv_f64m8_tu
// CHECK-RV64-SAME: (<vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmacc.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmacc.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfnmacc_vv_f64m8_tu(vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) { vfloat64m8_t test_vfnmacc_vv_f64m8_tu(vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfnmacc_vv_f64m8_tu(vd, vs1, vs2, vl); return __riscv_vfnmacc_vv_f64m8_tu(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmacc_vf_f64m8_tu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmacc_vf_f64m8_tu
// CHECK-RV64-SAME: (<vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmacc.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmacc.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfnmacc_vf_f64m8_tu(vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) { vfloat64m8_t test_vfnmacc_vf_f64m8_tu(vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfnmacc_vf_f64m8_tu(vd, rs1, vs2, vl); return __riscv_vfnmacc_vf_f64m8_tu(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmacc_vv_f16mf4_tum // CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmacc_vv_f16mf4_tum
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmacc.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmacc.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
// //
vfloat16mf4_t test_vfnmacc_vv_f16mf4_tum(vbool64_t mask, vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) { vfloat16mf4_t test_vfnmacc_vv_f16mf4_tum(vbool64_t mask, vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfnmacc_vv_f16mf4_tum(mask, vd, vs1, vs2, vl); return __riscv_vfnmacc_vv_f16mf4_tum(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmacc_vf_f16mf4_tum // CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmacc_vf_f16mf4_tum
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmacc.mask.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmacc.mask.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
// //
vfloat16mf4_t test_vfnmacc_vf_f16mf4_tum(vbool64_t mask, vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) { vfloat16mf4_t test_vfnmacc_vf_f16mf4_tum(vbool64_t mask, vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfnmacc_vf_f16mf4_tum(mask, vd, rs1, vs2, vl); return __riscv_vfnmacc_vf_f16mf4_tum(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmacc_vv_f16mf2_tum // CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmacc_vv_f16mf2_tum
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmacc.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmacc.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
// //
vfloat16mf2_t test_vfnmacc_vv_f16mf2_tum(vbool32_t mask, vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) { vfloat16mf2_t test_vfnmacc_vv_f16mf2_tum(vbool32_t mask, vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfnmacc_vv_f16mf2_tum(mask, vd, vs1, vs2, vl); return __riscv_vfnmacc_vv_f16mf2_tum(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmacc_vf_f16mf2_tum // CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmacc_vf_f16mf2_tum
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmacc.mask.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmacc.mask.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
// //
vfloat16mf2_t test_vfnmacc_vf_f16mf2_tum(vbool32_t mask, vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) { vfloat16mf2_t test_vfnmacc_vf_f16mf2_tum(vbool32_t mask, vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfnmacc_vf_f16mf2_tum(mask, vd, rs1, vs2, vl); return __riscv_vfnmacc_vf_f16mf2_tum(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmacc_vv_f16m1_tum // CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmacc_vv_f16m1_tum
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmacc.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmacc.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
// //
vfloat16m1_t test_vfnmacc_vv_f16m1_tum(vbool16_t mask, vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) { vfloat16m1_t test_vfnmacc_vv_f16m1_tum(vbool16_t mask, vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfnmacc_vv_f16m1_tum(mask, vd, vs1, vs2, vl); return __riscv_vfnmacc_vv_f16m1_tum(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmacc_vf_f16m1_tum // CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmacc_vf_f16m1_tum
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmacc.mask.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmacc.mask.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
// //
vfloat16m1_t test_vfnmacc_vf_f16m1_tum(vbool16_t mask, vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) { vfloat16m1_t test_vfnmacc_vf_f16m1_tum(vbool16_t mask, vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfnmacc_vf_f16m1_tum(mask, vd, rs1, vs2, vl); return __riscv_vfnmacc_vf_f16m1_tum(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmacc_vv_f16m2_tum // CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmacc_vv_f16m2_tum
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmacc.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmacc.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
// //
vfloat16m2_t test_vfnmacc_vv_f16m2_tum(vbool8_t mask, vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) { vfloat16m2_t test_vfnmacc_vv_f16m2_tum(vbool8_t mask, vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfnmacc_vv_f16m2_tum(mask, vd, vs1, vs2, vl); return __riscv_vfnmacc_vv_f16m2_tum(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmacc_vf_f16m2_tum // CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmacc_vf_f16m2_tum
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmacc.mask.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmacc.mask.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
// //
vfloat16m2_t test_vfnmacc_vf_f16m2_tum(vbool8_t mask, vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) { vfloat16m2_t test_vfnmacc_vf_f16m2_tum(vbool8_t mask, vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfnmacc_vf_f16m2_tum(mask, vd, rs1, vs2, vl); return __riscv_vfnmacc_vf_f16m2_tum(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmacc_vv_f16m4_tum // CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmacc_vv_f16m4_tum
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmacc.mask.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmacc.mask.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
// //
vfloat16m4_t test_vfnmacc_vv_f16m4_tum(vbool4_t mask, vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) { vfloat16m4_t test_vfnmacc_vv_f16m4_tum(vbool4_t mask, vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfnmacc_vv_f16m4_tum(mask, vd, vs1, vs2, vl); return __riscv_vfnmacc_vv_f16m4_tum(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmacc_vf_f16m4_tum // CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmacc_vf_f16m4_tum
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmacc.mask.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmacc.mask.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
// //
vfloat16m4_t test_vfnmacc_vf_f16m4_tum(vbool4_t mask, vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) { vfloat16m4_t test_vfnmacc_vf_f16m4_tum(vbool4_t mask, vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfnmacc_vf_f16m4_tum(mask, vd, rs1, vs2, vl); return __riscv_vfnmacc_vf_f16m4_tum(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmacc_vv_f16m8_tum // CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmacc_vv_f16m8_tum
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmacc.mask.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmacc.mask.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
// //
vfloat16m8_t test_vfnmacc_vv_f16m8_tum(vbool2_t mask, vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) { vfloat16m8_t test_vfnmacc_vv_f16m8_tum(vbool2_t mask, vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfnmacc_vv_f16m8_tum(mask, vd, vs1, vs2, vl); return __riscv_vfnmacc_vv_f16m8_tum(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmacc_vf_f16m8_tum // CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmacc_vf_f16m8_tum
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmacc.mask.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmacc.mask.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
// //
vfloat16m8_t test_vfnmacc_vf_f16m8_tum(vbool2_t mask, vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) { vfloat16m8_t test_vfnmacc_vf_f16m8_tum(vbool2_t mask, vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfnmacc_vf_f16m8_tum(mask, vd, rs1, vs2, vl); return __riscv_vfnmacc_vf_f16m8_tum(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmacc_vv_f32mf2_tum // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmacc_vv_f32mf2_tum
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmacc.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmacc.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfnmacc_vv_f32mf2_tum(vbool64_t mask, vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) { vfloat32mf2_t test_vfnmacc_vv_f32mf2_tum(vbool64_t mask, vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfnmacc_vv_f32mf2_tum(mask, vd, vs1, vs2, vl); return __riscv_vfnmacc_vv_f32mf2_tum(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmacc_vf_f32mf2_tum // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmacc_vf_f32mf2_tum
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmacc.mask.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmacc.mask.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfnmacc_vf_f32mf2_tum(vbool64_t mask, vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) { vfloat32mf2_t test_vfnmacc_vf_f32mf2_tum(vbool64_t mask, vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfnmacc_vf_f32mf2_tum(mask, vd, rs1, vs2, vl); return __riscv_vfnmacc_vf_f32mf2_tum(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmacc_vv_f32m1_tum // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmacc_vv_f32m1_tum
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmacc.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmacc.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfnmacc_vv_f32m1_tum(vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) { vfloat32m1_t test_vfnmacc_vv_f32m1_tum(vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfnmacc_vv_f32m1_tum(mask, vd, vs1, vs2, vl); return __riscv_vfnmacc_vv_f32m1_tum(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmacc_vf_f32m1_tum // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmacc_vf_f32m1_tum
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmacc.mask.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmacc.mask.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfnmacc_vf_f32m1_tum(vbool32_t mask, vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) { vfloat32m1_t test_vfnmacc_vf_f32m1_tum(vbool32_t mask, vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfnmacc_vf_f32m1_tum(mask, vd, rs1, vs2, vl); return __riscv_vfnmacc_vf_f32m1_tum(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmacc_vv_f32m2_tum // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmacc_vv_f32m2_tum
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmacc.mask.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmacc.mask.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfnmacc_vv_f32m2_tum(vbool16_t mask, vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) { vfloat32m2_t test_vfnmacc_vv_f32m2_tum(vbool16_t mask, vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfnmacc_vv_f32m2_tum(mask, vd, vs1, vs2, vl); return __riscv_vfnmacc_vv_f32m2_tum(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmacc_vf_f32m2_tum // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmacc_vf_f32m2_tum
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmacc.mask.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmacc.mask.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfnmacc_vf_f32m2_tum(vbool16_t mask, vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) { vfloat32m2_t test_vfnmacc_vf_f32m2_tum(vbool16_t mask, vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfnmacc_vf_f32m2_tum(mask, vd, rs1, vs2, vl); return __riscv_vfnmacc_vf_f32m2_tum(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmacc_vv_f32m4_tum // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmacc_vv_f32m4_tum
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmacc.mask.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmacc.mask.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfnmacc_vv_f32m4_tum(vbool8_t mask, vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) { vfloat32m4_t test_vfnmacc_vv_f32m4_tum(vbool8_t mask, vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfnmacc_vv_f32m4_tum(mask, vd, vs1, vs2, vl); return __riscv_vfnmacc_vv_f32m4_tum(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmacc_vf_f32m4_tum // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmacc_vf_f32m4_tum
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmacc.mask.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmacc.mask.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfnmacc_vf_f32m4_tum(vbool8_t mask, vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) { vfloat32m4_t test_vfnmacc_vf_f32m4_tum(vbool8_t mask, vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfnmacc_vf_f32m4_tum(mask, vd, rs1, vs2, vl); return __riscv_vfnmacc_vf_f32m4_tum(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmacc_vv_f32m8_tum // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmacc_vv_f32m8_tum
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmacc.mask.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmacc.mask.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfnmacc_vv_f32m8_tum(vbool4_t mask, vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) { vfloat32m8_t test_vfnmacc_vv_f32m8_tum(vbool4_t mask, vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfnmacc_vv_f32m8_tum(mask, vd, vs1, vs2, vl); return __riscv_vfnmacc_vv_f32m8_tum(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmacc_vf_f32m8_tum // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmacc_vf_f32m8_tum
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmacc.mask.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmacc.mask.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfnmacc_vf_f32m8_tum(vbool4_t mask, vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) { vfloat32m8_t test_vfnmacc_vf_f32m8_tum(vbool4_t mask, vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfnmacc_vf_f32m8_tum(mask, vd, rs1, vs2, vl); return __riscv_vfnmacc_vf_f32m8_tum(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmacc_vv_f64m1_tum // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmacc_vv_f64m1_tum
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmacc.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmacc.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfnmacc_vv_f64m1_tum(vbool64_t mask, vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) { vfloat64m1_t test_vfnmacc_vv_f64m1_tum(vbool64_t mask, vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfnmacc_vv_f64m1_tum(mask, vd, vs1, vs2, vl); return __riscv_vfnmacc_vv_f64m1_tum(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmacc_vf_f64m1_tum // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmacc_vf_f64m1_tum
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmacc.mask.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmacc.mask.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfnmacc_vf_f64m1_tum(vbool64_t mask, vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) { vfloat64m1_t test_vfnmacc_vf_f64m1_tum(vbool64_t mask, vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfnmacc_vf_f64m1_tum(mask, vd, rs1, vs2, vl); return __riscv_vfnmacc_vf_f64m1_tum(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmacc_vv_f64m2_tum // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmacc_vv_f64m2_tum
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmacc.mask.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmacc.mask.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfnmacc_vv_f64m2_tum(vbool32_t mask, vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) { vfloat64m2_t test_vfnmacc_vv_f64m2_tum(vbool32_t mask, vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfnmacc_vv_f64m2_tum(mask, vd, vs1, vs2, vl); return __riscv_vfnmacc_vv_f64m2_tum(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmacc_vf_f64m2_tum // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmacc_vf_f64m2_tum
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmacc.mask.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmacc.mask.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfnmacc_vf_f64m2_tum(vbool32_t mask, vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) { vfloat64m2_t test_vfnmacc_vf_f64m2_tum(vbool32_t mask, vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfnmacc_vf_f64m2_tum(mask, vd, rs1, vs2, vl); return __riscv_vfnmacc_vf_f64m2_tum(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmacc_vv_f64m4_tum // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmacc_vv_f64m4_tum
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmacc.mask.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmacc.mask.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfnmacc_vv_f64m4_tum(vbool16_t mask, vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) { vfloat64m4_t test_vfnmacc_vv_f64m4_tum(vbool16_t mask, vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfnmacc_vv_f64m4_tum(mask, vd, vs1, vs2, vl); return __riscv_vfnmacc_vv_f64m4_tum(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmacc_vf_f64m4_tum // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmacc_vf_f64m4_tum
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmacc.mask.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmacc.mask.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfnmacc_vf_f64m4_tum(vbool16_t mask, vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) { vfloat64m4_t test_vfnmacc_vf_f64m4_tum(vbool16_t mask, vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfnmacc_vf_f64m4_tum(mask, vd, rs1, vs2, vl); return __riscv_vfnmacc_vf_f64m4_tum(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmacc_vv_f64m8_tum // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmacc_vv_f64m8_tum
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmacc.mask.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmacc.mask.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfnmacc_vv_f64m8_tum(vbool8_t mask, vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) { vfloat64m8_t test_vfnmacc_vv_f64m8_tum(vbool8_t mask, vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfnmacc_vv_f64m8_tum(mask, vd, vs1, vs2, vl); return __riscv_vfnmacc_vv_f64m8_tum(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmacc_vf_f64m8_tum // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmacc_vf_f64m8_tum
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmacc.mask.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmacc.mask.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfnmacc_vf_f64m8_tum(vbool8_t mask, vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) { vfloat64m8_t test_vfnmacc_vf_f64m8_tum(vbool8_t mask, vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfnmacc_vf_f64m8_tum(mask, vd, rs1, vs2, vl); return __riscv_vfnmacc_vf_f64m8_tum(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmacc_vv_f16mf4_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmacc_vv_f16mf4_tumu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmacc.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmacc.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
// //
vfloat16mf4_t test_vfnmacc_vv_f16mf4_tumu(vbool64_t mask, vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) { vfloat16mf4_t test_vfnmacc_vv_f16mf4_tumu(vbool64_t mask, vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfnmacc_vv_f16mf4_tumu(mask, vd, vs1, vs2, vl); return __riscv_vfnmacc_vv_f16mf4_tumu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmacc_vf_f16mf4_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmacc_vf_f16mf4_tumu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmacc.mask.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmacc.mask.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
// //
vfloat16mf4_t test_vfnmacc_vf_f16mf4_tumu(vbool64_t mask, vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) { vfloat16mf4_t test_vfnmacc_vf_f16mf4_tumu(vbool64_t mask, vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfnmacc_vf_f16mf4_tumu(mask, vd, rs1, vs2, vl); return __riscv_vfnmacc_vf_f16mf4_tumu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmacc_vv_f16mf2_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmacc_vv_f16mf2_tumu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmacc.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmacc.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
// //
vfloat16mf2_t test_vfnmacc_vv_f16mf2_tumu(vbool32_t mask, vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) { vfloat16mf2_t test_vfnmacc_vv_f16mf2_tumu(vbool32_t mask, vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfnmacc_vv_f16mf2_tumu(mask, vd, vs1, vs2, vl); return __riscv_vfnmacc_vv_f16mf2_tumu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmacc_vf_f16mf2_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmacc_vf_f16mf2_tumu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmacc.mask.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmacc.mask.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
// //
vfloat16mf2_t test_vfnmacc_vf_f16mf2_tumu(vbool32_t mask, vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) { vfloat16mf2_t test_vfnmacc_vf_f16mf2_tumu(vbool32_t mask, vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfnmacc_vf_f16mf2_tumu(mask, vd, rs1, vs2, vl); return __riscv_vfnmacc_vf_f16mf2_tumu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmacc_vv_f16m1_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmacc_vv_f16m1_tumu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmacc.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmacc.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
// //
vfloat16m1_t test_vfnmacc_vv_f16m1_tumu(vbool16_t mask, vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) { vfloat16m1_t test_vfnmacc_vv_f16m1_tumu(vbool16_t mask, vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfnmacc_vv_f16m1_tumu(mask, vd, vs1, vs2, vl); return __riscv_vfnmacc_vv_f16m1_tumu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmacc_vf_f16m1_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmacc_vf_f16m1_tumu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmacc.mask.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmacc.mask.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
// //
vfloat16m1_t test_vfnmacc_vf_f16m1_tumu(vbool16_t mask, vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) { vfloat16m1_t test_vfnmacc_vf_f16m1_tumu(vbool16_t mask, vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfnmacc_vf_f16m1_tumu(mask, vd, rs1, vs2, vl); return __riscv_vfnmacc_vf_f16m1_tumu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmacc_vv_f16m2_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmacc_vv_f16m2_tumu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmacc.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmacc.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
// //
vfloat16m2_t test_vfnmacc_vv_f16m2_tumu(vbool8_t mask, vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) { vfloat16m2_t test_vfnmacc_vv_f16m2_tumu(vbool8_t mask, vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfnmacc_vv_f16m2_tumu(mask, vd, vs1, vs2, vl); return __riscv_vfnmacc_vv_f16m2_tumu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmacc_vf_f16m2_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmacc_vf_f16m2_tumu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmacc.mask.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmacc.mask.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
// //
vfloat16m2_t test_vfnmacc_vf_f16m2_tumu(vbool8_t mask, vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) { vfloat16m2_t test_vfnmacc_vf_f16m2_tumu(vbool8_t mask, vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfnmacc_vf_f16m2_tumu(mask, vd, rs1, vs2, vl); return __riscv_vfnmacc_vf_f16m2_tumu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmacc_vv_f16m4_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmacc_vv_f16m4_tumu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmacc.mask.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmacc.mask.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
// //
vfloat16m4_t test_vfnmacc_vv_f16m4_tumu(vbool4_t mask, vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) { vfloat16m4_t test_vfnmacc_vv_f16m4_tumu(vbool4_t mask, vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfnmacc_vv_f16m4_tumu(mask, vd, vs1, vs2, vl); return __riscv_vfnmacc_vv_f16m4_tumu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmacc_vf_f16m4_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmacc_vf_f16m4_tumu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmacc.mask.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmacc.mask.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
// //
vfloat16m4_t test_vfnmacc_vf_f16m4_tumu(vbool4_t mask, vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) { vfloat16m4_t test_vfnmacc_vf_f16m4_tumu(vbool4_t mask, vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfnmacc_vf_f16m4_tumu(mask, vd, rs1, vs2, vl); return __riscv_vfnmacc_vf_f16m4_tumu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmacc_vv_f16m8_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmacc_vv_f16m8_tumu
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmacc.mask.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmacc.mask.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
// //
vfloat16m8_t test_vfnmacc_vv_f16m8_tumu(vbool2_t mask, vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) { vfloat16m8_t test_vfnmacc_vv_f16m8_tumu(vbool2_t mask, vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfnmacc_vv_f16m8_tumu(mask, vd, vs1, vs2, vl); return __riscv_vfnmacc_vv_f16m8_tumu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmacc_vf_f16m8_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmacc_vf_f16m8_tumu
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmacc.mask.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmacc.mask.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
// //
vfloat16m8_t test_vfnmacc_vf_f16m8_tumu(vbool2_t mask, vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) { vfloat16m8_t test_vfnmacc_vf_f16m8_tumu(vbool2_t mask, vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfnmacc_vf_f16m8_tumu(mask, vd, rs1, vs2, vl); return __riscv_vfnmacc_vf_f16m8_tumu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmacc_vv_f32mf2_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmacc_vv_f32mf2_tumu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmacc.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmacc.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfnmacc_vv_f32mf2_tumu(vbool64_t mask, vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) { vfloat32mf2_t test_vfnmacc_vv_f32mf2_tumu(vbool64_t mask, vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfnmacc_vv_f32mf2_tumu(mask, vd, vs1, vs2, vl); return __riscv_vfnmacc_vv_f32mf2_tumu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmacc_vf_f32mf2_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmacc_vf_f32mf2_tumu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmacc.mask.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmacc.mask.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfnmacc_vf_f32mf2_tumu(vbool64_t mask, vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) { vfloat32mf2_t test_vfnmacc_vf_f32mf2_tumu(vbool64_t mask, vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfnmacc_vf_f32mf2_tumu(mask, vd, rs1, vs2, vl); return __riscv_vfnmacc_vf_f32mf2_tumu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmacc_vv_f32m1_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmacc_vv_f32m1_tumu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmacc.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmacc.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfnmacc_vv_f32m1_tumu(vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) { vfloat32m1_t test_vfnmacc_vv_f32m1_tumu(vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfnmacc_vv_f32m1_tumu(mask, vd, vs1, vs2, vl); return __riscv_vfnmacc_vv_f32m1_tumu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmacc_vf_f32m1_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmacc_vf_f32m1_tumu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmacc.mask.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmacc.mask.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfnmacc_vf_f32m1_tumu(vbool32_t mask, vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) { vfloat32m1_t test_vfnmacc_vf_f32m1_tumu(vbool32_t mask, vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfnmacc_vf_f32m1_tumu(mask, vd, rs1, vs2, vl); return __riscv_vfnmacc_vf_f32m1_tumu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmacc_vv_f32m2_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmacc_vv_f32m2_tumu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmacc.mask.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmacc.mask.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfnmacc_vv_f32m2_tumu(vbool16_t mask, vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) { vfloat32m2_t test_vfnmacc_vv_f32m2_tumu(vbool16_t mask, vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfnmacc_vv_f32m2_tumu(mask, vd, vs1, vs2, vl); return __riscv_vfnmacc_vv_f32m2_tumu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmacc_vf_f32m2_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmacc_vf_f32m2_tumu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmacc.mask.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmacc.mask.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfnmacc_vf_f32m2_tumu(vbool16_t mask, vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) { vfloat32m2_t test_vfnmacc_vf_f32m2_tumu(vbool16_t mask, vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfnmacc_vf_f32m2_tumu(mask, vd, rs1, vs2, vl); return __riscv_vfnmacc_vf_f32m2_tumu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmacc_vv_f32m4_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmacc_vv_f32m4_tumu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmacc.mask.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmacc.mask.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfnmacc_vv_f32m4_tumu(vbool8_t mask, vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) { vfloat32m4_t test_vfnmacc_vv_f32m4_tumu(vbool8_t mask, vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfnmacc_vv_f32m4_tumu(mask, vd, vs1, vs2, vl); return __riscv_vfnmacc_vv_f32m4_tumu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmacc_vf_f32m4_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmacc_vf_f32m4_tumu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmacc.mask.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmacc.mask.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfnmacc_vf_f32m4_tumu(vbool8_t mask, vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) { vfloat32m4_t test_vfnmacc_vf_f32m4_tumu(vbool8_t mask, vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfnmacc_vf_f32m4_tumu(mask, vd, rs1, vs2, vl); return __riscv_vfnmacc_vf_f32m4_tumu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmacc_vv_f32m8_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmacc_vv_f32m8_tumu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmacc.mask.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmacc.mask.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfnmacc_vv_f32m8_tumu(vbool4_t mask, vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) { vfloat32m8_t test_vfnmacc_vv_f32m8_tumu(vbool4_t mask, vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfnmacc_vv_f32m8_tumu(mask, vd, vs1, vs2, vl); return __riscv_vfnmacc_vv_f32m8_tumu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmacc_vf_f32m8_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmacc_vf_f32m8_tumu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmacc.mask.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmacc.mask.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfnmacc_vf_f32m8_tumu(vbool4_t mask, vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) { vfloat32m8_t test_vfnmacc_vf_f32m8_tumu(vbool4_t mask, vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfnmacc_vf_f32m8_tumu(mask, vd, rs1, vs2, vl); return __riscv_vfnmacc_vf_f32m8_tumu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmacc_vv_f64m1_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmacc_vv_f64m1_tumu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmacc.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmacc.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfnmacc_vv_f64m1_tumu(vbool64_t mask, vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) { vfloat64m1_t test_vfnmacc_vv_f64m1_tumu(vbool64_t mask, vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfnmacc_vv_f64m1_tumu(mask, vd, vs1, vs2, vl); return __riscv_vfnmacc_vv_f64m1_tumu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmacc_vf_f64m1_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmacc_vf_f64m1_tumu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmacc.mask.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmacc.mask.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfnmacc_vf_f64m1_tumu(vbool64_t mask, vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) { vfloat64m1_t test_vfnmacc_vf_f64m1_tumu(vbool64_t mask, vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfnmacc_vf_f64m1_tumu(mask, vd, rs1, vs2, vl); return __riscv_vfnmacc_vf_f64m1_tumu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmacc_vv_f64m2_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmacc_vv_f64m2_tumu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmacc.mask.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmacc.mask.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfnmacc_vv_f64m2_tumu(vbool32_t mask, vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) { vfloat64m2_t test_vfnmacc_vv_f64m2_tumu(vbool32_t mask, vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfnmacc_vv_f64m2_tumu(mask, vd, vs1, vs2, vl); return __riscv_vfnmacc_vv_f64m2_tumu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmacc_vf_f64m2_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmacc_vf_f64m2_tumu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmacc.mask.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmacc.mask.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfnmacc_vf_f64m2_tumu(vbool32_t mask, vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) { vfloat64m2_t test_vfnmacc_vf_f64m2_tumu(vbool32_t mask, vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfnmacc_vf_f64m2_tumu(mask, vd, rs1, vs2, vl); return __riscv_vfnmacc_vf_f64m2_tumu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmacc_vv_f64m4_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmacc_vv_f64m4_tumu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmacc.mask.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmacc.mask.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfnmacc_vv_f64m4_tumu(vbool16_t mask, vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) { vfloat64m4_t test_vfnmacc_vv_f64m4_tumu(vbool16_t mask, vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfnmacc_vv_f64m4_tumu(mask, vd, vs1, vs2, vl); return __riscv_vfnmacc_vv_f64m4_tumu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmacc_vf_f64m4_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmacc_vf_f64m4_tumu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmacc.mask.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmacc.mask.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfnmacc_vf_f64m4_tumu(vbool16_t mask, vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) { vfloat64m4_t test_vfnmacc_vf_f64m4_tumu(vbool16_t mask, vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfnmacc_vf_f64m4_tumu(mask, vd, rs1, vs2, vl); return __riscv_vfnmacc_vf_f64m4_tumu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmacc_vv_f64m8_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmacc_vv_f64m8_tumu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmacc.mask.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmacc.mask.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfnmacc_vv_f64m8_tumu(vbool8_t mask, vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) { vfloat64m8_t test_vfnmacc_vv_f64m8_tumu(vbool8_t mask, vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfnmacc_vv_f64m8_tumu(mask, vd, vs1, vs2, vl); return __riscv_vfnmacc_vv_f64m8_tumu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmacc_vf_f64m8_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmacc_vf_f64m8_tumu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmacc.mask.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmacc.mask.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfnmacc_vf_f64m8_tumu(vbool8_t mask, vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) { vfloat64m8_t test_vfnmacc_vf_f64m8_tumu(vbool8_t mask, vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfnmacc_vf_f64m8_tumu(mask, vd, rs1, vs2, vl); return __riscv_vfnmacc_vf_f64m8_tumu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmacc_vv_f16mf4_mu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmacc_vv_f16mf4_mu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmacc.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmacc.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
// //
vfloat16mf4_t test_vfnmacc_vv_f16mf4_mu(vbool64_t mask, vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) { vfloat16mf4_t test_vfnmacc_vv_f16mf4_mu(vbool64_t mask, vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfnmacc_vv_f16mf4_mu(mask, vd, vs1, vs2, vl); return __riscv_vfnmacc_vv_f16mf4_mu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmacc_vf_f16mf4_mu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmacc_vf_f16mf4_mu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmacc.mask.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmacc.mask.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
// //
vfloat16mf4_t test_vfnmacc_vf_f16mf4_mu(vbool64_t mask, vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) { vfloat16mf4_t test_vfnmacc_vf_f16mf4_mu(vbool64_t mask, vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfnmacc_vf_f16mf4_mu(mask, vd, rs1, vs2, vl); return __riscv_vfnmacc_vf_f16mf4_mu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmacc_vv_f16mf2_mu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmacc_vv_f16mf2_mu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmacc.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmacc.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
// //
vfloat16mf2_t test_vfnmacc_vv_f16mf2_mu(vbool32_t mask, vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) { vfloat16mf2_t test_vfnmacc_vv_f16mf2_mu(vbool32_t mask, vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfnmacc_vv_f16mf2_mu(mask, vd, vs1, vs2, vl); return __riscv_vfnmacc_vv_f16mf2_mu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmacc_vf_f16mf2_mu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmacc_vf_f16mf2_mu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmacc.mask.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmacc.mask.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
// //
vfloat16mf2_t test_vfnmacc_vf_f16mf2_mu(vbool32_t mask, vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) { vfloat16mf2_t test_vfnmacc_vf_f16mf2_mu(vbool32_t mask, vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfnmacc_vf_f16mf2_mu(mask, vd, rs1, vs2, vl); return __riscv_vfnmacc_vf_f16mf2_mu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmacc_vv_f16m1_mu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmacc_vv_f16m1_mu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmacc.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmacc.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
// //
vfloat16m1_t test_vfnmacc_vv_f16m1_mu(vbool16_t mask, vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) { vfloat16m1_t test_vfnmacc_vv_f16m1_mu(vbool16_t mask, vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfnmacc_vv_f16m1_mu(mask, vd, vs1, vs2, vl); return __riscv_vfnmacc_vv_f16m1_mu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmacc_vf_f16m1_mu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmacc_vf_f16m1_mu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmacc.mask.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmacc.mask.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
// //
vfloat16m1_t test_vfnmacc_vf_f16m1_mu(vbool16_t mask, vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) { vfloat16m1_t test_vfnmacc_vf_f16m1_mu(vbool16_t mask, vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfnmacc_vf_f16m1_mu(mask, vd, rs1, vs2, vl); return __riscv_vfnmacc_vf_f16m1_mu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmacc_vv_f16m2_mu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmacc_vv_f16m2_mu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmacc.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmacc.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
// //
vfloat16m2_t test_vfnmacc_vv_f16m2_mu(vbool8_t mask, vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) { vfloat16m2_t test_vfnmacc_vv_f16m2_mu(vbool8_t mask, vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfnmacc_vv_f16m2_mu(mask, vd, vs1, vs2, vl); return __riscv_vfnmacc_vv_f16m2_mu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmacc_vf_f16m2_mu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmacc_vf_f16m2_mu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmacc.mask.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmacc.mask.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
// //
vfloat16m2_t test_vfnmacc_vf_f16m2_mu(vbool8_t mask, vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) { vfloat16m2_t test_vfnmacc_vf_f16m2_mu(vbool8_t mask, vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfnmacc_vf_f16m2_mu(mask, vd, rs1, vs2, vl); return __riscv_vfnmacc_vf_f16m2_mu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmacc_vv_f16m4_mu // CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmacc_vv_f16m4_mu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmacc.mask.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmacc.mask.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
// //
vfloat16m4_t test_vfnmacc_vv_f16m4_mu(vbool4_t mask, vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) { vfloat16m4_t test_vfnmacc_vv_f16m4_mu(vbool4_t mask, vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfnmacc_vv_f16m4_mu(mask, vd, vs1, vs2, vl); return __riscv_vfnmacc_vv_f16m4_mu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmacc_vf_f16m4_mu // CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmacc_vf_f16m4_mu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmacc.mask.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmacc.mask.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
// //
vfloat16m4_t test_vfnmacc_vf_f16m4_mu(vbool4_t mask, vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) { vfloat16m4_t test_vfnmacc_vf_f16m4_mu(vbool4_t mask, vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfnmacc_vf_f16m4_mu(mask, vd, rs1, vs2, vl); return __riscv_vfnmacc_vf_f16m4_mu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmacc_vv_f16m8_mu // CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmacc_vv_f16m8_mu
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmacc.mask.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmacc.mask.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
// //
vfloat16m8_t test_vfnmacc_vv_f16m8_mu(vbool2_t mask, vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) { vfloat16m8_t test_vfnmacc_vv_f16m8_mu(vbool2_t mask, vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfnmacc_vv_f16m8_mu(mask, vd, vs1, vs2, vl); return __riscv_vfnmacc_vv_f16m8_mu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmacc_vf_f16m8_mu // CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmacc_vf_f16m8_mu
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmacc.mask.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmacc.mask.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
// //
vfloat16m8_t test_vfnmacc_vf_f16m8_mu(vbool2_t mask, vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) { vfloat16m8_t test_vfnmacc_vf_f16m8_mu(vbool2_t mask, vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfnmacc_vf_f16m8_mu(mask, vd, rs1, vs2, vl); return __riscv_vfnmacc_vf_f16m8_mu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmacc_vv_f32mf2_mu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmacc_vv_f32mf2_mu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmacc.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmacc.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfnmacc_vv_f32mf2_mu(vbool64_t mask, vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) { vfloat32mf2_t test_vfnmacc_vv_f32mf2_mu(vbool64_t mask, vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfnmacc_vv_f32mf2_mu(mask, vd, vs1, vs2, vl); return __riscv_vfnmacc_vv_f32mf2_mu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmacc_vf_f32mf2_mu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmacc_vf_f32mf2_mu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmacc.mask.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmacc.mask.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfnmacc_vf_f32mf2_mu(vbool64_t mask, vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) { vfloat32mf2_t test_vfnmacc_vf_f32mf2_mu(vbool64_t mask, vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfnmacc_vf_f32mf2_mu(mask, vd, rs1, vs2, vl); return __riscv_vfnmacc_vf_f32mf2_mu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmacc_vv_f32m1_mu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmacc_vv_f32m1_mu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmacc.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmacc.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfnmacc_vv_f32m1_mu(vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) { vfloat32m1_t test_vfnmacc_vv_f32m1_mu(vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfnmacc_vv_f32m1_mu(mask, vd, vs1, vs2, vl); return __riscv_vfnmacc_vv_f32m1_mu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmacc_vf_f32m1_mu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmacc_vf_f32m1_mu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmacc.mask.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmacc.mask.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfnmacc_vf_f32m1_mu(vbool32_t mask, vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) { vfloat32m1_t test_vfnmacc_vf_f32m1_mu(vbool32_t mask, vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfnmacc_vf_f32m1_mu(mask, vd, rs1, vs2, vl); return __riscv_vfnmacc_vf_f32m1_mu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmacc_vv_f32m2_mu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmacc_vv_f32m2_mu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmacc.mask.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmacc.mask.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfnmacc_vv_f32m2_mu(vbool16_t mask, vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) { vfloat32m2_t test_vfnmacc_vv_f32m2_mu(vbool16_t mask, vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfnmacc_vv_f32m2_mu(mask, vd, vs1, vs2, vl); return __riscv_vfnmacc_vv_f32m2_mu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmacc_vf_f32m2_mu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmacc_vf_f32m2_mu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmacc.mask.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmacc.mask.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfnmacc_vf_f32m2_mu(vbool16_t mask, vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) { vfloat32m2_t test_vfnmacc_vf_f32m2_mu(vbool16_t mask, vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfnmacc_vf_f32m2_mu(mask, vd, rs1, vs2, vl); return __riscv_vfnmacc_vf_f32m2_mu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmacc_vv_f32m4_mu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmacc_vv_f32m4_mu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmacc.mask.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmacc.mask.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfnmacc_vv_f32m4_mu(vbool8_t mask, vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) { vfloat32m4_t test_vfnmacc_vv_f32m4_mu(vbool8_t mask, vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfnmacc_vv_f32m4_mu(mask, vd, vs1, vs2, vl); return __riscv_vfnmacc_vv_f32m4_mu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmacc_vf_f32m4_mu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmacc_vf_f32m4_mu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmacc.mask.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmacc.mask.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfnmacc_vf_f32m4_mu(vbool8_t mask, vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) { vfloat32m4_t test_vfnmacc_vf_f32m4_mu(vbool8_t mask, vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfnmacc_vf_f32m4_mu(mask, vd, rs1, vs2, vl); return __riscv_vfnmacc_vf_f32m4_mu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmacc_vv_f32m8_mu // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmacc_vv_f32m8_mu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmacc.mask.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmacc.mask.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfnmacc_vv_f32m8_mu(vbool4_t mask, vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) { vfloat32m8_t test_vfnmacc_vv_f32m8_mu(vbool4_t mask, vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfnmacc_vv_f32m8_mu(mask, vd, vs1, vs2, vl); return __riscv_vfnmacc_vv_f32m8_mu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmacc_vf_f32m8_mu // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmacc_vf_f32m8_mu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmacc.mask.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmacc.mask.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfnmacc_vf_f32m8_mu(vbool4_t mask, vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) { vfloat32m8_t test_vfnmacc_vf_f32m8_mu(vbool4_t mask, vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfnmacc_vf_f32m8_mu(mask, vd, rs1, vs2, vl); return __riscv_vfnmacc_vf_f32m8_mu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmacc_vv_f64m1_mu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmacc_vv_f64m1_mu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmacc.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmacc.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfnmacc_vv_f64m1_mu(vbool64_t mask, vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) { vfloat64m1_t test_vfnmacc_vv_f64m1_mu(vbool64_t mask, vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfnmacc_vv_f64m1_mu(mask, vd, vs1, vs2, vl); return __riscv_vfnmacc_vv_f64m1_mu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmacc_vf_f64m1_mu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmacc_vf_f64m1_mu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmacc.mask.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmacc.mask.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfnmacc_vf_f64m1_mu(vbool64_t mask, vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) { vfloat64m1_t test_vfnmacc_vf_f64m1_mu(vbool64_t mask, vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfnmacc_vf_f64m1_mu(mask, vd, rs1, vs2, vl); return __riscv_vfnmacc_vf_f64m1_mu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmacc_vv_f64m2_mu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmacc_vv_f64m2_mu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmacc.mask.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmacc.mask.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfnmacc_vv_f64m2_mu(vbool32_t mask, vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) { vfloat64m2_t test_vfnmacc_vv_f64m2_mu(vbool32_t mask, vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfnmacc_vv_f64m2_mu(mask, vd, vs1, vs2, vl); return __riscv_vfnmacc_vv_f64m2_mu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmacc_vf_f64m2_mu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmacc_vf_f64m2_mu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmacc.mask.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmacc.mask.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfnmacc_vf_f64m2_mu(vbool32_t mask, vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) { vfloat64m2_t test_vfnmacc_vf_f64m2_mu(vbool32_t mask, vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfnmacc_vf_f64m2_mu(mask, vd, rs1, vs2, vl); return __riscv_vfnmacc_vf_f64m2_mu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmacc_vv_f64m4_mu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmacc_vv_f64m4_mu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmacc.mask.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmacc.mask.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfnmacc_vv_f64m4_mu(vbool16_t mask, vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) { vfloat64m4_t test_vfnmacc_vv_f64m4_mu(vbool16_t mask, vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfnmacc_vv_f64m4_mu(mask, vd, vs1, vs2, vl); return __riscv_vfnmacc_vv_f64m4_mu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmacc_vf_f64m4_mu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmacc_vf_f64m4_mu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmacc.mask.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmacc.mask.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfnmacc_vf_f64m4_mu(vbool16_t mask, vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) { vfloat64m4_t test_vfnmacc_vf_f64m4_mu(vbool16_t mask, vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfnmacc_vf_f64m4_mu(mask, vd, rs1, vs2, vl); return __riscv_vfnmacc_vf_f64m4_mu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmacc_vv_f64m8_mu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmacc_vv_f64m8_mu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmacc.mask.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmacc.mask.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfnmacc_vv_f64m8_mu(vbool8_t mask, vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) { vfloat64m8_t test_vfnmacc_vv_f64m8_mu(vbool8_t mask, vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfnmacc_vv_f64m8_mu(mask, vd, vs1, vs2, vl); return __riscv_vfnmacc_vv_f64m8_mu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmacc_vf_f64m8_mu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmacc_vf_f64m8_mu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmacc.mask.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmacc.mask.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfnmacc_vf_f64m8_mu(vbool8_t mask, vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) { vfloat64m8_t test_vfnmacc_vf_f64m8_mu(vbool8_t mask, vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfnmacc_vf_f64m8_mu(mask, vd, rs1, vs2, vl); return __riscv_vfnmacc_vf_f64m8_mu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmacc_vv_f16mf4_rm_tu
// CHECK-RV64-SAME: (<vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmacc.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
//
vfloat16mf4_t test_vfnmacc_vv_f16mf4_rm_tu(vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfnmacc_vv_f16mf4_rm_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmacc_vf_f16mf4_rm_tu
// CHECK-RV64-SAME: (<vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmacc.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
//
vfloat16mf4_t test_vfnmacc_vf_f16mf4_rm_tu(vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfnmacc_vf_f16mf4_rm_tu(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmacc_vv_f16mf2_rm_tu
// CHECK-RV64-SAME: (<vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmacc.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
//
vfloat16mf2_t test_vfnmacc_vv_f16mf2_rm_tu(vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfnmacc_vv_f16mf2_rm_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmacc_vf_f16mf2_rm_tu
// CHECK-RV64-SAME: (<vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmacc.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
//
vfloat16mf2_t test_vfnmacc_vf_f16mf2_rm_tu(vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfnmacc_vf_f16mf2_rm_tu(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmacc_vv_f16m1_rm_tu
// CHECK-RV64-SAME: (<vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmacc.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfnmacc_vv_f16m1_rm_tu(vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfnmacc_vv_f16m1_rm_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmacc_vf_f16m1_rm_tu
// CHECK-RV64-SAME: (<vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmacc.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfnmacc_vf_f16m1_rm_tu(vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfnmacc_vf_f16m1_rm_tu(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmacc_vv_f16m2_rm_tu
// CHECK-RV64-SAME: (<vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmacc.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
//
vfloat16m2_t test_vfnmacc_vv_f16m2_rm_tu(vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfnmacc_vv_f16m2_rm_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmacc_vf_f16m2_rm_tu
// CHECK-RV64-SAME: (<vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmacc.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
//
vfloat16m2_t test_vfnmacc_vf_f16m2_rm_tu(vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfnmacc_vf_f16m2_rm_tu(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmacc_vv_f16m4_rm_tu
// CHECK-RV64-SAME: (<vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmacc.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
//
vfloat16m4_t test_vfnmacc_vv_f16m4_rm_tu(vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfnmacc_vv_f16m4_rm_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmacc_vf_f16m4_rm_tu
// CHECK-RV64-SAME: (<vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmacc.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
//
vfloat16m4_t test_vfnmacc_vf_f16m4_rm_tu(vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfnmacc_vf_f16m4_rm_tu(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmacc_vv_f16m8_rm_tu
// CHECK-RV64-SAME: (<vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmacc.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
//
vfloat16m8_t test_vfnmacc_vv_f16m8_rm_tu(vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfnmacc_vv_f16m8_rm_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmacc_vf_f16m8_rm_tu
// CHECK-RV64-SAME: (<vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmacc.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
//
vfloat16m8_t test_vfnmacc_vf_f16m8_rm_tu(vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfnmacc_vf_f16m8_rm_tu(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmacc_vv_f32mf2_rm_tu
// CHECK-RV64-SAME: (<vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmacc.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
//
vfloat32mf2_t test_vfnmacc_vv_f32mf2_rm_tu(vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfnmacc_vv_f32mf2_rm_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmacc_vf_f32mf2_rm_tu
// CHECK-RV64-SAME: (<vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmacc.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
//
vfloat32mf2_t test_vfnmacc_vf_f32mf2_rm_tu(vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfnmacc_vf_f32mf2_rm_tu(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmacc_vv_f32m1_rm_tu
// CHECK-RV64-SAME: (<vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmacc.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfnmacc_vv_f32m1_rm_tu(vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfnmacc_vv_f32m1_rm_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmacc_vf_f32m1_rm_tu
// CHECK-RV64-SAME: (<vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmacc.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfnmacc_vf_f32m1_rm_tu(vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfnmacc_vf_f32m1_rm_tu(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmacc_vv_f32m2_rm_tu
// CHECK-RV64-SAME: (<vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmacc.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
//
vfloat32m2_t test_vfnmacc_vv_f32m2_rm_tu(vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfnmacc_vv_f32m2_rm_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmacc_vf_f32m2_rm_tu
// CHECK-RV64-SAME: (<vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmacc.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
//
vfloat32m2_t test_vfnmacc_vf_f32m2_rm_tu(vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfnmacc_vf_f32m2_rm_tu(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmacc_vv_f32m4_rm_tu
// CHECK-RV64-SAME: (<vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmacc.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
//
vfloat32m4_t test_vfnmacc_vv_f32m4_rm_tu(vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfnmacc_vv_f32m4_rm_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmacc_vf_f32m4_rm_tu
// CHECK-RV64-SAME: (<vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmacc.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
//
vfloat32m4_t test_vfnmacc_vf_f32m4_rm_tu(vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfnmacc_vf_f32m4_rm_tu(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmacc_vv_f32m8_rm_tu
// CHECK-RV64-SAME: (<vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmacc.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
//
vfloat32m8_t test_vfnmacc_vv_f32m8_rm_tu(vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfnmacc_vv_f32m8_rm_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmacc_vf_f32m8_rm_tu
// CHECK-RV64-SAME: (<vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmacc.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
//
vfloat32m8_t test_vfnmacc_vf_f32m8_rm_tu(vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfnmacc_vf_f32m8_rm_tu(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmacc_vv_f64m1_rm_tu
// CHECK-RV64-SAME: (<vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmacc.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfnmacc_vv_f64m1_rm_tu(vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfnmacc_vv_f64m1_rm_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmacc_vf_f64m1_rm_tu
// CHECK-RV64-SAME: (<vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmacc.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfnmacc_vf_f64m1_rm_tu(vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfnmacc_vf_f64m1_rm_tu(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmacc_vv_f64m2_rm_tu
// CHECK-RV64-SAME: (<vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmacc.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
//
vfloat64m2_t test_vfnmacc_vv_f64m2_rm_tu(vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfnmacc_vv_f64m2_rm_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmacc_vf_f64m2_rm_tu
// CHECK-RV64-SAME: (<vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmacc.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
//
vfloat64m2_t test_vfnmacc_vf_f64m2_rm_tu(vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfnmacc_vf_f64m2_rm_tu(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmacc_vv_f64m4_rm_tu
// CHECK-RV64-SAME: (<vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmacc.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
//
vfloat64m4_t test_vfnmacc_vv_f64m4_rm_tu(vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfnmacc_vv_f64m4_rm_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmacc_vf_f64m4_rm_tu
// CHECK-RV64-SAME: (<vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmacc.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
//
vfloat64m4_t test_vfnmacc_vf_f64m4_rm_tu(vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfnmacc_vf_f64m4_rm_tu(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmacc_vv_f64m8_rm_tu
// CHECK-RV64-SAME: (<vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmacc.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
//
vfloat64m8_t test_vfnmacc_vv_f64m8_rm_tu(vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfnmacc_vv_f64m8_rm_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmacc_vf_f64m8_rm_tu
// CHECK-RV64-SAME: (<vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmacc.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
//
vfloat64m8_t test_vfnmacc_vf_f64m8_rm_tu(vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfnmacc_vf_f64m8_rm_tu(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmacc_vv_f16mf4_rm_tum
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmacc.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
//
vfloat16mf4_t test_vfnmacc_vv_f16mf4_rm_tum(vbool64_t mask, vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfnmacc_vv_f16mf4_rm_tum(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmacc_vf_f16mf4_rm_tum
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmacc.mask.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
//
vfloat16mf4_t test_vfnmacc_vf_f16mf4_rm_tum(vbool64_t mask, vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfnmacc_vf_f16mf4_rm_tum(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmacc_vv_f16mf2_rm_tum
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmacc.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
//
vfloat16mf2_t test_vfnmacc_vv_f16mf2_rm_tum(vbool32_t mask, vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfnmacc_vv_f16mf2_rm_tum(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmacc_vf_f16mf2_rm_tum
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmacc.mask.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
//
vfloat16mf2_t test_vfnmacc_vf_f16mf2_rm_tum(vbool32_t mask, vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfnmacc_vf_f16mf2_rm_tum(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmacc_vv_f16m1_rm_tum
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmacc.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfnmacc_vv_f16m1_rm_tum(vbool16_t mask, vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfnmacc_vv_f16m1_rm_tum(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmacc_vf_f16m1_rm_tum
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmacc.mask.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfnmacc_vf_f16m1_rm_tum(vbool16_t mask, vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfnmacc_vf_f16m1_rm_tum(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmacc_vv_f16m2_rm_tum
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmacc.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
//
vfloat16m2_t test_vfnmacc_vv_f16m2_rm_tum(vbool8_t mask, vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfnmacc_vv_f16m2_rm_tum(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmacc_vf_f16m2_rm_tum
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmacc.mask.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
//
vfloat16m2_t test_vfnmacc_vf_f16m2_rm_tum(vbool8_t mask, vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfnmacc_vf_f16m2_rm_tum(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmacc_vv_f16m4_rm_tum
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmacc.mask.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
//
vfloat16m4_t test_vfnmacc_vv_f16m4_rm_tum(vbool4_t mask, vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfnmacc_vv_f16m4_rm_tum(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmacc_vf_f16m4_rm_tum
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmacc.mask.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
//
vfloat16m4_t test_vfnmacc_vf_f16m4_rm_tum(vbool4_t mask, vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfnmacc_vf_f16m4_rm_tum(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmacc_vv_f16m8_rm_tum
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmacc.mask.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
//
vfloat16m8_t test_vfnmacc_vv_f16m8_rm_tum(vbool2_t mask, vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfnmacc_vv_f16m8_rm_tum(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmacc_vf_f16m8_rm_tum
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmacc.mask.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
//
vfloat16m8_t test_vfnmacc_vf_f16m8_rm_tum(vbool2_t mask, vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfnmacc_vf_f16m8_rm_tum(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmacc_vv_f32mf2_rm_tum
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmacc.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
//
vfloat32mf2_t test_vfnmacc_vv_f32mf2_rm_tum(vbool64_t mask, vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfnmacc_vv_f32mf2_rm_tum(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmacc_vf_f32mf2_rm_tum
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmacc.mask.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
//
vfloat32mf2_t test_vfnmacc_vf_f32mf2_rm_tum(vbool64_t mask, vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfnmacc_vf_f32mf2_rm_tum(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmacc_vv_f32m1_rm_tum
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmacc.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfnmacc_vv_f32m1_rm_tum(vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfnmacc_vv_f32m1_rm_tum(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmacc_vf_f32m1_rm_tum
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmacc.mask.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfnmacc_vf_f32m1_rm_tum(vbool32_t mask, vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfnmacc_vf_f32m1_rm_tum(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmacc_vv_f32m2_rm_tum
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmacc.mask.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
//
vfloat32m2_t test_vfnmacc_vv_f32m2_rm_tum(vbool16_t mask, vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfnmacc_vv_f32m2_rm_tum(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmacc_vf_f32m2_rm_tum
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmacc.mask.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
//
vfloat32m2_t test_vfnmacc_vf_f32m2_rm_tum(vbool16_t mask, vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfnmacc_vf_f32m2_rm_tum(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmacc_vv_f32m4_rm_tum
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmacc.mask.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
//
vfloat32m4_t test_vfnmacc_vv_f32m4_rm_tum(vbool8_t mask, vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfnmacc_vv_f32m4_rm_tum(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmacc_vf_f32m4_rm_tum
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmacc.mask.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
//
vfloat32m4_t test_vfnmacc_vf_f32m4_rm_tum(vbool8_t mask, vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfnmacc_vf_f32m4_rm_tum(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmacc_vv_f32m8_rm_tum
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmacc.mask.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
//
vfloat32m8_t test_vfnmacc_vv_f32m8_rm_tum(vbool4_t mask, vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfnmacc_vv_f32m8_rm_tum(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmacc_vf_f32m8_rm_tum
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmacc.mask.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
//
vfloat32m8_t test_vfnmacc_vf_f32m8_rm_tum(vbool4_t mask, vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfnmacc_vf_f32m8_rm_tum(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmacc_vv_f64m1_rm_tum
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmacc.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfnmacc_vv_f64m1_rm_tum(vbool64_t mask, vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfnmacc_vv_f64m1_rm_tum(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmacc_vf_f64m1_rm_tum
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmacc.mask.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfnmacc_vf_f64m1_rm_tum(vbool64_t mask, vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfnmacc_vf_f64m1_rm_tum(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmacc_vv_f64m2_rm_tum
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmacc.mask.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
//
vfloat64m2_t test_vfnmacc_vv_f64m2_rm_tum(vbool32_t mask, vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfnmacc_vv_f64m2_rm_tum(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmacc_vf_f64m2_rm_tum
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmacc.mask.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
//
vfloat64m2_t test_vfnmacc_vf_f64m2_rm_tum(vbool32_t mask, vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfnmacc_vf_f64m2_rm_tum(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmacc_vv_f64m4_rm_tum
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmacc.mask.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
//
vfloat64m4_t test_vfnmacc_vv_f64m4_rm_tum(vbool16_t mask, vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfnmacc_vv_f64m4_rm_tum(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmacc_vf_f64m4_rm_tum
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmacc.mask.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
//
vfloat64m4_t test_vfnmacc_vf_f64m4_rm_tum(vbool16_t mask, vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfnmacc_vf_f64m4_rm_tum(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmacc_vv_f64m8_rm_tum
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmacc.mask.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
//
vfloat64m8_t test_vfnmacc_vv_f64m8_rm_tum(vbool8_t mask, vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfnmacc_vv_f64m8_rm_tum(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmacc_vf_f64m8_rm_tum
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmacc.mask.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
//
vfloat64m8_t test_vfnmacc_vf_f64m8_rm_tum(vbool8_t mask, vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfnmacc_vf_f64m8_rm_tum(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmacc_vv_f16mf4_rm_tumu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmacc.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
//
vfloat16mf4_t test_vfnmacc_vv_f16mf4_rm_tumu(vbool64_t mask, vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfnmacc_vv_f16mf4_rm_tumu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmacc_vf_f16mf4_rm_tumu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmacc.mask.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
//
vfloat16mf4_t test_vfnmacc_vf_f16mf4_rm_tumu(vbool64_t mask, vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfnmacc_vf_f16mf4_rm_tumu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmacc_vv_f16mf2_rm_tumu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmacc.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
//
vfloat16mf2_t test_vfnmacc_vv_f16mf2_rm_tumu(vbool32_t mask, vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfnmacc_vv_f16mf2_rm_tumu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmacc_vf_f16mf2_rm_tumu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmacc.mask.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
//
vfloat16mf2_t test_vfnmacc_vf_f16mf2_rm_tumu(vbool32_t mask, vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfnmacc_vf_f16mf2_rm_tumu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmacc_vv_f16m1_rm_tumu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmacc.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfnmacc_vv_f16m1_rm_tumu(vbool16_t mask, vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfnmacc_vv_f16m1_rm_tumu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmacc_vf_f16m1_rm_tumu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmacc.mask.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfnmacc_vf_f16m1_rm_tumu(vbool16_t mask, vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfnmacc_vf_f16m1_rm_tumu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmacc_vv_f16m2_rm_tumu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmacc.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
//
vfloat16m2_t test_vfnmacc_vv_f16m2_rm_tumu(vbool8_t mask, vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfnmacc_vv_f16m2_rm_tumu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmacc_vf_f16m2_rm_tumu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmacc.mask.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
//
vfloat16m2_t test_vfnmacc_vf_f16m2_rm_tumu(vbool8_t mask, vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfnmacc_vf_f16m2_rm_tumu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmacc_vv_f16m4_rm_tumu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmacc.mask.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
//
vfloat16m4_t test_vfnmacc_vv_f16m4_rm_tumu(vbool4_t mask, vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfnmacc_vv_f16m4_rm_tumu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmacc_vf_f16m4_rm_tumu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmacc.mask.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
//
vfloat16m4_t test_vfnmacc_vf_f16m4_rm_tumu(vbool4_t mask, vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfnmacc_vf_f16m4_rm_tumu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmacc_vv_f16m8_rm_tumu
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmacc.mask.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
//
vfloat16m8_t test_vfnmacc_vv_f16m8_rm_tumu(vbool2_t mask, vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfnmacc_vv_f16m8_rm_tumu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmacc_vf_f16m8_rm_tumu
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmacc.mask.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
//
vfloat16m8_t test_vfnmacc_vf_f16m8_rm_tumu(vbool2_t mask, vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfnmacc_vf_f16m8_rm_tumu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmacc_vv_f32mf2_rm_tumu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmacc.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
//
vfloat32mf2_t test_vfnmacc_vv_f32mf2_rm_tumu(vbool64_t mask, vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfnmacc_vv_f32mf2_rm_tumu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmacc_vf_f32mf2_rm_tumu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmacc.mask.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
//
vfloat32mf2_t test_vfnmacc_vf_f32mf2_rm_tumu(vbool64_t mask, vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfnmacc_vf_f32mf2_rm_tumu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmacc_vv_f32m1_rm_tumu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmacc.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfnmacc_vv_f32m1_rm_tumu(vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfnmacc_vv_f32m1_rm_tumu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmacc_vf_f32m1_rm_tumu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmacc.mask.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfnmacc_vf_f32m1_rm_tumu(vbool32_t mask, vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfnmacc_vf_f32m1_rm_tumu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmacc_vv_f32m2_rm_tumu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmacc.mask.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
//
vfloat32m2_t test_vfnmacc_vv_f32m2_rm_tumu(vbool16_t mask, vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfnmacc_vv_f32m2_rm_tumu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmacc_vf_f32m2_rm_tumu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmacc.mask.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
//
vfloat32m2_t test_vfnmacc_vf_f32m2_rm_tumu(vbool16_t mask, vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfnmacc_vf_f32m2_rm_tumu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmacc_vv_f32m4_rm_tumu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmacc.mask.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
//
vfloat32m4_t test_vfnmacc_vv_f32m4_rm_tumu(vbool8_t mask, vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfnmacc_vv_f32m4_rm_tumu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmacc_vf_f32m4_rm_tumu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmacc.mask.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
//
vfloat32m4_t test_vfnmacc_vf_f32m4_rm_tumu(vbool8_t mask, vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfnmacc_vf_f32m4_rm_tumu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmacc_vv_f32m8_rm_tumu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmacc.mask.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
//
vfloat32m8_t test_vfnmacc_vv_f32m8_rm_tumu(vbool4_t mask, vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfnmacc_vv_f32m8_rm_tumu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmacc_vf_f32m8_rm_tumu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmacc.mask.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
//
vfloat32m8_t test_vfnmacc_vf_f32m8_rm_tumu(vbool4_t mask, vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfnmacc_vf_f32m8_rm_tumu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmacc_vv_f64m1_rm_tumu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmacc.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfnmacc_vv_f64m1_rm_tumu(vbool64_t mask, vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfnmacc_vv_f64m1_rm_tumu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmacc_vf_f64m1_rm_tumu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmacc.mask.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfnmacc_vf_f64m1_rm_tumu(vbool64_t mask, vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfnmacc_vf_f64m1_rm_tumu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmacc_vv_f64m2_rm_tumu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmacc.mask.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
//
vfloat64m2_t test_vfnmacc_vv_f64m2_rm_tumu(vbool32_t mask, vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfnmacc_vv_f64m2_rm_tumu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmacc_vf_f64m2_rm_tumu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmacc.mask.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
//
vfloat64m2_t test_vfnmacc_vf_f64m2_rm_tumu(vbool32_t mask, vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfnmacc_vf_f64m2_rm_tumu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmacc_vv_f64m4_rm_tumu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmacc.mask.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
//
vfloat64m4_t test_vfnmacc_vv_f64m4_rm_tumu(vbool16_t mask, vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfnmacc_vv_f64m4_rm_tumu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmacc_vf_f64m4_rm_tumu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmacc.mask.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
//
vfloat64m4_t test_vfnmacc_vf_f64m4_rm_tumu(vbool16_t mask, vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfnmacc_vf_f64m4_rm_tumu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmacc_vv_f64m8_rm_tumu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmacc.mask.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
//
vfloat64m8_t test_vfnmacc_vv_f64m8_rm_tumu(vbool8_t mask, vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfnmacc_vv_f64m8_rm_tumu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmacc_vf_f64m8_rm_tumu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmacc.mask.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
//
vfloat64m8_t test_vfnmacc_vf_f64m8_rm_tumu(vbool8_t mask, vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfnmacc_vf_f64m8_rm_tumu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmacc_vv_f16mf4_rm_mu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmacc.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
//
vfloat16mf4_t test_vfnmacc_vv_f16mf4_rm_mu(vbool64_t mask, vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfnmacc_vv_f16mf4_rm_mu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmacc_vf_f16mf4_rm_mu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmacc.mask.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
//
vfloat16mf4_t test_vfnmacc_vf_f16mf4_rm_mu(vbool64_t mask, vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfnmacc_vf_f16mf4_rm_mu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmacc_vv_f16mf2_rm_mu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmacc.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
//
vfloat16mf2_t test_vfnmacc_vv_f16mf2_rm_mu(vbool32_t mask, vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfnmacc_vv_f16mf2_rm_mu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmacc_vf_f16mf2_rm_mu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmacc.mask.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
//
vfloat16mf2_t test_vfnmacc_vf_f16mf2_rm_mu(vbool32_t mask, vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfnmacc_vf_f16mf2_rm_mu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmacc_vv_f16m1_rm_mu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmacc.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfnmacc_vv_f16m1_rm_mu(vbool16_t mask, vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfnmacc_vv_f16m1_rm_mu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmacc_vf_f16m1_rm_mu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmacc.mask.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfnmacc_vf_f16m1_rm_mu(vbool16_t mask, vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfnmacc_vf_f16m1_rm_mu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmacc_vv_f16m2_rm_mu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmacc.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
//
vfloat16m2_t test_vfnmacc_vv_f16m2_rm_mu(vbool8_t mask, vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfnmacc_vv_f16m2_rm_mu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmacc_vf_f16m2_rm_mu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmacc.mask.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
//
vfloat16m2_t test_vfnmacc_vf_f16m2_rm_mu(vbool8_t mask, vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfnmacc_vf_f16m2_rm_mu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmacc_vv_f16m4_rm_mu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmacc.mask.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
//
vfloat16m4_t test_vfnmacc_vv_f16m4_rm_mu(vbool4_t mask, vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfnmacc_vv_f16m4_rm_mu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmacc_vf_f16m4_rm_mu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmacc.mask.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
//
vfloat16m4_t test_vfnmacc_vf_f16m4_rm_mu(vbool4_t mask, vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfnmacc_vf_f16m4_rm_mu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmacc_vv_f16m8_rm_mu
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmacc.mask.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
//
vfloat16m8_t test_vfnmacc_vv_f16m8_rm_mu(vbool2_t mask, vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfnmacc_vv_f16m8_rm_mu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmacc_vf_f16m8_rm_mu
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmacc.mask.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
//
vfloat16m8_t test_vfnmacc_vf_f16m8_rm_mu(vbool2_t mask, vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfnmacc_vf_f16m8_rm_mu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmacc_vv_f32mf2_rm_mu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmacc.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
//
vfloat32mf2_t test_vfnmacc_vv_f32mf2_rm_mu(vbool64_t mask, vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfnmacc_vv_f32mf2_rm_mu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmacc_vf_f32mf2_rm_mu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmacc.mask.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
//
vfloat32mf2_t test_vfnmacc_vf_f32mf2_rm_mu(vbool64_t mask, vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfnmacc_vf_f32mf2_rm_mu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmacc_vv_f32m1_rm_mu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmacc.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfnmacc_vv_f32m1_rm_mu(vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfnmacc_vv_f32m1_rm_mu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmacc_vf_f32m1_rm_mu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmacc.mask.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfnmacc_vf_f32m1_rm_mu(vbool32_t mask, vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfnmacc_vf_f32m1_rm_mu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmacc_vv_f32m2_rm_mu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmacc.mask.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
//
vfloat32m2_t test_vfnmacc_vv_f32m2_rm_mu(vbool16_t mask, vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfnmacc_vv_f32m2_rm_mu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmacc_vf_f32m2_rm_mu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmacc.mask.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
//
vfloat32m2_t test_vfnmacc_vf_f32m2_rm_mu(vbool16_t mask, vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfnmacc_vf_f32m2_rm_mu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmacc_vv_f32m4_rm_mu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmacc.mask.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
//
vfloat32m4_t test_vfnmacc_vv_f32m4_rm_mu(vbool8_t mask, vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfnmacc_vv_f32m4_rm_mu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmacc_vf_f32m4_rm_mu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmacc.mask.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
//
vfloat32m4_t test_vfnmacc_vf_f32m4_rm_mu(vbool8_t mask, vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfnmacc_vf_f32m4_rm_mu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmacc_vv_f32m8_rm_mu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmacc.mask.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
//
vfloat32m8_t test_vfnmacc_vv_f32m8_rm_mu(vbool4_t mask, vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfnmacc_vv_f32m8_rm_mu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmacc_vf_f32m8_rm_mu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmacc.mask.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
//
vfloat32m8_t test_vfnmacc_vf_f32m8_rm_mu(vbool4_t mask, vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfnmacc_vf_f32m8_rm_mu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmacc_vv_f64m1_rm_mu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmacc.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfnmacc_vv_f64m1_rm_mu(vbool64_t mask, vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfnmacc_vv_f64m1_rm_mu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmacc_vf_f64m1_rm_mu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmacc.mask.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfnmacc_vf_f64m1_rm_mu(vbool64_t mask, vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfnmacc_vf_f64m1_rm_mu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmacc_vv_f64m2_rm_mu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmacc.mask.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
//
vfloat64m2_t test_vfnmacc_vv_f64m2_rm_mu(vbool32_t mask, vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfnmacc_vv_f64m2_rm_mu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmacc_vf_f64m2_rm_mu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmacc.mask.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
//
vfloat64m2_t test_vfnmacc_vf_f64m2_rm_mu(vbool32_t mask, vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfnmacc_vf_f64m2_rm_mu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmacc_vv_f64m4_rm_mu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmacc.mask.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
//
vfloat64m4_t test_vfnmacc_vv_f64m4_rm_mu(vbool16_t mask, vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfnmacc_vv_f64m4_rm_mu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmacc_vf_f64m4_rm_mu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmacc.mask.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
//
vfloat64m4_t test_vfnmacc_vf_f64m4_rm_mu(vbool16_t mask, vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfnmacc_vf_f64m4_rm_mu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmacc_vv_f64m8_rm_mu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmacc.mask.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
//
vfloat64m8_t test_vfnmacc_vv_f64m8_rm_mu(vbool8_t mask, vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfnmacc_vv_f64m8_rm_mu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmacc_vf_f64m8_rm_mu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmacc.mask.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
//
vfloat64m8_t test_vfnmacc_vf_f64m8_rm_mu(vbool8_t mask, vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfnmacc_vf_f64m8_rm_mu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}

clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmadd.c

// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target // REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh \ // RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh \
// RUN: -target-feature +experimental-zvfh -disable-O0-optnone \ // RUN: -target-feature +experimental-zvfh -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ // RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s // RUN: FileCheck --check-prefix=CHECK-RV64 %s
#include <riscv_vector.h> #include <riscv_vector.h>
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmadd_vv_f16mf4_tu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmadd_vv_f16mf4_tu
// CHECK-RV64-SAME: (<vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK-RV64-SAME: (<vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmadd.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmadd.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
// //
vfloat16mf4_t test_vfnmadd_vv_f16mf4_tu(vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) { vfloat16mf4_t test_vfnmadd_vv_f16mf4_tu(vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfnmadd_vv_f16mf4_tu(vd, vs1, vs2, vl); return __riscv_vfnmadd_vv_f16mf4_tu(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmadd_vf_f16mf4_tu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmadd_vf_f16mf4_tu
// CHECK-RV64-SAME: (<vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmadd.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmadd.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
// //
vfloat16mf4_t test_vfnmadd_vf_f16mf4_tu(vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) { vfloat16mf4_t test_vfnmadd_vf_f16mf4_tu(vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfnmadd_vf_f16mf4_tu(vd, rs1, vs2, vl); return __riscv_vfnmadd_vf_f16mf4_tu(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmadd_vv_f16mf2_tu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmadd_vv_f16mf2_tu
// CHECK-RV64-SAME: (<vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmadd.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmadd.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
// //
vfloat16mf2_t test_vfnmadd_vv_f16mf2_tu(vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) { vfloat16mf2_t test_vfnmadd_vv_f16mf2_tu(vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfnmadd_vv_f16mf2_tu(vd, vs1, vs2, vl); return __riscv_vfnmadd_vv_f16mf2_tu(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmadd_vf_f16mf2_tu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmadd_vf_f16mf2_tu
// CHECK-RV64-SAME: (<vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmadd.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmadd.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
// //
vfloat16mf2_t test_vfnmadd_vf_f16mf2_tu(vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) { vfloat16mf2_t test_vfnmadd_vf_f16mf2_tu(vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfnmadd_vf_f16mf2_tu(vd, rs1, vs2, vl); return __riscv_vfnmadd_vf_f16mf2_tu(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmadd_vv_f16m1_tu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmadd_vv_f16m1_tu
// CHECK-RV64-SAME: (<vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmadd.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmadd.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
// //
vfloat16m1_t test_vfnmadd_vv_f16m1_tu(vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) { vfloat16m1_t test_vfnmadd_vv_f16m1_tu(vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfnmadd_vv_f16m1_tu(vd, vs1, vs2, vl); return __riscv_vfnmadd_vv_f16m1_tu(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmadd_vf_f16m1_tu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmadd_vf_f16m1_tu
// CHECK-RV64-SAME: (<vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmadd.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmadd.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
// //
vfloat16m1_t test_vfnmadd_vf_f16m1_tu(vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) { vfloat16m1_t test_vfnmadd_vf_f16m1_tu(vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfnmadd_vf_f16m1_tu(vd, rs1, vs2, vl); return __riscv_vfnmadd_vf_f16m1_tu(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmadd_vv_f16m2_tu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmadd_vv_f16m2_tu
// CHECK-RV64-SAME: (<vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmadd.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmadd.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
// //
vfloat16m2_t test_vfnmadd_vv_f16m2_tu(vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) { vfloat16m2_t test_vfnmadd_vv_f16m2_tu(vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfnmadd_vv_f16m2_tu(vd, vs1, vs2, vl); return __riscv_vfnmadd_vv_f16m2_tu(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmadd_vf_f16m2_tu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmadd_vf_f16m2_tu
// CHECK-RV64-SAME: (<vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmadd.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmadd.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
// //
vfloat16m2_t test_vfnmadd_vf_f16m2_tu(vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) { vfloat16m2_t test_vfnmadd_vf_f16m2_tu(vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfnmadd_vf_f16m2_tu(vd, rs1, vs2, vl); return __riscv_vfnmadd_vf_f16m2_tu(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmadd_vv_f16m4_tu // CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmadd_vv_f16m4_tu
// CHECK-RV64-SAME: (<vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmadd.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmadd.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
// //
vfloat16m4_t test_vfnmadd_vv_f16m4_tu(vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) { vfloat16m4_t test_vfnmadd_vv_f16m4_tu(vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfnmadd_vv_f16m4_tu(vd, vs1, vs2, vl); return __riscv_vfnmadd_vv_f16m4_tu(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmadd_vf_f16m4_tu // CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmadd_vf_f16m4_tu
// CHECK-RV64-SAME: (<vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmadd.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmadd.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
// //
vfloat16m4_t test_vfnmadd_vf_f16m4_tu(vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) { vfloat16m4_t test_vfnmadd_vf_f16m4_tu(vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfnmadd_vf_f16m4_tu(vd, rs1, vs2, vl); return __riscv_vfnmadd_vf_f16m4_tu(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmadd_vv_f16m8_tu // CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmadd_vv_f16m8_tu
// CHECK-RV64-SAME: (<vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmadd.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmadd.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
// //
vfloat16m8_t test_vfnmadd_vv_f16m8_tu(vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) { vfloat16m8_t test_vfnmadd_vv_f16m8_tu(vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfnmadd_vv_f16m8_tu(vd, vs1, vs2, vl); return __riscv_vfnmadd_vv_f16m8_tu(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmadd_vf_f16m8_tu // CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmadd_vf_f16m8_tu
// CHECK-RV64-SAME: (<vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmadd.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmadd.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
// //
vfloat16m8_t test_vfnmadd_vf_f16m8_tu(vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) { vfloat16m8_t test_vfnmadd_vf_f16m8_tu(vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfnmadd_vf_f16m8_tu(vd, rs1, vs2, vl); return __riscv_vfnmadd_vf_f16m8_tu(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmadd_vv_f32mf2_tu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmadd_vv_f32mf2_tu
// CHECK-RV64-SAME: (<vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmadd.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmadd.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfnmadd_vv_f32mf2_tu(vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) { vfloat32mf2_t test_vfnmadd_vv_f32mf2_tu(vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfnmadd_vv_f32mf2_tu(vd, vs1, vs2, vl); return __riscv_vfnmadd_vv_f32mf2_tu(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmadd_vf_f32mf2_tu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmadd_vf_f32mf2_tu
// CHECK-RV64-SAME: (<vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmadd.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmadd.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfnmadd_vf_f32mf2_tu(vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) { vfloat32mf2_t test_vfnmadd_vf_f32mf2_tu(vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfnmadd_vf_f32mf2_tu(vd, rs1, vs2, vl); return __riscv_vfnmadd_vf_f32mf2_tu(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmadd_vv_f32m1_tu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmadd_vv_f32m1_tu
// CHECK-RV64-SAME: (<vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmadd.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmadd.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfnmadd_vv_f32m1_tu(vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) { vfloat32m1_t test_vfnmadd_vv_f32m1_tu(vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfnmadd_vv_f32m1_tu(vd, vs1, vs2, vl); return __riscv_vfnmadd_vv_f32m1_tu(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmadd_vf_f32m1_tu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmadd_vf_f32m1_tu
// CHECK-RV64-SAME: (<vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmadd.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmadd.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfnmadd_vf_f32m1_tu(vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) { vfloat32m1_t test_vfnmadd_vf_f32m1_tu(vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfnmadd_vf_f32m1_tu(vd, rs1, vs2, vl); return __riscv_vfnmadd_vf_f32m1_tu(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmadd_vv_f32m2_tu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmadd_vv_f32m2_tu
// CHECK-RV64-SAME: (<vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmadd.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmadd.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfnmadd_vv_f32m2_tu(vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) { vfloat32m2_t test_vfnmadd_vv_f32m2_tu(vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfnmadd_vv_f32m2_tu(vd, vs1, vs2, vl); return __riscv_vfnmadd_vv_f32m2_tu(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmadd_vf_f32m2_tu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmadd_vf_f32m2_tu
// CHECK-RV64-SAME: (<vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmadd.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmadd.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfnmadd_vf_f32m2_tu(vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) { vfloat32m2_t test_vfnmadd_vf_f32m2_tu(vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfnmadd_vf_f32m2_tu(vd, rs1, vs2, vl); return __riscv_vfnmadd_vf_f32m2_tu(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmadd_vv_f32m4_tu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmadd_vv_f32m4_tu
// CHECK-RV64-SAME: (<vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmadd.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmadd.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfnmadd_vv_f32m4_tu(vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) { vfloat32m4_t test_vfnmadd_vv_f32m4_tu(vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfnmadd_vv_f32m4_tu(vd, vs1, vs2, vl); return __riscv_vfnmadd_vv_f32m4_tu(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmadd_vf_f32m4_tu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmadd_vf_f32m4_tu
// CHECK-RV64-SAME: (<vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmadd.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmadd.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfnmadd_vf_f32m4_tu(vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) { vfloat32m4_t test_vfnmadd_vf_f32m4_tu(vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfnmadd_vf_f32m4_tu(vd, rs1, vs2, vl); return __riscv_vfnmadd_vf_f32m4_tu(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmadd_vv_f32m8_tu // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmadd_vv_f32m8_tu
// CHECK-RV64-SAME: (<vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmadd.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmadd.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfnmadd_vv_f32m8_tu(vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) { vfloat32m8_t test_vfnmadd_vv_f32m8_tu(vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfnmadd_vv_f32m8_tu(vd, vs1, vs2, vl); return __riscv_vfnmadd_vv_f32m8_tu(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmadd_vf_f32m8_tu // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmadd_vf_f32m8_tu
// CHECK-RV64-SAME: (<vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmadd.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmadd.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfnmadd_vf_f32m8_tu(vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) { vfloat32m8_t test_vfnmadd_vf_f32m8_tu(vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfnmadd_vf_f32m8_tu(vd, rs1, vs2, vl); return __riscv_vfnmadd_vf_f32m8_tu(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmadd_vv_f64m1_tu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmadd_vv_f64m1_tu
// CHECK-RV64-SAME: (<vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmadd.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmadd.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfnmadd_vv_f64m1_tu(vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) { vfloat64m1_t test_vfnmadd_vv_f64m1_tu(vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfnmadd_vv_f64m1_tu(vd, vs1, vs2, vl); return __riscv_vfnmadd_vv_f64m1_tu(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmadd_vf_f64m1_tu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmadd_vf_f64m1_tu
// CHECK-RV64-SAME: (<vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmadd.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmadd.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfnmadd_vf_f64m1_tu(vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) { vfloat64m1_t test_vfnmadd_vf_f64m1_tu(vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfnmadd_vf_f64m1_tu(vd, rs1, vs2, vl); return __riscv_vfnmadd_vf_f64m1_tu(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmadd_vv_f64m2_tu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmadd_vv_f64m2_tu
// CHECK-RV64-SAME: (<vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmadd.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmadd.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfnmadd_vv_f64m2_tu(vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) { vfloat64m2_t test_vfnmadd_vv_f64m2_tu(vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfnmadd_vv_f64m2_tu(vd, vs1, vs2, vl); return __riscv_vfnmadd_vv_f64m2_tu(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmadd_vf_f64m2_tu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmadd_vf_f64m2_tu
// CHECK-RV64-SAME: (<vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmadd.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmadd.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfnmadd_vf_f64m2_tu(vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) { vfloat64m2_t test_vfnmadd_vf_f64m2_tu(vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfnmadd_vf_f64m2_tu(vd, rs1, vs2, vl); return __riscv_vfnmadd_vf_f64m2_tu(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmadd_vv_f64m4_tu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmadd_vv_f64m4_tu
// CHECK-RV64-SAME: (<vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmadd.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmadd.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfnmadd_vv_f64m4_tu(vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) { vfloat64m4_t test_vfnmadd_vv_f64m4_tu(vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfnmadd_vv_f64m4_tu(vd, vs1, vs2, vl); return __riscv_vfnmadd_vv_f64m4_tu(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmadd_vf_f64m4_tu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmadd_vf_f64m4_tu
// CHECK-RV64-SAME: (<vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmadd.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmadd.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfnmadd_vf_f64m4_tu(vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) { vfloat64m4_t test_vfnmadd_vf_f64m4_tu(vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfnmadd_vf_f64m4_tu(vd, rs1, vs2, vl); return __riscv_vfnmadd_vf_f64m4_tu(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmadd_vv_f64m8_tu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmadd_vv_f64m8_tu
// CHECK-RV64-SAME: (<vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmadd.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmadd.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfnmadd_vv_f64m8_tu(vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) { vfloat64m8_t test_vfnmadd_vv_f64m8_tu(vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfnmadd_vv_f64m8_tu(vd, vs1, vs2, vl); return __riscv_vfnmadd_vv_f64m8_tu(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmadd_vf_f64m8_tu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmadd_vf_f64m8_tu
// CHECK-RV64-SAME: (<vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmadd.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmadd.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfnmadd_vf_f64m8_tu(vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) { vfloat64m8_t test_vfnmadd_vf_f64m8_tu(vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfnmadd_vf_f64m8_tu(vd, rs1, vs2, vl); return __riscv_vfnmadd_vf_f64m8_tu(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmadd_vv_f16mf4_tum // CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmadd_vv_f16mf4_tum
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmadd.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmadd.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
// //
vfloat16mf4_t test_vfnmadd_vv_f16mf4_tum(vbool64_t mask, vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) { vfloat16mf4_t test_vfnmadd_vv_f16mf4_tum(vbool64_t mask, vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfnmadd_vv_f16mf4_tum(mask, vd, vs1, vs2, vl); return __riscv_vfnmadd_vv_f16mf4_tum(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmadd_vf_f16mf4_tum // CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmadd_vf_f16mf4_tum
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmadd.mask.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmadd.mask.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
// //
vfloat16mf4_t test_vfnmadd_vf_f16mf4_tum(vbool64_t mask, vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) { vfloat16mf4_t test_vfnmadd_vf_f16mf4_tum(vbool64_t mask, vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfnmadd_vf_f16mf4_tum(mask, vd, rs1, vs2, vl); return __riscv_vfnmadd_vf_f16mf4_tum(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmadd_vv_f16mf2_tum // CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmadd_vv_f16mf2_tum
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmadd.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmadd.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
// //
vfloat16mf2_t test_vfnmadd_vv_f16mf2_tum(vbool32_t mask, vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) { vfloat16mf2_t test_vfnmadd_vv_f16mf2_tum(vbool32_t mask, vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfnmadd_vv_f16mf2_tum(mask, vd, vs1, vs2, vl); return __riscv_vfnmadd_vv_f16mf2_tum(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmadd_vf_f16mf2_tum // CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmadd_vf_f16mf2_tum
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmadd.mask.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmadd.mask.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
// //
vfloat16mf2_t test_vfnmadd_vf_f16mf2_tum(vbool32_t mask, vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) { vfloat16mf2_t test_vfnmadd_vf_f16mf2_tum(vbool32_t mask, vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfnmadd_vf_f16mf2_tum(mask, vd, rs1, vs2, vl); return __riscv_vfnmadd_vf_f16mf2_tum(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmadd_vv_f16m1_tum // CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmadd_vv_f16m1_tum
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmadd.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmadd.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
// //
vfloat16m1_t test_vfnmadd_vv_f16m1_tum(vbool16_t mask, vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) { vfloat16m1_t test_vfnmadd_vv_f16m1_tum(vbool16_t mask, vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfnmadd_vv_f16m1_tum(mask, vd, vs1, vs2, vl); return __riscv_vfnmadd_vv_f16m1_tum(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmadd_vf_f16m1_tum // CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmadd_vf_f16m1_tum
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmadd.mask.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmadd.mask.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
// //
vfloat16m1_t test_vfnmadd_vf_f16m1_tum(vbool16_t mask, vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) { vfloat16m1_t test_vfnmadd_vf_f16m1_tum(vbool16_t mask, vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfnmadd_vf_f16m1_tum(mask, vd, rs1, vs2, vl); return __riscv_vfnmadd_vf_f16m1_tum(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmadd_vv_f16m2_tum // CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmadd_vv_f16m2_tum
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmadd.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmadd.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
// //
vfloat16m2_t test_vfnmadd_vv_f16m2_tum(vbool8_t mask, vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) { vfloat16m2_t test_vfnmadd_vv_f16m2_tum(vbool8_t mask, vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfnmadd_vv_f16m2_tum(mask, vd, vs1, vs2, vl); return __riscv_vfnmadd_vv_f16m2_tum(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmadd_vf_f16m2_tum // CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmadd_vf_f16m2_tum
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmadd.mask.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmadd.mask.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
// //
vfloat16m2_t test_vfnmadd_vf_f16m2_tum(vbool8_t mask, vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) { vfloat16m2_t test_vfnmadd_vf_f16m2_tum(vbool8_t mask, vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfnmadd_vf_f16m2_tum(mask, vd, rs1, vs2, vl); return __riscv_vfnmadd_vf_f16m2_tum(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmadd_vv_f16m4_tum // CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmadd_vv_f16m4_tum
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmadd.mask.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmadd.mask.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
// //
vfloat16m4_t test_vfnmadd_vv_f16m4_tum(vbool4_t mask, vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) { vfloat16m4_t test_vfnmadd_vv_f16m4_tum(vbool4_t mask, vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfnmadd_vv_f16m4_tum(mask, vd, vs1, vs2, vl); return __riscv_vfnmadd_vv_f16m4_tum(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmadd_vf_f16m4_tum // CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmadd_vf_f16m4_tum
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmadd.mask.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmadd.mask.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
// //
vfloat16m4_t test_vfnmadd_vf_f16m4_tum(vbool4_t mask, vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) { vfloat16m4_t test_vfnmadd_vf_f16m4_tum(vbool4_t mask, vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfnmadd_vf_f16m4_tum(mask, vd, rs1, vs2, vl); return __riscv_vfnmadd_vf_f16m4_tum(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmadd_vv_f16m8_tum // CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmadd_vv_f16m8_tum
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmadd.mask.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmadd.mask.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
// //
vfloat16m8_t test_vfnmadd_vv_f16m8_tum(vbool2_t mask, vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) { vfloat16m8_t test_vfnmadd_vv_f16m8_tum(vbool2_t mask, vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfnmadd_vv_f16m8_tum(mask, vd, vs1, vs2, vl); return __riscv_vfnmadd_vv_f16m8_tum(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmadd_vf_f16m8_tum // CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmadd_vf_f16m8_tum
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmadd.mask.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmadd.mask.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
// //
vfloat16m8_t test_vfnmadd_vf_f16m8_tum(vbool2_t mask, vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) { vfloat16m8_t test_vfnmadd_vf_f16m8_tum(vbool2_t mask, vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfnmadd_vf_f16m8_tum(mask, vd, rs1, vs2, vl); return __riscv_vfnmadd_vf_f16m8_tum(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmadd_vv_f32mf2_tum // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmadd_vv_f32mf2_tum
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmadd.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmadd.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfnmadd_vv_f32mf2_tum(vbool64_t mask, vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) { vfloat32mf2_t test_vfnmadd_vv_f32mf2_tum(vbool64_t mask, vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfnmadd_vv_f32mf2_tum(mask, vd, vs1, vs2, vl); return __riscv_vfnmadd_vv_f32mf2_tum(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmadd_vf_f32mf2_tum // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmadd_vf_f32mf2_tum
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmadd.mask.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmadd.mask.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfnmadd_vf_f32mf2_tum(vbool64_t mask, vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) { vfloat32mf2_t test_vfnmadd_vf_f32mf2_tum(vbool64_t mask, vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfnmadd_vf_f32mf2_tum(mask, vd, rs1, vs2, vl); return __riscv_vfnmadd_vf_f32mf2_tum(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmadd_vv_f32m1_tum // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmadd_vv_f32m1_tum
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmadd.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmadd.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfnmadd_vv_f32m1_tum(vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) { vfloat32m1_t test_vfnmadd_vv_f32m1_tum(vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfnmadd_vv_f32m1_tum(mask, vd, vs1, vs2, vl); return __riscv_vfnmadd_vv_f32m1_tum(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmadd_vf_f32m1_tum // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmadd_vf_f32m1_tum
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmadd.mask.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmadd.mask.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfnmadd_vf_f32m1_tum(vbool32_t mask, vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) { vfloat32m1_t test_vfnmadd_vf_f32m1_tum(vbool32_t mask, vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfnmadd_vf_f32m1_tum(mask, vd, rs1, vs2, vl); return __riscv_vfnmadd_vf_f32m1_tum(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmadd_vv_f32m2_tum // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmadd_vv_f32m2_tum
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmadd.mask.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmadd.mask.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfnmadd_vv_f32m2_tum(vbool16_t mask, vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) { vfloat32m2_t test_vfnmadd_vv_f32m2_tum(vbool16_t mask, vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfnmadd_vv_f32m2_tum(mask, vd, vs1, vs2, vl); return __riscv_vfnmadd_vv_f32m2_tum(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmadd_vf_f32m2_tum // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmadd_vf_f32m2_tum
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmadd.mask.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmadd.mask.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfnmadd_vf_f32m2_tum(vbool16_t mask, vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) { vfloat32m2_t test_vfnmadd_vf_f32m2_tum(vbool16_t mask, vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfnmadd_vf_f32m2_tum(mask, vd, rs1, vs2, vl); return __riscv_vfnmadd_vf_f32m2_tum(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmadd_vv_f32m4_tum // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmadd_vv_f32m4_tum
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmadd.mask.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmadd.mask.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfnmadd_vv_f32m4_tum(vbool8_t mask, vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) { vfloat32m4_t test_vfnmadd_vv_f32m4_tum(vbool8_t mask, vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfnmadd_vv_f32m4_tum(mask, vd, vs1, vs2, vl); return __riscv_vfnmadd_vv_f32m4_tum(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmadd_vf_f32m4_tum // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmadd_vf_f32m4_tum
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmadd.mask.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmadd.mask.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfnmadd_vf_f32m4_tum(vbool8_t mask, vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) { vfloat32m4_t test_vfnmadd_vf_f32m4_tum(vbool8_t mask, vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfnmadd_vf_f32m4_tum(mask, vd, rs1, vs2, vl); return __riscv_vfnmadd_vf_f32m4_tum(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmadd_vv_f32m8_tum // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmadd_vv_f32m8_tum
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmadd.mask.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmadd.mask.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfnmadd_vv_f32m8_tum(vbool4_t mask, vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) { vfloat32m8_t test_vfnmadd_vv_f32m8_tum(vbool4_t mask, vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfnmadd_vv_f32m8_tum(mask, vd, vs1, vs2, vl); return __riscv_vfnmadd_vv_f32m8_tum(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmadd_vf_f32m8_tum // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmadd_vf_f32m8_tum
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmadd.mask.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmadd.mask.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfnmadd_vf_f32m8_tum(vbool4_t mask, vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) { vfloat32m8_t test_vfnmadd_vf_f32m8_tum(vbool4_t mask, vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfnmadd_vf_f32m8_tum(mask, vd, rs1, vs2, vl); return __riscv_vfnmadd_vf_f32m8_tum(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmadd_vv_f64m1_tum // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmadd_vv_f64m1_tum
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmadd.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmadd.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfnmadd_vv_f64m1_tum(vbool64_t mask, vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) { vfloat64m1_t test_vfnmadd_vv_f64m1_tum(vbool64_t mask, vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfnmadd_vv_f64m1_tum(mask, vd, vs1, vs2, vl); return __riscv_vfnmadd_vv_f64m1_tum(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmadd_vf_f64m1_tum // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmadd_vf_f64m1_tum
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmadd.mask.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmadd.mask.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfnmadd_vf_f64m1_tum(vbool64_t mask, vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) { vfloat64m1_t test_vfnmadd_vf_f64m1_tum(vbool64_t mask, vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfnmadd_vf_f64m1_tum(mask, vd, rs1, vs2, vl); return __riscv_vfnmadd_vf_f64m1_tum(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmadd_vv_f64m2_tum // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmadd_vv_f64m2_tum
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmadd.mask.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmadd.mask.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfnmadd_vv_f64m2_tum(vbool32_t mask, vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) { vfloat64m2_t test_vfnmadd_vv_f64m2_tum(vbool32_t mask, vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfnmadd_vv_f64m2_tum(mask, vd, vs1, vs2, vl); return __riscv_vfnmadd_vv_f64m2_tum(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmadd_vf_f64m2_tum // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmadd_vf_f64m2_tum
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmadd.mask.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmadd.mask.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfnmadd_vf_f64m2_tum(vbool32_t mask, vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) { vfloat64m2_t test_vfnmadd_vf_f64m2_tum(vbool32_t mask, vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfnmadd_vf_f64m2_tum(mask, vd, rs1, vs2, vl); return __riscv_vfnmadd_vf_f64m2_tum(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmadd_vv_f64m4_tum // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmadd_vv_f64m4_tum
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmadd.mask.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmadd.mask.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfnmadd_vv_f64m4_tum(vbool16_t mask, vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) { vfloat64m4_t test_vfnmadd_vv_f64m4_tum(vbool16_t mask, vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfnmadd_vv_f64m4_tum(mask, vd, vs1, vs2, vl); return __riscv_vfnmadd_vv_f64m4_tum(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmadd_vf_f64m4_tum // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmadd_vf_f64m4_tum
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmadd.mask.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmadd.mask.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfnmadd_vf_f64m4_tum(vbool16_t mask, vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) { vfloat64m4_t test_vfnmadd_vf_f64m4_tum(vbool16_t mask, vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfnmadd_vf_f64m4_tum(mask, vd, rs1, vs2, vl); return __riscv_vfnmadd_vf_f64m4_tum(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmadd_vv_f64m8_tum // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmadd_vv_f64m8_tum
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmadd.mask.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmadd.mask.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfnmadd_vv_f64m8_tum(vbool8_t mask, vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) { vfloat64m8_t test_vfnmadd_vv_f64m8_tum(vbool8_t mask, vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfnmadd_vv_f64m8_tum(mask, vd, vs1, vs2, vl); return __riscv_vfnmadd_vv_f64m8_tum(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmadd_vf_f64m8_tum // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmadd_vf_f64m8_tum
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmadd.mask.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmadd.mask.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfnmadd_vf_f64m8_tum(vbool8_t mask, vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) { vfloat64m8_t test_vfnmadd_vf_f64m8_tum(vbool8_t mask, vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfnmadd_vf_f64m8_tum(mask, vd, rs1, vs2, vl); return __riscv_vfnmadd_vf_f64m8_tum(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmadd_vv_f16mf4_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmadd_vv_f16mf4_tumu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmadd.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmadd.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
// //
vfloat16mf4_t test_vfnmadd_vv_f16mf4_tumu(vbool64_t mask, vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) { vfloat16mf4_t test_vfnmadd_vv_f16mf4_tumu(vbool64_t mask, vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfnmadd_vv_f16mf4_tumu(mask, vd, vs1, vs2, vl); return __riscv_vfnmadd_vv_f16mf4_tumu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmadd_vf_f16mf4_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmadd_vf_f16mf4_tumu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmadd.mask.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmadd.mask.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
// //
vfloat16mf4_t test_vfnmadd_vf_f16mf4_tumu(vbool64_t mask, vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) { vfloat16mf4_t test_vfnmadd_vf_f16mf4_tumu(vbool64_t mask, vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfnmadd_vf_f16mf4_tumu(mask, vd, rs1, vs2, vl); return __riscv_vfnmadd_vf_f16mf4_tumu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmadd_vv_f16mf2_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmadd_vv_f16mf2_tumu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmadd.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmadd.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
// //
vfloat16mf2_t test_vfnmadd_vv_f16mf2_tumu(vbool32_t mask, vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) { vfloat16mf2_t test_vfnmadd_vv_f16mf2_tumu(vbool32_t mask, vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfnmadd_vv_f16mf2_tumu(mask, vd, vs1, vs2, vl); return __riscv_vfnmadd_vv_f16mf2_tumu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmadd_vf_f16mf2_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmadd_vf_f16mf2_tumu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmadd.mask.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmadd.mask.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
// //
vfloat16mf2_t test_vfnmadd_vf_f16mf2_tumu(vbool32_t mask, vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) { vfloat16mf2_t test_vfnmadd_vf_f16mf2_tumu(vbool32_t mask, vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfnmadd_vf_f16mf2_tumu(mask, vd, rs1, vs2, vl); return __riscv_vfnmadd_vf_f16mf2_tumu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmadd_vv_f16m1_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmadd_vv_f16m1_tumu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmadd.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmadd.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
// //
vfloat16m1_t test_vfnmadd_vv_f16m1_tumu(vbool16_t mask, vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) { vfloat16m1_t test_vfnmadd_vv_f16m1_tumu(vbool16_t mask, vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfnmadd_vv_f16m1_tumu(mask, vd, vs1, vs2, vl); return __riscv_vfnmadd_vv_f16m1_tumu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmadd_vf_f16m1_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmadd_vf_f16m1_tumu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmadd.mask.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmadd.mask.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
// //
vfloat16m1_t test_vfnmadd_vf_f16m1_tumu(vbool16_t mask, vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) { vfloat16m1_t test_vfnmadd_vf_f16m1_tumu(vbool16_t mask, vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfnmadd_vf_f16m1_tumu(mask, vd, rs1, vs2, vl); return __riscv_vfnmadd_vf_f16m1_tumu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmadd_vv_f16m2_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmadd_vv_f16m2_tumu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmadd.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmadd.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
// //
vfloat16m2_t test_vfnmadd_vv_f16m2_tumu(vbool8_t mask, vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) { vfloat16m2_t test_vfnmadd_vv_f16m2_tumu(vbool8_t mask, vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfnmadd_vv_f16m2_tumu(mask, vd, vs1, vs2, vl); return __riscv_vfnmadd_vv_f16m2_tumu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmadd_vf_f16m2_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmadd_vf_f16m2_tumu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmadd.mask.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmadd.mask.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
// //
vfloat16m2_t test_vfnmadd_vf_f16m2_tumu(vbool8_t mask, vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) { vfloat16m2_t test_vfnmadd_vf_f16m2_tumu(vbool8_t mask, vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfnmadd_vf_f16m2_tumu(mask, vd, rs1, vs2, vl); return __riscv_vfnmadd_vf_f16m2_tumu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmadd_vv_f16m4_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmadd_vv_f16m4_tumu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmadd.mask.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmadd.mask.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
// //
vfloat16m4_t test_vfnmadd_vv_f16m4_tumu(vbool4_t mask, vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) { vfloat16m4_t test_vfnmadd_vv_f16m4_tumu(vbool4_t mask, vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfnmadd_vv_f16m4_tumu(mask, vd, vs1, vs2, vl); return __riscv_vfnmadd_vv_f16m4_tumu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmadd_vf_f16m4_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmadd_vf_f16m4_tumu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmadd.mask.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmadd.mask.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
// //
vfloat16m4_t test_vfnmadd_vf_f16m4_tumu(vbool4_t mask, vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) { vfloat16m4_t test_vfnmadd_vf_f16m4_tumu(vbool4_t mask, vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfnmadd_vf_f16m4_tumu(mask, vd, rs1, vs2, vl); return __riscv_vfnmadd_vf_f16m4_tumu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmadd_vv_f16m8_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmadd_vv_f16m8_tumu
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmadd.mask.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmadd.mask.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
// //
vfloat16m8_t test_vfnmadd_vv_f16m8_tumu(vbool2_t mask, vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) { vfloat16m8_t test_vfnmadd_vv_f16m8_tumu(vbool2_t mask, vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfnmadd_vv_f16m8_tumu(mask, vd, vs1, vs2, vl); return __riscv_vfnmadd_vv_f16m8_tumu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmadd_vf_f16m8_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmadd_vf_f16m8_tumu
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmadd.mask.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmadd.mask.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
// //
vfloat16m8_t test_vfnmadd_vf_f16m8_tumu(vbool2_t mask, vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) { vfloat16m8_t test_vfnmadd_vf_f16m8_tumu(vbool2_t mask, vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfnmadd_vf_f16m8_tumu(mask, vd, rs1, vs2, vl); return __riscv_vfnmadd_vf_f16m8_tumu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmadd_vv_f32mf2_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmadd_vv_f32mf2_tumu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmadd.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmadd.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfnmadd_vv_f32mf2_tumu(vbool64_t mask, vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) { vfloat32mf2_t test_vfnmadd_vv_f32mf2_tumu(vbool64_t mask, vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfnmadd_vv_f32mf2_tumu(mask, vd, vs1, vs2, vl); return __riscv_vfnmadd_vv_f32mf2_tumu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmadd_vf_f32mf2_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmadd_vf_f32mf2_tumu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmadd.mask.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmadd.mask.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfnmadd_vf_f32mf2_tumu(vbool64_t mask, vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) { vfloat32mf2_t test_vfnmadd_vf_f32mf2_tumu(vbool64_t mask, vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfnmadd_vf_f32mf2_tumu(mask, vd, rs1, vs2, vl); return __riscv_vfnmadd_vf_f32mf2_tumu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmadd_vv_f32m1_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmadd_vv_f32m1_tumu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmadd.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmadd.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfnmadd_vv_f32m1_tumu(vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) { vfloat32m1_t test_vfnmadd_vv_f32m1_tumu(vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfnmadd_vv_f32m1_tumu(mask, vd, vs1, vs2, vl); return __riscv_vfnmadd_vv_f32m1_tumu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmadd_vf_f32m1_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmadd_vf_f32m1_tumu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmadd.mask.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmadd.mask.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfnmadd_vf_f32m1_tumu(vbool32_t mask, vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) { vfloat32m1_t test_vfnmadd_vf_f32m1_tumu(vbool32_t mask, vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfnmadd_vf_f32m1_tumu(mask, vd, rs1, vs2, vl); return __riscv_vfnmadd_vf_f32m1_tumu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmadd_vv_f32m2_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmadd_vv_f32m2_tumu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmadd.mask.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmadd.mask.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfnmadd_vv_f32m2_tumu(vbool16_t mask, vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) { vfloat32m2_t test_vfnmadd_vv_f32m2_tumu(vbool16_t mask, vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfnmadd_vv_f32m2_tumu(mask, vd, vs1, vs2, vl); return __riscv_vfnmadd_vv_f32m2_tumu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmadd_vf_f32m2_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmadd_vf_f32m2_tumu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmadd.mask.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmadd.mask.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfnmadd_vf_f32m2_tumu(vbool16_t mask, vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) { vfloat32m2_t test_vfnmadd_vf_f32m2_tumu(vbool16_t mask, vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfnmadd_vf_f32m2_tumu(mask, vd, rs1, vs2, vl); return __riscv_vfnmadd_vf_f32m2_tumu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmadd_vv_f32m4_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmadd_vv_f32m4_tumu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmadd.mask.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmadd.mask.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfnmadd_vv_f32m4_tumu(vbool8_t mask, vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) { vfloat32m4_t test_vfnmadd_vv_f32m4_tumu(vbool8_t mask, vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfnmadd_vv_f32m4_tumu(mask, vd, vs1, vs2, vl); return __riscv_vfnmadd_vv_f32m4_tumu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmadd_vf_f32m4_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmadd_vf_f32m4_tumu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmadd.mask.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmadd.mask.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfnmadd_vf_f32m4_tumu(vbool8_t mask, vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) { vfloat32m4_t test_vfnmadd_vf_f32m4_tumu(vbool8_t mask, vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfnmadd_vf_f32m4_tumu(mask, vd, rs1, vs2, vl); return __riscv_vfnmadd_vf_f32m4_tumu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmadd_vv_f32m8_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmadd_vv_f32m8_tumu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmadd.mask.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmadd.mask.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfnmadd_vv_f32m8_tumu(vbool4_t mask, vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) { vfloat32m8_t test_vfnmadd_vv_f32m8_tumu(vbool4_t mask, vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfnmadd_vv_f32m8_tumu(mask, vd, vs1, vs2, vl); return __riscv_vfnmadd_vv_f32m8_tumu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmadd_vf_f32m8_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmadd_vf_f32m8_tumu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmadd.mask.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmadd.mask.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfnmadd_vf_f32m8_tumu(vbool4_t mask, vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) { vfloat32m8_t test_vfnmadd_vf_f32m8_tumu(vbool4_t mask, vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfnmadd_vf_f32m8_tumu(mask, vd, rs1, vs2, vl); return __riscv_vfnmadd_vf_f32m8_tumu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmadd_vv_f64m1_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmadd_vv_f64m1_tumu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmadd.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmadd.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfnmadd_vv_f64m1_tumu(vbool64_t mask, vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) { vfloat64m1_t test_vfnmadd_vv_f64m1_tumu(vbool64_t mask, vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfnmadd_vv_f64m1_tumu(mask, vd, vs1, vs2, vl); return __riscv_vfnmadd_vv_f64m1_tumu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmadd_vf_f64m1_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmadd_vf_f64m1_tumu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmadd.mask.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmadd.mask.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfnmadd_vf_f64m1_tumu(vbool64_t mask, vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) { vfloat64m1_t test_vfnmadd_vf_f64m1_tumu(vbool64_t mask, vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfnmadd_vf_f64m1_tumu(mask, vd, rs1, vs2, vl); return __riscv_vfnmadd_vf_f64m1_tumu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmadd_vv_f64m2_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmadd_vv_f64m2_tumu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmadd.mask.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmadd.mask.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfnmadd_vv_f64m2_tumu(vbool32_t mask, vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) { vfloat64m2_t test_vfnmadd_vv_f64m2_tumu(vbool32_t mask, vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfnmadd_vv_f64m2_tumu(mask, vd, vs1, vs2, vl); return __riscv_vfnmadd_vv_f64m2_tumu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmadd_vf_f64m2_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmadd_vf_f64m2_tumu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmadd.mask.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmadd.mask.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfnmadd_vf_f64m2_tumu(vbool32_t mask, vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) { vfloat64m2_t test_vfnmadd_vf_f64m2_tumu(vbool32_t mask, vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfnmadd_vf_f64m2_tumu(mask, vd, rs1, vs2, vl); return __riscv_vfnmadd_vf_f64m2_tumu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmadd_vv_f64m4_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmadd_vv_f64m4_tumu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmadd.mask.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmadd.mask.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfnmadd_vv_f64m4_tumu(vbool16_t mask, vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) { vfloat64m4_t test_vfnmadd_vv_f64m4_tumu(vbool16_t mask, vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfnmadd_vv_f64m4_tumu(mask, vd, vs1, vs2, vl); return __riscv_vfnmadd_vv_f64m4_tumu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmadd_vf_f64m4_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmadd_vf_f64m4_tumu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmadd.mask.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmadd.mask.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfnmadd_vf_f64m4_tumu(vbool16_t mask, vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) { vfloat64m4_t test_vfnmadd_vf_f64m4_tumu(vbool16_t mask, vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfnmadd_vf_f64m4_tumu(mask, vd, rs1, vs2, vl); return __riscv_vfnmadd_vf_f64m4_tumu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmadd_vv_f64m8_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmadd_vv_f64m8_tumu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmadd.mask.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmadd.mask.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfnmadd_vv_f64m8_tumu(vbool8_t mask, vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) { vfloat64m8_t test_vfnmadd_vv_f64m8_tumu(vbool8_t mask, vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfnmadd_vv_f64m8_tumu(mask, vd, vs1, vs2, vl); return __riscv_vfnmadd_vv_f64m8_tumu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmadd_vf_f64m8_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmadd_vf_f64m8_tumu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmadd.mask.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmadd.mask.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfnmadd_vf_f64m8_tumu(vbool8_t mask, vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) { vfloat64m8_t test_vfnmadd_vf_f64m8_tumu(vbool8_t mask, vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfnmadd_vf_f64m8_tumu(mask, vd, rs1, vs2, vl); return __riscv_vfnmadd_vf_f64m8_tumu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmadd_vv_f16mf4_mu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmadd_vv_f16mf4_mu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmadd.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmadd.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
// //
vfloat16mf4_t test_vfnmadd_vv_f16mf4_mu(vbool64_t mask, vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) { vfloat16mf4_t test_vfnmadd_vv_f16mf4_mu(vbool64_t mask, vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfnmadd_vv_f16mf4_mu(mask, vd, vs1, vs2, vl); return __riscv_vfnmadd_vv_f16mf4_mu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmadd_vf_f16mf4_mu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmadd_vf_f16mf4_mu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmadd.mask.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmadd.mask.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
// //
vfloat16mf4_t test_vfnmadd_vf_f16mf4_mu(vbool64_t mask, vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) { vfloat16mf4_t test_vfnmadd_vf_f16mf4_mu(vbool64_t mask, vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfnmadd_vf_f16mf4_mu(mask, vd, rs1, vs2, vl); return __riscv_vfnmadd_vf_f16mf4_mu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmadd_vv_f16mf2_mu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmadd_vv_f16mf2_mu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmadd.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmadd.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
// //
vfloat16mf2_t test_vfnmadd_vv_f16mf2_mu(vbool32_t mask, vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) { vfloat16mf2_t test_vfnmadd_vv_f16mf2_mu(vbool32_t mask, vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfnmadd_vv_f16mf2_mu(mask, vd, vs1, vs2, vl); return __riscv_vfnmadd_vv_f16mf2_mu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmadd_vf_f16mf2_mu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmadd_vf_f16mf2_mu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmadd.mask.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmadd.mask.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
// //
vfloat16mf2_t test_vfnmadd_vf_f16mf2_mu(vbool32_t mask, vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) { vfloat16mf2_t test_vfnmadd_vf_f16mf2_mu(vbool32_t mask, vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfnmadd_vf_f16mf2_mu(mask, vd, rs1, vs2, vl); return __riscv_vfnmadd_vf_f16mf2_mu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmadd_vv_f16m1_mu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmadd_vv_f16m1_mu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmadd.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmadd.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
// //
vfloat16m1_t test_vfnmadd_vv_f16m1_mu(vbool16_t mask, vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) { vfloat16m1_t test_vfnmadd_vv_f16m1_mu(vbool16_t mask, vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfnmadd_vv_f16m1_mu(mask, vd, vs1, vs2, vl); return __riscv_vfnmadd_vv_f16m1_mu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmadd_vf_f16m1_mu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmadd_vf_f16m1_mu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmadd.mask.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmadd.mask.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
// //
vfloat16m1_t test_vfnmadd_vf_f16m1_mu(vbool16_t mask, vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) { vfloat16m1_t test_vfnmadd_vf_f16m1_mu(vbool16_t mask, vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfnmadd_vf_f16m1_mu(mask, vd, rs1, vs2, vl); return __riscv_vfnmadd_vf_f16m1_mu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmadd_vv_f16m2_mu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmadd_vv_f16m2_mu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmadd.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmadd.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
// //
vfloat16m2_t test_vfnmadd_vv_f16m2_mu(vbool8_t mask, vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) { vfloat16m2_t test_vfnmadd_vv_f16m2_mu(vbool8_t mask, vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfnmadd_vv_f16m2_mu(mask, vd, vs1, vs2, vl); return __riscv_vfnmadd_vv_f16m2_mu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmadd_vf_f16m2_mu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmadd_vf_f16m2_mu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmadd.mask.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmadd.mask.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
// //
vfloat16m2_t test_vfnmadd_vf_f16m2_mu(vbool8_t mask, vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) { vfloat16m2_t test_vfnmadd_vf_f16m2_mu(vbool8_t mask, vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfnmadd_vf_f16m2_mu(mask, vd, rs1, vs2, vl); return __riscv_vfnmadd_vf_f16m2_mu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmadd_vv_f16m4_mu // CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmadd_vv_f16m4_mu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmadd.mask.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmadd.mask.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
// //
vfloat16m4_t test_vfnmadd_vv_f16m4_mu(vbool4_t mask, vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) { vfloat16m4_t test_vfnmadd_vv_f16m4_mu(vbool4_t mask, vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfnmadd_vv_f16m4_mu(mask, vd, vs1, vs2, vl); return __riscv_vfnmadd_vv_f16m4_mu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmadd_vf_f16m4_mu // CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmadd_vf_f16m4_mu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmadd.mask.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmadd.mask.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
// //
vfloat16m4_t test_vfnmadd_vf_f16m4_mu(vbool4_t mask, vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) { vfloat16m4_t test_vfnmadd_vf_f16m4_mu(vbool4_t mask, vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfnmadd_vf_f16m4_mu(mask, vd, rs1, vs2, vl); return __riscv_vfnmadd_vf_f16m4_mu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmadd_vv_f16m8_mu // CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmadd_vv_f16m8_mu
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmadd.mask.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmadd.mask.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
// //
vfloat16m8_t test_vfnmadd_vv_f16m8_mu(vbool2_t mask, vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) { vfloat16m8_t test_vfnmadd_vv_f16m8_mu(vbool2_t mask, vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfnmadd_vv_f16m8_mu(mask, vd, vs1, vs2, vl); return __riscv_vfnmadd_vv_f16m8_mu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmadd_vf_f16m8_mu // CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmadd_vf_f16m8_mu
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmadd.mask.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmadd.mask.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
// //
vfloat16m8_t test_vfnmadd_vf_f16m8_mu(vbool2_t mask, vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) { vfloat16m8_t test_vfnmadd_vf_f16m8_mu(vbool2_t mask, vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfnmadd_vf_f16m8_mu(mask, vd, rs1, vs2, vl); return __riscv_vfnmadd_vf_f16m8_mu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmadd_vv_f32mf2_mu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmadd_vv_f32mf2_mu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmadd.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmadd.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfnmadd_vv_f32mf2_mu(vbool64_t mask, vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) { vfloat32mf2_t test_vfnmadd_vv_f32mf2_mu(vbool64_t mask, vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfnmadd_vv_f32mf2_mu(mask, vd, vs1, vs2, vl); return __riscv_vfnmadd_vv_f32mf2_mu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmadd_vf_f32mf2_mu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmadd_vf_f32mf2_mu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmadd.mask.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmadd.mask.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfnmadd_vf_f32mf2_mu(vbool64_t mask, vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) { vfloat32mf2_t test_vfnmadd_vf_f32mf2_mu(vbool64_t mask, vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfnmadd_vf_f32mf2_mu(mask, vd, rs1, vs2, vl); return __riscv_vfnmadd_vf_f32mf2_mu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmadd_vv_f32m1_mu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmadd_vv_f32m1_mu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmadd.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmadd.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfnmadd_vv_f32m1_mu(vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) { vfloat32m1_t test_vfnmadd_vv_f32m1_mu(vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfnmadd_vv_f32m1_mu(mask, vd, vs1, vs2, vl); return __riscv_vfnmadd_vv_f32m1_mu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmadd_vf_f32m1_mu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmadd_vf_f32m1_mu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmadd.mask.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmadd.mask.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfnmadd_vf_f32m1_mu(vbool32_t mask, vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) { vfloat32m1_t test_vfnmadd_vf_f32m1_mu(vbool32_t mask, vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfnmadd_vf_f32m1_mu(mask, vd, rs1, vs2, vl); return __riscv_vfnmadd_vf_f32m1_mu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmadd_vv_f32m2_mu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmadd_vv_f32m2_mu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmadd.mask.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmadd.mask.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfnmadd_vv_f32m2_mu(vbool16_t mask, vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) { vfloat32m2_t test_vfnmadd_vv_f32m2_mu(vbool16_t mask, vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfnmadd_vv_f32m2_mu(mask, vd, vs1, vs2, vl); return __riscv_vfnmadd_vv_f32m2_mu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmadd_vf_f32m2_mu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmadd_vf_f32m2_mu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmadd.mask.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmadd.mask.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfnmadd_vf_f32m2_mu(vbool16_t mask, vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) { vfloat32m2_t test_vfnmadd_vf_f32m2_mu(vbool16_t mask, vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfnmadd_vf_f32m2_mu(mask, vd, rs1, vs2, vl); return __riscv_vfnmadd_vf_f32m2_mu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmadd_vv_f32m4_mu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmadd_vv_f32m4_mu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmadd.mask.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmadd.mask.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfnmadd_vv_f32m4_mu(vbool8_t mask, vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) { vfloat32m4_t test_vfnmadd_vv_f32m4_mu(vbool8_t mask, vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfnmadd_vv_f32m4_mu(mask, vd, vs1, vs2, vl); return __riscv_vfnmadd_vv_f32m4_mu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmadd_vf_f32m4_mu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmadd_vf_f32m4_mu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmadd.mask.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmadd.mask.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfnmadd_vf_f32m4_mu(vbool8_t mask, vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) { vfloat32m4_t test_vfnmadd_vf_f32m4_mu(vbool8_t mask, vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfnmadd_vf_f32m4_mu(mask, vd, rs1, vs2, vl); return __riscv_vfnmadd_vf_f32m4_mu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmadd_vv_f32m8_mu // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmadd_vv_f32m8_mu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmadd.mask.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmadd.mask.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfnmadd_vv_f32m8_mu(vbool4_t mask, vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) { vfloat32m8_t test_vfnmadd_vv_f32m8_mu(vbool4_t mask, vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfnmadd_vv_f32m8_mu(mask, vd, vs1, vs2, vl); return __riscv_vfnmadd_vv_f32m8_mu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmadd_vf_f32m8_mu // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmadd_vf_f32m8_mu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmadd.mask.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmadd.mask.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfnmadd_vf_f32m8_mu(vbool4_t mask, vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) { vfloat32m8_t test_vfnmadd_vf_f32m8_mu(vbool4_t mask, vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfnmadd_vf_f32m8_mu(mask, vd, rs1, vs2, vl); return __riscv_vfnmadd_vf_f32m8_mu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmadd_vv_f64m1_mu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmadd_vv_f64m1_mu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmadd.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmadd.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfnmadd_vv_f64m1_mu(vbool64_t mask, vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) { vfloat64m1_t test_vfnmadd_vv_f64m1_mu(vbool64_t mask, vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfnmadd_vv_f64m1_mu(mask, vd, vs1, vs2, vl); return __riscv_vfnmadd_vv_f64m1_mu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmadd_vf_f64m1_mu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmadd_vf_f64m1_mu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmadd.mask.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmadd.mask.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfnmadd_vf_f64m1_mu(vbool64_t mask, vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) { vfloat64m1_t test_vfnmadd_vf_f64m1_mu(vbool64_t mask, vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfnmadd_vf_f64m1_mu(mask, vd, rs1, vs2, vl); return __riscv_vfnmadd_vf_f64m1_mu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmadd_vv_f64m2_mu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmadd_vv_f64m2_mu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmadd.mask.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmadd.mask.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfnmadd_vv_f64m2_mu(vbool32_t mask, vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) { vfloat64m2_t test_vfnmadd_vv_f64m2_mu(vbool32_t mask, vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfnmadd_vv_f64m2_mu(mask, vd, vs1, vs2, vl); return __riscv_vfnmadd_vv_f64m2_mu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmadd_vf_f64m2_mu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmadd_vf_f64m2_mu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmadd.mask.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmadd.mask.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfnmadd_vf_f64m2_mu(vbool32_t mask, vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) { vfloat64m2_t test_vfnmadd_vf_f64m2_mu(vbool32_t mask, vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfnmadd_vf_f64m2_mu(mask, vd, rs1, vs2, vl); return __riscv_vfnmadd_vf_f64m2_mu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmadd_vv_f64m4_mu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmadd_vv_f64m4_mu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmadd.mask.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmadd.mask.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfnmadd_vv_f64m4_mu(vbool16_t mask, vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) { vfloat64m4_t test_vfnmadd_vv_f64m4_mu(vbool16_t mask, vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfnmadd_vv_f64m4_mu(mask, vd, vs1, vs2, vl); return __riscv_vfnmadd_vv_f64m4_mu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmadd_vf_f64m4_mu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmadd_vf_f64m4_mu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmadd.mask.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmadd.mask.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfnmadd_vf_f64m4_mu(vbool16_t mask, vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) { vfloat64m4_t test_vfnmadd_vf_f64m4_mu(vbool16_t mask, vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfnmadd_vf_f64m4_mu(mask, vd, rs1, vs2, vl); return __riscv_vfnmadd_vf_f64m4_mu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmadd_vv_f64m8_mu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmadd_vv_f64m8_mu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmadd.mask.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmadd.mask.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfnmadd_vv_f64m8_mu(vbool8_t mask, vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) { vfloat64m8_t test_vfnmadd_vv_f64m8_mu(vbool8_t mask, vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfnmadd_vv_f64m8_mu(mask, vd, vs1, vs2, vl); return __riscv_vfnmadd_vv_f64m8_mu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmadd_vf_f64m8_mu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmadd_vf_f64m8_mu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmadd.mask.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmadd.mask.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfnmadd_vf_f64m8_mu(vbool8_t mask, vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) { vfloat64m8_t test_vfnmadd_vf_f64m8_mu(vbool8_t mask, vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfnmadd_vf_f64m8_mu(mask, vd, rs1, vs2, vl); return __riscv_vfnmadd_vf_f64m8_mu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmadd_vv_f16mf4_rm_tu
// CHECK-RV64-SAME: (<vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmadd.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
//
vfloat16mf4_t test_vfnmadd_vv_f16mf4_rm_tu(vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfnmadd_vv_f16mf4_rm_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmadd_vf_f16mf4_rm_tu
// CHECK-RV64-SAME: (<vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmadd.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
//
vfloat16mf4_t test_vfnmadd_vf_f16mf4_rm_tu(vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfnmadd_vf_f16mf4_rm_tu(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmadd_vv_f16mf2_rm_tu
// CHECK-RV64-SAME: (<vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmadd.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
//
vfloat16mf2_t test_vfnmadd_vv_f16mf2_rm_tu(vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfnmadd_vv_f16mf2_rm_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmadd_vf_f16mf2_rm_tu
// CHECK-RV64-SAME: (<vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmadd.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
//
vfloat16mf2_t test_vfnmadd_vf_f16mf2_rm_tu(vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfnmadd_vf_f16mf2_rm_tu(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmadd_vv_f16m1_rm_tu
// CHECK-RV64-SAME: (<vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmadd.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfnmadd_vv_f16m1_rm_tu(vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfnmadd_vv_f16m1_rm_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmadd_vf_f16m1_rm_tu
// CHECK-RV64-SAME: (<vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmadd.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfnmadd_vf_f16m1_rm_tu(vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfnmadd_vf_f16m1_rm_tu(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmadd_vv_f16m2_rm_tu
// CHECK-RV64-SAME: (<vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmadd.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
//
vfloat16m2_t test_vfnmadd_vv_f16m2_rm_tu(vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfnmadd_vv_f16m2_rm_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmadd_vf_f16m2_rm_tu
// CHECK-RV64-SAME: (<vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmadd.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
//
vfloat16m2_t test_vfnmadd_vf_f16m2_rm_tu(vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfnmadd_vf_f16m2_rm_tu(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmadd_vv_f16m4_rm_tu
// CHECK-RV64-SAME: (<vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmadd.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
//
vfloat16m4_t test_vfnmadd_vv_f16m4_rm_tu(vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfnmadd_vv_f16m4_rm_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmadd_vf_f16m4_rm_tu
// CHECK-RV64-SAME: (<vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmadd.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
//
vfloat16m4_t test_vfnmadd_vf_f16m4_rm_tu(vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfnmadd_vf_f16m4_rm_tu(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmadd_vv_f16m8_rm_tu
// CHECK-RV64-SAME: (<vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmadd.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
//
vfloat16m8_t test_vfnmadd_vv_f16m8_rm_tu(vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfnmadd_vv_f16m8_rm_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmadd_vf_f16m8_rm_tu
// CHECK-RV64-SAME: (<vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmadd.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
//
vfloat16m8_t test_vfnmadd_vf_f16m8_rm_tu(vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfnmadd_vf_f16m8_rm_tu(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmadd_vv_f32mf2_rm_tu
// CHECK-RV64-SAME: (<vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmadd.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
//
vfloat32mf2_t test_vfnmadd_vv_f32mf2_rm_tu(vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfnmadd_vv_f32mf2_rm_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmadd_vf_f32mf2_rm_tu
// CHECK-RV64-SAME: (<vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmadd.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
//
vfloat32mf2_t test_vfnmadd_vf_f32mf2_rm_tu(vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfnmadd_vf_f32mf2_rm_tu(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmadd_vv_f32m1_rm_tu
// CHECK-RV64-SAME: (<vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmadd.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfnmadd_vv_f32m1_rm_tu(vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfnmadd_vv_f32m1_rm_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmadd_vf_f32m1_rm_tu
// CHECK-RV64-SAME: (<vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmadd.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfnmadd_vf_f32m1_rm_tu(vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfnmadd_vf_f32m1_rm_tu(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmadd_vv_f32m2_rm_tu
// CHECK-RV64-SAME: (<vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmadd.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
//
vfloat32m2_t test_vfnmadd_vv_f32m2_rm_tu(vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfnmadd_vv_f32m2_rm_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmadd_vf_f32m2_rm_tu
// CHECK-RV64-SAME: (<vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmadd.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
//
vfloat32m2_t test_vfnmadd_vf_f32m2_rm_tu(vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfnmadd_vf_f32m2_rm_tu(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmadd_vv_f32m4_rm_tu
// CHECK-RV64-SAME: (<vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmadd.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
//
vfloat32m4_t test_vfnmadd_vv_f32m4_rm_tu(vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfnmadd_vv_f32m4_rm_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmadd_vf_f32m4_rm_tu
// CHECK-RV64-SAME: (<vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmadd.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
//
vfloat32m4_t test_vfnmadd_vf_f32m4_rm_tu(vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfnmadd_vf_f32m4_rm_tu(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmadd_vv_f32m8_rm_tu
// CHECK-RV64-SAME: (<vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmadd.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
//
vfloat32m8_t test_vfnmadd_vv_f32m8_rm_tu(vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfnmadd_vv_f32m8_rm_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmadd_vf_f32m8_rm_tu
// CHECK-RV64-SAME: (<vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmadd.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
//
vfloat32m8_t test_vfnmadd_vf_f32m8_rm_tu(vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfnmadd_vf_f32m8_rm_tu(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmadd_vv_f64m1_rm_tu
// CHECK-RV64-SAME: (<vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmadd.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfnmadd_vv_f64m1_rm_tu(vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfnmadd_vv_f64m1_rm_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmadd_vf_f64m1_rm_tu
// CHECK-RV64-SAME: (<vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmadd.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfnmadd_vf_f64m1_rm_tu(vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfnmadd_vf_f64m1_rm_tu(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmadd_vv_f64m2_rm_tu
// CHECK-RV64-SAME: (<vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmadd.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
//
vfloat64m2_t test_vfnmadd_vv_f64m2_rm_tu(vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfnmadd_vv_f64m2_rm_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmadd_vf_f64m2_rm_tu
// CHECK-RV64-SAME: (<vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmadd.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
//
vfloat64m2_t test_vfnmadd_vf_f64m2_rm_tu(vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfnmadd_vf_f64m2_rm_tu(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmadd_vv_f64m4_rm_tu
// CHECK-RV64-SAME: (<vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmadd.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
//
vfloat64m4_t test_vfnmadd_vv_f64m4_rm_tu(vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfnmadd_vv_f64m4_rm_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmadd_vf_f64m4_rm_tu
// CHECK-RV64-SAME: (<vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmadd.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
//
vfloat64m4_t test_vfnmadd_vf_f64m4_rm_tu(vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfnmadd_vf_f64m4_rm_tu(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmadd_vv_f64m8_rm_tu
// CHECK-RV64-SAME: (<vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmadd.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
//
vfloat64m8_t test_vfnmadd_vv_f64m8_rm_tu(vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfnmadd_vv_f64m8_rm_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmadd_vf_f64m8_rm_tu
// CHECK-RV64-SAME: (<vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmadd.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
//
vfloat64m8_t test_vfnmadd_vf_f64m8_rm_tu(vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfnmadd_vf_f64m8_rm_tu(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmadd_vv_f16mf4_rm_tum
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmadd.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
//
vfloat16mf4_t test_vfnmadd_vv_f16mf4_rm_tum(vbool64_t mask, vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfnmadd_vv_f16mf4_rm_tum(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmadd_vf_f16mf4_rm_tum
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmadd.mask.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
//
vfloat16mf4_t test_vfnmadd_vf_f16mf4_rm_tum(vbool64_t mask, vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfnmadd_vf_f16mf4_rm_tum(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmadd_vv_f16mf2_rm_tum
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmadd.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
//
vfloat16mf2_t test_vfnmadd_vv_f16mf2_rm_tum(vbool32_t mask, vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfnmadd_vv_f16mf2_rm_tum(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmadd_vf_f16mf2_rm_tum
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmadd.mask.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
//
vfloat16mf2_t test_vfnmadd_vf_f16mf2_rm_tum(vbool32_t mask, vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfnmadd_vf_f16mf2_rm_tum(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmadd_vv_f16m1_rm_tum
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmadd.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfnmadd_vv_f16m1_rm_tum(vbool16_t mask, vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfnmadd_vv_f16m1_rm_tum(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmadd_vf_f16m1_rm_tum
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmadd.mask.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfnmadd_vf_f16m1_rm_tum(vbool16_t mask, vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfnmadd_vf_f16m1_rm_tum(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmadd_vv_f16m2_rm_tum
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmadd.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
//
vfloat16m2_t test_vfnmadd_vv_f16m2_rm_tum(vbool8_t mask, vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfnmadd_vv_f16m2_rm_tum(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmadd_vf_f16m2_rm_tum
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmadd.mask.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
//
vfloat16m2_t test_vfnmadd_vf_f16m2_rm_tum(vbool8_t mask, vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfnmadd_vf_f16m2_rm_tum(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmadd_vv_f16m4_rm_tum
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmadd.mask.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
//
vfloat16m4_t test_vfnmadd_vv_f16m4_rm_tum(vbool4_t mask, vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfnmadd_vv_f16m4_rm_tum(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmadd_vf_f16m4_rm_tum
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmadd.mask.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
//
vfloat16m4_t test_vfnmadd_vf_f16m4_rm_tum(vbool4_t mask, vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfnmadd_vf_f16m4_rm_tum(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmadd_vv_f16m8_rm_tum
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmadd.mask.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
//
vfloat16m8_t test_vfnmadd_vv_f16m8_rm_tum(vbool2_t mask, vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfnmadd_vv_f16m8_rm_tum(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmadd_vf_f16m8_rm_tum
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmadd.mask.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
//
vfloat16m8_t test_vfnmadd_vf_f16m8_rm_tum(vbool2_t mask, vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfnmadd_vf_f16m8_rm_tum(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmadd_vv_f32mf2_rm_tum
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmadd.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
//
vfloat32mf2_t test_vfnmadd_vv_f32mf2_rm_tum(vbool64_t mask, vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfnmadd_vv_f32mf2_rm_tum(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmadd_vf_f32mf2_rm_tum
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmadd.mask.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
//
vfloat32mf2_t test_vfnmadd_vf_f32mf2_rm_tum(vbool64_t mask, vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfnmadd_vf_f32mf2_rm_tum(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmadd_vv_f32m1_rm_tum
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmadd.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfnmadd_vv_f32m1_rm_tum(vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfnmadd_vv_f32m1_rm_tum(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmadd_vf_f32m1_rm_tum
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmadd.mask.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfnmadd_vf_f32m1_rm_tum(vbool32_t mask, vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfnmadd_vf_f32m1_rm_tum(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmadd_vv_f32m2_rm_tum
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmadd.mask.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
//
vfloat32m2_t test_vfnmadd_vv_f32m2_rm_tum(vbool16_t mask, vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfnmadd_vv_f32m2_rm_tum(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmadd_vf_f32m2_rm_tum
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmadd.mask.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
//
vfloat32m2_t test_vfnmadd_vf_f32m2_rm_tum(vbool16_t mask, vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfnmadd_vf_f32m2_rm_tum(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmadd_vv_f32m4_rm_tum
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmadd.mask.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
//
vfloat32m4_t test_vfnmadd_vv_f32m4_rm_tum(vbool8_t mask, vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfnmadd_vv_f32m4_rm_tum(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmadd_vf_f32m4_rm_tum
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmadd.mask.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
//
vfloat32m4_t test_vfnmadd_vf_f32m4_rm_tum(vbool8_t mask, vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfnmadd_vf_f32m4_rm_tum(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmadd_vv_f32m8_rm_tum
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmadd.mask.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
//
vfloat32m8_t test_vfnmadd_vv_f32m8_rm_tum(vbool4_t mask, vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfnmadd_vv_f32m8_rm_tum(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmadd_vf_f32m8_rm_tum
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmadd.mask.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
//
vfloat32m8_t test_vfnmadd_vf_f32m8_rm_tum(vbool4_t mask, vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfnmadd_vf_f32m8_rm_tum(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmadd_vv_f64m1_rm_tum
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmadd.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfnmadd_vv_f64m1_rm_tum(vbool64_t mask, vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfnmadd_vv_f64m1_rm_tum(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmadd_vf_f64m1_rm_tum
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmadd.mask.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfnmadd_vf_f64m1_rm_tum(vbool64_t mask, vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfnmadd_vf_f64m1_rm_tum(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmadd_vv_f64m2_rm_tum
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmadd.mask.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
//
vfloat64m2_t test_vfnmadd_vv_f64m2_rm_tum(vbool32_t mask, vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfnmadd_vv_f64m2_rm_tum(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmadd_vf_f64m2_rm_tum
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmadd.mask.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
//
vfloat64m2_t test_vfnmadd_vf_f64m2_rm_tum(vbool32_t mask, vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfnmadd_vf_f64m2_rm_tum(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmadd_vv_f64m4_rm_tum
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmadd.mask.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
//
vfloat64m4_t test_vfnmadd_vv_f64m4_rm_tum(vbool16_t mask, vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfnmadd_vv_f64m4_rm_tum(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmadd_vf_f64m4_rm_tum
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmadd.mask.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
//
vfloat64m4_t test_vfnmadd_vf_f64m4_rm_tum(vbool16_t mask, vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfnmadd_vf_f64m4_rm_tum(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmadd_vv_f64m8_rm_tum
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmadd.mask.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
//
vfloat64m8_t test_vfnmadd_vv_f64m8_rm_tum(vbool8_t mask, vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfnmadd_vv_f64m8_rm_tum(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmadd_vf_f64m8_rm_tum
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmadd.mask.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
//
vfloat64m8_t test_vfnmadd_vf_f64m8_rm_tum(vbool8_t mask, vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfnmadd_vf_f64m8_rm_tum(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmadd_vv_f16mf4_rm_tumu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmadd.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
//
vfloat16mf4_t test_vfnmadd_vv_f16mf4_rm_tumu(vbool64_t mask, vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfnmadd_vv_f16mf4_rm_tumu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmadd_vf_f16mf4_rm_tumu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmadd.mask.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
//
vfloat16mf4_t test_vfnmadd_vf_f16mf4_rm_tumu(vbool64_t mask, vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfnmadd_vf_f16mf4_rm_tumu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmadd_vv_f16mf2_rm_tumu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmadd.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
//
vfloat16mf2_t test_vfnmadd_vv_f16mf2_rm_tumu(vbool32_t mask, vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfnmadd_vv_f16mf2_rm_tumu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmadd_vf_f16mf2_rm_tumu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmadd.mask.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
//
vfloat16mf2_t test_vfnmadd_vf_f16mf2_rm_tumu(vbool32_t mask, vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfnmadd_vf_f16mf2_rm_tumu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmadd_vv_f16m1_rm_tumu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmadd.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfnmadd_vv_f16m1_rm_tumu(vbool16_t mask, vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfnmadd_vv_f16m1_rm_tumu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmadd_vf_f16m1_rm_tumu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmadd.mask.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfnmadd_vf_f16m1_rm_tumu(vbool16_t mask, vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfnmadd_vf_f16m1_rm_tumu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmadd_vv_f16m2_rm_tumu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmadd.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
//
vfloat16m2_t test_vfnmadd_vv_f16m2_rm_tumu(vbool8_t mask, vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfnmadd_vv_f16m2_rm_tumu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmadd_vf_f16m2_rm_tumu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmadd.mask.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
//
vfloat16m2_t test_vfnmadd_vf_f16m2_rm_tumu(vbool8_t mask, vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfnmadd_vf_f16m2_rm_tumu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmadd_vv_f16m4_rm_tumu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmadd.mask.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
//
vfloat16m4_t test_vfnmadd_vv_f16m4_rm_tumu(vbool4_t mask, vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfnmadd_vv_f16m4_rm_tumu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmadd_vf_f16m4_rm_tumu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmadd.mask.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
//
vfloat16m4_t test_vfnmadd_vf_f16m4_rm_tumu(vbool4_t mask, vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfnmadd_vf_f16m4_rm_tumu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmadd_vv_f16m8_rm_tumu
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmadd.mask.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
//
vfloat16m8_t test_vfnmadd_vv_f16m8_rm_tumu(vbool2_t mask, vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfnmadd_vv_f16m8_rm_tumu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmadd_vf_f16m8_rm_tumu
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmadd.mask.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
//
vfloat16m8_t test_vfnmadd_vf_f16m8_rm_tumu(vbool2_t mask, vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfnmadd_vf_f16m8_rm_tumu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmadd_vv_f32mf2_rm_tumu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmadd.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
//
vfloat32mf2_t test_vfnmadd_vv_f32mf2_rm_tumu(vbool64_t mask, vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfnmadd_vv_f32mf2_rm_tumu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmadd_vf_f32mf2_rm_tumu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmadd.mask.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
//
vfloat32mf2_t test_vfnmadd_vf_f32mf2_rm_tumu(vbool64_t mask, vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfnmadd_vf_f32mf2_rm_tumu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmadd_vv_f32m1_rm_tumu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmadd.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfnmadd_vv_f32m1_rm_tumu(vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfnmadd_vv_f32m1_rm_tumu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmadd_vf_f32m1_rm_tumu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmadd.mask.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfnmadd_vf_f32m1_rm_tumu(vbool32_t mask, vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfnmadd_vf_f32m1_rm_tumu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmadd_vv_f32m2_rm_tumu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmadd.mask.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
//
vfloat32m2_t test_vfnmadd_vv_f32m2_rm_tumu(vbool16_t mask, vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfnmadd_vv_f32m2_rm_tumu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmadd_vf_f32m2_rm_tumu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmadd.mask.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
//
vfloat32m2_t test_vfnmadd_vf_f32m2_rm_tumu(vbool16_t mask, vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfnmadd_vf_f32m2_rm_tumu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmadd_vv_f32m4_rm_tumu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmadd.mask.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
//
vfloat32m4_t test_vfnmadd_vv_f32m4_rm_tumu(vbool8_t mask, vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfnmadd_vv_f32m4_rm_tumu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmadd_vf_f32m4_rm_tumu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmadd.mask.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
//
vfloat32m4_t test_vfnmadd_vf_f32m4_rm_tumu(vbool8_t mask, vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfnmadd_vf_f32m4_rm_tumu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmadd_vv_f32m8_rm_tumu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmadd.mask.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
//
vfloat32m8_t test_vfnmadd_vv_f32m8_rm_tumu(vbool4_t mask, vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfnmadd_vv_f32m8_rm_tumu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmadd_vf_f32m8_rm_tumu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmadd.mask.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
//
vfloat32m8_t test_vfnmadd_vf_f32m8_rm_tumu(vbool4_t mask, vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfnmadd_vf_f32m8_rm_tumu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmadd_vv_f64m1_rm_tumu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmadd.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfnmadd_vv_f64m1_rm_tumu(vbool64_t mask, vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfnmadd_vv_f64m1_rm_tumu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmadd_vf_f64m1_rm_tumu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmadd.mask.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfnmadd_vf_f64m1_rm_tumu(vbool64_t mask, vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfnmadd_vf_f64m1_rm_tumu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmadd_vv_f64m2_rm_tumu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmadd.mask.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
//
vfloat64m2_t test_vfnmadd_vv_f64m2_rm_tumu(vbool32_t mask, vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfnmadd_vv_f64m2_rm_tumu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmadd_vf_f64m2_rm_tumu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmadd.mask.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
//
vfloat64m2_t test_vfnmadd_vf_f64m2_rm_tumu(vbool32_t mask, vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfnmadd_vf_f64m2_rm_tumu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmadd_vv_f64m4_rm_tumu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmadd.mask.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
//
vfloat64m4_t test_vfnmadd_vv_f64m4_rm_tumu(vbool16_t mask, vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfnmadd_vv_f64m4_rm_tumu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmadd_vf_f64m4_rm_tumu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmadd.mask.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
//
vfloat64m4_t test_vfnmadd_vf_f64m4_rm_tumu(vbool16_t mask, vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfnmadd_vf_f64m4_rm_tumu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmadd_vv_f64m8_rm_tumu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmadd.mask.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
//
vfloat64m8_t test_vfnmadd_vv_f64m8_rm_tumu(vbool8_t mask, vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfnmadd_vv_f64m8_rm_tumu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmadd_vf_f64m8_rm_tumu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmadd.mask.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
//
vfloat64m8_t test_vfnmadd_vf_f64m8_rm_tumu(vbool8_t mask, vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfnmadd_vf_f64m8_rm_tumu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmadd_vv_f16mf4_rm_mu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmadd.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
//
vfloat16mf4_t test_vfnmadd_vv_f16mf4_rm_mu(vbool64_t mask, vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfnmadd_vv_f16mf4_rm_mu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmadd_vf_f16mf4_rm_mu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmadd.mask.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
//
vfloat16mf4_t test_vfnmadd_vf_f16mf4_rm_mu(vbool64_t mask, vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfnmadd_vf_f16mf4_rm_mu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmadd_vv_f16mf2_rm_mu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmadd.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
//
vfloat16mf2_t test_vfnmadd_vv_f16mf2_rm_mu(vbool32_t mask, vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfnmadd_vv_f16mf2_rm_mu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmadd_vf_f16mf2_rm_mu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmadd.mask.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
//
vfloat16mf2_t test_vfnmadd_vf_f16mf2_rm_mu(vbool32_t mask, vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfnmadd_vf_f16mf2_rm_mu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmadd_vv_f16m1_rm_mu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmadd.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfnmadd_vv_f16m1_rm_mu(vbool16_t mask, vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfnmadd_vv_f16m1_rm_mu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmadd_vf_f16m1_rm_mu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmadd.mask.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfnmadd_vf_f16m1_rm_mu(vbool16_t mask, vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfnmadd_vf_f16m1_rm_mu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmadd_vv_f16m2_rm_mu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmadd.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
//
vfloat16m2_t test_vfnmadd_vv_f16m2_rm_mu(vbool8_t mask, vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfnmadd_vv_f16m2_rm_mu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmadd_vf_f16m2_rm_mu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmadd.mask.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
//
vfloat16m2_t test_vfnmadd_vf_f16m2_rm_mu(vbool8_t mask, vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfnmadd_vf_f16m2_rm_mu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmadd_vv_f16m4_rm_mu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmadd.mask.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
//
vfloat16m4_t test_vfnmadd_vv_f16m4_rm_mu(vbool4_t mask, vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfnmadd_vv_f16m4_rm_mu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmadd_vf_f16m4_rm_mu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmadd.mask.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
//
vfloat16m4_t test_vfnmadd_vf_f16m4_rm_mu(vbool4_t mask, vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfnmadd_vf_f16m4_rm_mu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmadd_vv_f16m8_rm_mu
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmadd.mask.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
//
vfloat16m8_t test_vfnmadd_vv_f16m8_rm_mu(vbool2_t mask, vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfnmadd_vv_f16m8_rm_mu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmadd_vf_f16m8_rm_mu
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmadd.mask.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
//
vfloat16m8_t test_vfnmadd_vf_f16m8_rm_mu(vbool2_t mask, vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfnmadd_vf_f16m8_rm_mu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmadd_vv_f32mf2_rm_mu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmadd.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
//
vfloat32mf2_t test_vfnmadd_vv_f32mf2_rm_mu(vbool64_t mask, vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfnmadd_vv_f32mf2_rm_mu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmadd_vf_f32mf2_rm_mu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmadd.mask.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
//
vfloat32mf2_t test_vfnmadd_vf_f32mf2_rm_mu(vbool64_t mask, vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfnmadd_vf_f32mf2_rm_mu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmadd_vv_f32m1_rm_mu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmadd.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfnmadd_vv_f32m1_rm_mu(vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfnmadd_vv_f32m1_rm_mu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmadd_vf_f32m1_rm_mu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmadd.mask.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfnmadd_vf_f32m1_rm_mu(vbool32_t mask, vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfnmadd_vf_f32m1_rm_mu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmadd_vv_f32m2_rm_mu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmadd.mask.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
//
vfloat32m2_t test_vfnmadd_vv_f32m2_rm_mu(vbool16_t mask, vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfnmadd_vv_f32m2_rm_mu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmadd_vf_f32m2_rm_mu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmadd.mask.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
//
vfloat32m2_t test_vfnmadd_vf_f32m2_rm_mu(vbool16_t mask, vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfnmadd_vf_f32m2_rm_mu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmadd_vv_f32m4_rm_mu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmadd.mask.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
//
vfloat32m4_t test_vfnmadd_vv_f32m4_rm_mu(vbool8_t mask, vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfnmadd_vv_f32m4_rm_mu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmadd_vf_f32m4_rm_mu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmadd.mask.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
//
vfloat32m4_t test_vfnmadd_vf_f32m4_rm_mu(vbool8_t mask, vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfnmadd_vf_f32m4_rm_mu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmadd_vv_f32m8_rm_mu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmadd.mask.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
//
vfloat32m8_t test_vfnmadd_vv_f32m8_rm_mu(vbool4_t mask, vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfnmadd_vv_f32m8_rm_mu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmadd_vf_f32m8_rm_mu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmadd.mask.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
//
vfloat32m8_t test_vfnmadd_vf_f32m8_rm_mu(vbool4_t mask, vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfnmadd_vf_f32m8_rm_mu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmadd_vv_f64m1_rm_mu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmadd.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfnmadd_vv_f64m1_rm_mu(vbool64_t mask, vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfnmadd_vv_f64m1_rm_mu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmadd_vf_f64m1_rm_mu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmadd.mask.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfnmadd_vf_f64m1_rm_mu(vbool64_t mask, vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfnmadd_vf_f64m1_rm_mu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmadd_vv_f64m2_rm_mu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmadd.mask.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
//
vfloat64m2_t test_vfnmadd_vv_f64m2_rm_mu(vbool32_t mask, vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfnmadd_vv_f64m2_rm_mu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmadd_vf_f64m2_rm_mu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmadd.mask.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
//
vfloat64m2_t test_vfnmadd_vf_f64m2_rm_mu(vbool32_t mask, vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfnmadd_vf_f64m2_rm_mu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmadd_vv_f64m4_rm_mu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmadd.mask.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
//
vfloat64m4_t test_vfnmadd_vv_f64m4_rm_mu(vbool16_t mask, vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfnmadd_vv_f64m4_rm_mu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmadd_vf_f64m4_rm_mu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmadd.mask.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
//
vfloat64m4_t test_vfnmadd_vf_f64m4_rm_mu(vbool16_t mask, vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfnmadd_vf_f64m4_rm_mu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmadd_vv_f64m8_rm_mu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmadd.mask.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
//
vfloat64m8_t test_vfnmadd_vv_f64m8_rm_mu(vbool8_t mask, vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfnmadd_vv_f64m8_rm_mu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmadd_vf_f64m8_rm_mu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmadd.mask.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
//
vfloat64m8_t test_vfnmadd_vf_f64m8_rm_mu(vbool8_t mask, vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfnmadd_vf_f64m8_rm_mu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}

clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmsac.c

// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target // REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh \ // RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh \
// RUN: -target-feature +experimental-zvfh -disable-O0-optnone \ // RUN: -target-feature +experimental-zvfh -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ // RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s // RUN: FileCheck --check-prefix=CHECK-RV64 %s
#include <riscv_vector.h> #include <riscv_vector.h>
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmsac_vv_f16mf4_tu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmsac_vv_f16mf4_tu
// CHECK-RV64-SAME: (<vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK-RV64-SAME: (<vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmsac.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmsac.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
// //
vfloat16mf4_t test_vfnmsac_vv_f16mf4_tu(vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) { vfloat16mf4_t test_vfnmsac_vv_f16mf4_tu(vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfnmsac_vv_f16mf4_tu(vd, vs1, vs2, vl); return __riscv_vfnmsac_vv_f16mf4_tu(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmsac_vf_f16mf4_tu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmsac_vf_f16mf4_tu
// CHECK-RV64-SAME: (<vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmsac.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmsac.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
// //
vfloat16mf4_t test_vfnmsac_vf_f16mf4_tu(vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) { vfloat16mf4_t test_vfnmsac_vf_f16mf4_tu(vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfnmsac_vf_f16mf4_tu(vd, rs1, vs2, vl); return __riscv_vfnmsac_vf_f16mf4_tu(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmsac_vv_f16mf2_tu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmsac_vv_f16mf2_tu
// CHECK-RV64-SAME: (<vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmsac.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmsac.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
// //
vfloat16mf2_t test_vfnmsac_vv_f16mf2_tu(vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) { vfloat16mf2_t test_vfnmsac_vv_f16mf2_tu(vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfnmsac_vv_f16mf2_tu(vd, vs1, vs2, vl); return __riscv_vfnmsac_vv_f16mf2_tu(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmsac_vf_f16mf2_tu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmsac_vf_f16mf2_tu
// CHECK-RV64-SAME: (<vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmsac.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmsac.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
// //
vfloat16mf2_t test_vfnmsac_vf_f16mf2_tu(vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) { vfloat16mf2_t test_vfnmsac_vf_f16mf2_tu(vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfnmsac_vf_f16mf2_tu(vd, rs1, vs2, vl); return __riscv_vfnmsac_vf_f16mf2_tu(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmsac_vv_f16m1_tu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmsac_vv_f16m1_tu
// CHECK-RV64-SAME: (<vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmsac.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmsac.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
// //
vfloat16m1_t test_vfnmsac_vv_f16m1_tu(vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) { vfloat16m1_t test_vfnmsac_vv_f16m1_tu(vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfnmsac_vv_f16m1_tu(vd, vs1, vs2, vl); return __riscv_vfnmsac_vv_f16m1_tu(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmsac_vf_f16m1_tu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmsac_vf_f16m1_tu
// CHECK-RV64-SAME: (<vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmsac.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmsac.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
// //
vfloat16m1_t test_vfnmsac_vf_f16m1_tu(vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) { vfloat16m1_t test_vfnmsac_vf_f16m1_tu(vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfnmsac_vf_f16m1_tu(vd, rs1, vs2, vl); return __riscv_vfnmsac_vf_f16m1_tu(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmsac_vv_f16m2_tu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmsac_vv_f16m2_tu
// CHECK-RV64-SAME: (<vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmsac.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmsac.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
// //
vfloat16m2_t test_vfnmsac_vv_f16m2_tu(vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) { vfloat16m2_t test_vfnmsac_vv_f16m2_tu(vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfnmsac_vv_f16m2_tu(vd, vs1, vs2, vl); return __riscv_vfnmsac_vv_f16m2_tu(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmsac_vf_f16m2_tu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmsac_vf_f16m2_tu
// CHECK-RV64-SAME: (<vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmsac.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmsac.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
// //
vfloat16m2_t test_vfnmsac_vf_f16m2_tu(vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) { vfloat16m2_t test_vfnmsac_vf_f16m2_tu(vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfnmsac_vf_f16m2_tu(vd, rs1, vs2, vl); return __riscv_vfnmsac_vf_f16m2_tu(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmsac_vv_f16m4_tu // CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmsac_vv_f16m4_tu
// CHECK-RV64-SAME: (<vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmsac.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmsac.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
// //
vfloat16m4_t test_vfnmsac_vv_f16m4_tu(vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) { vfloat16m4_t test_vfnmsac_vv_f16m4_tu(vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfnmsac_vv_f16m4_tu(vd, vs1, vs2, vl); return __riscv_vfnmsac_vv_f16m4_tu(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmsac_vf_f16m4_tu // CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmsac_vf_f16m4_tu
// CHECK-RV64-SAME: (<vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmsac.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmsac.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
// //
vfloat16m4_t test_vfnmsac_vf_f16m4_tu(vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) { vfloat16m4_t test_vfnmsac_vf_f16m4_tu(vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfnmsac_vf_f16m4_tu(vd, rs1, vs2, vl); return __riscv_vfnmsac_vf_f16m4_tu(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmsac_vv_f16m8_tu // CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmsac_vv_f16m8_tu
// CHECK-RV64-SAME: (<vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmsac.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmsac.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
// //
vfloat16m8_t test_vfnmsac_vv_f16m8_tu(vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) { vfloat16m8_t test_vfnmsac_vv_f16m8_tu(vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfnmsac_vv_f16m8_tu(vd, vs1, vs2, vl); return __riscv_vfnmsac_vv_f16m8_tu(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmsac_vf_f16m8_tu // CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmsac_vf_f16m8_tu
// CHECK-RV64-SAME: (<vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmsac.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmsac.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
// //
vfloat16m8_t test_vfnmsac_vf_f16m8_tu(vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) { vfloat16m8_t test_vfnmsac_vf_f16m8_tu(vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfnmsac_vf_f16m8_tu(vd, rs1, vs2, vl); return __riscv_vfnmsac_vf_f16m8_tu(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmsac_vv_f32mf2_tu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmsac_vv_f32mf2_tu
// CHECK-RV64-SAME: (<vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmsac.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmsac.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfnmsac_vv_f32mf2_tu(vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) { vfloat32mf2_t test_vfnmsac_vv_f32mf2_tu(vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfnmsac_vv_f32mf2_tu(vd, vs1, vs2, vl); return __riscv_vfnmsac_vv_f32mf2_tu(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmsac_vf_f32mf2_tu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmsac_vf_f32mf2_tu
// CHECK-RV64-SAME: (<vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmsac.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmsac.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfnmsac_vf_f32mf2_tu(vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) { vfloat32mf2_t test_vfnmsac_vf_f32mf2_tu(vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfnmsac_vf_f32mf2_tu(vd, rs1, vs2, vl); return __riscv_vfnmsac_vf_f32mf2_tu(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmsac_vv_f32m1_tu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmsac_vv_f32m1_tu
// CHECK-RV64-SAME: (<vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmsac.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmsac.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfnmsac_vv_f32m1_tu(vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) { vfloat32m1_t test_vfnmsac_vv_f32m1_tu(vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfnmsac_vv_f32m1_tu(vd, vs1, vs2, vl); return __riscv_vfnmsac_vv_f32m1_tu(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmsac_vf_f32m1_tu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmsac_vf_f32m1_tu
// CHECK-RV64-SAME: (<vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmsac.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmsac.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfnmsac_vf_f32m1_tu(vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) { vfloat32m1_t test_vfnmsac_vf_f32m1_tu(vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfnmsac_vf_f32m1_tu(vd, rs1, vs2, vl); return __riscv_vfnmsac_vf_f32m1_tu(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmsac_vv_f32m2_tu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmsac_vv_f32m2_tu
// CHECK-RV64-SAME: (<vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmsac.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmsac.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfnmsac_vv_f32m2_tu(vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) { vfloat32m2_t test_vfnmsac_vv_f32m2_tu(vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfnmsac_vv_f32m2_tu(vd, vs1, vs2, vl); return __riscv_vfnmsac_vv_f32m2_tu(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmsac_vf_f32m2_tu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmsac_vf_f32m2_tu
// CHECK-RV64-SAME: (<vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmsac.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmsac.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfnmsac_vf_f32m2_tu(vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) { vfloat32m2_t test_vfnmsac_vf_f32m2_tu(vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfnmsac_vf_f32m2_tu(vd, rs1, vs2, vl); return __riscv_vfnmsac_vf_f32m2_tu(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmsac_vv_f32m4_tu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmsac_vv_f32m4_tu
// CHECK-RV64-SAME: (<vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmsac.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmsac.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfnmsac_vv_f32m4_tu(vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) { vfloat32m4_t test_vfnmsac_vv_f32m4_tu(vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfnmsac_vv_f32m4_tu(vd, vs1, vs2, vl); return __riscv_vfnmsac_vv_f32m4_tu(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmsac_vf_f32m4_tu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmsac_vf_f32m4_tu
// CHECK-RV64-SAME: (<vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmsac.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmsac.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfnmsac_vf_f32m4_tu(vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) { vfloat32m4_t test_vfnmsac_vf_f32m4_tu(vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfnmsac_vf_f32m4_tu(vd, rs1, vs2, vl); return __riscv_vfnmsac_vf_f32m4_tu(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmsac_vv_f32m8_tu // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmsac_vv_f32m8_tu
// CHECK-RV64-SAME: (<vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmsac.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmsac.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfnmsac_vv_f32m8_tu(vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) { vfloat32m8_t test_vfnmsac_vv_f32m8_tu(vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfnmsac_vv_f32m8_tu(vd, vs1, vs2, vl); return __riscv_vfnmsac_vv_f32m8_tu(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmsac_vf_f32m8_tu // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmsac_vf_f32m8_tu
// CHECK-RV64-SAME: (<vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmsac.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmsac.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfnmsac_vf_f32m8_tu(vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) { vfloat32m8_t test_vfnmsac_vf_f32m8_tu(vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfnmsac_vf_f32m8_tu(vd, rs1, vs2, vl); return __riscv_vfnmsac_vf_f32m8_tu(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmsac_vv_f64m1_tu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmsac_vv_f64m1_tu
// CHECK-RV64-SAME: (<vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmsac.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmsac.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfnmsac_vv_f64m1_tu(vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) { vfloat64m1_t test_vfnmsac_vv_f64m1_tu(vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfnmsac_vv_f64m1_tu(vd, vs1, vs2, vl); return __riscv_vfnmsac_vv_f64m1_tu(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmsac_vf_f64m1_tu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmsac_vf_f64m1_tu
// CHECK-RV64-SAME: (<vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmsac.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmsac.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfnmsac_vf_f64m1_tu(vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) { vfloat64m1_t test_vfnmsac_vf_f64m1_tu(vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfnmsac_vf_f64m1_tu(vd, rs1, vs2, vl); return __riscv_vfnmsac_vf_f64m1_tu(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmsac_vv_f64m2_tu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmsac_vv_f64m2_tu
// CHECK-RV64-SAME: (<vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmsac.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmsac.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfnmsac_vv_f64m2_tu(vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) { vfloat64m2_t test_vfnmsac_vv_f64m2_tu(vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfnmsac_vv_f64m2_tu(vd, vs1, vs2, vl); return __riscv_vfnmsac_vv_f64m2_tu(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmsac_vf_f64m2_tu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmsac_vf_f64m2_tu
// CHECK-RV64-SAME: (<vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmsac.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmsac.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfnmsac_vf_f64m2_tu(vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) { vfloat64m2_t test_vfnmsac_vf_f64m2_tu(vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfnmsac_vf_f64m2_tu(vd, rs1, vs2, vl); return __riscv_vfnmsac_vf_f64m2_tu(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmsac_vv_f64m4_tu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmsac_vv_f64m4_tu
// CHECK-RV64-SAME: (<vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmsac.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmsac.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfnmsac_vv_f64m4_tu(vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) { vfloat64m4_t test_vfnmsac_vv_f64m4_tu(vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfnmsac_vv_f64m4_tu(vd, vs1, vs2, vl); return __riscv_vfnmsac_vv_f64m4_tu(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmsac_vf_f64m4_tu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmsac_vf_f64m4_tu
// CHECK-RV64-SAME: (<vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmsac.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmsac.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfnmsac_vf_f64m4_tu(vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) { vfloat64m4_t test_vfnmsac_vf_f64m4_tu(vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfnmsac_vf_f64m4_tu(vd, rs1, vs2, vl); return __riscv_vfnmsac_vf_f64m4_tu(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmsac_vv_f64m8_tu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmsac_vv_f64m8_tu
// CHECK-RV64-SAME: (<vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmsac.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmsac.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfnmsac_vv_f64m8_tu(vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) { vfloat64m8_t test_vfnmsac_vv_f64m8_tu(vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfnmsac_vv_f64m8_tu(vd, vs1, vs2, vl); return __riscv_vfnmsac_vv_f64m8_tu(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmsac_vf_f64m8_tu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmsac_vf_f64m8_tu
// CHECK-RV64-SAME: (<vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmsac.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmsac.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfnmsac_vf_f64m8_tu(vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) { vfloat64m8_t test_vfnmsac_vf_f64m8_tu(vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfnmsac_vf_f64m8_tu(vd, rs1, vs2, vl); return __riscv_vfnmsac_vf_f64m8_tu(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmsac_vv_f16mf4_tum // CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmsac_vv_f16mf4_tum
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmsac.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmsac.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
// //
vfloat16mf4_t test_vfnmsac_vv_f16mf4_tum(vbool64_t mask, vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) { vfloat16mf4_t test_vfnmsac_vv_f16mf4_tum(vbool64_t mask, vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfnmsac_vv_f16mf4_tum(mask, vd, vs1, vs2, vl); return __riscv_vfnmsac_vv_f16mf4_tum(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmsac_vf_f16mf4_tum // CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmsac_vf_f16mf4_tum
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmsac.mask.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmsac.mask.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
// //
vfloat16mf4_t test_vfnmsac_vf_f16mf4_tum(vbool64_t mask, vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) { vfloat16mf4_t test_vfnmsac_vf_f16mf4_tum(vbool64_t mask, vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfnmsac_vf_f16mf4_tum(mask, vd, rs1, vs2, vl); return __riscv_vfnmsac_vf_f16mf4_tum(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmsac_vv_f16mf2_tum // CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmsac_vv_f16mf2_tum
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmsac.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmsac.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
// //
vfloat16mf2_t test_vfnmsac_vv_f16mf2_tum(vbool32_t mask, vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) { vfloat16mf2_t test_vfnmsac_vv_f16mf2_tum(vbool32_t mask, vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfnmsac_vv_f16mf2_tum(mask, vd, vs1, vs2, vl); return __riscv_vfnmsac_vv_f16mf2_tum(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmsac_vf_f16mf2_tum // CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmsac_vf_f16mf2_tum
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmsac.mask.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmsac.mask.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
// //
vfloat16mf2_t test_vfnmsac_vf_f16mf2_tum(vbool32_t mask, vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) { vfloat16mf2_t test_vfnmsac_vf_f16mf2_tum(vbool32_t mask, vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfnmsac_vf_f16mf2_tum(mask, vd, rs1, vs2, vl); return __riscv_vfnmsac_vf_f16mf2_tum(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmsac_vv_f16m1_tum // CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmsac_vv_f16m1_tum
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmsac.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmsac.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
// //
vfloat16m1_t test_vfnmsac_vv_f16m1_tum(vbool16_t mask, vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) { vfloat16m1_t test_vfnmsac_vv_f16m1_tum(vbool16_t mask, vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfnmsac_vv_f16m1_tum(mask, vd, vs1, vs2, vl); return __riscv_vfnmsac_vv_f16m1_tum(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmsac_vf_f16m1_tum // CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmsac_vf_f16m1_tum
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmsac.mask.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmsac.mask.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
// //
vfloat16m1_t test_vfnmsac_vf_f16m1_tum(vbool16_t mask, vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) { vfloat16m1_t test_vfnmsac_vf_f16m1_tum(vbool16_t mask, vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfnmsac_vf_f16m1_tum(mask, vd, rs1, vs2, vl); return __riscv_vfnmsac_vf_f16m1_tum(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmsac_vv_f16m2_tum // CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmsac_vv_f16m2_tum
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmsac.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmsac.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
// //
vfloat16m2_t test_vfnmsac_vv_f16m2_tum(vbool8_t mask, vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) { vfloat16m2_t test_vfnmsac_vv_f16m2_tum(vbool8_t mask, vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfnmsac_vv_f16m2_tum(mask, vd, vs1, vs2, vl); return __riscv_vfnmsac_vv_f16m2_tum(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmsac_vf_f16m2_tum // CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmsac_vf_f16m2_tum
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmsac.mask.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmsac.mask.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
// //
vfloat16m2_t test_vfnmsac_vf_f16m2_tum(vbool8_t mask, vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) { vfloat16m2_t test_vfnmsac_vf_f16m2_tum(vbool8_t mask, vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfnmsac_vf_f16m2_tum(mask, vd, rs1, vs2, vl); return __riscv_vfnmsac_vf_f16m2_tum(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmsac_vv_f16m4_tum // CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmsac_vv_f16m4_tum
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmsac.mask.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmsac.mask.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
// //
vfloat16m4_t test_vfnmsac_vv_f16m4_tum(vbool4_t mask, vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) { vfloat16m4_t test_vfnmsac_vv_f16m4_tum(vbool4_t mask, vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfnmsac_vv_f16m4_tum(mask, vd, vs1, vs2, vl); return __riscv_vfnmsac_vv_f16m4_tum(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmsac_vf_f16m4_tum // CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmsac_vf_f16m4_tum
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmsac.mask.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmsac.mask.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
// //
vfloat16m4_t test_vfnmsac_vf_f16m4_tum(vbool4_t mask, vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) { vfloat16m4_t test_vfnmsac_vf_f16m4_tum(vbool4_t mask, vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfnmsac_vf_f16m4_tum(mask, vd, rs1, vs2, vl); return __riscv_vfnmsac_vf_f16m4_tum(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmsac_vv_f16m8_tum // CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmsac_vv_f16m8_tum
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmsac.mask.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmsac.mask.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
// //
vfloat16m8_t test_vfnmsac_vv_f16m8_tum(vbool2_t mask, vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) { vfloat16m8_t test_vfnmsac_vv_f16m8_tum(vbool2_t mask, vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfnmsac_vv_f16m8_tum(mask, vd, vs1, vs2, vl); return __riscv_vfnmsac_vv_f16m8_tum(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmsac_vf_f16m8_tum // CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmsac_vf_f16m8_tum
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmsac.mask.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmsac.mask.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
// //
vfloat16m8_t test_vfnmsac_vf_f16m8_tum(vbool2_t mask, vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) { vfloat16m8_t test_vfnmsac_vf_f16m8_tum(vbool2_t mask, vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfnmsac_vf_f16m8_tum(mask, vd, rs1, vs2, vl); return __riscv_vfnmsac_vf_f16m8_tum(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmsac_vv_f32mf2_tum // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmsac_vv_f32mf2_tum
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmsac.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmsac.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfnmsac_vv_f32mf2_tum(vbool64_t mask, vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) { vfloat32mf2_t test_vfnmsac_vv_f32mf2_tum(vbool64_t mask, vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfnmsac_vv_f32mf2_tum(mask, vd, vs1, vs2, vl); return __riscv_vfnmsac_vv_f32mf2_tum(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmsac_vf_f32mf2_tum // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmsac_vf_f32mf2_tum
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmsac.mask.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmsac.mask.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfnmsac_vf_f32mf2_tum(vbool64_t mask, vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) { vfloat32mf2_t test_vfnmsac_vf_f32mf2_tum(vbool64_t mask, vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfnmsac_vf_f32mf2_tum(mask, vd, rs1, vs2, vl); return __riscv_vfnmsac_vf_f32mf2_tum(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmsac_vv_f32m1_tum // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmsac_vv_f32m1_tum
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmsac.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmsac.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfnmsac_vv_f32m1_tum(vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) { vfloat32m1_t test_vfnmsac_vv_f32m1_tum(vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfnmsac_vv_f32m1_tum(mask, vd, vs1, vs2, vl); return __riscv_vfnmsac_vv_f32m1_tum(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmsac_vf_f32m1_tum // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmsac_vf_f32m1_tum
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmsac.mask.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmsac.mask.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfnmsac_vf_f32m1_tum(vbool32_t mask, vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) { vfloat32m1_t test_vfnmsac_vf_f32m1_tum(vbool32_t mask, vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfnmsac_vf_f32m1_tum(mask, vd, rs1, vs2, vl); return __riscv_vfnmsac_vf_f32m1_tum(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmsac_vv_f32m2_tum // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmsac_vv_f32m2_tum
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmsac.mask.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmsac.mask.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfnmsac_vv_f32m2_tum(vbool16_t mask, vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) { vfloat32m2_t test_vfnmsac_vv_f32m2_tum(vbool16_t mask, vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfnmsac_vv_f32m2_tum(mask, vd, vs1, vs2, vl); return __riscv_vfnmsac_vv_f32m2_tum(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmsac_vf_f32m2_tum // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmsac_vf_f32m2_tum
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmsac.mask.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmsac.mask.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfnmsac_vf_f32m2_tum(vbool16_t mask, vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) { vfloat32m2_t test_vfnmsac_vf_f32m2_tum(vbool16_t mask, vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfnmsac_vf_f32m2_tum(mask, vd, rs1, vs2, vl); return __riscv_vfnmsac_vf_f32m2_tum(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmsac_vv_f32m4_tum // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmsac_vv_f32m4_tum
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmsac.mask.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmsac.mask.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfnmsac_vv_f32m4_tum(vbool8_t mask, vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) { vfloat32m4_t test_vfnmsac_vv_f32m4_tum(vbool8_t mask, vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfnmsac_vv_f32m4_tum(mask, vd, vs1, vs2, vl); return __riscv_vfnmsac_vv_f32m4_tum(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmsac_vf_f32m4_tum // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmsac_vf_f32m4_tum
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmsac.mask.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmsac.mask.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfnmsac_vf_f32m4_tum(vbool8_t mask, vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) { vfloat32m4_t test_vfnmsac_vf_f32m4_tum(vbool8_t mask, vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfnmsac_vf_f32m4_tum(mask, vd, rs1, vs2, vl); return __riscv_vfnmsac_vf_f32m4_tum(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmsac_vv_f32m8_tum // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmsac_vv_f32m8_tum
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmsac.mask.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmsac.mask.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfnmsac_vv_f32m8_tum(vbool4_t mask, vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) { vfloat32m8_t test_vfnmsac_vv_f32m8_tum(vbool4_t mask, vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfnmsac_vv_f32m8_tum(mask, vd, vs1, vs2, vl); return __riscv_vfnmsac_vv_f32m8_tum(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmsac_vf_f32m8_tum // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmsac_vf_f32m8_tum
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmsac.mask.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmsac.mask.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfnmsac_vf_f32m8_tum(vbool4_t mask, vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) { vfloat32m8_t test_vfnmsac_vf_f32m8_tum(vbool4_t mask, vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfnmsac_vf_f32m8_tum(mask, vd, rs1, vs2, vl); return __riscv_vfnmsac_vf_f32m8_tum(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmsac_vv_f64m1_tum // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmsac_vv_f64m1_tum
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmsac.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmsac.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfnmsac_vv_f64m1_tum(vbool64_t mask, vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) { vfloat64m1_t test_vfnmsac_vv_f64m1_tum(vbool64_t mask, vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfnmsac_vv_f64m1_tum(mask, vd, vs1, vs2, vl); return __riscv_vfnmsac_vv_f64m1_tum(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmsac_vf_f64m1_tum // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmsac_vf_f64m1_tum
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmsac.mask.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmsac.mask.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfnmsac_vf_f64m1_tum(vbool64_t mask, vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) { vfloat64m1_t test_vfnmsac_vf_f64m1_tum(vbool64_t mask, vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfnmsac_vf_f64m1_tum(mask, vd, rs1, vs2, vl); return __riscv_vfnmsac_vf_f64m1_tum(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmsac_vv_f64m2_tum // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmsac_vv_f64m2_tum
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmsac.mask.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmsac.mask.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfnmsac_vv_f64m2_tum(vbool32_t mask, vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) { vfloat64m2_t test_vfnmsac_vv_f64m2_tum(vbool32_t mask, vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfnmsac_vv_f64m2_tum(mask, vd, vs1, vs2, vl); return __riscv_vfnmsac_vv_f64m2_tum(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmsac_vf_f64m2_tum // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmsac_vf_f64m2_tum
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmsac.mask.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmsac.mask.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfnmsac_vf_f64m2_tum(vbool32_t mask, vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) { vfloat64m2_t test_vfnmsac_vf_f64m2_tum(vbool32_t mask, vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfnmsac_vf_f64m2_tum(mask, vd, rs1, vs2, vl); return __riscv_vfnmsac_vf_f64m2_tum(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmsac_vv_f64m4_tum // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmsac_vv_f64m4_tum
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmsac.mask.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmsac.mask.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfnmsac_vv_f64m4_tum(vbool16_t mask, vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) { vfloat64m4_t test_vfnmsac_vv_f64m4_tum(vbool16_t mask, vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfnmsac_vv_f64m4_tum(mask, vd, vs1, vs2, vl); return __riscv_vfnmsac_vv_f64m4_tum(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmsac_vf_f64m4_tum // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmsac_vf_f64m4_tum
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmsac.mask.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmsac.mask.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfnmsac_vf_f64m4_tum(vbool16_t mask, vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) { vfloat64m4_t test_vfnmsac_vf_f64m4_tum(vbool16_t mask, vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfnmsac_vf_f64m4_tum(mask, vd, rs1, vs2, vl); return __riscv_vfnmsac_vf_f64m4_tum(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmsac_vv_f64m8_tum // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmsac_vv_f64m8_tum
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmsac.mask.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmsac.mask.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfnmsac_vv_f64m8_tum(vbool8_t mask, vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) { vfloat64m8_t test_vfnmsac_vv_f64m8_tum(vbool8_t mask, vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfnmsac_vv_f64m8_tum(mask, vd, vs1, vs2, vl); return __riscv_vfnmsac_vv_f64m8_tum(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmsac_vf_f64m8_tum // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmsac_vf_f64m8_tum
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmsac.mask.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmsac.mask.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfnmsac_vf_f64m8_tum(vbool8_t mask, vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) { vfloat64m8_t test_vfnmsac_vf_f64m8_tum(vbool8_t mask, vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfnmsac_vf_f64m8_tum(mask, vd, rs1, vs2, vl); return __riscv_vfnmsac_vf_f64m8_tum(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmsac_vv_f16mf4_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmsac_vv_f16mf4_tumu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmsac.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmsac.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
// //
vfloat16mf4_t test_vfnmsac_vv_f16mf4_tumu(vbool64_t mask, vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) { vfloat16mf4_t test_vfnmsac_vv_f16mf4_tumu(vbool64_t mask, vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfnmsac_vv_f16mf4_tumu(mask, vd, vs1, vs2, vl); return __riscv_vfnmsac_vv_f16mf4_tumu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmsac_vf_f16mf4_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmsac_vf_f16mf4_tumu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmsac.mask.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmsac.mask.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
// //
vfloat16mf4_t test_vfnmsac_vf_f16mf4_tumu(vbool64_t mask, vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) { vfloat16mf4_t test_vfnmsac_vf_f16mf4_tumu(vbool64_t mask, vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfnmsac_vf_f16mf4_tumu(mask, vd, rs1, vs2, vl); return __riscv_vfnmsac_vf_f16mf4_tumu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmsac_vv_f16mf2_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmsac_vv_f16mf2_tumu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmsac.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmsac.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
// //
vfloat16mf2_t test_vfnmsac_vv_f16mf2_tumu(vbool32_t mask, vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) { vfloat16mf2_t test_vfnmsac_vv_f16mf2_tumu(vbool32_t mask, vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfnmsac_vv_f16mf2_tumu(mask, vd, vs1, vs2, vl); return __riscv_vfnmsac_vv_f16mf2_tumu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmsac_vf_f16mf2_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmsac_vf_f16mf2_tumu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmsac.mask.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmsac.mask.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
// //
vfloat16mf2_t test_vfnmsac_vf_f16mf2_tumu(vbool32_t mask, vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) { vfloat16mf2_t test_vfnmsac_vf_f16mf2_tumu(vbool32_t mask, vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfnmsac_vf_f16mf2_tumu(mask, vd, rs1, vs2, vl); return __riscv_vfnmsac_vf_f16mf2_tumu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmsac_vv_f16m1_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmsac_vv_f16m1_tumu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmsac.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmsac.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
// //
vfloat16m1_t test_vfnmsac_vv_f16m1_tumu(vbool16_t mask, vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) { vfloat16m1_t test_vfnmsac_vv_f16m1_tumu(vbool16_t mask, vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfnmsac_vv_f16m1_tumu(mask, vd, vs1, vs2, vl); return __riscv_vfnmsac_vv_f16m1_tumu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmsac_vf_f16m1_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmsac_vf_f16m1_tumu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmsac.mask.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmsac.mask.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
// //
vfloat16m1_t test_vfnmsac_vf_f16m1_tumu(vbool16_t mask, vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) { vfloat16m1_t test_vfnmsac_vf_f16m1_tumu(vbool16_t mask, vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfnmsac_vf_f16m1_tumu(mask, vd, rs1, vs2, vl); return __riscv_vfnmsac_vf_f16m1_tumu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmsac_vv_f16m2_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmsac_vv_f16m2_tumu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmsac.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmsac.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
// //
vfloat16m2_t test_vfnmsac_vv_f16m2_tumu(vbool8_t mask, vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) { vfloat16m2_t test_vfnmsac_vv_f16m2_tumu(vbool8_t mask, vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfnmsac_vv_f16m2_tumu(mask, vd, vs1, vs2, vl); return __riscv_vfnmsac_vv_f16m2_tumu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmsac_vf_f16m2_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmsac_vf_f16m2_tumu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmsac.mask.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmsac.mask.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
// //
vfloat16m2_t test_vfnmsac_vf_f16m2_tumu(vbool8_t mask, vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) { vfloat16m2_t test_vfnmsac_vf_f16m2_tumu(vbool8_t mask, vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfnmsac_vf_f16m2_tumu(mask, vd, rs1, vs2, vl); return __riscv_vfnmsac_vf_f16m2_tumu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmsac_vv_f16m4_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmsac_vv_f16m4_tumu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmsac.mask.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmsac.mask.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
// //
vfloat16m4_t test_vfnmsac_vv_f16m4_tumu(vbool4_t mask, vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) { vfloat16m4_t test_vfnmsac_vv_f16m4_tumu(vbool4_t mask, vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfnmsac_vv_f16m4_tumu(mask, vd, vs1, vs2, vl); return __riscv_vfnmsac_vv_f16m4_tumu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmsac_vf_f16m4_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmsac_vf_f16m4_tumu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmsac.mask.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmsac.mask.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
// //
vfloat16m4_t test_vfnmsac_vf_f16m4_tumu(vbool4_t mask, vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) { vfloat16m4_t test_vfnmsac_vf_f16m4_tumu(vbool4_t mask, vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfnmsac_vf_f16m4_tumu(mask, vd, rs1, vs2, vl); return __riscv_vfnmsac_vf_f16m4_tumu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmsac_vv_f16m8_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmsac_vv_f16m8_tumu
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmsac.mask.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmsac.mask.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
// //
vfloat16m8_t test_vfnmsac_vv_f16m8_tumu(vbool2_t mask, vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) { vfloat16m8_t test_vfnmsac_vv_f16m8_tumu(vbool2_t mask, vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfnmsac_vv_f16m8_tumu(mask, vd, vs1, vs2, vl); return __riscv_vfnmsac_vv_f16m8_tumu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmsac_vf_f16m8_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmsac_vf_f16m8_tumu
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmsac.mask.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmsac.mask.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
// //
vfloat16m8_t test_vfnmsac_vf_f16m8_tumu(vbool2_t mask, vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) { vfloat16m8_t test_vfnmsac_vf_f16m8_tumu(vbool2_t mask, vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfnmsac_vf_f16m8_tumu(mask, vd, rs1, vs2, vl); return __riscv_vfnmsac_vf_f16m8_tumu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmsac_vv_f32mf2_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmsac_vv_f32mf2_tumu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmsac.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmsac.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfnmsac_vv_f32mf2_tumu(vbool64_t mask, vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) { vfloat32mf2_t test_vfnmsac_vv_f32mf2_tumu(vbool64_t mask, vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfnmsac_vv_f32mf2_tumu(mask, vd, vs1, vs2, vl); return __riscv_vfnmsac_vv_f32mf2_tumu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmsac_vf_f32mf2_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmsac_vf_f32mf2_tumu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmsac.mask.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmsac.mask.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfnmsac_vf_f32mf2_tumu(vbool64_t mask, vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) { vfloat32mf2_t test_vfnmsac_vf_f32mf2_tumu(vbool64_t mask, vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfnmsac_vf_f32mf2_tumu(mask, vd, rs1, vs2, vl); return __riscv_vfnmsac_vf_f32mf2_tumu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmsac_vv_f32m1_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmsac_vv_f32m1_tumu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmsac.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmsac.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfnmsac_vv_f32m1_tumu(vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) { vfloat32m1_t test_vfnmsac_vv_f32m1_tumu(vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfnmsac_vv_f32m1_tumu(mask, vd, vs1, vs2, vl); return __riscv_vfnmsac_vv_f32m1_tumu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmsac_vf_f32m1_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmsac_vf_f32m1_tumu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmsac.mask.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmsac.mask.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfnmsac_vf_f32m1_tumu(vbool32_t mask, vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) { vfloat32m1_t test_vfnmsac_vf_f32m1_tumu(vbool32_t mask, vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfnmsac_vf_f32m1_tumu(mask, vd, rs1, vs2, vl); return __riscv_vfnmsac_vf_f32m1_tumu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmsac_vv_f32m2_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmsac_vv_f32m2_tumu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmsac.mask.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmsac.mask.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfnmsac_vv_f32m2_tumu(vbool16_t mask, vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) { vfloat32m2_t test_vfnmsac_vv_f32m2_tumu(vbool16_t mask, vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfnmsac_vv_f32m2_tumu(mask, vd, vs1, vs2, vl); return __riscv_vfnmsac_vv_f32m2_tumu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmsac_vf_f32m2_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmsac_vf_f32m2_tumu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmsac.mask.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmsac.mask.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfnmsac_vf_f32m2_tumu(vbool16_t mask, vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) { vfloat32m2_t test_vfnmsac_vf_f32m2_tumu(vbool16_t mask, vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfnmsac_vf_f32m2_tumu(mask, vd, rs1, vs2, vl); return __riscv_vfnmsac_vf_f32m2_tumu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmsac_vv_f32m4_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmsac_vv_f32m4_tumu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmsac.mask.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmsac.mask.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfnmsac_vv_f32m4_tumu(vbool8_t mask, vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) { vfloat32m4_t test_vfnmsac_vv_f32m4_tumu(vbool8_t mask, vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfnmsac_vv_f32m4_tumu(mask, vd, vs1, vs2, vl); return __riscv_vfnmsac_vv_f32m4_tumu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmsac_vf_f32m4_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmsac_vf_f32m4_tumu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmsac.mask.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmsac.mask.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfnmsac_vf_f32m4_tumu(vbool8_t mask, vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) { vfloat32m4_t test_vfnmsac_vf_f32m4_tumu(vbool8_t mask, vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfnmsac_vf_f32m4_tumu(mask, vd, rs1, vs2, vl); return __riscv_vfnmsac_vf_f32m4_tumu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmsac_vv_f32m8_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmsac_vv_f32m8_tumu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmsac.mask.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmsac.mask.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfnmsac_vv_f32m8_tumu(vbool4_t mask, vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) { vfloat32m8_t test_vfnmsac_vv_f32m8_tumu(vbool4_t mask, vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfnmsac_vv_f32m8_tumu(mask, vd, vs1, vs2, vl); return __riscv_vfnmsac_vv_f32m8_tumu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmsac_vf_f32m8_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmsac_vf_f32m8_tumu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmsac.mask.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmsac.mask.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfnmsac_vf_f32m8_tumu(vbool4_t mask, vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) { vfloat32m8_t test_vfnmsac_vf_f32m8_tumu(vbool4_t mask, vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfnmsac_vf_f32m8_tumu(mask, vd, rs1, vs2, vl); return __riscv_vfnmsac_vf_f32m8_tumu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmsac_vv_f64m1_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmsac_vv_f64m1_tumu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmsac.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmsac.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfnmsac_vv_f64m1_tumu(vbool64_t mask, vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) { vfloat64m1_t test_vfnmsac_vv_f64m1_tumu(vbool64_t mask, vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfnmsac_vv_f64m1_tumu(mask, vd, vs1, vs2, vl); return __riscv_vfnmsac_vv_f64m1_tumu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmsac_vf_f64m1_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmsac_vf_f64m1_tumu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmsac.mask.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmsac.mask.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfnmsac_vf_f64m1_tumu(vbool64_t mask, vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) { vfloat64m1_t test_vfnmsac_vf_f64m1_tumu(vbool64_t mask, vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfnmsac_vf_f64m1_tumu(mask, vd, rs1, vs2, vl); return __riscv_vfnmsac_vf_f64m1_tumu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmsac_vv_f64m2_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmsac_vv_f64m2_tumu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmsac.mask.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmsac.mask.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfnmsac_vv_f64m2_tumu(vbool32_t mask, vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) { vfloat64m2_t test_vfnmsac_vv_f64m2_tumu(vbool32_t mask, vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfnmsac_vv_f64m2_tumu(mask, vd, vs1, vs2, vl); return __riscv_vfnmsac_vv_f64m2_tumu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmsac_vf_f64m2_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmsac_vf_f64m2_tumu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmsac.mask.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmsac.mask.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfnmsac_vf_f64m2_tumu(vbool32_t mask, vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) { vfloat64m2_t test_vfnmsac_vf_f64m2_tumu(vbool32_t mask, vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfnmsac_vf_f64m2_tumu(mask, vd, rs1, vs2, vl); return __riscv_vfnmsac_vf_f64m2_tumu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmsac_vv_f64m4_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmsac_vv_f64m4_tumu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmsac.mask.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmsac.mask.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfnmsac_vv_f64m4_tumu(vbool16_t mask, vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) { vfloat64m4_t test_vfnmsac_vv_f64m4_tumu(vbool16_t mask, vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfnmsac_vv_f64m4_tumu(mask, vd, vs1, vs2, vl); return __riscv_vfnmsac_vv_f64m4_tumu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmsac_vf_f64m4_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmsac_vf_f64m4_tumu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmsac.mask.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmsac.mask.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfnmsac_vf_f64m4_tumu(vbool16_t mask, vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) { vfloat64m4_t test_vfnmsac_vf_f64m4_tumu(vbool16_t mask, vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfnmsac_vf_f64m4_tumu(mask, vd, rs1, vs2, vl); return __riscv_vfnmsac_vf_f64m4_tumu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmsac_vv_f64m8_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmsac_vv_f64m8_tumu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmsac.mask.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmsac.mask.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfnmsac_vv_f64m8_tumu(vbool8_t mask, vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) { vfloat64m8_t test_vfnmsac_vv_f64m8_tumu(vbool8_t mask, vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfnmsac_vv_f64m8_tumu(mask, vd, vs1, vs2, vl); return __riscv_vfnmsac_vv_f64m8_tumu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmsac_vf_f64m8_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmsac_vf_f64m8_tumu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmsac.mask.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmsac.mask.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfnmsac_vf_f64m8_tumu(vbool8_t mask, vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) { vfloat64m8_t test_vfnmsac_vf_f64m8_tumu(vbool8_t mask, vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfnmsac_vf_f64m8_tumu(mask, vd, rs1, vs2, vl); return __riscv_vfnmsac_vf_f64m8_tumu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmsac_vv_f16mf4_mu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmsac_vv_f16mf4_mu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmsac.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmsac.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
// //
vfloat16mf4_t test_vfnmsac_vv_f16mf4_mu(vbool64_t mask, vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) { vfloat16mf4_t test_vfnmsac_vv_f16mf4_mu(vbool64_t mask, vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfnmsac_vv_f16mf4_mu(mask, vd, vs1, vs2, vl); return __riscv_vfnmsac_vv_f16mf4_mu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmsac_vf_f16mf4_mu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmsac_vf_f16mf4_mu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmsac.mask.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmsac.mask.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
// //
vfloat16mf4_t test_vfnmsac_vf_f16mf4_mu(vbool64_t mask, vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) { vfloat16mf4_t test_vfnmsac_vf_f16mf4_mu(vbool64_t mask, vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfnmsac_vf_f16mf4_mu(mask, vd, rs1, vs2, vl); return __riscv_vfnmsac_vf_f16mf4_mu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmsac_vv_f16mf2_mu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmsac_vv_f16mf2_mu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmsac.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmsac.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
// //
vfloat16mf2_t test_vfnmsac_vv_f16mf2_mu(vbool32_t mask, vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) { vfloat16mf2_t test_vfnmsac_vv_f16mf2_mu(vbool32_t mask, vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfnmsac_vv_f16mf2_mu(mask, vd, vs1, vs2, vl); return __riscv_vfnmsac_vv_f16mf2_mu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmsac_vf_f16mf2_mu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmsac_vf_f16mf2_mu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmsac.mask.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmsac.mask.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
// //
vfloat16mf2_t test_vfnmsac_vf_f16mf2_mu(vbool32_t mask, vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) { vfloat16mf2_t test_vfnmsac_vf_f16mf2_mu(vbool32_t mask, vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfnmsac_vf_f16mf2_mu(mask, vd, rs1, vs2, vl); return __riscv_vfnmsac_vf_f16mf2_mu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmsac_vv_f16m1_mu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmsac_vv_f16m1_mu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmsac.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmsac.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
// //
vfloat16m1_t test_vfnmsac_vv_f16m1_mu(vbool16_t mask, vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) { vfloat16m1_t test_vfnmsac_vv_f16m1_mu(vbool16_t mask, vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfnmsac_vv_f16m1_mu(mask, vd, vs1, vs2, vl); return __riscv_vfnmsac_vv_f16m1_mu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmsac_vf_f16m1_mu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmsac_vf_f16m1_mu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmsac.mask.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmsac.mask.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
// //
vfloat16m1_t test_vfnmsac_vf_f16m1_mu(vbool16_t mask, vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) { vfloat16m1_t test_vfnmsac_vf_f16m1_mu(vbool16_t mask, vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfnmsac_vf_f16m1_mu(mask, vd, rs1, vs2, vl); return __riscv_vfnmsac_vf_f16m1_mu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmsac_vv_f16m2_mu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmsac_vv_f16m2_mu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmsac.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmsac.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
// //
vfloat16m2_t test_vfnmsac_vv_f16m2_mu(vbool8_t mask, vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) { vfloat16m2_t test_vfnmsac_vv_f16m2_mu(vbool8_t mask, vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfnmsac_vv_f16m2_mu(mask, vd, vs1, vs2, vl); return __riscv_vfnmsac_vv_f16m2_mu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmsac_vf_f16m2_mu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmsac_vf_f16m2_mu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmsac.mask.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmsac.mask.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
// //
vfloat16m2_t test_vfnmsac_vf_f16m2_mu(vbool8_t mask, vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) { vfloat16m2_t test_vfnmsac_vf_f16m2_mu(vbool8_t mask, vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfnmsac_vf_f16m2_mu(mask, vd, rs1, vs2, vl); return __riscv_vfnmsac_vf_f16m2_mu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmsac_vv_f16m4_mu // CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmsac_vv_f16m4_mu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmsac.mask.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmsac.mask.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
// //
vfloat16m4_t test_vfnmsac_vv_f16m4_mu(vbool4_t mask, vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) { vfloat16m4_t test_vfnmsac_vv_f16m4_mu(vbool4_t mask, vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfnmsac_vv_f16m4_mu(mask, vd, vs1, vs2, vl); return __riscv_vfnmsac_vv_f16m4_mu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmsac_vf_f16m4_mu // CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmsac_vf_f16m4_mu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmsac.mask.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmsac.mask.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
// //
vfloat16m4_t test_vfnmsac_vf_f16m4_mu(vbool4_t mask, vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) { vfloat16m4_t test_vfnmsac_vf_f16m4_mu(vbool4_t mask, vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfnmsac_vf_f16m4_mu(mask, vd, rs1, vs2, vl); return __riscv_vfnmsac_vf_f16m4_mu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmsac_vv_f16m8_mu // CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmsac_vv_f16m8_mu
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmsac.mask.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmsac.mask.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
// //
vfloat16m8_t test_vfnmsac_vv_f16m8_mu(vbool2_t mask, vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) { vfloat16m8_t test_vfnmsac_vv_f16m8_mu(vbool2_t mask, vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfnmsac_vv_f16m8_mu(mask, vd, vs1, vs2, vl); return __riscv_vfnmsac_vv_f16m8_mu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmsac_vf_f16m8_mu // CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmsac_vf_f16m8_mu
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmsac.mask.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmsac.mask.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
// //
vfloat16m8_t test_vfnmsac_vf_f16m8_mu(vbool2_t mask, vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) { vfloat16m8_t test_vfnmsac_vf_f16m8_mu(vbool2_t mask, vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfnmsac_vf_f16m8_mu(mask, vd, rs1, vs2, vl); return __riscv_vfnmsac_vf_f16m8_mu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmsac_vv_f32mf2_mu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmsac_vv_f32mf2_mu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmsac.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmsac.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfnmsac_vv_f32mf2_mu(vbool64_t mask, vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) { vfloat32mf2_t test_vfnmsac_vv_f32mf2_mu(vbool64_t mask, vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfnmsac_vv_f32mf2_mu(mask, vd, vs1, vs2, vl); return __riscv_vfnmsac_vv_f32mf2_mu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmsac_vf_f32mf2_mu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmsac_vf_f32mf2_mu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmsac.mask.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmsac.mask.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfnmsac_vf_f32mf2_mu(vbool64_t mask, vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) { vfloat32mf2_t test_vfnmsac_vf_f32mf2_mu(vbool64_t mask, vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfnmsac_vf_f32mf2_mu(mask, vd, rs1, vs2, vl); return __riscv_vfnmsac_vf_f32mf2_mu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmsac_vv_f32m1_mu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmsac_vv_f32m1_mu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmsac.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmsac.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfnmsac_vv_f32m1_mu(vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) { vfloat32m1_t test_vfnmsac_vv_f32m1_mu(vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfnmsac_vv_f32m1_mu(mask, vd, vs1, vs2, vl); return __riscv_vfnmsac_vv_f32m1_mu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmsac_vf_f32m1_mu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmsac_vf_f32m1_mu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmsac.mask.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmsac.mask.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfnmsac_vf_f32m1_mu(vbool32_t mask, vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) { vfloat32m1_t test_vfnmsac_vf_f32m1_mu(vbool32_t mask, vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfnmsac_vf_f32m1_mu(mask, vd, rs1, vs2, vl); return __riscv_vfnmsac_vf_f32m1_mu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmsac_vv_f32m2_mu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmsac_vv_f32m2_mu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmsac.mask.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmsac.mask.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfnmsac_vv_f32m2_mu(vbool16_t mask, vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) { vfloat32m2_t test_vfnmsac_vv_f32m2_mu(vbool16_t mask, vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfnmsac_vv_f32m2_mu(mask, vd, vs1, vs2, vl); return __riscv_vfnmsac_vv_f32m2_mu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmsac_vf_f32m2_mu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmsac_vf_f32m2_mu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmsac.mask.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmsac.mask.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfnmsac_vf_f32m2_mu(vbool16_t mask, vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) { vfloat32m2_t test_vfnmsac_vf_f32m2_mu(vbool16_t mask, vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfnmsac_vf_f32m2_mu(mask, vd, rs1, vs2, vl); return __riscv_vfnmsac_vf_f32m2_mu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmsac_vv_f32m4_mu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmsac_vv_f32m4_mu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmsac.mask.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmsac.mask.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfnmsac_vv_f32m4_mu(vbool8_t mask, vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) { vfloat32m4_t test_vfnmsac_vv_f32m4_mu(vbool8_t mask, vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfnmsac_vv_f32m4_mu(mask, vd, vs1, vs2, vl); return __riscv_vfnmsac_vv_f32m4_mu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmsac_vf_f32m4_mu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmsac_vf_f32m4_mu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmsac.mask.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmsac.mask.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfnmsac_vf_f32m4_mu(vbool8_t mask, vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) { vfloat32m4_t test_vfnmsac_vf_f32m4_mu(vbool8_t mask, vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfnmsac_vf_f32m4_mu(mask, vd, rs1, vs2, vl); return __riscv_vfnmsac_vf_f32m4_mu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmsac_vv_f32m8_mu // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmsac_vv_f32m8_mu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmsac.mask.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmsac.mask.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfnmsac_vv_f32m8_mu(vbool4_t mask, vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) { vfloat32m8_t test_vfnmsac_vv_f32m8_mu(vbool4_t mask, vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfnmsac_vv_f32m8_mu(mask, vd, vs1, vs2, vl); return __riscv_vfnmsac_vv_f32m8_mu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmsac_vf_f32m8_mu // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmsac_vf_f32m8_mu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmsac.mask.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmsac.mask.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfnmsac_vf_f32m8_mu(vbool4_t mask, vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) { vfloat32m8_t test_vfnmsac_vf_f32m8_mu(vbool4_t mask, vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfnmsac_vf_f32m8_mu(mask, vd, rs1, vs2, vl); return __riscv_vfnmsac_vf_f32m8_mu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmsac_vv_f64m1_mu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmsac_vv_f64m1_mu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmsac.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmsac.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfnmsac_vv_f64m1_mu(vbool64_t mask, vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) { vfloat64m1_t test_vfnmsac_vv_f64m1_mu(vbool64_t mask, vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfnmsac_vv_f64m1_mu(mask, vd, vs1, vs2, vl); return __riscv_vfnmsac_vv_f64m1_mu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmsac_vf_f64m1_mu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmsac_vf_f64m1_mu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmsac.mask.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmsac.mask.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfnmsac_vf_f64m1_mu(vbool64_t mask, vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) { vfloat64m1_t test_vfnmsac_vf_f64m1_mu(vbool64_t mask, vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfnmsac_vf_f64m1_mu(mask, vd, rs1, vs2, vl); return __riscv_vfnmsac_vf_f64m1_mu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmsac_vv_f64m2_mu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmsac_vv_f64m2_mu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmsac.mask.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmsac.mask.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfnmsac_vv_f64m2_mu(vbool32_t mask, vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) { vfloat64m2_t test_vfnmsac_vv_f64m2_mu(vbool32_t mask, vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfnmsac_vv_f64m2_mu(mask, vd, vs1, vs2, vl); return __riscv_vfnmsac_vv_f64m2_mu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmsac_vf_f64m2_mu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmsac_vf_f64m2_mu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmsac.mask.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmsac.mask.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfnmsac_vf_f64m2_mu(vbool32_t mask, vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) { vfloat64m2_t test_vfnmsac_vf_f64m2_mu(vbool32_t mask, vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfnmsac_vf_f64m2_mu(mask, vd, rs1, vs2, vl); return __riscv_vfnmsac_vf_f64m2_mu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmsac_vv_f64m4_mu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmsac_vv_f64m4_mu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmsac.mask.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmsac.mask.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfnmsac_vv_f64m4_mu(vbool16_t mask, vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) { vfloat64m4_t test_vfnmsac_vv_f64m4_mu(vbool16_t mask, vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfnmsac_vv_f64m4_mu(mask, vd, vs1, vs2, vl); return __riscv_vfnmsac_vv_f64m4_mu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmsac_vf_f64m4_mu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmsac_vf_f64m4_mu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmsac.mask.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmsac.mask.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfnmsac_vf_f64m4_mu(vbool16_t mask, vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) { vfloat64m4_t test_vfnmsac_vf_f64m4_mu(vbool16_t mask, vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfnmsac_vf_f64m4_mu(mask, vd, rs1, vs2, vl); return __riscv_vfnmsac_vf_f64m4_mu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmsac_vv_f64m8_mu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmsac_vv_f64m8_mu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmsac.mask.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmsac.mask.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfnmsac_vv_f64m8_mu(vbool8_t mask, vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) { vfloat64m8_t test_vfnmsac_vv_f64m8_mu(vbool8_t mask, vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfnmsac_vv_f64m8_mu(mask, vd, vs1, vs2, vl); return __riscv_vfnmsac_vv_f64m8_mu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmsac_vf_f64m8_mu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmsac_vf_f64m8_mu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmsac.mask.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmsac.mask.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfnmsac_vf_f64m8_mu(vbool8_t mask, vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) { vfloat64m8_t test_vfnmsac_vf_f64m8_mu(vbool8_t mask, vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfnmsac_vf_f64m8_mu(mask, vd, rs1, vs2, vl); return __riscv_vfnmsac_vf_f64m8_mu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmsac_vv_f16mf4_rm_tu
// CHECK-RV64-SAME: (<vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmsac.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
//
vfloat16mf4_t test_vfnmsac_vv_f16mf4_rm_tu(vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfnmsac_vv_f16mf4_rm_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmsac_vf_f16mf4_rm_tu
// CHECK-RV64-SAME: (<vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmsac.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
//
vfloat16mf4_t test_vfnmsac_vf_f16mf4_rm_tu(vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfnmsac_vf_f16mf4_rm_tu(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmsac_vv_f16mf2_rm_tu
// CHECK-RV64-SAME: (<vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmsac.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
//
vfloat16mf2_t test_vfnmsac_vv_f16mf2_rm_tu(vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfnmsac_vv_f16mf2_rm_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmsac_vf_f16mf2_rm_tu
// CHECK-RV64-SAME: (<vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmsac.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
//
vfloat16mf2_t test_vfnmsac_vf_f16mf2_rm_tu(vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfnmsac_vf_f16mf2_rm_tu(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmsac_vv_f16m1_rm_tu
// CHECK-RV64-SAME: (<vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmsac.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfnmsac_vv_f16m1_rm_tu(vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfnmsac_vv_f16m1_rm_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmsac_vf_f16m1_rm_tu
// CHECK-RV64-SAME: (<vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmsac.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfnmsac_vf_f16m1_rm_tu(vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfnmsac_vf_f16m1_rm_tu(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmsac_vv_f16m2_rm_tu
// CHECK-RV64-SAME: (<vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmsac.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
//
vfloat16m2_t test_vfnmsac_vv_f16m2_rm_tu(vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfnmsac_vv_f16m2_rm_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmsac_vf_f16m2_rm_tu
// CHECK-RV64-SAME: (<vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmsac.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
//
vfloat16m2_t test_vfnmsac_vf_f16m2_rm_tu(vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfnmsac_vf_f16m2_rm_tu(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmsac_vv_f16m4_rm_tu
// CHECK-RV64-SAME: (<vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmsac.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
//
vfloat16m4_t test_vfnmsac_vv_f16m4_rm_tu(vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfnmsac_vv_f16m4_rm_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmsac_vf_f16m4_rm_tu
// CHECK-RV64-SAME: (<vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmsac.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
//
vfloat16m4_t test_vfnmsac_vf_f16m4_rm_tu(vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfnmsac_vf_f16m4_rm_tu(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmsac_vv_f16m8_rm_tu
// CHECK-RV64-SAME: (<vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmsac.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
//
vfloat16m8_t test_vfnmsac_vv_f16m8_rm_tu(vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfnmsac_vv_f16m8_rm_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmsac_vf_f16m8_rm_tu
// CHECK-RV64-SAME: (<vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmsac.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
//
vfloat16m8_t test_vfnmsac_vf_f16m8_rm_tu(vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfnmsac_vf_f16m8_rm_tu(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmsac_vv_f32mf2_rm_tu
// CHECK-RV64-SAME: (<vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmsac.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
//
vfloat32mf2_t test_vfnmsac_vv_f32mf2_rm_tu(vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfnmsac_vv_f32mf2_rm_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmsac_vf_f32mf2_rm_tu
// CHECK-RV64-SAME: (<vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmsac.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
//
vfloat32mf2_t test_vfnmsac_vf_f32mf2_rm_tu(vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfnmsac_vf_f32mf2_rm_tu(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmsac_vv_f32m1_rm_tu
// CHECK-RV64-SAME: (<vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmsac.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfnmsac_vv_f32m1_rm_tu(vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfnmsac_vv_f32m1_rm_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmsac_vf_f32m1_rm_tu
// CHECK-RV64-SAME: (<vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmsac.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfnmsac_vf_f32m1_rm_tu(vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfnmsac_vf_f32m1_rm_tu(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmsac_vv_f32m2_rm_tu
// CHECK-RV64-SAME: (<vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmsac.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
//
vfloat32m2_t test_vfnmsac_vv_f32m2_rm_tu(vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfnmsac_vv_f32m2_rm_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmsac_vf_f32m2_rm_tu
// CHECK-RV64-SAME: (<vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmsac.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
//
vfloat32m2_t test_vfnmsac_vf_f32m2_rm_tu(vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfnmsac_vf_f32m2_rm_tu(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmsac_vv_f32m4_rm_tu
// CHECK-RV64-SAME: (<vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmsac.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
//
vfloat32m4_t test_vfnmsac_vv_f32m4_rm_tu(vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfnmsac_vv_f32m4_rm_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmsac_vf_f32m4_rm_tu
// CHECK-RV64-SAME: (<vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmsac.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
//
vfloat32m4_t test_vfnmsac_vf_f32m4_rm_tu(vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfnmsac_vf_f32m4_rm_tu(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmsac_vv_f32m8_rm_tu
// CHECK-RV64-SAME: (<vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmsac.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
//
vfloat32m8_t test_vfnmsac_vv_f32m8_rm_tu(vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfnmsac_vv_f32m8_rm_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmsac_vf_f32m8_rm_tu
// CHECK-RV64-SAME: (<vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmsac.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
//
vfloat32m8_t test_vfnmsac_vf_f32m8_rm_tu(vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfnmsac_vf_f32m8_rm_tu(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmsac_vv_f64m1_rm_tu
// CHECK-RV64-SAME: (<vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmsac.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfnmsac_vv_f64m1_rm_tu(vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfnmsac_vv_f64m1_rm_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmsac_vf_f64m1_rm_tu
// CHECK-RV64-SAME: (<vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmsac.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfnmsac_vf_f64m1_rm_tu(vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfnmsac_vf_f64m1_rm_tu(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmsac_vv_f64m2_rm_tu
// CHECK-RV64-SAME: (<vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmsac.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
//
vfloat64m2_t test_vfnmsac_vv_f64m2_rm_tu(vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfnmsac_vv_f64m2_rm_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmsac_vf_f64m2_rm_tu
// CHECK-RV64-SAME: (<vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmsac.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
//
vfloat64m2_t test_vfnmsac_vf_f64m2_rm_tu(vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfnmsac_vf_f64m2_rm_tu(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmsac_vv_f64m4_rm_tu
// CHECK-RV64-SAME: (<vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmsac.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
//
vfloat64m4_t test_vfnmsac_vv_f64m4_rm_tu(vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfnmsac_vv_f64m4_rm_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmsac_vf_f64m4_rm_tu
// CHECK-RV64-SAME: (<vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmsac.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
//
vfloat64m4_t test_vfnmsac_vf_f64m4_rm_tu(vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfnmsac_vf_f64m4_rm_tu(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmsac_vv_f64m8_rm_tu
// CHECK-RV64-SAME: (<vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmsac.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
//
vfloat64m8_t test_vfnmsac_vv_f64m8_rm_tu(vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfnmsac_vv_f64m8_rm_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmsac_vf_f64m8_rm_tu
// CHECK-RV64-SAME: (<vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmsac.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
//
vfloat64m8_t test_vfnmsac_vf_f64m8_rm_tu(vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfnmsac_vf_f64m8_rm_tu(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmsac_vv_f16mf4_rm_tum
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmsac.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
//
vfloat16mf4_t test_vfnmsac_vv_f16mf4_rm_tum(vbool64_t mask, vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfnmsac_vv_f16mf4_rm_tum(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmsac_vf_f16mf4_rm_tum
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmsac.mask.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
//
vfloat16mf4_t test_vfnmsac_vf_f16mf4_rm_tum(vbool64_t mask, vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfnmsac_vf_f16mf4_rm_tum(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmsac_vv_f16mf2_rm_tum
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmsac.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
//
vfloat16mf2_t test_vfnmsac_vv_f16mf2_rm_tum(vbool32_t mask, vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfnmsac_vv_f16mf2_rm_tum(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmsac_vf_f16mf2_rm_tum
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmsac.mask.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
//
vfloat16mf2_t test_vfnmsac_vf_f16mf2_rm_tum(vbool32_t mask, vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfnmsac_vf_f16mf2_rm_tum(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmsac_vv_f16m1_rm_tum
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmsac.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfnmsac_vv_f16m1_rm_tum(vbool16_t mask, vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfnmsac_vv_f16m1_rm_tum(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmsac_vf_f16m1_rm_tum
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmsac.mask.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfnmsac_vf_f16m1_rm_tum(vbool16_t mask, vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfnmsac_vf_f16m1_rm_tum(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmsac_vv_f16m2_rm_tum
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmsac.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
//
vfloat16m2_t test_vfnmsac_vv_f16m2_rm_tum(vbool8_t mask, vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfnmsac_vv_f16m2_rm_tum(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmsac_vf_f16m2_rm_tum
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmsac.mask.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
//
vfloat16m2_t test_vfnmsac_vf_f16m2_rm_tum(vbool8_t mask, vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfnmsac_vf_f16m2_rm_tum(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmsac_vv_f16m4_rm_tum
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmsac.mask.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
//
vfloat16m4_t test_vfnmsac_vv_f16m4_rm_tum(vbool4_t mask, vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfnmsac_vv_f16m4_rm_tum(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmsac_vf_f16m4_rm_tum
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmsac.mask.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
//
vfloat16m4_t test_vfnmsac_vf_f16m4_rm_tum(vbool4_t mask, vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfnmsac_vf_f16m4_rm_tum(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmsac_vv_f16m8_rm_tum
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmsac.mask.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
//
vfloat16m8_t test_vfnmsac_vv_f16m8_rm_tum(vbool2_t mask, vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfnmsac_vv_f16m8_rm_tum(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmsac_vf_f16m8_rm_tum
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmsac.mask.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
//
vfloat16m8_t test_vfnmsac_vf_f16m8_rm_tum(vbool2_t mask, vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfnmsac_vf_f16m8_rm_tum(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmsac_vv_f32mf2_rm_tum
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmsac.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
//
vfloat32mf2_t test_vfnmsac_vv_f32mf2_rm_tum(vbool64_t mask, vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfnmsac_vv_f32mf2_rm_tum(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmsac_vf_f32mf2_rm_tum
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmsac.mask.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
//
vfloat32mf2_t test_vfnmsac_vf_f32mf2_rm_tum(vbool64_t mask, vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfnmsac_vf_f32mf2_rm_tum(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmsac_vv_f32m1_rm_tum
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmsac.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfnmsac_vv_f32m1_rm_tum(vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfnmsac_vv_f32m1_rm_tum(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmsac_vf_f32m1_rm_tum
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmsac.mask.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfnmsac_vf_f32m1_rm_tum(vbool32_t mask, vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfnmsac_vf_f32m1_rm_tum(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmsac_vv_f32m2_rm_tum
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmsac.mask.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
//
vfloat32m2_t test_vfnmsac_vv_f32m2_rm_tum(vbool16_t mask, vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfnmsac_vv_f32m2_rm_tum(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmsac_vf_f32m2_rm_tum
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmsac.mask.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
//
vfloat32m2_t test_vfnmsac_vf_f32m2_rm_tum(vbool16_t mask, vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfnmsac_vf_f32m2_rm_tum(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmsac_vv_f32m4_rm_tum
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmsac.mask.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
//
vfloat32m4_t test_vfnmsac_vv_f32m4_rm_tum(vbool8_t mask, vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfnmsac_vv_f32m4_rm_tum(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmsac_vf_f32m4_rm_tum
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmsac.mask.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
//
vfloat32m4_t test_vfnmsac_vf_f32m4_rm_tum(vbool8_t mask, vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfnmsac_vf_f32m4_rm_tum(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmsac_vv_f32m8_rm_tum
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmsac.mask.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
//
vfloat32m8_t test_vfnmsac_vv_f32m8_rm_tum(vbool4_t mask, vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfnmsac_vv_f32m8_rm_tum(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmsac_vf_f32m8_rm_tum
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmsac.mask.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
//
vfloat32m8_t test_vfnmsac_vf_f32m8_rm_tum(vbool4_t mask, vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfnmsac_vf_f32m8_rm_tum(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmsac_vv_f64m1_rm_tum
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmsac.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfnmsac_vv_f64m1_rm_tum(vbool64_t mask, vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfnmsac_vv_f64m1_rm_tum(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmsac_vf_f64m1_rm_tum
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmsac.mask.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfnmsac_vf_f64m1_rm_tum(vbool64_t mask, vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfnmsac_vf_f64m1_rm_tum(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmsac_vv_f64m2_rm_tum
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmsac.mask.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
//
vfloat64m2_t test_vfnmsac_vv_f64m2_rm_tum(vbool32_t mask, vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfnmsac_vv_f64m2_rm_tum(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmsac_vf_f64m2_rm_tum
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmsac.mask.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
//
vfloat64m2_t test_vfnmsac_vf_f64m2_rm_tum(vbool32_t mask, vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfnmsac_vf_f64m2_rm_tum(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmsac_vv_f64m4_rm_tum
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmsac.mask.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
//
vfloat64m4_t test_vfnmsac_vv_f64m4_rm_tum(vbool16_t mask, vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfnmsac_vv_f64m4_rm_tum(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmsac_vf_f64m4_rm_tum
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmsac.mask.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
//
vfloat64m4_t test_vfnmsac_vf_f64m4_rm_tum(vbool16_t mask, vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfnmsac_vf_f64m4_rm_tum(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmsac_vv_f64m8_rm_tum
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmsac.mask.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
//
vfloat64m8_t test_vfnmsac_vv_f64m8_rm_tum(vbool8_t mask, vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfnmsac_vv_f64m8_rm_tum(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmsac_vf_f64m8_rm_tum
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmsac.mask.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
//
vfloat64m8_t test_vfnmsac_vf_f64m8_rm_tum(vbool8_t mask, vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfnmsac_vf_f64m8_rm_tum(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmsac_vv_f16mf4_rm_tumu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmsac.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
//
vfloat16mf4_t test_vfnmsac_vv_f16mf4_rm_tumu(vbool64_t mask, vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfnmsac_vv_f16mf4_rm_tumu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmsac_vf_f16mf4_rm_tumu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmsac.mask.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
//
vfloat16mf4_t test_vfnmsac_vf_f16mf4_rm_tumu(vbool64_t mask, vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfnmsac_vf_f16mf4_rm_tumu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmsac_vv_f16mf2_rm_tumu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmsac.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
//
vfloat16mf2_t test_vfnmsac_vv_f16mf2_rm_tumu(vbool32_t mask, vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfnmsac_vv_f16mf2_rm_tumu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmsac_vf_f16mf2_rm_tumu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmsac.mask.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
//
vfloat16mf2_t test_vfnmsac_vf_f16mf2_rm_tumu(vbool32_t mask, vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfnmsac_vf_f16mf2_rm_tumu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmsac_vv_f16m1_rm_tumu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmsac.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfnmsac_vv_f16m1_rm_tumu(vbool16_t mask, vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfnmsac_vv_f16m1_rm_tumu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmsac_vf_f16m1_rm_tumu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmsac.mask.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfnmsac_vf_f16m1_rm_tumu(vbool16_t mask, vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfnmsac_vf_f16m1_rm_tumu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmsac_vv_f16m2_rm_tumu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmsac.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
//
vfloat16m2_t test_vfnmsac_vv_f16m2_rm_tumu(vbool8_t mask, vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfnmsac_vv_f16m2_rm_tumu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmsac_vf_f16m2_rm_tumu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmsac.mask.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
//
vfloat16m2_t test_vfnmsac_vf_f16m2_rm_tumu(vbool8_t mask, vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfnmsac_vf_f16m2_rm_tumu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmsac_vv_f16m4_rm_tumu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmsac.mask.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
//
vfloat16m4_t test_vfnmsac_vv_f16m4_rm_tumu(vbool4_t mask, vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfnmsac_vv_f16m4_rm_tumu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmsac_vf_f16m4_rm_tumu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmsac.mask.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
//
vfloat16m4_t test_vfnmsac_vf_f16m4_rm_tumu(vbool4_t mask, vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfnmsac_vf_f16m4_rm_tumu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmsac_vv_f16m8_rm_tumu
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmsac.mask.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
//
vfloat16m8_t test_vfnmsac_vv_f16m8_rm_tumu(vbool2_t mask, vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfnmsac_vv_f16m8_rm_tumu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmsac_vf_f16m8_rm_tumu
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmsac.mask.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
//
vfloat16m8_t test_vfnmsac_vf_f16m8_rm_tumu(vbool2_t mask, vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfnmsac_vf_f16m8_rm_tumu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmsac_vv_f32mf2_rm_tumu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmsac.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
//
vfloat32mf2_t test_vfnmsac_vv_f32mf2_rm_tumu(vbool64_t mask, vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfnmsac_vv_f32mf2_rm_tumu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmsac_vf_f32mf2_rm_tumu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmsac.mask.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
//
vfloat32mf2_t test_vfnmsac_vf_f32mf2_rm_tumu(vbool64_t mask, vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfnmsac_vf_f32mf2_rm_tumu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmsac_vv_f32m1_rm_tumu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmsac.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfnmsac_vv_f32m1_rm_tumu(vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfnmsac_vv_f32m1_rm_tumu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmsac_vf_f32m1_rm_tumu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmsac.mask.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfnmsac_vf_f32m1_rm_tumu(vbool32_t mask, vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfnmsac_vf_f32m1_rm_tumu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmsac_vv_f32m2_rm_tumu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmsac.mask.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
//
vfloat32m2_t test_vfnmsac_vv_f32m2_rm_tumu(vbool16_t mask, vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfnmsac_vv_f32m2_rm_tumu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmsac_vf_f32m2_rm_tumu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmsac.mask.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
//
vfloat32m2_t test_vfnmsac_vf_f32m2_rm_tumu(vbool16_t mask, vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfnmsac_vf_f32m2_rm_tumu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmsac_vv_f32m4_rm_tumu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmsac.mask.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
//
vfloat32m4_t test_vfnmsac_vv_f32m4_rm_tumu(vbool8_t mask, vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfnmsac_vv_f32m4_rm_tumu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmsac_vf_f32m4_rm_tumu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmsac.mask.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
//
vfloat32m4_t test_vfnmsac_vf_f32m4_rm_tumu(vbool8_t mask, vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfnmsac_vf_f32m4_rm_tumu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmsac_vv_f32m8_rm_tumu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmsac.mask.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
//
vfloat32m8_t test_vfnmsac_vv_f32m8_rm_tumu(vbool4_t mask, vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfnmsac_vv_f32m8_rm_tumu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmsac_vf_f32m8_rm_tumu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmsac.mask.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
//
vfloat32m8_t test_vfnmsac_vf_f32m8_rm_tumu(vbool4_t mask, vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfnmsac_vf_f32m8_rm_tumu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmsac_vv_f64m1_rm_tumu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmsac.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfnmsac_vv_f64m1_rm_tumu(vbool64_t mask, vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfnmsac_vv_f64m1_rm_tumu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmsac_vf_f64m1_rm_tumu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmsac.mask.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfnmsac_vf_f64m1_rm_tumu(vbool64_t mask, vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfnmsac_vf_f64m1_rm_tumu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmsac_vv_f64m2_rm_tumu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmsac.mask.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
//
vfloat64m2_t test_vfnmsac_vv_f64m2_rm_tumu(vbool32_t mask, vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfnmsac_vv_f64m2_rm_tumu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmsac_vf_f64m2_rm_tumu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmsac.mask.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
//
vfloat64m2_t test_vfnmsac_vf_f64m2_rm_tumu(vbool32_t mask, vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfnmsac_vf_f64m2_rm_tumu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmsac_vv_f64m4_rm_tumu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmsac.mask.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
//
vfloat64m4_t test_vfnmsac_vv_f64m4_rm_tumu(vbool16_t mask, vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfnmsac_vv_f64m4_rm_tumu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmsac_vf_f64m4_rm_tumu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmsac.mask.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
//
vfloat64m4_t test_vfnmsac_vf_f64m4_rm_tumu(vbool16_t mask, vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfnmsac_vf_f64m4_rm_tumu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmsac_vv_f64m8_rm_tumu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmsac.mask.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
//
vfloat64m8_t test_vfnmsac_vv_f64m8_rm_tumu(vbool8_t mask, vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfnmsac_vv_f64m8_rm_tumu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmsac_vf_f64m8_rm_tumu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmsac.mask.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
//
vfloat64m8_t test_vfnmsac_vf_f64m8_rm_tumu(vbool8_t mask, vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfnmsac_vf_f64m8_rm_tumu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmsac_vv_f16mf4_rm_mu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmsac.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
//
vfloat16mf4_t test_vfnmsac_vv_f16mf4_rm_mu(vbool64_t mask, vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfnmsac_vv_f16mf4_rm_mu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmsac_vf_f16mf4_rm_mu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmsac.mask.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
//
vfloat16mf4_t test_vfnmsac_vf_f16mf4_rm_mu(vbool64_t mask, vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfnmsac_vf_f16mf4_rm_mu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmsac_vv_f16mf2_rm_mu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmsac.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
//
vfloat16mf2_t test_vfnmsac_vv_f16mf2_rm_mu(vbool32_t mask, vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfnmsac_vv_f16mf2_rm_mu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmsac_vf_f16mf2_rm_mu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmsac.mask.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
//
vfloat16mf2_t test_vfnmsac_vf_f16mf2_rm_mu(vbool32_t mask, vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfnmsac_vf_f16mf2_rm_mu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmsac_vv_f16m1_rm_mu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmsac.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfnmsac_vv_f16m1_rm_mu(vbool16_t mask, vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfnmsac_vv_f16m1_rm_mu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmsac_vf_f16m1_rm_mu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmsac.mask.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfnmsac_vf_f16m1_rm_mu(vbool16_t mask, vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfnmsac_vf_f16m1_rm_mu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmsac_vv_f16m2_rm_mu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmsac.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
//
vfloat16m2_t test_vfnmsac_vv_f16m2_rm_mu(vbool8_t mask, vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfnmsac_vv_f16m2_rm_mu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmsac_vf_f16m2_rm_mu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmsac.mask.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
//
vfloat16m2_t test_vfnmsac_vf_f16m2_rm_mu(vbool8_t mask, vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfnmsac_vf_f16m2_rm_mu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmsac_vv_f16m4_rm_mu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmsac.mask.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
//
vfloat16m4_t test_vfnmsac_vv_f16m4_rm_mu(vbool4_t mask, vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfnmsac_vv_f16m4_rm_mu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmsac_vf_f16m4_rm_mu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmsac.mask.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
//
vfloat16m4_t test_vfnmsac_vf_f16m4_rm_mu(vbool4_t mask, vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfnmsac_vf_f16m4_rm_mu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmsac_vv_f16m8_rm_mu
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmsac.mask.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
//
vfloat16m8_t test_vfnmsac_vv_f16m8_rm_mu(vbool2_t mask, vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfnmsac_vv_f16m8_rm_mu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmsac_vf_f16m8_rm_mu
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmsac.mask.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
//
vfloat16m8_t test_vfnmsac_vf_f16m8_rm_mu(vbool2_t mask, vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfnmsac_vf_f16m8_rm_mu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmsac_vv_f32mf2_rm_mu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmsac.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
//
vfloat32mf2_t test_vfnmsac_vv_f32mf2_rm_mu(vbool64_t mask, vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfnmsac_vv_f32mf2_rm_mu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmsac_vf_f32mf2_rm_mu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmsac.mask.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
//
vfloat32mf2_t test_vfnmsac_vf_f32mf2_rm_mu(vbool64_t mask, vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfnmsac_vf_f32mf2_rm_mu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmsac_vv_f32m1_rm_mu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmsac.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfnmsac_vv_f32m1_rm_mu(vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfnmsac_vv_f32m1_rm_mu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmsac_vf_f32m1_rm_mu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmsac.mask.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfnmsac_vf_f32m1_rm_mu(vbool32_t mask, vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfnmsac_vf_f32m1_rm_mu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmsac_vv_f32m2_rm_mu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmsac.mask.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
//
vfloat32m2_t test_vfnmsac_vv_f32m2_rm_mu(vbool16_t mask, vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfnmsac_vv_f32m2_rm_mu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmsac_vf_f32m2_rm_mu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmsac.mask.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
//
vfloat32m2_t test_vfnmsac_vf_f32m2_rm_mu(vbool16_t mask, vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfnmsac_vf_f32m2_rm_mu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmsac_vv_f32m4_rm_mu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmsac.mask.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
//
vfloat32m4_t test_vfnmsac_vv_f32m4_rm_mu(vbool8_t mask, vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfnmsac_vv_f32m4_rm_mu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmsac_vf_f32m4_rm_mu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmsac.mask.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
//
vfloat32m4_t test_vfnmsac_vf_f32m4_rm_mu(vbool8_t mask, vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfnmsac_vf_f32m4_rm_mu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmsac_vv_f32m8_rm_mu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmsac.mask.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
//
vfloat32m8_t test_vfnmsac_vv_f32m8_rm_mu(vbool4_t mask, vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfnmsac_vv_f32m8_rm_mu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmsac_vf_f32m8_rm_mu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmsac.mask.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
//
vfloat32m8_t test_vfnmsac_vf_f32m8_rm_mu(vbool4_t mask, vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfnmsac_vf_f32m8_rm_mu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmsac_vv_f64m1_rm_mu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmsac.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfnmsac_vv_f64m1_rm_mu(vbool64_t mask, vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfnmsac_vv_f64m1_rm_mu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmsac_vf_f64m1_rm_mu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmsac.mask.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfnmsac_vf_f64m1_rm_mu(vbool64_t mask, vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfnmsac_vf_f64m1_rm_mu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmsac_vv_f64m2_rm_mu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmsac.mask.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
//
vfloat64m2_t test_vfnmsac_vv_f64m2_rm_mu(vbool32_t mask, vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfnmsac_vv_f64m2_rm_mu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmsac_vf_f64m2_rm_mu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmsac.mask.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
//
vfloat64m2_t test_vfnmsac_vf_f64m2_rm_mu(vbool32_t mask, vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfnmsac_vf_f64m2_rm_mu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmsac_vv_f64m4_rm_mu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmsac.mask.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
//
vfloat64m4_t test_vfnmsac_vv_f64m4_rm_mu(vbool16_t mask, vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfnmsac_vv_f64m4_rm_mu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmsac_vf_f64m4_rm_mu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmsac.mask.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
//
vfloat64m4_t test_vfnmsac_vf_f64m4_rm_mu(vbool16_t mask, vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfnmsac_vf_f64m4_rm_mu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmsac_vv_f64m8_rm_mu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmsac.mask.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
//
vfloat64m8_t test_vfnmsac_vv_f64m8_rm_mu(vbool8_t mask, vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfnmsac_vv_f64m8_rm_mu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmsac_vf_f64m8_rm_mu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmsac.mask.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
//
vfloat64m8_t test_vfnmsac_vf_f64m8_rm_mu(vbool8_t mask, vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfnmsac_vf_f64m8_rm_mu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}

clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/non-overloaded/vfnmsub.c

// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target // REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh \ // RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh \
// RUN: -target-feature +experimental-zvfh -disable-O0-optnone \ // RUN: -target-feature +experimental-zvfh -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ // RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s // RUN: FileCheck --check-prefix=CHECK-RV64 %s
#include <riscv_vector.h> #include <riscv_vector.h>
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmsub_vv_f16mf4_tu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmsub_vv_f16mf4_tu
// CHECK-RV64-SAME: (<vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK-RV64-SAME: (<vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmsub.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmsub.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
// //
vfloat16mf4_t test_vfnmsub_vv_f16mf4_tu(vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) { vfloat16mf4_t test_vfnmsub_vv_f16mf4_tu(vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfnmsub_vv_f16mf4_tu(vd, vs1, vs2, vl); return __riscv_vfnmsub_vv_f16mf4_tu(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmsub_vf_f16mf4_tu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmsub_vf_f16mf4_tu
// CHECK-RV64-SAME: (<vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmsub.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmsub.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
// //
vfloat16mf4_t test_vfnmsub_vf_f16mf4_tu(vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) { vfloat16mf4_t test_vfnmsub_vf_f16mf4_tu(vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfnmsub_vf_f16mf4_tu(vd, rs1, vs2, vl); return __riscv_vfnmsub_vf_f16mf4_tu(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmsub_vv_f16mf2_tu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmsub_vv_f16mf2_tu
// CHECK-RV64-SAME: (<vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmsub.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmsub.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
// //
vfloat16mf2_t test_vfnmsub_vv_f16mf2_tu(vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) { vfloat16mf2_t test_vfnmsub_vv_f16mf2_tu(vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfnmsub_vv_f16mf2_tu(vd, vs1, vs2, vl); return __riscv_vfnmsub_vv_f16mf2_tu(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmsub_vf_f16mf2_tu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmsub_vf_f16mf2_tu
// CHECK-RV64-SAME: (<vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmsub.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmsub.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
// //
vfloat16mf2_t test_vfnmsub_vf_f16mf2_tu(vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) { vfloat16mf2_t test_vfnmsub_vf_f16mf2_tu(vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfnmsub_vf_f16mf2_tu(vd, rs1, vs2, vl); return __riscv_vfnmsub_vf_f16mf2_tu(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmsub_vv_f16m1_tu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmsub_vv_f16m1_tu
// CHECK-RV64-SAME: (<vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmsub.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmsub.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
// //
vfloat16m1_t test_vfnmsub_vv_f16m1_tu(vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) { vfloat16m1_t test_vfnmsub_vv_f16m1_tu(vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfnmsub_vv_f16m1_tu(vd, vs1, vs2, vl); return __riscv_vfnmsub_vv_f16m1_tu(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmsub_vf_f16m1_tu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmsub_vf_f16m1_tu
// CHECK-RV64-SAME: (<vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmsub.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmsub.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
// //
vfloat16m1_t test_vfnmsub_vf_f16m1_tu(vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) { vfloat16m1_t test_vfnmsub_vf_f16m1_tu(vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfnmsub_vf_f16m1_tu(vd, rs1, vs2, vl); return __riscv_vfnmsub_vf_f16m1_tu(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmsub_vv_f16m2_tu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmsub_vv_f16m2_tu
// CHECK-RV64-SAME: (<vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmsub.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmsub.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
// //
vfloat16m2_t test_vfnmsub_vv_f16m2_tu(vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) { vfloat16m2_t test_vfnmsub_vv_f16m2_tu(vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfnmsub_vv_f16m2_tu(vd, vs1, vs2, vl); return __riscv_vfnmsub_vv_f16m2_tu(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmsub_vf_f16m2_tu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmsub_vf_f16m2_tu
// CHECK-RV64-SAME: (<vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmsub.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmsub.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
// //
vfloat16m2_t test_vfnmsub_vf_f16m2_tu(vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) { vfloat16m2_t test_vfnmsub_vf_f16m2_tu(vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfnmsub_vf_f16m2_tu(vd, rs1, vs2, vl); return __riscv_vfnmsub_vf_f16m2_tu(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmsub_vv_f16m4_tu // CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmsub_vv_f16m4_tu
// CHECK-RV64-SAME: (<vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmsub.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmsub.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
// //
vfloat16m4_t test_vfnmsub_vv_f16m4_tu(vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) { vfloat16m4_t test_vfnmsub_vv_f16m4_tu(vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfnmsub_vv_f16m4_tu(vd, vs1, vs2, vl); return __riscv_vfnmsub_vv_f16m4_tu(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmsub_vf_f16m4_tu // CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmsub_vf_f16m4_tu
// CHECK-RV64-SAME: (<vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmsub.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmsub.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
// //
vfloat16m4_t test_vfnmsub_vf_f16m4_tu(vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) { vfloat16m4_t test_vfnmsub_vf_f16m4_tu(vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfnmsub_vf_f16m4_tu(vd, rs1, vs2, vl); return __riscv_vfnmsub_vf_f16m4_tu(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmsub_vv_f16m8_tu // CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmsub_vv_f16m8_tu
// CHECK-RV64-SAME: (<vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmsub.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmsub.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
// //
vfloat16m8_t test_vfnmsub_vv_f16m8_tu(vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) { vfloat16m8_t test_vfnmsub_vv_f16m8_tu(vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfnmsub_vv_f16m8_tu(vd, vs1, vs2, vl); return __riscv_vfnmsub_vv_f16m8_tu(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmsub_vf_f16m8_tu // CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmsub_vf_f16m8_tu
// CHECK-RV64-SAME: (<vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmsub.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmsub.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
// //
vfloat16m8_t test_vfnmsub_vf_f16m8_tu(vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) { vfloat16m8_t test_vfnmsub_vf_f16m8_tu(vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfnmsub_vf_f16m8_tu(vd, rs1, vs2, vl); return __riscv_vfnmsub_vf_f16m8_tu(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmsub_vv_f32mf2_tu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmsub_vv_f32mf2_tu
// CHECK-RV64-SAME: (<vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmsub.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmsub.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfnmsub_vv_f32mf2_tu(vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) { vfloat32mf2_t test_vfnmsub_vv_f32mf2_tu(vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfnmsub_vv_f32mf2_tu(vd, vs1, vs2, vl); return __riscv_vfnmsub_vv_f32mf2_tu(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmsub_vf_f32mf2_tu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmsub_vf_f32mf2_tu
// CHECK-RV64-SAME: (<vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmsub.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmsub.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfnmsub_vf_f32mf2_tu(vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) { vfloat32mf2_t test_vfnmsub_vf_f32mf2_tu(vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfnmsub_vf_f32mf2_tu(vd, rs1, vs2, vl); return __riscv_vfnmsub_vf_f32mf2_tu(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmsub_vv_f32m1_tu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmsub_vv_f32m1_tu
// CHECK-RV64-SAME: (<vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmsub.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmsub.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfnmsub_vv_f32m1_tu(vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) { vfloat32m1_t test_vfnmsub_vv_f32m1_tu(vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfnmsub_vv_f32m1_tu(vd, vs1, vs2, vl); return __riscv_vfnmsub_vv_f32m1_tu(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmsub_vf_f32m1_tu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmsub_vf_f32m1_tu
// CHECK-RV64-SAME: (<vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmsub.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmsub.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfnmsub_vf_f32m1_tu(vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) { vfloat32m1_t test_vfnmsub_vf_f32m1_tu(vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfnmsub_vf_f32m1_tu(vd, rs1, vs2, vl); return __riscv_vfnmsub_vf_f32m1_tu(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmsub_vv_f32m2_tu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmsub_vv_f32m2_tu
// CHECK-RV64-SAME: (<vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmsub.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmsub.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfnmsub_vv_f32m2_tu(vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) { vfloat32m2_t test_vfnmsub_vv_f32m2_tu(vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfnmsub_vv_f32m2_tu(vd, vs1, vs2, vl); return __riscv_vfnmsub_vv_f32m2_tu(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmsub_vf_f32m2_tu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmsub_vf_f32m2_tu
// CHECK-RV64-SAME: (<vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmsub.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmsub.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfnmsub_vf_f32m2_tu(vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) { vfloat32m2_t test_vfnmsub_vf_f32m2_tu(vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfnmsub_vf_f32m2_tu(vd, rs1, vs2, vl); return __riscv_vfnmsub_vf_f32m2_tu(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmsub_vv_f32m4_tu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmsub_vv_f32m4_tu
// CHECK-RV64-SAME: (<vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmsub.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmsub.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfnmsub_vv_f32m4_tu(vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) { vfloat32m4_t test_vfnmsub_vv_f32m4_tu(vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfnmsub_vv_f32m4_tu(vd, vs1, vs2, vl); return __riscv_vfnmsub_vv_f32m4_tu(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmsub_vf_f32m4_tu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmsub_vf_f32m4_tu
// CHECK-RV64-SAME: (<vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmsub.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmsub.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfnmsub_vf_f32m4_tu(vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) { vfloat32m4_t test_vfnmsub_vf_f32m4_tu(vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfnmsub_vf_f32m4_tu(vd, rs1, vs2, vl); return __riscv_vfnmsub_vf_f32m4_tu(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmsub_vv_f32m8_tu // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmsub_vv_f32m8_tu
// CHECK-RV64-SAME: (<vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmsub.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmsub.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfnmsub_vv_f32m8_tu(vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) { vfloat32m8_t test_vfnmsub_vv_f32m8_tu(vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfnmsub_vv_f32m8_tu(vd, vs1, vs2, vl); return __riscv_vfnmsub_vv_f32m8_tu(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmsub_vf_f32m8_tu // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmsub_vf_f32m8_tu
// CHECK-RV64-SAME: (<vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmsub.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmsub.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfnmsub_vf_f32m8_tu(vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) { vfloat32m8_t test_vfnmsub_vf_f32m8_tu(vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfnmsub_vf_f32m8_tu(vd, rs1, vs2, vl); return __riscv_vfnmsub_vf_f32m8_tu(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmsub_vv_f64m1_tu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmsub_vv_f64m1_tu
// CHECK-RV64-SAME: (<vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmsub.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmsub.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfnmsub_vv_f64m1_tu(vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) { vfloat64m1_t test_vfnmsub_vv_f64m1_tu(vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfnmsub_vv_f64m1_tu(vd, vs1, vs2, vl); return __riscv_vfnmsub_vv_f64m1_tu(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmsub_vf_f64m1_tu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmsub_vf_f64m1_tu
// CHECK-RV64-SAME: (<vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmsub.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmsub.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfnmsub_vf_f64m1_tu(vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) { vfloat64m1_t test_vfnmsub_vf_f64m1_tu(vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfnmsub_vf_f64m1_tu(vd, rs1, vs2, vl); return __riscv_vfnmsub_vf_f64m1_tu(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmsub_vv_f64m2_tu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmsub_vv_f64m2_tu
// CHECK-RV64-SAME: (<vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmsub.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmsub.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfnmsub_vv_f64m2_tu(vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) { vfloat64m2_t test_vfnmsub_vv_f64m2_tu(vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfnmsub_vv_f64m2_tu(vd, vs1, vs2, vl); return __riscv_vfnmsub_vv_f64m2_tu(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmsub_vf_f64m2_tu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmsub_vf_f64m2_tu
// CHECK-RV64-SAME: (<vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmsub.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmsub.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfnmsub_vf_f64m2_tu(vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) { vfloat64m2_t test_vfnmsub_vf_f64m2_tu(vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfnmsub_vf_f64m2_tu(vd, rs1, vs2, vl); return __riscv_vfnmsub_vf_f64m2_tu(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmsub_vv_f64m4_tu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmsub_vv_f64m4_tu
// CHECK-RV64-SAME: (<vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmsub.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmsub.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfnmsub_vv_f64m4_tu(vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) { vfloat64m4_t test_vfnmsub_vv_f64m4_tu(vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfnmsub_vv_f64m4_tu(vd, vs1, vs2, vl); return __riscv_vfnmsub_vv_f64m4_tu(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmsub_vf_f64m4_tu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmsub_vf_f64m4_tu
// CHECK-RV64-SAME: (<vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmsub.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmsub.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfnmsub_vf_f64m4_tu(vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) { vfloat64m4_t test_vfnmsub_vf_f64m4_tu(vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfnmsub_vf_f64m4_tu(vd, rs1, vs2, vl); return __riscv_vfnmsub_vf_f64m4_tu(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmsub_vv_f64m8_tu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmsub_vv_f64m8_tu
// CHECK-RV64-SAME: (<vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmsub.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmsub.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfnmsub_vv_f64m8_tu(vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) { vfloat64m8_t test_vfnmsub_vv_f64m8_tu(vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfnmsub_vv_f64m8_tu(vd, vs1, vs2, vl); return __riscv_vfnmsub_vv_f64m8_tu(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmsub_vf_f64m8_tu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmsub_vf_f64m8_tu
// CHECK-RV64-SAME: (<vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmsub.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmsub.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfnmsub_vf_f64m8_tu(vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) { vfloat64m8_t test_vfnmsub_vf_f64m8_tu(vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfnmsub_vf_f64m8_tu(vd, rs1, vs2, vl); return __riscv_vfnmsub_vf_f64m8_tu(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmsub_vv_f16mf4_tum // CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmsub_vv_f16mf4_tum
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmsub.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmsub.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
// //
vfloat16mf4_t test_vfnmsub_vv_f16mf4_tum(vbool64_t mask, vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) { vfloat16mf4_t test_vfnmsub_vv_f16mf4_tum(vbool64_t mask, vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfnmsub_vv_f16mf4_tum(mask, vd, vs1, vs2, vl); return __riscv_vfnmsub_vv_f16mf4_tum(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmsub_vf_f16mf4_tum // CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmsub_vf_f16mf4_tum
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmsub.mask.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmsub.mask.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
// //
vfloat16mf4_t test_vfnmsub_vf_f16mf4_tum(vbool64_t mask, vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) { vfloat16mf4_t test_vfnmsub_vf_f16mf4_tum(vbool64_t mask, vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfnmsub_vf_f16mf4_tum(mask, vd, rs1, vs2, vl); return __riscv_vfnmsub_vf_f16mf4_tum(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmsub_vv_f16mf2_tum // CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmsub_vv_f16mf2_tum
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmsub.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmsub.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
// //
vfloat16mf2_t test_vfnmsub_vv_f16mf2_tum(vbool32_t mask, vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) { vfloat16mf2_t test_vfnmsub_vv_f16mf2_tum(vbool32_t mask, vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfnmsub_vv_f16mf2_tum(mask, vd, vs1, vs2, vl); return __riscv_vfnmsub_vv_f16mf2_tum(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmsub_vf_f16mf2_tum // CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmsub_vf_f16mf2_tum
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmsub.mask.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmsub.mask.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
// //
vfloat16mf2_t test_vfnmsub_vf_f16mf2_tum(vbool32_t mask, vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) { vfloat16mf2_t test_vfnmsub_vf_f16mf2_tum(vbool32_t mask, vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfnmsub_vf_f16mf2_tum(mask, vd, rs1, vs2, vl); return __riscv_vfnmsub_vf_f16mf2_tum(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmsub_vv_f16m1_tum // CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmsub_vv_f16m1_tum
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmsub.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmsub.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
// //
vfloat16m1_t test_vfnmsub_vv_f16m1_tum(vbool16_t mask, vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) { vfloat16m1_t test_vfnmsub_vv_f16m1_tum(vbool16_t mask, vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfnmsub_vv_f16m1_tum(mask, vd, vs1, vs2, vl); return __riscv_vfnmsub_vv_f16m1_tum(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmsub_vf_f16m1_tum // CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmsub_vf_f16m1_tum
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmsub.mask.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmsub.mask.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
// //
vfloat16m1_t test_vfnmsub_vf_f16m1_tum(vbool16_t mask, vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) { vfloat16m1_t test_vfnmsub_vf_f16m1_tum(vbool16_t mask, vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfnmsub_vf_f16m1_tum(mask, vd, rs1, vs2, vl); return __riscv_vfnmsub_vf_f16m1_tum(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmsub_vv_f16m2_tum // CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmsub_vv_f16m2_tum
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmsub.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmsub.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
// //
vfloat16m2_t test_vfnmsub_vv_f16m2_tum(vbool8_t mask, vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) { vfloat16m2_t test_vfnmsub_vv_f16m2_tum(vbool8_t mask, vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfnmsub_vv_f16m2_tum(mask, vd, vs1, vs2, vl); return __riscv_vfnmsub_vv_f16m2_tum(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmsub_vf_f16m2_tum // CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmsub_vf_f16m2_tum
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmsub.mask.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmsub.mask.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
// //
vfloat16m2_t test_vfnmsub_vf_f16m2_tum(vbool8_t mask, vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) { vfloat16m2_t test_vfnmsub_vf_f16m2_tum(vbool8_t mask, vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfnmsub_vf_f16m2_tum(mask, vd, rs1, vs2, vl); return __riscv_vfnmsub_vf_f16m2_tum(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmsub_vv_f16m4_tum // CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmsub_vv_f16m4_tum
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmsub.mask.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmsub.mask.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
// //
vfloat16m4_t test_vfnmsub_vv_f16m4_tum(vbool4_t mask, vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) { vfloat16m4_t test_vfnmsub_vv_f16m4_tum(vbool4_t mask, vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfnmsub_vv_f16m4_tum(mask, vd, vs1, vs2, vl); return __riscv_vfnmsub_vv_f16m4_tum(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmsub_vf_f16m4_tum // CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmsub_vf_f16m4_tum
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmsub.mask.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmsub.mask.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
// //
vfloat16m4_t test_vfnmsub_vf_f16m4_tum(vbool4_t mask, vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) { vfloat16m4_t test_vfnmsub_vf_f16m4_tum(vbool4_t mask, vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfnmsub_vf_f16m4_tum(mask, vd, rs1, vs2, vl); return __riscv_vfnmsub_vf_f16m4_tum(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmsub_vv_f16m8_tum // CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmsub_vv_f16m8_tum
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmsub.mask.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmsub.mask.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
// //
vfloat16m8_t test_vfnmsub_vv_f16m8_tum(vbool2_t mask, vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) { vfloat16m8_t test_vfnmsub_vv_f16m8_tum(vbool2_t mask, vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfnmsub_vv_f16m8_tum(mask, vd, vs1, vs2, vl); return __riscv_vfnmsub_vv_f16m8_tum(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmsub_vf_f16m8_tum // CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmsub_vf_f16m8_tum
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmsub.mask.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmsub.mask.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
// //
vfloat16m8_t test_vfnmsub_vf_f16m8_tum(vbool2_t mask, vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) { vfloat16m8_t test_vfnmsub_vf_f16m8_tum(vbool2_t mask, vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfnmsub_vf_f16m8_tum(mask, vd, rs1, vs2, vl); return __riscv_vfnmsub_vf_f16m8_tum(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmsub_vv_f32mf2_tum // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmsub_vv_f32mf2_tum
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmsub.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmsub.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfnmsub_vv_f32mf2_tum(vbool64_t mask, vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) { vfloat32mf2_t test_vfnmsub_vv_f32mf2_tum(vbool64_t mask, vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfnmsub_vv_f32mf2_tum(mask, vd, vs1, vs2, vl); return __riscv_vfnmsub_vv_f32mf2_tum(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmsub_vf_f32mf2_tum // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmsub_vf_f32mf2_tum
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmsub.mask.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmsub.mask.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfnmsub_vf_f32mf2_tum(vbool64_t mask, vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) { vfloat32mf2_t test_vfnmsub_vf_f32mf2_tum(vbool64_t mask, vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfnmsub_vf_f32mf2_tum(mask, vd, rs1, vs2, vl); return __riscv_vfnmsub_vf_f32mf2_tum(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmsub_vv_f32m1_tum // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmsub_vv_f32m1_tum
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmsub.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmsub.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfnmsub_vv_f32m1_tum(vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) { vfloat32m1_t test_vfnmsub_vv_f32m1_tum(vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfnmsub_vv_f32m1_tum(mask, vd, vs1, vs2, vl); return __riscv_vfnmsub_vv_f32m1_tum(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmsub_vf_f32m1_tum // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmsub_vf_f32m1_tum
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmsub.mask.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmsub.mask.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfnmsub_vf_f32m1_tum(vbool32_t mask, vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) { vfloat32m1_t test_vfnmsub_vf_f32m1_tum(vbool32_t mask, vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfnmsub_vf_f32m1_tum(mask, vd, rs1, vs2, vl); return __riscv_vfnmsub_vf_f32m1_tum(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmsub_vv_f32m2_tum // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmsub_vv_f32m2_tum
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmsub.mask.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmsub.mask.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfnmsub_vv_f32m2_tum(vbool16_t mask, vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) { vfloat32m2_t test_vfnmsub_vv_f32m2_tum(vbool16_t mask, vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfnmsub_vv_f32m2_tum(mask, vd, vs1, vs2, vl); return __riscv_vfnmsub_vv_f32m2_tum(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmsub_vf_f32m2_tum // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmsub_vf_f32m2_tum
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmsub.mask.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmsub.mask.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfnmsub_vf_f32m2_tum(vbool16_t mask, vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) { vfloat32m2_t test_vfnmsub_vf_f32m2_tum(vbool16_t mask, vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfnmsub_vf_f32m2_tum(mask, vd, rs1, vs2, vl); return __riscv_vfnmsub_vf_f32m2_tum(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmsub_vv_f32m4_tum // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmsub_vv_f32m4_tum
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmsub.mask.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmsub.mask.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfnmsub_vv_f32m4_tum(vbool8_t mask, vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) { vfloat32m4_t test_vfnmsub_vv_f32m4_tum(vbool8_t mask, vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfnmsub_vv_f32m4_tum(mask, vd, vs1, vs2, vl); return __riscv_vfnmsub_vv_f32m4_tum(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmsub_vf_f32m4_tum // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmsub_vf_f32m4_tum
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmsub.mask.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmsub.mask.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfnmsub_vf_f32m4_tum(vbool8_t mask, vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) { vfloat32m4_t test_vfnmsub_vf_f32m4_tum(vbool8_t mask, vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfnmsub_vf_f32m4_tum(mask, vd, rs1, vs2, vl); return __riscv_vfnmsub_vf_f32m4_tum(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmsub_vv_f32m8_tum // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmsub_vv_f32m8_tum
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmsub.mask.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmsub.mask.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfnmsub_vv_f32m8_tum(vbool4_t mask, vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) { vfloat32m8_t test_vfnmsub_vv_f32m8_tum(vbool4_t mask, vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfnmsub_vv_f32m8_tum(mask, vd, vs1, vs2, vl); return __riscv_vfnmsub_vv_f32m8_tum(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmsub_vf_f32m8_tum // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmsub_vf_f32m8_tum
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmsub.mask.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmsub.mask.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfnmsub_vf_f32m8_tum(vbool4_t mask, vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) { vfloat32m8_t test_vfnmsub_vf_f32m8_tum(vbool4_t mask, vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfnmsub_vf_f32m8_tum(mask, vd, rs1, vs2, vl); return __riscv_vfnmsub_vf_f32m8_tum(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmsub_vv_f64m1_tum // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmsub_vv_f64m1_tum
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmsub.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmsub.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfnmsub_vv_f64m1_tum(vbool64_t mask, vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) { vfloat64m1_t test_vfnmsub_vv_f64m1_tum(vbool64_t mask, vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfnmsub_vv_f64m1_tum(mask, vd, vs1, vs2, vl); return __riscv_vfnmsub_vv_f64m1_tum(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmsub_vf_f64m1_tum // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmsub_vf_f64m1_tum
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmsub.mask.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmsub.mask.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfnmsub_vf_f64m1_tum(vbool64_t mask, vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) { vfloat64m1_t test_vfnmsub_vf_f64m1_tum(vbool64_t mask, vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfnmsub_vf_f64m1_tum(mask, vd, rs1, vs2, vl); return __riscv_vfnmsub_vf_f64m1_tum(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmsub_vv_f64m2_tum // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmsub_vv_f64m2_tum
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmsub.mask.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmsub.mask.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfnmsub_vv_f64m2_tum(vbool32_t mask, vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) { vfloat64m2_t test_vfnmsub_vv_f64m2_tum(vbool32_t mask, vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfnmsub_vv_f64m2_tum(mask, vd, vs1, vs2, vl); return __riscv_vfnmsub_vv_f64m2_tum(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmsub_vf_f64m2_tum // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmsub_vf_f64m2_tum
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmsub.mask.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmsub.mask.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfnmsub_vf_f64m2_tum(vbool32_t mask, vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) { vfloat64m2_t test_vfnmsub_vf_f64m2_tum(vbool32_t mask, vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfnmsub_vf_f64m2_tum(mask, vd, rs1, vs2, vl); return __riscv_vfnmsub_vf_f64m2_tum(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmsub_vv_f64m4_tum // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmsub_vv_f64m4_tum
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmsub.mask.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmsub.mask.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfnmsub_vv_f64m4_tum(vbool16_t mask, vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) { vfloat64m4_t test_vfnmsub_vv_f64m4_tum(vbool16_t mask, vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfnmsub_vv_f64m4_tum(mask, vd, vs1, vs2, vl); return __riscv_vfnmsub_vv_f64m4_tum(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmsub_vf_f64m4_tum // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmsub_vf_f64m4_tum
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmsub.mask.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmsub.mask.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfnmsub_vf_f64m4_tum(vbool16_t mask, vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) { vfloat64m4_t test_vfnmsub_vf_f64m4_tum(vbool16_t mask, vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfnmsub_vf_f64m4_tum(mask, vd, rs1, vs2, vl); return __riscv_vfnmsub_vf_f64m4_tum(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmsub_vv_f64m8_tum // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmsub_vv_f64m8_tum
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmsub.mask.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmsub.mask.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfnmsub_vv_f64m8_tum(vbool8_t mask, vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) { vfloat64m8_t test_vfnmsub_vv_f64m8_tum(vbool8_t mask, vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfnmsub_vv_f64m8_tum(mask, vd, vs1, vs2, vl); return __riscv_vfnmsub_vv_f64m8_tum(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmsub_vf_f64m8_tum // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmsub_vf_f64m8_tum
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmsub.mask.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmsub.mask.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfnmsub_vf_f64m8_tum(vbool8_t mask, vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) { vfloat64m8_t test_vfnmsub_vf_f64m8_tum(vbool8_t mask, vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfnmsub_vf_f64m8_tum(mask, vd, rs1, vs2, vl); return __riscv_vfnmsub_vf_f64m8_tum(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmsub_vv_f16mf4_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmsub_vv_f16mf4_tumu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmsub.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmsub.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
// //
vfloat16mf4_t test_vfnmsub_vv_f16mf4_tumu(vbool64_t mask, vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) { vfloat16mf4_t test_vfnmsub_vv_f16mf4_tumu(vbool64_t mask, vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfnmsub_vv_f16mf4_tumu(mask, vd, vs1, vs2, vl); return __riscv_vfnmsub_vv_f16mf4_tumu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmsub_vf_f16mf4_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmsub_vf_f16mf4_tumu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmsub.mask.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmsub.mask.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
// //
vfloat16mf4_t test_vfnmsub_vf_f16mf4_tumu(vbool64_t mask, vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) { vfloat16mf4_t test_vfnmsub_vf_f16mf4_tumu(vbool64_t mask, vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfnmsub_vf_f16mf4_tumu(mask, vd, rs1, vs2, vl); return __riscv_vfnmsub_vf_f16mf4_tumu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmsub_vv_f16mf2_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmsub_vv_f16mf2_tumu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmsub.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmsub.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
// //
vfloat16mf2_t test_vfnmsub_vv_f16mf2_tumu(vbool32_t mask, vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) { vfloat16mf2_t test_vfnmsub_vv_f16mf2_tumu(vbool32_t mask, vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfnmsub_vv_f16mf2_tumu(mask, vd, vs1, vs2, vl); return __riscv_vfnmsub_vv_f16mf2_tumu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmsub_vf_f16mf2_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmsub_vf_f16mf2_tumu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmsub.mask.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmsub.mask.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
// //
vfloat16mf2_t test_vfnmsub_vf_f16mf2_tumu(vbool32_t mask, vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) { vfloat16mf2_t test_vfnmsub_vf_f16mf2_tumu(vbool32_t mask, vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfnmsub_vf_f16mf2_tumu(mask, vd, rs1, vs2, vl); return __riscv_vfnmsub_vf_f16mf2_tumu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmsub_vv_f16m1_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmsub_vv_f16m1_tumu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmsub.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmsub.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
// //
vfloat16m1_t test_vfnmsub_vv_f16m1_tumu(vbool16_t mask, vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) { vfloat16m1_t test_vfnmsub_vv_f16m1_tumu(vbool16_t mask, vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfnmsub_vv_f16m1_tumu(mask, vd, vs1, vs2, vl); return __riscv_vfnmsub_vv_f16m1_tumu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmsub_vf_f16m1_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmsub_vf_f16m1_tumu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmsub.mask.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmsub.mask.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
// //
vfloat16m1_t test_vfnmsub_vf_f16m1_tumu(vbool16_t mask, vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) { vfloat16m1_t test_vfnmsub_vf_f16m1_tumu(vbool16_t mask, vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfnmsub_vf_f16m1_tumu(mask, vd, rs1, vs2, vl); return __riscv_vfnmsub_vf_f16m1_tumu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmsub_vv_f16m2_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmsub_vv_f16m2_tumu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmsub.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmsub.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
// //
vfloat16m2_t test_vfnmsub_vv_f16m2_tumu(vbool8_t mask, vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) { vfloat16m2_t test_vfnmsub_vv_f16m2_tumu(vbool8_t mask, vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfnmsub_vv_f16m2_tumu(mask, vd, vs1, vs2, vl); return __riscv_vfnmsub_vv_f16m2_tumu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmsub_vf_f16m2_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmsub_vf_f16m2_tumu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmsub.mask.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmsub.mask.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
// //
vfloat16m2_t test_vfnmsub_vf_f16m2_tumu(vbool8_t mask, vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) { vfloat16m2_t test_vfnmsub_vf_f16m2_tumu(vbool8_t mask, vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfnmsub_vf_f16m2_tumu(mask, vd, rs1, vs2, vl); return __riscv_vfnmsub_vf_f16m2_tumu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmsub_vv_f16m4_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmsub_vv_f16m4_tumu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmsub.mask.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmsub.mask.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
// //
vfloat16m4_t test_vfnmsub_vv_f16m4_tumu(vbool4_t mask, vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) { vfloat16m4_t test_vfnmsub_vv_f16m4_tumu(vbool4_t mask, vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfnmsub_vv_f16m4_tumu(mask, vd, vs1, vs2, vl); return __riscv_vfnmsub_vv_f16m4_tumu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmsub_vf_f16m4_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmsub_vf_f16m4_tumu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmsub.mask.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmsub.mask.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
// //
vfloat16m4_t test_vfnmsub_vf_f16m4_tumu(vbool4_t mask, vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) { vfloat16m4_t test_vfnmsub_vf_f16m4_tumu(vbool4_t mask, vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfnmsub_vf_f16m4_tumu(mask, vd, rs1, vs2, vl); return __riscv_vfnmsub_vf_f16m4_tumu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmsub_vv_f16m8_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmsub_vv_f16m8_tumu
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmsub.mask.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmsub.mask.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
// //
vfloat16m8_t test_vfnmsub_vv_f16m8_tumu(vbool2_t mask, vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) { vfloat16m8_t test_vfnmsub_vv_f16m8_tumu(vbool2_t mask, vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfnmsub_vv_f16m8_tumu(mask, vd, vs1, vs2, vl); return __riscv_vfnmsub_vv_f16m8_tumu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmsub_vf_f16m8_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmsub_vf_f16m8_tumu
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmsub.mask.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmsub.mask.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
// //
vfloat16m8_t test_vfnmsub_vf_f16m8_tumu(vbool2_t mask, vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) { vfloat16m8_t test_vfnmsub_vf_f16m8_tumu(vbool2_t mask, vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfnmsub_vf_f16m8_tumu(mask, vd, rs1, vs2, vl); return __riscv_vfnmsub_vf_f16m8_tumu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmsub_vv_f32mf2_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmsub_vv_f32mf2_tumu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmsub.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmsub.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfnmsub_vv_f32mf2_tumu(vbool64_t mask, vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) { vfloat32mf2_t test_vfnmsub_vv_f32mf2_tumu(vbool64_t mask, vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfnmsub_vv_f32mf2_tumu(mask, vd, vs1, vs2, vl); return __riscv_vfnmsub_vv_f32mf2_tumu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmsub_vf_f32mf2_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmsub_vf_f32mf2_tumu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmsub.mask.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmsub.mask.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfnmsub_vf_f32mf2_tumu(vbool64_t mask, vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) { vfloat32mf2_t test_vfnmsub_vf_f32mf2_tumu(vbool64_t mask, vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfnmsub_vf_f32mf2_tumu(mask, vd, rs1, vs2, vl); return __riscv_vfnmsub_vf_f32mf2_tumu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmsub_vv_f32m1_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmsub_vv_f32m1_tumu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmsub.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmsub.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfnmsub_vv_f32m1_tumu(vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) { vfloat32m1_t test_vfnmsub_vv_f32m1_tumu(vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfnmsub_vv_f32m1_tumu(mask, vd, vs1, vs2, vl); return __riscv_vfnmsub_vv_f32m1_tumu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmsub_vf_f32m1_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmsub_vf_f32m1_tumu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmsub.mask.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmsub.mask.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfnmsub_vf_f32m1_tumu(vbool32_t mask, vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) { vfloat32m1_t test_vfnmsub_vf_f32m1_tumu(vbool32_t mask, vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfnmsub_vf_f32m1_tumu(mask, vd, rs1, vs2, vl); return __riscv_vfnmsub_vf_f32m1_tumu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmsub_vv_f32m2_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmsub_vv_f32m2_tumu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmsub.mask.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmsub.mask.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfnmsub_vv_f32m2_tumu(vbool16_t mask, vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) { vfloat32m2_t test_vfnmsub_vv_f32m2_tumu(vbool16_t mask, vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfnmsub_vv_f32m2_tumu(mask, vd, vs1, vs2, vl); return __riscv_vfnmsub_vv_f32m2_tumu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmsub_vf_f32m2_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmsub_vf_f32m2_tumu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmsub.mask.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmsub.mask.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfnmsub_vf_f32m2_tumu(vbool16_t mask, vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) { vfloat32m2_t test_vfnmsub_vf_f32m2_tumu(vbool16_t mask, vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfnmsub_vf_f32m2_tumu(mask, vd, rs1, vs2, vl); return __riscv_vfnmsub_vf_f32m2_tumu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmsub_vv_f32m4_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmsub_vv_f32m4_tumu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmsub.mask.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmsub.mask.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfnmsub_vv_f32m4_tumu(vbool8_t mask, vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) { vfloat32m4_t test_vfnmsub_vv_f32m4_tumu(vbool8_t mask, vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfnmsub_vv_f32m4_tumu(mask, vd, vs1, vs2, vl); return __riscv_vfnmsub_vv_f32m4_tumu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmsub_vf_f32m4_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmsub_vf_f32m4_tumu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmsub.mask.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmsub.mask.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfnmsub_vf_f32m4_tumu(vbool8_t mask, vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) { vfloat32m4_t test_vfnmsub_vf_f32m4_tumu(vbool8_t mask, vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfnmsub_vf_f32m4_tumu(mask, vd, rs1, vs2, vl); return __riscv_vfnmsub_vf_f32m4_tumu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmsub_vv_f32m8_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmsub_vv_f32m8_tumu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmsub.mask.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmsub.mask.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfnmsub_vv_f32m8_tumu(vbool4_t mask, vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) { vfloat32m8_t test_vfnmsub_vv_f32m8_tumu(vbool4_t mask, vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfnmsub_vv_f32m8_tumu(mask, vd, vs1, vs2, vl); return __riscv_vfnmsub_vv_f32m8_tumu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmsub_vf_f32m8_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmsub_vf_f32m8_tumu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmsub.mask.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmsub.mask.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfnmsub_vf_f32m8_tumu(vbool4_t mask, vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) { vfloat32m8_t test_vfnmsub_vf_f32m8_tumu(vbool4_t mask, vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfnmsub_vf_f32m8_tumu(mask, vd, rs1, vs2, vl); return __riscv_vfnmsub_vf_f32m8_tumu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmsub_vv_f64m1_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmsub_vv_f64m1_tumu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmsub.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmsub.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfnmsub_vv_f64m1_tumu(vbool64_t mask, vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) { vfloat64m1_t test_vfnmsub_vv_f64m1_tumu(vbool64_t mask, vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfnmsub_vv_f64m1_tumu(mask, vd, vs1, vs2, vl); return __riscv_vfnmsub_vv_f64m1_tumu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmsub_vf_f64m1_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmsub_vf_f64m1_tumu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmsub.mask.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmsub.mask.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfnmsub_vf_f64m1_tumu(vbool64_t mask, vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) { vfloat64m1_t test_vfnmsub_vf_f64m1_tumu(vbool64_t mask, vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfnmsub_vf_f64m1_tumu(mask, vd, rs1, vs2, vl); return __riscv_vfnmsub_vf_f64m1_tumu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmsub_vv_f64m2_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmsub_vv_f64m2_tumu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmsub.mask.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmsub.mask.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfnmsub_vv_f64m2_tumu(vbool32_t mask, vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) { vfloat64m2_t test_vfnmsub_vv_f64m2_tumu(vbool32_t mask, vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfnmsub_vv_f64m2_tumu(mask, vd, vs1, vs2, vl); return __riscv_vfnmsub_vv_f64m2_tumu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmsub_vf_f64m2_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmsub_vf_f64m2_tumu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmsub.mask.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmsub.mask.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfnmsub_vf_f64m2_tumu(vbool32_t mask, vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) { vfloat64m2_t test_vfnmsub_vf_f64m2_tumu(vbool32_t mask, vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfnmsub_vf_f64m2_tumu(mask, vd, rs1, vs2, vl); return __riscv_vfnmsub_vf_f64m2_tumu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmsub_vv_f64m4_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmsub_vv_f64m4_tumu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmsub.mask.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmsub.mask.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfnmsub_vv_f64m4_tumu(vbool16_t mask, vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) { vfloat64m4_t test_vfnmsub_vv_f64m4_tumu(vbool16_t mask, vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfnmsub_vv_f64m4_tumu(mask, vd, vs1, vs2, vl); return __riscv_vfnmsub_vv_f64m4_tumu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmsub_vf_f64m4_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmsub_vf_f64m4_tumu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmsub.mask.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmsub.mask.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfnmsub_vf_f64m4_tumu(vbool16_t mask, vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) { vfloat64m4_t test_vfnmsub_vf_f64m4_tumu(vbool16_t mask, vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfnmsub_vf_f64m4_tumu(mask, vd, rs1, vs2, vl); return __riscv_vfnmsub_vf_f64m4_tumu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmsub_vv_f64m8_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmsub_vv_f64m8_tumu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmsub.mask.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmsub.mask.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfnmsub_vv_f64m8_tumu(vbool8_t mask, vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) { vfloat64m8_t test_vfnmsub_vv_f64m8_tumu(vbool8_t mask, vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfnmsub_vv_f64m8_tumu(mask, vd, vs1, vs2, vl); return __riscv_vfnmsub_vv_f64m8_tumu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmsub_vf_f64m8_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmsub_vf_f64m8_tumu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmsub.mask.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmsub.mask.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfnmsub_vf_f64m8_tumu(vbool8_t mask, vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) { vfloat64m8_t test_vfnmsub_vf_f64m8_tumu(vbool8_t mask, vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfnmsub_vf_f64m8_tumu(mask, vd, rs1, vs2, vl); return __riscv_vfnmsub_vf_f64m8_tumu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmsub_vv_f16mf4_mu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmsub_vv_f16mf4_mu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmsub.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmsub.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
// //
vfloat16mf4_t test_vfnmsub_vv_f16mf4_mu(vbool64_t mask, vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) { vfloat16mf4_t test_vfnmsub_vv_f16mf4_mu(vbool64_t mask, vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfnmsub_vv_f16mf4_mu(mask, vd, vs1, vs2, vl); return __riscv_vfnmsub_vv_f16mf4_mu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmsub_vf_f16mf4_mu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmsub_vf_f16mf4_mu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmsub.mask.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmsub.mask.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
// //
vfloat16mf4_t test_vfnmsub_vf_f16mf4_mu(vbool64_t mask, vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) { vfloat16mf4_t test_vfnmsub_vf_f16mf4_mu(vbool64_t mask, vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfnmsub_vf_f16mf4_mu(mask, vd, rs1, vs2, vl); return __riscv_vfnmsub_vf_f16mf4_mu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmsub_vv_f16mf2_mu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmsub_vv_f16mf2_mu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmsub.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmsub.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
// //
vfloat16mf2_t test_vfnmsub_vv_f16mf2_mu(vbool32_t mask, vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) { vfloat16mf2_t test_vfnmsub_vv_f16mf2_mu(vbool32_t mask, vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfnmsub_vv_f16mf2_mu(mask, vd, vs1, vs2, vl); return __riscv_vfnmsub_vv_f16mf2_mu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmsub_vf_f16mf2_mu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmsub_vf_f16mf2_mu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmsub.mask.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmsub.mask.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
// //
vfloat16mf2_t test_vfnmsub_vf_f16mf2_mu(vbool32_t mask, vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) { vfloat16mf2_t test_vfnmsub_vf_f16mf2_mu(vbool32_t mask, vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfnmsub_vf_f16mf2_mu(mask, vd, rs1, vs2, vl); return __riscv_vfnmsub_vf_f16mf2_mu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmsub_vv_f16m1_mu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmsub_vv_f16m1_mu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmsub.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmsub.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
// //
vfloat16m1_t test_vfnmsub_vv_f16m1_mu(vbool16_t mask, vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) { vfloat16m1_t test_vfnmsub_vv_f16m1_mu(vbool16_t mask, vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfnmsub_vv_f16m1_mu(mask, vd, vs1, vs2, vl); return __riscv_vfnmsub_vv_f16m1_mu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmsub_vf_f16m1_mu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmsub_vf_f16m1_mu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmsub.mask.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmsub.mask.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
// //
vfloat16m1_t test_vfnmsub_vf_f16m1_mu(vbool16_t mask, vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) { vfloat16m1_t test_vfnmsub_vf_f16m1_mu(vbool16_t mask, vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfnmsub_vf_f16m1_mu(mask, vd, rs1, vs2, vl); return __riscv_vfnmsub_vf_f16m1_mu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmsub_vv_f16m2_mu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmsub_vv_f16m2_mu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmsub.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmsub.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
// //
vfloat16m2_t test_vfnmsub_vv_f16m2_mu(vbool8_t mask, vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) { vfloat16m2_t test_vfnmsub_vv_f16m2_mu(vbool8_t mask, vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfnmsub_vv_f16m2_mu(mask, vd, vs1, vs2, vl); return __riscv_vfnmsub_vv_f16m2_mu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmsub_vf_f16m2_mu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmsub_vf_f16m2_mu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmsub.mask.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmsub.mask.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
// //
vfloat16m2_t test_vfnmsub_vf_f16m2_mu(vbool8_t mask, vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) { vfloat16m2_t test_vfnmsub_vf_f16m2_mu(vbool8_t mask, vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfnmsub_vf_f16m2_mu(mask, vd, rs1, vs2, vl); return __riscv_vfnmsub_vf_f16m2_mu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmsub_vv_f16m4_mu // CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmsub_vv_f16m4_mu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmsub.mask.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmsub.mask.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
// //
vfloat16m4_t test_vfnmsub_vv_f16m4_mu(vbool4_t mask, vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) { vfloat16m4_t test_vfnmsub_vv_f16m4_mu(vbool4_t mask, vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfnmsub_vv_f16m4_mu(mask, vd, vs1, vs2, vl); return __riscv_vfnmsub_vv_f16m4_mu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmsub_vf_f16m4_mu // CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmsub_vf_f16m4_mu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmsub.mask.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmsub.mask.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
// //
vfloat16m4_t test_vfnmsub_vf_f16m4_mu(vbool4_t mask, vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) { vfloat16m4_t test_vfnmsub_vf_f16m4_mu(vbool4_t mask, vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfnmsub_vf_f16m4_mu(mask, vd, rs1, vs2, vl); return __riscv_vfnmsub_vf_f16m4_mu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmsub_vv_f16m8_mu // CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmsub_vv_f16m8_mu
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmsub.mask.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmsub.mask.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
// //
vfloat16m8_t test_vfnmsub_vv_f16m8_mu(vbool2_t mask, vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) { vfloat16m8_t test_vfnmsub_vv_f16m8_mu(vbool2_t mask, vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfnmsub_vv_f16m8_mu(mask, vd, vs1, vs2, vl); return __riscv_vfnmsub_vv_f16m8_mu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmsub_vf_f16m8_mu // CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmsub_vf_f16m8_mu
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmsub.mask.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmsub.mask.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
// //
vfloat16m8_t test_vfnmsub_vf_f16m8_mu(vbool2_t mask, vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) { vfloat16m8_t test_vfnmsub_vf_f16m8_mu(vbool2_t mask, vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfnmsub_vf_f16m8_mu(mask, vd, rs1, vs2, vl); return __riscv_vfnmsub_vf_f16m8_mu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmsub_vv_f32mf2_mu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmsub_vv_f32mf2_mu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmsub.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmsub.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfnmsub_vv_f32mf2_mu(vbool64_t mask, vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) { vfloat32mf2_t test_vfnmsub_vv_f32mf2_mu(vbool64_t mask, vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfnmsub_vv_f32mf2_mu(mask, vd, vs1, vs2, vl); return __riscv_vfnmsub_vv_f32mf2_mu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmsub_vf_f32mf2_mu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmsub_vf_f32mf2_mu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmsub.mask.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmsub.mask.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfnmsub_vf_f32mf2_mu(vbool64_t mask, vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) { vfloat32mf2_t test_vfnmsub_vf_f32mf2_mu(vbool64_t mask, vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfnmsub_vf_f32mf2_mu(mask, vd, rs1, vs2, vl); return __riscv_vfnmsub_vf_f32mf2_mu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmsub_vv_f32m1_mu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmsub_vv_f32m1_mu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmsub.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmsub.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfnmsub_vv_f32m1_mu(vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) { vfloat32m1_t test_vfnmsub_vv_f32m1_mu(vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfnmsub_vv_f32m1_mu(mask, vd, vs1, vs2, vl); return __riscv_vfnmsub_vv_f32m1_mu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmsub_vf_f32m1_mu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmsub_vf_f32m1_mu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmsub.mask.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmsub.mask.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfnmsub_vf_f32m1_mu(vbool32_t mask, vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) { vfloat32m1_t test_vfnmsub_vf_f32m1_mu(vbool32_t mask, vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfnmsub_vf_f32m1_mu(mask, vd, rs1, vs2, vl); return __riscv_vfnmsub_vf_f32m1_mu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmsub_vv_f32m2_mu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmsub_vv_f32m2_mu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmsub.mask.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmsub.mask.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfnmsub_vv_f32m2_mu(vbool16_t mask, vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) { vfloat32m2_t test_vfnmsub_vv_f32m2_mu(vbool16_t mask, vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfnmsub_vv_f32m2_mu(mask, vd, vs1, vs2, vl); return __riscv_vfnmsub_vv_f32m2_mu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmsub_vf_f32m2_mu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmsub_vf_f32m2_mu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmsub.mask.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmsub.mask.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfnmsub_vf_f32m2_mu(vbool16_t mask, vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) { vfloat32m2_t test_vfnmsub_vf_f32m2_mu(vbool16_t mask, vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfnmsub_vf_f32m2_mu(mask, vd, rs1, vs2, vl); return __riscv_vfnmsub_vf_f32m2_mu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmsub_vv_f32m4_mu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmsub_vv_f32m4_mu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmsub.mask.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmsub.mask.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfnmsub_vv_f32m4_mu(vbool8_t mask, vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) { vfloat32m4_t test_vfnmsub_vv_f32m4_mu(vbool8_t mask, vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfnmsub_vv_f32m4_mu(mask, vd, vs1, vs2, vl); return __riscv_vfnmsub_vv_f32m4_mu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmsub_vf_f32m4_mu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmsub_vf_f32m4_mu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmsub.mask.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmsub.mask.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfnmsub_vf_f32m4_mu(vbool8_t mask, vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) { vfloat32m4_t test_vfnmsub_vf_f32m4_mu(vbool8_t mask, vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfnmsub_vf_f32m4_mu(mask, vd, rs1, vs2, vl); return __riscv_vfnmsub_vf_f32m4_mu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmsub_vv_f32m8_mu // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmsub_vv_f32m8_mu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmsub.mask.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmsub.mask.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfnmsub_vv_f32m8_mu(vbool4_t mask, vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) { vfloat32m8_t test_vfnmsub_vv_f32m8_mu(vbool4_t mask, vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfnmsub_vv_f32m8_mu(mask, vd, vs1, vs2, vl); return __riscv_vfnmsub_vv_f32m8_mu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmsub_vf_f32m8_mu // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmsub_vf_f32m8_mu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmsub.mask.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmsub.mask.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfnmsub_vf_f32m8_mu(vbool4_t mask, vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) { vfloat32m8_t test_vfnmsub_vf_f32m8_mu(vbool4_t mask, vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfnmsub_vf_f32m8_mu(mask, vd, rs1, vs2, vl); return __riscv_vfnmsub_vf_f32m8_mu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmsub_vv_f64m1_mu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmsub_vv_f64m1_mu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmsub.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmsub.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfnmsub_vv_f64m1_mu(vbool64_t mask, vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) { vfloat64m1_t test_vfnmsub_vv_f64m1_mu(vbool64_t mask, vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfnmsub_vv_f64m1_mu(mask, vd, vs1, vs2, vl); return __riscv_vfnmsub_vv_f64m1_mu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmsub_vf_f64m1_mu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmsub_vf_f64m1_mu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmsub.mask.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmsub.mask.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfnmsub_vf_f64m1_mu(vbool64_t mask, vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) { vfloat64m1_t test_vfnmsub_vf_f64m1_mu(vbool64_t mask, vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfnmsub_vf_f64m1_mu(mask, vd, rs1, vs2, vl); return __riscv_vfnmsub_vf_f64m1_mu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmsub_vv_f64m2_mu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmsub_vv_f64m2_mu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmsub.mask.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmsub.mask.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfnmsub_vv_f64m2_mu(vbool32_t mask, vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) { vfloat64m2_t test_vfnmsub_vv_f64m2_mu(vbool32_t mask, vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfnmsub_vv_f64m2_mu(mask, vd, vs1, vs2, vl); return __riscv_vfnmsub_vv_f64m2_mu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmsub_vf_f64m2_mu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmsub_vf_f64m2_mu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmsub.mask.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmsub.mask.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfnmsub_vf_f64m2_mu(vbool32_t mask, vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) { vfloat64m2_t test_vfnmsub_vf_f64m2_mu(vbool32_t mask, vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfnmsub_vf_f64m2_mu(mask, vd, rs1, vs2, vl); return __riscv_vfnmsub_vf_f64m2_mu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmsub_vv_f64m4_mu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmsub_vv_f64m4_mu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmsub.mask.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmsub.mask.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfnmsub_vv_f64m4_mu(vbool16_t mask, vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) { vfloat64m4_t test_vfnmsub_vv_f64m4_mu(vbool16_t mask, vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfnmsub_vv_f64m4_mu(mask, vd, vs1, vs2, vl); return __riscv_vfnmsub_vv_f64m4_mu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmsub_vf_f64m4_mu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmsub_vf_f64m4_mu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmsub.mask.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmsub.mask.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfnmsub_vf_f64m4_mu(vbool16_t mask, vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) { vfloat64m4_t test_vfnmsub_vf_f64m4_mu(vbool16_t mask, vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfnmsub_vf_f64m4_mu(mask, vd, rs1, vs2, vl); return __riscv_vfnmsub_vf_f64m4_mu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmsub_vv_f64m8_mu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmsub_vv_f64m8_mu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmsub.mask.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmsub.mask.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfnmsub_vv_f64m8_mu(vbool8_t mask, vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) { vfloat64m8_t test_vfnmsub_vv_f64m8_mu(vbool8_t mask, vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfnmsub_vv_f64m8_mu(mask, vd, vs1, vs2, vl); return __riscv_vfnmsub_vv_f64m8_mu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmsub_vf_f64m8_mu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmsub_vf_f64m8_mu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmsub.mask.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmsub.mask.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfnmsub_vf_f64m8_mu(vbool8_t mask, vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) { vfloat64m8_t test_vfnmsub_vf_f64m8_mu(vbool8_t mask, vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfnmsub_vf_f64m8_mu(mask, vd, rs1, vs2, vl); return __riscv_vfnmsub_vf_f64m8_mu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmsub_vv_f16mf4_rm_tu
// CHECK-RV64-SAME: (<vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmsub.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
//
vfloat16mf4_t test_vfnmsub_vv_f16mf4_rm_tu(vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfnmsub_vv_f16mf4_rm_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmsub_vf_f16mf4_rm_tu
// CHECK-RV64-SAME: (<vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmsub.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
//
vfloat16mf4_t test_vfnmsub_vf_f16mf4_rm_tu(vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfnmsub_vf_f16mf4_rm_tu(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmsub_vv_f16mf2_rm_tu
// CHECK-RV64-SAME: (<vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmsub.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
//
vfloat16mf2_t test_vfnmsub_vv_f16mf2_rm_tu(vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfnmsub_vv_f16mf2_rm_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmsub_vf_f16mf2_rm_tu
// CHECK-RV64-SAME: (<vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmsub.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
//
vfloat16mf2_t test_vfnmsub_vf_f16mf2_rm_tu(vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfnmsub_vf_f16mf2_rm_tu(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmsub_vv_f16m1_rm_tu
// CHECK-RV64-SAME: (<vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmsub.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfnmsub_vv_f16m1_rm_tu(vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfnmsub_vv_f16m1_rm_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmsub_vf_f16m1_rm_tu
// CHECK-RV64-SAME: (<vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmsub.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfnmsub_vf_f16m1_rm_tu(vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfnmsub_vf_f16m1_rm_tu(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmsub_vv_f16m2_rm_tu
// CHECK-RV64-SAME: (<vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmsub.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
//
vfloat16m2_t test_vfnmsub_vv_f16m2_rm_tu(vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfnmsub_vv_f16m2_rm_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmsub_vf_f16m2_rm_tu
// CHECK-RV64-SAME: (<vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmsub.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
//
vfloat16m2_t test_vfnmsub_vf_f16m2_rm_tu(vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfnmsub_vf_f16m2_rm_tu(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmsub_vv_f16m4_rm_tu
// CHECK-RV64-SAME: (<vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmsub.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
//
vfloat16m4_t test_vfnmsub_vv_f16m4_rm_tu(vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfnmsub_vv_f16m4_rm_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmsub_vf_f16m4_rm_tu
// CHECK-RV64-SAME: (<vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmsub.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
//
vfloat16m4_t test_vfnmsub_vf_f16m4_rm_tu(vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfnmsub_vf_f16m4_rm_tu(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmsub_vv_f16m8_rm_tu
// CHECK-RV64-SAME: (<vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmsub.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
//
vfloat16m8_t test_vfnmsub_vv_f16m8_rm_tu(vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfnmsub_vv_f16m8_rm_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmsub_vf_f16m8_rm_tu
// CHECK-RV64-SAME: (<vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmsub.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
//
vfloat16m8_t test_vfnmsub_vf_f16m8_rm_tu(vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfnmsub_vf_f16m8_rm_tu(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmsub_vv_f32mf2_rm_tu
// CHECK-RV64-SAME: (<vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmsub.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
//
vfloat32mf2_t test_vfnmsub_vv_f32mf2_rm_tu(vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfnmsub_vv_f32mf2_rm_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmsub_vf_f32mf2_rm_tu
// CHECK-RV64-SAME: (<vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmsub.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
//
vfloat32mf2_t test_vfnmsub_vf_f32mf2_rm_tu(vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfnmsub_vf_f32mf2_rm_tu(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmsub_vv_f32m1_rm_tu
// CHECK-RV64-SAME: (<vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmsub.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfnmsub_vv_f32m1_rm_tu(vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfnmsub_vv_f32m1_rm_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmsub_vf_f32m1_rm_tu
// CHECK-RV64-SAME: (<vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmsub.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfnmsub_vf_f32m1_rm_tu(vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfnmsub_vf_f32m1_rm_tu(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmsub_vv_f32m2_rm_tu
// CHECK-RV64-SAME: (<vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmsub.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
//
vfloat32m2_t test_vfnmsub_vv_f32m2_rm_tu(vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfnmsub_vv_f32m2_rm_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmsub_vf_f32m2_rm_tu
// CHECK-RV64-SAME: (<vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmsub.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
//
vfloat32m2_t test_vfnmsub_vf_f32m2_rm_tu(vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfnmsub_vf_f32m2_rm_tu(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmsub_vv_f32m4_rm_tu
// CHECK-RV64-SAME: (<vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmsub.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
//
vfloat32m4_t test_vfnmsub_vv_f32m4_rm_tu(vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfnmsub_vv_f32m4_rm_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmsub_vf_f32m4_rm_tu
// CHECK-RV64-SAME: (<vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmsub.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
//
vfloat32m4_t test_vfnmsub_vf_f32m4_rm_tu(vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfnmsub_vf_f32m4_rm_tu(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmsub_vv_f32m8_rm_tu
// CHECK-RV64-SAME: (<vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmsub.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
//
vfloat32m8_t test_vfnmsub_vv_f32m8_rm_tu(vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfnmsub_vv_f32m8_rm_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmsub_vf_f32m8_rm_tu
// CHECK-RV64-SAME: (<vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmsub.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
//
vfloat32m8_t test_vfnmsub_vf_f32m8_rm_tu(vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfnmsub_vf_f32m8_rm_tu(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmsub_vv_f64m1_rm_tu
// CHECK-RV64-SAME: (<vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmsub.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfnmsub_vv_f64m1_rm_tu(vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfnmsub_vv_f64m1_rm_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmsub_vf_f64m1_rm_tu
// CHECK-RV64-SAME: (<vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmsub.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfnmsub_vf_f64m1_rm_tu(vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfnmsub_vf_f64m1_rm_tu(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmsub_vv_f64m2_rm_tu
// CHECK-RV64-SAME: (<vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmsub.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
//
vfloat64m2_t test_vfnmsub_vv_f64m2_rm_tu(vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfnmsub_vv_f64m2_rm_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmsub_vf_f64m2_rm_tu
// CHECK-RV64-SAME: (<vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmsub.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
//
vfloat64m2_t test_vfnmsub_vf_f64m2_rm_tu(vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfnmsub_vf_f64m2_rm_tu(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmsub_vv_f64m4_rm_tu
// CHECK-RV64-SAME: (<vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmsub.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
//
vfloat64m4_t test_vfnmsub_vv_f64m4_rm_tu(vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfnmsub_vv_f64m4_rm_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmsub_vf_f64m4_rm_tu
// CHECK-RV64-SAME: (<vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmsub.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
//
vfloat64m4_t test_vfnmsub_vf_f64m4_rm_tu(vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfnmsub_vf_f64m4_rm_tu(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmsub_vv_f64m8_rm_tu
// CHECK-RV64-SAME: (<vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmsub.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
//
vfloat64m8_t test_vfnmsub_vv_f64m8_rm_tu(vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfnmsub_vv_f64m8_rm_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmsub_vf_f64m8_rm_tu
// CHECK-RV64-SAME: (<vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmsub.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
//
vfloat64m8_t test_vfnmsub_vf_f64m8_rm_tu(vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfnmsub_vf_f64m8_rm_tu(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmsub_vv_f16mf4_rm_tum
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmsub.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
//
vfloat16mf4_t test_vfnmsub_vv_f16mf4_rm_tum(vbool64_t mask, vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfnmsub_vv_f16mf4_rm_tum(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmsub_vf_f16mf4_rm_tum
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmsub.mask.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
//
vfloat16mf4_t test_vfnmsub_vf_f16mf4_rm_tum(vbool64_t mask, vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfnmsub_vf_f16mf4_rm_tum(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmsub_vv_f16mf2_rm_tum
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmsub.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
//
vfloat16mf2_t test_vfnmsub_vv_f16mf2_rm_tum(vbool32_t mask, vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfnmsub_vv_f16mf2_rm_tum(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmsub_vf_f16mf2_rm_tum
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmsub.mask.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
//
vfloat16mf2_t test_vfnmsub_vf_f16mf2_rm_tum(vbool32_t mask, vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfnmsub_vf_f16mf2_rm_tum(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmsub_vv_f16m1_rm_tum
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmsub.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfnmsub_vv_f16m1_rm_tum(vbool16_t mask, vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfnmsub_vv_f16m1_rm_tum(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmsub_vf_f16m1_rm_tum
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmsub.mask.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfnmsub_vf_f16m1_rm_tum(vbool16_t mask, vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfnmsub_vf_f16m1_rm_tum(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmsub_vv_f16m2_rm_tum
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmsub.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
//
vfloat16m2_t test_vfnmsub_vv_f16m2_rm_tum(vbool8_t mask, vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfnmsub_vv_f16m2_rm_tum(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmsub_vf_f16m2_rm_tum
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmsub.mask.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
//
vfloat16m2_t test_vfnmsub_vf_f16m2_rm_tum(vbool8_t mask, vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfnmsub_vf_f16m2_rm_tum(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmsub_vv_f16m4_rm_tum
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmsub.mask.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
//
vfloat16m4_t test_vfnmsub_vv_f16m4_rm_tum(vbool4_t mask, vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfnmsub_vv_f16m4_rm_tum(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmsub_vf_f16m4_rm_tum
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmsub.mask.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
//
vfloat16m4_t test_vfnmsub_vf_f16m4_rm_tum(vbool4_t mask, vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfnmsub_vf_f16m4_rm_tum(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmsub_vv_f16m8_rm_tum
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmsub.mask.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
//
vfloat16m8_t test_vfnmsub_vv_f16m8_rm_tum(vbool2_t mask, vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfnmsub_vv_f16m8_rm_tum(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmsub_vf_f16m8_rm_tum
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmsub.mask.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
//
vfloat16m8_t test_vfnmsub_vf_f16m8_rm_tum(vbool2_t mask, vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfnmsub_vf_f16m8_rm_tum(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmsub_vv_f32mf2_rm_tum
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmsub.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
//
vfloat32mf2_t test_vfnmsub_vv_f32mf2_rm_tum(vbool64_t mask, vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfnmsub_vv_f32mf2_rm_tum(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmsub_vf_f32mf2_rm_tum
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmsub.mask.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
//
vfloat32mf2_t test_vfnmsub_vf_f32mf2_rm_tum(vbool64_t mask, vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfnmsub_vf_f32mf2_rm_tum(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmsub_vv_f32m1_rm_tum
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmsub.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfnmsub_vv_f32m1_rm_tum(vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfnmsub_vv_f32m1_rm_tum(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmsub_vf_f32m1_rm_tum
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmsub.mask.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfnmsub_vf_f32m1_rm_tum(vbool32_t mask, vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfnmsub_vf_f32m1_rm_tum(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmsub_vv_f32m2_rm_tum
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmsub.mask.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
//
vfloat32m2_t test_vfnmsub_vv_f32m2_rm_tum(vbool16_t mask, vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfnmsub_vv_f32m2_rm_tum(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmsub_vf_f32m2_rm_tum
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmsub.mask.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
//
vfloat32m2_t test_vfnmsub_vf_f32m2_rm_tum(vbool16_t mask, vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfnmsub_vf_f32m2_rm_tum(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmsub_vv_f32m4_rm_tum
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmsub.mask.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
//
vfloat32m4_t test_vfnmsub_vv_f32m4_rm_tum(vbool8_t mask, vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfnmsub_vv_f32m4_rm_tum(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmsub_vf_f32m4_rm_tum
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmsub.mask.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
//
vfloat32m4_t test_vfnmsub_vf_f32m4_rm_tum(vbool8_t mask, vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfnmsub_vf_f32m4_rm_tum(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmsub_vv_f32m8_rm_tum
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmsub.mask.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
//
vfloat32m8_t test_vfnmsub_vv_f32m8_rm_tum(vbool4_t mask, vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfnmsub_vv_f32m8_rm_tum(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmsub_vf_f32m8_rm_tum
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmsub.mask.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
//
vfloat32m8_t test_vfnmsub_vf_f32m8_rm_tum(vbool4_t mask, vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfnmsub_vf_f32m8_rm_tum(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmsub_vv_f64m1_rm_tum
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmsub.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfnmsub_vv_f64m1_rm_tum(vbool64_t mask, vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfnmsub_vv_f64m1_rm_tum(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmsub_vf_f64m1_rm_tum
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmsub.mask.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfnmsub_vf_f64m1_rm_tum(vbool64_t mask, vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfnmsub_vf_f64m1_rm_tum(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmsub_vv_f64m2_rm_tum
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmsub.mask.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
//
vfloat64m2_t test_vfnmsub_vv_f64m2_rm_tum(vbool32_t mask, vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfnmsub_vv_f64m2_rm_tum(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmsub_vf_f64m2_rm_tum
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmsub.mask.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
//
vfloat64m2_t test_vfnmsub_vf_f64m2_rm_tum(vbool32_t mask, vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfnmsub_vf_f64m2_rm_tum(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmsub_vv_f64m4_rm_tum
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmsub.mask.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
//
vfloat64m4_t test_vfnmsub_vv_f64m4_rm_tum(vbool16_t mask, vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfnmsub_vv_f64m4_rm_tum(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmsub_vf_f64m4_rm_tum
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmsub.mask.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
//
vfloat64m4_t test_vfnmsub_vf_f64m4_rm_tum(vbool16_t mask, vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfnmsub_vf_f64m4_rm_tum(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmsub_vv_f64m8_rm_tum
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmsub.mask.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
//
vfloat64m8_t test_vfnmsub_vv_f64m8_rm_tum(vbool8_t mask, vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfnmsub_vv_f64m8_rm_tum(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmsub_vf_f64m8_rm_tum
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmsub.mask.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
//
vfloat64m8_t test_vfnmsub_vf_f64m8_rm_tum(vbool8_t mask, vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfnmsub_vf_f64m8_rm_tum(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmsub_vv_f16mf4_rm_tumu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmsub.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
//
vfloat16mf4_t test_vfnmsub_vv_f16mf4_rm_tumu(vbool64_t mask, vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfnmsub_vv_f16mf4_rm_tumu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmsub_vf_f16mf4_rm_tumu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmsub.mask.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
//
vfloat16mf4_t test_vfnmsub_vf_f16mf4_rm_tumu(vbool64_t mask, vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfnmsub_vf_f16mf4_rm_tumu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmsub_vv_f16mf2_rm_tumu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmsub.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
//
vfloat16mf2_t test_vfnmsub_vv_f16mf2_rm_tumu(vbool32_t mask, vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfnmsub_vv_f16mf2_rm_tumu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmsub_vf_f16mf2_rm_tumu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmsub.mask.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
//
vfloat16mf2_t test_vfnmsub_vf_f16mf2_rm_tumu(vbool32_t mask, vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfnmsub_vf_f16mf2_rm_tumu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmsub_vv_f16m1_rm_tumu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmsub.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfnmsub_vv_f16m1_rm_tumu(vbool16_t mask, vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfnmsub_vv_f16m1_rm_tumu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmsub_vf_f16m1_rm_tumu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmsub.mask.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfnmsub_vf_f16m1_rm_tumu(vbool16_t mask, vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfnmsub_vf_f16m1_rm_tumu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmsub_vv_f16m2_rm_tumu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmsub.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
//
vfloat16m2_t test_vfnmsub_vv_f16m2_rm_tumu(vbool8_t mask, vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfnmsub_vv_f16m2_rm_tumu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmsub_vf_f16m2_rm_tumu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmsub.mask.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
//
vfloat16m2_t test_vfnmsub_vf_f16m2_rm_tumu(vbool8_t mask, vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfnmsub_vf_f16m2_rm_tumu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmsub_vv_f16m4_rm_tumu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmsub.mask.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
//
vfloat16m4_t test_vfnmsub_vv_f16m4_rm_tumu(vbool4_t mask, vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfnmsub_vv_f16m4_rm_tumu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmsub_vf_f16m4_rm_tumu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmsub.mask.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
//
vfloat16m4_t test_vfnmsub_vf_f16m4_rm_tumu(vbool4_t mask, vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfnmsub_vf_f16m4_rm_tumu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmsub_vv_f16m8_rm_tumu
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmsub.mask.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
//
vfloat16m8_t test_vfnmsub_vv_f16m8_rm_tumu(vbool2_t mask, vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfnmsub_vv_f16m8_rm_tumu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmsub_vf_f16m8_rm_tumu
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmsub.mask.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
//
vfloat16m8_t test_vfnmsub_vf_f16m8_rm_tumu(vbool2_t mask, vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfnmsub_vf_f16m8_rm_tumu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmsub_vv_f32mf2_rm_tumu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmsub.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
//
vfloat32mf2_t test_vfnmsub_vv_f32mf2_rm_tumu(vbool64_t mask, vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfnmsub_vv_f32mf2_rm_tumu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmsub_vf_f32mf2_rm_tumu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmsub.mask.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
//
vfloat32mf2_t test_vfnmsub_vf_f32mf2_rm_tumu(vbool64_t mask, vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfnmsub_vf_f32mf2_rm_tumu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmsub_vv_f32m1_rm_tumu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmsub.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfnmsub_vv_f32m1_rm_tumu(vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfnmsub_vv_f32m1_rm_tumu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmsub_vf_f32m1_rm_tumu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmsub.mask.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfnmsub_vf_f32m1_rm_tumu(vbool32_t mask, vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfnmsub_vf_f32m1_rm_tumu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmsub_vv_f32m2_rm_tumu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmsub.mask.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
//
vfloat32m2_t test_vfnmsub_vv_f32m2_rm_tumu(vbool16_t mask, vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfnmsub_vv_f32m2_rm_tumu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmsub_vf_f32m2_rm_tumu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmsub.mask.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
//
vfloat32m2_t test_vfnmsub_vf_f32m2_rm_tumu(vbool16_t mask, vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfnmsub_vf_f32m2_rm_tumu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmsub_vv_f32m4_rm_tumu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmsub.mask.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
//
vfloat32m4_t test_vfnmsub_vv_f32m4_rm_tumu(vbool8_t mask, vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfnmsub_vv_f32m4_rm_tumu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmsub_vf_f32m4_rm_tumu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmsub.mask.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
//
vfloat32m4_t test_vfnmsub_vf_f32m4_rm_tumu(vbool8_t mask, vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfnmsub_vf_f32m4_rm_tumu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmsub_vv_f32m8_rm_tumu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmsub.mask.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
//
vfloat32m8_t test_vfnmsub_vv_f32m8_rm_tumu(vbool4_t mask, vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfnmsub_vv_f32m8_rm_tumu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmsub_vf_f32m8_rm_tumu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmsub.mask.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
//
vfloat32m8_t test_vfnmsub_vf_f32m8_rm_tumu(vbool4_t mask, vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfnmsub_vf_f32m8_rm_tumu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmsub_vv_f64m1_rm_tumu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmsub.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfnmsub_vv_f64m1_rm_tumu(vbool64_t mask, vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfnmsub_vv_f64m1_rm_tumu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmsub_vf_f64m1_rm_tumu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmsub.mask.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfnmsub_vf_f64m1_rm_tumu(vbool64_t mask, vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfnmsub_vf_f64m1_rm_tumu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmsub_vv_f64m2_rm_tumu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmsub.mask.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
//
vfloat64m2_t test_vfnmsub_vv_f64m2_rm_tumu(vbool32_t mask, vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfnmsub_vv_f64m2_rm_tumu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmsub_vf_f64m2_rm_tumu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmsub.mask.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
//
vfloat64m2_t test_vfnmsub_vf_f64m2_rm_tumu(vbool32_t mask, vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfnmsub_vf_f64m2_rm_tumu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmsub_vv_f64m4_rm_tumu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmsub.mask.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
//
vfloat64m4_t test_vfnmsub_vv_f64m4_rm_tumu(vbool16_t mask, vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfnmsub_vv_f64m4_rm_tumu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmsub_vf_f64m4_rm_tumu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmsub.mask.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
//
vfloat64m4_t test_vfnmsub_vf_f64m4_rm_tumu(vbool16_t mask, vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfnmsub_vf_f64m4_rm_tumu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmsub_vv_f64m8_rm_tumu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmsub.mask.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
//
vfloat64m8_t test_vfnmsub_vv_f64m8_rm_tumu(vbool8_t mask, vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfnmsub_vv_f64m8_rm_tumu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmsub_vf_f64m8_rm_tumu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmsub.mask.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
//
vfloat64m8_t test_vfnmsub_vf_f64m8_rm_tumu(vbool8_t mask, vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfnmsub_vf_f64m8_rm_tumu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmsub_vv_f16mf4_rm_mu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmsub.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
//
vfloat16mf4_t test_vfnmsub_vv_f16mf4_rm_mu(vbool64_t mask, vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfnmsub_vv_f16mf4_rm_mu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmsub_vf_f16mf4_rm_mu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmsub.mask.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
//
vfloat16mf4_t test_vfnmsub_vf_f16mf4_rm_mu(vbool64_t mask, vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfnmsub_vf_f16mf4_rm_mu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmsub_vv_f16mf2_rm_mu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmsub.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
//
vfloat16mf2_t test_vfnmsub_vv_f16mf2_rm_mu(vbool32_t mask, vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfnmsub_vv_f16mf2_rm_mu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmsub_vf_f16mf2_rm_mu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmsub.mask.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
//
vfloat16mf2_t test_vfnmsub_vf_f16mf2_rm_mu(vbool32_t mask, vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfnmsub_vf_f16mf2_rm_mu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmsub_vv_f16m1_rm_mu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmsub.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfnmsub_vv_f16m1_rm_mu(vbool16_t mask, vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfnmsub_vv_f16m1_rm_mu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmsub_vf_f16m1_rm_mu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmsub.mask.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfnmsub_vf_f16m1_rm_mu(vbool16_t mask, vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfnmsub_vf_f16m1_rm_mu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmsub_vv_f16m2_rm_mu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmsub.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
//
vfloat16m2_t test_vfnmsub_vv_f16m2_rm_mu(vbool8_t mask, vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfnmsub_vv_f16m2_rm_mu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmsub_vf_f16m2_rm_mu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmsub.mask.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
//
vfloat16m2_t test_vfnmsub_vf_f16m2_rm_mu(vbool8_t mask, vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfnmsub_vf_f16m2_rm_mu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmsub_vv_f16m4_rm_mu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmsub.mask.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
//
vfloat16m4_t test_vfnmsub_vv_f16m4_rm_mu(vbool4_t mask, vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfnmsub_vv_f16m4_rm_mu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmsub_vf_f16m4_rm_mu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmsub.mask.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
//
vfloat16m4_t test_vfnmsub_vf_f16m4_rm_mu(vbool4_t mask, vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfnmsub_vf_f16m4_rm_mu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmsub_vv_f16m8_rm_mu
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmsub.mask.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
//
vfloat16m8_t test_vfnmsub_vv_f16m8_rm_mu(vbool2_t mask, vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfnmsub_vv_f16m8_rm_mu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmsub_vf_f16m8_rm_mu
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmsub.mask.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
//
vfloat16m8_t test_vfnmsub_vf_f16m8_rm_mu(vbool2_t mask, vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfnmsub_vf_f16m8_rm_mu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmsub_vv_f32mf2_rm_mu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmsub.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
//
vfloat32mf2_t test_vfnmsub_vv_f32mf2_rm_mu(vbool64_t mask, vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfnmsub_vv_f32mf2_rm_mu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmsub_vf_f32mf2_rm_mu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmsub.mask.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
//
vfloat32mf2_t test_vfnmsub_vf_f32mf2_rm_mu(vbool64_t mask, vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfnmsub_vf_f32mf2_rm_mu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmsub_vv_f32m1_rm_mu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmsub.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfnmsub_vv_f32m1_rm_mu(vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfnmsub_vv_f32m1_rm_mu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmsub_vf_f32m1_rm_mu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmsub.mask.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfnmsub_vf_f32m1_rm_mu(vbool32_t mask, vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfnmsub_vf_f32m1_rm_mu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmsub_vv_f32m2_rm_mu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmsub.mask.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
//
vfloat32m2_t test_vfnmsub_vv_f32m2_rm_mu(vbool16_t mask, vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfnmsub_vv_f32m2_rm_mu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmsub_vf_f32m2_rm_mu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmsub.mask.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
//
vfloat32m2_t test_vfnmsub_vf_f32m2_rm_mu(vbool16_t mask, vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfnmsub_vf_f32m2_rm_mu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmsub_vv_f32m4_rm_mu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmsub.mask.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
//
vfloat32m4_t test_vfnmsub_vv_f32m4_rm_mu(vbool8_t mask, vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfnmsub_vv_f32m4_rm_mu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmsub_vf_f32m4_rm_mu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmsub.mask.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
//
vfloat32m4_t test_vfnmsub_vf_f32m4_rm_mu(vbool8_t mask, vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfnmsub_vf_f32m4_rm_mu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmsub_vv_f32m8_rm_mu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmsub.mask.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
//
vfloat32m8_t test_vfnmsub_vv_f32m8_rm_mu(vbool4_t mask, vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfnmsub_vv_f32m8_rm_mu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmsub_vf_f32m8_rm_mu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmsub.mask.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
//
vfloat32m8_t test_vfnmsub_vf_f32m8_rm_mu(vbool4_t mask, vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfnmsub_vf_f32m8_rm_mu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmsub_vv_f64m1_rm_mu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmsub.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfnmsub_vv_f64m1_rm_mu(vbool64_t mask, vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfnmsub_vv_f64m1_rm_mu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmsub_vf_f64m1_rm_mu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmsub.mask.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfnmsub_vf_f64m1_rm_mu(vbool64_t mask, vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfnmsub_vf_f64m1_rm_mu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmsub_vv_f64m2_rm_mu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmsub.mask.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
//
vfloat64m2_t test_vfnmsub_vv_f64m2_rm_mu(vbool32_t mask, vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfnmsub_vv_f64m2_rm_mu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmsub_vf_f64m2_rm_mu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmsub.mask.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
//
vfloat64m2_t test_vfnmsub_vf_f64m2_rm_mu(vbool32_t mask, vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfnmsub_vf_f64m2_rm_mu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmsub_vv_f64m4_rm_mu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmsub.mask.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
//
vfloat64m4_t test_vfnmsub_vv_f64m4_rm_mu(vbool16_t mask, vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfnmsub_vv_f64m4_rm_mu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmsub_vf_f64m4_rm_mu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmsub.mask.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
//
vfloat64m4_t test_vfnmsub_vf_f64m4_rm_mu(vbool16_t mask, vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfnmsub_vf_f64m4_rm_mu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmsub_vv_f64m8_rm_mu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmsub.mask.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
//
vfloat64m8_t test_vfnmsub_vv_f64m8_rm_mu(vbool8_t mask, vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfnmsub_vv_f64m8_rm_mu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmsub_vf_f64m8_rm_mu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmsub.mask.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
//
vfloat64m8_t test_vfnmsub_vf_f64m8_rm_mu(vbool8_t mask, vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfnmsub_vf_f64m8_rm_mu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}

clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmacc.c

// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target // REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh \ // RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh \
// RUN: -target-feature +experimental-zvfh -disable-O0-optnone \ // RUN: -target-feature +experimental-zvfh -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ // RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s // RUN: FileCheck --check-prefix=CHECK-RV64 %s
#include <riscv_vector.h> #include <riscv_vector.h>
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmacc_vv_f16mf4_tu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmacc_vv_f16mf4_tu
// CHECK-RV64-SAME: (<vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK-RV64-SAME: (<vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmacc.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmacc.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
// //
vfloat16mf4_t test_vfmacc_vv_f16mf4_tu(vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) { vfloat16mf4_t test_vfmacc_vv_f16mf4_tu(vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfmacc_tu(vd, vs1, vs2, vl); return __riscv_vfmacc_tu(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmacc_vf_f16mf4_tu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmacc_vf_f16mf4_tu
// CHECK-RV64-SAME: (<vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmacc.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmacc.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
// //
vfloat16mf4_t test_vfmacc_vf_f16mf4_tu(vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) { vfloat16mf4_t test_vfmacc_vf_f16mf4_tu(vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfmacc_tu(vd, rs1, vs2, vl); return __riscv_vfmacc_tu(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmacc_vv_f16mf2_tu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmacc_vv_f16mf2_tu
// CHECK-RV64-SAME: (<vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmacc.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmacc.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
// //
vfloat16mf2_t test_vfmacc_vv_f16mf2_tu(vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) { vfloat16mf2_t test_vfmacc_vv_f16mf2_tu(vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfmacc_tu(vd, vs1, vs2, vl); return __riscv_vfmacc_tu(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmacc_vf_f16mf2_tu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmacc_vf_f16mf2_tu
// CHECK-RV64-SAME: (<vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmacc.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmacc.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
// //
vfloat16mf2_t test_vfmacc_vf_f16mf2_tu(vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) { vfloat16mf2_t test_vfmacc_vf_f16mf2_tu(vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfmacc_tu(vd, rs1, vs2, vl); return __riscv_vfmacc_tu(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmacc_vv_f16m1_tu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmacc_vv_f16m1_tu
// CHECK-RV64-SAME: (<vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmacc.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmacc.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
// //
vfloat16m1_t test_vfmacc_vv_f16m1_tu(vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) { vfloat16m1_t test_vfmacc_vv_f16m1_tu(vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfmacc_tu(vd, vs1, vs2, vl); return __riscv_vfmacc_tu(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmacc_vf_f16m1_tu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmacc_vf_f16m1_tu
// CHECK-RV64-SAME: (<vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmacc.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmacc.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
// //
vfloat16m1_t test_vfmacc_vf_f16m1_tu(vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) { vfloat16m1_t test_vfmacc_vf_f16m1_tu(vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfmacc_tu(vd, rs1, vs2, vl); return __riscv_vfmacc_tu(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmacc_vv_f16m2_tu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmacc_vv_f16m2_tu
// CHECK-RV64-SAME: (<vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmacc.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmacc.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
// //
vfloat16m2_t test_vfmacc_vv_f16m2_tu(vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) { vfloat16m2_t test_vfmacc_vv_f16m2_tu(vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfmacc_tu(vd, vs1, vs2, vl); return __riscv_vfmacc_tu(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmacc_vf_f16m2_tu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmacc_vf_f16m2_tu
// CHECK-RV64-SAME: (<vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmacc.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmacc.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
// //
vfloat16m2_t test_vfmacc_vf_f16m2_tu(vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) { vfloat16m2_t test_vfmacc_vf_f16m2_tu(vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfmacc_tu(vd, rs1, vs2, vl); return __riscv_vfmacc_tu(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmacc_vv_f16m4_tu // CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmacc_vv_f16m4_tu
// CHECK-RV64-SAME: (<vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmacc.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmacc.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
// //
vfloat16m4_t test_vfmacc_vv_f16m4_tu(vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) { vfloat16m4_t test_vfmacc_vv_f16m4_tu(vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfmacc_tu(vd, vs1, vs2, vl); return __riscv_vfmacc_tu(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmacc_vf_f16m4_tu // CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmacc_vf_f16m4_tu
// CHECK-RV64-SAME: (<vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmacc.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmacc.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
// //
vfloat16m4_t test_vfmacc_vf_f16m4_tu(vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) { vfloat16m4_t test_vfmacc_vf_f16m4_tu(vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfmacc_tu(vd, rs1, vs2, vl); return __riscv_vfmacc_tu(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmacc_vv_f16m8_tu // CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmacc_vv_f16m8_tu
// CHECK-RV64-SAME: (<vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmacc.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmacc.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
// //
vfloat16m8_t test_vfmacc_vv_f16m8_tu(vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) { vfloat16m8_t test_vfmacc_vv_f16m8_tu(vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfmacc_tu(vd, vs1, vs2, vl); return __riscv_vfmacc_tu(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmacc_vf_f16m8_tu // CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmacc_vf_f16m8_tu
// CHECK-RV64-SAME: (<vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmacc.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmacc.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
// //
vfloat16m8_t test_vfmacc_vf_f16m8_tu(vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) { vfloat16m8_t test_vfmacc_vf_f16m8_tu(vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfmacc_tu(vd, rs1, vs2, vl); return __riscv_vfmacc_tu(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmacc_vv_f32mf2_tu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmacc_vv_f32mf2_tu
// CHECK-RV64-SAME: (<vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmacc.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmacc.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfmacc_vv_f32mf2_tu(vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) { vfloat32mf2_t test_vfmacc_vv_f32mf2_tu(vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfmacc_tu(vd, vs1, vs2, vl); return __riscv_vfmacc_tu(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmacc_vf_f32mf2_tu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmacc_vf_f32mf2_tu
// CHECK-RV64-SAME: (<vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmacc.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmacc.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfmacc_vf_f32mf2_tu(vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) { vfloat32mf2_t test_vfmacc_vf_f32mf2_tu(vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfmacc_tu(vd, rs1, vs2, vl); return __riscv_vfmacc_tu(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmacc_vv_f32m1_tu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmacc_vv_f32m1_tu
// CHECK-RV64-SAME: (<vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmacc.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmacc.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfmacc_vv_f32m1_tu(vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) { vfloat32m1_t test_vfmacc_vv_f32m1_tu(vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfmacc_tu(vd, vs1, vs2, vl); return __riscv_vfmacc_tu(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmacc_vf_f32m1_tu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmacc_vf_f32m1_tu
// CHECK-RV64-SAME: (<vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmacc.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmacc.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfmacc_vf_f32m1_tu(vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) { vfloat32m1_t test_vfmacc_vf_f32m1_tu(vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfmacc_tu(vd, rs1, vs2, vl); return __riscv_vfmacc_tu(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmacc_vv_f32m2_tu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmacc_vv_f32m2_tu
// CHECK-RV64-SAME: (<vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmacc.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmacc.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfmacc_vv_f32m2_tu(vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) { vfloat32m2_t test_vfmacc_vv_f32m2_tu(vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfmacc_tu(vd, vs1, vs2, vl); return __riscv_vfmacc_tu(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmacc_vf_f32m2_tu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmacc_vf_f32m2_tu
// CHECK-RV64-SAME: (<vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmacc.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmacc.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfmacc_vf_f32m2_tu(vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) { vfloat32m2_t test_vfmacc_vf_f32m2_tu(vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfmacc_tu(vd, rs1, vs2, vl); return __riscv_vfmacc_tu(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmacc_vv_f32m4_tu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmacc_vv_f32m4_tu
// CHECK-RV64-SAME: (<vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmacc.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmacc.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfmacc_vv_f32m4_tu(vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) { vfloat32m4_t test_vfmacc_vv_f32m4_tu(vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfmacc_tu(vd, vs1, vs2, vl); return __riscv_vfmacc_tu(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmacc_vf_f32m4_tu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmacc_vf_f32m4_tu
// CHECK-RV64-SAME: (<vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmacc.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmacc.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfmacc_vf_f32m4_tu(vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) { vfloat32m4_t test_vfmacc_vf_f32m4_tu(vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfmacc_tu(vd, rs1, vs2, vl); return __riscv_vfmacc_tu(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmacc_vv_f32m8_tu // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmacc_vv_f32m8_tu
// CHECK-RV64-SAME: (<vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmacc.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmacc.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfmacc_vv_f32m8_tu(vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) { vfloat32m8_t test_vfmacc_vv_f32m8_tu(vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfmacc_tu(vd, vs1, vs2, vl); return __riscv_vfmacc_tu(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmacc_vf_f32m8_tu // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmacc_vf_f32m8_tu
// CHECK-RV64-SAME: (<vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmacc.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmacc.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfmacc_vf_f32m8_tu(vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) { vfloat32m8_t test_vfmacc_vf_f32m8_tu(vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfmacc_tu(vd, rs1, vs2, vl); return __riscv_vfmacc_tu(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmacc_vv_f64m1_tu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmacc_vv_f64m1_tu
// CHECK-RV64-SAME: (<vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmacc.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmacc.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfmacc_vv_f64m1_tu(vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) { vfloat64m1_t test_vfmacc_vv_f64m1_tu(vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfmacc_tu(vd, vs1, vs2, vl); return __riscv_vfmacc_tu(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmacc_vf_f64m1_tu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmacc_vf_f64m1_tu
// CHECK-RV64-SAME: (<vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmacc.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmacc.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfmacc_vf_f64m1_tu(vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) { vfloat64m1_t test_vfmacc_vf_f64m1_tu(vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfmacc_tu(vd, rs1, vs2, vl); return __riscv_vfmacc_tu(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmacc_vv_f64m2_tu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmacc_vv_f64m2_tu
// CHECK-RV64-SAME: (<vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmacc.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmacc.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfmacc_vv_f64m2_tu(vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) { vfloat64m2_t test_vfmacc_vv_f64m2_tu(vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfmacc_tu(vd, vs1, vs2, vl); return __riscv_vfmacc_tu(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmacc_vf_f64m2_tu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmacc_vf_f64m2_tu
// CHECK-RV64-SAME: (<vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmacc.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmacc.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfmacc_vf_f64m2_tu(vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) { vfloat64m2_t test_vfmacc_vf_f64m2_tu(vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfmacc_tu(vd, rs1, vs2, vl); return __riscv_vfmacc_tu(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmacc_vv_f64m4_tu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmacc_vv_f64m4_tu
// CHECK-RV64-SAME: (<vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmacc.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmacc.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfmacc_vv_f64m4_tu(vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) { vfloat64m4_t test_vfmacc_vv_f64m4_tu(vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfmacc_tu(vd, vs1, vs2, vl); return __riscv_vfmacc_tu(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmacc_vf_f64m4_tu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmacc_vf_f64m4_tu
// CHECK-RV64-SAME: (<vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmacc.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmacc.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfmacc_vf_f64m4_tu(vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) { vfloat64m4_t test_vfmacc_vf_f64m4_tu(vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfmacc_tu(vd, rs1, vs2, vl); return __riscv_vfmacc_tu(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmacc_vv_f64m8_tu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmacc_vv_f64m8_tu
// CHECK-RV64-SAME: (<vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmacc.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmacc.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfmacc_vv_f64m8_tu(vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) { vfloat64m8_t test_vfmacc_vv_f64m8_tu(vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfmacc_tu(vd, vs1, vs2, vl); return __riscv_vfmacc_tu(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmacc_vf_f64m8_tu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmacc_vf_f64m8_tu
// CHECK-RV64-SAME: (<vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmacc.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmacc.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfmacc_vf_f64m8_tu(vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) { vfloat64m8_t test_vfmacc_vf_f64m8_tu(vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfmacc_tu(vd, rs1, vs2, vl); return __riscv_vfmacc_tu(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmacc_vv_f16mf4_tum // CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmacc_vv_f16mf4_tum
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmacc.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmacc.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
// //
vfloat16mf4_t test_vfmacc_vv_f16mf4_tum(vbool64_t mask, vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) { vfloat16mf4_t test_vfmacc_vv_f16mf4_tum(vbool64_t mask, vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfmacc_tum(mask, vd, vs1, vs2, vl); return __riscv_vfmacc_tum(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmacc_vf_f16mf4_tum // CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmacc_vf_f16mf4_tum
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmacc.mask.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmacc.mask.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
// //
vfloat16mf4_t test_vfmacc_vf_f16mf4_tum(vbool64_t mask, vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) { vfloat16mf4_t test_vfmacc_vf_f16mf4_tum(vbool64_t mask, vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfmacc_tum(mask, vd, rs1, vs2, vl); return __riscv_vfmacc_tum(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmacc_vv_f16mf2_tum // CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmacc_vv_f16mf2_tum
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmacc.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmacc.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
// //
vfloat16mf2_t test_vfmacc_vv_f16mf2_tum(vbool32_t mask, vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) { vfloat16mf2_t test_vfmacc_vv_f16mf2_tum(vbool32_t mask, vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfmacc_tum(mask, vd, vs1, vs2, vl); return __riscv_vfmacc_tum(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmacc_vf_f16mf2_tum // CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmacc_vf_f16mf2_tum
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmacc.mask.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmacc.mask.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
// //
vfloat16mf2_t test_vfmacc_vf_f16mf2_tum(vbool32_t mask, vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) { vfloat16mf2_t test_vfmacc_vf_f16mf2_tum(vbool32_t mask, vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfmacc_tum(mask, vd, rs1, vs2, vl); return __riscv_vfmacc_tum(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmacc_vv_f16m1_tum // CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmacc_vv_f16m1_tum
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmacc.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmacc.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
// //
vfloat16m1_t test_vfmacc_vv_f16m1_tum(vbool16_t mask, vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) { vfloat16m1_t test_vfmacc_vv_f16m1_tum(vbool16_t mask, vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfmacc_tum(mask, vd, vs1, vs2, vl); return __riscv_vfmacc_tum(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmacc_vf_f16m1_tum // CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmacc_vf_f16m1_tum
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmacc.mask.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmacc.mask.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
// //
vfloat16m1_t test_vfmacc_vf_f16m1_tum(vbool16_t mask, vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) { vfloat16m1_t test_vfmacc_vf_f16m1_tum(vbool16_t mask, vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfmacc_tum(mask, vd, rs1, vs2, vl); return __riscv_vfmacc_tum(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmacc_vv_f16m2_tum // CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmacc_vv_f16m2_tum
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmacc.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmacc.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
// //
vfloat16m2_t test_vfmacc_vv_f16m2_tum(vbool8_t mask, vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) { vfloat16m2_t test_vfmacc_vv_f16m2_tum(vbool8_t mask, vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfmacc_tum(mask, vd, vs1, vs2, vl); return __riscv_vfmacc_tum(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmacc_vf_f16m2_tum // CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmacc_vf_f16m2_tum
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmacc.mask.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmacc.mask.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
// //
vfloat16m2_t test_vfmacc_vf_f16m2_tum(vbool8_t mask, vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) { vfloat16m2_t test_vfmacc_vf_f16m2_tum(vbool8_t mask, vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfmacc_tum(mask, vd, rs1, vs2, vl); return __riscv_vfmacc_tum(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmacc_vv_f16m4_tum // CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmacc_vv_f16m4_tum
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmacc.mask.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmacc.mask.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
// //
vfloat16m4_t test_vfmacc_vv_f16m4_tum(vbool4_t mask, vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) { vfloat16m4_t test_vfmacc_vv_f16m4_tum(vbool4_t mask, vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfmacc_tum(mask, vd, vs1, vs2, vl); return __riscv_vfmacc_tum(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmacc_vf_f16m4_tum // CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmacc_vf_f16m4_tum
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmacc.mask.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmacc.mask.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
// //
vfloat16m4_t test_vfmacc_vf_f16m4_tum(vbool4_t mask, vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) { vfloat16m4_t test_vfmacc_vf_f16m4_tum(vbool4_t mask, vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfmacc_tum(mask, vd, rs1, vs2, vl); return __riscv_vfmacc_tum(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmacc_vv_f16m8_tum // CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmacc_vv_f16m8_tum
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmacc.mask.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmacc.mask.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
// //
vfloat16m8_t test_vfmacc_vv_f16m8_tum(vbool2_t mask, vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) { vfloat16m8_t test_vfmacc_vv_f16m8_tum(vbool2_t mask, vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfmacc_tum(mask, vd, vs1, vs2, vl); return __riscv_vfmacc_tum(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmacc_vf_f16m8_tum // CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmacc_vf_f16m8_tum
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmacc.mask.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmacc.mask.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
// //
vfloat16m8_t test_vfmacc_vf_f16m8_tum(vbool2_t mask, vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) { vfloat16m8_t test_vfmacc_vf_f16m8_tum(vbool2_t mask, vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfmacc_tum(mask, vd, rs1, vs2, vl); return __riscv_vfmacc_tum(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmacc_vv_f32mf2_tum // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmacc_vv_f32mf2_tum
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmacc.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmacc.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfmacc_vv_f32mf2_tum(vbool64_t mask, vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) { vfloat32mf2_t test_vfmacc_vv_f32mf2_tum(vbool64_t mask, vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfmacc_tum(mask, vd, vs1, vs2, vl); return __riscv_vfmacc_tum(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmacc_vf_f32mf2_tum // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmacc_vf_f32mf2_tum
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmacc.mask.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmacc.mask.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfmacc_vf_f32mf2_tum(vbool64_t mask, vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) { vfloat32mf2_t test_vfmacc_vf_f32mf2_tum(vbool64_t mask, vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfmacc_tum(mask, vd, rs1, vs2, vl); return __riscv_vfmacc_tum(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmacc_vv_f32m1_tum // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmacc_vv_f32m1_tum
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmacc.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmacc.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfmacc_vv_f32m1_tum(vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) { vfloat32m1_t test_vfmacc_vv_f32m1_tum(vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfmacc_tum(mask, vd, vs1, vs2, vl); return __riscv_vfmacc_tum(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmacc_vf_f32m1_tum // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmacc_vf_f32m1_tum
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmacc.mask.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmacc.mask.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfmacc_vf_f32m1_tum(vbool32_t mask, vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) { vfloat32m1_t test_vfmacc_vf_f32m1_tum(vbool32_t mask, vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfmacc_tum(mask, vd, rs1, vs2, vl); return __riscv_vfmacc_tum(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmacc_vv_f32m2_tum // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmacc_vv_f32m2_tum
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmacc.mask.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmacc.mask.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfmacc_vv_f32m2_tum(vbool16_t mask, vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) { vfloat32m2_t test_vfmacc_vv_f32m2_tum(vbool16_t mask, vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfmacc_tum(mask, vd, vs1, vs2, vl); return __riscv_vfmacc_tum(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmacc_vf_f32m2_tum // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmacc_vf_f32m2_tum
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmacc.mask.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmacc.mask.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfmacc_vf_f32m2_tum(vbool16_t mask, vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) { vfloat32m2_t test_vfmacc_vf_f32m2_tum(vbool16_t mask, vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfmacc_tum(mask, vd, rs1, vs2, vl); return __riscv_vfmacc_tum(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmacc_vv_f32m4_tum // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmacc_vv_f32m4_tum
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmacc.mask.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmacc.mask.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfmacc_vv_f32m4_tum(vbool8_t mask, vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) { vfloat32m4_t test_vfmacc_vv_f32m4_tum(vbool8_t mask, vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfmacc_tum(mask, vd, vs1, vs2, vl); return __riscv_vfmacc_tum(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmacc_vf_f32m4_tum // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmacc_vf_f32m4_tum
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmacc.mask.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmacc.mask.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfmacc_vf_f32m4_tum(vbool8_t mask, vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) { vfloat32m4_t test_vfmacc_vf_f32m4_tum(vbool8_t mask, vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfmacc_tum(mask, vd, rs1, vs2, vl); return __riscv_vfmacc_tum(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmacc_vv_f32m8_tum // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmacc_vv_f32m8_tum
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmacc.mask.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmacc.mask.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfmacc_vv_f32m8_tum(vbool4_t mask, vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) { vfloat32m8_t test_vfmacc_vv_f32m8_tum(vbool4_t mask, vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfmacc_tum(mask, vd, vs1, vs2, vl); return __riscv_vfmacc_tum(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmacc_vf_f32m8_tum // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmacc_vf_f32m8_tum
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmacc.mask.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmacc.mask.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfmacc_vf_f32m8_tum(vbool4_t mask, vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) { vfloat32m8_t test_vfmacc_vf_f32m8_tum(vbool4_t mask, vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfmacc_tum(mask, vd, rs1, vs2, vl); return __riscv_vfmacc_tum(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmacc_vv_f64m1_tum // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmacc_vv_f64m1_tum
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmacc.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmacc.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfmacc_vv_f64m1_tum(vbool64_t mask, vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) { vfloat64m1_t test_vfmacc_vv_f64m1_tum(vbool64_t mask, vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfmacc_tum(mask, vd, vs1, vs2, vl); return __riscv_vfmacc_tum(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmacc_vf_f64m1_tum // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmacc_vf_f64m1_tum
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmacc.mask.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmacc.mask.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfmacc_vf_f64m1_tum(vbool64_t mask, vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) { vfloat64m1_t test_vfmacc_vf_f64m1_tum(vbool64_t mask, vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfmacc_tum(mask, vd, rs1, vs2, vl); return __riscv_vfmacc_tum(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmacc_vv_f64m2_tum // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmacc_vv_f64m2_tum
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmacc.mask.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmacc.mask.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfmacc_vv_f64m2_tum(vbool32_t mask, vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) { vfloat64m2_t test_vfmacc_vv_f64m2_tum(vbool32_t mask, vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfmacc_tum(mask, vd, vs1, vs2, vl); return __riscv_vfmacc_tum(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmacc_vf_f64m2_tum // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmacc_vf_f64m2_tum
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmacc.mask.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmacc.mask.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfmacc_vf_f64m2_tum(vbool32_t mask, vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) { vfloat64m2_t test_vfmacc_vf_f64m2_tum(vbool32_t mask, vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfmacc_tum(mask, vd, rs1, vs2, vl); return __riscv_vfmacc_tum(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmacc_vv_f64m4_tum // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmacc_vv_f64m4_tum
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmacc.mask.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmacc.mask.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfmacc_vv_f64m4_tum(vbool16_t mask, vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) { vfloat64m4_t test_vfmacc_vv_f64m4_tum(vbool16_t mask, vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfmacc_tum(mask, vd, vs1, vs2, vl); return __riscv_vfmacc_tum(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmacc_vf_f64m4_tum // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmacc_vf_f64m4_tum
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmacc.mask.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmacc.mask.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfmacc_vf_f64m4_tum(vbool16_t mask, vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) { vfloat64m4_t test_vfmacc_vf_f64m4_tum(vbool16_t mask, vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfmacc_tum(mask, vd, rs1, vs2, vl); return __riscv_vfmacc_tum(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmacc_vv_f64m8_tum // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmacc_vv_f64m8_tum
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmacc.mask.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmacc.mask.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfmacc_vv_f64m8_tum(vbool8_t mask, vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) { vfloat64m8_t test_vfmacc_vv_f64m8_tum(vbool8_t mask, vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfmacc_tum(mask, vd, vs1, vs2, vl); return __riscv_vfmacc_tum(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmacc_vf_f64m8_tum // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmacc_vf_f64m8_tum
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmacc.mask.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmacc.mask.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfmacc_vf_f64m8_tum(vbool8_t mask, vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) { vfloat64m8_t test_vfmacc_vf_f64m8_tum(vbool8_t mask, vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfmacc_tum(mask, vd, rs1, vs2, vl); return __riscv_vfmacc_tum(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmacc_vv_f16mf4_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmacc_vv_f16mf4_tumu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmacc.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmacc.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
// //
vfloat16mf4_t test_vfmacc_vv_f16mf4_tumu(vbool64_t mask, vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) { vfloat16mf4_t test_vfmacc_vv_f16mf4_tumu(vbool64_t mask, vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfmacc_tumu(mask, vd, vs1, vs2, vl); return __riscv_vfmacc_tumu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmacc_vf_f16mf4_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmacc_vf_f16mf4_tumu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmacc.mask.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmacc.mask.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
// //
vfloat16mf4_t test_vfmacc_vf_f16mf4_tumu(vbool64_t mask, vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) { vfloat16mf4_t test_vfmacc_vf_f16mf4_tumu(vbool64_t mask, vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfmacc_tumu(mask, vd, rs1, vs2, vl); return __riscv_vfmacc_tumu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmacc_vv_f16mf2_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmacc_vv_f16mf2_tumu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmacc.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmacc.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
// //
vfloat16mf2_t test_vfmacc_vv_f16mf2_tumu(vbool32_t mask, vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) { vfloat16mf2_t test_vfmacc_vv_f16mf2_tumu(vbool32_t mask, vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfmacc_tumu(mask, vd, vs1, vs2, vl); return __riscv_vfmacc_tumu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmacc_vf_f16mf2_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmacc_vf_f16mf2_tumu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmacc.mask.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmacc.mask.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
// //
vfloat16mf2_t test_vfmacc_vf_f16mf2_tumu(vbool32_t mask, vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) { vfloat16mf2_t test_vfmacc_vf_f16mf2_tumu(vbool32_t mask, vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfmacc_tumu(mask, vd, rs1, vs2, vl); return __riscv_vfmacc_tumu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmacc_vv_f16m1_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmacc_vv_f16m1_tumu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmacc.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmacc.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
// //
vfloat16m1_t test_vfmacc_vv_f16m1_tumu(vbool16_t mask, vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) { vfloat16m1_t test_vfmacc_vv_f16m1_tumu(vbool16_t mask, vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfmacc_tumu(mask, vd, vs1, vs2, vl); return __riscv_vfmacc_tumu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmacc_vf_f16m1_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmacc_vf_f16m1_tumu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmacc.mask.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmacc.mask.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
// //
vfloat16m1_t test_vfmacc_vf_f16m1_tumu(vbool16_t mask, vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) { vfloat16m1_t test_vfmacc_vf_f16m1_tumu(vbool16_t mask, vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfmacc_tumu(mask, vd, rs1, vs2, vl); return __riscv_vfmacc_tumu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmacc_vv_f16m2_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmacc_vv_f16m2_tumu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmacc.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmacc.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
// //
vfloat16m2_t test_vfmacc_vv_f16m2_tumu(vbool8_t mask, vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) { vfloat16m2_t test_vfmacc_vv_f16m2_tumu(vbool8_t mask, vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfmacc_tumu(mask, vd, vs1, vs2, vl); return __riscv_vfmacc_tumu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmacc_vf_f16m2_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmacc_vf_f16m2_tumu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmacc.mask.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmacc.mask.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
// //
vfloat16m2_t test_vfmacc_vf_f16m2_tumu(vbool8_t mask, vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) { vfloat16m2_t test_vfmacc_vf_f16m2_tumu(vbool8_t mask, vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfmacc_tumu(mask, vd, rs1, vs2, vl); return __riscv_vfmacc_tumu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmacc_vv_f16m4_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmacc_vv_f16m4_tumu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmacc.mask.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmacc.mask.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
// //
vfloat16m4_t test_vfmacc_vv_f16m4_tumu(vbool4_t mask, vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) { vfloat16m4_t test_vfmacc_vv_f16m4_tumu(vbool4_t mask, vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfmacc_tumu(mask, vd, vs1, vs2, vl); return __riscv_vfmacc_tumu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmacc_vf_f16m4_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmacc_vf_f16m4_tumu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmacc.mask.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmacc.mask.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
// //
vfloat16m4_t test_vfmacc_vf_f16m4_tumu(vbool4_t mask, vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) { vfloat16m4_t test_vfmacc_vf_f16m4_tumu(vbool4_t mask, vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfmacc_tumu(mask, vd, rs1, vs2, vl); return __riscv_vfmacc_tumu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmacc_vv_f16m8_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmacc_vv_f16m8_tumu
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmacc.mask.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmacc.mask.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
// //
vfloat16m8_t test_vfmacc_vv_f16m8_tumu(vbool2_t mask, vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) { vfloat16m8_t test_vfmacc_vv_f16m8_tumu(vbool2_t mask, vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfmacc_tumu(mask, vd, vs1, vs2, vl); return __riscv_vfmacc_tumu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmacc_vf_f16m8_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmacc_vf_f16m8_tumu
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmacc.mask.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmacc.mask.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
// //
vfloat16m8_t test_vfmacc_vf_f16m8_tumu(vbool2_t mask, vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) { vfloat16m8_t test_vfmacc_vf_f16m8_tumu(vbool2_t mask, vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfmacc_tumu(mask, vd, rs1, vs2, vl); return __riscv_vfmacc_tumu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmacc_vv_f32mf2_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmacc_vv_f32mf2_tumu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmacc.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmacc.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfmacc_vv_f32mf2_tumu(vbool64_t mask, vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) { vfloat32mf2_t test_vfmacc_vv_f32mf2_tumu(vbool64_t mask, vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfmacc_tumu(mask, vd, vs1, vs2, vl); return __riscv_vfmacc_tumu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmacc_vf_f32mf2_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmacc_vf_f32mf2_tumu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmacc.mask.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmacc.mask.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfmacc_vf_f32mf2_tumu(vbool64_t mask, vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) { vfloat32mf2_t test_vfmacc_vf_f32mf2_tumu(vbool64_t mask, vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfmacc_tumu(mask, vd, rs1, vs2, vl); return __riscv_vfmacc_tumu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmacc_vv_f32m1_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmacc_vv_f32m1_tumu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmacc.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmacc.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfmacc_vv_f32m1_tumu(vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) { vfloat32m1_t test_vfmacc_vv_f32m1_tumu(vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfmacc_tumu(mask, vd, vs1, vs2, vl); return __riscv_vfmacc_tumu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmacc_vf_f32m1_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmacc_vf_f32m1_tumu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmacc.mask.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmacc.mask.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfmacc_vf_f32m1_tumu(vbool32_t mask, vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) { vfloat32m1_t test_vfmacc_vf_f32m1_tumu(vbool32_t mask, vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfmacc_tumu(mask, vd, rs1, vs2, vl); return __riscv_vfmacc_tumu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmacc_vv_f32m2_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmacc_vv_f32m2_tumu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmacc.mask.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmacc.mask.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfmacc_vv_f32m2_tumu(vbool16_t mask, vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) { vfloat32m2_t test_vfmacc_vv_f32m2_tumu(vbool16_t mask, vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfmacc_tumu(mask, vd, vs1, vs2, vl); return __riscv_vfmacc_tumu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmacc_vf_f32m2_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmacc_vf_f32m2_tumu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmacc.mask.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmacc.mask.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfmacc_vf_f32m2_tumu(vbool16_t mask, vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) { vfloat32m2_t test_vfmacc_vf_f32m2_tumu(vbool16_t mask, vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfmacc_tumu(mask, vd, rs1, vs2, vl); return __riscv_vfmacc_tumu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmacc_vv_f32m4_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmacc_vv_f32m4_tumu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmacc.mask.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmacc.mask.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfmacc_vv_f32m4_tumu(vbool8_t mask, vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) { vfloat32m4_t test_vfmacc_vv_f32m4_tumu(vbool8_t mask, vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfmacc_tumu(mask, vd, vs1, vs2, vl); return __riscv_vfmacc_tumu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmacc_vf_f32m4_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmacc_vf_f32m4_tumu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmacc.mask.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmacc.mask.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfmacc_vf_f32m4_tumu(vbool8_t mask, vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) { vfloat32m4_t test_vfmacc_vf_f32m4_tumu(vbool8_t mask, vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfmacc_tumu(mask, vd, rs1, vs2, vl); return __riscv_vfmacc_tumu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmacc_vv_f32m8_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmacc_vv_f32m8_tumu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmacc.mask.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmacc.mask.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfmacc_vv_f32m8_tumu(vbool4_t mask, vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) { vfloat32m8_t test_vfmacc_vv_f32m8_tumu(vbool4_t mask, vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfmacc_tumu(mask, vd, vs1, vs2, vl); return __riscv_vfmacc_tumu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmacc_vf_f32m8_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmacc_vf_f32m8_tumu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmacc.mask.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmacc.mask.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfmacc_vf_f32m8_tumu(vbool4_t mask, vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) { vfloat32m8_t test_vfmacc_vf_f32m8_tumu(vbool4_t mask, vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfmacc_tumu(mask, vd, rs1, vs2, vl); return __riscv_vfmacc_tumu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmacc_vv_f64m1_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmacc_vv_f64m1_tumu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmacc.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmacc.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfmacc_vv_f64m1_tumu(vbool64_t mask, vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) { vfloat64m1_t test_vfmacc_vv_f64m1_tumu(vbool64_t mask, vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfmacc_tumu(mask, vd, vs1, vs2, vl); return __riscv_vfmacc_tumu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmacc_vf_f64m1_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmacc_vf_f64m1_tumu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmacc.mask.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmacc.mask.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfmacc_vf_f64m1_tumu(vbool64_t mask, vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) { vfloat64m1_t test_vfmacc_vf_f64m1_tumu(vbool64_t mask, vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfmacc_tumu(mask, vd, rs1, vs2, vl); return __riscv_vfmacc_tumu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmacc_vv_f64m2_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmacc_vv_f64m2_tumu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmacc.mask.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmacc.mask.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfmacc_vv_f64m2_tumu(vbool32_t mask, vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) { vfloat64m2_t test_vfmacc_vv_f64m2_tumu(vbool32_t mask, vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfmacc_tumu(mask, vd, vs1, vs2, vl); return __riscv_vfmacc_tumu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmacc_vf_f64m2_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmacc_vf_f64m2_tumu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmacc.mask.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmacc.mask.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfmacc_vf_f64m2_tumu(vbool32_t mask, vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) { vfloat64m2_t test_vfmacc_vf_f64m2_tumu(vbool32_t mask, vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfmacc_tumu(mask, vd, rs1, vs2, vl); return __riscv_vfmacc_tumu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmacc_vv_f64m4_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmacc_vv_f64m4_tumu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmacc.mask.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmacc.mask.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfmacc_vv_f64m4_tumu(vbool16_t mask, vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) { vfloat64m4_t test_vfmacc_vv_f64m4_tumu(vbool16_t mask, vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfmacc_tumu(mask, vd, vs1, vs2, vl); return __riscv_vfmacc_tumu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmacc_vf_f64m4_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmacc_vf_f64m4_tumu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmacc.mask.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmacc.mask.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfmacc_vf_f64m4_tumu(vbool16_t mask, vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) { vfloat64m4_t test_vfmacc_vf_f64m4_tumu(vbool16_t mask, vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfmacc_tumu(mask, vd, rs1, vs2, vl); return __riscv_vfmacc_tumu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmacc_vv_f64m8_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmacc_vv_f64m8_tumu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmacc.mask.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmacc.mask.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfmacc_vv_f64m8_tumu(vbool8_t mask, vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) { vfloat64m8_t test_vfmacc_vv_f64m8_tumu(vbool8_t mask, vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfmacc_tumu(mask, vd, vs1, vs2, vl); return __riscv_vfmacc_tumu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmacc_vf_f64m8_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmacc_vf_f64m8_tumu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmacc.mask.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmacc.mask.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfmacc_vf_f64m8_tumu(vbool8_t mask, vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) { vfloat64m8_t test_vfmacc_vf_f64m8_tumu(vbool8_t mask, vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfmacc_tumu(mask, vd, rs1, vs2, vl); return __riscv_vfmacc_tumu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmacc_vv_f16mf4_mu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmacc_vv_f16mf4_mu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmacc.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmacc.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
// //
vfloat16mf4_t test_vfmacc_vv_f16mf4_mu(vbool64_t mask, vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) { vfloat16mf4_t test_vfmacc_vv_f16mf4_mu(vbool64_t mask, vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfmacc_mu(mask, vd, vs1, vs2, vl); return __riscv_vfmacc_mu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmacc_vf_f16mf4_mu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmacc_vf_f16mf4_mu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmacc.mask.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmacc.mask.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
// //
vfloat16mf4_t test_vfmacc_vf_f16mf4_mu(vbool64_t mask, vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) { vfloat16mf4_t test_vfmacc_vf_f16mf4_mu(vbool64_t mask, vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfmacc_mu(mask, vd, rs1, vs2, vl); return __riscv_vfmacc_mu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmacc_vv_f16mf2_mu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmacc_vv_f16mf2_mu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmacc.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmacc.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
// //
vfloat16mf2_t test_vfmacc_vv_f16mf2_mu(vbool32_t mask, vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) { vfloat16mf2_t test_vfmacc_vv_f16mf2_mu(vbool32_t mask, vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfmacc_mu(mask, vd, vs1, vs2, vl); return __riscv_vfmacc_mu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmacc_vf_f16mf2_mu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmacc_vf_f16mf2_mu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmacc.mask.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmacc.mask.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
// //
vfloat16mf2_t test_vfmacc_vf_f16mf2_mu(vbool32_t mask, vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) { vfloat16mf2_t test_vfmacc_vf_f16mf2_mu(vbool32_t mask, vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfmacc_mu(mask, vd, rs1, vs2, vl); return __riscv_vfmacc_mu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmacc_vv_f16m1_mu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmacc_vv_f16m1_mu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmacc.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmacc.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
// //
vfloat16m1_t test_vfmacc_vv_f16m1_mu(vbool16_t mask, vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) { vfloat16m1_t test_vfmacc_vv_f16m1_mu(vbool16_t mask, vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfmacc_mu(mask, vd, vs1, vs2, vl); return __riscv_vfmacc_mu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmacc_vf_f16m1_mu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmacc_vf_f16m1_mu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmacc.mask.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmacc.mask.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
// //
vfloat16m1_t test_vfmacc_vf_f16m1_mu(vbool16_t mask, vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) { vfloat16m1_t test_vfmacc_vf_f16m1_mu(vbool16_t mask, vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfmacc_mu(mask, vd, rs1, vs2, vl); return __riscv_vfmacc_mu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmacc_vv_f16m2_mu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmacc_vv_f16m2_mu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmacc.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmacc.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
// //
vfloat16m2_t test_vfmacc_vv_f16m2_mu(vbool8_t mask, vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) { vfloat16m2_t test_vfmacc_vv_f16m2_mu(vbool8_t mask, vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfmacc_mu(mask, vd, vs1, vs2, vl); return __riscv_vfmacc_mu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmacc_vf_f16m2_mu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmacc_vf_f16m2_mu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmacc.mask.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmacc.mask.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
// //
vfloat16m2_t test_vfmacc_vf_f16m2_mu(vbool8_t mask, vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) { vfloat16m2_t test_vfmacc_vf_f16m2_mu(vbool8_t mask, vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfmacc_mu(mask, vd, rs1, vs2, vl); return __riscv_vfmacc_mu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmacc_vv_f16m4_mu // CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmacc_vv_f16m4_mu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmacc.mask.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmacc.mask.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
// //
vfloat16m4_t test_vfmacc_vv_f16m4_mu(vbool4_t mask, vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) { vfloat16m4_t test_vfmacc_vv_f16m4_mu(vbool4_t mask, vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfmacc_mu(mask, vd, vs1, vs2, vl); return __riscv_vfmacc_mu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmacc_vf_f16m4_mu // CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmacc_vf_f16m4_mu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmacc.mask.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmacc.mask.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
// //
vfloat16m4_t test_vfmacc_vf_f16m4_mu(vbool4_t mask, vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) { vfloat16m4_t test_vfmacc_vf_f16m4_mu(vbool4_t mask, vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfmacc_mu(mask, vd, rs1, vs2, vl); return __riscv_vfmacc_mu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmacc_vv_f16m8_mu // CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmacc_vv_f16m8_mu
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmacc.mask.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmacc.mask.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
// //
vfloat16m8_t test_vfmacc_vv_f16m8_mu(vbool2_t mask, vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) { vfloat16m8_t test_vfmacc_vv_f16m8_mu(vbool2_t mask, vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfmacc_mu(mask, vd, vs1, vs2, vl); return __riscv_vfmacc_mu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmacc_vf_f16m8_mu // CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmacc_vf_f16m8_mu
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmacc.mask.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmacc.mask.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
// //
vfloat16m8_t test_vfmacc_vf_f16m8_mu(vbool2_t mask, vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) { vfloat16m8_t test_vfmacc_vf_f16m8_mu(vbool2_t mask, vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfmacc_mu(mask, vd, rs1, vs2, vl); return __riscv_vfmacc_mu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmacc_vv_f32mf2_mu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmacc_vv_f32mf2_mu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmacc.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmacc.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfmacc_vv_f32mf2_mu(vbool64_t mask, vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) { vfloat32mf2_t test_vfmacc_vv_f32mf2_mu(vbool64_t mask, vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfmacc_mu(mask, vd, vs1, vs2, vl); return __riscv_vfmacc_mu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmacc_vf_f32mf2_mu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmacc_vf_f32mf2_mu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmacc.mask.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmacc.mask.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfmacc_vf_f32mf2_mu(vbool64_t mask, vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) { vfloat32mf2_t test_vfmacc_vf_f32mf2_mu(vbool64_t mask, vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfmacc_mu(mask, vd, rs1, vs2, vl); return __riscv_vfmacc_mu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmacc_vv_f32m1_mu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmacc_vv_f32m1_mu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmacc.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmacc.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfmacc_vv_f32m1_mu(vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) { vfloat32m1_t test_vfmacc_vv_f32m1_mu(vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfmacc_mu(mask, vd, vs1, vs2, vl); return __riscv_vfmacc_mu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmacc_vf_f32m1_mu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmacc_vf_f32m1_mu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmacc.mask.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmacc.mask.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfmacc_vf_f32m1_mu(vbool32_t mask, vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) { vfloat32m1_t test_vfmacc_vf_f32m1_mu(vbool32_t mask, vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfmacc_mu(mask, vd, rs1, vs2, vl); return __riscv_vfmacc_mu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmacc_vv_f32m2_mu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmacc_vv_f32m2_mu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmacc.mask.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmacc.mask.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfmacc_vv_f32m2_mu(vbool16_t mask, vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) { vfloat32m2_t test_vfmacc_vv_f32m2_mu(vbool16_t mask, vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfmacc_mu(mask, vd, vs1, vs2, vl); return __riscv_vfmacc_mu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmacc_vf_f32m2_mu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmacc_vf_f32m2_mu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmacc.mask.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmacc.mask.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfmacc_vf_f32m2_mu(vbool16_t mask, vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) { vfloat32m2_t test_vfmacc_vf_f32m2_mu(vbool16_t mask, vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfmacc_mu(mask, vd, rs1, vs2, vl); return __riscv_vfmacc_mu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmacc_vv_f32m4_mu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmacc_vv_f32m4_mu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmacc.mask.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmacc.mask.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfmacc_vv_f32m4_mu(vbool8_t mask, vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) { vfloat32m4_t test_vfmacc_vv_f32m4_mu(vbool8_t mask, vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfmacc_mu(mask, vd, vs1, vs2, vl); return __riscv_vfmacc_mu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmacc_vf_f32m4_mu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmacc_vf_f32m4_mu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmacc.mask.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmacc.mask.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfmacc_vf_f32m4_mu(vbool8_t mask, vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) { vfloat32m4_t test_vfmacc_vf_f32m4_mu(vbool8_t mask, vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfmacc_mu(mask, vd, rs1, vs2, vl); return __riscv_vfmacc_mu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmacc_vv_f32m8_mu // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmacc_vv_f32m8_mu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmacc.mask.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmacc.mask.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfmacc_vv_f32m8_mu(vbool4_t mask, vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) { vfloat32m8_t test_vfmacc_vv_f32m8_mu(vbool4_t mask, vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfmacc_mu(mask, vd, vs1, vs2, vl); return __riscv_vfmacc_mu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmacc_vf_f32m8_mu // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmacc_vf_f32m8_mu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmacc.mask.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmacc.mask.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfmacc_vf_f32m8_mu(vbool4_t mask, vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) { vfloat32m8_t test_vfmacc_vf_f32m8_mu(vbool4_t mask, vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfmacc_mu(mask, vd, rs1, vs2, vl); return __riscv_vfmacc_mu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmacc_vv_f64m1_mu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmacc_vv_f64m1_mu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmacc.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmacc.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfmacc_vv_f64m1_mu(vbool64_t mask, vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) { vfloat64m1_t test_vfmacc_vv_f64m1_mu(vbool64_t mask, vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfmacc_mu(mask, vd, vs1, vs2, vl); return __riscv_vfmacc_mu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmacc_vf_f64m1_mu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmacc_vf_f64m1_mu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmacc.mask.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmacc.mask.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfmacc_vf_f64m1_mu(vbool64_t mask, vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) { vfloat64m1_t test_vfmacc_vf_f64m1_mu(vbool64_t mask, vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfmacc_mu(mask, vd, rs1, vs2, vl); return __riscv_vfmacc_mu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmacc_vv_f64m2_mu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmacc_vv_f64m2_mu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmacc.mask.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmacc.mask.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfmacc_vv_f64m2_mu(vbool32_t mask, vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) { vfloat64m2_t test_vfmacc_vv_f64m2_mu(vbool32_t mask, vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfmacc_mu(mask, vd, vs1, vs2, vl); return __riscv_vfmacc_mu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmacc_vf_f64m2_mu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmacc_vf_f64m2_mu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmacc.mask.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmacc.mask.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfmacc_vf_f64m2_mu(vbool32_t mask, vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) { vfloat64m2_t test_vfmacc_vf_f64m2_mu(vbool32_t mask, vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfmacc_mu(mask, vd, rs1, vs2, vl); return __riscv_vfmacc_mu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmacc_vv_f64m4_mu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmacc_vv_f64m4_mu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmacc.mask.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmacc.mask.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfmacc_vv_f64m4_mu(vbool16_t mask, vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) { vfloat64m4_t test_vfmacc_vv_f64m4_mu(vbool16_t mask, vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfmacc_mu(mask, vd, vs1, vs2, vl); return __riscv_vfmacc_mu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmacc_vf_f64m4_mu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmacc_vf_f64m4_mu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmacc.mask.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmacc.mask.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfmacc_vf_f64m4_mu(vbool16_t mask, vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) { vfloat64m4_t test_vfmacc_vf_f64m4_mu(vbool16_t mask, vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfmacc_mu(mask, vd, rs1, vs2, vl); return __riscv_vfmacc_mu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmacc_vv_f64m8_mu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmacc_vv_f64m8_mu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmacc.mask.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmacc.mask.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfmacc_vv_f64m8_mu(vbool8_t mask, vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) { vfloat64m8_t test_vfmacc_vv_f64m8_mu(vbool8_t mask, vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfmacc_mu(mask, vd, vs1, vs2, vl); return __riscv_vfmacc_mu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmacc_vf_f64m8_mu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmacc_vf_f64m8_mu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmacc.mask.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmacc.mask.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfmacc_vf_f64m8_mu(vbool8_t mask, vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) { vfloat64m8_t test_vfmacc_vf_f64m8_mu(vbool8_t mask, vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfmacc_mu(mask, vd, rs1, vs2, vl); return __riscv_vfmacc_mu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmacc_vv_f16mf4_rm_tu
// CHECK-RV64-SAME: (<vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmacc.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
//
vfloat16mf4_t test_vfmacc_vv_f16mf4_rm_tu(vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfmacc_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmacc_vf_f16mf4_rm_tu
// CHECK-RV64-SAME: (<vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmacc.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
//
vfloat16mf4_t test_vfmacc_vf_f16mf4_rm_tu(vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfmacc_tu(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmacc_vv_f16mf2_rm_tu
// CHECK-RV64-SAME: (<vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmacc.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
//
vfloat16mf2_t test_vfmacc_vv_f16mf2_rm_tu(vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfmacc_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmacc_vf_f16mf2_rm_tu
// CHECK-RV64-SAME: (<vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmacc.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
//
vfloat16mf2_t test_vfmacc_vf_f16mf2_rm_tu(vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfmacc_tu(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmacc_vv_f16m1_rm_tu
// CHECK-RV64-SAME: (<vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmacc.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfmacc_vv_f16m1_rm_tu(vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfmacc_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmacc_vf_f16m1_rm_tu
// CHECK-RV64-SAME: (<vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmacc.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfmacc_vf_f16m1_rm_tu(vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfmacc_tu(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmacc_vv_f16m2_rm_tu
// CHECK-RV64-SAME: (<vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmacc.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
//
vfloat16m2_t test_vfmacc_vv_f16m2_rm_tu(vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfmacc_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmacc_vf_f16m2_rm_tu
// CHECK-RV64-SAME: (<vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmacc.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
//
vfloat16m2_t test_vfmacc_vf_f16m2_rm_tu(vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfmacc_tu(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmacc_vv_f16m4_rm_tu
// CHECK-RV64-SAME: (<vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmacc.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
//
vfloat16m4_t test_vfmacc_vv_f16m4_rm_tu(vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfmacc_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmacc_vf_f16m4_rm_tu
// CHECK-RV64-SAME: (<vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmacc.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
//
vfloat16m4_t test_vfmacc_vf_f16m4_rm_tu(vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfmacc_tu(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmacc_vv_f16m8_rm_tu
// CHECK-RV64-SAME: (<vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmacc.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
//
vfloat16m8_t test_vfmacc_vv_f16m8_rm_tu(vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfmacc_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmacc_vf_f16m8_rm_tu
// CHECK-RV64-SAME: (<vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmacc.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
//
vfloat16m8_t test_vfmacc_vf_f16m8_rm_tu(vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfmacc_tu(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmacc_vv_f32mf2_rm_tu
// CHECK-RV64-SAME: (<vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmacc.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
//
vfloat32mf2_t test_vfmacc_vv_f32mf2_rm_tu(vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfmacc_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmacc_vf_f32mf2_rm_tu
// CHECK-RV64-SAME: (<vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmacc.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
//
vfloat32mf2_t test_vfmacc_vf_f32mf2_rm_tu(vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfmacc_tu(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmacc_vv_f32m1_rm_tu
// CHECK-RV64-SAME: (<vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmacc.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfmacc_vv_f32m1_rm_tu(vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfmacc_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmacc_vf_f32m1_rm_tu
// CHECK-RV64-SAME: (<vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmacc.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfmacc_vf_f32m1_rm_tu(vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfmacc_tu(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmacc_vv_f32m2_rm_tu
// CHECK-RV64-SAME: (<vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmacc.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
//
vfloat32m2_t test_vfmacc_vv_f32m2_rm_tu(vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfmacc_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmacc_vf_f32m2_rm_tu
// CHECK-RV64-SAME: (<vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmacc.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
//
vfloat32m2_t test_vfmacc_vf_f32m2_rm_tu(vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfmacc_tu(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmacc_vv_f32m4_rm_tu
// CHECK-RV64-SAME: (<vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmacc.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
//
vfloat32m4_t test_vfmacc_vv_f32m4_rm_tu(vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfmacc_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmacc_vf_f32m4_rm_tu
// CHECK-RV64-SAME: (<vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmacc.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
//
vfloat32m4_t test_vfmacc_vf_f32m4_rm_tu(vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfmacc_tu(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmacc_vv_f32m8_rm_tu
// CHECK-RV64-SAME: (<vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmacc.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
//
vfloat32m8_t test_vfmacc_vv_f32m8_rm_tu(vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfmacc_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmacc_vf_f32m8_rm_tu
// CHECK-RV64-SAME: (<vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmacc.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
//
vfloat32m8_t test_vfmacc_vf_f32m8_rm_tu(vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfmacc_tu(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmacc_vv_f64m1_rm_tu
// CHECK-RV64-SAME: (<vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmacc.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfmacc_vv_f64m1_rm_tu(vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfmacc_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmacc_vf_f64m1_rm_tu
// CHECK-RV64-SAME: (<vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmacc.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfmacc_vf_f64m1_rm_tu(vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfmacc_tu(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmacc_vv_f64m2_rm_tu
// CHECK-RV64-SAME: (<vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmacc.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
//
vfloat64m2_t test_vfmacc_vv_f64m2_rm_tu(vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfmacc_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmacc_vf_f64m2_rm_tu
// CHECK-RV64-SAME: (<vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmacc.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
//
vfloat64m2_t test_vfmacc_vf_f64m2_rm_tu(vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfmacc_tu(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmacc_vv_f64m4_rm_tu
// CHECK-RV64-SAME: (<vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmacc.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
//
vfloat64m4_t test_vfmacc_vv_f64m4_rm_tu(vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfmacc_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmacc_vf_f64m4_rm_tu
// CHECK-RV64-SAME: (<vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmacc.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
//
vfloat64m4_t test_vfmacc_vf_f64m4_rm_tu(vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfmacc_tu(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmacc_vv_f64m8_rm_tu
// CHECK-RV64-SAME: (<vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmacc.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
//
vfloat64m8_t test_vfmacc_vv_f64m8_rm_tu(vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfmacc_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmacc_vf_f64m8_rm_tu
// CHECK-RV64-SAME: (<vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmacc.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
//
vfloat64m8_t test_vfmacc_vf_f64m8_rm_tu(vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfmacc_tu(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmacc_vv_f16mf4_rm_tum
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmacc.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
//
vfloat16mf4_t test_vfmacc_vv_f16mf4_rm_tum(vbool64_t mask, vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfmacc_tum(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmacc_vf_f16mf4_rm_tum
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmacc.mask.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
//
vfloat16mf4_t test_vfmacc_vf_f16mf4_rm_tum(vbool64_t mask, vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfmacc_tum(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmacc_vv_f16mf2_rm_tum
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmacc.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
//
vfloat16mf2_t test_vfmacc_vv_f16mf2_rm_tum(vbool32_t mask, vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfmacc_tum(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmacc_vf_f16mf2_rm_tum
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmacc.mask.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
//
vfloat16mf2_t test_vfmacc_vf_f16mf2_rm_tum(vbool32_t mask, vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfmacc_tum(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmacc_vv_f16m1_rm_tum
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmacc.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfmacc_vv_f16m1_rm_tum(vbool16_t mask, vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfmacc_tum(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmacc_vf_f16m1_rm_tum
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmacc.mask.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfmacc_vf_f16m1_rm_tum(vbool16_t mask, vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfmacc_tum(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmacc_vv_f16m2_rm_tum
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmacc.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
//
vfloat16m2_t test_vfmacc_vv_f16m2_rm_tum(vbool8_t mask, vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfmacc_tum(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmacc_vf_f16m2_rm_tum
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmacc.mask.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
//
vfloat16m2_t test_vfmacc_vf_f16m2_rm_tum(vbool8_t mask, vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfmacc_tum(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmacc_vv_f16m4_rm_tum
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmacc.mask.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
//
vfloat16m4_t test_vfmacc_vv_f16m4_rm_tum(vbool4_t mask, vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfmacc_tum(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmacc_vf_f16m4_rm_tum
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmacc.mask.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
//
vfloat16m4_t test_vfmacc_vf_f16m4_rm_tum(vbool4_t mask, vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfmacc_tum(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmacc_vv_f16m8_rm_tum
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmacc.mask.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
//
vfloat16m8_t test_vfmacc_vv_f16m8_rm_tum(vbool2_t mask, vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfmacc_tum(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmacc_vf_f16m8_rm_tum
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmacc.mask.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
//
vfloat16m8_t test_vfmacc_vf_f16m8_rm_tum(vbool2_t mask, vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfmacc_tum(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmacc_vv_f32mf2_rm_tum
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmacc.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
//
vfloat32mf2_t test_vfmacc_vv_f32mf2_rm_tum(vbool64_t mask, vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfmacc_tum(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmacc_vf_f32mf2_rm_tum
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmacc.mask.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
//
vfloat32mf2_t test_vfmacc_vf_f32mf2_rm_tum(vbool64_t mask, vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfmacc_tum(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmacc_vv_f32m1_rm_tum
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmacc.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfmacc_vv_f32m1_rm_tum(vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfmacc_tum(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmacc_vf_f32m1_rm_tum
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmacc.mask.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfmacc_vf_f32m1_rm_tum(vbool32_t mask, vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfmacc_tum(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmacc_vv_f32m2_rm_tum
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmacc.mask.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
//
vfloat32m2_t test_vfmacc_vv_f32m2_rm_tum(vbool16_t mask, vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfmacc_tum(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmacc_vf_f32m2_rm_tum
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmacc.mask.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
//
vfloat32m2_t test_vfmacc_vf_f32m2_rm_tum(vbool16_t mask, vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfmacc_tum(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmacc_vv_f32m4_rm_tum
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmacc.mask.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
//
vfloat32m4_t test_vfmacc_vv_f32m4_rm_tum(vbool8_t mask, vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfmacc_tum(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmacc_vf_f32m4_rm_tum
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmacc.mask.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
//
vfloat32m4_t test_vfmacc_vf_f32m4_rm_tum(vbool8_t mask, vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfmacc_tum(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmacc_vv_f32m8_rm_tum
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmacc.mask.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
//
vfloat32m8_t test_vfmacc_vv_f32m8_rm_tum(vbool4_t mask, vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfmacc_tum(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmacc_vf_f32m8_rm_tum
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmacc.mask.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
//
vfloat32m8_t test_vfmacc_vf_f32m8_rm_tum(vbool4_t mask, vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfmacc_tum(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmacc_vv_f64m1_rm_tum
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmacc.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfmacc_vv_f64m1_rm_tum(vbool64_t mask, vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfmacc_tum(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmacc_vf_f64m1_rm_tum
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmacc.mask.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfmacc_vf_f64m1_rm_tum(vbool64_t mask, vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfmacc_tum(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmacc_vv_f64m2_rm_tum
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmacc.mask.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
//
vfloat64m2_t test_vfmacc_vv_f64m2_rm_tum(vbool32_t mask, vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfmacc_tum(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmacc_vf_f64m2_rm_tum
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmacc.mask.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
//
vfloat64m2_t test_vfmacc_vf_f64m2_rm_tum(vbool32_t mask, vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfmacc_tum(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmacc_vv_f64m4_rm_tum
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmacc.mask.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
//
vfloat64m4_t test_vfmacc_vv_f64m4_rm_tum(vbool16_t mask, vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfmacc_tum(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmacc_vf_f64m4_rm_tum
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmacc.mask.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
//
vfloat64m4_t test_vfmacc_vf_f64m4_rm_tum(vbool16_t mask, vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfmacc_tum(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmacc_vv_f64m8_rm_tum
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmacc.mask.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
//
vfloat64m8_t test_vfmacc_vv_f64m8_rm_tum(vbool8_t mask, vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfmacc_tum(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmacc_vf_f64m8_rm_tum
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmacc.mask.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
//
vfloat64m8_t test_vfmacc_vf_f64m8_rm_tum(vbool8_t mask, vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfmacc_tum(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmacc_vv_f16mf4_rm_tumu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmacc.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
//
vfloat16mf4_t test_vfmacc_vv_f16mf4_rm_tumu(vbool64_t mask, vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfmacc_tumu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmacc_vf_f16mf4_rm_tumu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmacc.mask.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
//
vfloat16mf4_t test_vfmacc_vf_f16mf4_rm_tumu(vbool64_t mask, vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfmacc_tumu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmacc_vv_f16mf2_rm_tumu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmacc.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
//
vfloat16mf2_t test_vfmacc_vv_f16mf2_rm_tumu(vbool32_t mask, vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfmacc_tumu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmacc_vf_f16mf2_rm_tumu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmacc.mask.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
//
vfloat16mf2_t test_vfmacc_vf_f16mf2_rm_tumu(vbool32_t mask, vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfmacc_tumu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmacc_vv_f16m1_rm_tumu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmacc.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfmacc_vv_f16m1_rm_tumu(vbool16_t mask, vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfmacc_tumu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmacc_vf_f16m1_rm_tumu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmacc.mask.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfmacc_vf_f16m1_rm_tumu(vbool16_t mask, vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfmacc_tumu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmacc_vv_f16m2_rm_tumu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmacc.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
//
vfloat16m2_t test_vfmacc_vv_f16m2_rm_tumu(vbool8_t mask, vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfmacc_tumu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmacc_vf_f16m2_rm_tumu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmacc.mask.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
//
vfloat16m2_t test_vfmacc_vf_f16m2_rm_tumu(vbool8_t mask, vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfmacc_tumu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmacc_vv_f16m4_rm_tumu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmacc.mask.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
//
vfloat16m4_t test_vfmacc_vv_f16m4_rm_tumu(vbool4_t mask, vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfmacc_tumu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmacc_vf_f16m4_rm_tumu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmacc.mask.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
//
vfloat16m4_t test_vfmacc_vf_f16m4_rm_tumu(vbool4_t mask, vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfmacc_tumu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmacc_vv_f16m8_rm_tumu
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmacc.mask.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
//
vfloat16m8_t test_vfmacc_vv_f16m8_rm_tumu(vbool2_t mask, vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfmacc_tumu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmacc_vf_f16m8_rm_tumu
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmacc.mask.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
//
vfloat16m8_t test_vfmacc_vf_f16m8_rm_tumu(vbool2_t mask, vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfmacc_tumu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmacc_vv_f32mf2_rm_tumu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmacc.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
//
vfloat32mf2_t test_vfmacc_vv_f32mf2_rm_tumu(vbool64_t mask, vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfmacc_tumu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmacc_vf_f32mf2_rm_tumu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmacc.mask.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
//
vfloat32mf2_t test_vfmacc_vf_f32mf2_rm_tumu(vbool64_t mask, vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfmacc_tumu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmacc_vv_f32m1_rm_tumu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmacc.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfmacc_vv_f32m1_rm_tumu(vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfmacc_tumu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmacc_vf_f32m1_rm_tumu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmacc.mask.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfmacc_vf_f32m1_rm_tumu(vbool32_t mask, vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfmacc_tumu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmacc_vv_f32m2_rm_tumu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmacc.mask.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
//
vfloat32m2_t test_vfmacc_vv_f32m2_rm_tumu(vbool16_t mask, vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfmacc_tumu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmacc_vf_f32m2_rm_tumu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmacc.mask.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
//
vfloat32m2_t test_vfmacc_vf_f32m2_rm_tumu(vbool16_t mask, vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfmacc_tumu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmacc_vv_f32m4_rm_tumu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmacc.mask.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
//
vfloat32m4_t test_vfmacc_vv_f32m4_rm_tumu(vbool8_t mask, vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfmacc_tumu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmacc_vf_f32m4_rm_tumu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmacc.mask.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
//
vfloat32m4_t test_vfmacc_vf_f32m4_rm_tumu(vbool8_t mask, vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfmacc_tumu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmacc_vv_f32m8_rm_tumu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmacc.mask.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
//
vfloat32m8_t test_vfmacc_vv_f32m8_rm_tumu(vbool4_t mask, vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfmacc_tumu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmacc_vf_f32m8_rm_tumu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmacc.mask.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
//
vfloat32m8_t test_vfmacc_vf_f32m8_rm_tumu(vbool4_t mask, vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfmacc_tumu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmacc_vv_f64m1_rm_tumu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmacc.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfmacc_vv_f64m1_rm_tumu(vbool64_t mask, vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfmacc_tumu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmacc_vf_f64m1_rm_tumu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmacc.mask.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfmacc_vf_f64m1_rm_tumu(vbool64_t mask, vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfmacc_tumu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmacc_vv_f64m2_rm_tumu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmacc.mask.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
//
vfloat64m2_t test_vfmacc_vv_f64m2_rm_tumu(vbool32_t mask, vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfmacc_tumu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmacc_vf_f64m2_rm_tumu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmacc.mask.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
//
vfloat64m2_t test_vfmacc_vf_f64m2_rm_tumu(vbool32_t mask, vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfmacc_tumu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmacc_vv_f64m4_rm_tumu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmacc.mask.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
//
vfloat64m4_t test_vfmacc_vv_f64m4_rm_tumu(vbool16_t mask, vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfmacc_tumu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmacc_vf_f64m4_rm_tumu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmacc.mask.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
//
vfloat64m4_t test_vfmacc_vf_f64m4_rm_tumu(vbool16_t mask, vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfmacc_tumu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmacc_vv_f64m8_rm_tumu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmacc.mask.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
//
vfloat64m8_t test_vfmacc_vv_f64m8_rm_tumu(vbool8_t mask, vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfmacc_tumu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmacc_vf_f64m8_rm_tumu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmacc.mask.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
//
vfloat64m8_t test_vfmacc_vf_f64m8_rm_tumu(vbool8_t mask, vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfmacc_tumu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmacc_vv_f16mf4_rm_mu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmacc.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
//
vfloat16mf4_t test_vfmacc_vv_f16mf4_rm_mu(vbool64_t mask, vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfmacc_mu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmacc_vf_f16mf4_rm_mu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmacc.mask.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
//
vfloat16mf4_t test_vfmacc_vf_f16mf4_rm_mu(vbool64_t mask, vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfmacc_mu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmacc_vv_f16mf2_rm_mu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmacc.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
//
vfloat16mf2_t test_vfmacc_vv_f16mf2_rm_mu(vbool32_t mask, vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfmacc_mu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmacc_vf_f16mf2_rm_mu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmacc.mask.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
//
vfloat16mf2_t test_vfmacc_vf_f16mf2_rm_mu(vbool32_t mask, vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfmacc_mu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmacc_vv_f16m1_rm_mu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmacc.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfmacc_vv_f16m1_rm_mu(vbool16_t mask, vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfmacc_mu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmacc_vf_f16m1_rm_mu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmacc.mask.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfmacc_vf_f16m1_rm_mu(vbool16_t mask, vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfmacc_mu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmacc_vv_f16m2_rm_mu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmacc.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
//
vfloat16m2_t test_vfmacc_vv_f16m2_rm_mu(vbool8_t mask, vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfmacc_mu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmacc_vf_f16m2_rm_mu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmacc.mask.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
//
vfloat16m2_t test_vfmacc_vf_f16m2_rm_mu(vbool8_t mask, vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfmacc_mu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmacc_vv_f16m4_rm_mu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmacc.mask.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
//
vfloat16m4_t test_vfmacc_vv_f16m4_rm_mu(vbool4_t mask, vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfmacc_mu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmacc_vf_f16m4_rm_mu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmacc.mask.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
//
vfloat16m4_t test_vfmacc_vf_f16m4_rm_mu(vbool4_t mask, vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfmacc_mu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmacc_vv_f16m8_rm_mu
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmacc.mask.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
//
vfloat16m8_t test_vfmacc_vv_f16m8_rm_mu(vbool2_t mask, vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfmacc_mu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmacc_vf_f16m8_rm_mu
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmacc.mask.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
//
vfloat16m8_t test_vfmacc_vf_f16m8_rm_mu(vbool2_t mask, vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfmacc_mu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmacc_vv_f32mf2_rm_mu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmacc.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
//
vfloat32mf2_t test_vfmacc_vv_f32mf2_rm_mu(vbool64_t mask, vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfmacc_mu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmacc_vf_f32mf2_rm_mu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmacc.mask.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
//
vfloat32mf2_t test_vfmacc_vf_f32mf2_rm_mu(vbool64_t mask, vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfmacc_mu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmacc_vv_f32m1_rm_mu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmacc.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfmacc_vv_f32m1_rm_mu(vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfmacc_mu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmacc_vf_f32m1_rm_mu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmacc.mask.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfmacc_vf_f32m1_rm_mu(vbool32_t mask, vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfmacc_mu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmacc_vv_f32m2_rm_mu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmacc.mask.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
//
vfloat32m2_t test_vfmacc_vv_f32m2_rm_mu(vbool16_t mask, vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfmacc_mu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmacc_vf_f32m2_rm_mu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmacc.mask.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
//
vfloat32m2_t test_vfmacc_vf_f32m2_rm_mu(vbool16_t mask, vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfmacc_mu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmacc_vv_f32m4_rm_mu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmacc.mask.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
//
vfloat32m4_t test_vfmacc_vv_f32m4_rm_mu(vbool8_t mask, vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfmacc_mu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmacc_vf_f32m4_rm_mu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmacc.mask.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
//
vfloat32m4_t test_vfmacc_vf_f32m4_rm_mu(vbool8_t mask, vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfmacc_mu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmacc_vv_f32m8_rm_mu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmacc.mask.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
//
vfloat32m8_t test_vfmacc_vv_f32m8_rm_mu(vbool4_t mask, vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfmacc_mu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmacc_vf_f32m8_rm_mu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmacc.mask.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
//
vfloat32m8_t test_vfmacc_vf_f32m8_rm_mu(vbool4_t mask, vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfmacc_mu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmacc_vv_f64m1_rm_mu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmacc.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfmacc_vv_f64m1_rm_mu(vbool64_t mask, vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfmacc_mu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmacc_vf_f64m1_rm_mu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmacc.mask.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfmacc_vf_f64m1_rm_mu(vbool64_t mask, vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfmacc_mu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmacc_vv_f64m2_rm_mu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmacc.mask.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
//
vfloat64m2_t test_vfmacc_vv_f64m2_rm_mu(vbool32_t mask, vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfmacc_mu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmacc_vf_f64m2_rm_mu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmacc.mask.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
//
vfloat64m2_t test_vfmacc_vf_f64m2_rm_mu(vbool32_t mask, vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfmacc_mu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmacc_vv_f64m4_rm_mu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmacc.mask.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
//
vfloat64m4_t test_vfmacc_vv_f64m4_rm_mu(vbool16_t mask, vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfmacc_mu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmacc_vf_f64m4_rm_mu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmacc.mask.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
//
vfloat64m4_t test_vfmacc_vf_f64m4_rm_mu(vbool16_t mask, vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfmacc_mu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmacc_vv_f64m8_rm_mu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmacc.mask.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
//
vfloat64m8_t test_vfmacc_vv_f64m8_rm_mu(vbool8_t mask, vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfmacc_mu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmacc_vf_f64m8_rm_mu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmacc.mask.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
//
vfloat64m8_t test_vfmacc_vf_f64m8_rm_mu(vbool8_t mask, vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfmacc_mu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}

clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmadd.c

// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target // REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh \ // RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh \
// RUN: -target-feature +experimental-zvfh -disable-O0-optnone \ // RUN: -target-feature +experimental-zvfh -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ // RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s // RUN: FileCheck --check-prefix=CHECK-RV64 %s
#include <riscv_vector.h> #include <riscv_vector.h>
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmadd_vv_f16mf4_tu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmadd_vv_f16mf4_tu
// CHECK-RV64-SAME: (<vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK-RV64-SAME: (<vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmadd.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmadd.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
// //
vfloat16mf4_t test_vfmadd_vv_f16mf4_tu(vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) { vfloat16mf4_t test_vfmadd_vv_f16mf4_tu(vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfmadd_tu(vd, vs1, vs2, vl); return __riscv_vfmadd_tu(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmadd_vf_f16mf4_tu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmadd_vf_f16mf4_tu
// CHECK-RV64-SAME: (<vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmadd.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmadd.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
// //
vfloat16mf4_t test_vfmadd_vf_f16mf4_tu(vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) { vfloat16mf4_t test_vfmadd_vf_f16mf4_tu(vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfmadd_tu(vd, rs1, vs2, vl); return __riscv_vfmadd_tu(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmadd_vv_f16mf2_tu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmadd_vv_f16mf2_tu
// CHECK-RV64-SAME: (<vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmadd.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmadd.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
// //
vfloat16mf2_t test_vfmadd_vv_f16mf2_tu(vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) { vfloat16mf2_t test_vfmadd_vv_f16mf2_tu(vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfmadd_tu(vd, vs1, vs2, vl); return __riscv_vfmadd_tu(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmadd_vf_f16mf2_tu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmadd_vf_f16mf2_tu
// CHECK-RV64-SAME: (<vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmadd.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmadd.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
// //
vfloat16mf2_t test_vfmadd_vf_f16mf2_tu(vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) { vfloat16mf2_t test_vfmadd_vf_f16mf2_tu(vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfmadd_tu(vd, rs1, vs2, vl); return __riscv_vfmadd_tu(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmadd_vv_f16m1_tu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmadd_vv_f16m1_tu
// CHECK-RV64-SAME: (<vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmadd.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmadd.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
// //
vfloat16m1_t test_vfmadd_vv_f16m1_tu(vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) { vfloat16m1_t test_vfmadd_vv_f16m1_tu(vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfmadd_tu(vd, vs1, vs2, vl); return __riscv_vfmadd_tu(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmadd_vf_f16m1_tu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmadd_vf_f16m1_tu
// CHECK-RV64-SAME: (<vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmadd.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmadd.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
// //
vfloat16m1_t test_vfmadd_vf_f16m1_tu(vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) { vfloat16m1_t test_vfmadd_vf_f16m1_tu(vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfmadd_tu(vd, rs1, vs2, vl); return __riscv_vfmadd_tu(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmadd_vv_f16m2_tu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmadd_vv_f16m2_tu
// CHECK-RV64-SAME: (<vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmadd.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmadd.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
// //
vfloat16m2_t test_vfmadd_vv_f16m2_tu(vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) { vfloat16m2_t test_vfmadd_vv_f16m2_tu(vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfmadd_tu(vd, vs1, vs2, vl); return __riscv_vfmadd_tu(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmadd_vf_f16m2_tu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmadd_vf_f16m2_tu
// CHECK-RV64-SAME: (<vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmadd.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmadd.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
// //
vfloat16m2_t test_vfmadd_vf_f16m2_tu(vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) { vfloat16m2_t test_vfmadd_vf_f16m2_tu(vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfmadd_tu(vd, rs1, vs2, vl); return __riscv_vfmadd_tu(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmadd_vv_f16m4_tu // CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmadd_vv_f16m4_tu
// CHECK-RV64-SAME: (<vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmadd.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmadd.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
// //
vfloat16m4_t test_vfmadd_vv_f16m4_tu(vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) { vfloat16m4_t test_vfmadd_vv_f16m4_tu(vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfmadd_tu(vd, vs1, vs2, vl); return __riscv_vfmadd_tu(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmadd_vf_f16m4_tu // CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmadd_vf_f16m4_tu
// CHECK-RV64-SAME: (<vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmadd.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmadd.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
// //
vfloat16m4_t test_vfmadd_vf_f16m4_tu(vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) { vfloat16m4_t test_vfmadd_vf_f16m4_tu(vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfmadd_tu(vd, rs1, vs2, vl); return __riscv_vfmadd_tu(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmadd_vv_f16m8_tu // CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmadd_vv_f16m8_tu
// CHECK-RV64-SAME: (<vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmadd.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmadd.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
// //
vfloat16m8_t test_vfmadd_vv_f16m8_tu(vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) { vfloat16m8_t test_vfmadd_vv_f16m8_tu(vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfmadd_tu(vd, vs1, vs2, vl); return __riscv_vfmadd_tu(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmadd_vf_f16m8_tu // CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmadd_vf_f16m8_tu
// CHECK-RV64-SAME: (<vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmadd.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmadd.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
// //
vfloat16m8_t test_vfmadd_vf_f16m8_tu(vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) { vfloat16m8_t test_vfmadd_vf_f16m8_tu(vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfmadd_tu(vd, rs1, vs2, vl); return __riscv_vfmadd_tu(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmadd_vv_f32mf2_tu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmadd_vv_f32mf2_tu
// CHECK-RV64-SAME: (<vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmadd.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmadd.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfmadd_vv_f32mf2_tu(vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) { vfloat32mf2_t test_vfmadd_vv_f32mf2_tu(vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfmadd_tu(vd, vs1, vs2, vl); return __riscv_vfmadd_tu(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmadd_vf_f32mf2_tu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmadd_vf_f32mf2_tu
// CHECK-RV64-SAME: (<vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmadd.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmadd.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfmadd_vf_f32mf2_tu(vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) { vfloat32mf2_t test_vfmadd_vf_f32mf2_tu(vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfmadd_tu(vd, rs1, vs2, vl); return __riscv_vfmadd_tu(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmadd_vv_f32m1_tu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmadd_vv_f32m1_tu
// CHECK-RV64-SAME: (<vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmadd.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmadd.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfmadd_vv_f32m1_tu(vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) { vfloat32m1_t test_vfmadd_vv_f32m1_tu(vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfmadd_tu(vd, vs1, vs2, vl); return __riscv_vfmadd_tu(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmadd_vf_f32m1_tu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmadd_vf_f32m1_tu
// CHECK-RV64-SAME: (<vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmadd.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmadd.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfmadd_vf_f32m1_tu(vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) { vfloat32m1_t test_vfmadd_vf_f32m1_tu(vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfmadd_tu(vd, rs1, vs2, vl); return __riscv_vfmadd_tu(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmadd_vv_f32m2_tu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmadd_vv_f32m2_tu
// CHECK-RV64-SAME: (<vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmadd.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmadd.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfmadd_vv_f32m2_tu(vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) { vfloat32m2_t test_vfmadd_vv_f32m2_tu(vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfmadd_tu(vd, vs1, vs2, vl); return __riscv_vfmadd_tu(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmadd_vf_f32m2_tu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmadd_vf_f32m2_tu
// CHECK-RV64-SAME: (<vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmadd.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmadd.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfmadd_vf_f32m2_tu(vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) { vfloat32m2_t test_vfmadd_vf_f32m2_tu(vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfmadd_tu(vd, rs1, vs2, vl); return __riscv_vfmadd_tu(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmadd_vv_f32m4_tu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmadd_vv_f32m4_tu
// CHECK-RV64-SAME: (<vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmadd.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmadd.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfmadd_vv_f32m4_tu(vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) { vfloat32m4_t test_vfmadd_vv_f32m4_tu(vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfmadd_tu(vd, vs1, vs2, vl); return __riscv_vfmadd_tu(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmadd_vf_f32m4_tu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmadd_vf_f32m4_tu
// CHECK-RV64-SAME: (<vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmadd.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmadd.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfmadd_vf_f32m4_tu(vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) { vfloat32m4_t test_vfmadd_vf_f32m4_tu(vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfmadd_tu(vd, rs1, vs2, vl); return __riscv_vfmadd_tu(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmadd_vv_f32m8_tu // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmadd_vv_f32m8_tu
// CHECK-RV64-SAME: (<vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmadd.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmadd.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfmadd_vv_f32m8_tu(vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) { vfloat32m8_t test_vfmadd_vv_f32m8_tu(vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfmadd_tu(vd, vs1, vs2, vl); return __riscv_vfmadd_tu(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmadd_vf_f32m8_tu // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmadd_vf_f32m8_tu
// CHECK-RV64-SAME: (<vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmadd.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmadd.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfmadd_vf_f32m8_tu(vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) { vfloat32m8_t test_vfmadd_vf_f32m8_tu(vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfmadd_tu(vd, rs1, vs2, vl); return __riscv_vfmadd_tu(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmadd_vv_f64m1_tu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmadd_vv_f64m1_tu
// CHECK-RV64-SAME: (<vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmadd.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmadd.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfmadd_vv_f64m1_tu(vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) { vfloat64m1_t test_vfmadd_vv_f64m1_tu(vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfmadd_tu(vd, vs1, vs2, vl); return __riscv_vfmadd_tu(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmadd_vf_f64m1_tu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmadd_vf_f64m1_tu
// CHECK-RV64-SAME: (<vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmadd.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmadd.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfmadd_vf_f64m1_tu(vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) { vfloat64m1_t test_vfmadd_vf_f64m1_tu(vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfmadd_tu(vd, rs1, vs2, vl); return __riscv_vfmadd_tu(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmadd_vv_f64m2_tu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmadd_vv_f64m2_tu
// CHECK-RV64-SAME: (<vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmadd.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmadd.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfmadd_vv_f64m2_tu(vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) { vfloat64m2_t test_vfmadd_vv_f64m2_tu(vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfmadd_tu(vd, vs1, vs2, vl); return __riscv_vfmadd_tu(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmadd_vf_f64m2_tu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmadd_vf_f64m2_tu
// CHECK-RV64-SAME: (<vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmadd.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmadd.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfmadd_vf_f64m2_tu(vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) { vfloat64m2_t test_vfmadd_vf_f64m2_tu(vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfmadd_tu(vd, rs1, vs2, vl); return __riscv_vfmadd_tu(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmadd_vv_f64m4_tu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmadd_vv_f64m4_tu
// CHECK-RV64-SAME: (<vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmadd.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmadd.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfmadd_vv_f64m4_tu(vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) { vfloat64m4_t test_vfmadd_vv_f64m4_tu(vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfmadd_tu(vd, vs1, vs2, vl); return __riscv_vfmadd_tu(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmadd_vf_f64m4_tu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmadd_vf_f64m4_tu
// CHECK-RV64-SAME: (<vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmadd.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmadd.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfmadd_vf_f64m4_tu(vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) { vfloat64m4_t test_vfmadd_vf_f64m4_tu(vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfmadd_tu(vd, rs1, vs2, vl); return __riscv_vfmadd_tu(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmadd_vv_f64m8_tu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmadd_vv_f64m8_tu
// CHECK-RV64-SAME: (<vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmadd.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmadd.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfmadd_vv_f64m8_tu(vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) { vfloat64m8_t test_vfmadd_vv_f64m8_tu(vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfmadd_tu(vd, vs1, vs2, vl); return __riscv_vfmadd_tu(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmadd_vf_f64m8_tu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmadd_vf_f64m8_tu
// CHECK-RV64-SAME: (<vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmadd.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmadd.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfmadd_vf_f64m8_tu(vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) { vfloat64m8_t test_vfmadd_vf_f64m8_tu(vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfmadd_tu(vd, rs1, vs2, vl); return __riscv_vfmadd_tu(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmadd_vv_f16mf4_tum // CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmadd_vv_f16mf4_tum
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmadd.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmadd.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
// //
vfloat16mf4_t test_vfmadd_vv_f16mf4_tum(vbool64_t mask, vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) { vfloat16mf4_t test_vfmadd_vv_f16mf4_tum(vbool64_t mask, vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfmadd_tum(mask, vd, vs1, vs2, vl); return __riscv_vfmadd_tum(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmadd_vf_f16mf4_tum // CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmadd_vf_f16mf4_tum
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmadd.mask.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmadd.mask.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
// //
vfloat16mf4_t test_vfmadd_vf_f16mf4_tum(vbool64_t mask, vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) { vfloat16mf4_t test_vfmadd_vf_f16mf4_tum(vbool64_t mask, vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfmadd_tum(mask, vd, rs1, vs2, vl); return __riscv_vfmadd_tum(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmadd_vv_f16mf2_tum // CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmadd_vv_f16mf2_tum
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmadd.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmadd.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
// //
vfloat16mf2_t test_vfmadd_vv_f16mf2_tum(vbool32_t mask, vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) { vfloat16mf2_t test_vfmadd_vv_f16mf2_tum(vbool32_t mask, vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfmadd_tum(mask, vd, vs1, vs2, vl); return __riscv_vfmadd_tum(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmadd_vf_f16mf2_tum // CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmadd_vf_f16mf2_tum
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmadd.mask.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmadd.mask.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
// //
vfloat16mf2_t test_vfmadd_vf_f16mf2_tum(vbool32_t mask, vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) { vfloat16mf2_t test_vfmadd_vf_f16mf2_tum(vbool32_t mask, vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfmadd_tum(mask, vd, rs1, vs2, vl); return __riscv_vfmadd_tum(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmadd_vv_f16m1_tum // CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmadd_vv_f16m1_tum
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmadd.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmadd.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
// //
vfloat16m1_t test_vfmadd_vv_f16m1_tum(vbool16_t mask, vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) { vfloat16m1_t test_vfmadd_vv_f16m1_tum(vbool16_t mask, vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfmadd_tum(mask, vd, vs1, vs2, vl); return __riscv_vfmadd_tum(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmadd_vf_f16m1_tum // CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmadd_vf_f16m1_tum
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmadd.mask.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmadd.mask.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
// //
vfloat16m1_t test_vfmadd_vf_f16m1_tum(vbool16_t mask, vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) { vfloat16m1_t test_vfmadd_vf_f16m1_tum(vbool16_t mask, vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfmadd_tum(mask, vd, rs1, vs2, vl); return __riscv_vfmadd_tum(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmadd_vv_f16m2_tum // CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmadd_vv_f16m2_tum
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmadd.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmadd.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
// //
vfloat16m2_t test_vfmadd_vv_f16m2_tum(vbool8_t mask, vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) { vfloat16m2_t test_vfmadd_vv_f16m2_tum(vbool8_t mask, vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfmadd_tum(mask, vd, vs1, vs2, vl); return __riscv_vfmadd_tum(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmadd_vf_f16m2_tum // CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmadd_vf_f16m2_tum
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmadd.mask.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmadd.mask.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
// //
vfloat16m2_t test_vfmadd_vf_f16m2_tum(vbool8_t mask, vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) { vfloat16m2_t test_vfmadd_vf_f16m2_tum(vbool8_t mask, vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfmadd_tum(mask, vd, rs1, vs2, vl); return __riscv_vfmadd_tum(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmadd_vv_f16m4_tum // CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmadd_vv_f16m4_tum
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmadd.mask.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmadd.mask.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
// //
vfloat16m4_t test_vfmadd_vv_f16m4_tum(vbool4_t mask, vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) { vfloat16m4_t test_vfmadd_vv_f16m4_tum(vbool4_t mask, vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfmadd_tum(mask, vd, vs1, vs2, vl); return __riscv_vfmadd_tum(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmadd_vf_f16m4_tum // CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmadd_vf_f16m4_tum
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmadd.mask.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmadd.mask.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
// //
vfloat16m4_t test_vfmadd_vf_f16m4_tum(vbool4_t mask, vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) { vfloat16m4_t test_vfmadd_vf_f16m4_tum(vbool4_t mask, vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfmadd_tum(mask, vd, rs1, vs2, vl); return __riscv_vfmadd_tum(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmadd_vv_f16m8_tum // CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmadd_vv_f16m8_tum
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmadd.mask.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmadd.mask.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
// //
vfloat16m8_t test_vfmadd_vv_f16m8_tum(vbool2_t mask, vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) { vfloat16m8_t test_vfmadd_vv_f16m8_tum(vbool2_t mask, vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfmadd_tum(mask, vd, vs1, vs2, vl); return __riscv_vfmadd_tum(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmadd_vf_f16m8_tum // CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmadd_vf_f16m8_tum
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmadd.mask.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmadd.mask.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
// //
vfloat16m8_t test_vfmadd_vf_f16m8_tum(vbool2_t mask, vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) { vfloat16m8_t test_vfmadd_vf_f16m8_tum(vbool2_t mask, vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfmadd_tum(mask, vd, rs1, vs2, vl); return __riscv_vfmadd_tum(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmadd_vv_f32mf2_tum // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmadd_vv_f32mf2_tum
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmadd.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmadd.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfmadd_vv_f32mf2_tum(vbool64_t mask, vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) { vfloat32mf2_t test_vfmadd_vv_f32mf2_tum(vbool64_t mask, vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfmadd_tum(mask, vd, vs1, vs2, vl); return __riscv_vfmadd_tum(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmadd_vf_f32mf2_tum // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmadd_vf_f32mf2_tum
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmadd.mask.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmadd.mask.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfmadd_vf_f32mf2_tum(vbool64_t mask, vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) { vfloat32mf2_t test_vfmadd_vf_f32mf2_tum(vbool64_t mask, vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfmadd_tum(mask, vd, rs1, vs2, vl); return __riscv_vfmadd_tum(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmadd_vv_f32m1_tum // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmadd_vv_f32m1_tum
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmadd.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmadd.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfmadd_vv_f32m1_tum(vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) { vfloat32m1_t test_vfmadd_vv_f32m1_tum(vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfmadd_tum(mask, vd, vs1, vs2, vl); return __riscv_vfmadd_tum(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmadd_vf_f32m1_tum // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmadd_vf_f32m1_tum
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmadd.mask.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmadd.mask.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfmadd_vf_f32m1_tum(vbool32_t mask, vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) { vfloat32m1_t test_vfmadd_vf_f32m1_tum(vbool32_t mask, vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfmadd_tum(mask, vd, rs1, vs2, vl); return __riscv_vfmadd_tum(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmadd_vv_f32m2_tum // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmadd_vv_f32m2_tum
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmadd.mask.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmadd.mask.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfmadd_vv_f32m2_tum(vbool16_t mask, vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) { vfloat32m2_t test_vfmadd_vv_f32m2_tum(vbool16_t mask, vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfmadd_tum(mask, vd, vs1, vs2, vl); return __riscv_vfmadd_tum(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmadd_vf_f32m2_tum // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmadd_vf_f32m2_tum
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmadd.mask.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmadd.mask.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfmadd_vf_f32m2_tum(vbool16_t mask, vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) { vfloat32m2_t test_vfmadd_vf_f32m2_tum(vbool16_t mask, vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfmadd_tum(mask, vd, rs1, vs2, vl); return __riscv_vfmadd_tum(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmadd_vv_f32m4_tum // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmadd_vv_f32m4_tum
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmadd.mask.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmadd.mask.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfmadd_vv_f32m4_tum(vbool8_t mask, vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) { vfloat32m4_t test_vfmadd_vv_f32m4_tum(vbool8_t mask, vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfmadd_tum(mask, vd, vs1, vs2, vl); return __riscv_vfmadd_tum(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmadd_vf_f32m4_tum // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmadd_vf_f32m4_tum
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmadd.mask.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmadd.mask.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfmadd_vf_f32m4_tum(vbool8_t mask, vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) { vfloat32m4_t test_vfmadd_vf_f32m4_tum(vbool8_t mask, vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfmadd_tum(mask, vd, rs1, vs2, vl); return __riscv_vfmadd_tum(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmadd_vv_f32m8_tum // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmadd_vv_f32m8_tum
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmadd.mask.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmadd.mask.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfmadd_vv_f32m8_tum(vbool4_t mask, vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) { vfloat32m8_t test_vfmadd_vv_f32m8_tum(vbool4_t mask, vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfmadd_tum(mask, vd, vs1, vs2, vl); return __riscv_vfmadd_tum(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmadd_vf_f32m8_tum // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmadd_vf_f32m8_tum
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmadd.mask.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmadd.mask.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfmadd_vf_f32m8_tum(vbool4_t mask, vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) { vfloat32m8_t test_vfmadd_vf_f32m8_tum(vbool4_t mask, vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfmadd_tum(mask, vd, rs1, vs2, vl); return __riscv_vfmadd_tum(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmadd_vv_f64m1_tum // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmadd_vv_f64m1_tum
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmadd.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmadd.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfmadd_vv_f64m1_tum(vbool64_t mask, vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) { vfloat64m1_t test_vfmadd_vv_f64m1_tum(vbool64_t mask, vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfmadd_tum(mask, vd, vs1, vs2, vl); return __riscv_vfmadd_tum(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmadd_vf_f64m1_tum // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmadd_vf_f64m1_tum
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmadd.mask.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmadd.mask.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfmadd_vf_f64m1_tum(vbool64_t mask, vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) { vfloat64m1_t test_vfmadd_vf_f64m1_tum(vbool64_t mask, vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfmadd_tum(mask, vd, rs1, vs2, vl); return __riscv_vfmadd_tum(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmadd_vv_f64m2_tum // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmadd_vv_f64m2_tum
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmadd.mask.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmadd.mask.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfmadd_vv_f64m2_tum(vbool32_t mask, vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) { vfloat64m2_t test_vfmadd_vv_f64m2_tum(vbool32_t mask, vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfmadd_tum(mask, vd, vs1, vs2, vl); return __riscv_vfmadd_tum(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmadd_vf_f64m2_tum // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmadd_vf_f64m2_tum
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmadd.mask.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmadd.mask.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfmadd_vf_f64m2_tum(vbool32_t mask, vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) { vfloat64m2_t test_vfmadd_vf_f64m2_tum(vbool32_t mask, vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfmadd_tum(mask, vd, rs1, vs2, vl); return __riscv_vfmadd_tum(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmadd_vv_f64m4_tum // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmadd_vv_f64m4_tum
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmadd.mask.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmadd.mask.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfmadd_vv_f64m4_tum(vbool16_t mask, vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) { vfloat64m4_t test_vfmadd_vv_f64m4_tum(vbool16_t mask, vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfmadd_tum(mask, vd, vs1, vs2, vl); return __riscv_vfmadd_tum(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmadd_vf_f64m4_tum // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmadd_vf_f64m4_tum
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmadd.mask.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmadd.mask.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfmadd_vf_f64m4_tum(vbool16_t mask, vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) { vfloat64m4_t test_vfmadd_vf_f64m4_tum(vbool16_t mask, vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfmadd_tum(mask, vd, rs1, vs2, vl); return __riscv_vfmadd_tum(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmadd_vv_f64m8_tum // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmadd_vv_f64m8_tum
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmadd.mask.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmadd.mask.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfmadd_vv_f64m8_tum(vbool8_t mask, vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) { vfloat64m8_t test_vfmadd_vv_f64m8_tum(vbool8_t mask, vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfmadd_tum(mask, vd, vs1, vs2, vl); return __riscv_vfmadd_tum(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmadd_vf_f64m8_tum // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmadd_vf_f64m8_tum
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmadd.mask.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmadd.mask.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfmadd_vf_f64m8_tum(vbool8_t mask, vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) { vfloat64m8_t test_vfmadd_vf_f64m8_tum(vbool8_t mask, vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfmadd_tum(mask, vd, rs1, vs2, vl); return __riscv_vfmadd_tum(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmadd_vv_f16mf4_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmadd_vv_f16mf4_tumu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmadd.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmadd.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
// //
vfloat16mf4_t test_vfmadd_vv_f16mf4_tumu(vbool64_t mask, vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) { vfloat16mf4_t test_vfmadd_vv_f16mf4_tumu(vbool64_t mask, vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfmadd_tumu(mask, vd, vs1, vs2, vl); return __riscv_vfmadd_tumu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmadd_vf_f16mf4_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmadd_vf_f16mf4_tumu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmadd.mask.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmadd.mask.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
// //
vfloat16mf4_t test_vfmadd_vf_f16mf4_tumu(vbool64_t mask, vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) { vfloat16mf4_t test_vfmadd_vf_f16mf4_tumu(vbool64_t mask, vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfmadd_tumu(mask, vd, rs1, vs2, vl); return __riscv_vfmadd_tumu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmadd_vv_f16mf2_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmadd_vv_f16mf2_tumu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmadd.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmadd.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
// //
vfloat16mf2_t test_vfmadd_vv_f16mf2_tumu(vbool32_t mask, vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) { vfloat16mf2_t test_vfmadd_vv_f16mf2_tumu(vbool32_t mask, vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfmadd_tumu(mask, vd, vs1, vs2, vl); return __riscv_vfmadd_tumu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmadd_vf_f16mf2_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmadd_vf_f16mf2_tumu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmadd.mask.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmadd.mask.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
// //
vfloat16mf2_t test_vfmadd_vf_f16mf2_tumu(vbool32_t mask, vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) { vfloat16mf2_t test_vfmadd_vf_f16mf2_tumu(vbool32_t mask, vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfmadd_tumu(mask, vd, rs1, vs2, vl); return __riscv_vfmadd_tumu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmadd_vv_f16m1_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmadd_vv_f16m1_tumu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmadd.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmadd.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
// //
vfloat16m1_t test_vfmadd_vv_f16m1_tumu(vbool16_t mask, vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) { vfloat16m1_t test_vfmadd_vv_f16m1_tumu(vbool16_t mask, vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfmadd_tumu(mask, vd, vs1, vs2, vl); return __riscv_vfmadd_tumu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmadd_vf_f16m1_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmadd_vf_f16m1_tumu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmadd.mask.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmadd.mask.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
// //
vfloat16m1_t test_vfmadd_vf_f16m1_tumu(vbool16_t mask, vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) { vfloat16m1_t test_vfmadd_vf_f16m1_tumu(vbool16_t mask, vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfmadd_tumu(mask, vd, rs1, vs2, vl); return __riscv_vfmadd_tumu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmadd_vv_f16m2_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmadd_vv_f16m2_tumu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmadd.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmadd.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
// //
vfloat16m2_t test_vfmadd_vv_f16m2_tumu(vbool8_t mask, vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) { vfloat16m2_t test_vfmadd_vv_f16m2_tumu(vbool8_t mask, vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfmadd_tumu(mask, vd, vs1, vs2, vl); return __riscv_vfmadd_tumu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmadd_vf_f16m2_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmadd_vf_f16m2_tumu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmadd.mask.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmadd.mask.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
// //
vfloat16m2_t test_vfmadd_vf_f16m2_tumu(vbool8_t mask, vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) { vfloat16m2_t test_vfmadd_vf_f16m2_tumu(vbool8_t mask, vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfmadd_tumu(mask, vd, rs1, vs2, vl); return __riscv_vfmadd_tumu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmadd_vv_f16m4_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmadd_vv_f16m4_tumu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmadd.mask.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmadd.mask.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
// //
vfloat16m4_t test_vfmadd_vv_f16m4_tumu(vbool4_t mask, vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) { vfloat16m4_t test_vfmadd_vv_f16m4_tumu(vbool4_t mask, vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfmadd_tumu(mask, vd, vs1, vs2, vl); return __riscv_vfmadd_tumu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmadd_vf_f16m4_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmadd_vf_f16m4_tumu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmadd.mask.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmadd.mask.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
// //
vfloat16m4_t test_vfmadd_vf_f16m4_tumu(vbool4_t mask, vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) { vfloat16m4_t test_vfmadd_vf_f16m4_tumu(vbool4_t mask, vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfmadd_tumu(mask, vd, rs1, vs2, vl); return __riscv_vfmadd_tumu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmadd_vv_f16m8_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmadd_vv_f16m8_tumu
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmadd.mask.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmadd.mask.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
// //
vfloat16m8_t test_vfmadd_vv_f16m8_tumu(vbool2_t mask, vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) { vfloat16m8_t test_vfmadd_vv_f16m8_tumu(vbool2_t mask, vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfmadd_tumu(mask, vd, vs1, vs2, vl); return __riscv_vfmadd_tumu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmadd_vf_f16m8_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmadd_vf_f16m8_tumu
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmadd.mask.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmadd.mask.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
// //
vfloat16m8_t test_vfmadd_vf_f16m8_tumu(vbool2_t mask, vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) { vfloat16m8_t test_vfmadd_vf_f16m8_tumu(vbool2_t mask, vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfmadd_tumu(mask, vd, rs1, vs2, vl); return __riscv_vfmadd_tumu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmadd_vv_f32mf2_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmadd_vv_f32mf2_tumu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmadd.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmadd.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfmadd_vv_f32mf2_tumu(vbool64_t mask, vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) { vfloat32mf2_t test_vfmadd_vv_f32mf2_tumu(vbool64_t mask, vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfmadd_tumu(mask, vd, vs1, vs2, vl); return __riscv_vfmadd_tumu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmadd_vf_f32mf2_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmadd_vf_f32mf2_tumu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmadd.mask.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmadd.mask.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfmadd_vf_f32mf2_tumu(vbool64_t mask, vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) { vfloat32mf2_t test_vfmadd_vf_f32mf2_tumu(vbool64_t mask, vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfmadd_tumu(mask, vd, rs1, vs2, vl); return __riscv_vfmadd_tumu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmadd_vv_f32m1_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmadd_vv_f32m1_tumu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmadd.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmadd.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfmadd_vv_f32m1_tumu(vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) { vfloat32m1_t test_vfmadd_vv_f32m1_tumu(vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfmadd_tumu(mask, vd, vs1, vs2, vl); return __riscv_vfmadd_tumu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmadd_vf_f32m1_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmadd_vf_f32m1_tumu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmadd.mask.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmadd.mask.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfmadd_vf_f32m1_tumu(vbool32_t mask, vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) { vfloat32m1_t test_vfmadd_vf_f32m1_tumu(vbool32_t mask, vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfmadd_tumu(mask, vd, rs1, vs2, vl); return __riscv_vfmadd_tumu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmadd_vv_f32m2_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmadd_vv_f32m2_tumu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmadd.mask.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmadd.mask.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfmadd_vv_f32m2_tumu(vbool16_t mask, vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) { vfloat32m2_t test_vfmadd_vv_f32m2_tumu(vbool16_t mask, vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfmadd_tumu(mask, vd, vs1, vs2, vl); return __riscv_vfmadd_tumu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmadd_vf_f32m2_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmadd_vf_f32m2_tumu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmadd.mask.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmadd.mask.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfmadd_vf_f32m2_tumu(vbool16_t mask, vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) { vfloat32m2_t test_vfmadd_vf_f32m2_tumu(vbool16_t mask, vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfmadd_tumu(mask, vd, rs1, vs2, vl); return __riscv_vfmadd_tumu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmadd_vv_f32m4_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmadd_vv_f32m4_tumu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmadd.mask.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmadd.mask.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfmadd_vv_f32m4_tumu(vbool8_t mask, vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) { vfloat32m4_t test_vfmadd_vv_f32m4_tumu(vbool8_t mask, vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfmadd_tumu(mask, vd, vs1, vs2, vl); return __riscv_vfmadd_tumu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmadd_vf_f32m4_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmadd_vf_f32m4_tumu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmadd.mask.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmadd.mask.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfmadd_vf_f32m4_tumu(vbool8_t mask, vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) { vfloat32m4_t test_vfmadd_vf_f32m4_tumu(vbool8_t mask, vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfmadd_tumu(mask, vd, rs1, vs2, vl); return __riscv_vfmadd_tumu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmadd_vv_f32m8_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmadd_vv_f32m8_tumu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmadd.mask.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmadd.mask.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfmadd_vv_f32m8_tumu(vbool4_t mask, vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) { vfloat32m8_t test_vfmadd_vv_f32m8_tumu(vbool4_t mask, vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfmadd_tumu(mask, vd, vs1, vs2, vl); return __riscv_vfmadd_tumu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmadd_vf_f32m8_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmadd_vf_f32m8_tumu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmadd.mask.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmadd.mask.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfmadd_vf_f32m8_tumu(vbool4_t mask, vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) { vfloat32m8_t test_vfmadd_vf_f32m8_tumu(vbool4_t mask, vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfmadd_tumu(mask, vd, rs1, vs2, vl); return __riscv_vfmadd_tumu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmadd_vv_f64m1_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmadd_vv_f64m1_tumu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmadd.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmadd.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfmadd_vv_f64m1_tumu(vbool64_t mask, vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) { vfloat64m1_t test_vfmadd_vv_f64m1_tumu(vbool64_t mask, vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfmadd_tumu(mask, vd, vs1, vs2, vl); return __riscv_vfmadd_tumu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmadd_vf_f64m1_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmadd_vf_f64m1_tumu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmadd.mask.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmadd.mask.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfmadd_vf_f64m1_tumu(vbool64_t mask, vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) { vfloat64m1_t test_vfmadd_vf_f64m1_tumu(vbool64_t mask, vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfmadd_tumu(mask, vd, rs1, vs2, vl); return __riscv_vfmadd_tumu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmadd_vv_f64m2_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmadd_vv_f64m2_tumu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmadd.mask.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmadd.mask.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfmadd_vv_f64m2_tumu(vbool32_t mask, vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) { vfloat64m2_t test_vfmadd_vv_f64m2_tumu(vbool32_t mask, vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfmadd_tumu(mask, vd, vs1, vs2, vl); return __riscv_vfmadd_tumu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmadd_vf_f64m2_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmadd_vf_f64m2_tumu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmadd.mask.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmadd.mask.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfmadd_vf_f64m2_tumu(vbool32_t mask, vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) { vfloat64m2_t test_vfmadd_vf_f64m2_tumu(vbool32_t mask, vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfmadd_tumu(mask, vd, rs1, vs2, vl); return __riscv_vfmadd_tumu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmadd_vv_f64m4_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmadd_vv_f64m4_tumu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmadd.mask.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmadd.mask.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfmadd_vv_f64m4_tumu(vbool16_t mask, vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) { vfloat64m4_t test_vfmadd_vv_f64m4_tumu(vbool16_t mask, vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfmadd_tumu(mask, vd, vs1, vs2, vl); return __riscv_vfmadd_tumu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmadd_vf_f64m4_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmadd_vf_f64m4_tumu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmadd.mask.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmadd.mask.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfmadd_vf_f64m4_tumu(vbool16_t mask, vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) { vfloat64m4_t test_vfmadd_vf_f64m4_tumu(vbool16_t mask, vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfmadd_tumu(mask, vd, rs1, vs2, vl); return __riscv_vfmadd_tumu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmadd_vv_f64m8_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmadd_vv_f64m8_tumu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmadd.mask.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmadd.mask.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfmadd_vv_f64m8_tumu(vbool8_t mask, vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) { vfloat64m8_t test_vfmadd_vv_f64m8_tumu(vbool8_t mask, vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfmadd_tumu(mask, vd, vs1, vs2, vl); return __riscv_vfmadd_tumu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmadd_vf_f64m8_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmadd_vf_f64m8_tumu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmadd.mask.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmadd.mask.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfmadd_vf_f64m8_tumu(vbool8_t mask, vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) { vfloat64m8_t test_vfmadd_vf_f64m8_tumu(vbool8_t mask, vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfmadd_tumu(mask, vd, rs1, vs2, vl); return __riscv_vfmadd_tumu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmadd_vv_f16mf4_mu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmadd_vv_f16mf4_mu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmadd.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmadd.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
// //
vfloat16mf4_t test_vfmadd_vv_f16mf4_mu(vbool64_t mask, vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) { vfloat16mf4_t test_vfmadd_vv_f16mf4_mu(vbool64_t mask, vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfmadd_mu(mask, vd, vs1, vs2, vl); return __riscv_vfmadd_mu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmadd_vf_f16mf4_mu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmadd_vf_f16mf4_mu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmadd.mask.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmadd.mask.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
// //
vfloat16mf4_t test_vfmadd_vf_f16mf4_mu(vbool64_t mask, vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) { vfloat16mf4_t test_vfmadd_vf_f16mf4_mu(vbool64_t mask, vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfmadd_mu(mask, vd, rs1, vs2, vl); return __riscv_vfmadd_mu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmadd_vv_f16mf2_mu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmadd_vv_f16mf2_mu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmadd.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmadd.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
// //
vfloat16mf2_t test_vfmadd_vv_f16mf2_mu(vbool32_t mask, vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) { vfloat16mf2_t test_vfmadd_vv_f16mf2_mu(vbool32_t mask, vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfmadd_mu(mask, vd, vs1, vs2, vl); return __riscv_vfmadd_mu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmadd_vf_f16mf2_mu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmadd_vf_f16mf2_mu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmadd.mask.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmadd.mask.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
// //
vfloat16mf2_t test_vfmadd_vf_f16mf2_mu(vbool32_t mask, vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) { vfloat16mf2_t test_vfmadd_vf_f16mf2_mu(vbool32_t mask, vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfmadd_mu(mask, vd, rs1, vs2, vl); return __riscv_vfmadd_mu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmadd_vv_f16m1_mu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmadd_vv_f16m1_mu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmadd.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmadd.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
// //
vfloat16m1_t test_vfmadd_vv_f16m1_mu(vbool16_t mask, vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) { vfloat16m1_t test_vfmadd_vv_f16m1_mu(vbool16_t mask, vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfmadd_mu(mask, vd, vs1, vs2, vl); return __riscv_vfmadd_mu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmadd_vf_f16m1_mu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmadd_vf_f16m1_mu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmadd.mask.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmadd.mask.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
// //
vfloat16m1_t test_vfmadd_vf_f16m1_mu(vbool16_t mask, vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) { vfloat16m1_t test_vfmadd_vf_f16m1_mu(vbool16_t mask, vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfmadd_mu(mask, vd, rs1, vs2, vl); return __riscv_vfmadd_mu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmadd_vv_f16m2_mu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmadd_vv_f16m2_mu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmadd.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmadd.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
// //
vfloat16m2_t test_vfmadd_vv_f16m2_mu(vbool8_t mask, vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) { vfloat16m2_t test_vfmadd_vv_f16m2_mu(vbool8_t mask, vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfmadd_mu(mask, vd, vs1, vs2, vl); return __riscv_vfmadd_mu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmadd_vf_f16m2_mu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmadd_vf_f16m2_mu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmadd.mask.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmadd.mask.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
// //
vfloat16m2_t test_vfmadd_vf_f16m2_mu(vbool8_t mask, vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) { vfloat16m2_t test_vfmadd_vf_f16m2_mu(vbool8_t mask, vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfmadd_mu(mask, vd, rs1, vs2, vl); return __riscv_vfmadd_mu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmadd_vv_f16m4_mu // CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmadd_vv_f16m4_mu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmadd.mask.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmadd.mask.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
// //
vfloat16m4_t test_vfmadd_vv_f16m4_mu(vbool4_t mask, vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) { vfloat16m4_t test_vfmadd_vv_f16m4_mu(vbool4_t mask, vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfmadd_mu(mask, vd, vs1, vs2, vl); return __riscv_vfmadd_mu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmadd_vf_f16m4_mu // CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmadd_vf_f16m4_mu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmadd.mask.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmadd.mask.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
// //
vfloat16m4_t test_vfmadd_vf_f16m4_mu(vbool4_t mask, vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) { vfloat16m4_t test_vfmadd_vf_f16m4_mu(vbool4_t mask, vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfmadd_mu(mask, vd, rs1, vs2, vl); return __riscv_vfmadd_mu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmadd_vv_f16m8_mu // CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmadd_vv_f16m8_mu
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmadd.mask.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmadd.mask.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
// //
vfloat16m8_t test_vfmadd_vv_f16m8_mu(vbool2_t mask, vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) { vfloat16m8_t test_vfmadd_vv_f16m8_mu(vbool2_t mask, vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfmadd_mu(mask, vd, vs1, vs2, vl); return __riscv_vfmadd_mu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmadd_vf_f16m8_mu // CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmadd_vf_f16m8_mu
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmadd.mask.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmadd.mask.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
// //
vfloat16m8_t test_vfmadd_vf_f16m8_mu(vbool2_t mask, vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) { vfloat16m8_t test_vfmadd_vf_f16m8_mu(vbool2_t mask, vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfmadd_mu(mask, vd, rs1, vs2, vl); return __riscv_vfmadd_mu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmadd_vv_f32mf2_mu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmadd_vv_f32mf2_mu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmadd.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmadd.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfmadd_vv_f32mf2_mu(vbool64_t mask, vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) { vfloat32mf2_t test_vfmadd_vv_f32mf2_mu(vbool64_t mask, vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfmadd_mu(mask, vd, vs1, vs2, vl); return __riscv_vfmadd_mu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmadd_vf_f32mf2_mu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmadd_vf_f32mf2_mu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmadd.mask.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmadd.mask.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfmadd_vf_f32mf2_mu(vbool64_t mask, vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) { vfloat32mf2_t test_vfmadd_vf_f32mf2_mu(vbool64_t mask, vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfmadd_mu(mask, vd, rs1, vs2, vl); return __riscv_vfmadd_mu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmadd_vv_f32m1_mu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmadd_vv_f32m1_mu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmadd.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmadd.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfmadd_vv_f32m1_mu(vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) { vfloat32m1_t test_vfmadd_vv_f32m1_mu(vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfmadd_mu(mask, vd, vs1, vs2, vl); return __riscv_vfmadd_mu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmadd_vf_f32m1_mu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmadd_vf_f32m1_mu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmadd.mask.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmadd.mask.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfmadd_vf_f32m1_mu(vbool32_t mask, vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) { vfloat32m1_t test_vfmadd_vf_f32m1_mu(vbool32_t mask, vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfmadd_mu(mask, vd, rs1, vs2, vl); return __riscv_vfmadd_mu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmadd_vv_f32m2_mu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmadd_vv_f32m2_mu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmadd.mask.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmadd.mask.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfmadd_vv_f32m2_mu(vbool16_t mask, vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) { vfloat32m2_t test_vfmadd_vv_f32m2_mu(vbool16_t mask, vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfmadd_mu(mask, vd, vs1, vs2, vl); return __riscv_vfmadd_mu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmadd_vf_f32m2_mu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmadd_vf_f32m2_mu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmadd.mask.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmadd.mask.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfmadd_vf_f32m2_mu(vbool16_t mask, vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) { vfloat32m2_t test_vfmadd_vf_f32m2_mu(vbool16_t mask, vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfmadd_mu(mask, vd, rs1, vs2, vl); return __riscv_vfmadd_mu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmadd_vv_f32m4_mu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmadd_vv_f32m4_mu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmadd.mask.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmadd.mask.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfmadd_vv_f32m4_mu(vbool8_t mask, vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) { vfloat32m4_t test_vfmadd_vv_f32m4_mu(vbool8_t mask, vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfmadd_mu(mask, vd, vs1, vs2, vl); return __riscv_vfmadd_mu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmadd_vf_f32m4_mu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmadd_vf_f32m4_mu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmadd.mask.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmadd.mask.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfmadd_vf_f32m4_mu(vbool8_t mask, vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) { vfloat32m4_t test_vfmadd_vf_f32m4_mu(vbool8_t mask, vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfmadd_mu(mask, vd, rs1, vs2, vl); return __riscv_vfmadd_mu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmadd_vv_f32m8_mu // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmadd_vv_f32m8_mu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmadd.mask.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmadd.mask.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfmadd_vv_f32m8_mu(vbool4_t mask, vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) { vfloat32m8_t test_vfmadd_vv_f32m8_mu(vbool4_t mask, vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfmadd_mu(mask, vd, vs1, vs2, vl); return __riscv_vfmadd_mu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmadd_vf_f32m8_mu // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmadd_vf_f32m8_mu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmadd.mask.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmadd.mask.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfmadd_vf_f32m8_mu(vbool4_t mask, vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) { vfloat32m8_t test_vfmadd_vf_f32m8_mu(vbool4_t mask, vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfmadd_mu(mask, vd, rs1, vs2, vl); return __riscv_vfmadd_mu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmadd_vv_f64m1_mu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmadd_vv_f64m1_mu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmadd.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmadd.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfmadd_vv_f64m1_mu(vbool64_t mask, vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) { vfloat64m1_t test_vfmadd_vv_f64m1_mu(vbool64_t mask, vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfmadd_mu(mask, vd, vs1, vs2, vl); return __riscv_vfmadd_mu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmadd_vf_f64m1_mu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmadd_vf_f64m1_mu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmadd.mask.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmadd.mask.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfmadd_vf_f64m1_mu(vbool64_t mask, vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) { vfloat64m1_t test_vfmadd_vf_f64m1_mu(vbool64_t mask, vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfmadd_mu(mask, vd, rs1, vs2, vl); return __riscv_vfmadd_mu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmadd_vv_f64m2_mu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmadd_vv_f64m2_mu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmadd.mask.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmadd.mask.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfmadd_vv_f64m2_mu(vbool32_t mask, vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) { vfloat64m2_t test_vfmadd_vv_f64m2_mu(vbool32_t mask, vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfmadd_mu(mask, vd, vs1, vs2, vl); return __riscv_vfmadd_mu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmadd_vf_f64m2_mu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmadd_vf_f64m2_mu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmadd.mask.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmadd.mask.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfmadd_vf_f64m2_mu(vbool32_t mask, vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) { vfloat64m2_t test_vfmadd_vf_f64m2_mu(vbool32_t mask, vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfmadd_mu(mask, vd, rs1, vs2, vl); return __riscv_vfmadd_mu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmadd_vv_f64m4_mu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmadd_vv_f64m4_mu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmadd.mask.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmadd.mask.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfmadd_vv_f64m4_mu(vbool16_t mask, vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) { vfloat64m4_t test_vfmadd_vv_f64m4_mu(vbool16_t mask, vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfmadd_mu(mask, vd, vs1, vs2, vl); return __riscv_vfmadd_mu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmadd_vf_f64m4_mu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmadd_vf_f64m4_mu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmadd.mask.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmadd.mask.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfmadd_vf_f64m4_mu(vbool16_t mask, vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) { vfloat64m4_t test_vfmadd_vf_f64m4_mu(vbool16_t mask, vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfmadd_mu(mask, vd, rs1, vs2, vl); return __riscv_vfmadd_mu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmadd_vv_f64m8_mu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmadd_vv_f64m8_mu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmadd.mask.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmadd.mask.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfmadd_vv_f64m8_mu(vbool8_t mask, vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) { vfloat64m8_t test_vfmadd_vv_f64m8_mu(vbool8_t mask, vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfmadd_mu(mask, vd, vs1, vs2, vl); return __riscv_vfmadd_mu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmadd_vf_f64m8_mu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmadd_vf_f64m8_mu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmadd.mask.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmadd.mask.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfmadd_vf_f64m8_mu(vbool8_t mask, vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) { vfloat64m8_t test_vfmadd_vf_f64m8_mu(vbool8_t mask, vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfmadd_mu(mask, vd, rs1, vs2, vl); return __riscv_vfmadd_mu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmadd_vv_f16mf4_rm_tu
// CHECK-RV64-SAME: (<vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmadd.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
//
vfloat16mf4_t test_vfmadd_vv_f16mf4_rm_tu(vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfmadd_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmadd_vf_f16mf4_rm_tu
// CHECK-RV64-SAME: (<vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmadd.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
//
vfloat16mf4_t test_vfmadd_vf_f16mf4_rm_tu(vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfmadd_tu(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmadd_vv_f16mf2_rm_tu
// CHECK-RV64-SAME: (<vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmadd.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
//
vfloat16mf2_t test_vfmadd_vv_f16mf2_rm_tu(vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfmadd_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmadd_vf_f16mf2_rm_tu
// CHECK-RV64-SAME: (<vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmadd.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
//
vfloat16mf2_t test_vfmadd_vf_f16mf2_rm_tu(vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfmadd_tu(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmadd_vv_f16m1_rm_tu
// CHECK-RV64-SAME: (<vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmadd.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfmadd_vv_f16m1_rm_tu(vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfmadd_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmadd_vf_f16m1_rm_tu
// CHECK-RV64-SAME: (<vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmadd.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfmadd_vf_f16m1_rm_tu(vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfmadd_tu(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmadd_vv_f16m2_rm_tu
// CHECK-RV64-SAME: (<vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmadd.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
//
vfloat16m2_t test_vfmadd_vv_f16m2_rm_tu(vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfmadd_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmadd_vf_f16m2_rm_tu
// CHECK-RV64-SAME: (<vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmadd.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
//
vfloat16m2_t test_vfmadd_vf_f16m2_rm_tu(vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfmadd_tu(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmadd_vv_f16m4_rm_tu
// CHECK-RV64-SAME: (<vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmadd.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
//
vfloat16m4_t test_vfmadd_vv_f16m4_rm_tu(vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfmadd_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmadd_vf_f16m4_rm_tu
// CHECK-RV64-SAME: (<vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmadd.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
//
vfloat16m4_t test_vfmadd_vf_f16m4_rm_tu(vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfmadd_tu(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmadd_vv_f16m8_rm_tu
// CHECK-RV64-SAME: (<vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmadd.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
//
vfloat16m8_t test_vfmadd_vv_f16m8_rm_tu(vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfmadd_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmadd_vf_f16m8_rm_tu
// CHECK-RV64-SAME: (<vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmadd.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
//
vfloat16m8_t test_vfmadd_vf_f16m8_rm_tu(vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfmadd_tu(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmadd_vv_f32mf2_rm_tu
// CHECK-RV64-SAME: (<vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmadd.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
//
vfloat32mf2_t test_vfmadd_vv_f32mf2_rm_tu(vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfmadd_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmadd_vf_f32mf2_rm_tu
// CHECK-RV64-SAME: (<vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmadd.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
//
vfloat32mf2_t test_vfmadd_vf_f32mf2_rm_tu(vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfmadd_tu(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmadd_vv_f32m1_rm_tu
// CHECK-RV64-SAME: (<vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmadd.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfmadd_vv_f32m1_rm_tu(vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfmadd_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmadd_vf_f32m1_rm_tu
// CHECK-RV64-SAME: (<vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmadd.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfmadd_vf_f32m1_rm_tu(vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfmadd_tu(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmadd_vv_f32m2_rm_tu
// CHECK-RV64-SAME: (<vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmadd.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
//
vfloat32m2_t test_vfmadd_vv_f32m2_rm_tu(vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfmadd_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmadd_vf_f32m2_rm_tu
// CHECK-RV64-SAME: (<vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmadd.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
//
vfloat32m2_t test_vfmadd_vf_f32m2_rm_tu(vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfmadd_tu(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmadd_vv_f32m4_rm_tu
// CHECK-RV64-SAME: (<vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmadd.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
//
vfloat32m4_t test_vfmadd_vv_f32m4_rm_tu(vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfmadd_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmadd_vf_f32m4_rm_tu
// CHECK-RV64-SAME: (<vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmadd.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
//
vfloat32m4_t test_vfmadd_vf_f32m4_rm_tu(vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfmadd_tu(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmadd_vv_f32m8_rm_tu
// CHECK-RV64-SAME: (<vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmadd.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
//
vfloat32m8_t test_vfmadd_vv_f32m8_rm_tu(vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfmadd_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmadd_vf_f32m8_rm_tu
// CHECK-RV64-SAME: (<vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmadd.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
//
vfloat32m8_t test_vfmadd_vf_f32m8_rm_tu(vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfmadd_tu(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmadd_vv_f64m1_rm_tu
// CHECK-RV64-SAME: (<vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmadd.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfmadd_vv_f64m1_rm_tu(vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfmadd_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmadd_vf_f64m1_rm_tu
// CHECK-RV64-SAME: (<vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmadd.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfmadd_vf_f64m1_rm_tu(vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfmadd_tu(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmadd_vv_f64m2_rm_tu
// CHECK-RV64-SAME: (<vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmadd.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
//
vfloat64m2_t test_vfmadd_vv_f64m2_rm_tu(vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfmadd_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmadd_vf_f64m2_rm_tu
// CHECK-RV64-SAME: (<vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmadd.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
//
vfloat64m2_t test_vfmadd_vf_f64m2_rm_tu(vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfmadd_tu(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmadd_vv_f64m4_rm_tu
// CHECK-RV64-SAME: (<vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmadd.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
//
vfloat64m4_t test_vfmadd_vv_f64m4_rm_tu(vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfmadd_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmadd_vf_f64m4_rm_tu
// CHECK-RV64-SAME: (<vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmadd.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
//
vfloat64m4_t test_vfmadd_vf_f64m4_rm_tu(vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfmadd_tu(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmadd_vv_f64m8_rm_tu
// CHECK-RV64-SAME: (<vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmadd.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
//
vfloat64m8_t test_vfmadd_vv_f64m8_rm_tu(vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfmadd_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmadd_vf_f64m8_rm_tu
// CHECK-RV64-SAME: (<vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmadd.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
//
vfloat64m8_t test_vfmadd_vf_f64m8_rm_tu(vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfmadd_tu(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmadd_vv_f16mf4_rm_tum
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmadd.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
//
vfloat16mf4_t test_vfmadd_vv_f16mf4_rm_tum(vbool64_t mask, vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfmadd_tum(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmadd_vf_f16mf4_rm_tum
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmadd.mask.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
//
vfloat16mf4_t test_vfmadd_vf_f16mf4_rm_tum(vbool64_t mask, vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfmadd_tum(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmadd_vv_f16mf2_rm_tum
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmadd.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
//
vfloat16mf2_t test_vfmadd_vv_f16mf2_rm_tum(vbool32_t mask, vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfmadd_tum(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmadd_vf_f16mf2_rm_tum
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmadd.mask.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
//
vfloat16mf2_t test_vfmadd_vf_f16mf2_rm_tum(vbool32_t mask, vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfmadd_tum(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmadd_vv_f16m1_rm_tum
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmadd.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfmadd_vv_f16m1_rm_tum(vbool16_t mask, vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfmadd_tum(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmadd_vf_f16m1_rm_tum
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmadd.mask.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfmadd_vf_f16m1_rm_tum(vbool16_t mask, vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfmadd_tum(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmadd_vv_f16m2_rm_tum
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmadd.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
//
vfloat16m2_t test_vfmadd_vv_f16m2_rm_tum(vbool8_t mask, vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfmadd_tum(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmadd_vf_f16m2_rm_tum
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmadd.mask.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
//
vfloat16m2_t test_vfmadd_vf_f16m2_rm_tum(vbool8_t mask, vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfmadd_tum(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmadd_vv_f16m4_rm_tum
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmadd.mask.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
//
vfloat16m4_t test_vfmadd_vv_f16m4_rm_tum(vbool4_t mask, vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfmadd_tum(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmadd_vf_f16m4_rm_tum
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmadd.mask.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
//
vfloat16m4_t test_vfmadd_vf_f16m4_rm_tum(vbool4_t mask, vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfmadd_tum(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmadd_vv_f16m8_rm_tum
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmadd.mask.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
//
vfloat16m8_t test_vfmadd_vv_f16m8_rm_tum(vbool2_t mask, vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfmadd_tum(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmadd_vf_f16m8_rm_tum
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmadd.mask.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
//
vfloat16m8_t test_vfmadd_vf_f16m8_rm_tum(vbool2_t mask, vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfmadd_tum(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmadd_vv_f32mf2_rm_tum
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmadd.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
//
vfloat32mf2_t test_vfmadd_vv_f32mf2_rm_tum(vbool64_t mask, vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfmadd_tum(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmadd_vf_f32mf2_rm_tum
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmadd.mask.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
//
vfloat32mf2_t test_vfmadd_vf_f32mf2_rm_tum(vbool64_t mask, vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfmadd_tum(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmadd_vv_f32m1_rm_tum
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmadd.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfmadd_vv_f32m1_rm_tum(vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfmadd_tum(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmadd_vf_f32m1_rm_tum
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmadd.mask.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfmadd_vf_f32m1_rm_tum(vbool32_t mask, vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfmadd_tum(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmadd_vv_f32m2_rm_tum
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmadd.mask.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
//
vfloat32m2_t test_vfmadd_vv_f32m2_rm_tum(vbool16_t mask, vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfmadd_tum(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmadd_vf_f32m2_rm_tum
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmadd.mask.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
//
vfloat32m2_t test_vfmadd_vf_f32m2_rm_tum(vbool16_t mask, vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfmadd_tum(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmadd_vv_f32m4_rm_tum
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmadd.mask.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
//
vfloat32m4_t test_vfmadd_vv_f32m4_rm_tum(vbool8_t mask, vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfmadd_tum(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmadd_vf_f32m4_rm_tum
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmadd.mask.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
//
vfloat32m4_t test_vfmadd_vf_f32m4_rm_tum(vbool8_t mask, vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfmadd_tum(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmadd_vv_f32m8_rm_tum
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmadd.mask.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
//
vfloat32m8_t test_vfmadd_vv_f32m8_rm_tum(vbool4_t mask, vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfmadd_tum(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmadd_vf_f32m8_rm_tum
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmadd.mask.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
//
vfloat32m8_t test_vfmadd_vf_f32m8_rm_tum(vbool4_t mask, vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfmadd_tum(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmadd_vv_f64m1_rm_tum
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmadd.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfmadd_vv_f64m1_rm_tum(vbool64_t mask, vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfmadd_tum(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmadd_vf_f64m1_rm_tum
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmadd.mask.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfmadd_vf_f64m1_rm_tum(vbool64_t mask, vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfmadd_tum(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmadd_vv_f64m2_rm_tum
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmadd.mask.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
//
vfloat64m2_t test_vfmadd_vv_f64m2_rm_tum(vbool32_t mask, vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfmadd_tum(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmadd_vf_f64m2_rm_tum
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmadd.mask.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
//
vfloat64m2_t test_vfmadd_vf_f64m2_rm_tum(vbool32_t mask, vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfmadd_tum(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmadd_vv_f64m4_rm_tum
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmadd.mask.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
//
vfloat64m4_t test_vfmadd_vv_f64m4_rm_tum(vbool16_t mask, vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfmadd_tum(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmadd_vf_f64m4_rm_tum
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmadd.mask.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
//
vfloat64m4_t test_vfmadd_vf_f64m4_rm_tum(vbool16_t mask, vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfmadd_tum(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmadd_vv_f64m8_rm_tum
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmadd.mask.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
//
vfloat64m8_t test_vfmadd_vv_f64m8_rm_tum(vbool8_t mask, vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfmadd_tum(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmadd_vf_f64m8_rm_tum
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmadd.mask.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
//
vfloat64m8_t test_vfmadd_vf_f64m8_rm_tum(vbool8_t mask, vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfmadd_tum(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmadd_vv_f16mf4_rm_tumu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmadd.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
//
vfloat16mf4_t test_vfmadd_vv_f16mf4_rm_tumu(vbool64_t mask, vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfmadd_tumu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmadd_vf_f16mf4_rm_tumu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmadd.mask.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
//
vfloat16mf4_t test_vfmadd_vf_f16mf4_rm_tumu(vbool64_t mask, vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfmadd_tumu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmadd_vv_f16mf2_rm_tumu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmadd.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
//
vfloat16mf2_t test_vfmadd_vv_f16mf2_rm_tumu(vbool32_t mask, vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfmadd_tumu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmadd_vf_f16mf2_rm_tumu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmadd.mask.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
//
vfloat16mf2_t test_vfmadd_vf_f16mf2_rm_tumu(vbool32_t mask, vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfmadd_tumu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmadd_vv_f16m1_rm_tumu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmadd.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfmadd_vv_f16m1_rm_tumu(vbool16_t mask, vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfmadd_tumu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmadd_vf_f16m1_rm_tumu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmadd.mask.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfmadd_vf_f16m1_rm_tumu(vbool16_t mask, vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfmadd_tumu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmadd_vv_f16m2_rm_tumu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmadd.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
//
vfloat16m2_t test_vfmadd_vv_f16m2_rm_tumu(vbool8_t mask, vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfmadd_tumu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmadd_vf_f16m2_rm_tumu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmadd.mask.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
//
vfloat16m2_t test_vfmadd_vf_f16m2_rm_tumu(vbool8_t mask, vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfmadd_tumu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmadd_vv_f16m4_rm_tumu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmadd.mask.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
//
vfloat16m4_t test_vfmadd_vv_f16m4_rm_tumu(vbool4_t mask, vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfmadd_tumu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmadd_vf_f16m4_rm_tumu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmadd.mask.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
//
vfloat16m4_t test_vfmadd_vf_f16m4_rm_tumu(vbool4_t mask, vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfmadd_tumu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmadd_vv_f16m8_rm_tumu
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmadd.mask.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
//
vfloat16m8_t test_vfmadd_vv_f16m8_rm_tumu(vbool2_t mask, vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfmadd_tumu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmadd_vf_f16m8_rm_tumu
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmadd.mask.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
//
vfloat16m8_t test_vfmadd_vf_f16m8_rm_tumu(vbool2_t mask, vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfmadd_tumu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmadd_vv_f32mf2_rm_tumu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmadd.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
//
vfloat32mf2_t test_vfmadd_vv_f32mf2_rm_tumu(vbool64_t mask, vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfmadd_tumu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmadd_vf_f32mf2_rm_tumu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmadd.mask.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
//
vfloat32mf2_t test_vfmadd_vf_f32mf2_rm_tumu(vbool64_t mask, vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfmadd_tumu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmadd_vv_f32m1_rm_tumu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmadd.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfmadd_vv_f32m1_rm_tumu(vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfmadd_tumu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmadd_vf_f32m1_rm_tumu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmadd.mask.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfmadd_vf_f32m1_rm_tumu(vbool32_t mask, vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfmadd_tumu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmadd_vv_f32m2_rm_tumu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmadd.mask.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
//
vfloat32m2_t test_vfmadd_vv_f32m2_rm_tumu(vbool16_t mask, vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfmadd_tumu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmadd_vf_f32m2_rm_tumu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmadd.mask.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
//
vfloat32m2_t test_vfmadd_vf_f32m2_rm_tumu(vbool16_t mask, vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfmadd_tumu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmadd_vv_f32m4_rm_tumu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmadd.mask.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
//
vfloat32m4_t test_vfmadd_vv_f32m4_rm_tumu(vbool8_t mask, vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfmadd_tumu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmadd_vf_f32m4_rm_tumu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmadd.mask.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
//
vfloat32m4_t test_vfmadd_vf_f32m4_rm_tumu(vbool8_t mask, vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfmadd_tumu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmadd_vv_f32m8_rm_tumu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmadd.mask.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
//
vfloat32m8_t test_vfmadd_vv_f32m8_rm_tumu(vbool4_t mask, vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfmadd_tumu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmadd_vf_f32m8_rm_tumu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmadd.mask.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
//
vfloat32m8_t test_vfmadd_vf_f32m8_rm_tumu(vbool4_t mask, vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfmadd_tumu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmadd_vv_f64m1_rm_tumu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmadd.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfmadd_vv_f64m1_rm_tumu(vbool64_t mask, vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfmadd_tumu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmadd_vf_f64m1_rm_tumu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmadd.mask.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfmadd_vf_f64m1_rm_tumu(vbool64_t mask, vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfmadd_tumu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmadd_vv_f64m2_rm_tumu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmadd.mask.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
//
vfloat64m2_t test_vfmadd_vv_f64m2_rm_tumu(vbool32_t mask, vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfmadd_tumu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmadd_vf_f64m2_rm_tumu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmadd.mask.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
//
vfloat64m2_t test_vfmadd_vf_f64m2_rm_tumu(vbool32_t mask, vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfmadd_tumu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmadd_vv_f64m4_rm_tumu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmadd.mask.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
//
vfloat64m4_t test_vfmadd_vv_f64m4_rm_tumu(vbool16_t mask, vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfmadd_tumu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmadd_vf_f64m4_rm_tumu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmadd.mask.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
//
vfloat64m4_t test_vfmadd_vf_f64m4_rm_tumu(vbool16_t mask, vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfmadd_tumu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmadd_vv_f64m8_rm_tumu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmadd.mask.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
//
vfloat64m8_t test_vfmadd_vv_f64m8_rm_tumu(vbool8_t mask, vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfmadd_tumu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmadd_vf_f64m8_rm_tumu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmadd.mask.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
//
vfloat64m8_t test_vfmadd_vf_f64m8_rm_tumu(vbool8_t mask, vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfmadd_tumu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmadd_vv_f16mf4_rm_mu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmadd.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
//
vfloat16mf4_t test_vfmadd_vv_f16mf4_rm_mu(vbool64_t mask, vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfmadd_mu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmadd_vf_f16mf4_rm_mu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmadd.mask.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
//
vfloat16mf4_t test_vfmadd_vf_f16mf4_rm_mu(vbool64_t mask, vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfmadd_mu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmadd_vv_f16mf2_rm_mu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmadd.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
//
vfloat16mf2_t test_vfmadd_vv_f16mf2_rm_mu(vbool32_t mask, vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfmadd_mu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmadd_vf_f16mf2_rm_mu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmadd.mask.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
//
vfloat16mf2_t test_vfmadd_vf_f16mf2_rm_mu(vbool32_t mask, vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfmadd_mu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmadd_vv_f16m1_rm_mu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmadd.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfmadd_vv_f16m1_rm_mu(vbool16_t mask, vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfmadd_mu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmadd_vf_f16m1_rm_mu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmadd.mask.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfmadd_vf_f16m1_rm_mu(vbool16_t mask, vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfmadd_mu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmadd_vv_f16m2_rm_mu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmadd.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
//
vfloat16m2_t test_vfmadd_vv_f16m2_rm_mu(vbool8_t mask, vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfmadd_mu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmadd_vf_f16m2_rm_mu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmadd.mask.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
//
vfloat16m2_t test_vfmadd_vf_f16m2_rm_mu(vbool8_t mask, vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfmadd_mu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmadd_vv_f16m4_rm_mu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmadd.mask.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
//
vfloat16m4_t test_vfmadd_vv_f16m4_rm_mu(vbool4_t mask, vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfmadd_mu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmadd_vf_f16m4_rm_mu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmadd.mask.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
//
vfloat16m4_t test_vfmadd_vf_f16m4_rm_mu(vbool4_t mask, vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfmadd_mu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmadd_vv_f16m8_rm_mu
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmadd.mask.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
//
vfloat16m8_t test_vfmadd_vv_f16m8_rm_mu(vbool2_t mask, vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfmadd_mu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmadd_vf_f16m8_rm_mu
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmadd.mask.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
//
vfloat16m8_t test_vfmadd_vf_f16m8_rm_mu(vbool2_t mask, vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfmadd_mu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmadd_vv_f32mf2_rm_mu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmadd.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
//
vfloat32mf2_t test_vfmadd_vv_f32mf2_rm_mu(vbool64_t mask, vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfmadd_mu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmadd_vf_f32mf2_rm_mu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmadd.mask.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
//
vfloat32mf2_t test_vfmadd_vf_f32mf2_rm_mu(vbool64_t mask, vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfmadd_mu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmadd_vv_f32m1_rm_mu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmadd.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfmadd_vv_f32m1_rm_mu(vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfmadd_mu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmadd_vf_f32m1_rm_mu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmadd.mask.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfmadd_vf_f32m1_rm_mu(vbool32_t mask, vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfmadd_mu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmadd_vv_f32m2_rm_mu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmadd.mask.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
//
vfloat32m2_t test_vfmadd_vv_f32m2_rm_mu(vbool16_t mask, vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfmadd_mu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmadd_vf_f32m2_rm_mu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmadd.mask.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
//
vfloat32m2_t test_vfmadd_vf_f32m2_rm_mu(vbool16_t mask, vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfmadd_mu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmadd_vv_f32m4_rm_mu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmadd.mask.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
//
vfloat32m4_t test_vfmadd_vv_f32m4_rm_mu(vbool8_t mask, vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfmadd_mu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmadd_vf_f32m4_rm_mu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmadd.mask.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
//
vfloat32m4_t test_vfmadd_vf_f32m4_rm_mu(vbool8_t mask, vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfmadd_mu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmadd_vv_f32m8_rm_mu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmadd.mask.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
//
vfloat32m8_t test_vfmadd_vv_f32m8_rm_mu(vbool4_t mask, vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfmadd_mu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmadd_vf_f32m8_rm_mu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmadd.mask.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
//
vfloat32m8_t test_vfmadd_vf_f32m8_rm_mu(vbool4_t mask, vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfmadd_mu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmadd_vv_f64m1_rm_mu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmadd.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfmadd_vv_f64m1_rm_mu(vbool64_t mask, vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfmadd_mu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmadd_vf_f64m1_rm_mu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmadd.mask.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfmadd_vf_f64m1_rm_mu(vbool64_t mask, vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfmadd_mu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmadd_vv_f64m2_rm_mu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmadd.mask.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
//
vfloat64m2_t test_vfmadd_vv_f64m2_rm_mu(vbool32_t mask, vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfmadd_mu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmadd_vf_f64m2_rm_mu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmadd.mask.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
//
vfloat64m2_t test_vfmadd_vf_f64m2_rm_mu(vbool32_t mask, vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfmadd_mu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmadd_vv_f64m4_rm_mu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmadd.mask.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
//
vfloat64m4_t test_vfmadd_vv_f64m4_rm_mu(vbool16_t mask, vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfmadd_mu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmadd_vf_f64m4_rm_mu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmadd.mask.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
//
vfloat64m4_t test_vfmadd_vf_f64m4_rm_mu(vbool16_t mask, vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfmadd_mu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmadd_vv_f64m8_rm_mu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmadd.mask.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
//
vfloat64m8_t test_vfmadd_vv_f64m8_rm_mu(vbool8_t mask, vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfmadd_mu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmadd_vf_f64m8_rm_mu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmadd.mask.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
//
vfloat64m8_t test_vfmadd_vf_f64m8_rm_mu(vbool8_t mask, vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfmadd_mu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}

clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmsac.c

// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target // REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh \ // RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh \
// RUN: -target-feature +experimental-zvfh -disable-O0-optnone \ // RUN: -target-feature +experimental-zvfh -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ // RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s // RUN: FileCheck --check-prefix=CHECK-RV64 %s
#include <riscv_vector.h> #include <riscv_vector.h>
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmsac_vv_f16mf4_tu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmsac_vv_f16mf4_tu
// CHECK-RV64-SAME: (<vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK-RV64-SAME: (<vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmsac.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmsac.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
// //
vfloat16mf4_t test_vfmsac_vv_f16mf4_tu(vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) { vfloat16mf4_t test_vfmsac_vv_f16mf4_tu(vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfmsac_tu(vd, vs1, vs2, vl); return __riscv_vfmsac_tu(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmsac_vf_f16mf4_tu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmsac_vf_f16mf4_tu
// CHECK-RV64-SAME: (<vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmsac.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmsac.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
// //
vfloat16mf4_t test_vfmsac_vf_f16mf4_tu(vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) { vfloat16mf4_t test_vfmsac_vf_f16mf4_tu(vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfmsac_tu(vd, rs1, vs2, vl); return __riscv_vfmsac_tu(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmsac_vv_f16mf2_tu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmsac_vv_f16mf2_tu
// CHECK-RV64-SAME: (<vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmsac.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmsac.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
// //
vfloat16mf2_t test_vfmsac_vv_f16mf2_tu(vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) { vfloat16mf2_t test_vfmsac_vv_f16mf2_tu(vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfmsac_tu(vd, vs1, vs2, vl); return __riscv_vfmsac_tu(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmsac_vf_f16mf2_tu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmsac_vf_f16mf2_tu
// CHECK-RV64-SAME: (<vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmsac.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmsac.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
// //
vfloat16mf2_t test_vfmsac_vf_f16mf2_tu(vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) { vfloat16mf2_t test_vfmsac_vf_f16mf2_tu(vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfmsac_tu(vd, rs1, vs2, vl); return __riscv_vfmsac_tu(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmsac_vv_f16m1_tu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmsac_vv_f16m1_tu
// CHECK-RV64-SAME: (<vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmsac.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmsac.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
// //
vfloat16m1_t test_vfmsac_vv_f16m1_tu(vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) { vfloat16m1_t test_vfmsac_vv_f16m1_tu(vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfmsac_tu(vd, vs1, vs2, vl); return __riscv_vfmsac_tu(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmsac_vf_f16m1_tu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmsac_vf_f16m1_tu
// CHECK-RV64-SAME: (<vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmsac.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmsac.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
// //
vfloat16m1_t test_vfmsac_vf_f16m1_tu(vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) { vfloat16m1_t test_vfmsac_vf_f16m1_tu(vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfmsac_tu(vd, rs1, vs2, vl); return __riscv_vfmsac_tu(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmsac_vv_f16m2_tu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmsac_vv_f16m2_tu
// CHECK-RV64-SAME: (<vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmsac.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmsac.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
// //
vfloat16m2_t test_vfmsac_vv_f16m2_tu(vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) { vfloat16m2_t test_vfmsac_vv_f16m2_tu(vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfmsac_tu(vd, vs1, vs2, vl); return __riscv_vfmsac_tu(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmsac_vf_f16m2_tu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmsac_vf_f16m2_tu
// CHECK-RV64-SAME: (<vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmsac.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmsac.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
// //
vfloat16m2_t test_vfmsac_vf_f16m2_tu(vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) { vfloat16m2_t test_vfmsac_vf_f16m2_tu(vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfmsac_tu(vd, rs1, vs2, vl); return __riscv_vfmsac_tu(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmsac_vv_f16m4_tu // CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmsac_vv_f16m4_tu
// CHECK-RV64-SAME: (<vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmsac.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmsac.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
// //
vfloat16m4_t test_vfmsac_vv_f16m4_tu(vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) { vfloat16m4_t test_vfmsac_vv_f16m4_tu(vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfmsac_tu(vd, vs1, vs2, vl); return __riscv_vfmsac_tu(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmsac_vf_f16m4_tu // CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmsac_vf_f16m4_tu
// CHECK-RV64-SAME: (<vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmsac.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmsac.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
// //
vfloat16m4_t test_vfmsac_vf_f16m4_tu(vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) { vfloat16m4_t test_vfmsac_vf_f16m4_tu(vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfmsac_tu(vd, rs1, vs2, vl); return __riscv_vfmsac_tu(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmsac_vv_f16m8_tu // CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmsac_vv_f16m8_tu
// CHECK-RV64-SAME: (<vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmsac.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmsac.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
// //
vfloat16m8_t test_vfmsac_vv_f16m8_tu(vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) { vfloat16m8_t test_vfmsac_vv_f16m8_tu(vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfmsac_tu(vd, vs1, vs2, vl); return __riscv_vfmsac_tu(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmsac_vf_f16m8_tu // CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmsac_vf_f16m8_tu
// CHECK-RV64-SAME: (<vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmsac.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmsac.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
// //
vfloat16m8_t test_vfmsac_vf_f16m8_tu(vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) { vfloat16m8_t test_vfmsac_vf_f16m8_tu(vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfmsac_tu(vd, rs1, vs2, vl); return __riscv_vfmsac_tu(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmsac_vv_f32mf2_tu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmsac_vv_f32mf2_tu
// CHECK-RV64-SAME: (<vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmsac.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmsac.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfmsac_vv_f32mf2_tu(vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) { vfloat32mf2_t test_vfmsac_vv_f32mf2_tu(vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfmsac_tu(vd, vs1, vs2, vl); return __riscv_vfmsac_tu(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmsac_vf_f32mf2_tu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmsac_vf_f32mf2_tu
// CHECK-RV64-SAME: (<vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmsac.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmsac.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfmsac_vf_f32mf2_tu(vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) { vfloat32mf2_t test_vfmsac_vf_f32mf2_tu(vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfmsac_tu(vd, rs1, vs2, vl); return __riscv_vfmsac_tu(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmsac_vv_f32m1_tu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmsac_vv_f32m1_tu
// CHECK-RV64-SAME: (<vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmsac.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmsac.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfmsac_vv_f32m1_tu(vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) { vfloat32m1_t test_vfmsac_vv_f32m1_tu(vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfmsac_tu(vd, vs1, vs2, vl); return __riscv_vfmsac_tu(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmsac_vf_f32m1_tu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmsac_vf_f32m1_tu
// CHECK-RV64-SAME: (<vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmsac.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmsac.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfmsac_vf_f32m1_tu(vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) { vfloat32m1_t test_vfmsac_vf_f32m1_tu(vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfmsac_tu(vd, rs1, vs2, vl); return __riscv_vfmsac_tu(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmsac_vv_f32m2_tu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmsac_vv_f32m2_tu
// CHECK-RV64-SAME: (<vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmsac.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmsac.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfmsac_vv_f32m2_tu(vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) { vfloat32m2_t test_vfmsac_vv_f32m2_tu(vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfmsac_tu(vd, vs1, vs2, vl); return __riscv_vfmsac_tu(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmsac_vf_f32m2_tu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmsac_vf_f32m2_tu
// CHECK-RV64-SAME: (<vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmsac.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmsac.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfmsac_vf_f32m2_tu(vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) { vfloat32m2_t test_vfmsac_vf_f32m2_tu(vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfmsac_tu(vd, rs1, vs2, vl); return __riscv_vfmsac_tu(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmsac_vv_f32m4_tu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmsac_vv_f32m4_tu
// CHECK-RV64-SAME: (<vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmsac.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmsac.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfmsac_vv_f32m4_tu(vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) { vfloat32m4_t test_vfmsac_vv_f32m4_tu(vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfmsac_tu(vd, vs1, vs2, vl); return __riscv_vfmsac_tu(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmsac_vf_f32m4_tu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmsac_vf_f32m4_tu
// CHECK-RV64-SAME: (<vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmsac.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmsac.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfmsac_vf_f32m4_tu(vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) { vfloat32m4_t test_vfmsac_vf_f32m4_tu(vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfmsac_tu(vd, rs1, vs2, vl); return __riscv_vfmsac_tu(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmsac_vv_f32m8_tu // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmsac_vv_f32m8_tu
// CHECK-RV64-SAME: (<vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmsac.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmsac.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfmsac_vv_f32m8_tu(vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) { vfloat32m8_t test_vfmsac_vv_f32m8_tu(vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfmsac_tu(vd, vs1, vs2, vl); return __riscv_vfmsac_tu(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmsac_vf_f32m8_tu // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmsac_vf_f32m8_tu
// CHECK-RV64-SAME: (<vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmsac.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmsac.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfmsac_vf_f32m8_tu(vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) { vfloat32m8_t test_vfmsac_vf_f32m8_tu(vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfmsac_tu(vd, rs1, vs2, vl); return __riscv_vfmsac_tu(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmsac_vv_f64m1_tu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmsac_vv_f64m1_tu
// CHECK-RV64-SAME: (<vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmsac.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmsac.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfmsac_vv_f64m1_tu(vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) { vfloat64m1_t test_vfmsac_vv_f64m1_tu(vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfmsac_tu(vd, vs1, vs2, vl); return __riscv_vfmsac_tu(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmsac_vf_f64m1_tu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmsac_vf_f64m1_tu
// CHECK-RV64-SAME: (<vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmsac.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmsac.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfmsac_vf_f64m1_tu(vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) { vfloat64m1_t test_vfmsac_vf_f64m1_tu(vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfmsac_tu(vd, rs1, vs2, vl); return __riscv_vfmsac_tu(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmsac_vv_f64m2_tu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmsac_vv_f64m2_tu
// CHECK-RV64-SAME: (<vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmsac.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmsac.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfmsac_vv_f64m2_tu(vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) { vfloat64m2_t test_vfmsac_vv_f64m2_tu(vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfmsac_tu(vd, vs1, vs2, vl); return __riscv_vfmsac_tu(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmsac_vf_f64m2_tu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmsac_vf_f64m2_tu
// CHECK-RV64-SAME: (<vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmsac.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmsac.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfmsac_vf_f64m2_tu(vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) { vfloat64m2_t test_vfmsac_vf_f64m2_tu(vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfmsac_tu(vd, rs1, vs2, vl); return __riscv_vfmsac_tu(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmsac_vv_f64m4_tu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmsac_vv_f64m4_tu
// CHECK-RV64-SAME: (<vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmsac.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmsac.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfmsac_vv_f64m4_tu(vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) { vfloat64m4_t test_vfmsac_vv_f64m4_tu(vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfmsac_tu(vd, vs1, vs2, vl); return __riscv_vfmsac_tu(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmsac_vf_f64m4_tu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmsac_vf_f64m4_tu
// CHECK-RV64-SAME: (<vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmsac.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmsac.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfmsac_vf_f64m4_tu(vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) { vfloat64m4_t test_vfmsac_vf_f64m4_tu(vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfmsac_tu(vd, rs1, vs2, vl); return __riscv_vfmsac_tu(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmsac_vv_f64m8_tu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmsac_vv_f64m8_tu
// CHECK-RV64-SAME: (<vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmsac.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmsac.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfmsac_vv_f64m8_tu(vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) { vfloat64m8_t test_vfmsac_vv_f64m8_tu(vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfmsac_tu(vd, vs1, vs2, vl); return __riscv_vfmsac_tu(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmsac_vf_f64m8_tu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmsac_vf_f64m8_tu
// CHECK-RV64-SAME: (<vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmsac.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmsac.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfmsac_vf_f64m8_tu(vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) { vfloat64m8_t test_vfmsac_vf_f64m8_tu(vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfmsac_tu(vd, rs1, vs2, vl); return __riscv_vfmsac_tu(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmsac_vv_f16mf4_tum // CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmsac_vv_f16mf4_tum
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmsac.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmsac.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
// //
vfloat16mf4_t test_vfmsac_vv_f16mf4_tum(vbool64_t mask, vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) { vfloat16mf4_t test_vfmsac_vv_f16mf4_tum(vbool64_t mask, vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfmsac_tum(mask, vd, vs1, vs2, vl); return __riscv_vfmsac_tum(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmsac_vf_f16mf4_tum // CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmsac_vf_f16mf4_tum
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmsac.mask.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmsac.mask.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
// //
vfloat16mf4_t test_vfmsac_vf_f16mf4_tum(vbool64_t mask, vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) { vfloat16mf4_t test_vfmsac_vf_f16mf4_tum(vbool64_t mask, vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfmsac_tum(mask, vd, rs1, vs2, vl); return __riscv_vfmsac_tum(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmsac_vv_f16mf2_tum // CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmsac_vv_f16mf2_tum
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmsac.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmsac.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
// //
vfloat16mf2_t test_vfmsac_vv_f16mf2_tum(vbool32_t mask, vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) { vfloat16mf2_t test_vfmsac_vv_f16mf2_tum(vbool32_t mask, vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfmsac_tum(mask, vd, vs1, vs2, vl); return __riscv_vfmsac_tum(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmsac_vf_f16mf2_tum // CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmsac_vf_f16mf2_tum
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmsac.mask.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmsac.mask.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
// //
vfloat16mf2_t test_vfmsac_vf_f16mf2_tum(vbool32_t mask, vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) { vfloat16mf2_t test_vfmsac_vf_f16mf2_tum(vbool32_t mask, vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfmsac_tum(mask, vd, rs1, vs2, vl); return __riscv_vfmsac_tum(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmsac_vv_f16m1_tum // CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmsac_vv_f16m1_tum
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmsac.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmsac.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
// //
vfloat16m1_t test_vfmsac_vv_f16m1_tum(vbool16_t mask, vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) { vfloat16m1_t test_vfmsac_vv_f16m1_tum(vbool16_t mask, vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfmsac_tum(mask, vd, vs1, vs2, vl); return __riscv_vfmsac_tum(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmsac_vf_f16m1_tum // CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmsac_vf_f16m1_tum
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmsac.mask.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmsac.mask.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
// //
vfloat16m1_t test_vfmsac_vf_f16m1_tum(vbool16_t mask, vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) { vfloat16m1_t test_vfmsac_vf_f16m1_tum(vbool16_t mask, vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfmsac_tum(mask, vd, rs1, vs2, vl); return __riscv_vfmsac_tum(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmsac_vv_f16m2_tum // CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmsac_vv_f16m2_tum
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmsac.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmsac.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
// //
vfloat16m2_t test_vfmsac_vv_f16m2_tum(vbool8_t mask, vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) { vfloat16m2_t test_vfmsac_vv_f16m2_tum(vbool8_t mask, vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfmsac_tum(mask, vd, vs1, vs2, vl); return __riscv_vfmsac_tum(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmsac_vf_f16m2_tum // CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmsac_vf_f16m2_tum
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmsac.mask.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmsac.mask.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
// //
vfloat16m2_t test_vfmsac_vf_f16m2_tum(vbool8_t mask, vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) { vfloat16m2_t test_vfmsac_vf_f16m2_tum(vbool8_t mask, vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfmsac_tum(mask, vd, rs1, vs2, vl); return __riscv_vfmsac_tum(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmsac_vv_f16m4_tum // CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmsac_vv_f16m4_tum
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmsac.mask.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmsac.mask.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
// //
vfloat16m4_t test_vfmsac_vv_f16m4_tum(vbool4_t mask, vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) { vfloat16m4_t test_vfmsac_vv_f16m4_tum(vbool4_t mask, vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfmsac_tum(mask, vd, vs1, vs2, vl); return __riscv_vfmsac_tum(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmsac_vf_f16m4_tum // CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmsac_vf_f16m4_tum
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmsac.mask.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmsac.mask.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
// //
vfloat16m4_t test_vfmsac_vf_f16m4_tum(vbool4_t mask, vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) { vfloat16m4_t test_vfmsac_vf_f16m4_tum(vbool4_t mask, vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfmsac_tum(mask, vd, rs1, vs2, vl); return __riscv_vfmsac_tum(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmsac_vv_f16m8_tum // CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmsac_vv_f16m8_tum
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmsac.mask.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmsac.mask.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
// //
vfloat16m8_t test_vfmsac_vv_f16m8_tum(vbool2_t mask, vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) { vfloat16m8_t test_vfmsac_vv_f16m8_tum(vbool2_t mask, vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfmsac_tum(mask, vd, vs1, vs2, vl); return __riscv_vfmsac_tum(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmsac_vf_f16m8_tum // CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmsac_vf_f16m8_tum
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmsac.mask.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmsac.mask.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
// //
vfloat16m8_t test_vfmsac_vf_f16m8_tum(vbool2_t mask, vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) { vfloat16m8_t test_vfmsac_vf_f16m8_tum(vbool2_t mask, vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfmsac_tum(mask, vd, rs1, vs2, vl); return __riscv_vfmsac_tum(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmsac_vv_f32mf2_tum // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmsac_vv_f32mf2_tum
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmsac.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmsac.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfmsac_vv_f32mf2_tum(vbool64_t mask, vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) { vfloat32mf2_t test_vfmsac_vv_f32mf2_tum(vbool64_t mask, vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfmsac_tum(mask, vd, vs1, vs2, vl); return __riscv_vfmsac_tum(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmsac_vf_f32mf2_tum // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmsac_vf_f32mf2_tum
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmsac.mask.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmsac.mask.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfmsac_vf_f32mf2_tum(vbool64_t mask, vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) { vfloat32mf2_t test_vfmsac_vf_f32mf2_tum(vbool64_t mask, vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfmsac_tum(mask, vd, rs1, vs2, vl); return __riscv_vfmsac_tum(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmsac_vv_f32m1_tum // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmsac_vv_f32m1_tum
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmsac.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmsac.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfmsac_vv_f32m1_tum(vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) { vfloat32m1_t test_vfmsac_vv_f32m1_tum(vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfmsac_tum(mask, vd, vs1, vs2, vl); return __riscv_vfmsac_tum(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmsac_vf_f32m1_tum // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmsac_vf_f32m1_tum
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmsac.mask.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmsac.mask.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfmsac_vf_f32m1_tum(vbool32_t mask, vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) { vfloat32m1_t test_vfmsac_vf_f32m1_tum(vbool32_t mask, vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfmsac_tum(mask, vd, rs1, vs2, vl); return __riscv_vfmsac_tum(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmsac_vv_f32m2_tum // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmsac_vv_f32m2_tum
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmsac.mask.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmsac.mask.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfmsac_vv_f32m2_tum(vbool16_t mask, vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) { vfloat32m2_t test_vfmsac_vv_f32m2_tum(vbool16_t mask, vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfmsac_tum(mask, vd, vs1, vs2, vl); return __riscv_vfmsac_tum(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmsac_vf_f32m2_tum // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmsac_vf_f32m2_tum
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmsac.mask.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmsac.mask.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfmsac_vf_f32m2_tum(vbool16_t mask, vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) { vfloat32m2_t test_vfmsac_vf_f32m2_tum(vbool16_t mask, vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfmsac_tum(mask, vd, rs1, vs2, vl); return __riscv_vfmsac_tum(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmsac_vv_f32m4_tum // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmsac_vv_f32m4_tum
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmsac.mask.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmsac.mask.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfmsac_vv_f32m4_tum(vbool8_t mask, vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) { vfloat32m4_t test_vfmsac_vv_f32m4_tum(vbool8_t mask, vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfmsac_tum(mask, vd, vs1, vs2, vl); return __riscv_vfmsac_tum(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmsac_vf_f32m4_tum // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmsac_vf_f32m4_tum
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmsac.mask.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmsac.mask.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfmsac_vf_f32m4_tum(vbool8_t mask, vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) { vfloat32m4_t test_vfmsac_vf_f32m4_tum(vbool8_t mask, vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfmsac_tum(mask, vd, rs1, vs2, vl); return __riscv_vfmsac_tum(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmsac_vv_f32m8_tum // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmsac_vv_f32m8_tum
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmsac.mask.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmsac.mask.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfmsac_vv_f32m8_tum(vbool4_t mask, vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) { vfloat32m8_t test_vfmsac_vv_f32m8_tum(vbool4_t mask, vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfmsac_tum(mask, vd, vs1, vs2, vl); return __riscv_vfmsac_tum(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmsac_vf_f32m8_tum // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmsac_vf_f32m8_tum
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmsac.mask.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmsac.mask.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfmsac_vf_f32m8_tum(vbool4_t mask, vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) { vfloat32m8_t test_vfmsac_vf_f32m8_tum(vbool4_t mask, vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfmsac_tum(mask, vd, rs1, vs2, vl); return __riscv_vfmsac_tum(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmsac_vv_f64m1_tum // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmsac_vv_f64m1_tum
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmsac.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmsac.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfmsac_vv_f64m1_tum(vbool64_t mask, vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) { vfloat64m1_t test_vfmsac_vv_f64m1_tum(vbool64_t mask, vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfmsac_tum(mask, vd, vs1, vs2, vl); return __riscv_vfmsac_tum(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmsac_vf_f64m1_tum // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmsac_vf_f64m1_tum
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmsac.mask.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmsac.mask.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfmsac_vf_f64m1_tum(vbool64_t mask, vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) { vfloat64m1_t test_vfmsac_vf_f64m1_tum(vbool64_t mask, vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfmsac_tum(mask, vd, rs1, vs2, vl); return __riscv_vfmsac_tum(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmsac_vv_f64m2_tum // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmsac_vv_f64m2_tum
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmsac.mask.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmsac.mask.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfmsac_vv_f64m2_tum(vbool32_t mask, vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) { vfloat64m2_t test_vfmsac_vv_f64m2_tum(vbool32_t mask, vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfmsac_tum(mask, vd, vs1, vs2, vl); return __riscv_vfmsac_tum(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmsac_vf_f64m2_tum // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmsac_vf_f64m2_tum
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmsac.mask.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmsac.mask.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfmsac_vf_f64m2_tum(vbool32_t mask, vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) { vfloat64m2_t test_vfmsac_vf_f64m2_tum(vbool32_t mask, vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfmsac_tum(mask, vd, rs1, vs2, vl); return __riscv_vfmsac_tum(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmsac_vv_f64m4_tum // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmsac_vv_f64m4_tum
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmsac.mask.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmsac.mask.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfmsac_vv_f64m4_tum(vbool16_t mask, vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) { vfloat64m4_t test_vfmsac_vv_f64m4_tum(vbool16_t mask, vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfmsac_tum(mask, vd, vs1, vs2, vl); return __riscv_vfmsac_tum(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmsac_vf_f64m4_tum // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmsac_vf_f64m4_tum
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmsac.mask.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmsac.mask.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfmsac_vf_f64m4_tum(vbool16_t mask, vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) { vfloat64m4_t test_vfmsac_vf_f64m4_tum(vbool16_t mask, vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfmsac_tum(mask, vd, rs1, vs2, vl); return __riscv_vfmsac_tum(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmsac_vv_f64m8_tum // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmsac_vv_f64m8_tum
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmsac.mask.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmsac.mask.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfmsac_vv_f64m8_tum(vbool8_t mask, vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) { vfloat64m8_t test_vfmsac_vv_f64m8_tum(vbool8_t mask, vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfmsac_tum(mask, vd, vs1, vs2, vl); return __riscv_vfmsac_tum(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmsac_vf_f64m8_tum // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmsac_vf_f64m8_tum
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmsac.mask.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmsac.mask.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfmsac_vf_f64m8_tum(vbool8_t mask, vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) { vfloat64m8_t test_vfmsac_vf_f64m8_tum(vbool8_t mask, vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfmsac_tum(mask, vd, rs1, vs2, vl); return __riscv_vfmsac_tum(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmsac_vv_f16mf4_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmsac_vv_f16mf4_tumu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmsac.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmsac.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
// //
vfloat16mf4_t test_vfmsac_vv_f16mf4_tumu(vbool64_t mask, vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) { vfloat16mf4_t test_vfmsac_vv_f16mf4_tumu(vbool64_t mask, vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfmsac_tumu(mask, vd, vs1, vs2, vl); return __riscv_vfmsac_tumu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmsac_vf_f16mf4_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmsac_vf_f16mf4_tumu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmsac.mask.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmsac.mask.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
// //
vfloat16mf4_t test_vfmsac_vf_f16mf4_tumu(vbool64_t mask, vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) { vfloat16mf4_t test_vfmsac_vf_f16mf4_tumu(vbool64_t mask, vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfmsac_tumu(mask, vd, rs1, vs2, vl); return __riscv_vfmsac_tumu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmsac_vv_f16mf2_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmsac_vv_f16mf2_tumu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmsac.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmsac.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
// //
vfloat16mf2_t test_vfmsac_vv_f16mf2_tumu(vbool32_t mask, vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) { vfloat16mf2_t test_vfmsac_vv_f16mf2_tumu(vbool32_t mask, vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfmsac_tumu(mask, vd, vs1, vs2, vl); return __riscv_vfmsac_tumu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmsac_vf_f16mf2_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmsac_vf_f16mf2_tumu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmsac.mask.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmsac.mask.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
// //
vfloat16mf2_t test_vfmsac_vf_f16mf2_tumu(vbool32_t mask, vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) { vfloat16mf2_t test_vfmsac_vf_f16mf2_tumu(vbool32_t mask, vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfmsac_tumu(mask, vd, rs1, vs2, vl); return __riscv_vfmsac_tumu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmsac_vv_f16m1_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmsac_vv_f16m1_tumu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmsac.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmsac.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
// //
vfloat16m1_t test_vfmsac_vv_f16m1_tumu(vbool16_t mask, vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) { vfloat16m1_t test_vfmsac_vv_f16m1_tumu(vbool16_t mask, vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfmsac_tumu(mask, vd, vs1, vs2, vl); return __riscv_vfmsac_tumu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmsac_vf_f16m1_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmsac_vf_f16m1_tumu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmsac.mask.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmsac.mask.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
// //
vfloat16m1_t test_vfmsac_vf_f16m1_tumu(vbool16_t mask, vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) { vfloat16m1_t test_vfmsac_vf_f16m1_tumu(vbool16_t mask, vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfmsac_tumu(mask, vd, rs1, vs2, vl); return __riscv_vfmsac_tumu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmsac_vv_f16m2_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmsac_vv_f16m2_tumu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmsac.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmsac.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
// //
vfloat16m2_t test_vfmsac_vv_f16m2_tumu(vbool8_t mask, vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) { vfloat16m2_t test_vfmsac_vv_f16m2_tumu(vbool8_t mask, vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfmsac_tumu(mask, vd, vs1, vs2, vl); return __riscv_vfmsac_tumu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmsac_vf_f16m2_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmsac_vf_f16m2_tumu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmsac.mask.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmsac.mask.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
// //
vfloat16m2_t test_vfmsac_vf_f16m2_tumu(vbool8_t mask, vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) { vfloat16m2_t test_vfmsac_vf_f16m2_tumu(vbool8_t mask, vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfmsac_tumu(mask, vd, rs1, vs2, vl); return __riscv_vfmsac_tumu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmsac_vv_f16m4_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmsac_vv_f16m4_tumu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmsac.mask.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmsac.mask.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
// //
vfloat16m4_t test_vfmsac_vv_f16m4_tumu(vbool4_t mask, vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) { vfloat16m4_t test_vfmsac_vv_f16m4_tumu(vbool4_t mask, vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfmsac_tumu(mask, vd, vs1, vs2, vl); return __riscv_vfmsac_tumu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmsac_vf_f16m4_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmsac_vf_f16m4_tumu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmsac.mask.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmsac.mask.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
// //
vfloat16m4_t test_vfmsac_vf_f16m4_tumu(vbool4_t mask, vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) { vfloat16m4_t test_vfmsac_vf_f16m4_tumu(vbool4_t mask, vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfmsac_tumu(mask, vd, rs1, vs2, vl); return __riscv_vfmsac_tumu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmsac_vv_f16m8_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmsac_vv_f16m8_tumu
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmsac.mask.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmsac.mask.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
// //
vfloat16m8_t test_vfmsac_vv_f16m8_tumu(vbool2_t mask, vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) { vfloat16m8_t test_vfmsac_vv_f16m8_tumu(vbool2_t mask, vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfmsac_tumu(mask, vd, vs1, vs2, vl); return __riscv_vfmsac_tumu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmsac_vf_f16m8_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmsac_vf_f16m8_tumu
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmsac.mask.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmsac.mask.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
// //
vfloat16m8_t test_vfmsac_vf_f16m8_tumu(vbool2_t mask, vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) { vfloat16m8_t test_vfmsac_vf_f16m8_tumu(vbool2_t mask, vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfmsac_tumu(mask, vd, rs1, vs2, vl); return __riscv_vfmsac_tumu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmsac_vv_f32mf2_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmsac_vv_f32mf2_tumu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmsac.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmsac.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfmsac_vv_f32mf2_tumu(vbool64_t mask, vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) { vfloat32mf2_t test_vfmsac_vv_f32mf2_tumu(vbool64_t mask, vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfmsac_tumu(mask, vd, vs1, vs2, vl); return __riscv_vfmsac_tumu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmsac_vf_f32mf2_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmsac_vf_f32mf2_tumu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmsac.mask.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmsac.mask.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfmsac_vf_f32mf2_tumu(vbool64_t mask, vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) { vfloat32mf2_t test_vfmsac_vf_f32mf2_tumu(vbool64_t mask, vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfmsac_tumu(mask, vd, rs1, vs2, vl); return __riscv_vfmsac_tumu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmsac_vv_f32m1_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmsac_vv_f32m1_tumu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmsac.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmsac.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfmsac_vv_f32m1_tumu(vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) { vfloat32m1_t test_vfmsac_vv_f32m1_tumu(vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfmsac_tumu(mask, vd, vs1, vs2, vl); return __riscv_vfmsac_tumu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmsac_vf_f32m1_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmsac_vf_f32m1_tumu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmsac.mask.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmsac.mask.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfmsac_vf_f32m1_tumu(vbool32_t mask, vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) { vfloat32m1_t test_vfmsac_vf_f32m1_tumu(vbool32_t mask, vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfmsac_tumu(mask, vd, rs1, vs2, vl); return __riscv_vfmsac_tumu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmsac_vv_f32m2_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmsac_vv_f32m2_tumu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmsac.mask.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmsac.mask.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfmsac_vv_f32m2_tumu(vbool16_t mask, vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) { vfloat32m2_t test_vfmsac_vv_f32m2_tumu(vbool16_t mask, vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfmsac_tumu(mask, vd, vs1, vs2, vl); return __riscv_vfmsac_tumu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmsac_vf_f32m2_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmsac_vf_f32m2_tumu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmsac.mask.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmsac.mask.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfmsac_vf_f32m2_tumu(vbool16_t mask, vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) { vfloat32m2_t test_vfmsac_vf_f32m2_tumu(vbool16_t mask, vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfmsac_tumu(mask, vd, rs1, vs2, vl); return __riscv_vfmsac_tumu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmsac_vv_f32m4_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmsac_vv_f32m4_tumu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmsac.mask.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmsac.mask.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfmsac_vv_f32m4_tumu(vbool8_t mask, vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) { vfloat32m4_t test_vfmsac_vv_f32m4_tumu(vbool8_t mask, vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfmsac_tumu(mask, vd, vs1, vs2, vl); return __riscv_vfmsac_tumu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmsac_vf_f32m4_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmsac_vf_f32m4_tumu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmsac.mask.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmsac.mask.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfmsac_vf_f32m4_tumu(vbool8_t mask, vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) { vfloat32m4_t test_vfmsac_vf_f32m4_tumu(vbool8_t mask, vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfmsac_tumu(mask, vd, rs1, vs2, vl); return __riscv_vfmsac_tumu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmsac_vv_f32m8_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmsac_vv_f32m8_tumu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmsac.mask.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmsac.mask.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfmsac_vv_f32m8_tumu(vbool4_t mask, vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) { vfloat32m8_t test_vfmsac_vv_f32m8_tumu(vbool4_t mask, vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfmsac_tumu(mask, vd, vs1, vs2, vl); return __riscv_vfmsac_tumu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmsac_vf_f32m8_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmsac_vf_f32m8_tumu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmsac.mask.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmsac.mask.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfmsac_vf_f32m8_tumu(vbool4_t mask, vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) { vfloat32m8_t test_vfmsac_vf_f32m8_tumu(vbool4_t mask, vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfmsac_tumu(mask, vd, rs1, vs2, vl); return __riscv_vfmsac_tumu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmsac_vv_f64m1_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmsac_vv_f64m1_tumu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmsac.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmsac.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfmsac_vv_f64m1_tumu(vbool64_t mask, vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) { vfloat64m1_t test_vfmsac_vv_f64m1_tumu(vbool64_t mask, vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfmsac_tumu(mask, vd, vs1, vs2, vl); return __riscv_vfmsac_tumu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmsac_vf_f64m1_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmsac_vf_f64m1_tumu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmsac.mask.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmsac.mask.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfmsac_vf_f64m1_tumu(vbool64_t mask, vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) { vfloat64m1_t test_vfmsac_vf_f64m1_tumu(vbool64_t mask, vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfmsac_tumu(mask, vd, rs1, vs2, vl); return __riscv_vfmsac_tumu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmsac_vv_f64m2_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmsac_vv_f64m2_tumu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmsac.mask.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmsac.mask.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfmsac_vv_f64m2_tumu(vbool32_t mask, vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) { vfloat64m2_t test_vfmsac_vv_f64m2_tumu(vbool32_t mask, vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfmsac_tumu(mask, vd, vs1, vs2, vl); return __riscv_vfmsac_tumu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmsac_vf_f64m2_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmsac_vf_f64m2_tumu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmsac.mask.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmsac.mask.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfmsac_vf_f64m2_tumu(vbool32_t mask, vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) { vfloat64m2_t test_vfmsac_vf_f64m2_tumu(vbool32_t mask, vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfmsac_tumu(mask, vd, rs1, vs2, vl); return __riscv_vfmsac_tumu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmsac_vv_f64m4_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmsac_vv_f64m4_tumu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmsac.mask.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmsac.mask.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfmsac_vv_f64m4_tumu(vbool16_t mask, vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) { vfloat64m4_t test_vfmsac_vv_f64m4_tumu(vbool16_t mask, vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfmsac_tumu(mask, vd, vs1, vs2, vl); return __riscv_vfmsac_tumu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmsac_vf_f64m4_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmsac_vf_f64m4_tumu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmsac.mask.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmsac.mask.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfmsac_vf_f64m4_tumu(vbool16_t mask, vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) { vfloat64m4_t test_vfmsac_vf_f64m4_tumu(vbool16_t mask, vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfmsac_tumu(mask, vd, rs1, vs2, vl); return __riscv_vfmsac_tumu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmsac_vv_f64m8_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmsac_vv_f64m8_tumu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmsac.mask.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmsac.mask.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfmsac_vv_f64m8_tumu(vbool8_t mask, vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) { vfloat64m8_t test_vfmsac_vv_f64m8_tumu(vbool8_t mask, vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfmsac_tumu(mask, vd, vs1, vs2, vl); return __riscv_vfmsac_tumu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmsac_vf_f64m8_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmsac_vf_f64m8_tumu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmsac.mask.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmsac.mask.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfmsac_vf_f64m8_tumu(vbool8_t mask, vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) { vfloat64m8_t test_vfmsac_vf_f64m8_tumu(vbool8_t mask, vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfmsac_tumu(mask, vd, rs1, vs2, vl); return __riscv_vfmsac_tumu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmsac_vv_f16mf4_mu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmsac_vv_f16mf4_mu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmsac.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmsac.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
// //
vfloat16mf4_t test_vfmsac_vv_f16mf4_mu(vbool64_t mask, vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) { vfloat16mf4_t test_vfmsac_vv_f16mf4_mu(vbool64_t mask, vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfmsac_mu(mask, vd, vs1, vs2, vl); return __riscv_vfmsac_mu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmsac_vf_f16mf4_mu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmsac_vf_f16mf4_mu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmsac.mask.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmsac.mask.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
// //
vfloat16mf4_t test_vfmsac_vf_f16mf4_mu(vbool64_t mask, vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) { vfloat16mf4_t test_vfmsac_vf_f16mf4_mu(vbool64_t mask, vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfmsac_mu(mask, vd, rs1, vs2, vl); return __riscv_vfmsac_mu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmsac_vv_f16mf2_mu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmsac_vv_f16mf2_mu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmsac.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmsac.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
// //
vfloat16mf2_t test_vfmsac_vv_f16mf2_mu(vbool32_t mask, vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) { vfloat16mf2_t test_vfmsac_vv_f16mf2_mu(vbool32_t mask, vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfmsac_mu(mask, vd, vs1, vs2, vl); return __riscv_vfmsac_mu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmsac_vf_f16mf2_mu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmsac_vf_f16mf2_mu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmsac.mask.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmsac.mask.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
// //
vfloat16mf2_t test_vfmsac_vf_f16mf2_mu(vbool32_t mask, vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) { vfloat16mf2_t test_vfmsac_vf_f16mf2_mu(vbool32_t mask, vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfmsac_mu(mask, vd, rs1, vs2, vl); return __riscv_vfmsac_mu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmsac_vv_f16m1_mu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmsac_vv_f16m1_mu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmsac.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmsac.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
// //
vfloat16m1_t test_vfmsac_vv_f16m1_mu(vbool16_t mask, vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) { vfloat16m1_t test_vfmsac_vv_f16m1_mu(vbool16_t mask, vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfmsac_mu(mask, vd, vs1, vs2, vl); return __riscv_vfmsac_mu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmsac_vf_f16m1_mu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmsac_vf_f16m1_mu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmsac.mask.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmsac.mask.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
// //
vfloat16m1_t test_vfmsac_vf_f16m1_mu(vbool16_t mask, vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) { vfloat16m1_t test_vfmsac_vf_f16m1_mu(vbool16_t mask, vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfmsac_mu(mask, vd, rs1, vs2, vl); return __riscv_vfmsac_mu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmsac_vv_f16m2_mu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmsac_vv_f16m2_mu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmsac.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmsac.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
// //
vfloat16m2_t test_vfmsac_vv_f16m2_mu(vbool8_t mask, vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) { vfloat16m2_t test_vfmsac_vv_f16m2_mu(vbool8_t mask, vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfmsac_mu(mask, vd, vs1, vs2, vl); return __riscv_vfmsac_mu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmsac_vf_f16m2_mu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmsac_vf_f16m2_mu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmsac.mask.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmsac.mask.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
// //
vfloat16m2_t test_vfmsac_vf_f16m2_mu(vbool8_t mask, vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) { vfloat16m2_t test_vfmsac_vf_f16m2_mu(vbool8_t mask, vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfmsac_mu(mask, vd, rs1, vs2, vl); return __riscv_vfmsac_mu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmsac_vv_f16m4_mu // CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmsac_vv_f16m4_mu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmsac.mask.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmsac.mask.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
// //
vfloat16m4_t test_vfmsac_vv_f16m4_mu(vbool4_t mask, vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) { vfloat16m4_t test_vfmsac_vv_f16m4_mu(vbool4_t mask, vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfmsac_mu(mask, vd, vs1, vs2, vl); return __riscv_vfmsac_mu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmsac_vf_f16m4_mu // CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmsac_vf_f16m4_mu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmsac.mask.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmsac.mask.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
// //
vfloat16m4_t test_vfmsac_vf_f16m4_mu(vbool4_t mask, vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) { vfloat16m4_t test_vfmsac_vf_f16m4_mu(vbool4_t mask, vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfmsac_mu(mask, vd, rs1, vs2, vl); return __riscv_vfmsac_mu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmsac_vv_f16m8_mu // CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmsac_vv_f16m8_mu
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmsac.mask.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmsac.mask.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
// //
vfloat16m8_t test_vfmsac_vv_f16m8_mu(vbool2_t mask, vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) { vfloat16m8_t test_vfmsac_vv_f16m8_mu(vbool2_t mask, vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfmsac_mu(mask, vd, vs1, vs2, vl); return __riscv_vfmsac_mu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmsac_vf_f16m8_mu // CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmsac_vf_f16m8_mu
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmsac.mask.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmsac.mask.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
// //
vfloat16m8_t test_vfmsac_vf_f16m8_mu(vbool2_t mask, vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) { vfloat16m8_t test_vfmsac_vf_f16m8_mu(vbool2_t mask, vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfmsac_mu(mask, vd, rs1, vs2, vl); return __riscv_vfmsac_mu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmsac_vv_f32mf2_mu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmsac_vv_f32mf2_mu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmsac.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmsac.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfmsac_vv_f32mf2_mu(vbool64_t mask, vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) { vfloat32mf2_t test_vfmsac_vv_f32mf2_mu(vbool64_t mask, vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfmsac_mu(mask, vd, vs1, vs2, vl); return __riscv_vfmsac_mu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmsac_vf_f32mf2_mu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmsac_vf_f32mf2_mu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmsac.mask.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmsac.mask.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfmsac_vf_f32mf2_mu(vbool64_t mask, vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) { vfloat32mf2_t test_vfmsac_vf_f32mf2_mu(vbool64_t mask, vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfmsac_mu(mask, vd, rs1, vs2, vl); return __riscv_vfmsac_mu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmsac_vv_f32m1_mu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmsac_vv_f32m1_mu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmsac.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmsac.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfmsac_vv_f32m1_mu(vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) { vfloat32m1_t test_vfmsac_vv_f32m1_mu(vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfmsac_mu(mask, vd, vs1, vs2, vl); return __riscv_vfmsac_mu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmsac_vf_f32m1_mu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmsac_vf_f32m1_mu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmsac.mask.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmsac.mask.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfmsac_vf_f32m1_mu(vbool32_t mask, vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) { vfloat32m1_t test_vfmsac_vf_f32m1_mu(vbool32_t mask, vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfmsac_mu(mask, vd, rs1, vs2, vl); return __riscv_vfmsac_mu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmsac_vv_f32m2_mu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmsac_vv_f32m2_mu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmsac.mask.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmsac.mask.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfmsac_vv_f32m2_mu(vbool16_t mask, vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) { vfloat32m2_t test_vfmsac_vv_f32m2_mu(vbool16_t mask, vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfmsac_mu(mask, vd, vs1, vs2, vl); return __riscv_vfmsac_mu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmsac_vf_f32m2_mu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmsac_vf_f32m2_mu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmsac.mask.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmsac.mask.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfmsac_vf_f32m2_mu(vbool16_t mask, vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) { vfloat32m2_t test_vfmsac_vf_f32m2_mu(vbool16_t mask, vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfmsac_mu(mask, vd, rs1, vs2, vl); return __riscv_vfmsac_mu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmsac_vv_f32m4_mu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmsac_vv_f32m4_mu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmsac.mask.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmsac.mask.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfmsac_vv_f32m4_mu(vbool8_t mask, vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) { vfloat32m4_t test_vfmsac_vv_f32m4_mu(vbool8_t mask, vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfmsac_mu(mask, vd, vs1, vs2, vl); return __riscv_vfmsac_mu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmsac_vf_f32m4_mu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmsac_vf_f32m4_mu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmsac.mask.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmsac.mask.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfmsac_vf_f32m4_mu(vbool8_t mask, vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) { vfloat32m4_t test_vfmsac_vf_f32m4_mu(vbool8_t mask, vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfmsac_mu(mask, vd, rs1, vs2, vl); return __riscv_vfmsac_mu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmsac_vv_f32m8_mu // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmsac_vv_f32m8_mu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmsac.mask.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmsac.mask.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfmsac_vv_f32m8_mu(vbool4_t mask, vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) { vfloat32m8_t test_vfmsac_vv_f32m8_mu(vbool4_t mask, vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfmsac_mu(mask, vd, vs1, vs2, vl); return __riscv_vfmsac_mu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmsac_vf_f32m8_mu // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmsac_vf_f32m8_mu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmsac.mask.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmsac.mask.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfmsac_vf_f32m8_mu(vbool4_t mask, vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) { vfloat32m8_t test_vfmsac_vf_f32m8_mu(vbool4_t mask, vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfmsac_mu(mask, vd, rs1, vs2, vl); return __riscv_vfmsac_mu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmsac_vv_f64m1_mu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmsac_vv_f64m1_mu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmsac.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmsac.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfmsac_vv_f64m1_mu(vbool64_t mask, vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) { vfloat64m1_t test_vfmsac_vv_f64m1_mu(vbool64_t mask, vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfmsac_mu(mask, vd, vs1, vs2, vl); return __riscv_vfmsac_mu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmsac_vf_f64m1_mu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmsac_vf_f64m1_mu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmsac.mask.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmsac.mask.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfmsac_vf_f64m1_mu(vbool64_t mask, vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) { vfloat64m1_t test_vfmsac_vf_f64m1_mu(vbool64_t mask, vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfmsac_mu(mask, vd, rs1, vs2, vl); return __riscv_vfmsac_mu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmsac_vv_f64m2_mu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmsac_vv_f64m2_mu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmsac.mask.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmsac.mask.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfmsac_vv_f64m2_mu(vbool32_t mask, vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) { vfloat64m2_t test_vfmsac_vv_f64m2_mu(vbool32_t mask, vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfmsac_mu(mask, vd, vs1, vs2, vl); return __riscv_vfmsac_mu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmsac_vf_f64m2_mu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmsac_vf_f64m2_mu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmsac.mask.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmsac.mask.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfmsac_vf_f64m2_mu(vbool32_t mask, vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) { vfloat64m2_t test_vfmsac_vf_f64m2_mu(vbool32_t mask, vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfmsac_mu(mask, vd, rs1, vs2, vl); return __riscv_vfmsac_mu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmsac_vv_f64m4_mu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmsac_vv_f64m4_mu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmsac.mask.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmsac.mask.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfmsac_vv_f64m4_mu(vbool16_t mask, vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) { vfloat64m4_t test_vfmsac_vv_f64m4_mu(vbool16_t mask, vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfmsac_mu(mask, vd, vs1, vs2, vl); return __riscv_vfmsac_mu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmsac_vf_f64m4_mu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmsac_vf_f64m4_mu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmsac.mask.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmsac.mask.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfmsac_vf_f64m4_mu(vbool16_t mask, vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) { vfloat64m4_t test_vfmsac_vf_f64m4_mu(vbool16_t mask, vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfmsac_mu(mask, vd, rs1, vs2, vl); return __riscv_vfmsac_mu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmsac_vv_f64m8_mu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmsac_vv_f64m8_mu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmsac.mask.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmsac.mask.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfmsac_vv_f64m8_mu(vbool8_t mask, vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) { vfloat64m8_t test_vfmsac_vv_f64m8_mu(vbool8_t mask, vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfmsac_mu(mask, vd, vs1, vs2, vl); return __riscv_vfmsac_mu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmsac_vf_f64m8_mu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmsac_vf_f64m8_mu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmsac.mask.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmsac.mask.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfmsac_vf_f64m8_mu(vbool8_t mask, vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) { vfloat64m8_t test_vfmsac_vf_f64m8_mu(vbool8_t mask, vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfmsac_mu(mask, vd, rs1, vs2, vl); return __riscv_vfmsac_mu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmsac_vv_f16mf4_rm_tu
// CHECK-RV64-SAME: (<vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmsac.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
//
vfloat16mf4_t test_vfmsac_vv_f16mf4_rm_tu(vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfmsac_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmsac_vf_f16mf4_rm_tu
// CHECK-RV64-SAME: (<vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmsac.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
//
vfloat16mf4_t test_vfmsac_vf_f16mf4_rm_tu(vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfmsac_tu(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmsac_vv_f16mf2_rm_tu
// CHECK-RV64-SAME: (<vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmsac.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
//
vfloat16mf2_t test_vfmsac_vv_f16mf2_rm_tu(vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfmsac_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmsac_vf_f16mf2_rm_tu
// CHECK-RV64-SAME: (<vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmsac.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
//
vfloat16mf2_t test_vfmsac_vf_f16mf2_rm_tu(vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfmsac_tu(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmsac_vv_f16m1_rm_tu
// CHECK-RV64-SAME: (<vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmsac.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfmsac_vv_f16m1_rm_tu(vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfmsac_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmsac_vf_f16m1_rm_tu
// CHECK-RV64-SAME: (<vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmsac.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfmsac_vf_f16m1_rm_tu(vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfmsac_tu(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmsac_vv_f16m2_rm_tu
// CHECK-RV64-SAME: (<vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmsac.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
//
vfloat16m2_t test_vfmsac_vv_f16m2_rm_tu(vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfmsac_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmsac_vf_f16m2_rm_tu
// CHECK-RV64-SAME: (<vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmsac.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
//
vfloat16m2_t test_vfmsac_vf_f16m2_rm_tu(vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfmsac_tu(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmsac_vv_f16m4_rm_tu
// CHECK-RV64-SAME: (<vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmsac.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
//
vfloat16m4_t test_vfmsac_vv_f16m4_rm_tu(vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfmsac_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmsac_vf_f16m4_rm_tu
// CHECK-RV64-SAME: (<vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmsac.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
//
vfloat16m4_t test_vfmsac_vf_f16m4_rm_tu(vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfmsac_tu(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmsac_vv_f16m8_rm_tu
// CHECK-RV64-SAME: (<vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmsac.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
//
vfloat16m8_t test_vfmsac_vv_f16m8_rm_tu(vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfmsac_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmsac_vf_f16m8_rm_tu
// CHECK-RV64-SAME: (<vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmsac.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
//
vfloat16m8_t test_vfmsac_vf_f16m8_rm_tu(vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfmsac_tu(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmsac_vv_f32mf2_rm_tu
// CHECK-RV64-SAME: (<vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmsac.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
//
vfloat32mf2_t test_vfmsac_vv_f32mf2_rm_tu(vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfmsac_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmsac_vf_f32mf2_rm_tu
// CHECK-RV64-SAME: (<vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmsac.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
//
vfloat32mf2_t test_vfmsac_vf_f32mf2_rm_tu(vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfmsac_tu(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmsac_vv_f32m1_rm_tu
// CHECK-RV64-SAME: (<vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmsac.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfmsac_vv_f32m1_rm_tu(vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfmsac_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmsac_vf_f32m1_rm_tu
// CHECK-RV64-SAME: (<vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmsac.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfmsac_vf_f32m1_rm_tu(vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfmsac_tu(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmsac_vv_f32m2_rm_tu
// CHECK-RV64-SAME: (<vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmsac.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
//
vfloat32m2_t test_vfmsac_vv_f32m2_rm_tu(vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfmsac_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmsac_vf_f32m2_rm_tu
// CHECK-RV64-SAME: (<vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmsac.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
//
vfloat32m2_t test_vfmsac_vf_f32m2_rm_tu(vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfmsac_tu(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmsac_vv_f32m4_rm_tu
// CHECK-RV64-SAME: (<vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmsac.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
//
vfloat32m4_t test_vfmsac_vv_f32m4_rm_tu(vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfmsac_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmsac_vf_f32m4_rm_tu
// CHECK-RV64-SAME: (<vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmsac.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
//
vfloat32m4_t test_vfmsac_vf_f32m4_rm_tu(vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfmsac_tu(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmsac_vv_f32m8_rm_tu
// CHECK-RV64-SAME: (<vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmsac.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
//
vfloat32m8_t test_vfmsac_vv_f32m8_rm_tu(vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfmsac_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmsac_vf_f32m8_rm_tu
// CHECK-RV64-SAME: (<vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmsac.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
//
vfloat32m8_t test_vfmsac_vf_f32m8_rm_tu(vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfmsac_tu(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmsac_vv_f64m1_rm_tu
// CHECK-RV64-SAME: (<vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmsac.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfmsac_vv_f64m1_rm_tu(vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfmsac_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmsac_vf_f64m1_rm_tu
// CHECK-RV64-SAME: (<vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmsac.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfmsac_vf_f64m1_rm_tu(vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfmsac_tu(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmsac_vv_f64m2_rm_tu
// CHECK-RV64-SAME: (<vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmsac.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
//
vfloat64m2_t test_vfmsac_vv_f64m2_rm_tu(vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfmsac_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmsac_vf_f64m2_rm_tu
// CHECK-RV64-SAME: (<vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmsac.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
//
vfloat64m2_t test_vfmsac_vf_f64m2_rm_tu(vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfmsac_tu(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmsac_vv_f64m4_rm_tu
// CHECK-RV64-SAME: (<vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmsac.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
//
vfloat64m4_t test_vfmsac_vv_f64m4_rm_tu(vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfmsac_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmsac_vf_f64m4_rm_tu
// CHECK-RV64-SAME: (<vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmsac.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
//
vfloat64m4_t test_vfmsac_vf_f64m4_rm_tu(vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfmsac_tu(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmsac_vv_f64m8_rm_tu
// CHECK-RV64-SAME: (<vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmsac.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
//
vfloat64m8_t test_vfmsac_vv_f64m8_rm_tu(vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfmsac_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmsac_vf_f64m8_rm_tu
// CHECK-RV64-SAME: (<vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmsac.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
//
vfloat64m8_t test_vfmsac_vf_f64m8_rm_tu(vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfmsac_tu(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmsac_vv_f16mf4_rm_tum
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmsac.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
//
vfloat16mf4_t test_vfmsac_vv_f16mf4_rm_tum(vbool64_t mask, vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfmsac_tum(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmsac_vf_f16mf4_rm_tum
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmsac.mask.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
//
vfloat16mf4_t test_vfmsac_vf_f16mf4_rm_tum(vbool64_t mask, vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfmsac_tum(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmsac_vv_f16mf2_rm_tum
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmsac.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
//
vfloat16mf2_t test_vfmsac_vv_f16mf2_rm_tum(vbool32_t mask, vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfmsac_tum(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmsac_vf_f16mf2_rm_tum
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmsac.mask.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
//
vfloat16mf2_t test_vfmsac_vf_f16mf2_rm_tum(vbool32_t mask, vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfmsac_tum(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmsac_vv_f16m1_rm_tum
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmsac.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfmsac_vv_f16m1_rm_tum(vbool16_t mask, vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfmsac_tum(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmsac_vf_f16m1_rm_tum
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmsac.mask.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfmsac_vf_f16m1_rm_tum(vbool16_t mask, vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfmsac_tum(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmsac_vv_f16m2_rm_tum
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmsac.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
//
vfloat16m2_t test_vfmsac_vv_f16m2_rm_tum(vbool8_t mask, vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfmsac_tum(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmsac_vf_f16m2_rm_tum
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmsac.mask.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
//
vfloat16m2_t test_vfmsac_vf_f16m2_rm_tum(vbool8_t mask, vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfmsac_tum(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmsac_vv_f16m4_rm_tum
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmsac.mask.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
//
vfloat16m4_t test_vfmsac_vv_f16m4_rm_tum(vbool4_t mask, vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfmsac_tum(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmsac_vf_f16m4_rm_tum
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmsac.mask.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
//
vfloat16m4_t test_vfmsac_vf_f16m4_rm_tum(vbool4_t mask, vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfmsac_tum(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmsac_vv_f16m8_rm_tum
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmsac.mask.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
//
vfloat16m8_t test_vfmsac_vv_f16m8_rm_tum(vbool2_t mask, vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfmsac_tum(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmsac_vf_f16m8_rm_tum
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmsac.mask.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
//
vfloat16m8_t test_vfmsac_vf_f16m8_rm_tum(vbool2_t mask, vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfmsac_tum(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmsac_vv_f32mf2_rm_tum
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmsac.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
//
vfloat32mf2_t test_vfmsac_vv_f32mf2_rm_tum(vbool64_t mask, vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfmsac_tum(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmsac_vf_f32mf2_rm_tum
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmsac.mask.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
//
vfloat32mf2_t test_vfmsac_vf_f32mf2_rm_tum(vbool64_t mask, vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfmsac_tum(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmsac_vv_f32m1_rm_tum
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmsac.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfmsac_vv_f32m1_rm_tum(vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfmsac_tum(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmsac_vf_f32m1_rm_tum
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmsac.mask.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfmsac_vf_f32m1_rm_tum(vbool32_t mask, vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfmsac_tum(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmsac_vv_f32m2_rm_tum
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmsac.mask.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
//
vfloat32m2_t test_vfmsac_vv_f32m2_rm_tum(vbool16_t mask, vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfmsac_tum(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmsac_vf_f32m2_rm_tum
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmsac.mask.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
//
vfloat32m2_t test_vfmsac_vf_f32m2_rm_tum(vbool16_t mask, vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfmsac_tum(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmsac_vv_f32m4_rm_tum
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmsac.mask.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
//
vfloat32m4_t test_vfmsac_vv_f32m4_rm_tum(vbool8_t mask, vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfmsac_tum(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmsac_vf_f32m4_rm_tum
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmsac.mask.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
//
vfloat32m4_t test_vfmsac_vf_f32m4_rm_tum(vbool8_t mask, vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfmsac_tum(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmsac_vv_f32m8_rm_tum
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmsac.mask.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
//
vfloat32m8_t test_vfmsac_vv_f32m8_rm_tum(vbool4_t mask, vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfmsac_tum(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmsac_vf_f32m8_rm_tum
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmsac.mask.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
//
vfloat32m8_t test_vfmsac_vf_f32m8_rm_tum(vbool4_t mask, vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfmsac_tum(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmsac_vv_f64m1_rm_tum
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmsac.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfmsac_vv_f64m1_rm_tum(vbool64_t mask, vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfmsac_tum(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmsac_vf_f64m1_rm_tum
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmsac.mask.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfmsac_vf_f64m1_rm_tum(vbool64_t mask, vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfmsac_tum(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmsac_vv_f64m2_rm_tum
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmsac.mask.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
//
vfloat64m2_t test_vfmsac_vv_f64m2_rm_tum(vbool32_t mask, vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfmsac_tum(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmsac_vf_f64m2_rm_tum
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmsac.mask.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
//
vfloat64m2_t test_vfmsac_vf_f64m2_rm_tum(vbool32_t mask, vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfmsac_tum(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmsac_vv_f64m4_rm_tum
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmsac.mask.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
//
vfloat64m4_t test_vfmsac_vv_f64m4_rm_tum(vbool16_t mask, vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfmsac_tum(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmsac_vf_f64m4_rm_tum
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmsac.mask.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
//
vfloat64m4_t test_vfmsac_vf_f64m4_rm_tum(vbool16_t mask, vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfmsac_tum(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmsac_vv_f64m8_rm_tum
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmsac.mask.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
//
vfloat64m8_t test_vfmsac_vv_f64m8_rm_tum(vbool8_t mask, vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfmsac_tum(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmsac_vf_f64m8_rm_tum
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmsac.mask.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
//
vfloat64m8_t test_vfmsac_vf_f64m8_rm_tum(vbool8_t mask, vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfmsac_tum(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmsac_vv_f16mf4_rm_tumu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmsac.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
//
vfloat16mf4_t test_vfmsac_vv_f16mf4_rm_tumu(vbool64_t mask, vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfmsac_tumu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmsac_vf_f16mf4_rm_tumu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmsac.mask.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
//
vfloat16mf4_t test_vfmsac_vf_f16mf4_rm_tumu(vbool64_t mask, vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfmsac_tumu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmsac_vv_f16mf2_rm_tumu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmsac.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
//
vfloat16mf2_t test_vfmsac_vv_f16mf2_rm_tumu(vbool32_t mask, vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfmsac_tumu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmsac_vf_f16mf2_rm_tumu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmsac.mask.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
//
vfloat16mf2_t test_vfmsac_vf_f16mf2_rm_tumu(vbool32_t mask, vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfmsac_tumu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmsac_vv_f16m1_rm_tumu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmsac.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfmsac_vv_f16m1_rm_tumu(vbool16_t mask, vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfmsac_tumu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmsac_vf_f16m1_rm_tumu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmsac.mask.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfmsac_vf_f16m1_rm_tumu(vbool16_t mask, vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfmsac_tumu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmsac_vv_f16m2_rm_tumu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmsac.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
//
vfloat16m2_t test_vfmsac_vv_f16m2_rm_tumu(vbool8_t mask, vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfmsac_tumu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmsac_vf_f16m2_rm_tumu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmsac.mask.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
//
vfloat16m2_t test_vfmsac_vf_f16m2_rm_tumu(vbool8_t mask, vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfmsac_tumu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmsac_vv_f16m4_rm_tumu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmsac.mask.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
//
vfloat16m4_t test_vfmsac_vv_f16m4_rm_tumu(vbool4_t mask, vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfmsac_tumu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmsac_vf_f16m4_rm_tumu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmsac.mask.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
//
vfloat16m4_t test_vfmsac_vf_f16m4_rm_tumu(vbool4_t mask, vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfmsac_tumu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmsac_vv_f16m8_rm_tumu
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmsac.mask.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
//
vfloat16m8_t test_vfmsac_vv_f16m8_rm_tumu(vbool2_t mask, vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfmsac_tumu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmsac_vf_f16m8_rm_tumu
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmsac.mask.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
//
vfloat16m8_t test_vfmsac_vf_f16m8_rm_tumu(vbool2_t mask, vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfmsac_tumu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmsac_vv_f32mf2_rm_tumu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmsac.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
//
vfloat32mf2_t test_vfmsac_vv_f32mf2_rm_tumu(vbool64_t mask, vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfmsac_tumu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmsac_vf_f32mf2_rm_tumu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmsac.mask.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
//
vfloat32mf2_t test_vfmsac_vf_f32mf2_rm_tumu(vbool64_t mask, vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfmsac_tumu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmsac_vv_f32m1_rm_tumu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmsac.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfmsac_vv_f32m1_rm_tumu(vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfmsac_tumu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmsac_vf_f32m1_rm_tumu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmsac.mask.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfmsac_vf_f32m1_rm_tumu(vbool32_t mask, vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfmsac_tumu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmsac_vv_f32m2_rm_tumu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmsac.mask.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
//
vfloat32m2_t test_vfmsac_vv_f32m2_rm_tumu(vbool16_t mask, vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfmsac_tumu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmsac_vf_f32m2_rm_tumu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmsac.mask.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
//
vfloat32m2_t test_vfmsac_vf_f32m2_rm_tumu(vbool16_t mask, vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfmsac_tumu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmsac_vv_f32m4_rm_tumu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmsac.mask.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
//
vfloat32m4_t test_vfmsac_vv_f32m4_rm_tumu(vbool8_t mask, vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfmsac_tumu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmsac_vf_f32m4_rm_tumu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmsac.mask.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
//
vfloat32m4_t test_vfmsac_vf_f32m4_rm_tumu(vbool8_t mask, vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfmsac_tumu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmsac_vv_f32m8_rm_tumu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmsac.mask.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
//
vfloat32m8_t test_vfmsac_vv_f32m8_rm_tumu(vbool4_t mask, vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfmsac_tumu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmsac_vf_f32m8_rm_tumu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmsac.mask.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
//
vfloat32m8_t test_vfmsac_vf_f32m8_rm_tumu(vbool4_t mask, vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfmsac_tumu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmsac_vv_f64m1_rm_tumu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmsac.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfmsac_vv_f64m1_rm_tumu(vbool64_t mask, vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfmsac_tumu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmsac_vf_f64m1_rm_tumu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmsac.mask.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfmsac_vf_f64m1_rm_tumu(vbool64_t mask, vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfmsac_tumu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmsac_vv_f64m2_rm_tumu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmsac.mask.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
//
vfloat64m2_t test_vfmsac_vv_f64m2_rm_tumu(vbool32_t mask, vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfmsac_tumu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmsac_vf_f64m2_rm_tumu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmsac.mask.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
//
vfloat64m2_t test_vfmsac_vf_f64m2_rm_tumu(vbool32_t mask, vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfmsac_tumu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmsac_vv_f64m4_rm_tumu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmsac.mask.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
//
vfloat64m4_t test_vfmsac_vv_f64m4_rm_tumu(vbool16_t mask, vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfmsac_tumu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmsac_vf_f64m4_rm_tumu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmsac.mask.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
//
vfloat64m4_t test_vfmsac_vf_f64m4_rm_tumu(vbool16_t mask, vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfmsac_tumu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmsac_vv_f64m8_rm_tumu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmsac.mask.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
//
vfloat64m8_t test_vfmsac_vv_f64m8_rm_tumu(vbool8_t mask, vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfmsac_tumu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmsac_vf_f64m8_rm_tumu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmsac.mask.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
//
vfloat64m8_t test_vfmsac_vf_f64m8_rm_tumu(vbool8_t mask, vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfmsac_tumu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmsac_vv_f16mf4_rm_mu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmsac.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
//
vfloat16mf4_t test_vfmsac_vv_f16mf4_rm_mu(vbool64_t mask, vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfmsac_mu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmsac_vf_f16mf4_rm_mu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmsac.mask.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
//
vfloat16mf4_t test_vfmsac_vf_f16mf4_rm_mu(vbool64_t mask, vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfmsac_mu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmsac_vv_f16mf2_rm_mu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmsac.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
//
vfloat16mf2_t test_vfmsac_vv_f16mf2_rm_mu(vbool32_t mask, vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfmsac_mu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmsac_vf_f16mf2_rm_mu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmsac.mask.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
//
vfloat16mf2_t test_vfmsac_vf_f16mf2_rm_mu(vbool32_t mask, vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfmsac_mu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmsac_vv_f16m1_rm_mu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmsac.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfmsac_vv_f16m1_rm_mu(vbool16_t mask, vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfmsac_mu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmsac_vf_f16m1_rm_mu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmsac.mask.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfmsac_vf_f16m1_rm_mu(vbool16_t mask, vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfmsac_mu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmsac_vv_f16m2_rm_mu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmsac.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
//
vfloat16m2_t test_vfmsac_vv_f16m2_rm_mu(vbool8_t mask, vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfmsac_mu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmsac_vf_f16m2_rm_mu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmsac.mask.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
//
vfloat16m2_t test_vfmsac_vf_f16m2_rm_mu(vbool8_t mask, vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfmsac_mu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmsac_vv_f16m4_rm_mu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmsac.mask.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
//
vfloat16m4_t test_vfmsac_vv_f16m4_rm_mu(vbool4_t mask, vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfmsac_mu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmsac_vf_f16m4_rm_mu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmsac.mask.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
//
vfloat16m4_t test_vfmsac_vf_f16m4_rm_mu(vbool4_t mask, vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfmsac_mu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmsac_vv_f16m8_rm_mu
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmsac.mask.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
//
vfloat16m8_t test_vfmsac_vv_f16m8_rm_mu(vbool2_t mask, vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfmsac_mu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmsac_vf_f16m8_rm_mu
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmsac.mask.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
//
vfloat16m8_t test_vfmsac_vf_f16m8_rm_mu(vbool2_t mask, vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfmsac_mu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmsac_vv_f32mf2_rm_mu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmsac.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
//
vfloat32mf2_t test_vfmsac_vv_f32mf2_rm_mu(vbool64_t mask, vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfmsac_mu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmsac_vf_f32mf2_rm_mu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmsac.mask.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
//
vfloat32mf2_t test_vfmsac_vf_f32mf2_rm_mu(vbool64_t mask, vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfmsac_mu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmsac_vv_f32m1_rm_mu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmsac.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfmsac_vv_f32m1_rm_mu(vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfmsac_mu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmsac_vf_f32m1_rm_mu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmsac.mask.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfmsac_vf_f32m1_rm_mu(vbool32_t mask, vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfmsac_mu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmsac_vv_f32m2_rm_mu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmsac.mask.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
//
vfloat32m2_t test_vfmsac_vv_f32m2_rm_mu(vbool16_t mask, vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfmsac_mu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmsac_vf_f32m2_rm_mu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmsac.mask.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
//
vfloat32m2_t test_vfmsac_vf_f32m2_rm_mu(vbool16_t mask, vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfmsac_mu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmsac_vv_f32m4_rm_mu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmsac.mask.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
//
vfloat32m4_t test_vfmsac_vv_f32m4_rm_mu(vbool8_t mask, vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfmsac_mu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmsac_vf_f32m4_rm_mu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmsac.mask.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
//
vfloat32m4_t test_vfmsac_vf_f32m4_rm_mu(vbool8_t mask, vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfmsac_mu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmsac_vv_f32m8_rm_mu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmsac.mask.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
//
vfloat32m8_t test_vfmsac_vv_f32m8_rm_mu(vbool4_t mask, vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfmsac_mu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmsac_vf_f32m8_rm_mu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmsac.mask.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
//
vfloat32m8_t test_vfmsac_vf_f32m8_rm_mu(vbool4_t mask, vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfmsac_mu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmsac_vv_f64m1_rm_mu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmsac.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfmsac_vv_f64m1_rm_mu(vbool64_t mask, vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfmsac_mu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmsac_vf_f64m1_rm_mu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmsac.mask.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfmsac_vf_f64m1_rm_mu(vbool64_t mask, vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfmsac_mu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmsac_vv_f64m2_rm_mu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmsac.mask.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
//
vfloat64m2_t test_vfmsac_vv_f64m2_rm_mu(vbool32_t mask, vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfmsac_mu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmsac_vf_f64m2_rm_mu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmsac.mask.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
//
vfloat64m2_t test_vfmsac_vf_f64m2_rm_mu(vbool32_t mask, vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfmsac_mu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmsac_vv_f64m4_rm_mu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmsac.mask.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
//
vfloat64m4_t test_vfmsac_vv_f64m4_rm_mu(vbool16_t mask, vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfmsac_mu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmsac_vf_f64m4_rm_mu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmsac.mask.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
//
vfloat64m4_t test_vfmsac_vf_f64m4_rm_mu(vbool16_t mask, vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfmsac_mu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmsac_vv_f64m8_rm_mu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmsac.mask.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
//
vfloat64m8_t test_vfmsac_vv_f64m8_rm_mu(vbool8_t mask, vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfmsac_mu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmsac_vf_f64m8_rm_mu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmsac.mask.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
//
vfloat64m8_t test_vfmsac_vf_f64m8_rm_mu(vbool8_t mask, vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfmsac_mu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}

clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfmsub.c

// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target // REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh \ // RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh \
// RUN: -target-feature +experimental-zvfh -disable-O0-optnone \ // RUN: -target-feature +experimental-zvfh -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ // RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s // RUN: FileCheck --check-prefix=CHECK-RV64 %s
#include <riscv_vector.h> #include <riscv_vector.h>
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmsub_vv_f16mf4_tu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmsub_vv_f16mf4_tu
// CHECK-RV64-SAME: (<vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK-RV64-SAME: (<vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmsub.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmsub.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
// //
vfloat16mf4_t test_vfmsub_vv_f16mf4_tu(vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) { vfloat16mf4_t test_vfmsub_vv_f16mf4_tu(vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfmsub_tu(vd, vs1, vs2, vl); return __riscv_vfmsub_tu(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmsub_vf_f16mf4_tu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmsub_vf_f16mf4_tu
// CHECK-RV64-SAME: (<vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmsub.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmsub.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
// //
vfloat16mf4_t test_vfmsub_vf_f16mf4_tu(vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) { vfloat16mf4_t test_vfmsub_vf_f16mf4_tu(vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfmsub_tu(vd, rs1, vs2, vl); return __riscv_vfmsub_tu(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmsub_vv_f16mf2_tu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmsub_vv_f16mf2_tu
// CHECK-RV64-SAME: (<vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmsub.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmsub.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
// //
vfloat16mf2_t test_vfmsub_vv_f16mf2_tu(vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) { vfloat16mf2_t test_vfmsub_vv_f16mf2_tu(vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfmsub_tu(vd, vs1, vs2, vl); return __riscv_vfmsub_tu(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmsub_vf_f16mf2_tu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmsub_vf_f16mf2_tu
// CHECK-RV64-SAME: (<vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmsub.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmsub.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
// //
vfloat16mf2_t test_vfmsub_vf_f16mf2_tu(vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) { vfloat16mf2_t test_vfmsub_vf_f16mf2_tu(vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfmsub_tu(vd, rs1, vs2, vl); return __riscv_vfmsub_tu(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmsub_vv_f16m1_tu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmsub_vv_f16m1_tu
// CHECK-RV64-SAME: (<vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmsub.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmsub.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
// //
vfloat16m1_t test_vfmsub_vv_f16m1_tu(vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) { vfloat16m1_t test_vfmsub_vv_f16m1_tu(vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfmsub_tu(vd, vs1, vs2, vl); return __riscv_vfmsub_tu(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmsub_vf_f16m1_tu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmsub_vf_f16m1_tu
// CHECK-RV64-SAME: (<vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmsub.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmsub.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
// //
vfloat16m1_t test_vfmsub_vf_f16m1_tu(vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) { vfloat16m1_t test_vfmsub_vf_f16m1_tu(vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfmsub_tu(vd, rs1, vs2, vl); return __riscv_vfmsub_tu(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmsub_vv_f16m2_tu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmsub_vv_f16m2_tu
// CHECK-RV64-SAME: (<vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmsub.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmsub.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
// //
vfloat16m2_t test_vfmsub_vv_f16m2_tu(vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) { vfloat16m2_t test_vfmsub_vv_f16m2_tu(vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfmsub_tu(vd, vs1, vs2, vl); return __riscv_vfmsub_tu(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmsub_vf_f16m2_tu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmsub_vf_f16m2_tu
// CHECK-RV64-SAME: (<vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmsub.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmsub.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
// //
vfloat16m2_t test_vfmsub_vf_f16m2_tu(vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) { vfloat16m2_t test_vfmsub_vf_f16m2_tu(vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfmsub_tu(vd, rs1, vs2, vl); return __riscv_vfmsub_tu(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmsub_vv_f16m4_tu // CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmsub_vv_f16m4_tu
// CHECK-RV64-SAME: (<vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmsub.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmsub.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
// //
vfloat16m4_t test_vfmsub_vv_f16m4_tu(vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) { vfloat16m4_t test_vfmsub_vv_f16m4_tu(vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfmsub_tu(vd, vs1, vs2, vl); return __riscv_vfmsub_tu(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmsub_vf_f16m4_tu // CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmsub_vf_f16m4_tu
// CHECK-RV64-SAME: (<vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmsub.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmsub.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
// //
vfloat16m4_t test_vfmsub_vf_f16m4_tu(vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) { vfloat16m4_t test_vfmsub_vf_f16m4_tu(vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfmsub_tu(vd, rs1, vs2, vl); return __riscv_vfmsub_tu(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmsub_vv_f16m8_tu // CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmsub_vv_f16m8_tu
// CHECK-RV64-SAME: (<vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmsub.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmsub.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
// //
vfloat16m8_t test_vfmsub_vv_f16m8_tu(vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) { vfloat16m8_t test_vfmsub_vv_f16m8_tu(vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfmsub_tu(vd, vs1, vs2, vl); return __riscv_vfmsub_tu(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmsub_vf_f16m8_tu // CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmsub_vf_f16m8_tu
// CHECK-RV64-SAME: (<vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmsub.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmsub.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
// //
vfloat16m8_t test_vfmsub_vf_f16m8_tu(vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) { vfloat16m8_t test_vfmsub_vf_f16m8_tu(vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfmsub_tu(vd, rs1, vs2, vl); return __riscv_vfmsub_tu(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmsub_vv_f32mf2_tu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmsub_vv_f32mf2_tu
// CHECK-RV64-SAME: (<vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmsub.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmsub.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfmsub_vv_f32mf2_tu(vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) { vfloat32mf2_t test_vfmsub_vv_f32mf2_tu(vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfmsub_tu(vd, vs1, vs2, vl); return __riscv_vfmsub_tu(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmsub_vf_f32mf2_tu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmsub_vf_f32mf2_tu
// CHECK-RV64-SAME: (<vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmsub.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmsub.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfmsub_vf_f32mf2_tu(vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) { vfloat32mf2_t test_vfmsub_vf_f32mf2_tu(vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfmsub_tu(vd, rs1, vs2, vl); return __riscv_vfmsub_tu(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmsub_vv_f32m1_tu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmsub_vv_f32m1_tu
// CHECK-RV64-SAME: (<vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmsub.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmsub.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfmsub_vv_f32m1_tu(vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) { vfloat32m1_t test_vfmsub_vv_f32m1_tu(vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfmsub_tu(vd, vs1, vs2, vl); return __riscv_vfmsub_tu(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmsub_vf_f32m1_tu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmsub_vf_f32m1_tu
// CHECK-RV64-SAME: (<vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmsub.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmsub.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfmsub_vf_f32m1_tu(vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) { vfloat32m1_t test_vfmsub_vf_f32m1_tu(vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfmsub_tu(vd, rs1, vs2, vl); return __riscv_vfmsub_tu(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmsub_vv_f32m2_tu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmsub_vv_f32m2_tu
// CHECK-RV64-SAME: (<vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmsub.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmsub.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfmsub_vv_f32m2_tu(vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) { vfloat32m2_t test_vfmsub_vv_f32m2_tu(vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfmsub_tu(vd, vs1, vs2, vl); return __riscv_vfmsub_tu(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmsub_vf_f32m2_tu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmsub_vf_f32m2_tu
// CHECK-RV64-SAME: (<vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmsub.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmsub.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfmsub_vf_f32m2_tu(vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) { vfloat32m2_t test_vfmsub_vf_f32m2_tu(vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfmsub_tu(vd, rs1, vs2, vl); return __riscv_vfmsub_tu(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmsub_vv_f32m4_tu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmsub_vv_f32m4_tu
// CHECK-RV64-SAME: (<vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmsub.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmsub.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfmsub_vv_f32m4_tu(vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) { vfloat32m4_t test_vfmsub_vv_f32m4_tu(vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfmsub_tu(vd, vs1, vs2, vl); return __riscv_vfmsub_tu(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmsub_vf_f32m4_tu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmsub_vf_f32m4_tu
// CHECK-RV64-SAME: (<vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmsub.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmsub.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfmsub_vf_f32m4_tu(vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) { vfloat32m4_t test_vfmsub_vf_f32m4_tu(vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfmsub_tu(vd, rs1, vs2, vl); return __riscv_vfmsub_tu(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmsub_vv_f32m8_tu // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmsub_vv_f32m8_tu
// CHECK-RV64-SAME: (<vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmsub.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmsub.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfmsub_vv_f32m8_tu(vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) { vfloat32m8_t test_vfmsub_vv_f32m8_tu(vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfmsub_tu(vd, vs1, vs2, vl); return __riscv_vfmsub_tu(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmsub_vf_f32m8_tu // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmsub_vf_f32m8_tu
// CHECK-RV64-SAME: (<vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmsub.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmsub.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfmsub_vf_f32m8_tu(vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) { vfloat32m8_t test_vfmsub_vf_f32m8_tu(vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfmsub_tu(vd, rs1, vs2, vl); return __riscv_vfmsub_tu(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmsub_vv_f64m1_tu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmsub_vv_f64m1_tu
// CHECK-RV64-SAME: (<vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmsub.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmsub.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfmsub_vv_f64m1_tu(vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) { vfloat64m1_t test_vfmsub_vv_f64m1_tu(vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfmsub_tu(vd, vs1, vs2, vl); return __riscv_vfmsub_tu(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmsub_vf_f64m1_tu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmsub_vf_f64m1_tu
// CHECK-RV64-SAME: (<vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmsub.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmsub.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfmsub_vf_f64m1_tu(vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) { vfloat64m1_t test_vfmsub_vf_f64m1_tu(vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfmsub_tu(vd, rs1, vs2, vl); return __riscv_vfmsub_tu(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmsub_vv_f64m2_tu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmsub_vv_f64m2_tu
// CHECK-RV64-SAME: (<vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmsub.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmsub.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfmsub_vv_f64m2_tu(vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) { vfloat64m2_t test_vfmsub_vv_f64m2_tu(vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfmsub_tu(vd, vs1, vs2, vl); return __riscv_vfmsub_tu(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmsub_vf_f64m2_tu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmsub_vf_f64m2_tu
// CHECK-RV64-SAME: (<vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmsub.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmsub.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfmsub_vf_f64m2_tu(vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) { vfloat64m2_t test_vfmsub_vf_f64m2_tu(vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfmsub_tu(vd, rs1, vs2, vl); return __riscv_vfmsub_tu(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmsub_vv_f64m4_tu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmsub_vv_f64m4_tu
// CHECK-RV64-SAME: (<vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmsub.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmsub.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfmsub_vv_f64m4_tu(vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) { vfloat64m4_t test_vfmsub_vv_f64m4_tu(vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfmsub_tu(vd, vs1, vs2, vl); return __riscv_vfmsub_tu(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmsub_vf_f64m4_tu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmsub_vf_f64m4_tu
// CHECK-RV64-SAME: (<vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmsub.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmsub.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfmsub_vf_f64m4_tu(vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) { vfloat64m4_t test_vfmsub_vf_f64m4_tu(vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfmsub_tu(vd, rs1, vs2, vl); return __riscv_vfmsub_tu(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmsub_vv_f64m8_tu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmsub_vv_f64m8_tu
// CHECK-RV64-SAME: (<vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmsub.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmsub.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfmsub_vv_f64m8_tu(vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) { vfloat64m8_t test_vfmsub_vv_f64m8_tu(vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfmsub_tu(vd, vs1, vs2, vl); return __riscv_vfmsub_tu(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmsub_vf_f64m8_tu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmsub_vf_f64m8_tu
// CHECK-RV64-SAME: (<vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmsub.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmsub.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfmsub_vf_f64m8_tu(vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) { vfloat64m8_t test_vfmsub_vf_f64m8_tu(vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfmsub_tu(vd, rs1, vs2, vl); return __riscv_vfmsub_tu(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmsub_vv_f16mf4_tum // CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmsub_vv_f16mf4_tum
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmsub.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmsub.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
// //
vfloat16mf4_t test_vfmsub_vv_f16mf4_tum(vbool64_t mask, vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) { vfloat16mf4_t test_vfmsub_vv_f16mf4_tum(vbool64_t mask, vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfmsub_tum(mask, vd, vs1, vs2, vl); return __riscv_vfmsub_tum(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmsub_vf_f16mf4_tum // CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmsub_vf_f16mf4_tum
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmsub.mask.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmsub.mask.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
// //
vfloat16mf4_t test_vfmsub_vf_f16mf4_tum(vbool64_t mask, vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) { vfloat16mf4_t test_vfmsub_vf_f16mf4_tum(vbool64_t mask, vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfmsub_tum(mask, vd, rs1, vs2, vl); return __riscv_vfmsub_tum(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmsub_vv_f16mf2_tum // CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmsub_vv_f16mf2_tum
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmsub.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmsub.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
// //
vfloat16mf2_t test_vfmsub_vv_f16mf2_tum(vbool32_t mask, vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) { vfloat16mf2_t test_vfmsub_vv_f16mf2_tum(vbool32_t mask, vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfmsub_tum(mask, vd, vs1, vs2, vl); return __riscv_vfmsub_tum(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmsub_vf_f16mf2_tum // CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmsub_vf_f16mf2_tum
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmsub.mask.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmsub.mask.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
// //
vfloat16mf2_t test_vfmsub_vf_f16mf2_tum(vbool32_t mask, vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) { vfloat16mf2_t test_vfmsub_vf_f16mf2_tum(vbool32_t mask, vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfmsub_tum(mask, vd, rs1, vs2, vl); return __riscv_vfmsub_tum(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmsub_vv_f16m1_tum // CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmsub_vv_f16m1_tum
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmsub.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmsub.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
// //
vfloat16m1_t test_vfmsub_vv_f16m1_tum(vbool16_t mask, vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) { vfloat16m1_t test_vfmsub_vv_f16m1_tum(vbool16_t mask, vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfmsub_tum(mask, vd, vs1, vs2, vl); return __riscv_vfmsub_tum(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmsub_vf_f16m1_tum // CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmsub_vf_f16m1_tum
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmsub.mask.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmsub.mask.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
// //
vfloat16m1_t test_vfmsub_vf_f16m1_tum(vbool16_t mask, vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) { vfloat16m1_t test_vfmsub_vf_f16m1_tum(vbool16_t mask, vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfmsub_tum(mask, vd, rs1, vs2, vl); return __riscv_vfmsub_tum(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmsub_vv_f16m2_tum // CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmsub_vv_f16m2_tum
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmsub.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmsub.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
// //
vfloat16m2_t test_vfmsub_vv_f16m2_tum(vbool8_t mask, vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) { vfloat16m2_t test_vfmsub_vv_f16m2_tum(vbool8_t mask, vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfmsub_tum(mask, vd, vs1, vs2, vl); return __riscv_vfmsub_tum(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmsub_vf_f16m2_tum // CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmsub_vf_f16m2_tum
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmsub.mask.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmsub.mask.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
// //
vfloat16m2_t test_vfmsub_vf_f16m2_tum(vbool8_t mask, vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) { vfloat16m2_t test_vfmsub_vf_f16m2_tum(vbool8_t mask, vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfmsub_tum(mask, vd, rs1, vs2, vl); return __riscv_vfmsub_tum(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmsub_vv_f16m4_tum // CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmsub_vv_f16m4_tum
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmsub.mask.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmsub.mask.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
// //
vfloat16m4_t test_vfmsub_vv_f16m4_tum(vbool4_t mask, vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) { vfloat16m4_t test_vfmsub_vv_f16m4_tum(vbool4_t mask, vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfmsub_tum(mask, vd, vs1, vs2, vl); return __riscv_vfmsub_tum(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmsub_vf_f16m4_tum // CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmsub_vf_f16m4_tum
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmsub.mask.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmsub.mask.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
// //
vfloat16m4_t test_vfmsub_vf_f16m4_tum(vbool4_t mask, vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) { vfloat16m4_t test_vfmsub_vf_f16m4_tum(vbool4_t mask, vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfmsub_tum(mask, vd, rs1, vs2, vl); return __riscv_vfmsub_tum(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmsub_vv_f16m8_tum // CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmsub_vv_f16m8_tum
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmsub.mask.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmsub.mask.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
// //
vfloat16m8_t test_vfmsub_vv_f16m8_tum(vbool2_t mask, vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) { vfloat16m8_t test_vfmsub_vv_f16m8_tum(vbool2_t mask, vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfmsub_tum(mask, vd, vs1, vs2, vl); return __riscv_vfmsub_tum(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmsub_vf_f16m8_tum // CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmsub_vf_f16m8_tum
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmsub.mask.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmsub.mask.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
// //
vfloat16m8_t test_vfmsub_vf_f16m8_tum(vbool2_t mask, vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) { vfloat16m8_t test_vfmsub_vf_f16m8_tum(vbool2_t mask, vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfmsub_tum(mask, vd, rs1, vs2, vl); return __riscv_vfmsub_tum(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmsub_vv_f32mf2_tum // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmsub_vv_f32mf2_tum
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmsub.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmsub.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfmsub_vv_f32mf2_tum(vbool64_t mask, vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) { vfloat32mf2_t test_vfmsub_vv_f32mf2_tum(vbool64_t mask, vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfmsub_tum(mask, vd, vs1, vs2, vl); return __riscv_vfmsub_tum(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmsub_vf_f32mf2_tum // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmsub_vf_f32mf2_tum
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmsub.mask.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmsub.mask.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfmsub_vf_f32mf2_tum(vbool64_t mask, vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) { vfloat32mf2_t test_vfmsub_vf_f32mf2_tum(vbool64_t mask, vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfmsub_tum(mask, vd, rs1, vs2, vl); return __riscv_vfmsub_tum(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmsub_vv_f32m1_tum // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmsub_vv_f32m1_tum
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmsub.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmsub.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfmsub_vv_f32m1_tum(vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) { vfloat32m1_t test_vfmsub_vv_f32m1_tum(vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfmsub_tum(mask, vd, vs1, vs2, vl); return __riscv_vfmsub_tum(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmsub_vf_f32m1_tum // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmsub_vf_f32m1_tum
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmsub.mask.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmsub.mask.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfmsub_vf_f32m1_tum(vbool32_t mask, vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) { vfloat32m1_t test_vfmsub_vf_f32m1_tum(vbool32_t mask, vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfmsub_tum(mask, vd, rs1, vs2, vl); return __riscv_vfmsub_tum(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmsub_vv_f32m2_tum // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmsub_vv_f32m2_tum
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmsub.mask.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmsub.mask.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfmsub_vv_f32m2_tum(vbool16_t mask, vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) { vfloat32m2_t test_vfmsub_vv_f32m2_tum(vbool16_t mask, vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfmsub_tum(mask, vd, vs1, vs2, vl); return __riscv_vfmsub_tum(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmsub_vf_f32m2_tum // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmsub_vf_f32m2_tum
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmsub.mask.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmsub.mask.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfmsub_vf_f32m2_tum(vbool16_t mask, vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) { vfloat32m2_t test_vfmsub_vf_f32m2_tum(vbool16_t mask, vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfmsub_tum(mask, vd, rs1, vs2, vl); return __riscv_vfmsub_tum(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmsub_vv_f32m4_tum // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmsub_vv_f32m4_tum
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmsub.mask.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmsub.mask.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfmsub_vv_f32m4_tum(vbool8_t mask, vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) { vfloat32m4_t test_vfmsub_vv_f32m4_tum(vbool8_t mask, vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfmsub_tum(mask, vd, vs1, vs2, vl); return __riscv_vfmsub_tum(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmsub_vf_f32m4_tum // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmsub_vf_f32m4_tum
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmsub.mask.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmsub.mask.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfmsub_vf_f32m4_tum(vbool8_t mask, vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) { vfloat32m4_t test_vfmsub_vf_f32m4_tum(vbool8_t mask, vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfmsub_tum(mask, vd, rs1, vs2, vl); return __riscv_vfmsub_tum(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmsub_vv_f32m8_tum // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmsub_vv_f32m8_tum
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmsub.mask.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmsub.mask.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfmsub_vv_f32m8_tum(vbool4_t mask, vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) { vfloat32m8_t test_vfmsub_vv_f32m8_tum(vbool4_t mask, vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfmsub_tum(mask, vd, vs1, vs2, vl); return __riscv_vfmsub_tum(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmsub_vf_f32m8_tum // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmsub_vf_f32m8_tum
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmsub.mask.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmsub.mask.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfmsub_vf_f32m8_tum(vbool4_t mask, vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) { vfloat32m8_t test_vfmsub_vf_f32m8_tum(vbool4_t mask, vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfmsub_tum(mask, vd, rs1, vs2, vl); return __riscv_vfmsub_tum(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmsub_vv_f64m1_tum // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmsub_vv_f64m1_tum
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmsub.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmsub.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfmsub_vv_f64m1_tum(vbool64_t mask, vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) { vfloat64m1_t test_vfmsub_vv_f64m1_tum(vbool64_t mask, vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfmsub_tum(mask, vd, vs1, vs2, vl); return __riscv_vfmsub_tum(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmsub_vf_f64m1_tum // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmsub_vf_f64m1_tum
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmsub.mask.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmsub.mask.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfmsub_vf_f64m1_tum(vbool64_t mask, vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) { vfloat64m1_t test_vfmsub_vf_f64m1_tum(vbool64_t mask, vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfmsub_tum(mask, vd, rs1, vs2, vl); return __riscv_vfmsub_tum(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmsub_vv_f64m2_tum // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmsub_vv_f64m2_tum
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmsub.mask.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmsub.mask.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfmsub_vv_f64m2_tum(vbool32_t mask, vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) { vfloat64m2_t test_vfmsub_vv_f64m2_tum(vbool32_t mask, vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfmsub_tum(mask, vd, vs1, vs2, vl); return __riscv_vfmsub_tum(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmsub_vf_f64m2_tum // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmsub_vf_f64m2_tum
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmsub.mask.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmsub.mask.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfmsub_vf_f64m2_tum(vbool32_t mask, vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) { vfloat64m2_t test_vfmsub_vf_f64m2_tum(vbool32_t mask, vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfmsub_tum(mask, vd, rs1, vs2, vl); return __riscv_vfmsub_tum(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmsub_vv_f64m4_tum // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmsub_vv_f64m4_tum
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmsub.mask.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmsub.mask.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfmsub_vv_f64m4_tum(vbool16_t mask, vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) { vfloat64m4_t test_vfmsub_vv_f64m4_tum(vbool16_t mask, vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfmsub_tum(mask, vd, vs1, vs2, vl); return __riscv_vfmsub_tum(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmsub_vf_f64m4_tum // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmsub_vf_f64m4_tum
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmsub.mask.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmsub.mask.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfmsub_vf_f64m4_tum(vbool16_t mask, vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) { vfloat64m4_t test_vfmsub_vf_f64m4_tum(vbool16_t mask, vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfmsub_tum(mask, vd, rs1, vs2, vl); return __riscv_vfmsub_tum(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmsub_vv_f64m8_tum // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmsub_vv_f64m8_tum
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmsub.mask.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmsub.mask.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfmsub_vv_f64m8_tum(vbool8_t mask, vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) { vfloat64m8_t test_vfmsub_vv_f64m8_tum(vbool8_t mask, vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfmsub_tum(mask, vd, vs1, vs2, vl); return __riscv_vfmsub_tum(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmsub_vf_f64m8_tum // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmsub_vf_f64m8_tum
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmsub.mask.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmsub.mask.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfmsub_vf_f64m8_tum(vbool8_t mask, vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) { vfloat64m8_t test_vfmsub_vf_f64m8_tum(vbool8_t mask, vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfmsub_tum(mask, vd, rs1, vs2, vl); return __riscv_vfmsub_tum(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmsub_vv_f16mf4_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmsub_vv_f16mf4_tumu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmsub.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmsub.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
// //
vfloat16mf4_t test_vfmsub_vv_f16mf4_tumu(vbool64_t mask, vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) { vfloat16mf4_t test_vfmsub_vv_f16mf4_tumu(vbool64_t mask, vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfmsub_tumu(mask, vd, vs1, vs2, vl); return __riscv_vfmsub_tumu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmsub_vf_f16mf4_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmsub_vf_f16mf4_tumu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmsub.mask.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmsub.mask.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
// //
vfloat16mf4_t test_vfmsub_vf_f16mf4_tumu(vbool64_t mask, vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) { vfloat16mf4_t test_vfmsub_vf_f16mf4_tumu(vbool64_t mask, vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfmsub_tumu(mask, vd, rs1, vs2, vl); return __riscv_vfmsub_tumu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmsub_vv_f16mf2_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmsub_vv_f16mf2_tumu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmsub.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmsub.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
// //
vfloat16mf2_t test_vfmsub_vv_f16mf2_tumu(vbool32_t mask, vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) { vfloat16mf2_t test_vfmsub_vv_f16mf2_tumu(vbool32_t mask, vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfmsub_tumu(mask, vd, vs1, vs2, vl); return __riscv_vfmsub_tumu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmsub_vf_f16mf2_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmsub_vf_f16mf2_tumu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmsub.mask.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmsub.mask.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
// //
vfloat16mf2_t test_vfmsub_vf_f16mf2_tumu(vbool32_t mask, vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) { vfloat16mf2_t test_vfmsub_vf_f16mf2_tumu(vbool32_t mask, vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfmsub_tumu(mask, vd, rs1, vs2, vl); return __riscv_vfmsub_tumu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmsub_vv_f16m1_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmsub_vv_f16m1_tumu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmsub.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmsub.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
// //
vfloat16m1_t test_vfmsub_vv_f16m1_tumu(vbool16_t mask, vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) { vfloat16m1_t test_vfmsub_vv_f16m1_tumu(vbool16_t mask, vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfmsub_tumu(mask, vd, vs1, vs2, vl); return __riscv_vfmsub_tumu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmsub_vf_f16m1_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmsub_vf_f16m1_tumu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmsub.mask.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmsub.mask.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
// //
vfloat16m1_t test_vfmsub_vf_f16m1_tumu(vbool16_t mask, vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) { vfloat16m1_t test_vfmsub_vf_f16m1_tumu(vbool16_t mask, vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfmsub_tumu(mask, vd, rs1, vs2, vl); return __riscv_vfmsub_tumu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmsub_vv_f16m2_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmsub_vv_f16m2_tumu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmsub.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmsub.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
// //
vfloat16m2_t test_vfmsub_vv_f16m2_tumu(vbool8_t mask, vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) { vfloat16m2_t test_vfmsub_vv_f16m2_tumu(vbool8_t mask, vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfmsub_tumu(mask, vd, vs1, vs2, vl); return __riscv_vfmsub_tumu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmsub_vf_f16m2_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmsub_vf_f16m2_tumu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmsub.mask.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmsub.mask.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
// //
vfloat16m2_t test_vfmsub_vf_f16m2_tumu(vbool8_t mask, vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) { vfloat16m2_t test_vfmsub_vf_f16m2_tumu(vbool8_t mask, vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfmsub_tumu(mask, vd, rs1, vs2, vl); return __riscv_vfmsub_tumu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmsub_vv_f16m4_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmsub_vv_f16m4_tumu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmsub.mask.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmsub.mask.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
// //
vfloat16m4_t test_vfmsub_vv_f16m4_tumu(vbool4_t mask, vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) { vfloat16m4_t test_vfmsub_vv_f16m4_tumu(vbool4_t mask, vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfmsub_tumu(mask, vd, vs1, vs2, vl); return __riscv_vfmsub_tumu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmsub_vf_f16m4_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmsub_vf_f16m4_tumu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmsub.mask.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmsub.mask.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
// //
vfloat16m4_t test_vfmsub_vf_f16m4_tumu(vbool4_t mask, vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) { vfloat16m4_t test_vfmsub_vf_f16m4_tumu(vbool4_t mask, vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfmsub_tumu(mask, vd, rs1, vs2, vl); return __riscv_vfmsub_tumu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmsub_vv_f16m8_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmsub_vv_f16m8_tumu
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmsub.mask.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmsub.mask.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
// //
vfloat16m8_t test_vfmsub_vv_f16m8_tumu(vbool2_t mask, vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) { vfloat16m8_t test_vfmsub_vv_f16m8_tumu(vbool2_t mask, vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfmsub_tumu(mask, vd, vs1, vs2, vl); return __riscv_vfmsub_tumu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmsub_vf_f16m8_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmsub_vf_f16m8_tumu
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmsub.mask.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmsub.mask.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
// //
vfloat16m8_t test_vfmsub_vf_f16m8_tumu(vbool2_t mask, vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) { vfloat16m8_t test_vfmsub_vf_f16m8_tumu(vbool2_t mask, vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfmsub_tumu(mask, vd, rs1, vs2, vl); return __riscv_vfmsub_tumu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmsub_vv_f32mf2_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmsub_vv_f32mf2_tumu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmsub.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmsub.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfmsub_vv_f32mf2_tumu(vbool64_t mask, vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) { vfloat32mf2_t test_vfmsub_vv_f32mf2_tumu(vbool64_t mask, vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfmsub_tumu(mask, vd, vs1, vs2, vl); return __riscv_vfmsub_tumu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmsub_vf_f32mf2_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmsub_vf_f32mf2_tumu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmsub.mask.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmsub.mask.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfmsub_vf_f32mf2_tumu(vbool64_t mask, vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) { vfloat32mf2_t test_vfmsub_vf_f32mf2_tumu(vbool64_t mask, vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfmsub_tumu(mask, vd, rs1, vs2, vl); return __riscv_vfmsub_tumu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmsub_vv_f32m1_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmsub_vv_f32m1_tumu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmsub.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmsub.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfmsub_vv_f32m1_tumu(vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) { vfloat32m1_t test_vfmsub_vv_f32m1_tumu(vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfmsub_tumu(mask, vd, vs1, vs2, vl); return __riscv_vfmsub_tumu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmsub_vf_f32m1_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmsub_vf_f32m1_tumu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmsub.mask.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmsub.mask.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfmsub_vf_f32m1_tumu(vbool32_t mask, vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) { vfloat32m1_t test_vfmsub_vf_f32m1_tumu(vbool32_t mask, vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfmsub_tumu(mask, vd, rs1, vs2, vl); return __riscv_vfmsub_tumu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmsub_vv_f32m2_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmsub_vv_f32m2_tumu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmsub.mask.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmsub.mask.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfmsub_vv_f32m2_tumu(vbool16_t mask, vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) { vfloat32m2_t test_vfmsub_vv_f32m2_tumu(vbool16_t mask, vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfmsub_tumu(mask, vd, vs1, vs2, vl); return __riscv_vfmsub_tumu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmsub_vf_f32m2_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmsub_vf_f32m2_tumu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmsub.mask.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmsub.mask.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfmsub_vf_f32m2_tumu(vbool16_t mask, vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) { vfloat32m2_t test_vfmsub_vf_f32m2_tumu(vbool16_t mask, vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfmsub_tumu(mask, vd, rs1, vs2, vl); return __riscv_vfmsub_tumu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmsub_vv_f32m4_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmsub_vv_f32m4_tumu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmsub.mask.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmsub.mask.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfmsub_vv_f32m4_tumu(vbool8_t mask, vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) { vfloat32m4_t test_vfmsub_vv_f32m4_tumu(vbool8_t mask, vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfmsub_tumu(mask, vd, vs1, vs2, vl); return __riscv_vfmsub_tumu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmsub_vf_f32m4_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmsub_vf_f32m4_tumu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmsub.mask.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmsub.mask.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfmsub_vf_f32m4_tumu(vbool8_t mask, vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) { vfloat32m4_t test_vfmsub_vf_f32m4_tumu(vbool8_t mask, vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfmsub_tumu(mask, vd, rs1, vs2, vl); return __riscv_vfmsub_tumu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmsub_vv_f32m8_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmsub_vv_f32m8_tumu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmsub.mask.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmsub.mask.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfmsub_vv_f32m8_tumu(vbool4_t mask, vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) { vfloat32m8_t test_vfmsub_vv_f32m8_tumu(vbool4_t mask, vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfmsub_tumu(mask, vd, vs1, vs2, vl); return __riscv_vfmsub_tumu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmsub_vf_f32m8_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmsub_vf_f32m8_tumu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmsub.mask.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmsub.mask.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfmsub_vf_f32m8_tumu(vbool4_t mask, vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) { vfloat32m8_t test_vfmsub_vf_f32m8_tumu(vbool4_t mask, vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfmsub_tumu(mask, vd, rs1, vs2, vl); return __riscv_vfmsub_tumu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmsub_vv_f64m1_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmsub_vv_f64m1_tumu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmsub.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmsub.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfmsub_vv_f64m1_tumu(vbool64_t mask, vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) { vfloat64m1_t test_vfmsub_vv_f64m1_tumu(vbool64_t mask, vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfmsub_tumu(mask, vd, vs1, vs2, vl); return __riscv_vfmsub_tumu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmsub_vf_f64m1_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmsub_vf_f64m1_tumu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmsub.mask.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmsub.mask.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfmsub_vf_f64m1_tumu(vbool64_t mask, vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) { vfloat64m1_t test_vfmsub_vf_f64m1_tumu(vbool64_t mask, vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfmsub_tumu(mask, vd, rs1, vs2, vl); return __riscv_vfmsub_tumu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmsub_vv_f64m2_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmsub_vv_f64m2_tumu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmsub.mask.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmsub.mask.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfmsub_vv_f64m2_tumu(vbool32_t mask, vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) { vfloat64m2_t test_vfmsub_vv_f64m2_tumu(vbool32_t mask, vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfmsub_tumu(mask, vd, vs1, vs2, vl); return __riscv_vfmsub_tumu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmsub_vf_f64m2_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmsub_vf_f64m2_tumu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmsub.mask.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmsub.mask.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfmsub_vf_f64m2_tumu(vbool32_t mask, vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) { vfloat64m2_t test_vfmsub_vf_f64m2_tumu(vbool32_t mask, vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfmsub_tumu(mask, vd, rs1, vs2, vl); return __riscv_vfmsub_tumu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmsub_vv_f64m4_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmsub_vv_f64m4_tumu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmsub.mask.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmsub.mask.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfmsub_vv_f64m4_tumu(vbool16_t mask, vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) { vfloat64m4_t test_vfmsub_vv_f64m4_tumu(vbool16_t mask, vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfmsub_tumu(mask, vd, vs1, vs2, vl); return __riscv_vfmsub_tumu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmsub_vf_f64m4_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmsub_vf_f64m4_tumu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmsub.mask.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmsub.mask.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfmsub_vf_f64m4_tumu(vbool16_t mask, vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) { vfloat64m4_t test_vfmsub_vf_f64m4_tumu(vbool16_t mask, vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfmsub_tumu(mask, vd, rs1, vs2, vl); return __riscv_vfmsub_tumu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmsub_vv_f64m8_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmsub_vv_f64m8_tumu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmsub.mask.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmsub.mask.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfmsub_vv_f64m8_tumu(vbool8_t mask, vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) { vfloat64m8_t test_vfmsub_vv_f64m8_tumu(vbool8_t mask, vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfmsub_tumu(mask, vd, vs1, vs2, vl); return __riscv_vfmsub_tumu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmsub_vf_f64m8_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmsub_vf_f64m8_tumu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmsub.mask.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmsub.mask.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfmsub_vf_f64m8_tumu(vbool8_t mask, vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) { vfloat64m8_t test_vfmsub_vf_f64m8_tumu(vbool8_t mask, vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfmsub_tumu(mask, vd, rs1, vs2, vl); return __riscv_vfmsub_tumu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmsub_vv_f16mf4_mu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmsub_vv_f16mf4_mu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmsub.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmsub.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
// //
vfloat16mf4_t test_vfmsub_vv_f16mf4_mu(vbool64_t mask, vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) { vfloat16mf4_t test_vfmsub_vv_f16mf4_mu(vbool64_t mask, vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfmsub_mu(mask, vd, vs1, vs2, vl); return __riscv_vfmsub_mu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmsub_vf_f16mf4_mu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmsub_vf_f16mf4_mu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmsub.mask.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmsub.mask.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
// //
vfloat16mf4_t test_vfmsub_vf_f16mf4_mu(vbool64_t mask, vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) { vfloat16mf4_t test_vfmsub_vf_f16mf4_mu(vbool64_t mask, vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfmsub_mu(mask, vd, rs1, vs2, vl); return __riscv_vfmsub_mu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmsub_vv_f16mf2_mu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmsub_vv_f16mf2_mu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmsub.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmsub.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
// //
vfloat16mf2_t test_vfmsub_vv_f16mf2_mu(vbool32_t mask, vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) { vfloat16mf2_t test_vfmsub_vv_f16mf2_mu(vbool32_t mask, vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfmsub_mu(mask, vd, vs1, vs2, vl); return __riscv_vfmsub_mu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmsub_vf_f16mf2_mu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmsub_vf_f16mf2_mu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmsub.mask.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmsub.mask.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
// //
vfloat16mf2_t test_vfmsub_vf_f16mf2_mu(vbool32_t mask, vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) { vfloat16mf2_t test_vfmsub_vf_f16mf2_mu(vbool32_t mask, vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfmsub_mu(mask, vd, rs1, vs2, vl); return __riscv_vfmsub_mu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmsub_vv_f16m1_mu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmsub_vv_f16m1_mu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmsub.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmsub.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
// //
vfloat16m1_t test_vfmsub_vv_f16m1_mu(vbool16_t mask, vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) { vfloat16m1_t test_vfmsub_vv_f16m1_mu(vbool16_t mask, vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfmsub_mu(mask, vd, vs1, vs2, vl); return __riscv_vfmsub_mu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmsub_vf_f16m1_mu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmsub_vf_f16m1_mu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmsub.mask.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmsub.mask.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
// //
vfloat16m1_t test_vfmsub_vf_f16m1_mu(vbool16_t mask, vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) { vfloat16m1_t test_vfmsub_vf_f16m1_mu(vbool16_t mask, vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfmsub_mu(mask, vd, rs1, vs2, vl); return __riscv_vfmsub_mu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmsub_vv_f16m2_mu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmsub_vv_f16m2_mu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmsub.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmsub.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
// //
vfloat16m2_t test_vfmsub_vv_f16m2_mu(vbool8_t mask, vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) { vfloat16m2_t test_vfmsub_vv_f16m2_mu(vbool8_t mask, vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfmsub_mu(mask, vd, vs1, vs2, vl); return __riscv_vfmsub_mu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmsub_vf_f16m2_mu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmsub_vf_f16m2_mu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmsub.mask.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmsub.mask.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
// //
vfloat16m2_t test_vfmsub_vf_f16m2_mu(vbool8_t mask, vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) { vfloat16m2_t test_vfmsub_vf_f16m2_mu(vbool8_t mask, vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfmsub_mu(mask, vd, rs1, vs2, vl); return __riscv_vfmsub_mu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmsub_vv_f16m4_mu // CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmsub_vv_f16m4_mu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmsub.mask.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmsub.mask.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
// //
vfloat16m4_t test_vfmsub_vv_f16m4_mu(vbool4_t mask, vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) { vfloat16m4_t test_vfmsub_vv_f16m4_mu(vbool4_t mask, vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfmsub_mu(mask, vd, vs1, vs2, vl); return __riscv_vfmsub_mu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmsub_vf_f16m4_mu // CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmsub_vf_f16m4_mu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmsub.mask.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmsub.mask.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
// //
vfloat16m4_t test_vfmsub_vf_f16m4_mu(vbool4_t mask, vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) { vfloat16m4_t test_vfmsub_vf_f16m4_mu(vbool4_t mask, vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfmsub_mu(mask, vd, rs1, vs2, vl); return __riscv_vfmsub_mu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmsub_vv_f16m8_mu // CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmsub_vv_f16m8_mu
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmsub.mask.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmsub.mask.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
// //
vfloat16m8_t test_vfmsub_vv_f16m8_mu(vbool2_t mask, vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) { vfloat16m8_t test_vfmsub_vv_f16m8_mu(vbool2_t mask, vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfmsub_mu(mask, vd, vs1, vs2, vl); return __riscv_vfmsub_mu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmsub_vf_f16m8_mu // CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmsub_vf_f16m8_mu
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmsub.mask.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmsub.mask.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
// //
vfloat16m8_t test_vfmsub_vf_f16m8_mu(vbool2_t mask, vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) { vfloat16m8_t test_vfmsub_vf_f16m8_mu(vbool2_t mask, vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfmsub_mu(mask, vd, rs1, vs2, vl); return __riscv_vfmsub_mu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmsub_vv_f32mf2_mu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmsub_vv_f32mf2_mu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmsub.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmsub.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfmsub_vv_f32mf2_mu(vbool64_t mask, vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) { vfloat32mf2_t test_vfmsub_vv_f32mf2_mu(vbool64_t mask, vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfmsub_mu(mask, vd, vs1, vs2, vl); return __riscv_vfmsub_mu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmsub_vf_f32mf2_mu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmsub_vf_f32mf2_mu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmsub.mask.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmsub.mask.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfmsub_vf_f32mf2_mu(vbool64_t mask, vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) { vfloat32mf2_t test_vfmsub_vf_f32mf2_mu(vbool64_t mask, vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfmsub_mu(mask, vd, rs1, vs2, vl); return __riscv_vfmsub_mu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmsub_vv_f32m1_mu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmsub_vv_f32m1_mu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmsub.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmsub.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfmsub_vv_f32m1_mu(vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) { vfloat32m1_t test_vfmsub_vv_f32m1_mu(vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfmsub_mu(mask, vd, vs1, vs2, vl); return __riscv_vfmsub_mu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmsub_vf_f32m1_mu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmsub_vf_f32m1_mu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmsub.mask.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmsub.mask.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfmsub_vf_f32m1_mu(vbool32_t mask, vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) { vfloat32m1_t test_vfmsub_vf_f32m1_mu(vbool32_t mask, vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfmsub_mu(mask, vd, rs1, vs2, vl); return __riscv_vfmsub_mu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmsub_vv_f32m2_mu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmsub_vv_f32m2_mu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmsub.mask.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmsub.mask.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfmsub_vv_f32m2_mu(vbool16_t mask, vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) { vfloat32m2_t test_vfmsub_vv_f32m2_mu(vbool16_t mask, vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfmsub_mu(mask, vd, vs1, vs2, vl); return __riscv_vfmsub_mu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmsub_vf_f32m2_mu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmsub_vf_f32m2_mu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmsub.mask.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmsub.mask.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfmsub_vf_f32m2_mu(vbool16_t mask, vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) { vfloat32m2_t test_vfmsub_vf_f32m2_mu(vbool16_t mask, vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfmsub_mu(mask, vd, rs1, vs2, vl); return __riscv_vfmsub_mu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmsub_vv_f32m4_mu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmsub_vv_f32m4_mu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmsub.mask.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmsub.mask.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfmsub_vv_f32m4_mu(vbool8_t mask, vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) { vfloat32m4_t test_vfmsub_vv_f32m4_mu(vbool8_t mask, vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfmsub_mu(mask, vd, vs1, vs2, vl); return __riscv_vfmsub_mu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmsub_vf_f32m4_mu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmsub_vf_f32m4_mu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmsub.mask.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmsub.mask.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfmsub_vf_f32m4_mu(vbool8_t mask, vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) { vfloat32m4_t test_vfmsub_vf_f32m4_mu(vbool8_t mask, vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfmsub_mu(mask, vd, rs1, vs2, vl); return __riscv_vfmsub_mu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmsub_vv_f32m8_mu // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmsub_vv_f32m8_mu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmsub.mask.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmsub.mask.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfmsub_vv_f32m8_mu(vbool4_t mask, vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) { vfloat32m8_t test_vfmsub_vv_f32m8_mu(vbool4_t mask, vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfmsub_mu(mask, vd, vs1, vs2, vl); return __riscv_vfmsub_mu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmsub_vf_f32m8_mu // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmsub_vf_f32m8_mu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmsub.mask.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmsub.mask.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfmsub_vf_f32m8_mu(vbool4_t mask, vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) { vfloat32m8_t test_vfmsub_vf_f32m8_mu(vbool4_t mask, vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfmsub_mu(mask, vd, rs1, vs2, vl); return __riscv_vfmsub_mu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmsub_vv_f64m1_mu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmsub_vv_f64m1_mu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmsub.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmsub.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfmsub_vv_f64m1_mu(vbool64_t mask, vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) { vfloat64m1_t test_vfmsub_vv_f64m1_mu(vbool64_t mask, vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfmsub_mu(mask, vd, vs1, vs2, vl); return __riscv_vfmsub_mu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmsub_vf_f64m1_mu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmsub_vf_f64m1_mu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmsub.mask.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmsub.mask.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfmsub_vf_f64m1_mu(vbool64_t mask, vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) { vfloat64m1_t test_vfmsub_vf_f64m1_mu(vbool64_t mask, vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfmsub_mu(mask, vd, rs1, vs2, vl); return __riscv_vfmsub_mu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmsub_vv_f64m2_mu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmsub_vv_f64m2_mu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmsub.mask.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmsub.mask.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfmsub_vv_f64m2_mu(vbool32_t mask, vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) { vfloat64m2_t test_vfmsub_vv_f64m2_mu(vbool32_t mask, vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfmsub_mu(mask, vd, vs1, vs2, vl); return __riscv_vfmsub_mu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmsub_vf_f64m2_mu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmsub_vf_f64m2_mu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmsub.mask.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmsub.mask.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfmsub_vf_f64m2_mu(vbool32_t mask, vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) { vfloat64m2_t test_vfmsub_vf_f64m2_mu(vbool32_t mask, vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfmsub_mu(mask, vd, rs1, vs2, vl); return __riscv_vfmsub_mu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmsub_vv_f64m4_mu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmsub_vv_f64m4_mu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmsub.mask.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmsub.mask.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfmsub_vv_f64m4_mu(vbool16_t mask, vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) { vfloat64m4_t test_vfmsub_vv_f64m4_mu(vbool16_t mask, vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfmsub_mu(mask, vd, vs1, vs2, vl); return __riscv_vfmsub_mu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmsub_vf_f64m4_mu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmsub_vf_f64m4_mu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmsub.mask.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmsub.mask.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfmsub_vf_f64m4_mu(vbool16_t mask, vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) { vfloat64m4_t test_vfmsub_vf_f64m4_mu(vbool16_t mask, vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfmsub_mu(mask, vd, rs1, vs2, vl); return __riscv_vfmsub_mu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmsub_vv_f64m8_mu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmsub_vv_f64m8_mu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmsub.mask.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmsub.mask.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfmsub_vv_f64m8_mu(vbool8_t mask, vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) { vfloat64m8_t test_vfmsub_vv_f64m8_mu(vbool8_t mask, vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfmsub_mu(mask, vd, vs1, vs2, vl); return __riscv_vfmsub_mu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmsub_vf_f64m8_mu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmsub_vf_f64m8_mu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmsub.mask.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmsub.mask.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfmsub_vf_f64m8_mu(vbool8_t mask, vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) { vfloat64m8_t test_vfmsub_vf_f64m8_mu(vbool8_t mask, vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfmsub_mu(mask, vd, rs1, vs2, vl); return __riscv_vfmsub_mu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmsub_vv_f16mf4_rm_tu
// CHECK-RV64-SAME: (<vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmsub.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
//
vfloat16mf4_t test_vfmsub_vv_f16mf4_rm_tu(vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfmsub_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmsub_vf_f16mf4_rm_tu
// CHECK-RV64-SAME: (<vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmsub.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
//
vfloat16mf4_t test_vfmsub_vf_f16mf4_rm_tu(vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfmsub_tu(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmsub_vv_f16mf2_rm_tu
// CHECK-RV64-SAME: (<vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmsub.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
//
vfloat16mf2_t test_vfmsub_vv_f16mf2_rm_tu(vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfmsub_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmsub_vf_f16mf2_rm_tu
// CHECK-RV64-SAME: (<vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmsub.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
//
vfloat16mf2_t test_vfmsub_vf_f16mf2_rm_tu(vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfmsub_tu(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmsub_vv_f16m1_rm_tu
// CHECK-RV64-SAME: (<vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmsub.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfmsub_vv_f16m1_rm_tu(vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfmsub_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmsub_vf_f16m1_rm_tu
// CHECK-RV64-SAME: (<vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmsub.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfmsub_vf_f16m1_rm_tu(vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfmsub_tu(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmsub_vv_f16m2_rm_tu
// CHECK-RV64-SAME: (<vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmsub.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
//
vfloat16m2_t test_vfmsub_vv_f16m2_rm_tu(vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfmsub_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmsub_vf_f16m2_rm_tu
// CHECK-RV64-SAME: (<vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmsub.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
//
vfloat16m2_t test_vfmsub_vf_f16m2_rm_tu(vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfmsub_tu(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmsub_vv_f16m4_rm_tu
// CHECK-RV64-SAME: (<vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmsub.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
//
vfloat16m4_t test_vfmsub_vv_f16m4_rm_tu(vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfmsub_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmsub_vf_f16m4_rm_tu
// CHECK-RV64-SAME: (<vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmsub.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
//
vfloat16m4_t test_vfmsub_vf_f16m4_rm_tu(vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfmsub_tu(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmsub_vv_f16m8_rm_tu
// CHECK-RV64-SAME: (<vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmsub.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
//
vfloat16m8_t test_vfmsub_vv_f16m8_rm_tu(vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfmsub_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmsub_vf_f16m8_rm_tu
// CHECK-RV64-SAME: (<vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmsub.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
//
vfloat16m8_t test_vfmsub_vf_f16m8_rm_tu(vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfmsub_tu(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmsub_vv_f32mf2_rm_tu
// CHECK-RV64-SAME: (<vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmsub.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
//
vfloat32mf2_t test_vfmsub_vv_f32mf2_rm_tu(vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfmsub_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmsub_vf_f32mf2_rm_tu
// CHECK-RV64-SAME: (<vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmsub.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
//
vfloat32mf2_t test_vfmsub_vf_f32mf2_rm_tu(vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfmsub_tu(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmsub_vv_f32m1_rm_tu
// CHECK-RV64-SAME: (<vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmsub.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfmsub_vv_f32m1_rm_tu(vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfmsub_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmsub_vf_f32m1_rm_tu
// CHECK-RV64-SAME: (<vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmsub.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfmsub_vf_f32m1_rm_tu(vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfmsub_tu(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmsub_vv_f32m2_rm_tu
// CHECK-RV64-SAME: (<vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmsub.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
//
vfloat32m2_t test_vfmsub_vv_f32m2_rm_tu(vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfmsub_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmsub_vf_f32m2_rm_tu
// CHECK-RV64-SAME: (<vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmsub.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
//
vfloat32m2_t test_vfmsub_vf_f32m2_rm_tu(vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfmsub_tu(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmsub_vv_f32m4_rm_tu
// CHECK-RV64-SAME: (<vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmsub.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
//
vfloat32m4_t test_vfmsub_vv_f32m4_rm_tu(vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfmsub_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmsub_vf_f32m4_rm_tu
// CHECK-RV64-SAME: (<vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmsub.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
//
vfloat32m4_t test_vfmsub_vf_f32m4_rm_tu(vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfmsub_tu(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmsub_vv_f32m8_rm_tu
// CHECK-RV64-SAME: (<vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmsub.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
//
vfloat32m8_t test_vfmsub_vv_f32m8_rm_tu(vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfmsub_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmsub_vf_f32m8_rm_tu
// CHECK-RV64-SAME: (<vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmsub.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
//
vfloat32m8_t test_vfmsub_vf_f32m8_rm_tu(vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfmsub_tu(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmsub_vv_f64m1_rm_tu
// CHECK-RV64-SAME: (<vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmsub.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfmsub_vv_f64m1_rm_tu(vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfmsub_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmsub_vf_f64m1_rm_tu
// CHECK-RV64-SAME: (<vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmsub.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfmsub_vf_f64m1_rm_tu(vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfmsub_tu(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmsub_vv_f64m2_rm_tu
// CHECK-RV64-SAME: (<vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmsub.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
//
vfloat64m2_t test_vfmsub_vv_f64m2_rm_tu(vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfmsub_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmsub_vf_f64m2_rm_tu
// CHECK-RV64-SAME: (<vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmsub.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
//
vfloat64m2_t test_vfmsub_vf_f64m2_rm_tu(vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfmsub_tu(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmsub_vv_f64m4_rm_tu
// CHECK-RV64-SAME: (<vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmsub.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
//
vfloat64m4_t test_vfmsub_vv_f64m4_rm_tu(vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfmsub_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmsub_vf_f64m4_rm_tu
// CHECK-RV64-SAME: (<vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmsub.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
//
vfloat64m4_t test_vfmsub_vf_f64m4_rm_tu(vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfmsub_tu(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmsub_vv_f64m8_rm_tu
// CHECK-RV64-SAME: (<vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmsub.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
//
vfloat64m8_t test_vfmsub_vv_f64m8_rm_tu(vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfmsub_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmsub_vf_f64m8_rm_tu
// CHECK-RV64-SAME: (<vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmsub.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
//
vfloat64m8_t test_vfmsub_vf_f64m8_rm_tu(vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfmsub_tu(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmsub_vv_f16mf4_rm_tum
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmsub.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
//
vfloat16mf4_t test_vfmsub_vv_f16mf4_rm_tum(vbool64_t mask, vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfmsub_tum(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmsub_vf_f16mf4_rm_tum
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmsub.mask.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
//
vfloat16mf4_t test_vfmsub_vf_f16mf4_rm_tum(vbool64_t mask, vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfmsub_tum(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmsub_vv_f16mf2_rm_tum
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmsub.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
//
vfloat16mf2_t test_vfmsub_vv_f16mf2_rm_tum(vbool32_t mask, vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfmsub_tum(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmsub_vf_f16mf2_rm_tum
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmsub.mask.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
//
vfloat16mf2_t test_vfmsub_vf_f16mf2_rm_tum(vbool32_t mask, vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfmsub_tum(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmsub_vv_f16m1_rm_tum
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmsub.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfmsub_vv_f16m1_rm_tum(vbool16_t mask, vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfmsub_tum(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmsub_vf_f16m1_rm_tum
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmsub.mask.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfmsub_vf_f16m1_rm_tum(vbool16_t mask, vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfmsub_tum(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmsub_vv_f16m2_rm_tum
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmsub.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
//
vfloat16m2_t test_vfmsub_vv_f16m2_rm_tum(vbool8_t mask, vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfmsub_tum(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmsub_vf_f16m2_rm_tum
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmsub.mask.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
//
vfloat16m2_t test_vfmsub_vf_f16m2_rm_tum(vbool8_t mask, vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfmsub_tum(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmsub_vv_f16m4_rm_tum
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmsub.mask.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
//
vfloat16m4_t test_vfmsub_vv_f16m4_rm_tum(vbool4_t mask, vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfmsub_tum(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmsub_vf_f16m4_rm_tum
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmsub.mask.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
//
vfloat16m4_t test_vfmsub_vf_f16m4_rm_tum(vbool4_t mask, vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfmsub_tum(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmsub_vv_f16m8_rm_tum
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmsub.mask.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
//
vfloat16m8_t test_vfmsub_vv_f16m8_rm_tum(vbool2_t mask, vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfmsub_tum(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmsub_vf_f16m8_rm_tum
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmsub.mask.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
//
vfloat16m8_t test_vfmsub_vf_f16m8_rm_tum(vbool2_t mask, vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfmsub_tum(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmsub_vv_f32mf2_rm_tum
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmsub.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
//
vfloat32mf2_t test_vfmsub_vv_f32mf2_rm_tum(vbool64_t mask, vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfmsub_tum(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmsub_vf_f32mf2_rm_tum
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmsub.mask.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
//
vfloat32mf2_t test_vfmsub_vf_f32mf2_rm_tum(vbool64_t mask, vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfmsub_tum(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmsub_vv_f32m1_rm_tum
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmsub.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfmsub_vv_f32m1_rm_tum(vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfmsub_tum(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmsub_vf_f32m1_rm_tum
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmsub.mask.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfmsub_vf_f32m1_rm_tum(vbool32_t mask, vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfmsub_tum(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmsub_vv_f32m2_rm_tum
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmsub.mask.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
//
vfloat32m2_t test_vfmsub_vv_f32m2_rm_tum(vbool16_t mask, vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfmsub_tum(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmsub_vf_f32m2_rm_tum
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmsub.mask.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
//
vfloat32m2_t test_vfmsub_vf_f32m2_rm_tum(vbool16_t mask, vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfmsub_tum(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmsub_vv_f32m4_rm_tum
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmsub.mask.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
//
vfloat32m4_t test_vfmsub_vv_f32m4_rm_tum(vbool8_t mask, vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfmsub_tum(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmsub_vf_f32m4_rm_tum
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmsub.mask.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
//
vfloat32m4_t test_vfmsub_vf_f32m4_rm_tum(vbool8_t mask, vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfmsub_tum(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmsub_vv_f32m8_rm_tum
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmsub.mask.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
//
vfloat32m8_t test_vfmsub_vv_f32m8_rm_tum(vbool4_t mask, vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfmsub_tum(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmsub_vf_f32m8_rm_tum
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmsub.mask.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
//
vfloat32m8_t test_vfmsub_vf_f32m8_rm_tum(vbool4_t mask, vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfmsub_tum(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmsub_vv_f64m1_rm_tum
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmsub.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfmsub_vv_f64m1_rm_tum(vbool64_t mask, vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfmsub_tum(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmsub_vf_f64m1_rm_tum
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmsub.mask.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfmsub_vf_f64m1_rm_tum(vbool64_t mask, vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfmsub_tum(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmsub_vv_f64m2_rm_tum
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmsub.mask.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
//
vfloat64m2_t test_vfmsub_vv_f64m2_rm_tum(vbool32_t mask, vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfmsub_tum(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmsub_vf_f64m2_rm_tum
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmsub.mask.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
//
vfloat64m2_t test_vfmsub_vf_f64m2_rm_tum(vbool32_t mask, vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfmsub_tum(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmsub_vv_f64m4_rm_tum
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmsub.mask.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
//
vfloat64m4_t test_vfmsub_vv_f64m4_rm_tum(vbool16_t mask, vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfmsub_tum(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmsub_vf_f64m4_rm_tum
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmsub.mask.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
//
vfloat64m4_t test_vfmsub_vf_f64m4_rm_tum(vbool16_t mask, vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfmsub_tum(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmsub_vv_f64m8_rm_tum
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmsub.mask.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
//
vfloat64m8_t test_vfmsub_vv_f64m8_rm_tum(vbool8_t mask, vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfmsub_tum(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmsub_vf_f64m8_rm_tum
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmsub.mask.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
//
vfloat64m8_t test_vfmsub_vf_f64m8_rm_tum(vbool8_t mask, vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfmsub_tum(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmsub_vv_f16mf4_rm_tumu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmsub.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
//
vfloat16mf4_t test_vfmsub_vv_f16mf4_rm_tumu(vbool64_t mask, vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfmsub_tumu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmsub_vf_f16mf4_rm_tumu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmsub.mask.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
//
vfloat16mf4_t test_vfmsub_vf_f16mf4_rm_tumu(vbool64_t mask, vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfmsub_tumu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmsub_vv_f16mf2_rm_tumu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmsub.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
//
vfloat16mf2_t test_vfmsub_vv_f16mf2_rm_tumu(vbool32_t mask, vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfmsub_tumu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmsub_vf_f16mf2_rm_tumu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmsub.mask.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
//
vfloat16mf2_t test_vfmsub_vf_f16mf2_rm_tumu(vbool32_t mask, vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfmsub_tumu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmsub_vv_f16m1_rm_tumu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmsub.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfmsub_vv_f16m1_rm_tumu(vbool16_t mask, vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfmsub_tumu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmsub_vf_f16m1_rm_tumu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmsub.mask.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfmsub_vf_f16m1_rm_tumu(vbool16_t mask, vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfmsub_tumu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmsub_vv_f16m2_rm_tumu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmsub.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
//
vfloat16m2_t test_vfmsub_vv_f16m2_rm_tumu(vbool8_t mask, vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfmsub_tumu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmsub_vf_f16m2_rm_tumu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmsub.mask.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
//
vfloat16m2_t test_vfmsub_vf_f16m2_rm_tumu(vbool8_t mask, vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfmsub_tumu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmsub_vv_f16m4_rm_tumu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmsub.mask.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
//
vfloat16m4_t test_vfmsub_vv_f16m4_rm_tumu(vbool4_t mask, vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfmsub_tumu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmsub_vf_f16m4_rm_tumu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmsub.mask.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
//
vfloat16m4_t test_vfmsub_vf_f16m4_rm_tumu(vbool4_t mask, vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfmsub_tumu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmsub_vv_f16m8_rm_tumu
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmsub.mask.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
//
vfloat16m8_t test_vfmsub_vv_f16m8_rm_tumu(vbool2_t mask, vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfmsub_tumu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmsub_vf_f16m8_rm_tumu
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmsub.mask.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
//
vfloat16m8_t test_vfmsub_vf_f16m8_rm_tumu(vbool2_t mask, vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfmsub_tumu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmsub_vv_f32mf2_rm_tumu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmsub.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
//
vfloat32mf2_t test_vfmsub_vv_f32mf2_rm_tumu(vbool64_t mask, vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfmsub_tumu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmsub_vf_f32mf2_rm_tumu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmsub.mask.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
//
vfloat32mf2_t test_vfmsub_vf_f32mf2_rm_tumu(vbool64_t mask, vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfmsub_tumu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmsub_vv_f32m1_rm_tumu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmsub.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfmsub_vv_f32m1_rm_tumu(vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfmsub_tumu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmsub_vf_f32m1_rm_tumu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmsub.mask.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfmsub_vf_f32m1_rm_tumu(vbool32_t mask, vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfmsub_tumu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmsub_vv_f32m2_rm_tumu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmsub.mask.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
//
vfloat32m2_t test_vfmsub_vv_f32m2_rm_tumu(vbool16_t mask, vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfmsub_tumu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmsub_vf_f32m2_rm_tumu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmsub.mask.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
//
vfloat32m2_t test_vfmsub_vf_f32m2_rm_tumu(vbool16_t mask, vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfmsub_tumu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmsub_vv_f32m4_rm_tumu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmsub.mask.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
//
vfloat32m4_t test_vfmsub_vv_f32m4_rm_tumu(vbool8_t mask, vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfmsub_tumu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmsub_vf_f32m4_rm_tumu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmsub.mask.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
//
vfloat32m4_t test_vfmsub_vf_f32m4_rm_tumu(vbool8_t mask, vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfmsub_tumu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmsub_vv_f32m8_rm_tumu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmsub.mask.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
//
vfloat32m8_t test_vfmsub_vv_f32m8_rm_tumu(vbool4_t mask, vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfmsub_tumu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmsub_vf_f32m8_rm_tumu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmsub.mask.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
//
vfloat32m8_t test_vfmsub_vf_f32m8_rm_tumu(vbool4_t mask, vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfmsub_tumu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmsub_vv_f64m1_rm_tumu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmsub.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfmsub_vv_f64m1_rm_tumu(vbool64_t mask, vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfmsub_tumu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmsub_vf_f64m1_rm_tumu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmsub.mask.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfmsub_vf_f64m1_rm_tumu(vbool64_t mask, vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfmsub_tumu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmsub_vv_f64m2_rm_tumu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmsub.mask.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
//
vfloat64m2_t test_vfmsub_vv_f64m2_rm_tumu(vbool32_t mask, vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfmsub_tumu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmsub_vf_f64m2_rm_tumu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmsub.mask.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
//
vfloat64m2_t test_vfmsub_vf_f64m2_rm_tumu(vbool32_t mask, vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfmsub_tumu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmsub_vv_f64m4_rm_tumu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmsub.mask.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
//
vfloat64m4_t test_vfmsub_vv_f64m4_rm_tumu(vbool16_t mask, vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfmsub_tumu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmsub_vf_f64m4_rm_tumu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmsub.mask.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
//
vfloat64m4_t test_vfmsub_vf_f64m4_rm_tumu(vbool16_t mask, vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfmsub_tumu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmsub_vv_f64m8_rm_tumu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmsub.mask.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
//
vfloat64m8_t test_vfmsub_vv_f64m8_rm_tumu(vbool8_t mask, vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfmsub_tumu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmsub_vf_f64m8_rm_tumu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmsub.mask.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
//
vfloat64m8_t test_vfmsub_vf_f64m8_rm_tumu(vbool8_t mask, vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfmsub_tumu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmsub_vv_f16mf4_rm_mu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmsub.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
//
vfloat16mf4_t test_vfmsub_vv_f16mf4_rm_mu(vbool64_t mask, vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfmsub_mu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfmsub_vf_f16mf4_rm_mu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfmsub.mask.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
//
vfloat16mf4_t test_vfmsub_vf_f16mf4_rm_mu(vbool64_t mask, vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfmsub_mu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmsub_vv_f16mf2_rm_mu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmsub.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
//
vfloat16mf2_t test_vfmsub_vv_f16mf2_rm_mu(vbool32_t mask, vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfmsub_mu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfmsub_vf_f16mf2_rm_mu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfmsub.mask.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
//
vfloat16mf2_t test_vfmsub_vf_f16mf2_rm_mu(vbool32_t mask, vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfmsub_mu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmsub_vv_f16m1_rm_mu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmsub.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfmsub_vv_f16m1_rm_mu(vbool16_t mask, vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfmsub_mu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfmsub_vf_f16m1_rm_mu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfmsub.mask.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfmsub_vf_f16m1_rm_mu(vbool16_t mask, vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfmsub_mu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmsub_vv_f16m2_rm_mu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmsub.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
//
vfloat16m2_t test_vfmsub_vv_f16m2_rm_mu(vbool8_t mask, vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfmsub_mu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfmsub_vf_f16m2_rm_mu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfmsub.mask.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
//
vfloat16m2_t test_vfmsub_vf_f16m2_rm_mu(vbool8_t mask, vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfmsub_mu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmsub_vv_f16m4_rm_mu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmsub.mask.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
//
vfloat16m4_t test_vfmsub_vv_f16m4_rm_mu(vbool4_t mask, vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfmsub_mu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfmsub_vf_f16m4_rm_mu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfmsub.mask.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
//
vfloat16m4_t test_vfmsub_vf_f16m4_rm_mu(vbool4_t mask, vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfmsub_mu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmsub_vv_f16m8_rm_mu
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmsub.mask.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
//
vfloat16m8_t test_vfmsub_vv_f16m8_rm_mu(vbool2_t mask, vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfmsub_mu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfmsub_vf_f16m8_rm_mu
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfmsub.mask.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
//
vfloat16m8_t test_vfmsub_vf_f16m8_rm_mu(vbool2_t mask, vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfmsub_mu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmsub_vv_f32mf2_rm_mu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmsub.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
//
vfloat32mf2_t test_vfmsub_vv_f32mf2_rm_mu(vbool64_t mask, vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfmsub_mu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfmsub_vf_f32mf2_rm_mu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfmsub.mask.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
//
vfloat32mf2_t test_vfmsub_vf_f32mf2_rm_mu(vbool64_t mask, vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfmsub_mu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmsub_vv_f32m1_rm_mu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmsub.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfmsub_vv_f32m1_rm_mu(vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfmsub_mu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfmsub_vf_f32m1_rm_mu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfmsub.mask.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfmsub_vf_f32m1_rm_mu(vbool32_t mask, vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfmsub_mu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmsub_vv_f32m2_rm_mu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmsub.mask.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
//
vfloat32m2_t test_vfmsub_vv_f32m2_rm_mu(vbool16_t mask, vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfmsub_mu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfmsub_vf_f32m2_rm_mu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfmsub.mask.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
//
vfloat32m2_t test_vfmsub_vf_f32m2_rm_mu(vbool16_t mask, vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfmsub_mu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmsub_vv_f32m4_rm_mu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmsub.mask.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
//
vfloat32m4_t test_vfmsub_vv_f32m4_rm_mu(vbool8_t mask, vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfmsub_mu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfmsub_vf_f32m4_rm_mu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfmsub.mask.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
//
vfloat32m4_t test_vfmsub_vf_f32m4_rm_mu(vbool8_t mask, vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfmsub_mu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmsub_vv_f32m8_rm_mu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmsub.mask.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
//
vfloat32m8_t test_vfmsub_vv_f32m8_rm_mu(vbool4_t mask, vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfmsub_mu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfmsub_vf_f32m8_rm_mu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfmsub.mask.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
//
vfloat32m8_t test_vfmsub_vf_f32m8_rm_mu(vbool4_t mask, vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfmsub_mu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmsub_vv_f64m1_rm_mu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmsub.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfmsub_vv_f64m1_rm_mu(vbool64_t mask, vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfmsub_mu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfmsub_vf_f64m1_rm_mu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfmsub.mask.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfmsub_vf_f64m1_rm_mu(vbool64_t mask, vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfmsub_mu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmsub_vv_f64m2_rm_mu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmsub.mask.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
//
vfloat64m2_t test_vfmsub_vv_f64m2_rm_mu(vbool32_t mask, vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfmsub_mu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfmsub_vf_f64m2_rm_mu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfmsub.mask.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
//
vfloat64m2_t test_vfmsub_vf_f64m2_rm_mu(vbool32_t mask, vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfmsub_mu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmsub_vv_f64m4_rm_mu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmsub.mask.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
//
vfloat64m4_t test_vfmsub_vv_f64m4_rm_mu(vbool16_t mask, vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfmsub_mu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfmsub_vf_f64m4_rm_mu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfmsub.mask.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
//
vfloat64m4_t test_vfmsub_vf_f64m4_rm_mu(vbool16_t mask, vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfmsub_mu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmsub_vv_f64m8_rm_mu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmsub.mask.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
//
vfloat64m8_t test_vfmsub_vv_f64m8_rm_mu(vbool8_t mask, vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfmsub_mu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfmsub_vf_f64m8_rm_mu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfmsub.mask.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
//
vfloat64m8_t test_vfmsub_vf_f64m8_rm_mu(vbool8_t mask, vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfmsub_mu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}

clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmacc.c

// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target // REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh \ // RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh \
// RUN: -target-feature +experimental-zvfh -disable-O0-optnone \ // RUN: -target-feature +experimental-zvfh -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ // RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s // RUN: FileCheck --check-prefix=CHECK-RV64 %s
#include <riscv_vector.h> #include <riscv_vector.h>
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmacc_vv_f16mf4_tu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmacc_vv_f16mf4_tu
// CHECK-RV64-SAME: (<vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK-RV64-SAME: (<vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmacc.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmacc.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
// //
vfloat16mf4_t test_vfnmacc_vv_f16mf4_tu(vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) { vfloat16mf4_t test_vfnmacc_vv_f16mf4_tu(vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfnmacc_tu(vd, vs1, vs2, vl); return __riscv_vfnmacc_tu(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmacc_vf_f16mf4_tu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmacc_vf_f16mf4_tu
// CHECK-RV64-SAME: (<vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmacc.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmacc.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
// //
vfloat16mf4_t test_vfnmacc_vf_f16mf4_tu(vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) { vfloat16mf4_t test_vfnmacc_vf_f16mf4_tu(vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfnmacc_tu(vd, rs1, vs2, vl); return __riscv_vfnmacc_tu(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmacc_vv_f16mf2_tu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmacc_vv_f16mf2_tu
// CHECK-RV64-SAME: (<vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmacc.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmacc.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
// //
vfloat16mf2_t test_vfnmacc_vv_f16mf2_tu(vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) { vfloat16mf2_t test_vfnmacc_vv_f16mf2_tu(vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfnmacc_tu(vd, vs1, vs2, vl); return __riscv_vfnmacc_tu(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmacc_vf_f16mf2_tu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmacc_vf_f16mf2_tu
// CHECK-RV64-SAME: (<vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmacc.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmacc.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
// //
vfloat16mf2_t test_vfnmacc_vf_f16mf2_tu(vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) { vfloat16mf2_t test_vfnmacc_vf_f16mf2_tu(vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfnmacc_tu(vd, rs1, vs2, vl); return __riscv_vfnmacc_tu(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmacc_vv_f16m1_tu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmacc_vv_f16m1_tu
// CHECK-RV64-SAME: (<vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmacc.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmacc.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
// //
vfloat16m1_t test_vfnmacc_vv_f16m1_tu(vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) { vfloat16m1_t test_vfnmacc_vv_f16m1_tu(vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfnmacc_tu(vd, vs1, vs2, vl); return __riscv_vfnmacc_tu(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmacc_vf_f16m1_tu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmacc_vf_f16m1_tu
// CHECK-RV64-SAME: (<vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmacc.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmacc.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
// //
vfloat16m1_t test_vfnmacc_vf_f16m1_tu(vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) { vfloat16m1_t test_vfnmacc_vf_f16m1_tu(vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfnmacc_tu(vd, rs1, vs2, vl); return __riscv_vfnmacc_tu(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmacc_vv_f16m2_tu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmacc_vv_f16m2_tu
// CHECK-RV64-SAME: (<vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmacc.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmacc.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
// //
vfloat16m2_t test_vfnmacc_vv_f16m2_tu(vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) { vfloat16m2_t test_vfnmacc_vv_f16m2_tu(vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfnmacc_tu(vd, vs1, vs2, vl); return __riscv_vfnmacc_tu(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmacc_vf_f16m2_tu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmacc_vf_f16m2_tu
// CHECK-RV64-SAME: (<vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmacc.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmacc.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
// //
vfloat16m2_t test_vfnmacc_vf_f16m2_tu(vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) { vfloat16m2_t test_vfnmacc_vf_f16m2_tu(vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfnmacc_tu(vd, rs1, vs2, vl); return __riscv_vfnmacc_tu(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmacc_vv_f16m4_tu // CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmacc_vv_f16m4_tu
// CHECK-RV64-SAME: (<vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmacc.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmacc.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
// //
vfloat16m4_t test_vfnmacc_vv_f16m4_tu(vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) { vfloat16m4_t test_vfnmacc_vv_f16m4_tu(vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfnmacc_tu(vd, vs1, vs2, vl); return __riscv_vfnmacc_tu(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmacc_vf_f16m4_tu // CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmacc_vf_f16m4_tu
// CHECK-RV64-SAME: (<vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmacc.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmacc.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
// //
vfloat16m4_t test_vfnmacc_vf_f16m4_tu(vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) { vfloat16m4_t test_vfnmacc_vf_f16m4_tu(vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfnmacc_tu(vd, rs1, vs2, vl); return __riscv_vfnmacc_tu(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmacc_vv_f16m8_tu // CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmacc_vv_f16m8_tu
// CHECK-RV64-SAME: (<vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmacc.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmacc.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
// //
vfloat16m8_t test_vfnmacc_vv_f16m8_tu(vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) { vfloat16m8_t test_vfnmacc_vv_f16m8_tu(vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfnmacc_tu(vd, vs1, vs2, vl); return __riscv_vfnmacc_tu(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmacc_vf_f16m8_tu // CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmacc_vf_f16m8_tu
// CHECK-RV64-SAME: (<vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmacc.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmacc.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
// //
vfloat16m8_t test_vfnmacc_vf_f16m8_tu(vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) { vfloat16m8_t test_vfnmacc_vf_f16m8_tu(vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfnmacc_tu(vd, rs1, vs2, vl); return __riscv_vfnmacc_tu(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmacc_vv_f32mf2_tu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmacc_vv_f32mf2_tu
// CHECK-RV64-SAME: (<vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmacc.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmacc.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfnmacc_vv_f32mf2_tu(vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) { vfloat32mf2_t test_vfnmacc_vv_f32mf2_tu(vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfnmacc_tu(vd, vs1, vs2, vl); return __riscv_vfnmacc_tu(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmacc_vf_f32mf2_tu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmacc_vf_f32mf2_tu
// CHECK-RV64-SAME: (<vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmacc.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmacc.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfnmacc_vf_f32mf2_tu(vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) { vfloat32mf2_t test_vfnmacc_vf_f32mf2_tu(vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfnmacc_tu(vd, rs1, vs2, vl); return __riscv_vfnmacc_tu(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmacc_vv_f32m1_tu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmacc_vv_f32m1_tu
// CHECK-RV64-SAME: (<vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmacc.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmacc.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfnmacc_vv_f32m1_tu(vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) { vfloat32m1_t test_vfnmacc_vv_f32m1_tu(vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfnmacc_tu(vd, vs1, vs2, vl); return __riscv_vfnmacc_tu(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmacc_vf_f32m1_tu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmacc_vf_f32m1_tu
// CHECK-RV64-SAME: (<vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmacc.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmacc.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfnmacc_vf_f32m1_tu(vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) { vfloat32m1_t test_vfnmacc_vf_f32m1_tu(vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfnmacc_tu(vd, rs1, vs2, vl); return __riscv_vfnmacc_tu(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmacc_vv_f32m2_tu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmacc_vv_f32m2_tu
// CHECK-RV64-SAME: (<vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmacc.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmacc.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfnmacc_vv_f32m2_tu(vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) { vfloat32m2_t test_vfnmacc_vv_f32m2_tu(vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfnmacc_tu(vd, vs1, vs2, vl); return __riscv_vfnmacc_tu(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmacc_vf_f32m2_tu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmacc_vf_f32m2_tu
// CHECK-RV64-SAME: (<vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmacc.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmacc.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfnmacc_vf_f32m2_tu(vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) { vfloat32m2_t test_vfnmacc_vf_f32m2_tu(vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfnmacc_tu(vd, rs1, vs2, vl); return __riscv_vfnmacc_tu(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmacc_vv_f32m4_tu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmacc_vv_f32m4_tu
// CHECK-RV64-SAME: (<vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmacc.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmacc.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfnmacc_vv_f32m4_tu(vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) { vfloat32m4_t test_vfnmacc_vv_f32m4_tu(vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfnmacc_tu(vd, vs1, vs2, vl); return __riscv_vfnmacc_tu(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmacc_vf_f32m4_tu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmacc_vf_f32m4_tu
// CHECK-RV64-SAME: (<vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmacc.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmacc.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfnmacc_vf_f32m4_tu(vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) { vfloat32m4_t test_vfnmacc_vf_f32m4_tu(vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfnmacc_tu(vd, rs1, vs2, vl); return __riscv_vfnmacc_tu(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmacc_vv_f32m8_tu // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmacc_vv_f32m8_tu
// CHECK-RV64-SAME: (<vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmacc.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmacc.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfnmacc_vv_f32m8_tu(vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) { vfloat32m8_t test_vfnmacc_vv_f32m8_tu(vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfnmacc_tu(vd, vs1, vs2, vl); return __riscv_vfnmacc_tu(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmacc_vf_f32m8_tu // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmacc_vf_f32m8_tu
// CHECK-RV64-SAME: (<vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmacc.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmacc.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfnmacc_vf_f32m8_tu(vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) { vfloat32m8_t test_vfnmacc_vf_f32m8_tu(vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfnmacc_tu(vd, rs1, vs2, vl); return __riscv_vfnmacc_tu(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmacc_vv_f64m1_tu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmacc_vv_f64m1_tu
// CHECK-RV64-SAME: (<vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmacc.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmacc.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfnmacc_vv_f64m1_tu(vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) { vfloat64m1_t test_vfnmacc_vv_f64m1_tu(vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfnmacc_tu(vd, vs1, vs2, vl); return __riscv_vfnmacc_tu(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmacc_vf_f64m1_tu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmacc_vf_f64m1_tu
// CHECK-RV64-SAME: (<vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmacc.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmacc.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfnmacc_vf_f64m1_tu(vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) { vfloat64m1_t test_vfnmacc_vf_f64m1_tu(vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfnmacc_tu(vd, rs1, vs2, vl); return __riscv_vfnmacc_tu(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmacc_vv_f64m2_tu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmacc_vv_f64m2_tu
// CHECK-RV64-SAME: (<vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmacc.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmacc.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfnmacc_vv_f64m2_tu(vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) { vfloat64m2_t test_vfnmacc_vv_f64m2_tu(vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfnmacc_tu(vd, vs1, vs2, vl); return __riscv_vfnmacc_tu(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmacc_vf_f64m2_tu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmacc_vf_f64m2_tu
// CHECK-RV64-SAME: (<vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmacc.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmacc.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfnmacc_vf_f64m2_tu(vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) { vfloat64m2_t test_vfnmacc_vf_f64m2_tu(vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfnmacc_tu(vd, rs1, vs2, vl); return __riscv_vfnmacc_tu(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmacc_vv_f64m4_tu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmacc_vv_f64m4_tu
// CHECK-RV64-SAME: (<vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmacc.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmacc.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfnmacc_vv_f64m4_tu(vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) { vfloat64m4_t test_vfnmacc_vv_f64m4_tu(vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfnmacc_tu(vd, vs1, vs2, vl); return __riscv_vfnmacc_tu(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmacc_vf_f64m4_tu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmacc_vf_f64m4_tu
// CHECK-RV64-SAME: (<vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmacc.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmacc.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfnmacc_vf_f64m4_tu(vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) { vfloat64m4_t test_vfnmacc_vf_f64m4_tu(vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfnmacc_tu(vd, rs1, vs2, vl); return __riscv_vfnmacc_tu(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmacc_vv_f64m8_tu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmacc_vv_f64m8_tu
// CHECK-RV64-SAME: (<vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmacc.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmacc.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfnmacc_vv_f64m8_tu(vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) { vfloat64m8_t test_vfnmacc_vv_f64m8_tu(vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfnmacc_tu(vd, vs1, vs2, vl); return __riscv_vfnmacc_tu(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmacc_vf_f64m8_tu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmacc_vf_f64m8_tu
// CHECK-RV64-SAME: (<vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmacc.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmacc.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfnmacc_vf_f64m8_tu(vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) { vfloat64m8_t test_vfnmacc_vf_f64m8_tu(vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfnmacc_tu(vd, rs1, vs2, vl); return __riscv_vfnmacc_tu(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmacc_vv_f16mf4_tum // CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmacc_vv_f16mf4_tum
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmacc.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmacc.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
// //
vfloat16mf4_t test_vfnmacc_vv_f16mf4_tum(vbool64_t mask, vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) { vfloat16mf4_t test_vfnmacc_vv_f16mf4_tum(vbool64_t mask, vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfnmacc_tum(mask, vd, vs1, vs2, vl); return __riscv_vfnmacc_tum(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmacc_vf_f16mf4_tum // CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmacc_vf_f16mf4_tum
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmacc.mask.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmacc.mask.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
// //
vfloat16mf4_t test_vfnmacc_vf_f16mf4_tum(vbool64_t mask, vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) { vfloat16mf4_t test_vfnmacc_vf_f16mf4_tum(vbool64_t mask, vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfnmacc_tum(mask, vd, rs1, vs2, vl); return __riscv_vfnmacc_tum(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmacc_vv_f16mf2_tum // CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmacc_vv_f16mf2_tum
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmacc.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmacc.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
// //
vfloat16mf2_t test_vfnmacc_vv_f16mf2_tum(vbool32_t mask, vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) { vfloat16mf2_t test_vfnmacc_vv_f16mf2_tum(vbool32_t mask, vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfnmacc_tum(mask, vd, vs1, vs2, vl); return __riscv_vfnmacc_tum(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmacc_vf_f16mf2_tum // CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmacc_vf_f16mf2_tum
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmacc.mask.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmacc.mask.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
// //
vfloat16mf2_t test_vfnmacc_vf_f16mf2_tum(vbool32_t mask, vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) { vfloat16mf2_t test_vfnmacc_vf_f16mf2_tum(vbool32_t mask, vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfnmacc_tum(mask, vd, rs1, vs2, vl); return __riscv_vfnmacc_tum(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmacc_vv_f16m1_tum // CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmacc_vv_f16m1_tum
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmacc.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmacc.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
// //
vfloat16m1_t test_vfnmacc_vv_f16m1_tum(vbool16_t mask, vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) { vfloat16m1_t test_vfnmacc_vv_f16m1_tum(vbool16_t mask, vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfnmacc_tum(mask, vd, vs1, vs2, vl); return __riscv_vfnmacc_tum(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmacc_vf_f16m1_tum // CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmacc_vf_f16m1_tum
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmacc.mask.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmacc.mask.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
// //
vfloat16m1_t test_vfnmacc_vf_f16m1_tum(vbool16_t mask, vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) { vfloat16m1_t test_vfnmacc_vf_f16m1_tum(vbool16_t mask, vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfnmacc_tum(mask, vd, rs1, vs2, vl); return __riscv_vfnmacc_tum(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmacc_vv_f16m2_tum // CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmacc_vv_f16m2_tum
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmacc.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmacc.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
// //
vfloat16m2_t test_vfnmacc_vv_f16m2_tum(vbool8_t mask, vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) { vfloat16m2_t test_vfnmacc_vv_f16m2_tum(vbool8_t mask, vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfnmacc_tum(mask, vd, vs1, vs2, vl); return __riscv_vfnmacc_tum(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmacc_vf_f16m2_tum // CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmacc_vf_f16m2_tum
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmacc.mask.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmacc.mask.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
// //
vfloat16m2_t test_vfnmacc_vf_f16m2_tum(vbool8_t mask, vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) { vfloat16m2_t test_vfnmacc_vf_f16m2_tum(vbool8_t mask, vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfnmacc_tum(mask, vd, rs1, vs2, vl); return __riscv_vfnmacc_tum(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmacc_vv_f16m4_tum // CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmacc_vv_f16m4_tum
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmacc.mask.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmacc.mask.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
// //
vfloat16m4_t test_vfnmacc_vv_f16m4_tum(vbool4_t mask, vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) { vfloat16m4_t test_vfnmacc_vv_f16m4_tum(vbool4_t mask, vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfnmacc_tum(mask, vd, vs1, vs2, vl); return __riscv_vfnmacc_tum(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmacc_vf_f16m4_tum // CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmacc_vf_f16m4_tum
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmacc.mask.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmacc.mask.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
// //
vfloat16m4_t test_vfnmacc_vf_f16m4_tum(vbool4_t mask, vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) { vfloat16m4_t test_vfnmacc_vf_f16m4_tum(vbool4_t mask, vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfnmacc_tum(mask, vd, rs1, vs2, vl); return __riscv_vfnmacc_tum(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmacc_vv_f16m8_tum // CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmacc_vv_f16m8_tum
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmacc.mask.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmacc.mask.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
// //
vfloat16m8_t test_vfnmacc_vv_f16m8_tum(vbool2_t mask, vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) { vfloat16m8_t test_vfnmacc_vv_f16m8_tum(vbool2_t mask, vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfnmacc_tum(mask, vd, vs1, vs2, vl); return __riscv_vfnmacc_tum(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmacc_vf_f16m8_tum // CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmacc_vf_f16m8_tum
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmacc.mask.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmacc.mask.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
// //
vfloat16m8_t test_vfnmacc_vf_f16m8_tum(vbool2_t mask, vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) { vfloat16m8_t test_vfnmacc_vf_f16m8_tum(vbool2_t mask, vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfnmacc_tum(mask, vd, rs1, vs2, vl); return __riscv_vfnmacc_tum(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmacc_vv_f32mf2_tum // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmacc_vv_f32mf2_tum
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmacc.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmacc.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfnmacc_vv_f32mf2_tum(vbool64_t mask, vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) { vfloat32mf2_t test_vfnmacc_vv_f32mf2_tum(vbool64_t mask, vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfnmacc_tum(mask, vd, vs1, vs2, vl); return __riscv_vfnmacc_tum(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmacc_vf_f32mf2_tum // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmacc_vf_f32mf2_tum
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmacc.mask.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmacc.mask.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfnmacc_vf_f32mf2_tum(vbool64_t mask, vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) { vfloat32mf2_t test_vfnmacc_vf_f32mf2_tum(vbool64_t mask, vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfnmacc_tum(mask, vd, rs1, vs2, vl); return __riscv_vfnmacc_tum(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmacc_vv_f32m1_tum // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmacc_vv_f32m1_tum
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmacc.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmacc.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfnmacc_vv_f32m1_tum(vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) { vfloat32m1_t test_vfnmacc_vv_f32m1_tum(vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfnmacc_tum(mask, vd, vs1, vs2, vl); return __riscv_vfnmacc_tum(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmacc_vf_f32m1_tum // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmacc_vf_f32m1_tum
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmacc.mask.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmacc.mask.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfnmacc_vf_f32m1_tum(vbool32_t mask, vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) { vfloat32m1_t test_vfnmacc_vf_f32m1_tum(vbool32_t mask, vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfnmacc_tum(mask, vd, rs1, vs2, vl); return __riscv_vfnmacc_tum(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmacc_vv_f32m2_tum // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmacc_vv_f32m2_tum
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmacc.mask.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmacc.mask.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfnmacc_vv_f32m2_tum(vbool16_t mask, vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) { vfloat32m2_t test_vfnmacc_vv_f32m2_tum(vbool16_t mask, vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfnmacc_tum(mask, vd, vs1, vs2, vl); return __riscv_vfnmacc_tum(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmacc_vf_f32m2_tum // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmacc_vf_f32m2_tum
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmacc.mask.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmacc.mask.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfnmacc_vf_f32m2_tum(vbool16_t mask, vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) { vfloat32m2_t test_vfnmacc_vf_f32m2_tum(vbool16_t mask, vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfnmacc_tum(mask, vd, rs1, vs2, vl); return __riscv_vfnmacc_tum(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmacc_vv_f32m4_tum // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmacc_vv_f32m4_tum
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmacc.mask.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmacc.mask.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfnmacc_vv_f32m4_tum(vbool8_t mask, vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) { vfloat32m4_t test_vfnmacc_vv_f32m4_tum(vbool8_t mask, vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfnmacc_tum(mask, vd, vs1, vs2, vl); return __riscv_vfnmacc_tum(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmacc_vf_f32m4_tum // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmacc_vf_f32m4_tum
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmacc.mask.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmacc.mask.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfnmacc_vf_f32m4_tum(vbool8_t mask, vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) { vfloat32m4_t test_vfnmacc_vf_f32m4_tum(vbool8_t mask, vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfnmacc_tum(mask, vd, rs1, vs2, vl); return __riscv_vfnmacc_tum(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmacc_vv_f32m8_tum // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmacc_vv_f32m8_tum
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmacc.mask.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmacc.mask.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfnmacc_vv_f32m8_tum(vbool4_t mask, vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) { vfloat32m8_t test_vfnmacc_vv_f32m8_tum(vbool4_t mask, vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfnmacc_tum(mask, vd, vs1, vs2, vl); return __riscv_vfnmacc_tum(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmacc_vf_f32m8_tum // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmacc_vf_f32m8_tum
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmacc.mask.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmacc.mask.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfnmacc_vf_f32m8_tum(vbool4_t mask, vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) { vfloat32m8_t test_vfnmacc_vf_f32m8_tum(vbool4_t mask, vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfnmacc_tum(mask, vd, rs1, vs2, vl); return __riscv_vfnmacc_tum(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmacc_vv_f64m1_tum // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmacc_vv_f64m1_tum
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmacc.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmacc.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfnmacc_vv_f64m1_tum(vbool64_t mask, vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) { vfloat64m1_t test_vfnmacc_vv_f64m1_tum(vbool64_t mask, vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfnmacc_tum(mask, vd, vs1, vs2, vl); return __riscv_vfnmacc_tum(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmacc_vf_f64m1_tum // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmacc_vf_f64m1_tum
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmacc.mask.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmacc.mask.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfnmacc_vf_f64m1_tum(vbool64_t mask, vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) { vfloat64m1_t test_vfnmacc_vf_f64m1_tum(vbool64_t mask, vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfnmacc_tum(mask, vd, rs1, vs2, vl); return __riscv_vfnmacc_tum(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmacc_vv_f64m2_tum // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmacc_vv_f64m2_tum
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmacc.mask.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmacc.mask.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfnmacc_vv_f64m2_tum(vbool32_t mask, vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) { vfloat64m2_t test_vfnmacc_vv_f64m2_tum(vbool32_t mask, vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfnmacc_tum(mask, vd, vs1, vs2, vl); return __riscv_vfnmacc_tum(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmacc_vf_f64m2_tum // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmacc_vf_f64m2_tum
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmacc.mask.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmacc.mask.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfnmacc_vf_f64m2_tum(vbool32_t mask, vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) { vfloat64m2_t test_vfnmacc_vf_f64m2_tum(vbool32_t mask, vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfnmacc_tum(mask, vd, rs1, vs2, vl); return __riscv_vfnmacc_tum(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmacc_vv_f64m4_tum // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmacc_vv_f64m4_tum
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmacc.mask.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmacc.mask.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfnmacc_vv_f64m4_tum(vbool16_t mask, vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) { vfloat64m4_t test_vfnmacc_vv_f64m4_tum(vbool16_t mask, vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfnmacc_tum(mask, vd, vs1, vs2, vl); return __riscv_vfnmacc_tum(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmacc_vf_f64m4_tum // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmacc_vf_f64m4_tum
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmacc.mask.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmacc.mask.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfnmacc_vf_f64m4_tum(vbool16_t mask, vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) { vfloat64m4_t test_vfnmacc_vf_f64m4_tum(vbool16_t mask, vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfnmacc_tum(mask, vd, rs1, vs2, vl); return __riscv_vfnmacc_tum(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmacc_vv_f64m8_tum // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmacc_vv_f64m8_tum
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmacc.mask.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmacc.mask.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfnmacc_vv_f64m8_tum(vbool8_t mask, vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) { vfloat64m8_t test_vfnmacc_vv_f64m8_tum(vbool8_t mask, vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfnmacc_tum(mask, vd, vs1, vs2, vl); return __riscv_vfnmacc_tum(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmacc_vf_f64m8_tum // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmacc_vf_f64m8_tum
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmacc.mask.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmacc.mask.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfnmacc_vf_f64m8_tum(vbool8_t mask, vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) { vfloat64m8_t test_vfnmacc_vf_f64m8_tum(vbool8_t mask, vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfnmacc_tum(mask, vd, rs1, vs2, vl); return __riscv_vfnmacc_tum(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmacc_vv_f16mf4_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmacc_vv_f16mf4_tumu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmacc.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmacc.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
// //
vfloat16mf4_t test_vfnmacc_vv_f16mf4_tumu(vbool64_t mask, vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) { vfloat16mf4_t test_vfnmacc_vv_f16mf4_tumu(vbool64_t mask, vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfnmacc_tumu(mask, vd, vs1, vs2, vl); return __riscv_vfnmacc_tumu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmacc_vf_f16mf4_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmacc_vf_f16mf4_tumu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmacc.mask.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmacc.mask.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
// //
vfloat16mf4_t test_vfnmacc_vf_f16mf4_tumu(vbool64_t mask, vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) { vfloat16mf4_t test_vfnmacc_vf_f16mf4_tumu(vbool64_t mask, vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfnmacc_tumu(mask, vd, rs1, vs2, vl); return __riscv_vfnmacc_tumu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmacc_vv_f16mf2_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmacc_vv_f16mf2_tumu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmacc.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmacc.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
// //
vfloat16mf2_t test_vfnmacc_vv_f16mf2_tumu(vbool32_t mask, vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) { vfloat16mf2_t test_vfnmacc_vv_f16mf2_tumu(vbool32_t mask, vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfnmacc_tumu(mask, vd, vs1, vs2, vl); return __riscv_vfnmacc_tumu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmacc_vf_f16mf2_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmacc_vf_f16mf2_tumu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmacc.mask.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmacc.mask.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
// //
vfloat16mf2_t test_vfnmacc_vf_f16mf2_tumu(vbool32_t mask, vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) { vfloat16mf2_t test_vfnmacc_vf_f16mf2_tumu(vbool32_t mask, vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfnmacc_tumu(mask, vd, rs1, vs2, vl); return __riscv_vfnmacc_tumu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmacc_vv_f16m1_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmacc_vv_f16m1_tumu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmacc.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmacc.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
// //
vfloat16m1_t test_vfnmacc_vv_f16m1_tumu(vbool16_t mask, vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) { vfloat16m1_t test_vfnmacc_vv_f16m1_tumu(vbool16_t mask, vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfnmacc_tumu(mask, vd, vs1, vs2, vl); return __riscv_vfnmacc_tumu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmacc_vf_f16m1_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmacc_vf_f16m1_tumu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmacc.mask.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmacc.mask.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
// //
vfloat16m1_t test_vfnmacc_vf_f16m1_tumu(vbool16_t mask, vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) { vfloat16m1_t test_vfnmacc_vf_f16m1_tumu(vbool16_t mask, vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfnmacc_tumu(mask, vd, rs1, vs2, vl); return __riscv_vfnmacc_tumu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmacc_vv_f16m2_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmacc_vv_f16m2_tumu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmacc.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmacc.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
// //
vfloat16m2_t test_vfnmacc_vv_f16m2_tumu(vbool8_t mask, vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) { vfloat16m2_t test_vfnmacc_vv_f16m2_tumu(vbool8_t mask, vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfnmacc_tumu(mask, vd, vs1, vs2, vl); return __riscv_vfnmacc_tumu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmacc_vf_f16m2_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmacc_vf_f16m2_tumu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmacc.mask.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmacc.mask.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
// //
vfloat16m2_t test_vfnmacc_vf_f16m2_tumu(vbool8_t mask, vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) { vfloat16m2_t test_vfnmacc_vf_f16m2_tumu(vbool8_t mask, vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfnmacc_tumu(mask, vd, rs1, vs2, vl); return __riscv_vfnmacc_tumu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmacc_vv_f16m4_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmacc_vv_f16m4_tumu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmacc.mask.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmacc.mask.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
// //
vfloat16m4_t test_vfnmacc_vv_f16m4_tumu(vbool4_t mask, vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) { vfloat16m4_t test_vfnmacc_vv_f16m4_tumu(vbool4_t mask, vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfnmacc_tumu(mask, vd, vs1, vs2, vl); return __riscv_vfnmacc_tumu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmacc_vf_f16m4_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmacc_vf_f16m4_tumu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmacc.mask.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmacc.mask.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
// //
vfloat16m4_t test_vfnmacc_vf_f16m4_tumu(vbool4_t mask, vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) { vfloat16m4_t test_vfnmacc_vf_f16m4_tumu(vbool4_t mask, vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfnmacc_tumu(mask, vd, rs1, vs2, vl); return __riscv_vfnmacc_tumu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmacc_vv_f16m8_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmacc_vv_f16m8_tumu
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmacc.mask.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmacc.mask.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
// //
vfloat16m8_t test_vfnmacc_vv_f16m8_tumu(vbool2_t mask, vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) { vfloat16m8_t test_vfnmacc_vv_f16m8_tumu(vbool2_t mask, vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfnmacc_tumu(mask, vd, vs1, vs2, vl); return __riscv_vfnmacc_tumu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmacc_vf_f16m8_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmacc_vf_f16m8_tumu
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmacc.mask.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmacc.mask.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
// //
vfloat16m8_t test_vfnmacc_vf_f16m8_tumu(vbool2_t mask, vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) { vfloat16m8_t test_vfnmacc_vf_f16m8_tumu(vbool2_t mask, vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfnmacc_tumu(mask, vd, rs1, vs2, vl); return __riscv_vfnmacc_tumu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmacc_vv_f32mf2_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmacc_vv_f32mf2_tumu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmacc.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmacc.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfnmacc_vv_f32mf2_tumu(vbool64_t mask, vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) { vfloat32mf2_t test_vfnmacc_vv_f32mf2_tumu(vbool64_t mask, vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfnmacc_tumu(mask, vd, vs1, vs2, vl); return __riscv_vfnmacc_tumu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmacc_vf_f32mf2_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmacc_vf_f32mf2_tumu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmacc.mask.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmacc.mask.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfnmacc_vf_f32mf2_tumu(vbool64_t mask, vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) { vfloat32mf2_t test_vfnmacc_vf_f32mf2_tumu(vbool64_t mask, vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfnmacc_tumu(mask, vd, rs1, vs2, vl); return __riscv_vfnmacc_tumu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmacc_vv_f32m1_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmacc_vv_f32m1_tumu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmacc.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmacc.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfnmacc_vv_f32m1_tumu(vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) { vfloat32m1_t test_vfnmacc_vv_f32m1_tumu(vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfnmacc_tumu(mask, vd, vs1, vs2, vl); return __riscv_vfnmacc_tumu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmacc_vf_f32m1_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmacc_vf_f32m1_tumu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmacc.mask.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmacc.mask.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfnmacc_vf_f32m1_tumu(vbool32_t mask, vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) { vfloat32m1_t test_vfnmacc_vf_f32m1_tumu(vbool32_t mask, vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfnmacc_tumu(mask, vd, rs1, vs2, vl); return __riscv_vfnmacc_tumu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmacc_vv_f32m2_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmacc_vv_f32m2_tumu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmacc.mask.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmacc.mask.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfnmacc_vv_f32m2_tumu(vbool16_t mask, vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) { vfloat32m2_t test_vfnmacc_vv_f32m2_tumu(vbool16_t mask, vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfnmacc_tumu(mask, vd, vs1, vs2, vl); return __riscv_vfnmacc_tumu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmacc_vf_f32m2_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmacc_vf_f32m2_tumu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmacc.mask.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmacc.mask.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfnmacc_vf_f32m2_tumu(vbool16_t mask, vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) { vfloat32m2_t test_vfnmacc_vf_f32m2_tumu(vbool16_t mask, vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfnmacc_tumu(mask, vd, rs1, vs2, vl); return __riscv_vfnmacc_tumu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmacc_vv_f32m4_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmacc_vv_f32m4_tumu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmacc.mask.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmacc.mask.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfnmacc_vv_f32m4_tumu(vbool8_t mask, vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) { vfloat32m4_t test_vfnmacc_vv_f32m4_tumu(vbool8_t mask, vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfnmacc_tumu(mask, vd, vs1, vs2, vl); return __riscv_vfnmacc_tumu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmacc_vf_f32m4_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmacc_vf_f32m4_tumu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmacc.mask.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmacc.mask.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfnmacc_vf_f32m4_tumu(vbool8_t mask, vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) { vfloat32m4_t test_vfnmacc_vf_f32m4_tumu(vbool8_t mask, vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfnmacc_tumu(mask, vd, rs1, vs2, vl); return __riscv_vfnmacc_tumu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmacc_vv_f32m8_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmacc_vv_f32m8_tumu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmacc.mask.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmacc.mask.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfnmacc_vv_f32m8_tumu(vbool4_t mask, vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) { vfloat32m8_t test_vfnmacc_vv_f32m8_tumu(vbool4_t mask, vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfnmacc_tumu(mask, vd, vs1, vs2, vl); return __riscv_vfnmacc_tumu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmacc_vf_f32m8_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmacc_vf_f32m8_tumu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmacc.mask.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmacc.mask.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfnmacc_vf_f32m8_tumu(vbool4_t mask, vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) { vfloat32m8_t test_vfnmacc_vf_f32m8_tumu(vbool4_t mask, vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfnmacc_tumu(mask, vd, rs1, vs2, vl); return __riscv_vfnmacc_tumu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmacc_vv_f64m1_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmacc_vv_f64m1_tumu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmacc.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmacc.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfnmacc_vv_f64m1_tumu(vbool64_t mask, vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) { vfloat64m1_t test_vfnmacc_vv_f64m1_tumu(vbool64_t mask, vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfnmacc_tumu(mask, vd, vs1, vs2, vl); return __riscv_vfnmacc_tumu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmacc_vf_f64m1_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmacc_vf_f64m1_tumu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmacc.mask.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmacc.mask.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfnmacc_vf_f64m1_tumu(vbool64_t mask, vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) { vfloat64m1_t test_vfnmacc_vf_f64m1_tumu(vbool64_t mask, vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfnmacc_tumu(mask, vd, rs1, vs2, vl); return __riscv_vfnmacc_tumu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmacc_vv_f64m2_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmacc_vv_f64m2_tumu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmacc.mask.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmacc.mask.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfnmacc_vv_f64m2_tumu(vbool32_t mask, vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) { vfloat64m2_t test_vfnmacc_vv_f64m2_tumu(vbool32_t mask, vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfnmacc_tumu(mask, vd, vs1, vs2, vl); return __riscv_vfnmacc_tumu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmacc_vf_f64m2_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmacc_vf_f64m2_tumu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmacc.mask.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmacc.mask.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfnmacc_vf_f64m2_tumu(vbool32_t mask, vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) { vfloat64m2_t test_vfnmacc_vf_f64m2_tumu(vbool32_t mask, vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfnmacc_tumu(mask, vd, rs1, vs2, vl); return __riscv_vfnmacc_tumu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmacc_vv_f64m4_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmacc_vv_f64m4_tumu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmacc.mask.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmacc.mask.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfnmacc_vv_f64m4_tumu(vbool16_t mask, vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) { vfloat64m4_t test_vfnmacc_vv_f64m4_tumu(vbool16_t mask, vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfnmacc_tumu(mask, vd, vs1, vs2, vl); return __riscv_vfnmacc_tumu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmacc_vf_f64m4_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmacc_vf_f64m4_tumu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmacc.mask.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmacc.mask.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfnmacc_vf_f64m4_tumu(vbool16_t mask, vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) { vfloat64m4_t test_vfnmacc_vf_f64m4_tumu(vbool16_t mask, vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfnmacc_tumu(mask, vd, rs1, vs2, vl); return __riscv_vfnmacc_tumu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmacc_vv_f64m8_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmacc_vv_f64m8_tumu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmacc.mask.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmacc.mask.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfnmacc_vv_f64m8_tumu(vbool8_t mask, vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) { vfloat64m8_t test_vfnmacc_vv_f64m8_tumu(vbool8_t mask, vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfnmacc_tumu(mask, vd, vs1, vs2, vl); return __riscv_vfnmacc_tumu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmacc_vf_f64m8_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmacc_vf_f64m8_tumu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmacc.mask.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmacc.mask.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfnmacc_vf_f64m8_tumu(vbool8_t mask, vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) { vfloat64m8_t test_vfnmacc_vf_f64m8_tumu(vbool8_t mask, vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfnmacc_tumu(mask, vd, rs1, vs2, vl); return __riscv_vfnmacc_tumu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmacc_vv_f16mf4_mu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmacc_vv_f16mf4_mu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmacc.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmacc.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
// //
vfloat16mf4_t test_vfnmacc_vv_f16mf4_mu(vbool64_t mask, vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) { vfloat16mf4_t test_vfnmacc_vv_f16mf4_mu(vbool64_t mask, vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfnmacc_mu(mask, vd, vs1, vs2, vl); return __riscv_vfnmacc_mu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmacc_vf_f16mf4_mu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmacc_vf_f16mf4_mu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmacc.mask.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmacc.mask.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
// //
vfloat16mf4_t test_vfnmacc_vf_f16mf4_mu(vbool64_t mask, vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) { vfloat16mf4_t test_vfnmacc_vf_f16mf4_mu(vbool64_t mask, vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfnmacc_mu(mask, vd, rs1, vs2, vl); return __riscv_vfnmacc_mu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmacc_vv_f16mf2_mu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmacc_vv_f16mf2_mu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmacc.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmacc.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
// //
vfloat16mf2_t test_vfnmacc_vv_f16mf2_mu(vbool32_t mask, vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) { vfloat16mf2_t test_vfnmacc_vv_f16mf2_mu(vbool32_t mask, vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfnmacc_mu(mask, vd, vs1, vs2, vl); return __riscv_vfnmacc_mu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmacc_vf_f16mf2_mu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmacc_vf_f16mf2_mu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmacc.mask.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmacc.mask.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
// //
vfloat16mf2_t test_vfnmacc_vf_f16mf2_mu(vbool32_t mask, vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) { vfloat16mf2_t test_vfnmacc_vf_f16mf2_mu(vbool32_t mask, vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfnmacc_mu(mask, vd, rs1, vs2, vl); return __riscv_vfnmacc_mu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmacc_vv_f16m1_mu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmacc_vv_f16m1_mu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmacc.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmacc.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
// //
vfloat16m1_t test_vfnmacc_vv_f16m1_mu(vbool16_t mask, vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) { vfloat16m1_t test_vfnmacc_vv_f16m1_mu(vbool16_t mask, vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfnmacc_mu(mask, vd, vs1, vs2, vl); return __riscv_vfnmacc_mu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmacc_vf_f16m1_mu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmacc_vf_f16m1_mu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmacc.mask.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmacc.mask.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
// //
vfloat16m1_t test_vfnmacc_vf_f16m1_mu(vbool16_t mask, vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) { vfloat16m1_t test_vfnmacc_vf_f16m1_mu(vbool16_t mask, vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfnmacc_mu(mask, vd, rs1, vs2, vl); return __riscv_vfnmacc_mu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmacc_vv_f16m2_mu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmacc_vv_f16m2_mu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmacc.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmacc.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
// //
vfloat16m2_t test_vfnmacc_vv_f16m2_mu(vbool8_t mask, vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) { vfloat16m2_t test_vfnmacc_vv_f16m2_mu(vbool8_t mask, vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfnmacc_mu(mask, vd, vs1, vs2, vl); return __riscv_vfnmacc_mu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmacc_vf_f16m2_mu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmacc_vf_f16m2_mu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmacc.mask.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmacc.mask.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
// //
vfloat16m2_t test_vfnmacc_vf_f16m2_mu(vbool8_t mask, vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) { vfloat16m2_t test_vfnmacc_vf_f16m2_mu(vbool8_t mask, vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfnmacc_mu(mask, vd, rs1, vs2, vl); return __riscv_vfnmacc_mu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmacc_vv_f16m4_mu // CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmacc_vv_f16m4_mu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmacc.mask.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmacc.mask.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
// //
vfloat16m4_t test_vfnmacc_vv_f16m4_mu(vbool4_t mask, vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) { vfloat16m4_t test_vfnmacc_vv_f16m4_mu(vbool4_t mask, vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfnmacc_mu(mask, vd, vs1, vs2, vl); return __riscv_vfnmacc_mu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmacc_vf_f16m4_mu // CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmacc_vf_f16m4_mu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmacc.mask.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmacc.mask.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
// //
vfloat16m4_t test_vfnmacc_vf_f16m4_mu(vbool4_t mask, vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) { vfloat16m4_t test_vfnmacc_vf_f16m4_mu(vbool4_t mask, vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfnmacc_mu(mask, vd, rs1, vs2, vl); return __riscv_vfnmacc_mu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmacc_vv_f16m8_mu // CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmacc_vv_f16m8_mu
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmacc.mask.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmacc.mask.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
// //
vfloat16m8_t test_vfnmacc_vv_f16m8_mu(vbool2_t mask, vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) { vfloat16m8_t test_vfnmacc_vv_f16m8_mu(vbool2_t mask, vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfnmacc_mu(mask, vd, vs1, vs2, vl); return __riscv_vfnmacc_mu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmacc_vf_f16m8_mu // CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmacc_vf_f16m8_mu
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmacc.mask.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmacc.mask.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
// //
vfloat16m8_t test_vfnmacc_vf_f16m8_mu(vbool2_t mask, vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) { vfloat16m8_t test_vfnmacc_vf_f16m8_mu(vbool2_t mask, vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfnmacc_mu(mask, vd, rs1, vs2, vl); return __riscv_vfnmacc_mu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmacc_vv_f32mf2_mu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmacc_vv_f32mf2_mu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmacc.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmacc.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfnmacc_vv_f32mf2_mu(vbool64_t mask, vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) { vfloat32mf2_t test_vfnmacc_vv_f32mf2_mu(vbool64_t mask, vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfnmacc_mu(mask, vd, vs1, vs2, vl); return __riscv_vfnmacc_mu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmacc_vf_f32mf2_mu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmacc_vf_f32mf2_mu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmacc.mask.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmacc.mask.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfnmacc_vf_f32mf2_mu(vbool64_t mask, vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) { vfloat32mf2_t test_vfnmacc_vf_f32mf2_mu(vbool64_t mask, vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfnmacc_mu(mask, vd, rs1, vs2, vl); return __riscv_vfnmacc_mu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmacc_vv_f32m1_mu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmacc_vv_f32m1_mu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmacc.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmacc.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfnmacc_vv_f32m1_mu(vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) { vfloat32m1_t test_vfnmacc_vv_f32m1_mu(vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfnmacc_mu(mask, vd, vs1, vs2, vl); return __riscv_vfnmacc_mu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmacc_vf_f32m1_mu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmacc_vf_f32m1_mu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmacc.mask.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmacc.mask.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfnmacc_vf_f32m1_mu(vbool32_t mask, vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) { vfloat32m1_t test_vfnmacc_vf_f32m1_mu(vbool32_t mask, vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfnmacc_mu(mask, vd, rs1, vs2, vl); return __riscv_vfnmacc_mu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmacc_vv_f32m2_mu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmacc_vv_f32m2_mu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmacc.mask.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmacc.mask.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfnmacc_vv_f32m2_mu(vbool16_t mask, vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) { vfloat32m2_t test_vfnmacc_vv_f32m2_mu(vbool16_t mask, vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfnmacc_mu(mask, vd, vs1, vs2, vl); return __riscv_vfnmacc_mu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmacc_vf_f32m2_mu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmacc_vf_f32m2_mu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmacc.mask.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmacc.mask.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfnmacc_vf_f32m2_mu(vbool16_t mask, vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) { vfloat32m2_t test_vfnmacc_vf_f32m2_mu(vbool16_t mask, vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfnmacc_mu(mask, vd, rs1, vs2, vl); return __riscv_vfnmacc_mu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmacc_vv_f32m4_mu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmacc_vv_f32m4_mu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmacc.mask.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmacc.mask.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfnmacc_vv_f32m4_mu(vbool8_t mask, vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) { vfloat32m4_t test_vfnmacc_vv_f32m4_mu(vbool8_t mask, vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfnmacc_mu(mask, vd, vs1, vs2, vl); return __riscv_vfnmacc_mu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmacc_vf_f32m4_mu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmacc_vf_f32m4_mu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmacc.mask.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmacc.mask.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfnmacc_vf_f32m4_mu(vbool8_t mask, vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) { vfloat32m4_t test_vfnmacc_vf_f32m4_mu(vbool8_t mask, vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfnmacc_mu(mask, vd, rs1, vs2, vl); return __riscv_vfnmacc_mu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmacc_vv_f32m8_mu // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmacc_vv_f32m8_mu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmacc.mask.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmacc.mask.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfnmacc_vv_f32m8_mu(vbool4_t mask, vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) { vfloat32m8_t test_vfnmacc_vv_f32m8_mu(vbool4_t mask, vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfnmacc_mu(mask, vd, vs1, vs2, vl); return __riscv_vfnmacc_mu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmacc_vf_f32m8_mu // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmacc_vf_f32m8_mu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmacc.mask.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmacc.mask.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfnmacc_vf_f32m8_mu(vbool4_t mask, vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) { vfloat32m8_t test_vfnmacc_vf_f32m8_mu(vbool4_t mask, vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfnmacc_mu(mask, vd, rs1, vs2, vl); return __riscv_vfnmacc_mu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmacc_vv_f64m1_mu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmacc_vv_f64m1_mu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmacc.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmacc.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfnmacc_vv_f64m1_mu(vbool64_t mask, vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) { vfloat64m1_t test_vfnmacc_vv_f64m1_mu(vbool64_t mask, vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfnmacc_mu(mask, vd, vs1, vs2, vl); return __riscv_vfnmacc_mu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmacc_vf_f64m1_mu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmacc_vf_f64m1_mu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmacc.mask.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmacc.mask.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfnmacc_vf_f64m1_mu(vbool64_t mask, vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) { vfloat64m1_t test_vfnmacc_vf_f64m1_mu(vbool64_t mask, vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfnmacc_mu(mask, vd, rs1, vs2, vl); return __riscv_vfnmacc_mu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmacc_vv_f64m2_mu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmacc_vv_f64m2_mu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmacc.mask.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmacc.mask.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfnmacc_vv_f64m2_mu(vbool32_t mask, vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) { vfloat64m2_t test_vfnmacc_vv_f64m2_mu(vbool32_t mask, vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfnmacc_mu(mask, vd, vs1, vs2, vl); return __riscv_vfnmacc_mu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmacc_vf_f64m2_mu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmacc_vf_f64m2_mu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmacc.mask.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmacc.mask.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfnmacc_vf_f64m2_mu(vbool32_t mask, vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) { vfloat64m2_t test_vfnmacc_vf_f64m2_mu(vbool32_t mask, vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfnmacc_mu(mask, vd, rs1, vs2, vl); return __riscv_vfnmacc_mu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmacc_vv_f64m4_mu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmacc_vv_f64m4_mu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmacc.mask.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmacc.mask.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfnmacc_vv_f64m4_mu(vbool16_t mask, vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) { vfloat64m4_t test_vfnmacc_vv_f64m4_mu(vbool16_t mask, vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfnmacc_mu(mask, vd, vs1, vs2, vl); return __riscv_vfnmacc_mu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmacc_vf_f64m4_mu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmacc_vf_f64m4_mu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmacc.mask.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmacc.mask.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfnmacc_vf_f64m4_mu(vbool16_t mask, vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) { vfloat64m4_t test_vfnmacc_vf_f64m4_mu(vbool16_t mask, vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfnmacc_mu(mask, vd, rs1, vs2, vl); return __riscv_vfnmacc_mu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmacc_vv_f64m8_mu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmacc_vv_f64m8_mu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmacc.mask.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmacc.mask.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfnmacc_vv_f64m8_mu(vbool8_t mask, vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) { vfloat64m8_t test_vfnmacc_vv_f64m8_mu(vbool8_t mask, vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfnmacc_mu(mask, vd, vs1, vs2, vl); return __riscv_vfnmacc_mu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmacc_vf_f64m8_mu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmacc_vf_f64m8_mu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmacc.mask.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmacc.mask.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfnmacc_vf_f64m8_mu(vbool8_t mask, vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) { vfloat64m8_t test_vfnmacc_vf_f64m8_mu(vbool8_t mask, vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfnmacc_mu(mask, vd, rs1, vs2, vl); return __riscv_vfnmacc_mu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmacc_vv_f16mf4_rm_tu
// CHECK-RV64-SAME: (<vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmacc.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
//
vfloat16mf4_t test_vfnmacc_vv_f16mf4_rm_tu(vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfnmacc_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmacc_vf_f16mf4_rm_tu
// CHECK-RV64-SAME: (<vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmacc.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
//
vfloat16mf4_t test_vfnmacc_vf_f16mf4_rm_tu(vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfnmacc_tu(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmacc_vv_f16mf2_rm_tu
// CHECK-RV64-SAME: (<vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmacc.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
//
vfloat16mf2_t test_vfnmacc_vv_f16mf2_rm_tu(vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfnmacc_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmacc_vf_f16mf2_rm_tu
// CHECK-RV64-SAME: (<vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmacc.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
//
vfloat16mf2_t test_vfnmacc_vf_f16mf2_rm_tu(vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfnmacc_tu(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmacc_vv_f16m1_rm_tu
// CHECK-RV64-SAME: (<vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmacc.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfnmacc_vv_f16m1_rm_tu(vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfnmacc_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmacc_vf_f16m1_rm_tu
// CHECK-RV64-SAME: (<vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmacc.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfnmacc_vf_f16m1_rm_tu(vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfnmacc_tu(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmacc_vv_f16m2_rm_tu
// CHECK-RV64-SAME: (<vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmacc.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
//
vfloat16m2_t test_vfnmacc_vv_f16m2_rm_tu(vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfnmacc_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmacc_vf_f16m2_rm_tu
// CHECK-RV64-SAME: (<vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmacc.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
//
vfloat16m2_t test_vfnmacc_vf_f16m2_rm_tu(vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfnmacc_tu(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmacc_vv_f16m4_rm_tu
// CHECK-RV64-SAME: (<vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmacc.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
//
vfloat16m4_t test_vfnmacc_vv_f16m4_rm_tu(vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfnmacc_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmacc_vf_f16m4_rm_tu
// CHECK-RV64-SAME: (<vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmacc.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
//
vfloat16m4_t test_vfnmacc_vf_f16m4_rm_tu(vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfnmacc_tu(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmacc_vv_f16m8_rm_tu
// CHECK-RV64-SAME: (<vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmacc.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
//
vfloat16m8_t test_vfnmacc_vv_f16m8_rm_tu(vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfnmacc_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmacc_vf_f16m8_rm_tu
// CHECK-RV64-SAME: (<vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmacc.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
//
vfloat16m8_t test_vfnmacc_vf_f16m8_rm_tu(vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfnmacc_tu(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmacc_vv_f32mf2_rm_tu
// CHECK-RV64-SAME: (<vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmacc.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
//
vfloat32mf2_t test_vfnmacc_vv_f32mf2_rm_tu(vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfnmacc_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmacc_vf_f32mf2_rm_tu
// CHECK-RV64-SAME: (<vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmacc.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
//
vfloat32mf2_t test_vfnmacc_vf_f32mf2_rm_tu(vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfnmacc_tu(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmacc_vv_f32m1_rm_tu
// CHECK-RV64-SAME: (<vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmacc.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfnmacc_vv_f32m1_rm_tu(vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfnmacc_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmacc_vf_f32m1_rm_tu
// CHECK-RV64-SAME: (<vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmacc.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfnmacc_vf_f32m1_rm_tu(vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfnmacc_tu(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmacc_vv_f32m2_rm_tu
// CHECK-RV64-SAME: (<vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmacc.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
//
vfloat32m2_t test_vfnmacc_vv_f32m2_rm_tu(vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfnmacc_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmacc_vf_f32m2_rm_tu
// CHECK-RV64-SAME: (<vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmacc.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
//
vfloat32m2_t test_vfnmacc_vf_f32m2_rm_tu(vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfnmacc_tu(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmacc_vv_f32m4_rm_tu
// CHECK-RV64-SAME: (<vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmacc.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
//
vfloat32m4_t test_vfnmacc_vv_f32m4_rm_tu(vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfnmacc_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmacc_vf_f32m4_rm_tu
// CHECK-RV64-SAME: (<vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmacc.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
//
vfloat32m4_t test_vfnmacc_vf_f32m4_rm_tu(vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfnmacc_tu(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmacc_vv_f32m8_rm_tu
// CHECK-RV64-SAME: (<vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmacc.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
//
vfloat32m8_t test_vfnmacc_vv_f32m8_rm_tu(vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfnmacc_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmacc_vf_f32m8_rm_tu
// CHECK-RV64-SAME: (<vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmacc.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
//
vfloat32m8_t test_vfnmacc_vf_f32m8_rm_tu(vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfnmacc_tu(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmacc_vv_f64m1_rm_tu
// CHECK-RV64-SAME: (<vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmacc.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfnmacc_vv_f64m1_rm_tu(vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfnmacc_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmacc_vf_f64m1_rm_tu
// CHECK-RV64-SAME: (<vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmacc.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfnmacc_vf_f64m1_rm_tu(vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfnmacc_tu(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmacc_vv_f64m2_rm_tu
// CHECK-RV64-SAME: (<vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmacc.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
//
vfloat64m2_t test_vfnmacc_vv_f64m2_rm_tu(vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfnmacc_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmacc_vf_f64m2_rm_tu
// CHECK-RV64-SAME: (<vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmacc.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
//
vfloat64m2_t test_vfnmacc_vf_f64m2_rm_tu(vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfnmacc_tu(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmacc_vv_f64m4_rm_tu
// CHECK-RV64-SAME: (<vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmacc.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
//
vfloat64m4_t test_vfnmacc_vv_f64m4_rm_tu(vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfnmacc_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmacc_vf_f64m4_rm_tu
// CHECK-RV64-SAME: (<vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmacc.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
//
vfloat64m4_t test_vfnmacc_vf_f64m4_rm_tu(vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfnmacc_tu(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmacc_vv_f64m8_rm_tu
// CHECK-RV64-SAME: (<vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmacc.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
//
vfloat64m8_t test_vfnmacc_vv_f64m8_rm_tu(vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfnmacc_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmacc_vf_f64m8_rm_tu
// CHECK-RV64-SAME: (<vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmacc.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
//
vfloat64m8_t test_vfnmacc_vf_f64m8_rm_tu(vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfnmacc_tu(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmacc_vv_f16mf4_rm_tum
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmacc.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
//
vfloat16mf4_t test_vfnmacc_vv_f16mf4_rm_tum(vbool64_t mask, vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfnmacc_tum(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmacc_vf_f16mf4_rm_tum
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmacc.mask.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
//
vfloat16mf4_t test_vfnmacc_vf_f16mf4_rm_tum(vbool64_t mask, vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfnmacc_tum(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmacc_vv_f16mf2_rm_tum
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmacc.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
//
vfloat16mf2_t test_vfnmacc_vv_f16mf2_rm_tum(vbool32_t mask, vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfnmacc_tum(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmacc_vf_f16mf2_rm_tum
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmacc.mask.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
//
vfloat16mf2_t test_vfnmacc_vf_f16mf2_rm_tum(vbool32_t mask, vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfnmacc_tum(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmacc_vv_f16m1_rm_tum
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmacc.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfnmacc_vv_f16m1_rm_tum(vbool16_t mask, vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfnmacc_tum(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmacc_vf_f16m1_rm_tum
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmacc.mask.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfnmacc_vf_f16m1_rm_tum(vbool16_t mask, vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfnmacc_tum(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmacc_vv_f16m2_rm_tum
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmacc.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
//
vfloat16m2_t test_vfnmacc_vv_f16m2_rm_tum(vbool8_t mask, vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfnmacc_tum(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmacc_vf_f16m2_rm_tum
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmacc.mask.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
//
vfloat16m2_t test_vfnmacc_vf_f16m2_rm_tum(vbool8_t mask, vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfnmacc_tum(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmacc_vv_f16m4_rm_tum
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmacc.mask.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
//
vfloat16m4_t test_vfnmacc_vv_f16m4_rm_tum(vbool4_t mask, vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfnmacc_tum(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmacc_vf_f16m4_rm_tum
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmacc.mask.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
//
vfloat16m4_t test_vfnmacc_vf_f16m4_rm_tum(vbool4_t mask, vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfnmacc_tum(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmacc_vv_f16m8_rm_tum
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmacc.mask.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
//
vfloat16m8_t test_vfnmacc_vv_f16m8_rm_tum(vbool2_t mask, vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfnmacc_tum(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmacc_vf_f16m8_rm_tum
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmacc.mask.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
//
vfloat16m8_t test_vfnmacc_vf_f16m8_rm_tum(vbool2_t mask, vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfnmacc_tum(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmacc_vv_f32mf2_rm_tum
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmacc.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
//
vfloat32mf2_t test_vfnmacc_vv_f32mf2_rm_tum(vbool64_t mask, vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfnmacc_tum(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmacc_vf_f32mf2_rm_tum
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmacc.mask.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
//
vfloat32mf2_t test_vfnmacc_vf_f32mf2_rm_tum(vbool64_t mask, vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfnmacc_tum(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmacc_vv_f32m1_rm_tum
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmacc.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfnmacc_vv_f32m1_rm_tum(vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfnmacc_tum(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmacc_vf_f32m1_rm_tum
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmacc.mask.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfnmacc_vf_f32m1_rm_tum(vbool32_t mask, vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfnmacc_tum(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmacc_vv_f32m2_rm_tum
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmacc.mask.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
//
vfloat32m2_t test_vfnmacc_vv_f32m2_rm_tum(vbool16_t mask, vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfnmacc_tum(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmacc_vf_f32m2_rm_tum
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmacc.mask.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
//
vfloat32m2_t test_vfnmacc_vf_f32m2_rm_tum(vbool16_t mask, vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfnmacc_tum(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmacc_vv_f32m4_rm_tum
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmacc.mask.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
//
vfloat32m4_t test_vfnmacc_vv_f32m4_rm_tum(vbool8_t mask, vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfnmacc_tum(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmacc_vf_f32m4_rm_tum
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmacc.mask.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
//
vfloat32m4_t test_vfnmacc_vf_f32m4_rm_tum(vbool8_t mask, vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfnmacc_tum(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmacc_vv_f32m8_rm_tum
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmacc.mask.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
//
vfloat32m8_t test_vfnmacc_vv_f32m8_rm_tum(vbool4_t mask, vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfnmacc_tum(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmacc_vf_f32m8_rm_tum
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmacc.mask.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
//
vfloat32m8_t test_vfnmacc_vf_f32m8_rm_tum(vbool4_t mask, vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfnmacc_tum(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmacc_vv_f64m1_rm_tum
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmacc.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfnmacc_vv_f64m1_rm_tum(vbool64_t mask, vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfnmacc_tum(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmacc_vf_f64m1_rm_tum
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmacc.mask.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfnmacc_vf_f64m1_rm_tum(vbool64_t mask, vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfnmacc_tum(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmacc_vv_f64m2_rm_tum
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmacc.mask.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
//
vfloat64m2_t test_vfnmacc_vv_f64m2_rm_tum(vbool32_t mask, vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfnmacc_tum(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmacc_vf_f64m2_rm_tum
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmacc.mask.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
//
vfloat64m2_t test_vfnmacc_vf_f64m2_rm_tum(vbool32_t mask, vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfnmacc_tum(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmacc_vv_f64m4_rm_tum
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmacc.mask.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
//
vfloat64m4_t test_vfnmacc_vv_f64m4_rm_tum(vbool16_t mask, vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfnmacc_tum(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmacc_vf_f64m4_rm_tum
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmacc.mask.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
//
vfloat64m4_t test_vfnmacc_vf_f64m4_rm_tum(vbool16_t mask, vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfnmacc_tum(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmacc_vv_f64m8_rm_tum
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmacc.mask.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
//
vfloat64m8_t test_vfnmacc_vv_f64m8_rm_tum(vbool8_t mask, vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfnmacc_tum(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmacc_vf_f64m8_rm_tum
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmacc.mask.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
//
vfloat64m8_t test_vfnmacc_vf_f64m8_rm_tum(vbool8_t mask, vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfnmacc_tum(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmacc_vv_f16mf4_rm_tumu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmacc.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
//
vfloat16mf4_t test_vfnmacc_vv_f16mf4_rm_tumu(vbool64_t mask, vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfnmacc_tumu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmacc_vf_f16mf4_rm_tumu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmacc.mask.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
//
vfloat16mf4_t test_vfnmacc_vf_f16mf4_rm_tumu(vbool64_t mask, vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfnmacc_tumu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmacc_vv_f16mf2_rm_tumu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmacc.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
//
vfloat16mf2_t test_vfnmacc_vv_f16mf2_rm_tumu(vbool32_t mask, vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfnmacc_tumu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmacc_vf_f16mf2_rm_tumu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmacc.mask.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
//
vfloat16mf2_t test_vfnmacc_vf_f16mf2_rm_tumu(vbool32_t mask, vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfnmacc_tumu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmacc_vv_f16m1_rm_tumu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmacc.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfnmacc_vv_f16m1_rm_tumu(vbool16_t mask, vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfnmacc_tumu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmacc_vf_f16m1_rm_tumu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmacc.mask.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfnmacc_vf_f16m1_rm_tumu(vbool16_t mask, vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfnmacc_tumu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmacc_vv_f16m2_rm_tumu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmacc.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
//
vfloat16m2_t test_vfnmacc_vv_f16m2_rm_tumu(vbool8_t mask, vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfnmacc_tumu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmacc_vf_f16m2_rm_tumu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmacc.mask.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
//
vfloat16m2_t test_vfnmacc_vf_f16m2_rm_tumu(vbool8_t mask, vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfnmacc_tumu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmacc_vv_f16m4_rm_tumu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmacc.mask.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
//
vfloat16m4_t test_vfnmacc_vv_f16m4_rm_tumu(vbool4_t mask, vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfnmacc_tumu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmacc_vf_f16m4_rm_tumu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmacc.mask.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
//
vfloat16m4_t test_vfnmacc_vf_f16m4_rm_tumu(vbool4_t mask, vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfnmacc_tumu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmacc_vv_f16m8_rm_tumu
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmacc.mask.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
//
vfloat16m8_t test_vfnmacc_vv_f16m8_rm_tumu(vbool2_t mask, vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfnmacc_tumu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmacc_vf_f16m8_rm_tumu
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmacc.mask.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
//
vfloat16m8_t test_vfnmacc_vf_f16m8_rm_tumu(vbool2_t mask, vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfnmacc_tumu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmacc_vv_f32mf2_rm_tumu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmacc.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
//
vfloat32mf2_t test_vfnmacc_vv_f32mf2_rm_tumu(vbool64_t mask, vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfnmacc_tumu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmacc_vf_f32mf2_rm_tumu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmacc.mask.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
//
vfloat32mf2_t test_vfnmacc_vf_f32mf2_rm_tumu(vbool64_t mask, vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfnmacc_tumu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmacc_vv_f32m1_rm_tumu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmacc.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfnmacc_vv_f32m1_rm_tumu(vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfnmacc_tumu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmacc_vf_f32m1_rm_tumu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmacc.mask.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfnmacc_vf_f32m1_rm_tumu(vbool32_t mask, vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfnmacc_tumu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmacc_vv_f32m2_rm_tumu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmacc.mask.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
//
vfloat32m2_t test_vfnmacc_vv_f32m2_rm_tumu(vbool16_t mask, vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfnmacc_tumu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmacc_vf_f32m2_rm_tumu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmacc.mask.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
//
vfloat32m2_t test_vfnmacc_vf_f32m2_rm_tumu(vbool16_t mask, vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfnmacc_tumu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmacc_vv_f32m4_rm_tumu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmacc.mask.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
//
vfloat32m4_t test_vfnmacc_vv_f32m4_rm_tumu(vbool8_t mask, vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfnmacc_tumu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmacc_vf_f32m4_rm_tumu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmacc.mask.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
//
vfloat32m4_t test_vfnmacc_vf_f32m4_rm_tumu(vbool8_t mask, vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfnmacc_tumu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmacc_vv_f32m8_rm_tumu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmacc.mask.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
//
vfloat32m8_t test_vfnmacc_vv_f32m8_rm_tumu(vbool4_t mask, vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfnmacc_tumu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmacc_vf_f32m8_rm_tumu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmacc.mask.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
//
vfloat32m8_t test_vfnmacc_vf_f32m8_rm_tumu(vbool4_t mask, vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfnmacc_tumu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmacc_vv_f64m1_rm_tumu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmacc.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfnmacc_vv_f64m1_rm_tumu(vbool64_t mask, vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfnmacc_tumu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmacc_vf_f64m1_rm_tumu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmacc.mask.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfnmacc_vf_f64m1_rm_tumu(vbool64_t mask, vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfnmacc_tumu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmacc_vv_f64m2_rm_tumu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmacc.mask.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
//
vfloat64m2_t test_vfnmacc_vv_f64m2_rm_tumu(vbool32_t mask, vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfnmacc_tumu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmacc_vf_f64m2_rm_tumu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmacc.mask.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
//
vfloat64m2_t test_vfnmacc_vf_f64m2_rm_tumu(vbool32_t mask, vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfnmacc_tumu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmacc_vv_f64m4_rm_tumu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmacc.mask.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
//
vfloat64m4_t test_vfnmacc_vv_f64m4_rm_tumu(vbool16_t mask, vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfnmacc_tumu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmacc_vf_f64m4_rm_tumu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmacc.mask.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
//
vfloat64m4_t test_vfnmacc_vf_f64m4_rm_tumu(vbool16_t mask, vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfnmacc_tumu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmacc_vv_f64m8_rm_tumu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmacc.mask.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
//
vfloat64m8_t test_vfnmacc_vv_f64m8_rm_tumu(vbool8_t mask, vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfnmacc_tumu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmacc_vf_f64m8_rm_tumu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmacc.mask.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
//
vfloat64m8_t test_vfnmacc_vf_f64m8_rm_tumu(vbool8_t mask, vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfnmacc_tumu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmacc_vv_f16mf4_rm_mu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmacc.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
//
vfloat16mf4_t test_vfnmacc_vv_f16mf4_rm_mu(vbool64_t mask, vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfnmacc_mu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmacc_vf_f16mf4_rm_mu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmacc.mask.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
//
vfloat16mf4_t test_vfnmacc_vf_f16mf4_rm_mu(vbool64_t mask, vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfnmacc_mu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmacc_vv_f16mf2_rm_mu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmacc.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
//
vfloat16mf2_t test_vfnmacc_vv_f16mf2_rm_mu(vbool32_t mask, vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfnmacc_mu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmacc_vf_f16mf2_rm_mu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmacc.mask.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
//
vfloat16mf2_t test_vfnmacc_vf_f16mf2_rm_mu(vbool32_t mask, vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfnmacc_mu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmacc_vv_f16m1_rm_mu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmacc.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfnmacc_vv_f16m1_rm_mu(vbool16_t mask, vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfnmacc_mu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmacc_vf_f16m1_rm_mu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmacc.mask.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfnmacc_vf_f16m1_rm_mu(vbool16_t mask, vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfnmacc_mu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmacc_vv_f16m2_rm_mu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmacc.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
//
vfloat16m2_t test_vfnmacc_vv_f16m2_rm_mu(vbool8_t mask, vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfnmacc_mu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmacc_vf_f16m2_rm_mu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmacc.mask.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
//
vfloat16m2_t test_vfnmacc_vf_f16m2_rm_mu(vbool8_t mask, vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfnmacc_mu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmacc_vv_f16m4_rm_mu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmacc.mask.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
//
vfloat16m4_t test_vfnmacc_vv_f16m4_rm_mu(vbool4_t mask, vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfnmacc_mu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmacc_vf_f16m4_rm_mu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmacc.mask.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
//
vfloat16m4_t test_vfnmacc_vf_f16m4_rm_mu(vbool4_t mask, vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfnmacc_mu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmacc_vv_f16m8_rm_mu
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmacc.mask.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
//
vfloat16m8_t test_vfnmacc_vv_f16m8_rm_mu(vbool2_t mask, vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfnmacc_mu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmacc_vf_f16m8_rm_mu
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmacc.mask.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
//
vfloat16m8_t test_vfnmacc_vf_f16m8_rm_mu(vbool2_t mask, vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfnmacc_mu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmacc_vv_f32mf2_rm_mu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmacc.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
//
vfloat32mf2_t test_vfnmacc_vv_f32mf2_rm_mu(vbool64_t mask, vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfnmacc_mu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmacc_vf_f32mf2_rm_mu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmacc.mask.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
//
vfloat32mf2_t test_vfnmacc_vf_f32mf2_rm_mu(vbool64_t mask, vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfnmacc_mu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmacc_vv_f32m1_rm_mu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmacc.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfnmacc_vv_f32m1_rm_mu(vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfnmacc_mu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmacc_vf_f32m1_rm_mu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmacc.mask.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfnmacc_vf_f32m1_rm_mu(vbool32_t mask, vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfnmacc_mu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmacc_vv_f32m2_rm_mu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmacc.mask.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
//
vfloat32m2_t test_vfnmacc_vv_f32m2_rm_mu(vbool16_t mask, vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfnmacc_mu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmacc_vf_f32m2_rm_mu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmacc.mask.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
//
vfloat32m2_t test_vfnmacc_vf_f32m2_rm_mu(vbool16_t mask, vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfnmacc_mu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmacc_vv_f32m4_rm_mu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmacc.mask.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
//
vfloat32m4_t test_vfnmacc_vv_f32m4_rm_mu(vbool8_t mask, vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfnmacc_mu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmacc_vf_f32m4_rm_mu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmacc.mask.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
//
vfloat32m4_t test_vfnmacc_vf_f32m4_rm_mu(vbool8_t mask, vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfnmacc_mu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmacc_vv_f32m8_rm_mu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmacc.mask.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
//
vfloat32m8_t test_vfnmacc_vv_f32m8_rm_mu(vbool4_t mask, vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfnmacc_mu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmacc_vf_f32m8_rm_mu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmacc.mask.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
//
vfloat32m8_t test_vfnmacc_vf_f32m8_rm_mu(vbool4_t mask, vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfnmacc_mu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmacc_vv_f64m1_rm_mu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmacc.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfnmacc_vv_f64m1_rm_mu(vbool64_t mask, vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfnmacc_mu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmacc_vf_f64m1_rm_mu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmacc.mask.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfnmacc_vf_f64m1_rm_mu(vbool64_t mask, vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfnmacc_mu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmacc_vv_f64m2_rm_mu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmacc.mask.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
//
vfloat64m2_t test_vfnmacc_vv_f64m2_rm_mu(vbool32_t mask, vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfnmacc_mu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmacc_vf_f64m2_rm_mu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmacc.mask.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
//
vfloat64m2_t test_vfnmacc_vf_f64m2_rm_mu(vbool32_t mask, vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfnmacc_mu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmacc_vv_f64m4_rm_mu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmacc.mask.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
//
vfloat64m4_t test_vfnmacc_vv_f64m4_rm_mu(vbool16_t mask, vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfnmacc_mu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmacc_vf_f64m4_rm_mu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmacc.mask.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
//
vfloat64m4_t test_vfnmacc_vf_f64m4_rm_mu(vbool16_t mask, vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfnmacc_mu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmacc_vv_f64m8_rm_mu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmacc.mask.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
//
vfloat64m8_t test_vfnmacc_vv_f64m8_rm_mu(vbool8_t mask, vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfnmacc_mu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmacc_vf_f64m8_rm_mu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmacc.mask.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
//
vfloat64m8_t test_vfnmacc_vf_f64m8_rm_mu(vbool8_t mask, vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfnmacc_mu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}

clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmadd.c

// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target // REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh \ // RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh \
// RUN: -target-feature +experimental-zvfh -disable-O0-optnone \ // RUN: -target-feature +experimental-zvfh -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ // RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s // RUN: FileCheck --check-prefix=CHECK-RV64 %s
#include <riscv_vector.h> #include <riscv_vector.h>
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmadd_vv_f16mf4_tu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmadd_vv_f16mf4_tu
// CHECK-RV64-SAME: (<vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK-RV64-SAME: (<vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmadd.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmadd.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
// //
vfloat16mf4_t test_vfnmadd_vv_f16mf4_tu(vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) { vfloat16mf4_t test_vfnmadd_vv_f16mf4_tu(vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfnmadd_tu(vd, vs1, vs2, vl); return __riscv_vfnmadd_tu(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmadd_vf_f16mf4_tu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmadd_vf_f16mf4_tu
// CHECK-RV64-SAME: (<vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmadd.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmadd.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
// //
vfloat16mf4_t test_vfnmadd_vf_f16mf4_tu(vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) { vfloat16mf4_t test_vfnmadd_vf_f16mf4_tu(vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfnmadd_tu(vd, rs1, vs2, vl); return __riscv_vfnmadd_tu(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmadd_vv_f16mf2_tu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmadd_vv_f16mf2_tu
// CHECK-RV64-SAME: (<vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmadd.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmadd.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
// //
vfloat16mf2_t test_vfnmadd_vv_f16mf2_tu(vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) { vfloat16mf2_t test_vfnmadd_vv_f16mf2_tu(vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfnmadd_tu(vd, vs1, vs2, vl); return __riscv_vfnmadd_tu(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmadd_vf_f16mf2_tu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmadd_vf_f16mf2_tu
// CHECK-RV64-SAME: (<vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmadd.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmadd.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
// //
vfloat16mf2_t test_vfnmadd_vf_f16mf2_tu(vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) { vfloat16mf2_t test_vfnmadd_vf_f16mf2_tu(vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfnmadd_tu(vd, rs1, vs2, vl); return __riscv_vfnmadd_tu(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmadd_vv_f16m1_tu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmadd_vv_f16m1_tu
// CHECK-RV64-SAME: (<vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmadd.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmadd.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
// //
vfloat16m1_t test_vfnmadd_vv_f16m1_tu(vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) { vfloat16m1_t test_vfnmadd_vv_f16m1_tu(vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfnmadd_tu(vd, vs1, vs2, vl); return __riscv_vfnmadd_tu(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmadd_vf_f16m1_tu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmadd_vf_f16m1_tu
// CHECK-RV64-SAME: (<vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmadd.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmadd.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
// //
vfloat16m1_t test_vfnmadd_vf_f16m1_tu(vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) { vfloat16m1_t test_vfnmadd_vf_f16m1_tu(vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfnmadd_tu(vd, rs1, vs2, vl); return __riscv_vfnmadd_tu(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmadd_vv_f16m2_tu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmadd_vv_f16m2_tu
// CHECK-RV64-SAME: (<vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmadd.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmadd.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
// //
vfloat16m2_t test_vfnmadd_vv_f16m2_tu(vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) { vfloat16m2_t test_vfnmadd_vv_f16m2_tu(vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfnmadd_tu(vd, vs1, vs2, vl); return __riscv_vfnmadd_tu(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmadd_vf_f16m2_tu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmadd_vf_f16m2_tu
// CHECK-RV64-SAME: (<vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmadd.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmadd.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
// //
vfloat16m2_t test_vfnmadd_vf_f16m2_tu(vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) { vfloat16m2_t test_vfnmadd_vf_f16m2_tu(vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfnmadd_tu(vd, rs1, vs2, vl); return __riscv_vfnmadd_tu(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmadd_vv_f16m4_tu // CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmadd_vv_f16m4_tu
// CHECK-RV64-SAME: (<vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmadd.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmadd.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
// //
vfloat16m4_t test_vfnmadd_vv_f16m4_tu(vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) { vfloat16m4_t test_vfnmadd_vv_f16m4_tu(vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfnmadd_tu(vd, vs1, vs2, vl); return __riscv_vfnmadd_tu(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmadd_vf_f16m4_tu // CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmadd_vf_f16m4_tu
// CHECK-RV64-SAME: (<vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmadd.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmadd.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
// //
vfloat16m4_t test_vfnmadd_vf_f16m4_tu(vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) { vfloat16m4_t test_vfnmadd_vf_f16m4_tu(vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfnmadd_tu(vd, rs1, vs2, vl); return __riscv_vfnmadd_tu(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmadd_vv_f16m8_tu // CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmadd_vv_f16m8_tu
// CHECK-RV64-SAME: (<vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmadd.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmadd.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
// //
vfloat16m8_t test_vfnmadd_vv_f16m8_tu(vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) { vfloat16m8_t test_vfnmadd_vv_f16m8_tu(vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfnmadd_tu(vd, vs1, vs2, vl); return __riscv_vfnmadd_tu(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmadd_vf_f16m8_tu // CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmadd_vf_f16m8_tu
// CHECK-RV64-SAME: (<vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmadd.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmadd.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
// //
vfloat16m8_t test_vfnmadd_vf_f16m8_tu(vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) { vfloat16m8_t test_vfnmadd_vf_f16m8_tu(vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfnmadd_tu(vd, rs1, vs2, vl); return __riscv_vfnmadd_tu(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmadd_vv_f32mf2_tu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmadd_vv_f32mf2_tu
// CHECK-RV64-SAME: (<vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmadd.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmadd.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfnmadd_vv_f32mf2_tu(vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) { vfloat32mf2_t test_vfnmadd_vv_f32mf2_tu(vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfnmadd_tu(vd, vs1, vs2, vl); return __riscv_vfnmadd_tu(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmadd_vf_f32mf2_tu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmadd_vf_f32mf2_tu
// CHECK-RV64-SAME: (<vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmadd.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmadd.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfnmadd_vf_f32mf2_tu(vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) { vfloat32mf2_t test_vfnmadd_vf_f32mf2_tu(vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfnmadd_tu(vd, rs1, vs2, vl); return __riscv_vfnmadd_tu(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmadd_vv_f32m1_tu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmadd_vv_f32m1_tu
// CHECK-RV64-SAME: (<vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmadd.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmadd.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfnmadd_vv_f32m1_tu(vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) { vfloat32m1_t test_vfnmadd_vv_f32m1_tu(vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfnmadd_tu(vd, vs1, vs2, vl); return __riscv_vfnmadd_tu(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmadd_vf_f32m1_tu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmadd_vf_f32m1_tu
// CHECK-RV64-SAME: (<vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmadd.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmadd.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfnmadd_vf_f32m1_tu(vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) { vfloat32m1_t test_vfnmadd_vf_f32m1_tu(vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfnmadd_tu(vd, rs1, vs2, vl); return __riscv_vfnmadd_tu(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmadd_vv_f32m2_tu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmadd_vv_f32m2_tu
// CHECK-RV64-SAME: (<vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmadd.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmadd.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfnmadd_vv_f32m2_tu(vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) { vfloat32m2_t test_vfnmadd_vv_f32m2_tu(vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfnmadd_tu(vd, vs1, vs2, vl); return __riscv_vfnmadd_tu(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmadd_vf_f32m2_tu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmadd_vf_f32m2_tu
// CHECK-RV64-SAME: (<vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmadd.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmadd.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfnmadd_vf_f32m2_tu(vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) { vfloat32m2_t test_vfnmadd_vf_f32m2_tu(vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfnmadd_tu(vd, rs1, vs2, vl); return __riscv_vfnmadd_tu(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmadd_vv_f32m4_tu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmadd_vv_f32m4_tu
// CHECK-RV64-SAME: (<vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmadd.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmadd.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfnmadd_vv_f32m4_tu(vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) { vfloat32m4_t test_vfnmadd_vv_f32m4_tu(vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfnmadd_tu(vd, vs1, vs2, vl); return __riscv_vfnmadd_tu(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmadd_vf_f32m4_tu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmadd_vf_f32m4_tu
// CHECK-RV64-SAME: (<vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmadd.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmadd.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfnmadd_vf_f32m4_tu(vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) { vfloat32m4_t test_vfnmadd_vf_f32m4_tu(vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfnmadd_tu(vd, rs1, vs2, vl); return __riscv_vfnmadd_tu(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmadd_vv_f32m8_tu // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmadd_vv_f32m8_tu
// CHECK-RV64-SAME: (<vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmadd.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmadd.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfnmadd_vv_f32m8_tu(vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) { vfloat32m8_t test_vfnmadd_vv_f32m8_tu(vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfnmadd_tu(vd, vs1, vs2, vl); return __riscv_vfnmadd_tu(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmadd_vf_f32m8_tu // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmadd_vf_f32m8_tu
// CHECK-RV64-SAME: (<vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmadd.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmadd.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfnmadd_vf_f32m8_tu(vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) { vfloat32m8_t test_vfnmadd_vf_f32m8_tu(vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfnmadd_tu(vd, rs1, vs2, vl); return __riscv_vfnmadd_tu(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmadd_vv_f64m1_tu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmadd_vv_f64m1_tu
// CHECK-RV64-SAME: (<vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmadd.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmadd.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfnmadd_vv_f64m1_tu(vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) { vfloat64m1_t test_vfnmadd_vv_f64m1_tu(vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfnmadd_tu(vd, vs1, vs2, vl); return __riscv_vfnmadd_tu(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmadd_vf_f64m1_tu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmadd_vf_f64m1_tu
// CHECK-RV64-SAME: (<vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmadd.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmadd.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfnmadd_vf_f64m1_tu(vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) { vfloat64m1_t test_vfnmadd_vf_f64m1_tu(vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfnmadd_tu(vd, rs1, vs2, vl); return __riscv_vfnmadd_tu(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmadd_vv_f64m2_tu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmadd_vv_f64m2_tu
// CHECK-RV64-SAME: (<vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmadd.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmadd.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfnmadd_vv_f64m2_tu(vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) { vfloat64m2_t test_vfnmadd_vv_f64m2_tu(vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfnmadd_tu(vd, vs1, vs2, vl); return __riscv_vfnmadd_tu(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmadd_vf_f64m2_tu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmadd_vf_f64m2_tu
// CHECK-RV64-SAME: (<vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmadd.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmadd.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfnmadd_vf_f64m2_tu(vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) { vfloat64m2_t test_vfnmadd_vf_f64m2_tu(vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfnmadd_tu(vd, rs1, vs2, vl); return __riscv_vfnmadd_tu(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmadd_vv_f64m4_tu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmadd_vv_f64m4_tu
// CHECK-RV64-SAME: (<vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmadd.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmadd.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfnmadd_vv_f64m4_tu(vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) { vfloat64m4_t test_vfnmadd_vv_f64m4_tu(vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfnmadd_tu(vd, vs1, vs2, vl); return __riscv_vfnmadd_tu(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmadd_vf_f64m4_tu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmadd_vf_f64m4_tu
// CHECK-RV64-SAME: (<vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmadd.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmadd.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfnmadd_vf_f64m4_tu(vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) { vfloat64m4_t test_vfnmadd_vf_f64m4_tu(vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfnmadd_tu(vd, rs1, vs2, vl); return __riscv_vfnmadd_tu(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmadd_vv_f64m8_tu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmadd_vv_f64m8_tu
// CHECK-RV64-SAME: (<vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmadd.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmadd.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfnmadd_vv_f64m8_tu(vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) { vfloat64m8_t test_vfnmadd_vv_f64m8_tu(vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfnmadd_tu(vd, vs1, vs2, vl); return __riscv_vfnmadd_tu(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmadd_vf_f64m8_tu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmadd_vf_f64m8_tu
// CHECK-RV64-SAME: (<vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmadd.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmadd.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfnmadd_vf_f64m8_tu(vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) { vfloat64m8_t test_vfnmadd_vf_f64m8_tu(vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfnmadd_tu(vd, rs1, vs2, vl); return __riscv_vfnmadd_tu(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmadd_vv_f16mf4_tum // CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmadd_vv_f16mf4_tum
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmadd.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmadd.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
// //
vfloat16mf4_t test_vfnmadd_vv_f16mf4_tum(vbool64_t mask, vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) { vfloat16mf4_t test_vfnmadd_vv_f16mf4_tum(vbool64_t mask, vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfnmadd_tum(mask, vd, vs1, vs2, vl); return __riscv_vfnmadd_tum(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmadd_vf_f16mf4_tum // CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmadd_vf_f16mf4_tum
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmadd.mask.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmadd.mask.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
// //
vfloat16mf4_t test_vfnmadd_vf_f16mf4_tum(vbool64_t mask, vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) { vfloat16mf4_t test_vfnmadd_vf_f16mf4_tum(vbool64_t mask, vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfnmadd_tum(mask, vd, rs1, vs2, vl); return __riscv_vfnmadd_tum(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmadd_vv_f16mf2_tum // CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmadd_vv_f16mf2_tum
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmadd.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmadd.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
// //
vfloat16mf2_t test_vfnmadd_vv_f16mf2_tum(vbool32_t mask, vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) { vfloat16mf2_t test_vfnmadd_vv_f16mf2_tum(vbool32_t mask, vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfnmadd_tum(mask, vd, vs1, vs2, vl); return __riscv_vfnmadd_tum(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmadd_vf_f16mf2_tum // CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmadd_vf_f16mf2_tum
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmadd.mask.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmadd.mask.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
// //
vfloat16mf2_t test_vfnmadd_vf_f16mf2_tum(vbool32_t mask, vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) { vfloat16mf2_t test_vfnmadd_vf_f16mf2_tum(vbool32_t mask, vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfnmadd_tum(mask, vd, rs1, vs2, vl); return __riscv_vfnmadd_tum(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmadd_vv_f16m1_tum // CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmadd_vv_f16m1_tum
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmadd.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmadd.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
// //
vfloat16m1_t test_vfnmadd_vv_f16m1_tum(vbool16_t mask, vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) { vfloat16m1_t test_vfnmadd_vv_f16m1_tum(vbool16_t mask, vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfnmadd_tum(mask, vd, vs1, vs2, vl); return __riscv_vfnmadd_tum(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmadd_vf_f16m1_tum // CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmadd_vf_f16m1_tum
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmadd.mask.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmadd.mask.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
// //
vfloat16m1_t test_vfnmadd_vf_f16m1_tum(vbool16_t mask, vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) { vfloat16m1_t test_vfnmadd_vf_f16m1_tum(vbool16_t mask, vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfnmadd_tum(mask, vd, rs1, vs2, vl); return __riscv_vfnmadd_tum(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmadd_vv_f16m2_tum // CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmadd_vv_f16m2_tum
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmadd.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmadd.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
// //
vfloat16m2_t test_vfnmadd_vv_f16m2_tum(vbool8_t mask, vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) { vfloat16m2_t test_vfnmadd_vv_f16m2_tum(vbool8_t mask, vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfnmadd_tum(mask, vd, vs1, vs2, vl); return __riscv_vfnmadd_tum(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmadd_vf_f16m2_tum // CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmadd_vf_f16m2_tum
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmadd.mask.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmadd.mask.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
// //
vfloat16m2_t test_vfnmadd_vf_f16m2_tum(vbool8_t mask, vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) { vfloat16m2_t test_vfnmadd_vf_f16m2_tum(vbool8_t mask, vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfnmadd_tum(mask, vd, rs1, vs2, vl); return __riscv_vfnmadd_tum(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmadd_vv_f16m4_tum // CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmadd_vv_f16m4_tum
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmadd.mask.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmadd.mask.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
// //
vfloat16m4_t test_vfnmadd_vv_f16m4_tum(vbool4_t mask, vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) { vfloat16m4_t test_vfnmadd_vv_f16m4_tum(vbool4_t mask, vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfnmadd_tum(mask, vd, vs1, vs2, vl); return __riscv_vfnmadd_tum(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmadd_vf_f16m4_tum // CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmadd_vf_f16m4_tum
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmadd.mask.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmadd.mask.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
// //
vfloat16m4_t test_vfnmadd_vf_f16m4_tum(vbool4_t mask, vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) { vfloat16m4_t test_vfnmadd_vf_f16m4_tum(vbool4_t mask, vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfnmadd_tum(mask, vd, rs1, vs2, vl); return __riscv_vfnmadd_tum(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmadd_vv_f16m8_tum // CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmadd_vv_f16m8_tum
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmadd.mask.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmadd.mask.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
// //
vfloat16m8_t test_vfnmadd_vv_f16m8_tum(vbool2_t mask, vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) { vfloat16m8_t test_vfnmadd_vv_f16m8_tum(vbool2_t mask, vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfnmadd_tum(mask, vd, vs1, vs2, vl); return __riscv_vfnmadd_tum(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmadd_vf_f16m8_tum // CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmadd_vf_f16m8_tum
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmadd.mask.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmadd.mask.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
// //
vfloat16m8_t test_vfnmadd_vf_f16m8_tum(vbool2_t mask, vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) { vfloat16m8_t test_vfnmadd_vf_f16m8_tum(vbool2_t mask, vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfnmadd_tum(mask, vd, rs1, vs2, vl); return __riscv_vfnmadd_tum(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmadd_vv_f32mf2_tum // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmadd_vv_f32mf2_tum
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmadd.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmadd.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfnmadd_vv_f32mf2_tum(vbool64_t mask, vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) { vfloat32mf2_t test_vfnmadd_vv_f32mf2_tum(vbool64_t mask, vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfnmadd_tum(mask, vd, vs1, vs2, vl); return __riscv_vfnmadd_tum(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmadd_vf_f32mf2_tum // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmadd_vf_f32mf2_tum
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmadd.mask.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmadd.mask.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfnmadd_vf_f32mf2_tum(vbool64_t mask, vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) { vfloat32mf2_t test_vfnmadd_vf_f32mf2_tum(vbool64_t mask, vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfnmadd_tum(mask, vd, rs1, vs2, vl); return __riscv_vfnmadd_tum(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmadd_vv_f32m1_tum // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmadd_vv_f32m1_tum
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmadd.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmadd.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfnmadd_vv_f32m1_tum(vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) { vfloat32m1_t test_vfnmadd_vv_f32m1_tum(vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfnmadd_tum(mask, vd, vs1, vs2, vl); return __riscv_vfnmadd_tum(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmadd_vf_f32m1_tum // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmadd_vf_f32m1_tum
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmadd.mask.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmadd.mask.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfnmadd_vf_f32m1_tum(vbool32_t mask, vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) { vfloat32m1_t test_vfnmadd_vf_f32m1_tum(vbool32_t mask, vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfnmadd_tum(mask, vd, rs1, vs2, vl); return __riscv_vfnmadd_tum(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmadd_vv_f32m2_tum // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmadd_vv_f32m2_tum
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmadd.mask.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmadd.mask.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfnmadd_vv_f32m2_tum(vbool16_t mask, vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) { vfloat32m2_t test_vfnmadd_vv_f32m2_tum(vbool16_t mask, vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfnmadd_tum(mask, vd, vs1, vs2, vl); return __riscv_vfnmadd_tum(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmadd_vf_f32m2_tum // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmadd_vf_f32m2_tum
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmadd.mask.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmadd.mask.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfnmadd_vf_f32m2_tum(vbool16_t mask, vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) { vfloat32m2_t test_vfnmadd_vf_f32m2_tum(vbool16_t mask, vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfnmadd_tum(mask, vd, rs1, vs2, vl); return __riscv_vfnmadd_tum(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmadd_vv_f32m4_tum // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmadd_vv_f32m4_tum
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmadd.mask.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmadd.mask.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfnmadd_vv_f32m4_tum(vbool8_t mask, vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) { vfloat32m4_t test_vfnmadd_vv_f32m4_tum(vbool8_t mask, vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfnmadd_tum(mask, vd, vs1, vs2, vl); return __riscv_vfnmadd_tum(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmadd_vf_f32m4_tum // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmadd_vf_f32m4_tum
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmadd.mask.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmadd.mask.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfnmadd_vf_f32m4_tum(vbool8_t mask, vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) { vfloat32m4_t test_vfnmadd_vf_f32m4_tum(vbool8_t mask, vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfnmadd_tum(mask, vd, rs1, vs2, vl); return __riscv_vfnmadd_tum(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmadd_vv_f32m8_tum // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmadd_vv_f32m8_tum
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmadd.mask.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmadd.mask.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfnmadd_vv_f32m8_tum(vbool4_t mask, vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) { vfloat32m8_t test_vfnmadd_vv_f32m8_tum(vbool4_t mask, vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfnmadd_tum(mask, vd, vs1, vs2, vl); return __riscv_vfnmadd_tum(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmadd_vf_f32m8_tum // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmadd_vf_f32m8_tum
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmadd.mask.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmadd.mask.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfnmadd_vf_f32m8_tum(vbool4_t mask, vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) { vfloat32m8_t test_vfnmadd_vf_f32m8_tum(vbool4_t mask, vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfnmadd_tum(mask, vd, rs1, vs2, vl); return __riscv_vfnmadd_tum(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmadd_vv_f64m1_tum // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmadd_vv_f64m1_tum
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmadd.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmadd.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfnmadd_vv_f64m1_tum(vbool64_t mask, vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) { vfloat64m1_t test_vfnmadd_vv_f64m1_tum(vbool64_t mask, vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfnmadd_tum(mask, vd, vs1, vs2, vl); return __riscv_vfnmadd_tum(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmadd_vf_f64m1_tum // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmadd_vf_f64m1_tum
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmadd.mask.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmadd.mask.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfnmadd_vf_f64m1_tum(vbool64_t mask, vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) { vfloat64m1_t test_vfnmadd_vf_f64m1_tum(vbool64_t mask, vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfnmadd_tum(mask, vd, rs1, vs2, vl); return __riscv_vfnmadd_tum(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmadd_vv_f64m2_tum // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmadd_vv_f64m2_tum
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmadd.mask.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmadd.mask.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfnmadd_vv_f64m2_tum(vbool32_t mask, vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) { vfloat64m2_t test_vfnmadd_vv_f64m2_tum(vbool32_t mask, vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfnmadd_tum(mask, vd, vs1, vs2, vl); return __riscv_vfnmadd_tum(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmadd_vf_f64m2_tum // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmadd_vf_f64m2_tum
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmadd.mask.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmadd.mask.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfnmadd_vf_f64m2_tum(vbool32_t mask, vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) { vfloat64m2_t test_vfnmadd_vf_f64m2_tum(vbool32_t mask, vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfnmadd_tum(mask, vd, rs1, vs2, vl); return __riscv_vfnmadd_tum(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmadd_vv_f64m4_tum // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmadd_vv_f64m4_tum
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmadd.mask.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmadd.mask.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfnmadd_vv_f64m4_tum(vbool16_t mask, vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) { vfloat64m4_t test_vfnmadd_vv_f64m4_tum(vbool16_t mask, vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfnmadd_tum(mask, vd, vs1, vs2, vl); return __riscv_vfnmadd_tum(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmadd_vf_f64m4_tum // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmadd_vf_f64m4_tum
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmadd.mask.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmadd.mask.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfnmadd_vf_f64m4_tum(vbool16_t mask, vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) { vfloat64m4_t test_vfnmadd_vf_f64m4_tum(vbool16_t mask, vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfnmadd_tum(mask, vd, rs1, vs2, vl); return __riscv_vfnmadd_tum(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmadd_vv_f64m8_tum // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmadd_vv_f64m8_tum
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmadd.mask.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmadd.mask.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfnmadd_vv_f64m8_tum(vbool8_t mask, vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) { vfloat64m8_t test_vfnmadd_vv_f64m8_tum(vbool8_t mask, vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfnmadd_tum(mask, vd, vs1, vs2, vl); return __riscv_vfnmadd_tum(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmadd_vf_f64m8_tum // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmadd_vf_f64m8_tum
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmadd.mask.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmadd.mask.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfnmadd_vf_f64m8_tum(vbool8_t mask, vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) { vfloat64m8_t test_vfnmadd_vf_f64m8_tum(vbool8_t mask, vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfnmadd_tum(mask, vd, rs1, vs2, vl); return __riscv_vfnmadd_tum(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmadd_vv_f16mf4_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmadd_vv_f16mf4_tumu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmadd.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmadd.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
// //
vfloat16mf4_t test_vfnmadd_vv_f16mf4_tumu(vbool64_t mask, vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) { vfloat16mf4_t test_vfnmadd_vv_f16mf4_tumu(vbool64_t mask, vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfnmadd_tumu(mask, vd, vs1, vs2, vl); return __riscv_vfnmadd_tumu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmadd_vf_f16mf4_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmadd_vf_f16mf4_tumu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmadd.mask.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmadd.mask.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
// //
vfloat16mf4_t test_vfnmadd_vf_f16mf4_tumu(vbool64_t mask, vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) { vfloat16mf4_t test_vfnmadd_vf_f16mf4_tumu(vbool64_t mask, vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfnmadd_tumu(mask, vd, rs1, vs2, vl); return __riscv_vfnmadd_tumu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmadd_vv_f16mf2_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmadd_vv_f16mf2_tumu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmadd.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmadd.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
// //
vfloat16mf2_t test_vfnmadd_vv_f16mf2_tumu(vbool32_t mask, vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) { vfloat16mf2_t test_vfnmadd_vv_f16mf2_tumu(vbool32_t mask, vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfnmadd_tumu(mask, vd, vs1, vs2, vl); return __riscv_vfnmadd_tumu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmadd_vf_f16mf2_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmadd_vf_f16mf2_tumu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmadd.mask.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmadd.mask.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
// //
vfloat16mf2_t test_vfnmadd_vf_f16mf2_tumu(vbool32_t mask, vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) { vfloat16mf2_t test_vfnmadd_vf_f16mf2_tumu(vbool32_t mask, vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfnmadd_tumu(mask, vd, rs1, vs2, vl); return __riscv_vfnmadd_tumu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmadd_vv_f16m1_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmadd_vv_f16m1_tumu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmadd.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmadd.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
// //
vfloat16m1_t test_vfnmadd_vv_f16m1_tumu(vbool16_t mask, vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) { vfloat16m1_t test_vfnmadd_vv_f16m1_tumu(vbool16_t mask, vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfnmadd_tumu(mask, vd, vs1, vs2, vl); return __riscv_vfnmadd_tumu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmadd_vf_f16m1_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmadd_vf_f16m1_tumu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmadd.mask.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmadd.mask.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
// //
vfloat16m1_t test_vfnmadd_vf_f16m1_tumu(vbool16_t mask, vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) { vfloat16m1_t test_vfnmadd_vf_f16m1_tumu(vbool16_t mask, vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfnmadd_tumu(mask, vd, rs1, vs2, vl); return __riscv_vfnmadd_tumu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmadd_vv_f16m2_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmadd_vv_f16m2_tumu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmadd.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmadd.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
// //
vfloat16m2_t test_vfnmadd_vv_f16m2_tumu(vbool8_t mask, vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) { vfloat16m2_t test_vfnmadd_vv_f16m2_tumu(vbool8_t mask, vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfnmadd_tumu(mask, vd, vs1, vs2, vl); return __riscv_vfnmadd_tumu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmadd_vf_f16m2_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmadd_vf_f16m2_tumu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmadd.mask.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmadd.mask.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
// //
vfloat16m2_t test_vfnmadd_vf_f16m2_tumu(vbool8_t mask, vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) { vfloat16m2_t test_vfnmadd_vf_f16m2_tumu(vbool8_t mask, vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfnmadd_tumu(mask, vd, rs1, vs2, vl); return __riscv_vfnmadd_tumu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmadd_vv_f16m4_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmadd_vv_f16m4_tumu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmadd.mask.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmadd.mask.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
// //
vfloat16m4_t test_vfnmadd_vv_f16m4_tumu(vbool4_t mask, vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) { vfloat16m4_t test_vfnmadd_vv_f16m4_tumu(vbool4_t mask, vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfnmadd_tumu(mask, vd, vs1, vs2, vl); return __riscv_vfnmadd_tumu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmadd_vf_f16m4_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmadd_vf_f16m4_tumu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmadd.mask.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmadd.mask.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
// //
vfloat16m4_t test_vfnmadd_vf_f16m4_tumu(vbool4_t mask, vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) { vfloat16m4_t test_vfnmadd_vf_f16m4_tumu(vbool4_t mask, vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfnmadd_tumu(mask, vd, rs1, vs2, vl); return __riscv_vfnmadd_tumu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmadd_vv_f16m8_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmadd_vv_f16m8_tumu
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmadd.mask.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmadd.mask.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
// //
vfloat16m8_t test_vfnmadd_vv_f16m8_tumu(vbool2_t mask, vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) { vfloat16m8_t test_vfnmadd_vv_f16m8_tumu(vbool2_t mask, vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfnmadd_tumu(mask, vd, vs1, vs2, vl); return __riscv_vfnmadd_tumu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmadd_vf_f16m8_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmadd_vf_f16m8_tumu
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmadd.mask.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmadd.mask.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
// //
vfloat16m8_t test_vfnmadd_vf_f16m8_tumu(vbool2_t mask, vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) { vfloat16m8_t test_vfnmadd_vf_f16m8_tumu(vbool2_t mask, vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfnmadd_tumu(mask, vd, rs1, vs2, vl); return __riscv_vfnmadd_tumu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmadd_vv_f32mf2_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmadd_vv_f32mf2_tumu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmadd.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmadd.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfnmadd_vv_f32mf2_tumu(vbool64_t mask, vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) { vfloat32mf2_t test_vfnmadd_vv_f32mf2_tumu(vbool64_t mask, vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfnmadd_tumu(mask, vd, vs1, vs2, vl); return __riscv_vfnmadd_tumu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmadd_vf_f32mf2_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmadd_vf_f32mf2_tumu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmadd.mask.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmadd.mask.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfnmadd_vf_f32mf2_tumu(vbool64_t mask, vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) { vfloat32mf2_t test_vfnmadd_vf_f32mf2_tumu(vbool64_t mask, vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfnmadd_tumu(mask, vd, rs1, vs2, vl); return __riscv_vfnmadd_tumu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmadd_vv_f32m1_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmadd_vv_f32m1_tumu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmadd.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmadd.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfnmadd_vv_f32m1_tumu(vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) { vfloat32m1_t test_vfnmadd_vv_f32m1_tumu(vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfnmadd_tumu(mask, vd, vs1, vs2, vl); return __riscv_vfnmadd_tumu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmadd_vf_f32m1_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmadd_vf_f32m1_tumu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmadd.mask.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmadd.mask.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfnmadd_vf_f32m1_tumu(vbool32_t mask, vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) { vfloat32m1_t test_vfnmadd_vf_f32m1_tumu(vbool32_t mask, vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfnmadd_tumu(mask, vd, rs1, vs2, vl); return __riscv_vfnmadd_tumu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmadd_vv_f32m2_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmadd_vv_f32m2_tumu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmadd.mask.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmadd.mask.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfnmadd_vv_f32m2_tumu(vbool16_t mask, vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) { vfloat32m2_t test_vfnmadd_vv_f32m2_tumu(vbool16_t mask, vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfnmadd_tumu(mask, vd, vs1, vs2, vl); return __riscv_vfnmadd_tumu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmadd_vf_f32m2_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmadd_vf_f32m2_tumu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmadd.mask.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmadd.mask.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfnmadd_vf_f32m2_tumu(vbool16_t mask, vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) { vfloat32m2_t test_vfnmadd_vf_f32m2_tumu(vbool16_t mask, vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfnmadd_tumu(mask, vd, rs1, vs2, vl); return __riscv_vfnmadd_tumu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmadd_vv_f32m4_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmadd_vv_f32m4_tumu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmadd.mask.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmadd.mask.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfnmadd_vv_f32m4_tumu(vbool8_t mask, vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) { vfloat32m4_t test_vfnmadd_vv_f32m4_tumu(vbool8_t mask, vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfnmadd_tumu(mask, vd, vs1, vs2, vl); return __riscv_vfnmadd_tumu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmadd_vf_f32m4_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmadd_vf_f32m4_tumu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmadd.mask.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmadd.mask.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfnmadd_vf_f32m4_tumu(vbool8_t mask, vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) { vfloat32m4_t test_vfnmadd_vf_f32m4_tumu(vbool8_t mask, vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfnmadd_tumu(mask, vd, rs1, vs2, vl); return __riscv_vfnmadd_tumu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmadd_vv_f32m8_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmadd_vv_f32m8_tumu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmadd.mask.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmadd.mask.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfnmadd_vv_f32m8_tumu(vbool4_t mask, vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) { vfloat32m8_t test_vfnmadd_vv_f32m8_tumu(vbool4_t mask, vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfnmadd_tumu(mask, vd, vs1, vs2, vl); return __riscv_vfnmadd_tumu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmadd_vf_f32m8_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmadd_vf_f32m8_tumu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmadd.mask.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmadd.mask.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfnmadd_vf_f32m8_tumu(vbool4_t mask, vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) { vfloat32m8_t test_vfnmadd_vf_f32m8_tumu(vbool4_t mask, vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfnmadd_tumu(mask, vd, rs1, vs2, vl); return __riscv_vfnmadd_tumu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmadd_vv_f64m1_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmadd_vv_f64m1_tumu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmadd.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmadd.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfnmadd_vv_f64m1_tumu(vbool64_t mask, vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) { vfloat64m1_t test_vfnmadd_vv_f64m1_tumu(vbool64_t mask, vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfnmadd_tumu(mask, vd, vs1, vs2, vl); return __riscv_vfnmadd_tumu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmadd_vf_f64m1_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmadd_vf_f64m1_tumu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmadd.mask.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmadd.mask.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfnmadd_vf_f64m1_tumu(vbool64_t mask, vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) { vfloat64m1_t test_vfnmadd_vf_f64m1_tumu(vbool64_t mask, vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfnmadd_tumu(mask, vd, rs1, vs2, vl); return __riscv_vfnmadd_tumu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmadd_vv_f64m2_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmadd_vv_f64m2_tumu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmadd.mask.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmadd.mask.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfnmadd_vv_f64m2_tumu(vbool32_t mask, vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) { vfloat64m2_t test_vfnmadd_vv_f64m2_tumu(vbool32_t mask, vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfnmadd_tumu(mask, vd, vs1, vs2, vl); return __riscv_vfnmadd_tumu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmadd_vf_f64m2_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmadd_vf_f64m2_tumu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmadd.mask.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmadd.mask.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfnmadd_vf_f64m2_tumu(vbool32_t mask, vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) { vfloat64m2_t test_vfnmadd_vf_f64m2_tumu(vbool32_t mask, vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfnmadd_tumu(mask, vd, rs1, vs2, vl); return __riscv_vfnmadd_tumu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmadd_vv_f64m4_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmadd_vv_f64m4_tumu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmadd.mask.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmadd.mask.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfnmadd_vv_f64m4_tumu(vbool16_t mask, vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) { vfloat64m4_t test_vfnmadd_vv_f64m4_tumu(vbool16_t mask, vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfnmadd_tumu(mask, vd, vs1, vs2, vl); return __riscv_vfnmadd_tumu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmadd_vf_f64m4_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmadd_vf_f64m4_tumu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmadd.mask.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmadd.mask.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfnmadd_vf_f64m4_tumu(vbool16_t mask, vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) { vfloat64m4_t test_vfnmadd_vf_f64m4_tumu(vbool16_t mask, vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfnmadd_tumu(mask, vd, rs1, vs2, vl); return __riscv_vfnmadd_tumu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmadd_vv_f64m8_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmadd_vv_f64m8_tumu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmadd.mask.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmadd.mask.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfnmadd_vv_f64m8_tumu(vbool8_t mask, vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) { vfloat64m8_t test_vfnmadd_vv_f64m8_tumu(vbool8_t mask, vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfnmadd_tumu(mask, vd, vs1, vs2, vl); return __riscv_vfnmadd_tumu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmadd_vf_f64m8_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmadd_vf_f64m8_tumu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmadd.mask.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmadd.mask.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfnmadd_vf_f64m8_tumu(vbool8_t mask, vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) { vfloat64m8_t test_vfnmadd_vf_f64m8_tumu(vbool8_t mask, vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfnmadd_tumu(mask, vd, rs1, vs2, vl); return __riscv_vfnmadd_tumu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmadd_vv_f16mf4_mu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmadd_vv_f16mf4_mu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmadd.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmadd.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
// //
vfloat16mf4_t test_vfnmadd_vv_f16mf4_mu(vbool64_t mask, vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) { vfloat16mf4_t test_vfnmadd_vv_f16mf4_mu(vbool64_t mask, vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfnmadd_mu(mask, vd, vs1, vs2, vl); return __riscv_vfnmadd_mu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmadd_vf_f16mf4_mu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmadd_vf_f16mf4_mu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmadd.mask.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmadd.mask.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
// //
vfloat16mf4_t test_vfnmadd_vf_f16mf4_mu(vbool64_t mask, vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) { vfloat16mf4_t test_vfnmadd_vf_f16mf4_mu(vbool64_t mask, vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfnmadd_mu(mask, vd, rs1, vs2, vl); return __riscv_vfnmadd_mu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmadd_vv_f16mf2_mu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmadd_vv_f16mf2_mu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmadd.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmadd.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
// //
vfloat16mf2_t test_vfnmadd_vv_f16mf2_mu(vbool32_t mask, vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) { vfloat16mf2_t test_vfnmadd_vv_f16mf2_mu(vbool32_t mask, vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfnmadd_mu(mask, vd, vs1, vs2, vl); return __riscv_vfnmadd_mu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmadd_vf_f16mf2_mu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmadd_vf_f16mf2_mu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmadd.mask.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmadd.mask.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
// //
vfloat16mf2_t test_vfnmadd_vf_f16mf2_mu(vbool32_t mask, vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) { vfloat16mf2_t test_vfnmadd_vf_f16mf2_mu(vbool32_t mask, vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfnmadd_mu(mask, vd, rs1, vs2, vl); return __riscv_vfnmadd_mu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmadd_vv_f16m1_mu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmadd_vv_f16m1_mu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmadd.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmadd.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
// //
vfloat16m1_t test_vfnmadd_vv_f16m1_mu(vbool16_t mask, vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) { vfloat16m1_t test_vfnmadd_vv_f16m1_mu(vbool16_t mask, vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfnmadd_mu(mask, vd, vs1, vs2, vl); return __riscv_vfnmadd_mu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmadd_vf_f16m1_mu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmadd_vf_f16m1_mu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmadd.mask.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmadd.mask.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
// //
vfloat16m1_t test_vfnmadd_vf_f16m1_mu(vbool16_t mask, vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) { vfloat16m1_t test_vfnmadd_vf_f16m1_mu(vbool16_t mask, vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfnmadd_mu(mask, vd, rs1, vs2, vl); return __riscv_vfnmadd_mu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmadd_vv_f16m2_mu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmadd_vv_f16m2_mu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmadd.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmadd.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
// //
vfloat16m2_t test_vfnmadd_vv_f16m2_mu(vbool8_t mask, vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) { vfloat16m2_t test_vfnmadd_vv_f16m2_mu(vbool8_t mask, vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfnmadd_mu(mask, vd, vs1, vs2, vl); return __riscv_vfnmadd_mu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmadd_vf_f16m2_mu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmadd_vf_f16m2_mu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmadd.mask.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmadd.mask.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
// //
vfloat16m2_t test_vfnmadd_vf_f16m2_mu(vbool8_t mask, vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) { vfloat16m2_t test_vfnmadd_vf_f16m2_mu(vbool8_t mask, vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfnmadd_mu(mask, vd, rs1, vs2, vl); return __riscv_vfnmadd_mu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmadd_vv_f16m4_mu // CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmadd_vv_f16m4_mu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmadd.mask.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmadd.mask.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
// //
vfloat16m4_t test_vfnmadd_vv_f16m4_mu(vbool4_t mask, vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) { vfloat16m4_t test_vfnmadd_vv_f16m4_mu(vbool4_t mask, vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfnmadd_mu(mask, vd, vs1, vs2, vl); return __riscv_vfnmadd_mu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmadd_vf_f16m4_mu // CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmadd_vf_f16m4_mu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmadd.mask.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmadd.mask.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
// //
vfloat16m4_t test_vfnmadd_vf_f16m4_mu(vbool4_t mask, vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) { vfloat16m4_t test_vfnmadd_vf_f16m4_mu(vbool4_t mask, vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfnmadd_mu(mask, vd, rs1, vs2, vl); return __riscv_vfnmadd_mu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmadd_vv_f16m8_mu // CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmadd_vv_f16m8_mu
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmadd.mask.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmadd.mask.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
// //
vfloat16m8_t test_vfnmadd_vv_f16m8_mu(vbool2_t mask, vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) { vfloat16m8_t test_vfnmadd_vv_f16m8_mu(vbool2_t mask, vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfnmadd_mu(mask, vd, vs1, vs2, vl); return __riscv_vfnmadd_mu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmadd_vf_f16m8_mu // CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmadd_vf_f16m8_mu
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmadd.mask.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmadd.mask.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
// //
vfloat16m8_t test_vfnmadd_vf_f16m8_mu(vbool2_t mask, vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) { vfloat16m8_t test_vfnmadd_vf_f16m8_mu(vbool2_t mask, vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfnmadd_mu(mask, vd, rs1, vs2, vl); return __riscv_vfnmadd_mu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmadd_vv_f32mf2_mu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmadd_vv_f32mf2_mu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmadd.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmadd.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfnmadd_vv_f32mf2_mu(vbool64_t mask, vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) { vfloat32mf2_t test_vfnmadd_vv_f32mf2_mu(vbool64_t mask, vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfnmadd_mu(mask, vd, vs1, vs2, vl); return __riscv_vfnmadd_mu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmadd_vf_f32mf2_mu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmadd_vf_f32mf2_mu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmadd.mask.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmadd.mask.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfnmadd_vf_f32mf2_mu(vbool64_t mask, vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) { vfloat32mf2_t test_vfnmadd_vf_f32mf2_mu(vbool64_t mask, vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfnmadd_mu(mask, vd, rs1, vs2, vl); return __riscv_vfnmadd_mu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmadd_vv_f32m1_mu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmadd_vv_f32m1_mu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmadd.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmadd.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfnmadd_vv_f32m1_mu(vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) { vfloat32m1_t test_vfnmadd_vv_f32m1_mu(vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfnmadd_mu(mask, vd, vs1, vs2, vl); return __riscv_vfnmadd_mu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmadd_vf_f32m1_mu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmadd_vf_f32m1_mu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmadd.mask.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmadd.mask.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfnmadd_vf_f32m1_mu(vbool32_t mask, vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) { vfloat32m1_t test_vfnmadd_vf_f32m1_mu(vbool32_t mask, vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfnmadd_mu(mask, vd, rs1, vs2, vl); return __riscv_vfnmadd_mu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmadd_vv_f32m2_mu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmadd_vv_f32m2_mu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmadd.mask.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmadd.mask.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfnmadd_vv_f32m2_mu(vbool16_t mask, vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) { vfloat32m2_t test_vfnmadd_vv_f32m2_mu(vbool16_t mask, vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfnmadd_mu(mask, vd, vs1, vs2, vl); return __riscv_vfnmadd_mu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmadd_vf_f32m2_mu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmadd_vf_f32m2_mu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmadd.mask.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmadd.mask.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfnmadd_vf_f32m2_mu(vbool16_t mask, vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) { vfloat32m2_t test_vfnmadd_vf_f32m2_mu(vbool16_t mask, vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfnmadd_mu(mask, vd, rs1, vs2, vl); return __riscv_vfnmadd_mu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmadd_vv_f32m4_mu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmadd_vv_f32m4_mu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmadd.mask.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmadd.mask.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfnmadd_vv_f32m4_mu(vbool8_t mask, vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) { vfloat32m4_t test_vfnmadd_vv_f32m4_mu(vbool8_t mask, vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfnmadd_mu(mask, vd, vs1, vs2, vl); return __riscv_vfnmadd_mu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmadd_vf_f32m4_mu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmadd_vf_f32m4_mu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmadd.mask.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmadd.mask.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfnmadd_vf_f32m4_mu(vbool8_t mask, vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) { vfloat32m4_t test_vfnmadd_vf_f32m4_mu(vbool8_t mask, vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfnmadd_mu(mask, vd, rs1, vs2, vl); return __riscv_vfnmadd_mu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmadd_vv_f32m8_mu // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmadd_vv_f32m8_mu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmadd.mask.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmadd.mask.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfnmadd_vv_f32m8_mu(vbool4_t mask, vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) { vfloat32m8_t test_vfnmadd_vv_f32m8_mu(vbool4_t mask, vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfnmadd_mu(mask, vd, vs1, vs2, vl); return __riscv_vfnmadd_mu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmadd_vf_f32m8_mu // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmadd_vf_f32m8_mu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmadd.mask.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmadd.mask.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfnmadd_vf_f32m8_mu(vbool4_t mask, vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) { vfloat32m8_t test_vfnmadd_vf_f32m8_mu(vbool4_t mask, vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfnmadd_mu(mask, vd, rs1, vs2, vl); return __riscv_vfnmadd_mu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmadd_vv_f64m1_mu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmadd_vv_f64m1_mu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmadd.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmadd.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfnmadd_vv_f64m1_mu(vbool64_t mask, vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) { vfloat64m1_t test_vfnmadd_vv_f64m1_mu(vbool64_t mask, vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfnmadd_mu(mask, vd, vs1, vs2, vl); return __riscv_vfnmadd_mu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmadd_vf_f64m1_mu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmadd_vf_f64m1_mu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmadd.mask.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmadd.mask.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfnmadd_vf_f64m1_mu(vbool64_t mask, vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) { vfloat64m1_t test_vfnmadd_vf_f64m1_mu(vbool64_t mask, vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfnmadd_mu(mask, vd, rs1, vs2, vl); return __riscv_vfnmadd_mu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmadd_vv_f64m2_mu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmadd_vv_f64m2_mu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmadd.mask.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmadd.mask.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfnmadd_vv_f64m2_mu(vbool32_t mask, vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) { vfloat64m2_t test_vfnmadd_vv_f64m2_mu(vbool32_t mask, vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfnmadd_mu(mask, vd, vs1, vs2, vl); return __riscv_vfnmadd_mu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmadd_vf_f64m2_mu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmadd_vf_f64m2_mu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmadd.mask.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmadd.mask.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfnmadd_vf_f64m2_mu(vbool32_t mask, vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) { vfloat64m2_t test_vfnmadd_vf_f64m2_mu(vbool32_t mask, vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfnmadd_mu(mask, vd, rs1, vs2, vl); return __riscv_vfnmadd_mu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmadd_vv_f64m4_mu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmadd_vv_f64m4_mu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmadd.mask.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmadd.mask.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfnmadd_vv_f64m4_mu(vbool16_t mask, vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) { vfloat64m4_t test_vfnmadd_vv_f64m4_mu(vbool16_t mask, vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfnmadd_mu(mask, vd, vs1, vs2, vl); return __riscv_vfnmadd_mu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmadd_vf_f64m4_mu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmadd_vf_f64m4_mu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmadd.mask.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmadd.mask.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfnmadd_vf_f64m4_mu(vbool16_t mask, vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) { vfloat64m4_t test_vfnmadd_vf_f64m4_mu(vbool16_t mask, vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfnmadd_mu(mask, vd, rs1, vs2, vl); return __riscv_vfnmadd_mu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmadd_vv_f64m8_mu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmadd_vv_f64m8_mu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmadd.mask.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmadd.mask.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfnmadd_vv_f64m8_mu(vbool8_t mask, vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) { vfloat64m8_t test_vfnmadd_vv_f64m8_mu(vbool8_t mask, vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfnmadd_mu(mask, vd, vs1, vs2, vl); return __riscv_vfnmadd_mu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmadd_vf_f64m8_mu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmadd_vf_f64m8_mu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmadd.mask.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmadd.mask.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfnmadd_vf_f64m8_mu(vbool8_t mask, vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) { vfloat64m8_t test_vfnmadd_vf_f64m8_mu(vbool8_t mask, vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfnmadd_mu(mask, vd, rs1, vs2, vl); return __riscv_vfnmadd_mu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmadd_vv_f16mf4_rm_tu
// CHECK-RV64-SAME: (<vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmadd.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
//
vfloat16mf4_t test_vfnmadd_vv_f16mf4_rm_tu(vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfnmadd_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmadd_vf_f16mf4_rm_tu
// CHECK-RV64-SAME: (<vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmadd.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
//
vfloat16mf4_t test_vfnmadd_vf_f16mf4_rm_tu(vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfnmadd_tu(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmadd_vv_f16mf2_rm_tu
// CHECK-RV64-SAME: (<vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmadd.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
//
vfloat16mf2_t test_vfnmadd_vv_f16mf2_rm_tu(vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfnmadd_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmadd_vf_f16mf2_rm_tu
// CHECK-RV64-SAME: (<vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmadd.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
//
vfloat16mf2_t test_vfnmadd_vf_f16mf2_rm_tu(vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfnmadd_tu(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmadd_vv_f16m1_rm_tu
// CHECK-RV64-SAME: (<vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmadd.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfnmadd_vv_f16m1_rm_tu(vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfnmadd_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmadd_vf_f16m1_rm_tu
// CHECK-RV64-SAME: (<vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmadd.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfnmadd_vf_f16m1_rm_tu(vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfnmadd_tu(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmadd_vv_f16m2_rm_tu
// CHECK-RV64-SAME: (<vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmadd.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
//
vfloat16m2_t test_vfnmadd_vv_f16m2_rm_tu(vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfnmadd_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmadd_vf_f16m2_rm_tu
// CHECK-RV64-SAME: (<vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmadd.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
//
vfloat16m2_t test_vfnmadd_vf_f16m2_rm_tu(vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfnmadd_tu(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmadd_vv_f16m4_rm_tu
// CHECK-RV64-SAME: (<vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmadd.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
//
vfloat16m4_t test_vfnmadd_vv_f16m4_rm_tu(vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfnmadd_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmadd_vf_f16m4_rm_tu
// CHECK-RV64-SAME: (<vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmadd.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
//
vfloat16m4_t test_vfnmadd_vf_f16m4_rm_tu(vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfnmadd_tu(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmadd_vv_f16m8_rm_tu
// CHECK-RV64-SAME: (<vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmadd.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
//
vfloat16m8_t test_vfnmadd_vv_f16m8_rm_tu(vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfnmadd_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmadd_vf_f16m8_rm_tu
// CHECK-RV64-SAME: (<vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmadd.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
//
vfloat16m8_t test_vfnmadd_vf_f16m8_rm_tu(vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfnmadd_tu(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmadd_vv_f32mf2_rm_tu
// CHECK-RV64-SAME: (<vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmadd.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
//
vfloat32mf2_t test_vfnmadd_vv_f32mf2_rm_tu(vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfnmadd_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmadd_vf_f32mf2_rm_tu
// CHECK-RV64-SAME: (<vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmadd.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
//
vfloat32mf2_t test_vfnmadd_vf_f32mf2_rm_tu(vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfnmadd_tu(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmadd_vv_f32m1_rm_tu
// CHECK-RV64-SAME: (<vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmadd.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfnmadd_vv_f32m1_rm_tu(vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfnmadd_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmadd_vf_f32m1_rm_tu
// CHECK-RV64-SAME: (<vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmadd.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfnmadd_vf_f32m1_rm_tu(vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfnmadd_tu(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmadd_vv_f32m2_rm_tu
// CHECK-RV64-SAME: (<vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmadd.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
//
vfloat32m2_t test_vfnmadd_vv_f32m2_rm_tu(vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfnmadd_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmadd_vf_f32m2_rm_tu
// CHECK-RV64-SAME: (<vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmadd.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
//
vfloat32m2_t test_vfnmadd_vf_f32m2_rm_tu(vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfnmadd_tu(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmadd_vv_f32m4_rm_tu
// CHECK-RV64-SAME: (<vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmadd.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
//
vfloat32m4_t test_vfnmadd_vv_f32m4_rm_tu(vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfnmadd_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmadd_vf_f32m4_rm_tu
// CHECK-RV64-SAME: (<vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmadd.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
//
vfloat32m4_t test_vfnmadd_vf_f32m4_rm_tu(vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfnmadd_tu(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmadd_vv_f32m8_rm_tu
// CHECK-RV64-SAME: (<vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmadd.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
//
vfloat32m8_t test_vfnmadd_vv_f32m8_rm_tu(vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfnmadd_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmadd_vf_f32m8_rm_tu
// CHECK-RV64-SAME: (<vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmadd.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
//
vfloat32m8_t test_vfnmadd_vf_f32m8_rm_tu(vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfnmadd_tu(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmadd_vv_f64m1_rm_tu
// CHECK-RV64-SAME: (<vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmadd.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfnmadd_vv_f64m1_rm_tu(vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfnmadd_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmadd_vf_f64m1_rm_tu
// CHECK-RV64-SAME: (<vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmadd.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfnmadd_vf_f64m1_rm_tu(vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfnmadd_tu(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmadd_vv_f64m2_rm_tu
// CHECK-RV64-SAME: (<vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmadd.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
//
vfloat64m2_t test_vfnmadd_vv_f64m2_rm_tu(vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfnmadd_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmadd_vf_f64m2_rm_tu
// CHECK-RV64-SAME: (<vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmadd.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
//
vfloat64m2_t test_vfnmadd_vf_f64m2_rm_tu(vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfnmadd_tu(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmadd_vv_f64m4_rm_tu
// CHECK-RV64-SAME: (<vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmadd.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
//
vfloat64m4_t test_vfnmadd_vv_f64m4_rm_tu(vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfnmadd_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmadd_vf_f64m4_rm_tu
// CHECK-RV64-SAME: (<vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmadd.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
//
vfloat64m4_t test_vfnmadd_vf_f64m4_rm_tu(vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfnmadd_tu(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmadd_vv_f64m8_rm_tu
// CHECK-RV64-SAME: (<vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmadd.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
//
vfloat64m8_t test_vfnmadd_vv_f64m8_rm_tu(vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfnmadd_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmadd_vf_f64m8_rm_tu
// CHECK-RV64-SAME: (<vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmadd.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
//
vfloat64m8_t test_vfnmadd_vf_f64m8_rm_tu(vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfnmadd_tu(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmadd_vv_f16mf4_rm_tum
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmadd.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
//
vfloat16mf4_t test_vfnmadd_vv_f16mf4_rm_tum(vbool64_t mask, vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfnmadd_tum(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmadd_vf_f16mf4_rm_tum
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmadd.mask.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
//
vfloat16mf4_t test_vfnmadd_vf_f16mf4_rm_tum(vbool64_t mask, vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfnmadd_tum(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmadd_vv_f16mf2_rm_tum
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmadd.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
//
vfloat16mf2_t test_vfnmadd_vv_f16mf2_rm_tum(vbool32_t mask, vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfnmadd_tum(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmadd_vf_f16mf2_rm_tum
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmadd.mask.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
//
vfloat16mf2_t test_vfnmadd_vf_f16mf2_rm_tum(vbool32_t mask, vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfnmadd_tum(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmadd_vv_f16m1_rm_tum
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmadd.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfnmadd_vv_f16m1_rm_tum(vbool16_t mask, vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfnmadd_tum(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmadd_vf_f16m1_rm_tum
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmadd.mask.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfnmadd_vf_f16m1_rm_tum(vbool16_t mask, vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfnmadd_tum(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmadd_vv_f16m2_rm_tum
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmadd.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
//
vfloat16m2_t test_vfnmadd_vv_f16m2_rm_tum(vbool8_t mask, vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfnmadd_tum(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmadd_vf_f16m2_rm_tum
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmadd.mask.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
//
vfloat16m2_t test_vfnmadd_vf_f16m2_rm_tum(vbool8_t mask, vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfnmadd_tum(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmadd_vv_f16m4_rm_tum
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmadd.mask.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
//
vfloat16m4_t test_vfnmadd_vv_f16m4_rm_tum(vbool4_t mask, vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfnmadd_tum(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmadd_vf_f16m4_rm_tum
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmadd.mask.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
//
vfloat16m4_t test_vfnmadd_vf_f16m4_rm_tum(vbool4_t mask, vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfnmadd_tum(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmadd_vv_f16m8_rm_tum
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmadd.mask.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
//
vfloat16m8_t test_vfnmadd_vv_f16m8_rm_tum(vbool2_t mask, vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfnmadd_tum(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmadd_vf_f16m8_rm_tum
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmadd.mask.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
//
vfloat16m8_t test_vfnmadd_vf_f16m8_rm_tum(vbool2_t mask, vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfnmadd_tum(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmadd_vv_f32mf2_rm_tum
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmadd.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
//
vfloat32mf2_t test_vfnmadd_vv_f32mf2_rm_tum(vbool64_t mask, vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfnmadd_tum(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmadd_vf_f32mf2_rm_tum
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmadd.mask.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
//
vfloat32mf2_t test_vfnmadd_vf_f32mf2_rm_tum(vbool64_t mask, vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfnmadd_tum(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmadd_vv_f32m1_rm_tum
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmadd.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfnmadd_vv_f32m1_rm_tum(vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfnmadd_tum(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmadd_vf_f32m1_rm_tum
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmadd.mask.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfnmadd_vf_f32m1_rm_tum(vbool32_t mask, vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfnmadd_tum(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmadd_vv_f32m2_rm_tum
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmadd.mask.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
//
vfloat32m2_t test_vfnmadd_vv_f32m2_rm_tum(vbool16_t mask, vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfnmadd_tum(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmadd_vf_f32m2_rm_tum
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmadd.mask.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
//
vfloat32m2_t test_vfnmadd_vf_f32m2_rm_tum(vbool16_t mask, vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfnmadd_tum(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmadd_vv_f32m4_rm_tum
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmadd.mask.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
//
vfloat32m4_t test_vfnmadd_vv_f32m4_rm_tum(vbool8_t mask, vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfnmadd_tum(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmadd_vf_f32m4_rm_tum
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmadd.mask.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
//
vfloat32m4_t test_vfnmadd_vf_f32m4_rm_tum(vbool8_t mask, vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfnmadd_tum(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmadd_vv_f32m8_rm_tum
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmadd.mask.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
//
vfloat32m8_t test_vfnmadd_vv_f32m8_rm_tum(vbool4_t mask, vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfnmadd_tum(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmadd_vf_f32m8_rm_tum
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmadd.mask.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
//
vfloat32m8_t test_vfnmadd_vf_f32m8_rm_tum(vbool4_t mask, vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfnmadd_tum(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmadd_vv_f64m1_rm_tum
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmadd.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfnmadd_vv_f64m1_rm_tum(vbool64_t mask, vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfnmadd_tum(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmadd_vf_f64m1_rm_tum
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmadd.mask.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfnmadd_vf_f64m1_rm_tum(vbool64_t mask, vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfnmadd_tum(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmadd_vv_f64m2_rm_tum
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmadd.mask.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
//
vfloat64m2_t test_vfnmadd_vv_f64m2_rm_tum(vbool32_t mask, vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfnmadd_tum(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmadd_vf_f64m2_rm_tum
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmadd.mask.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
//
vfloat64m2_t test_vfnmadd_vf_f64m2_rm_tum(vbool32_t mask, vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfnmadd_tum(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmadd_vv_f64m4_rm_tum
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmadd.mask.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
//
vfloat64m4_t test_vfnmadd_vv_f64m4_rm_tum(vbool16_t mask, vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfnmadd_tum(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmadd_vf_f64m4_rm_tum
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmadd.mask.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
//
vfloat64m4_t test_vfnmadd_vf_f64m4_rm_tum(vbool16_t mask, vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfnmadd_tum(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmadd_vv_f64m8_rm_tum
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmadd.mask.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
//
vfloat64m8_t test_vfnmadd_vv_f64m8_rm_tum(vbool8_t mask, vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfnmadd_tum(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmadd_vf_f64m8_rm_tum
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmadd.mask.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
//
vfloat64m8_t test_vfnmadd_vf_f64m8_rm_tum(vbool8_t mask, vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfnmadd_tum(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmadd_vv_f16mf4_rm_tumu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmadd.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
//
vfloat16mf4_t test_vfnmadd_vv_f16mf4_rm_tumu(vbool64_t mask, vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfnmadd_tumu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmadd_vf_f16mf4_rm_tumu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmadd.mask.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
//
vfloat16mf4_t test_vfnmadd_vf_f16mf4_rm_tumu(vbool64_t mask, vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfnmadd_tumu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmadd_vv_f16mf2_rm_tumu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmadd.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
//
vfloat16mf2_t test_vfnmadd_vv_f16mf2_rm_tumu(vbool32_t mask, vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfnmadd_tumu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmadd_vf_f16mf2_rm_tumu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmadd.mask.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
//
vfloat16mf2_t test_vfnmadd_vf_f16mf2_rm_tumu(vbool32_t mask, vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfnmadd_tumu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmadd_vv_f16m1_rm_tumu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmadd.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfnmadd_vv_f16m1_rm_tumu(vbool16_t mask, vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfnmadd_tumu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmadd_vf_f16m1_rm_tumu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmadd.mask.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfnmadd_vf_f16m1_rm_tumu(vbool16_t mask, vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfnmadd_tumu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmadd_vv_f16m2_rm_tumu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmadd.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
//
vfloat16m2_t test_vfnmadd_vv_f16m2_rm_tumu(vbool8_t mask, vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfnmadd_tumu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmadd_vf_f16m2_rm_tumu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmadd.mask.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
//
vfloat16m2_t test_vfnmadd_vf_f16m2_rm_tumu(vbool8_t mask, vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfnmadd_tumu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmadd_vv_f16m4_rm_tumu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmadd.mask.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
//
vfloat16m4_t test_vfnmadd_vv_f16m4_rm_tumu(vbool4_t mask, vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfnmadd_tumu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmadd_vf_f16m4_rm_tumu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmadd.mask.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
//
vfloat16m4_t test_vfnmadd_vf_f16m4_rm_tumu(vbool4_t mask, vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfnmadd_tumu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmadd_vv_f16m8_rm_tumu
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmadd.mask.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
//
vfloat16m8_t test_vfnmadd_vv_f16m8_rm_tumu(vbool2_t mask, vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfnmadd_tumu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmadd_vf_f16m8_rm_tumu
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmadd.mask.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
//
vfloat16m8_t test_vfnmadd_vf_f16m8_rm_tumu(vbool2_t mask, vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfnmadd_tumu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmadd_vv_f32mf2_rm_tumu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmadd.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
//
vfloat32mf2_t test_vfnmadd_vv_f32mf2_rm_tumu(vbool64_t mask, vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfnmadd_tumu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmadd_vf_f32mf2_rm_tumu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmadd.mask.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
//
vfloat32mf2_t test_vfnmadd_vf_f32mf2_rm_tumu(vbool64_t mask, vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfnmadd_tumu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmadd_vv_f32m1_rm_tumu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmadd.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfnmadd_vv_f32m1_rm_tumu(vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfnmadd_tumu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmadd_vf_f32m1_rm_tumu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmadd.mask.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfnmadd_vf_f32m1_rm_tumu(vbool32_t mask, vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfnmadd_tumu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmadd_vv_f32m2_rm_tumu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmadd.mask.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
//
vfloat32m2_t test_vfnmadd_vv_f32m2_rm_tumu(vbool16_t mask, vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfnmadd_tumu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmadd_vf_f32m2_rm_tumu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmadd.mask.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
//
vfloat32m2_t test_vfnmadd_vf_f32m2_rm_tumu(vbool16_t mask, vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfnmadd_tumu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmadd_vv_f32m4_rm_tumu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmadd.mask.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
//
vfloat32m4_t test_vfnmadd_vv_f32m4_rm_tumu(vbool8_t mask, vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfnmadd_tumu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmadd_vf_f32m4_rm_tumu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmadd.mask.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
//
vfloat32m4_t test_vfnmadd_vf_f32m4_rm_tumu(vbool8_t mask, vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfnmadd_tumu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmadd_vv_f32m8_rm_tumu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmadd.mask.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
//
vfloat32m8_t test_vfnmadd_vv_f32m8_rm_tumu(vbool4_t mask, vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfnmadd_tumu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmadd_vf_f32m8_rm_tumu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmadd.mask.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
//
vfloat32m8_t test_vfnmadd_vf_f32m8_rm_tumu(vbool4_t mask, vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfnmadd_tumu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmadd_vv_f64m1_rm_tumu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmadd.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfnmadd_vv_f64m1_rm_tumu(vbool64_t mask, vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfnmadd_tumu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmadd_vf_f64m1_rm_tumu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmadd.mask.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfnmadd_vf_f64m1_rm_tumu(vbool64_t mask, vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfnmadd_tumu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmadd_vv_f64m2_rm_tumu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmadd.mask.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
//
vfloat64m2_t test_vfnmadd_vv_f64m2_rm_tumu(vbool32_t mask, vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfnmadd_tumu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmadd_vf_f64m2_rm_tumu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmadd.mask.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
//
vfloat64m2_t test_vfnmadd_vf_f64m2_rm_tumu(vbool32_t mask, vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfnmadd_tumu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmadd_vv_f64m4_rm_tumu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmadd.mask.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
//
vfloat64m4_t test_vfnmadd_vv_f64m4_rm_tumu(vbool16_t mask, vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfnmadd_tumu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmadd_vf_f64m4_rm_tumu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmadd.mask.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
//
vfloat64m4_t test_vfnmadd_vf_f64m4_rm_tumu(vbool16_t mask, vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfnmadd_tumu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmadd_vv_f64m8_rm_tumu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmadd.mask.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
//
vfloat64m8_t test_vfnmadd_vv_f64m8_rm_tumu(vbool8_t mask, vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfnmadd_tumu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmadd_vf_f64m8_rm_tumu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmadd.mask.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
//
vfloat64m8_t test_vfnmadd_vf_f64m8_rm_tumu(vbool8_t mask, vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfnmadd_tumu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmadd_vv_f16mf4_rm_mu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmadd.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
//
vfloat16mf4_t test_vfnmadd_vv_f16mf4_rm_mu(vbool64_t mask, vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfnmadd_mu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmadd_vf_f16mf4_rm_mu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmadd.mask.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
//
vfloat16mf4_t test_vfnmadd_vf_f16mf4_rm_mu(vbool64_t mask, vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfnmadd_mu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmadd_vv_f16mf2_rm_mu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmadd.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
//
vfloat16mf2_t test_vfnmadd_vv_f16mf2_rm_mu(vbool32_t mask, vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfnmadd_mu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmadd_vf_f16mf2_rm_mu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmadd.mask.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
//
vfloat16mf2_t test_vfnmadd_vf_f16mf2_rm_mu(vbool32_t mask, vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfnmadd_mu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmadd_vv_f16m1_rm_mu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmadd.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfnmadd_vv_f16m1_rm_mu(vbool16_t mask, vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfnmadd_mu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmadd_vf_f16m1_rm_mu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmadd.mask.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfnmadd_vf_f16m1_rm_mu(vbool16_t mask, vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfnmadd_mu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmadd_vv_f16m2_rm_mu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmadd.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
//
vfloat16m2_t test_vfnmadd_vv_f16m2_rm_mu(vbool8_t mask, vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfnmadd_mu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmadd_vf_f16m2_rm_mu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmadd.mask.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
//
vfloat16m2_t test_vfnmadd_vf_f16m2_rm_mu(vbool8_t mask, vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfnmadd_mu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmadd_vv_f16m4_rm_mu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmadd.mask.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
//
vfloat16m4_t test_vfnmadd_vv_f16m4_rm_mu(vbool4_t mask, vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfnmadd_mu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmadd_vf_f16m4_rm_mu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmadd.mask.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
//
vfloat16m4_t test_vfnmadd_vf_f16m4_rm_mu(vbool4_t mask, vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfnmadd_mu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmadd_vv_f16m8_rm_mu
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmadd.mask.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
//
vfloat16m8_t test_vfnmadd_vv_f16m8_rm_mu(vbool2_t mask, vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfnmadd_mu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmadd_vf_f16m8_rm_mu
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmadd.mask.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
//
vfloat16m8_t test_vfnmadd_vf_f16m8_rm_mu(vbool2_t mask, vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfnmadd_mu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmadd_vv_f32mf2_rm_mu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmadd.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
//
vfloat32mf2_t test_vfnmadd_vv_f32mf2_rm_mu(vbool64_t mask, vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfnmadd_mu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmadd_vf_f32mf2_rm_mu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmadd.mask.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
//
vfloat32mf2_t test_vfnmadd_vf_f32mf2_rm_mu(vbool64_t mask, vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfnmadd_mu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmadd_vv_f32m1_rm_mu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmadd.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfnmadd_vv_f32m1_rm_mu(vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfnmadd_mu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmadd_vf_f32m1_rm_mu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmadd.mask.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfnmadd_vf_f32m1_rm_mu(vbool32_t mask, vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfnmadd_mu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmadd_vv_f32m2_rm_mu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmadd.mask.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
//
vfloat32m2_t test_vfnmadd_vv_f32m2_rm_mu(vbool16_t mask, vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfnmadd_mu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmadd_vf_f32m2_rm_mu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmadd.mask.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
//
vfloat32m2_t test_vfnmadd_vf_f32m2_rm_mu(vbool16_t mask, vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfnmadd_mu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmadd_vv_f32m4_rm_mu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmadd.mask.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
//
vfloat32m4_t test_vfnmadd_vv_f32m4_rm_mu(vbool8_t mask, vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfnmadd_mu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmadd_vf_f32m4_rm_mu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmadd.mask.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
//
vfloat32m4_t test_vfnmadd_vf_f32m4_rm_mu(vbool8_t mask, vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfnmadd_mu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmadd_vv_f32m8_rm_mu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmadd.mask.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
//
vfloat32m8_t test_vfnmadd_vv_f32m8_rm_mu(vbool4_t mask, vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfnmadd_mu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmadd_vf_f32m8_rm_mu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmadd.mask.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
//
vfloat32m8_t test_vfnmadd_vf_f32m8_rm_mu(vbool4_t mask, vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfnmadd_mu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmadd_vv_f64m1_rm_mu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmadd.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfnmadd_vv_f64m1_rm_mu(vbool64_t mask, vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfnmadd_mu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmadd_vf_f64m1_rm_mu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmadd.mask.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfnmadd_vf_f64m1_rm_mu(vbool64_t mask, vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfnmadd_mu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmadd_vv_f64m2_rm_mu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmadd.mask.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
//
vfloat64m2_t test_vfnmadd_vv_f64m2_rm_mu(vbool32_t mask, vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfnmadd_mu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmadd_vf_f64m2_rm_mu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmadd.mask.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
//
vfloat64m2_t test_vfnmadd_vf_f64m2_rm_mu(vbool32_t mask, vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfnmadd_mu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmadd_vv_f64m4_rm_mu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmadd.mask.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
//
vfloat64m4_t test_vfnmadd_vv_f64m4_rm_mu(vbool16_t mask, vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfnmadd_mu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmadd_vf_f64m4_rm_mu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmadd.mask.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
//
vfloat64m4_t test_vfnmadd_vf_f64m4_rm_mu(vbool16_t mask, vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfnmadd_mu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmadd_vv_f64m8_rm_mu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmadd.mask.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
//
vfloat64m8_t test_vfnmadd_vv_f64m8_rm_mu(vbool8_t mask, vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfnmadd_mu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmadd_vf_f64m8_rm_mu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmadd.mask.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
//
vfloat64m8_t test_vfnmadd_vf_f64m8_rm_mu(vbool8_t mask, vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfnmadd_mu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}

clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmsac.c

// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target // REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh \ // RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh \
// RUN: -target-feature +experimental-zvfh -disable-O0-optnone \ // RUN: -target-feature +experimental-zvfh -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ // RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s // RUN: FileCheck --check-prefix=CHECK-RV64 %s
#include <riscv_vector.h> #include <riscv_vector.h>
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmsac_vv_f16mf4_tu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmsac_vv_f16mf4_tu
// CHECK-RV64-SAME: (<vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK-RV64-SAME: (<vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmsac.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmsac.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
// //
vfloat16mf4_t test_vfnmsac_vv_f16mf4_tu(vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) { vfloat16mf4_t test_vfnmsac_vv_f16mf4_tu(vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfnmsac_tu(vd, vs1, vs2, vl); return __riscv_vfnmsac_tu(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmsac_vf_f16mf4_tu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmsac_vf_f16mf4_tu
// CHECK-RV64-SAME: (<vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmsac.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmsac.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
// //
vfloat16mf4_t test_vfnmsac_vf_f16mf4_tu(vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) { vfloat16mf4_t test_vfnmsac_vf_f16mf4_tu(vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfnmsac_tu(vd, rs1, vs2, vl); return __riscv_vfnmsac_tu(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmsac_vv_f16mf2_tu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmsac_vv_f16mf2_tu
// CHECK-RV64-SAME: (<vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmsac.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmsac.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
// //
vfloat16mf2_t test_vfnmsac_vv_f16mf2_tu(vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) { vfloat16mf2_t test_vfnmsac_vv_f16mf2_tu(vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfnmsac_tu(vd, vs1, vs2, vl); return __riscv_vfnmsac_tu(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmsac_vf_f16mf2_tu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmsac_vf_f16mf2_tu
// CHECK-RV64-SAME: (<vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmsac.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmsac.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
// //
vfloat16mf2_t test_vfnmsac_vf_f16mf2_tu(vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) { vfloat16mf2_t test_vfnmsac_vf_f16mf2_tu(vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfnmsac_tu(vd, rs1, vs2, vl); return __riscv_vfnmsac_tu(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmsac_vv_f16m1_tu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmsac_vv_f16m1_tu
// CHECK-RV64-SAME: (<vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmsac.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmsac.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
// //
vfloat16m1_t test_vfnmsac_vv_f16m1_tu(vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) { vfloat16m1_t test_vfnmsac_vv_f16m1_tu(vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfnmsac_tu(vd, vs1, vs2, vl); return __riscv_vfnmsac_tu(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmsac_vf_f16m1_tu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmsac_vf_f16m1_tu
// CHECK-RV64-SAME: (<vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmsac.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmsac.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
// //
vfloat16m1_t test_vfnmsac_vf_f16m1_tu(vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) { vfloat16m1_t test_vfnmsac_vf_f16m1_tu(vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfnmsac_tu(vd, rs1, vs2, vl); return __riscv_vfnmsac_tu(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmsac_vv_f16m2_tu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmsac_vv_f16m2_tu
// CHECK-RV64-SAME: (<vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmsac.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmsac.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
// //
vfloat16m2_t test_vfnmsac_vv_f16m2_tu(vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) { vfloat16m2_t test_vfnmsac_vv_f16m2_tu(vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfnmsac_tu(vd, vs1, vs2, vl); return __riscv_vfnmsac_tu(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmsac_vf_f16m2_tu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmsac_vf_f16m2_tu
// CHECK-RV64-SAME: (<vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmsac.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmsac.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
// //
vfloat16m2_t test_vfnmsac_vf_f16m2_tu(vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) { vfloat16m2_t test_vfnmsac_vf_f16m2_tu(vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfnmsac_tu(vd, rs1, vs2, vl); return __riscv_vfnmsac_tu(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmsac_vv_f16m4_tu // CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmsac_vv_f16m4_tu
// CHECK-RV64-SAME: (<vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmsac.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmsac.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
// //
vfloat16m4_t test_vfnmsac_vv_f16m4_tu(vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) { vfloat16m4_t test_vfnmsac_vv_f16m4_tu(vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfnmsac_tu(vd, vs1, vs2, vl); return __riscv_vfnmsac_tu(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmsac_vf_f16m4_tu // CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmsac_vf_f16m4_tu
// CHECK-RV64-SAME: (<vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmsac.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmsac.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
// //
vfloat16m4_t test_vfnmsac_vf_f16m4_tu(vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) { vfloat16m4_t test_vfnmsac_vf_f16m4_tu(vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfnmsac_tu(vd, rs1, vs2, vl); return __riscv_vfnmsac_tu(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmsac_vv_f16m8_tu // CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmsac_vv_f16m8_tu
// CHECK-RV64-SAME: (<vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmsac.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmsac.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
// //
vfloat16m8_t test_vfnmsac_vv_f16m8_tu(vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) { vfloat16m8_t test_vfnmsac_vv_f16m8_tu(vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfnmsac_tu(vd, vs1, vs2, vl); return __riscv_vfnmsac_tu(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmsac_vf_f16m8_tu // CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmsac_vf_f16m8_tu
// CHECK-RV64-SAME: (<vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmsac.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmsac.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
// //
vfloat16m8_t test_vfnmsac_vf_f16m8_tu(vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) { vfloat16m8_t test_vfnmsac_vf_f16m8_tu(vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfnmsac_tu(vd, rs1, vs2, vl); return __riscv_vfnmsac_tu(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmsac_vv_f32mf2_tu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmsac_vv_f32mf2_tu
// CHECK-RV64-SAME: (<vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmsac.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmsac.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfnmsac_vv_f32mf2_tu(vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) { vfloat32mf2_t test_vfnmsac_vv_f32mf2_tu(vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfnmsac_tu(vd, vs1, vs2, vl); return __riscv_vfnmsac_tu(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmsac_vf_f32mf2_tu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmsac_vf_f32mf2_tu
// CHECK-RV64-SAME: (<vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmsac.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmsac.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfnmsac_vf_f32mf2_tu(vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) { vfloat32mf2_t test_vfnmsac_vf_f32mf2_tu(vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfnmsac_tu(vd, rs1, vs2, vl); return __riscv_vfnmsac_tu(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmsac_vv_f32m1_tu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmsac_vv_f32m1_tu
// CHECK-RV64-SAME: (<vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmsac.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmsac.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfnmsac_vv_f32m1_tu(vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) { vfloat32m1_t test_vfnmsac_vv_f32m1_tu(vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfnmsac_tu(vd, vs1, vs2, vl); return __riscv_vfnmsac_tu(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmsac_vf_f32m1_tu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmsac_vf_f32m1_tu
// CHECK-RV64-SAME: (<vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmsac.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmsac.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfnmsac_vf_f32m1_tu(vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) { vfloat32m1_t test_vfnmsac_vf_f32m1_tu(vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfnmsac_tu(vd, rs1, vs2, vl); return __riscv_vfnmsac_tu(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmsac_vv_f32m2_tu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmsac_vv_f32m2_tu
// CHECK-RV64-SAME: (<vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmsac.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmsac.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfnmsac_vv_f32m2_tu(vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) { vfloat32m2_t test_vfnmsac_vv_f32m2_tu(vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfnmsac_tu(vd, vs1, vs2, vl); return __riscv_vfnmsac_tu(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmsac_vf_f32m2_tu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmsac_vf_f32m2_tu
// CHECK-RV64-SAME: (<vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmsac.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmsac.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfnmsac_vf_f32m2_tu(vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) { vfloat32m2_t test_vfnmsac_vf_f32m2_tu(vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfnmsac_tu(vd, rs1, vs2, vl); return __riscv_vfnmsac_tu(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmsac_vv_f32m4_tu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmsac_vv_f32m4_tu
// CHECK-RV64-SAME: (<vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmsac.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmsac.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfnmsac_vv_f32m4_tu(vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) { vfloat32m4_t test_vfnmsac_vv_f32m4_tu(vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfnmsac_tu(vd, vs1, vs2, vl); return __riscv_vfnmsac_tu(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmsac_vf_f32m4_tu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmsac_vf_f32m4_tu
// CHECK-RV64-SAME: (<vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmsac.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmsac.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfnmsac_vf_f32m4_tu(vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) { vfloat32m4_t test_vfnmsac_vf_f32m4_tu(vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfnmsac_tu(vd, rs1, vs2, vl); return __riscv_vfnmsac_tu(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmsac_vv_f32m8_tu // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmsac_vv_f32m8_tu
// CHECK-RV64-SAME: (<vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmsac.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmsac.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfnmsac_vv_f32m8_tu(vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) { vfloat32m8_t test_vfnmsac_vv_f32m8_tu(vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfnmsac_tu(vd, vs1, vs2, vl); return __riscv_vfnmsac_tu(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmsac_vf_f32m8_tu // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmsac_vf_f32m8_tu
// CHECK-RV64-SAME: (<vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmsac.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmsac.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfnmsac_vf_f32m8_tu(vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) { vfloat32m8_t test_vfnmsac_vf_f32m8_tu(vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfnmsac_tu(vd, rs1, vs2, vl); return __riscv_vfnmsac_tu(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmsac_vv_f64m1_tu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmsac_vv_f64m1_tu
// CHECK-RV64-SAME: (<vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmsac.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmsac.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfnmsac_vv_f64m1_tu(vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) { vfloat64m1_t test_vfnmsac_vv_f64m1_tu(vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfnmsac_tu(vd, vs1, vs2, vl); return __riscv_vfnmsac_tu(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmsac_vf_f64m1_tu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmsac_vf_f64m1_tu
// CHECK-RV64-SAME: (<vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmsac.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmsac.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfnmsac_vf_f64m1_tu(vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) { vfloat64m1_t test_vfnmsac_vf_f64m1_tu(vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfnmsac_tu(vd, rs1, vs2, vl); return __riscv_vfnmsac_tu(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmsac_vv_f64m2_tu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmsac_vv_f64m2_tu
// CHECK-RV64-SAME: (<vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmsac.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmsac.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfnmsac_vv_f64m2_tu(vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) { vfloat64m2_t test_vfnmsac_vv_f64m2_tu(vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfnmsac_tu(vd, vs1, vs2, vl); return __riscv_vfnmsac_tu(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmsac_vf_f64m2_tu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmsac_vf_f64m2_tu
// CHECK-RV64-SAME: (<vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmsac.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmsac.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfnmsac_vf_f64m2_tu(vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) { vfloat64m2_t test_vfnmsac_vf_f64m2_tu(vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfnmsac_tu(vd, rs1, vs2, vl); return __riscv_vfnmsac_tu(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmsac_vv_f64m4_tu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmsac_vv_f64m4_tu
// CHECK-RV64-SAME: (<vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmsac.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmsac.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfnmsac_vv_f64m4_tu(vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) { vfloat64m4_t test_vfnmsac_vv_f64m4_tu(vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfnmsac_tu(vd, vs1, vs2, vl); return __riscv_vfnmsac_tu(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmsac_vf_f64m4_tu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmsac_vf_f64m4_tu
// CHECK-RV64-SAME: (<vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmsac.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmsac.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfnmsac_vf_f64m4_tu(vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) { vfloat64m4_t test_vfnmsac_vf_f64m4_tu(vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfnmsac_tu(vd, rs1, vs2, vl); return __riscv_vfnmsac_tu(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmsac_vv_f64m8_tu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmsac_vv_f64m8_tu
// CHECK-RV64-SAME: (<vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmsac.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmsac.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfnmsac_vv_f64m8_tu(vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) { vfloat64m8_t test_vfnmsac_vv_f64m8_tu(vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfnmsac_tu(vd, vs1, vs2, vl); return __riscv_vfnmsac_tu(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmsac_vf_f64m8_tu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmsac_vf_f64m8_tu
// CHECK-RV64-SAME: (<vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmsac.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmsac.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfnmsac_vf_f64m8_tu(vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) { vfloat64m8_t test_vfnmsac_vf_f64m8_tu(vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfnmsac_tu(vd, rs1, vs2, vl); return __riscv_vfnmsac_tu(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmsac_vv_f16mf4_tum // CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmsac_vv_f16mf4_tum
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmsac.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmsac.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
// //
vfloat16mf4_t test_vfnmsac_vv_f16mf4_tum(vbool64_t mask, vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) { vfloat16mf4_t test_vfnmsac_vv_f16mf4_tum(vbool64_t mask, vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfnmsac_tum(mask, vd, vs1, vs2, vl); return __riscv_vfnmsac_tum(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmsac_vf_f16mf4_tum // CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmsac_vf_f16mf4_tum
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmsac.mask.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmsac.mask.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
// //
vfloat16mf4_t test_vfnmsac_vf_f16mf4_tum(vbool64_t mask, vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) { vfloat16mf4_t test_vfnmsac_vf_f16mf4_tum(vbool64_t mask, vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfnmsac_tum(mask, vd, rs1, vs2, vl); return __riscv_vfnmsac_tum(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmsac_vv_f16mf2_tum // CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmsac_vv_f16mf2_tum
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmsac.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmsac.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
// //
vfloat16mf2_t test_vfnmsac_vv_f16mf2_tum(vbool32_t mask, vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) { vfloat16mf2_t test_vfnmsac_vv_f16mf2_tum(vbool32_t mask, vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfnmsac_tum(mask, vd, vs1, vs2, vl); return __riscv_vfnmsac_tum(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmsac_vf_f16mf2_tum // CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmsac_vf_f16mf2_tum
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmsac.mask.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmsac.mask.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
// //
vfloat16mf2_t test_vfnmsac_vf_f16mf2_tum(vbool32_t mask, vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) { vfloat16mf2_t test_vfnmsac_vf_f16mf2_tum(vbool32_t mask, vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfnmsac_tum(mask, vd, rs1, vs2, vl); return __riscv_vfnmsac_tum(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmsac_vv_f16m1_tum // CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmsac_vv_f16m1_tum
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmsac.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmsac.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
// //
vfloat16m1_t test_vfnmsac_vv_f16m1_tum(vbool16_t mask, vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) { vfloat16m1_t test_vfnmsac_vv_f16m1_tum(vbool16_t mask, vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfnmsac_tum(mask, vd, vs1, vs2, vl); return __riscv_vfnmsac_tum(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmsac_vf_f16m1_tum // CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmsac_vf_f16m1_tum
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmsac.mask.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmsac.mask.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
// //
vfloat16m1_t test_vfnmsac_vf_f16m1_tum(vbool16_t mask, vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) { vfloat16m1_t test_vfnmsac_vf_f16m1_tum(vbool16_t mask, vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfnmsac_tum(mask, vd, rs1, vs2, vl); return __riscv_vfnmsac_tum(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmsac_vv_f16m2_tum // CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmsac_vv_f16m2_tum
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmsac.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmsac.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
// //
vfloat16m2_t test_vfnmsac_vv_f16m2_tum(vbool8_t mask, vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) { vfloat16m2_t test_vfnmsac_vv_f16m2_tum(vbool8_t mask, vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfnmsac_tum(mask, vd, vs1, vs2, vl); return __riscv_vfnmsac_tum(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmsac_vf_f16m2_tum // CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmsac_vf_f16m2_tum
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmsac.mask.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmsac.mask.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
// //
vfloat16m2_t test_vfnmsac_vf_f16m2_tum(vbool8_t mask, vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) { vfloat16m2_t test_vfnmsac_vf_f16m2_tum(vbool8_t mask, vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfnmsac_tum(mask, vd, rs1, vs2, vl); return __riscv_vfnmsac_tum(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmsac_vv_f16m4_tum // CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmsac_vv_f16m4_tum
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmsac.mask.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmsac.mask.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
// //
vfloat16m4_t test_vfnmsac_vv_f16m4_tum(vbool4_t mask, vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) { vfloat16m4_t test_vfnmsac_vv_f16m4_tum(vbool4_t mask, vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfnmsac_tum(mask, vd, vs1, vs2, vl); return __riscv_vfnmsac_tum(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmsac_vf_f16m4_tum // CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmsac_vf_f16m4_tum
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmsac.mask.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmsac.mask.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
// //
vfloat16m4_t test_vfnmsac_vf_f16m4_tum(vbool4_t mask, vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) { vfloat16m4_t test_vfnmsac_vf_f16m4_tum(vbool4_t mask, vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfnmsac_tum(mask, vd, rs1, vs2, vl); return __riscv_vfnmsac_tum(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmsac_vv_f16m8_tum // CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmsac_vv_f16m8_tum
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmsac.mask.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmsac.mask.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
// //
vfloat16m8_t test_vfnmsac_vv_f16m8_tum(vbool2_t mask, vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) { vfloat16m8_t test_vfnmsac_vv_f16m8_tum(vbool2_t mask, vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfnmsac_tum(mask, vd, vs1, vs2, vl); return __riscv_vfnmsac_tum(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmsac_vf_f16m8_tum // CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmsac_vf_f16m8_tum
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmsac.mask.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmsac.mask.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
// //
vfloat16m8_t test_vfnmsac_vf_f16m8_tum(vbool2_t mask, vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) { vfloat16m8_t test_vfnmsac_vf_f16m8_tum(vbool2_t mask, vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfnmsac_tum(mask, vd, rs1, vs2, vl); return __riscv_vfnmsac_tum(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmsac_vv_f32mf2_tum // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmsac_vv_f32mf2_tum
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmsac.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmsac.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfnmsac_vv_f32mf2_tum(vbool64_t mask, vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) { vfloat32mf2_t test_vfnmsac_vv_f32mf2_tum(vbool64_t mask, vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfnmsac_tum(mask, vd, vs1, vs2, vl); return __riscv_vfnmsac_tum(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmsac_vf_f32mf2_tum // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmsac_vf_f32mf2_tum
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmsac.mask.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmsac.mask.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfnmsac_vf_f32mf2_tum(vbool64_t mask, vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) { vfloat32mf2_t test_vfnmsac_vf_f32mf2_tum(vbool64_t mask, vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfnmsac_tum(mask, vd, rs1, vs2, vl); return __riscv_vfnmsac_tum(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmsac_vv_f32m1_tum // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmsac_vv_f32m1_tum
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmsac.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmsac.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfnmsac_vv_f32m1_tum(vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) { vfloat32m1_t test_vfnmsac_vv_f32m1_tum(vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfnmsac_tum(mask, vd, vs1, vs2, vl); return __riscv_vfnmsac_tum(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmsac_vf_f32m1_tum // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmsac_vf_f32m1_tum
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmsac.mask.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmsac.mask.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfnmsac_vf_f32m1_tum(vbool32_t mask, vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) { vfloat32m1_t test_vfnmsac_vf_f32m1_tum(vbool32_t mask, vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfnmsac_tum(mask, vd, rs1, vs2, vl); return __riscv_vfnmsac_tum(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmsac_vv_f32m2_tum // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmsac_vv_f32m2_tum
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmsac.mask.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmsac.mask.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfnmsac_vv_f32m2_tum(vbool16_t mask, vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) { vfloat32m2_t test_vfnmsac_vv_f32m2_tum(vbool16_t mask, vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfnmsac_tum(mask, vd, vs1, vs2, vl); return __riscv_vfnmsac_tum(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmsac_vf_f32m2_tum // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmsac_vf_f32m2_tum
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmsac.mask.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmsac.mask.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfnmsac_vf_f32m2_tum(vbool16_t mask, vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) { vfloat32m2_t test_vfnmsac_vf_f32m2_tum(vbool16_t mask, vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfnmsac_tum(mask, vd, rs1, vs2, vl); return __riscv_vfnmsac_tum(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmsac_vv_f32m4_tum // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmsac_vv_f32m4_tum
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmsac.mask.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmsac.mask.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfnmsac_vv_f32m4_tum(vbool8_t mask, vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) { vfloat32m4_t test_vfnmsac_vv_f32m4_tum(vbool8_t mask, vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfnmsac_tum(mask, vd, vs1, vs2, vl); return __riscv_vfnmsac_tum(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmsac_vf_f32m4_tum // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmsac_vf_f32m4_tum
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmsac.mask.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmsac.mask.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfnmsac_vf_f32m4_tum(vbool8_t mask, vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) { vfloat32m4_t test_vfnmsac_vf_f32m4_tum(vbool8_t mask, vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfnmsac_tum(mask, vd, rs1, vs2, vl); return __riscv_vfnmsac_tum(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmsac_vv_f32m8_tum // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmsac_vv_f32m8_tum
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmsac.mask.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmsac.mask.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfnmsac_vv_f32m8_tum(vbool4_t mask, vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) { vfloat32m8_t test_vfnmsac_vv_f32m8_tum(vbool4_t mask, vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfnmsac_tum(mask, vd, vs1, vs2, vl); return __riscv_vfnmsac_tum(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmsac_vf_f32m8_tum // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmsac_vf_f32m8_tum
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmsac.mask.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmsac.mask.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfnmsac_vf_f32m8_tum(vbool4_t mask, vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) { vfloat32m8_t test_vfnmsac_vf_f32m8_tum(vbool4_t mask, vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfnmsac_tum(mask, vd, rs1, vs2, vl); return __riscv_vfnmsac_tum(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmsac_vv_f64m1_tum // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmsac_vv_f64m1_tum
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmsac.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmsac.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfnmsac_vv_f64m1_tum(vbool64_t mask, vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) { vfloat64m1_t test_vfnmsac_vv_f64m1_tum(vbool64_t mask, vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfnmsac_tum(mask, vd, vs1, vs2, vl); return __riscv_vfnmsac_tum(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmsac_vf_f64m1_tum // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmsac_vf_f64m1_tum
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmsac.mask.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmsac.mask.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfnmsac_vf_f64m1_tum(vbool64_t mask, vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) { vfloat64m1_t test_vfnmsac_vf_f64m1_tum(vbool64_t mask, vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfnmsac_tum(mask, vd, rs1, vs2, vl); return __riscv_vfnmsac_tum(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmsac_vv_f64m2_tum // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmsac_vv_f64m2_tum
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmsac.mask.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmsac.mask.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfnmsac_vv_f64m2_tum(vbool32_t mask, vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) { vfloat64m2_t test_vfnmsac_vv_f64m2_tum(vbool32_t mask, vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfnmsac_tum(mask, vd, vs1, vs2, vl); return __riscv_vfnmsac_tum(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmsac_vf_f64m2_tum // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmsac_vf_f64m2_tum
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmsac.mask.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmsac.mask.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfnmsac_vf_f64m2_tum(vbool32_t mask, vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) { vfloat64m2_t test_vfnmsac_vf_f64m2_tum(vbool32_t mask, vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfnmsac_tum(mask, vd, rs1, vs2, vl); return __riscv_vfnmsac_tum(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmsac_vv_f64m4_tum // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmsac_vv_f64m4_tum
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmsac.mask.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmsac.mask.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfnmsac_vv_f64m4_tum(vbool16_t mask, vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) { vfloat64m4_t test_vfnmsac_vv_f64m4_tum(vbool16_t mask, vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfnmsac_tum(mask, vd, vs1, vs2, vl); return __riscv_vfnmsac_tum(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmsac_vf_f64m4_tum // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmsac_vf_f64m4_tum
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmsac.mask.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmsac.mask.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfnmsac_vf_f64m4_tum(vbool16_t mask, vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) { vfloat64m4_t test_vfnmsac_vf_f64m4_tum(vbool16_t mask, vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfnmsac_tum(mask, vd, rs1, vs2, vl); return __riscv_vfnmsac_tum(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmsac_vv_f64m8_tum // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmsac_vv_f64m8_tum
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmsac.mask.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmsac.mask.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfnmsac_vv_f64m8_tum(vbool8_t mask, vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) { vfloat64m8_t test_vfnmsac_vv_f64m8_tum(vbool8_t mask, vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfnmsac_tum(mask, vd, vs1, vs2, vl); return __riscv_vfnmsac_tum(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmsac_vf_f64m8_tum // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmsac_vf_f64m8_tum
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmsac.mask.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmsac.mask.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfnmsac_vf_f64m8_tum(vbool8_t mask, vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) { vfloat64m8_t test_vfnmsac_vf_f64m8_tum(vbool8_t mask, vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfnmsac_tum(mask, vd, rs1, vs2, vl); return __riscv_vfnmsac_tum(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmsac_vv_f16mf4_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmsac_vv_f16mf4_tumu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmsac.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmsac.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
// //
vfloat16mf4_t test_vfnmsac_vv_f16mf4_tumu(vbool64_t mask, vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) { vfloat16mf4_t test_vfnmsac_vv_f16mf4_tumu(vbool64_t mask, vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfnmsac_tumu(mask, vd, vs1, vs2, vl); return __riscv_vfnmsac_tumu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmsac_vf_f16mf4_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmsac_vf_f16mf4_tumu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmsac.mask.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmsac.mask.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
// //
vfloat16mf4_t test_vfnmsac_vf_f16mf4_tumu(vbool64_t mask, vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) { vfloat16mf4_t test_vfnmsac_vf_f16mf4_tumu(vbool64_t mask, vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfnmsac_tumu(mask, vd, rs1, vs2, vl); return __riscv_vfnmsac_tumu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmsac_vv_f16mf2_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmsac_vv_f16mf2_tumu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmsac.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmsac.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
// //
vfloat16mf2_t test_vfnmsac_vv_f16mf2_tumu(vbool32_t mask, vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) { vfloat16mf2_t test_vfnmsac_vv_f16mf2_tumu(vbool32_t mask, vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfnmsac_tumu(mask, vd, vs1, vs2, vl); return __riscv_vfnmsac_tumu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmsac_vf_f16mf2_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmsac_vf_f16mf2_tumu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmsac.mask.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmsac.mask.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
// //
vfloat16mf2_t test_vfnmsac_vf_f16mf2_tumu(vbool32_t mask, vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) { vfloat16mf2_t test_vfnmsac_vf_f16mf2_tumu(vbool32_t mask, vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfnmsac_tumu(mask, vd, rs1, vs2, vl); return __riscv_vfnmsac_tumu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmsac_vv_f16m1_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmsac_vv_f16m1_tumu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmsac.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmsac.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
// //
vfloat16m1_t test_vfnmsac_vv_f16m1_tumu(vbool16_t mask, vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) { vfloat16m1_t test_vfnmsac_vv_f16m1_tumu(vbool16_t mask, vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfnmsac_tumu(mask, vd, vs1, vs2, vl); return __riscv_vfnmsac_tumu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmsac_vf_f16m1_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmsac_vf_f16m1_tumu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmsac.mask.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmsac.mask.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
// //
vfloat16m1_t test_vfnmsac_vf_f16m1_tumu(vbool16_t mask, vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) { vfloat16m1_t test_vfnmsac_vf_f16m1_tumu(vbool16_t mask, vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfnmsac_tumu(mask, vd, rs1, vs2, vl); return __riscv_vfnmsac_tumu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmsac_vv_f16m2_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmsac_vv_f16m2_tumu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmsac.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmsac.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
// //
vfloat16m2_t test_vfnmsac_vv_f16m2_tumu(vbool8_t mask, vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) { vfloat16m2_t test_vfnmsac_vv_f16m2_tumu(vbool8_t mask, vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfnmsac_tumu(mask, vd, vs1, vs2, vl); return __riscv_vfnmsac_tumu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmsac_vf_f16m2_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmsac_vf_f16m2_tumu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmsac.mask.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmsac.mask.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
// //
vfloat16m2_t test_vfnmsac_vf_f16m2_tumu(vbool8_t mask, vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) { vfloat16m2_t test_vfnmsac_vf_f16m2_tumu(vbool8_t mask, vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfnmsac_tumu(mask, vd, rs1, vs2, vl); return __riscv_vfnmsac_tumu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmsac_vv_f16m4_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmsac_vv_f16m4_tumu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmsac.mask.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmsac.mask.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
// //
vfloat16m4_t test_vfnmsac_vv_f16m4_tumu(vbool4_t mask, vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) { vfloat16m4_t test_vfnmsac_vv_f16m4_tumu(vbool4_t mask, vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfnmsac_tumu(mask, vd, vs1, vs2, vl); return __riscv_vfnmsac_tumu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmsac_vf_f16m4_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmsac_vf_f16m4_tumu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmsac.mask.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmsac.mask.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
// //
vfloat16m4_t test_vfnmsac_vf_f16m4_tumu(vbool4_t mask, vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) { vfloat16m4_t test_vfnmsac_vf_f16m4_tumu(vbool4_t mask, vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfnmsac_tumu(mask, vd, rs1, vs2, vl); return __riscv_vfnmsac_tumu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmsac_vv_f16m8_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmsac_vv_f16m8_tumu
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmsac.mask.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmsac.mask.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
// //
vfloat16m8_t test_vfnmsac_vv_f16m8_tumu(vbool2_t mask, vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) { vfloat16m8_t test_vfnmsac_vv_f16m8_tumu(vbool2_t mask, vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfnmsac_tumu(mask, vd, vs1, vs2, vl); return __riscv_vfnmsac_tumu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmsac_vf_f16m8_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmsac_vf_f16m8_tumu
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmsac.mask.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmsac.mask.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
// //
vfloat16m8_t test_vfnmsac_vf_f16m8_tumu(vbool2_t mask, vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) { vfloat16m8_t test_vfnmsac_vf_f16m8_tumu(vbool2_t mask, vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfnmsac_tumu(mask, vd, rs1, vs2, vl); return __riscv_vfnmsac_tumu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmsac_vv_f32mf2_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmsac_vv_f32mf2_tumu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmsac.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmsac.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfnmsac_vv_f32mf2_tumu(vbool64_t mask, vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) { vfloat32mf2_t test_vfnmsac_vv_f32mf2_tumu(vbool64_t mask, vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfnmsac_tumu(mask, vd, vs1, vs2, vl); return __riscv_vfnmsac_tumu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmsac_vf_f32mf2_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmsac_vf_f32mf2_tumu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmsac.mask.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmsac.mask.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfnmsac_vf_f32mf2_tumu(vbool64_t mask, vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) { vfloat32mf2_t test_vfnmsac_vf_f32mf2_tumu(vbool64_t mask, vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfnmsac_tumu(mask, vd, rs1, vs2, vl); return __riscv_vfnmsac_tumu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmsac_vv_f32m1_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmsac_vv_f32m1_tumu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmsac.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmsac.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfnmsac_vv_f32m1_tumu(vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) { vfloat32m1_t test_vfnmsac_vv_f32m1_tumu(vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfnmsac_tumu(mask, vd, vs1, vs2, vl); return __riscv_vfnmsac_tumu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmsac_vf_f32m1_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmsac_vf_f32m1_tumu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmsac.mask.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmsac.mask.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfnmsac_vf_f32m1_tumu(vbool32_t mask, vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) { vfloat32m1_t test_vfnmsac_vf_f32m1_tumu(vbool32_t mask, vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfnmsac_tumu(mask, vd, rs1, vs2, vl); return __riscv_vfnmsac_tumu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmsac_vv_f32m2_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmsac_vv_f32m2_tumu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmsac.mask.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmsac.mask.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfnmsac_vv_f32m2_tumu(vbool16_t mask, vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) { vfloat32m2_t test_vfnmsac_vv_f32m2_tumu(vbool16_t mask, vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfnmsac_tumu(mask, vd, vs1, vs2, vl); return __riscv_vfnmsac_tumu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmsac_vf_f32m2_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmsac_vf_f32m2_tumu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmsac.mask.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmsac.mask.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfnmsac_vf_f32m2_tumu(vbool16_t mask, vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) { vfloat32m2_t test_vfnmsac_vf_f32m2_tumu(vbool16_t mask, vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfnmsac_tumu(mask, vd, rs1, vs2, vl); return __riscv_vfnmsac_tumu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmsac_vv_f32m4_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmsac_vv_f32m4_tumu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmsac.mask.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmsac.mask.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfnmsac_vv_f32m4_tumu(vbool8_t mask, vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) { vfloat32m4_t test_vfnmsac_vv_f32m4_tumu(vbool8_t mask, vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfnmsac_tumu(mask, vd, vs1, vs2, vl); return __riscv_vfnmsac_tumu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmsac_vf_f32m4_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmsac_vf_f32m4_tumu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmsac.mask.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmsac.mask.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfnmsac_vf_f32m4_tumu(vbool8_t mask, vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) { vfloat32m4_t test_vfnmsac_vf_f32m4_tumu(vbool8_t mask, vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfnmsac_tumu(mask, vd, rs1, vs2, vl); return __riscv_vfnmsac_tumu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmsac_vv_f32m8_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmsac_vv_f32m8_tumu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmsac.mask.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmsac.mask.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfnmsac_vv_f32m8_tumu(vbool4_t mask, vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) { vfloat32m8_t test_vfnmsac_vv_f32m8_tumu(vbool4_t mask, vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfnmsac_tumu(mask, vd, vs1, vs2, vl); return __riscv_vfnmsac_tumu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmsac_vf_f32m8_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmsac_vf_f32m8_tumu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmsac.mask.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmsac.mask.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfnmsac_vf_f32m8_tumu(vbool4_t mask, vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) { vfloat32m8_t test_vfnmsac_vf_f32m8_tumu(vbool4_t mask, vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfnmsac_tumu(mask, vd, rs1, vs2, vl); return __riscv_vfnmsac_tumu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmsac_vv_f64m1_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmsac_vv_f64m1_tumu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmsac.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmsac.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfnmsac_vv_f64m1_tumu(vbool64_t mask, vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) { vfloat64m1_t test_vfnmsac_vv_f64m1_tumu(vbool64_t mask, vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfnmsac_tumu(mask, vd, vs1, vs2, vl); return __riscv_vfnmsac_tumu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmsac_vf_f64m1_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmsac_vf_f64m1_tumu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmsac.mask.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmsac.mask.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfnmsac_vf_f64m1_tumu(vbool64_t mask, vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) { vfloat64m1_t test_vfnmsac_vf_f64m1_tumu(vbool64_t mask, vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfnmsac_tumu(mask, vd, rs1, vs2, vl); return __riscv_vfnmsac_tumu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmsac_vv_f64m2_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmsac_vv_f64m2_tumu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmsac.mask.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmsac.mask.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfnmsac_vv_f64m2_tumu(vbool32_t mask, vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) { vfloat64m2_t test_vfnmsac_vv_f64m2_tumu(vbool32_t mask, vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfnmsac_tumu(mask, vd, vs1, vs2, vl); return __riscv_vfnmsac_tumu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmsac_vf_f64m2_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmsac_vf_f64m2_tumu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmsac.mask.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmsac.mask.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfnmsac_vf_f64m2_tumu(vbool32_t mask, vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) { vfloat64m2_t test_vfnmsac_vf_f64m2_tumu(vbool32_t mask, vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfnmsac_tumu(mask, vd, rs1, vs2, vl); return __riscv_vfnmsac_tumu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmsac_vv_f64m4_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmsac_vv_f64m4_tumu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmsac.mask.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmsac.mask.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfnmsac_vv_f64m4_tumu(vbool16_t mask, vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) { vfloat64m4_t test_vfnmsac_vv_f64m4_tumu(vbool16_t mask, vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfnmsac_tumu(mask, vd, vs1, vs2, vl); return __riscv_vfnmsac_tumu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmsac_vf_f64m4_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmsac_vf_f64m4_tumu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmsac.mask.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmsac.mask.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfnmsac_vf_f64m4_tumu(vbool16_t mask, vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) { vfloat64m4_t test_vfnmsac_vf_f64m4_tumu(vbool16_t mask, vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfnmsac_tumu(mask, vd, rs1, vs2, vl); return __riscv_vfnmsac_tumu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmsac_vv_f64m8_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmsac_vv_f64m8_tumu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmsac.mask.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmsac.mask.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfnmsac_vv_f64m8_tumu(vbool8_t mask, vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) { vfloat64m8_t test_vfnmsac_vv_f64m8_tumu(vbool8_t mask, vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfnmsac_tumu(mask, vd, vs1, vs2, vl); return __riscv_vfnmsac_tumu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmsac_vf_f64m8_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmsac_vf_f64m8_tumu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmsac.mask.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmsac.mask.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfnmsac_vf_f64m8_tumu(vbool8_t mask, vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) { vfloat64m8_t test_vfnmsac_vf_f64m8_tumu(vbool8_t mask, vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfnmsac_tumu(mask, vd, rs1, vs2, vl); return __riscv_vfnmsac_tumu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmsac_vv_f16mf4_mu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmsac_vv_f16mf4_mu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmsac.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmsac.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
// //
vfloat16mf4_t test_vfnmsac_vv_f16mf4_mu(vbool64_t mask, vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) { vfloat16mf4_t test_vfnmsac_vv_f16mf4_mu(vbool64_t mask, vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfnmsac_mu(mask, vd, vs1, vs2, vl); return __riscv_vfnmsac_mu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmsac_vf_f16mf4_mu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmsac_vf_f16mf4_mu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmsac.mask.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmsac.mask.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
// //
vfloat16mf4_t test_vfnmsac_vf_f16mf4_mu(vbool64_t mask, vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) { vfloat16mf4_t test_vfnmsac_vf_f16mf4_mu(vbool64_t mask, vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfnmsac_mu(mask, vd, rs1, vs2, vl); return __riscv_vfnmsac_mu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmsac_vv_f16mf2_mu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmsac_vv_f16mf2_mu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmsac.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmsac.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
// //
vfloat16mf2_t test_vfnmsac_vv_f16mf2_mu(vbool32_t mask, vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) { vfloat16mf2_t test_vfnmsac_vv_f16mf2_mu(vbool32_t mask, vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfnmsac_mu(mask, vd, vs1, vs2, vl); return __riscv_vfnmsac_mu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmsac_vf_f16mf2_mu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmsac_vf_f16mf2_mu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmsac.mask.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmsac.mask.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
// //
vfloat16mf2_t test_vfnmsac_vf_f16mf2_mu(vbool32_t mask, vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) { vfloat16mf2_t test_vfnmsac_vf_f16mf2_mu(vbool32_t mask, vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfnmsac_mu(mask, vd, rs1, vs2, vl); return __riscv_vfnmsac_mu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmsac_vv_f16m1_mu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmsac_vv_f16m1_mu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmsac.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmsac.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
// //
vfloat16m1_t test_vfnmsac_vv_f16m1_mu(vbool16_t mask, vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) { vfloat16m1_t test_vfnmsac_vv_f16m1_mu(vbool16_t mask, vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfnmsac_mu(mask, vd, vs1, vs2, vl); return __riscv_vfnmsac_mu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmsac_vf_f16m1_mu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmsac_vf_f16m1_mu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmsac.mask.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmsac.mask.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
// //
vfloat16m1_t test_vfnmsac_vf_f16m1_mu(vbool16_t mask, vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) { vfloat16m1_t test_vfnmsac_vf_f16m1_mu(vbool16_t mask, vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfnmsac_mu(mask, vd, rs1, vs2, vl); return __riscv_vfnmsac_mu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmsac_vv_f16m2_mu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmsac_vv_f16m2_mu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmsac.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmsac.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
// //
vfloat16m2_t test_vfnmsac_vv_f16m2_mu(vbool8_t mask, vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) { vfloat16m2_t test_vfnmsac_vv_f16m2_mu(vbool8_t mask, vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfnmsac_mu(mask, vd, vs1, vs2, vl); return __riscv_vfnmsac_mu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmsac_vf_f16m2_mu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmsac_vf_f16m2_mu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmsac.mask.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmsac.mask.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
// //
vfloat16m2_t test_vfnmsac_vf_f16m2_mu(vbool8_t mask, vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) { vfloat16m2_t test_vfnmsac_vf_f16m2_mu(vbool8_t mask, vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfnmsac_mu(mask, vd, rs1, vs2, vl); return __riscv_vfnmsac_mu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmsac_vv_f16m4_mu // CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmsac_vv_f16m4_mu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmsac.mask.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmsac.mask.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
// //
vfloat16m4_t test_vfnmsac_vv_f16m4_mu(vbool4_t mask, vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) { vfloat16m4_t test_vfnmsac_vv_f16m4_mu(vbool4_t mask, vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfnmsac_mu(mask, vd, vs1, vs2, vl); return __riscv_vfnmsac_mu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmsac_vf_f16m4_mu // CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmsac_vf_f16m4_mu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmsac.mask.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmsac.mask.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
// //
vfloat16m4_t test_vfnmsac_vf_f16m4_mu(vbool4_t mask, vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) { vfloat16m4_t test_vfnmsac_vf_f16m4_mu(vbool4_t mask, vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfnmsac_mu(mask, vd, rs1, vs2, vl); return __riscv_vfnmsac_mu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmsac_vv_f16m8_mu // CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmsac_vv_f16m8_mu
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmsac.mask.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmsac.mask.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
// //
vfloat16m8_t test_vfnmsac_vv_f16m8_mu(vbool2_t mask, vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) { vfloat16m8_t test_vfnmsac_vv_f16m8_mu(vbool2_t mask, vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfnmsac_mu(mask, vd, vs1, vs2, vl); return __riscv_vfnmsac_mu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmsac_vf_f16m8_mu // CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmsac_vf_f16m8_mu
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmsac.mask.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmsac.mask.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
// //
vfloat16m8_t test_vfnmsac_vf_f16m8_mu(vbool2_t mask, vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) { vfloat16m8_t test_vfnmsac_vf_f16m8_mu(vbool2_t mask, vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfnmsac_mu(mask, vd, rs1, vs2, vl); return __riscv_vfnmsac_mu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmsac_vv_f32mf2_mu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmsac_vv_f32mf2_mu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmsac.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmsac.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfnmsac_vv_f32mf2_mu(vbool64_t mask, vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) { vfloat32mf2_t test_vfnmsac_vv_f32mf2_mu(vbool64_t mask, vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfnmsac_mu(mask, vd, vs1, vs2, vl); return __riscv_vfnmsac_mu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmsac_vf_f32mf2_mu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmsac_vf_f32mf2_mu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmsac.mask.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmsac.mask.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfnmsac_vf_f32mf2_mu(vbool64_t mask, vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) { vfloat32mf2_t test_vfnmsac_vf_f32mf2_mu(vbool64_t mask, vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfnmsac_mu(mask, vd, rs1, vs2, vl); return __riscv_vfnmsac_mu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmsac_vv_f32m1_mu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmsac_vv_f32m1_mu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmsac.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmsac.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfnmsac_vv_f32m1_mu(vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) { vfloat32m1_t test_vfnmsac_vv_f32m1_mu(vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfnmsac_mu(mask, vd, vs1, vs2, vl); return __riscv_vfnmsac_mu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmsac_vf_f32m1_mu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmsac_vf_f32m1_mu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmsac.mask.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmsac.mask.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfnmsac_vf_f32m1_mu(vbool32_t mask, vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) { vfloat32m1_t test_vfnmsac_vf_f32m1_mu(vbool32_t mask, vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfnmsac_mu(mask, vd, rs1, vs2, vl); return __riscv_vfnmsac_mu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmsac_vv_f32m2_mu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmsac_vv_f32m2_mu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmsac.mask.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmsac.mask.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfnmsac_vv_f32m2_mu(vbool16_t mask, vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) { vfloat32m2_t test_vfnmsac_vv_f32m2_mu(vbool16_t mask, vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfnmsac_mu(mask, vd, vs1, vs2, vl); return __riscv_vfnmsac_mu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmsac_vf_f32m2_mu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmsac_vf_f32m2_mu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmsac.mask.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmsac.mask.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfnmsac_vf_f32m2_mu(vbool16_t mask, vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) { vfloat32m2_t test_vfnmsac_vf_f32m2_mu(vbool16_t mask, vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfnmsac_mu(mask, vd, rs1, vs2, vl); return __riscv_vfnmsac_mu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmsac_vv_f32m4_mu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmsac_vv_f32m4_mu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmsac.mask.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmsac.mask.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfnmsac_vv_f32m4_mu(vbool8_t mask, vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) { vfloat32m4_t test_vfnmsac_vv_f32m4_mu(vbool8_t mask, vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfnmsac_mu(mask, vd, vs1, vs2, vl); return __riscv_vfnmsac_mu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmsac_vf_f32m4_mu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmsac_vf_f32m4_mu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmsac.mask.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmsac.mask.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfnmsac_vf_f32m4_mu(vbool8_t mask, vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) { vfloat32m4_t test_vfnmsac_vf_f32m4_mu(vbool8_t mask, vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfnmsac_mu(mask, vd, rs1, vs2, vl); return __riscv_vfnmsac_mu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmsac_vv_f32m8_mu // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmsac_vv_f32m8_mu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmsac.mask.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmsac.mask.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfnmsac_vv_f32m8_mu(vbool4_t mask, vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) { vfloat32m8_t test_vfnmsac_vv_f32m8_mu(vbool4_t mask, vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfnmsac_mu(mask, vd, vs1, vs2, vl); return __riscv_vfnmsac_mu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmsac_vf_f32m8_mu // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmsac_vf_f32m8_mu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmsac.mask.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmsac.mask.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfnmsac_vf_f32m8_mu(vbool4_t mask, vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) { vfloat32m8_t test_vfnmsac_vf_f32m8_mu(vbool4_t mask, vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfnmsac_mu(mask, vd, rs1, vs2, vl); return __riscv_vfnmsac_mu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmsac_vv_f64m1_mu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmsac_vv_f64m1_mu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmsac.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmsac.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfnmsac_vv_f64m1_mu(vbool64_t mask, vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) { vfloat64m1_t test_vfnmsac_vv_f64m1_mu(vbool64_t mask, vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfnmsac_mu(mask, vd, vs1, vs2, vl); return __riscv_vfnmsac_mu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmsac_vf_f64m1_mu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmsac_vf_f64m1_mu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmsac.mask.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmsac.mask.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfnmsac_vf_f64m1_mu(vbool64_t mask, vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) { vfloat64m1_t test_vfnmsac_vf_f64m1_mu(vbool64_t mask, vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfnmsac_mu(mask, vd, rs1, vs2, vl); return __riscv_vfnmsac_mu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmsac_vv_f64m2_mu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmsac_vv_f64m2_mu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmsac.mask.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmsac.mask.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfnmsac_vv_f64m2_mu(vbool32_t mask, vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) { vfloat64m2_t test_vfnmsac_vv_f64m2_mu(vbool32_t mask, vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfnmsac_mu(mask, vd, vs1, vs2, vl); return __riscv_vfnmsac_mu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmsac_vf_f64m2_mu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmsac_vf_f64m2_mu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmsac.mask.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmsac.mask.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfnmsac_vf_f64m2_mu(vbool32_t mask, vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) { vfloat64m2_t test_vfnmsac_vf_f64m2_mu(vbool32_t mask, vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfnmsac_mu(mask, vd, rs1, vs2, vl); return __riscv_vfnmsac_mu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmsac_vv_f64m4_mu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmsac_vv_f64m4_mu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmsac.mask.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmsac.mask.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfnmsac_vv_f64m4_mu(vbool16_t mask, vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) { vfloat64m4_t test_vfnmsac_vv_f64m4_mu(vbool16_t mask, vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfnmsac_mu(mask, vd, vs1, vs2, vl); return __riscv_vfnmsac_mu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmsac_vf_f64m4_mu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmsac_vf_f64m4_mu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmsac.mask.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmsac.mask.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfnmsac_vf_f64m4_mu(vbool16_t mask, vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) { vfloat64m4_t test_vfnmsac_vf_f64m4_mu(vbool16_t mask, vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfnmsac_mu(mask, vd, rs1, vs2, vl); return __riscv_vfnmsac_mu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmsac_vv_f64m8_mu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmsac_vv_f64m8_mu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmsac.mask.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmsac.mask.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfnmsac_vv_f64m8_mu(vbool8_t mask, vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) { vfloat64m8_t test_vfnmsac_vv_f64m8_mu(vbool8_t mask, vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfnmsac_mu(mask, vd, vs1, vs2, vl); return __riscv_vfnmsac_mu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmsac_vf_f64m8_mu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmsac_vf_f64m8_mu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmsac.mask.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmsac.mask.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfnmsac_vf_f64m8_mu(vbool8_t mask, vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) { vfloat64m8_t test_vfnmsac_vf_f64m8_mu(vbool8_t mask, vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfnmsac_mu(mask, vd, rs1, vs2, vl); return __riscv_vfnmsac_mu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmsac_vv_f16mf4_rm_tu
// CHECK-RV64-SAME: (<vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmsac.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
//
vfloat16mf4_t test_vfnmsac_vv_f16mf4_rm_tu(vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfnmsac_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmsac_vf_f16mf4_rm_tu
// CHECK-RV64-SAME: (<vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmsac.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
//
vfloat16mf4_t test_vfnmsac_vf_f16mf4_rm_tu(vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfnmsac_tu(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmsac_vv_f16mf2_rm_tu
// CHECK-RV64-SAME: (<vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmsac.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
//
vfloat16mf2_t test_vfnmsac_vv_f16mf2_rm_tu(vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfnmsac_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmsac_vf_f16mf2_rm_tu
// CHECK-RV64-SAME: (<vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmsac.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
//
vfloat16mf2_t test_vfnmsac_vf_f16mf2_rm_tu(vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfnmsac_tu(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmsac_vv_f16m1_rm_tu
// CHECK-RV64-SAME: (<vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmsac.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfnmsac_vv_f16m1_rm_tu(vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfnmsac_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmsac_vf_f16m1_rm_tu
// CHECK-RV64-SAME: (<vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmsac.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfnmsac_vf_f16m1_rm_tu(vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfnmsac_tu(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmsac_vv_f16m2_rm_tu
// CHECK-RV64-SAME: (<vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmsac.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
//
vfloat16m2_t test_vfnmsac_vv_f16m2_rm_tu(vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfnmsac_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmsac_vf_f16m2_rm_tu
// CHECK-RV64-SAME: (<vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmsac.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
//
vfloat16m2_t test_vfnmsac_vf_f16m2_rm_tu(vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfnmsac_tu(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmsac_vv_f16m4_rm_tu
// CHECK-RV64-SAME: (<vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmsac.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
//
vfloat16m4_t test_vfnmsac_vv_f16m4_rm_tu(vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfnmsac_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmsac_vf_f16m4_rm_tu
// CHECK-RV64-SAME: (<vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmsac.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
//
vfloat16m4_t test_vfnmsac_vf_f16m4_rm_tu(vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfnmsac_tu(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmsac_vv_f16m8_rm_tu
// CHECK-RV64-SAME: (<vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmsac.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
//
vfloat16m8_t test_vfnmsac_vv_f16m8_rm_tu(vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfnmsac_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmsac_vf_f16m8_rm_tu
// CHECK-RV64-SAME: (<vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmsac.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
//
vfloat16m8_t test_vfnmsac_vf_f16m8_rm_tu(vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfnmsac_tu(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmsac_vv_f32mf2_rm_tu
// CHECK-RV64-SAME: (<vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmsac.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
//
vfloat32mf2_t test_vfnmsac_vv_f32mf2_rm_tu(vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfnmsac_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmsac_vf_f32mf2_rm_tu
// CHECK-RV64-SAME: (<vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmsac.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
//
vfloat32mf2_t test_vfnmsac_vf_f32mf2_rm_tu(vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfnmsac_tu(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmsac_vv_f32m1_rm_tu
// CHECK-RV64-SAME: (<vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmsac.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfnmsac_vv_f32m1_rm_tu(vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfnmsac_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmsac_vf_f32m1_rm_tu
// CHECK-RV64-SAME: (<vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmsac.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfnmsac_vf_f32m1_rm_tu(vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfnmsac_tu(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmsac_vv_f32m2_rm_tu
// CHECK-RV64-SAME: (<vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmsac.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
//
vfloat32m2_t test_vfnmsac_vv_f32m2_rm_tu(vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfnmsac_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmsac_vf_f32m2_rm_tu
// CHECK-RV64-SAME: (<vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmsac.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
//
vfloat32m2_t test_vfnmsac_vf_f32m2_rm_tu(vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfnmsac_tu(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmsac_vv_f32m4_rm_tu
// CHECK-RV64-SAME: (<vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmsac.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
//
vfloat32m4_t test_vfnmsac_vv_f32m4_rm_tu(vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfnmsac_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmsac_vf_f32m4_rm_tu
// CHECK-RV64-SAME: (<vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmsac.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
//
vfloat32m4_t test_vfnmsac_vf_f32m4_rm_tu(vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfnmsac_tu(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmsac_vv_f32m8_rm_tu
// CHECK-RV64-SAME: (<vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmsac.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
//
vfloat32m8_t test_vfnmsac_vv_f32m8_rm_tu(vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfnmsac_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmsac_vf_f32m8_rm_tu
// CHECK-RV64-SAME: (<vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmsac.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
//
vfloat32m8_t test_vfnmsac_vf_f32m8_rm_tu(vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfnmsac_tu(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmsac_vv_f64m1_rm_tu
// CHECK-RV64-SAME: (<vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmsac.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfnmsac_vv_f64m1_rm_tu(vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfnmsac_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmsac_vf_f64m1_rm_tu
// CHECK-RV64-SAME: (<vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmsac.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfnmsac_vf_f64m1_rm_tu(vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfnmsac_tu(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmsac_vv_f64m2_rm_tu
// CHECK-RV64-SAME: (<vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmsac.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
//
vfloat64m2_t test_vfnmsac_vv_f64m2_rm_tu(vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfnmsac_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmsac_vf_f64m2_rm_tu
// CHECK-RV64-SAME: (<vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmsac.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
//
vfloat64m2_t test_vfnmsac_vf_f64m2_rm_tu(vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfnmsac_tu(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmsac_vv_f64m4_rm_tu
// CHECK-RV64-SAME: (<vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmsac.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
//
vfloat64m4_t test_vfnmsac_vv_f64m4_rm_tu(vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfnmsac_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmsac_vf_f64m4_rm_tu
// CHECK-RV64-SAME: (<vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmsac.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
//
vfloat64m4_t test_vfnmsac_vf_f64m4_rm_tu(vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfnmsac_tu(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmsac_vv_f64m8_rm_tu
// CHECK-RV64-SAME: (<vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmsac.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
//
vfloat64m8_t test_vfnmsac_vv_f64m8_rm_tu(vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfnmsac_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmsac_vf_f64m8_rm_tu
// CHECK-RV64-SAME: (<vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmsac.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
//
vfloat64m8_t test_vfnmsac_vf_f64m8_rm_tu(vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfnmsac_tu(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmsac_vv_f16mf4_rm_tum
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmsac.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
//
vfloat16mf4_t test_vfnmsac_vv_f16mf4_rm_tum(vbool64_t mask, vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfnmsac_tum(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmsac_vf_f16mf4_rm_tum
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmsac.mask.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
//
vfloat16mf4_t test_vfnmsac_vf_f16mf4_rm_tum(vbool64_t mask, vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfnmsac_tum(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmsac_vv_f16mf2_rm_tum
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmsac.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
//
vfloat16mf2_t test_vfnmsac_vv_f16mf2_rm_tum(vbool32_t mask, vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfnmsac_tum(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmsac_vf_f16mf2_rm_tum
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmsac.mask.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
//
vfloat16mf2_t test_vfnmsac_vf_f16mf2_rm_tum(vbool32_t mask, vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfnmsac_tum(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmsac_vv_f16m1_rm_tum
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmsac.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfnmsac_vv_f16m1_rm_tum(vbool16_t mask, vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfnmsac_tum(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmsac_vf_f16m1_rm_tum
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmsac.mask.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfnmsac_vf_f16m1_rm_tum(vbool16_t mask, vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfnmsac_tum(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmsac_vv_f16m2_rm_tum
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmsac.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
//
vfloat16m2_t test_vfnmsac_vv_f16m2_rm_tum(vbool8_t mask, vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfnmsac_tum(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmsac_vf_f16m2_rm_tum
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmsac.mask.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
//
vfloat16m2_t test_vfnmsac_vf_f16m2_rm_tum(vbool8_t mask, vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfnmsac_tum(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmsac_vv_f16m4_rm_tum
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmsac.mask.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
//
vfloat16m4_t test_vfnmsac_vv_f16m4_rm_tum(vbool4_t mask, vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfnmsac_tum(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmsac_vf_f16m4_rm_tum
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmsac.mask.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
//
vfloat16m4_t test_vfnmsac_vf_f16m4_rm_tum(vbool4_t mask, vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfnmsac_tum(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmsac_vv_f16m8_rm_tum
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmsac.mask.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
//
vfloat16m8_t test_vfnmsac_vv_f16m8_rm_tum(vbool2_t mask, vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfnmsac_tum(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmsac_vf_f16m8_rm_tum
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmsac.mask.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
//
vfloat16m8_t test_vfnmsac_vf_f16m8_rm_tum(vbool2_t mask, vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfnmsac_tum(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmsac_vv_f32mf2_rm_tum
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmsac.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
//
vfloat32mf2_t test_vfnmsac_vv_f32mf2_rm_tum(vbool64_t mask, vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfnmsac_tum(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmsac_vf_f32mf2_rm_tum
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmsac.mask.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
//
vfloat32mf2_t test_vfnmsac_vf_f32mf2_rm_tum(vbool64_t mask, vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfnmsac_tum(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmsac_vv_f32m1_rm_tum
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmsac.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfnmsac_vv_f32m1_rm_tum(vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfnmsac_tum(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmsac_vf_f32m1_rm_tum
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmsac.mask.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfnmsac_vf_f32m1_rm_tum(vbool32_t mask, vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfnmsac_tum(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmsac_vv_f32m2_rm_tum
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmsac.mask.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
//
vfloat32m2_t test_vfnmsac_vv_f32m2_rm_tum(vbool16_t mask, vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfnmsac_tum(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmsac_vf_f32m2_rm_tum
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmsac.mask.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
//
vfloat32m2_t test_vfnmsac_vf_f32m2_rm_tum(vbool16_t mask, vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfnmsac_tum(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmsac_vv_f32m4_rm_tum
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmsac.mask.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
//
vfloat32m4_t test_vfnmsac_vv_f32m4_rm_tum(vbool8_t mask, vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfnmsac_tum(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmsac_vf_f32m4_rm_tum
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmsac.mask.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
//
vfloat32m4_t test_vfnmsac_vf_f32m4_rm_tum(vbool8_t mask, vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfnmsac_tum(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmsac_vv_f32m8_rm_tum
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmsac.mask.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
//
vfloat32m8_t test_vfnmsac_vv_f32m8_rm_tum(vbool4_t mask, vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfnmsac_tum(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmsac_vf_f32m8_rm_tum
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmsac.mask.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
//
vfloat32m8_t test_vfnmsac_vf_f32m8_rm_tum(vbool4_t mask, vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfnmsac_tum(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmsac_vv_f64m1_rm_tum
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmsac.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfnmsac_vv_f64m1_rm_tum(vbool64_t mask, vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfnmsac_tum(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmsac_vf_f64m1_rm_tum
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmsac.mask.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfnmsac_vf_f64m1_rm_tum(vbool64_t mask, vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfnmsac_tum(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmsac_vv_f64m2_rm_tum
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmsac.mask.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
//
vfloat64m2_t test_vfnmsac_vv_f64m2_rm_tum(vbool32_t mask, vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfnmsac_tum(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmsac_vf_f64m2_rm_tum
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmsac.mask.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
//
vfloat64m2_t test_vfnmsac_vf_f64m2_rm_tum(vbool32_t mask, vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfnmsac_tum(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmsac_vv_f64m4_rm_tum
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmsac.mask.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
//
vfloat64m4_t test_vfnmsac_vv_f64m4_rm_tum(vbool16_t mask, vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfnmsac_tum(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmsac_vf_f64m4_rm_tum
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmsac.mask.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
//
vfloat64m4_t test_vfnmsac_vf_f64m4_rm_tum(vbool16_t mask, vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfnmsac_tum(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmsac_vv_f64m8_rm_tum
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmsac.mask.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
//
vfloat64m8_t test_vfnmsac_vv_f64m8_rm_tum(vbool8_t mask, vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfnmsac_tum(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmsac_vf_f64m8_rm_tum
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmsac.mask.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
//
vfloat64m8_t test_vfnmsac_vf_f64m8_rm_tum(vbool8_t mask, vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfnmsac_tum(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmsac_vv_f16mf4_rm_tumu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmsac.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
//
vfloat16mf4_t test_vfnmsac_vv_f16mf4_rm_tumu(vbool64_t mask, vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfnmsac_tumu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmsac_vf_f16mf4_rm_tumu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmsac.mask.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
//
vfloat16mf4_t test_vfnmsac_vf_f16mf4_rm_tumu(vbool64_t mask, vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfnmsac_tumu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmsac_vv_f16mf2_rm_tumu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmsac.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
//
vfloat16mf2_t test_vfnmsac_vv_f16mf2_rm_tumu(vbool32_t mask, vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfnmsac_tumu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmsac_vf_f16mf2_rm_tumu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmsac.mask.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
//
vfloat16mf2_t test_vfnmsac_vf_f16mf2_rm_tumu(vbool32_t mask, vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfnmsac_tumu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmsac_vv_f16m1_rm_tumu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmsac.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfnmsac_vv_f16m1_rm_tumu(vbool16_t mask, vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfnmsac_tumu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmsac_vf_f16m1_rm_tumu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmsac.mask.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfnmsac_vf_f16m1_rm_tumu(vbool16_t mask, vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfnmsac_tumu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmsac_vv_f16m2_rm_tumu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmsac.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
//
vfloat16m2_t test_vfnmsac_vv_f16m2_rm_tumu(vbool8_t mask, vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfnmsac_tumu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmsac_vf_f16m2_rm_tumu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmsac.mask.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
//
vfloat16m2_t test_vfnmsac_vf_f16m2_rm_tumu(vbool8_t mask, vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfnmsac_tumu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmsac_vv_f16m4_rm_tumu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmsac.mask.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
//
vfloat16m4_t test_vfnmsac_vv_f16m4_rm_tumu(vbool4_t mask, vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfnmsac_tumu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmsac_vf_f16m4_rm_tumu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmsac.mask.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
//
vfloat16m4_t test_vfnmsac_vf_f16m4_rm_tumu(vbool4_t mask, vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfnmsac_tumu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmsac_vv_f16m8_rm_tumu
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmsac.mask.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
//
vfloat16m8_t test_vfnmsac_vv_f16m8_rm_tumu(vbool2_t mask, vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfnmsac_tumu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmsac_vf_f16m8_rm_tumu
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmsac.mask.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
//
vfloat16m8_t test_vfnmsac_vf_f16m8_rm_tumu(vbool2_t mask, vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfnmsac_tumu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmsac_vv_f32mf2_rm_tumu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmsac.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
//
vfloat32mf2_t test_vfnmsac_vv_f32mf2_rm_tumu(vbool64_t mask, vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfnmsac_tumu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmsac_vf_f32mf2_rm_tumu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmsac.mask.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
//
vfloat32mf2_t test_vfnmsac_vf_f32mf2_rm_tumu(vbool64_t mask, vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfnmsac_tumu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmsac_vv_f32m1_rm_tumu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmsac.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfnmsac_vv_f32m1_rm_tumu(vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfnmsac_tumu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmsac_vf_f32m1_rm_tumu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmsac.mask.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfnmsac_vf_f32m1_rm_tumu(vbool32_t mask, vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfnmsac_tumu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmsac_vv_f32m2_rm_tumu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmsac.mask.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
//
vfloat32m2_t test_vfnmsac_vv_f32m2_rm_tumu(vbool16_t mask, vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfnmsac_tumu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmsac_vf_f32m2_rm_tumu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmsac.mask.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
//
vfloat32m2_t test_vfnmsac_vf_f32m2_rm_tumu(vbool16_t mask, vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfnmsac_tumu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmsac_vv_f32m4_rm_tumu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmsac.mask.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
//
vfloat32m4_t test_vfnmsac_vv_f32m4_rm_tumu(vbool8_t mask, vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfnmsac_tumu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmsac_vf_f32m4_rm_tumu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmsac.mask.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
//
vfloat32m4_t test_vfnmsac_vf_f32m4_rm_tumu(vbool8_t mask, vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfnmsac_tumu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmsac_vv_f32m8_rm_tumu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmsac.mask.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
//
vfloat32m8_t test_vfnmsac_vv_f32m8_rm_tumu(vbool4_t mask, vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfnmsac_tumu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmsac_vf_f32m8_rm_tumu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmsac.mask.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
//
vfloat32m8_t test_vfnmsac_vf_f32m8_rm_tumu(vbool4_t mask, vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfnmsac_tumu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmsac_vv_f64m1_rm_tumu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmsac.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfnmsac_vv_f64m1_rm_tumu(vbool64_t mask, vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfnmsac_tumu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmsac_vf_f64m1_rm_tumu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmsac.mask.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfnmsac_vf_f64m1_rm_tumu(vbool64_t mask, vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfnmsac_tumu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmsac_vv_f64m2_rm_tumu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmsac.mask.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
//
vfloat64m2_t test_vfnmsac_vv_f64m2_rm_tumu(vbool32_t mask, vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfnmsac_tumu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmsac_vf_f64m2_rm_tumu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmsac.mask.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
//
vfloat64m2_t test_vfnmsac_vf_f64m2_rm_tumu(vbool32_t mask, vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfnmsac_tumu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmsac_vv_f64m4_rm_tumu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmsac.mask.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
//
vfloat64m4_t test_vfnmsac_vv_f64m4_rm_tumu(vbool16_t mask, vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfnmsac_tumu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmsac_vf_f64m4_rm_tumu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmsac.mask.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
//
vfloat64m4_t test_vfnmsac_vf_f64m4_rm_tumu(vbool16_t mask, vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfnmsac_tumu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmsac_vv_f64m8_rm_tumu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmsac.mask.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
//
vfloat64m8_t test_vfnmsac_vv_f64m8_rm_tumu(vbool8_t mask, vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfnmsac_tumu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmsac_vf_f64m8_rm_tumu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmsac.mask.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
//
vfloat64m8_t test_vfnmsac_vf_f64m8_rm_tumu(vbool8_t mask, vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfnmsac_tumu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmsac_vv_f16mf4_rm_mu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmsac.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
//
vfloat16mf4_t test_vfnmsac_vv_f16mf4_rm_mu(vbool64_t mask, vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfnmsac_mu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmsac_vf_f16mf4_rm_mu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmsac.mask.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
//
vfloat16mf4_t test_vfnmsac_vf_f16mf4_rm_mu(vbool64_t mask, vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfnmsac_mu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmsac_vv_f16mf2_rm_mu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmsac.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
//
vfloat16mf2_t test_vfnmsac_vv_f16mf2_rm_mu(vbool32_t mask, vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfnmsac_mu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmsac_vf_f16mf2_rm_mu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmsac.mask.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
//
vfloat16mf2_t test_vfnmsac_vf_f16mf2_rm_mu(vbool32_t mask, vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfnmsac_mu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmsac_vv_f16m1_rm_mu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmsac.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfnmsac_vv_f16m1_rm_mu(vbool16_t mask, vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfnmsac_mu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmsac_vf_f16m1_rm_mu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmsac.mask.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfnmsac_vf_f16m1_rm_mu(vbool16_t mask, vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfnmsac_mu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmsac_vv_f16m2_rm_mu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmsac.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
//
vfloat16m2_t test_vfnmsac_vv_f16m2_rm_mu(vbool8_t mask, vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfnmsac_mu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmsac_vf_f16m2_rm_mu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmsac.mask.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
//
vfloat16m2_t test_vfnmsac_vf_f16m2_rm_mu(vbool8_t mask, vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfnmsac_mu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmsac_vv_f16m4_rm_mu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmsac.mask.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
//
vfloat16m4_t test_vfnmsac_vv_f16m4_rm_mu(vbool4_t mask, vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfnmsac_mu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmsac_vf_f16m4_rm_mu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmsac.mask.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
//
vfloat16m4_t test_vfnmsac_vf_f16m4_rm_mu(vbool4_t mask, vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfnmsac_mu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmsac_vv_f16m8_rm_mu
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmsac.mask.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
//
vfloat16m8_t test_vfnmsac_vv_f16m8_rm_mu(vbool2_t mask, vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfnmsac_mu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmsac_vf_f16m8_rm_mu
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmsac.mask.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
//
vfloat16m8_t test_vfnmsac_vf_f16m8_rm_mu(vbool2_t mask, vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfnmsac_mu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmsac_vv_f32mf2_rm_mu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmsac.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
//
vfloat32mf2_t test_vfnmsac_vv_f32mf2_rm_mu(vbool64_t mask, vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfnmsac_mu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmsac_vf_f32mf2_rm_mu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmsac.mask.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
//
vfloat32mf2_t test_vfnmsac_vf_f32mf2_rm_mu(vbool64_t mask, vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfnmsac_mu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmsac_vv_f32m1_rm_mu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmsac.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfnmsac_vv_f32m1_rm_mu(vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfnmsac_mu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmsac_vf_f32m1_rm_mu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmsac.mask.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfnmsac_vf_f32m1_rm_mu(vbool32_t mask, vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfnmsac_mu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmsac_vv_f32m2_rm_mu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmsac.mask.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
//
vfloat32m2_t test_vfnmsac_vv_f32m2_rm_mu(vbool16_t mask, vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfnmsac_mu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmsac_vf_f32m2_rm_mu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmsac.mask.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
//
vfloat32m2_t test_vfnmsac_vf_f32m2_rm_mu(vbool16_t mask, vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfnmsac_mu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmsac_vv_f32m4_rm_mu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmsac.mask.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
//
vfloat32m4_t test_vfnmsac_vv_f32m4_rm_mu(vbool8_t mask, vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfnmsac_mu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmsac_vf_f32m4_rm_mu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmsac.mask.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
//
vfloat32m4_t test_vfnmsac_vf_f32m4_rm_mu(vbool8_t mask, vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfnmsac_mu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmsac_vv_f32m8_rm_mu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmsac.mask.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
//
vfloat32m8_t test_vfnmsac_vv_f32m8_rm_mu(vbool4_t mask, vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfnmsac_mu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmsac_vf_f32m8_rm_mu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmsac.mask.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
//
vfloat32m8_t test_vfnmsac_vf_f32m8_rm_mu(vbool4_t mask, vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfnmsac_mu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmsac_vv_f64m1_rm_mu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmsac.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfnmsac_vv_f64m1_rm_mu(vbool64_t mask, vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfnmsac_mu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmsac_vf_f64m1_rm_mu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmsac.mask.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfnmsac_vf_f64m1_rm_mu(vbool64_t mask, vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfnmsac_mu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmsac_vv_f64m2_rm_mu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmsac.mask.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
//
vfloat64m2_t test_vfnmsac_vv_f64m2_rm_mu(vbool32_t mask, vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfnmsac_mu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmsac_vf_f64m2_rm_mu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmsac.mask.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
//
vfloat64m2_t test_vfnmsac_vf_f64m2_rm_mu(vbool32_t mask, vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfnmsac_mu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmsac_vv_f64m4_rm_mu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmsac.mask.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
//
vfloat64m4_t test_vfnmsac_vv_f64m4_rm_mu(vbool16_t mask, vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfnmsac_mu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmsac_vf_f64m4_rm_mu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmsac.mask.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
//
vfloat64m4_t test_vfnmsac_vf_f64m4_rm_mu(vbool16_t mask, vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfnmsac_mu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmsac_vv_f64m8_rm_mu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmsac.mask.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
//
vfloat64m8_t test_vfnmsac_vv_f64m8_rm_mu(vbool8_t mask, vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfnmsac_mu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmsac_vf_f64m8_rm_mu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmsac.mask.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
//
vfloat64m8_t test_vfnmsac_vf_f64m8_rm_mu(vbool8_t mask, vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfnmsac_mu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}

clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/policy/overloaded/vfnmsub.c

// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 2
// REQUIRES: riscv-registered-target // REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh \ // RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh \
// RUN: -target-feature +experimental-zvfh -disable-O0-optnone \ // RUN: -target-feature +experimental-zvfh -disable-O0-optnone \
// RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \ // RUN: -emit-llvm %s -o - | opt -S -passes=mem2reg | \
// RUN: FileCheck --check-prefix=CHECK-RV64 %s // RUN: FileCheck --check-prefix=CHECK-RV64 %s
#include <riscv_vector.h> #include <riscv_vector.h>
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmsub_vv_f16mf4_tu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmsub_vv_f16mf4_tu
// CHECK-RV64-SAME: (<vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] { // CHECK-RV64-SAME: (<vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0:[0-9]+]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmsub.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmsub.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
// //
vfloat16mf4_t test_vfnmsub_vv_f16mf4_tu(vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) { vfloat16mf4_t test_vfnmsub_vv_f16mf4_tu(vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfnmsub_tu(vd, vs1, vs2, vl); return __riscv_vfnmsub_tu(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmsub_vf_f16mf4_tu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmsub_vf_f16mf4_tu
// CHECK-RV64-SAME: (<vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmsub.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmsub.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
// //
vfloat16mf4_t test_vfnmsub_vf_f16mf4_tu(vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) { vfloat16mf4_t test_vfnmsub_vf_f16mf4_tu(vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfnmsub_tu(vd, rs1, vs2, vl); return __riscv_vfnmsub_tu(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmsub_vv_f16mf2_tu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmsub_vv_f16mf2_tu
// CHECK-RV64-SAME: (<vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmsub.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmsub.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
// //
vfloat16mf2_t test_vfnmsub_vv_f16mf2_tu(vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) { vfloat16mf2_t test_vfnmsub_vv_f16mf2_tu(vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfnmsub_tu(vd, vs1, vs2, vl); return __riscv_vfnmsub_tu(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmsub_vf_f16mf2_tu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmsub_vf_f16mf2_tu
// CHECK-RV64-SAME: (<vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmsub.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmsub.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
// //
vfloat16mf2_t test_vfnmsub_vf_f16mf2_tu(vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) { vfloat16mf2_t test_vfnmsub_vf_f16mf2_tu(vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfnmsub_tu(vd, rs1, vs2, vl); return __riscv_vfnmsub_tu(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmsub_vv_f16m1_tu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmsub_vv_f16m1_tu
// CHECK-RV64-SAME: (<vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmsub.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmsub.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
// //
vfloat16m1_t test_vfnmsub_vv_f16m1_tu(vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) { vfloat16m1_t test_vfnmsub_vv_f16m1_tu(vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfnmsub_tu(vd, vs1, vs2, vl); return __riscv_vfnmsub_tu(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmsub_vf_f16m1_tu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmsub_vf_f16m1_tu
// CHECK-RV64-SAME: (<vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmsub.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmsub.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
// //
vfloat16m1_t test_vfnmsub_vf_f16m1_tu(vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) { vfloat16m1_t test_vfnmsub_vf_f16m1_tu(vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfnmsub_tu(vd, rs1, vs2, vl); return __riscv_vfnmsub_tu(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmsub_vv_f16m2_tu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmsub_vv_f16m2_tu
// CHECK-RV64-SAME: (<vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmsub.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmsub.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
// //
vfloat16m2_t test_vfnmsub_vv_f16m2_tu(vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) { vfloat16m2_t test_vfnmsub_vv_f16m2_tu(vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfnmsub_tu(vd, vs1, vs2, vl); return __riscv_vfnmsub_tu(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmsub_vf_f16m2_tu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmsub_vf_f16m2_tu
// CHECK-RV64-SAME: (<vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmsub.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmsub.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
// //
vfloat16m2_t test_vfnmsub_vf_f16m2_tu(vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) { vfloat16m2_t test_vfnmsub_vf_f16m2_tu(vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfnmsub_tu(vd, rs1, vs2, vl); return __riscv_vfnmsub_tu(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmsub_vv_f16m4_tu // CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmsub_vv_f16m4_tu
// CHECK-RV64-SAME: (<vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmsub.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmsub.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
// //
vfloat16m4_t test_vfnmsub_vv_f16m4_tu(vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) { vfloat16m4_t test_vfnmsub_vv_f16m4_tu(vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfnmsub_tu(vd, vs1, vs2, vl); return __riscv_vfnmsub_tu(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmsub_vf_f16m4_tu // CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmsub_vf_f16m4_tu
// CHECK-RV64-SAME: (<vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmsub.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmsub.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
// //
vfloat16m4_t test_vfnmsub_vf_f16m4_tu(vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) { vfloat16m4_t test_vfnmsub_vf_f16m4_tu(vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfnmsub_tu(vd, rs1, vs2, vl); return __riscv_vfnmsub_tu(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmsub_vv_f16m8_tu // CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmsub_vv_f16m8_tu
// CHECK-RV64-SAME: (<vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmsub.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmsub.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
// //
vfloat16m8_t test_vfnmsub_vv_f16m8_tu(vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) { vfloat16m8_t test_vfnmsub_vv_f16m8_tu(vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfnmsub_tu(vd, vs1, vs2, vl); return __riscv_vfnmsub_tu(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmsub_vf_f16m8_tu // CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmsub_vf_f16m8_tu
// CHECK-RV64-SAME: (<vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmsub.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmsub.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
// //
vfloat16m8_t test_vfnmsub_vf_f16m8_tu(vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) { vfloat16m8_t test_vfnmsub_vf_f16m8_tu(vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfnmsub_tu(vd, rs1, vs2, vl); return __riscv_vfnmsub_tu(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmsub_vv_f32mf2_tu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmsub_vv_f32mf2_tu
// CHECK-RV64-SAME: (<vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmsub.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmsub.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfnmsub_vv_f32mf2_tu(vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) { vfloat32mf2_t test_vfnmsub_vv_f32mf2_tu(vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfnmsub_tu(vd, vs1, vs2, vl); return __riscv_vfnmsub_tu(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmsub_vf_f32mf2_tu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmsub_vf_f32mf2_tu
// CHECK-RV64-SAME: (<vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmsub.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmsub.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfnmsub_vf_f32mf2_tu(vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) { vfloat32mf2_t test_vfnmsub_vf_f32mf2_tu(vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfnmsub_tu(vd, rs1, vs2, vl); return __riscv_vfnmsub_tu(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmsub_vv_f32m1_tu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmsub_vv_f32m1_tu
// CHECK-RV64-SAME: (<vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmsub.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmsub.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfnmsub_vv_f32m1_tu(vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) { vfloat32m1_t test_vfnmsub_vv_f32m1_tu(vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfnmsub_tu(vd, vs1, vs2, vl); return __riscv_vfnmsub_tu(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmsub_vf_f32m1_tu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmsub_vf_f32m1_tu
// CHECK-RV64-SAME: (<vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmsub.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmsub.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfnmsub_vf_f32m1_tu(vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) { vfloat32m1_t test_vfnmsub_vf_f32m1_tu(vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfnmsub_tu(vd, rs1, vs2, vl); return __riscv_vfnmsub_tu(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmsub_vv_f32m2_tu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmsub_vv_f32m2_tu
// CHECK-RV64-SAME: (<vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmsub.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmsub.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfnmsub_vv_f32m2_tu(vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) { vfloat32m2_t test_vfnmsub_vv_f32m2_tu(vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfnmsub_tu(vd, vs1, vs2, vl); return __riscv_vfnmsub_tu(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmsub_vf_f32m2_tu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmsub_vf_f32m2_tu
// CHECK-RV64-SAME: (<vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmsub.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmsub.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfnmsub_vf_f32m2_tu(vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) { vfloat32m2_t test_vfnmsub_vf_f32m2_tu(vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfnmsub_tu(vd, rs1, vs2, vl); return __riscv_vfnmsub_tu(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmsub_vv_f32m4_tu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmsub_vv_f32m4_tu
// CHECK-RV64-SAME: (<vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmsub.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmsub.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfnmsub_vv_f32m4_tu(vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) { vfloat32m4_t test_vfnmsub_vv_f32m4_tu(vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfnmsub_tu(vd, vs1, vs2, vl); return __riscv_vfnmsub_tu(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmsub_vf_f32m4_tu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmsub_vf_f32m4_tu
// CHECK-RV64-SAME: (<vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmsub.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmsub.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfnmsub_vf_f32m4_tu(vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) { vfloat32m4_t test_vfnmsub_vf_f32m4_tu(vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfnmsub_tu(vd, rs1, vs2, vl); return __riscv_vfnmsub_tu(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmsub_vv_f32m8_tu // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmsub_vv_f32m8_tu
// CHECK-RV64-SAME: (<vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmsub.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmsub.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfnmsub_vv_f32m8_tu(vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) { vfloat32m8_t test_vfnmsub_vv_f32m8_tu(vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfnmsub_tu(vd, vs1, vs2, vl); return __riscv_vfnmsub_tu(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmsub_vf_f32m8_tu // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmsub_vf_f32m8_tu
// CHECK-RV64-SAME: (<vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmsub.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmsub.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfnmsub_vf_f32m8_tu(vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) { vfloat32m8_t test_vfnmsub_vf_f32m8_tu(vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfnmsub_tu(vd, rs1, vs2, vl); return __riscv_vfnmsub_tu(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmsub_vv_f64m1_tu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmsub_vv_f64m1_tu
// CHECK-RV64-SAME: (<vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmsub.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmsub.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfnmsub_vv_f64m1_tu(vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) { vfloat64m1_t test_vfnmsub_vv_f64m1_tu(vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfnmsub_tu(vd, vs1, vs2, vl); return __riscv_vfnmsub_tu(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmsub_vf_f64m1_tu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmsub_vf_f64m1_tu
// CHECK-RV64-SAME: (<vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmsub.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmsub.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfnmsub_vf_f64m1_tu(vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) { vfloat64m1_t test_vfnmsub_vf_f64m1_tu(vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfnmsub_tu(vd, rs1, vs2, vl); return __riscv_vfnmsub_tu(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmsub_vv_f64m2_tu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmsub_vv_f64m2_tu
// CHECK-RV64-SAME: (<vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmsub.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmsub.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfnmsub_vv_f64m2_tu(vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) { vfloat64m2_t test_vfnmsub_vv_f64m2_tu(vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfnmsub_tu(vd, vs1, vs2, vl); return __riscv_vfnmsub_tu(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmsub_vf_f64m2_tu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmsub_vf_f64m2_tu
// CHECK-RV64-SAME: (<vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmsub.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmsub.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfnmsub_vf_f64m2_tu(vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) { vfloat64m2_t test_vfnmsub_vf_f64m2_tu(vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfnmsub_tu(vd, rs1, vs2, vl); return __riscv_vfnmsub_tu(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmsub_vv_f64m4_tu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmsub_vv_f64m4_tu
// CHECK-RV64-SAME: (<vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmsub.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmsub.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfnmsub_vv_f64m4_tu(vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) { vfloat64m4_t test_vfnmsub_vv_f64m4_tu(vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfnmsub_tu(vd, vs1, vs2, vl); return __riscv_vfnmsub_tu(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmsub_vf_f64m4_tu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmsub_vf_f64m4_tu
// CHECK-RV64-SAME: (<vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmsub.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmsub.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfnmsub_vf_f64m4_tu(vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) { vfloat64m4_t test_vfnmsub_vf_f64m4_tu(vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfnmsub_tu(vd, rs1, vs2, vl); return __riscv_vfnmsub_tu(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmsub_vv_f64m8_tu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmsub_vv_f64m8_tu
// CHECK-RV64-SAME: (<vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmsub.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmsub.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfnmsub_vv_f64m8_tu(vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) { vfloat64m8_t test_vfnmsub_vv_f64m8_tu(vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfnmsub_tu(vd, vs1, vs2, vl); return __riscv_vfnmsub_tu(vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmsub_vf_f64m8_tu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmsub_vf_f64m8_tu
// CHECK-RV64-SAME: (<vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmsub.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmsub.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfnmsub_vf_f64m8_tu(vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) { vfloat64m8_t test_vfnmsub_vf_f64m8_tu(vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfnmsub_tu(vd, rs1, vs2, vl); return __riscv_vfnmsub_tu(vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmsub_vv_f16mf4_tum // CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmsub_vv_f16mf4_tum
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmsub.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmsub.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
// //
vfloat16mf4_t test_vfnmsub_vv_f16mf4_tum(vbool64_t mask, vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) { vfloat16mf4_t test_vfnmsub_vv_f16mf4_tum(vbool64_t mask, vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfnmsub_tum(mask, vd, vs1, vs2, vl); return __riscv_vfnmsub_tum(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmsub_vf_f16mf4_tum // CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmsub_vf_f16mf4_tum
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmsub.mask.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmsub.mask.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
// //
vfloat16mf4_t test_vfnmsub_vf_f16mf4_tum(vbool64_t mask, vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) { vfloat16mf4_t test_vfnmsub_vf_f16mf4_tum(vbool64_t mask, vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfnmsub_tum(mask, vd, rs1, vs2, vl); return __riscv_vfnmsub_tum(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmsub_vv_f16mf2_tum // CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmsub_vv_f16mf2_tum
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmsub.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmsub.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
// //
vfloat16mf2_t test_vfnmsub_vv_f16mf2_tum(vbool32_t mask, vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) { vfloat16mf2_t test_vfnmsub_vv_f16mf2_tum(vbool32_t mask, vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfnmsub_tum(mask, vd, vs1, vs2, vl); return __riscv_vfnmsub_tum(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmsub_vf_f16mf2_tum // CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmsub_vf_f16mf2_tum
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmsub.mask.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmsub.mask.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
// //
vfloat16mf2_t test_vfnmsub_vf_f16mf2_tum(vbool32_t mask, vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) { vfloat16mf2_t test_vfnmsub_vf_f16mf2_tum(vbool32_t mask, vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfnmsub_tum(mask, vd, rs1, vs2, vl); return __riscv_vfnmsub_tum(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmsub_vv_f16m1_tum // CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmsub_vv_f16m1_tum
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmsub.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmsub.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
// //
vfloat16m1_t test_vfnmsub_vv_f16m1_tum(vbool16_t mask, vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) { vfloat16m1_t test_vfnmsub_vv_f16m1_tum(vbool16_t mask, vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfnmsub_tum(mask, vd, vs1, vs2, vl); return __riscv_vfnmsub_tum(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmsub_vf_f16m1_tum // CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmsub_vf_f16m1_tum
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmsub.mask.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmsub.mask.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
// //
vfloat16m1_t test_vfnmsub_vf_f16m1_tum(vbool16_t mask, vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) { vfloat16m1_t test_vfnmsub_vf_f16m1_tum(vbool16_t mask, vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfnmsub_tum(mask, vd, rs1, vs2, vl); return __riscv_vfnmsub_tum(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmsub_vv_f16m2_tum // CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmsub_vv_f16m2_tum
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmsub.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmsub.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
// //
vfloat16m2_t test_vfnmsub_vv_f16m2_tum(vbool8_t mask, vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) { vfloat16m2_t test_vfnmsub_vv_f16m2_tum(vbool8_t mask, vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfnmsub_tum(mask, vd, vs1, vs2, vl); return __riscv_vfnmsub_tum(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmsub_vf_f16m2_tum // CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmsub_vf_f16m2_tum
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmsub.mask.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmsub.mask.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
// //
vfloat16m2_t test_vfnmsub_vf_f16m2_tum(vbool8_t mask, vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) { vfloat16m2_t test_vfnmsub_vf_f16m2_tum(vbool8_t mask, vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfnmsub_tum(mask, vd, rs1, vs2, vl); return __riscv_vfnmsub_tum(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmsub_vv_f16m4_tum // CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmsub_vv_f16m4_tum
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmsub.mask.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmsub.mask.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
// //
vfloat16m4_t test_vfnmsub_vv_f16m4_tum(vbool4_t mask, vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) { vfloat16m4_t test_vfnmsub_vv_f16m4_tum(vbool4_t mask, vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfnmsub_tum(mask, vd, vs1, vs2, vl); return __riscv_vfnmsub_tum(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmsub_vf_f16m4_tum // CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmsub_vf_f16m4_tum
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmsub.mask.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmsub.mask.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
// //
vfloat16m4_t test_vfnmsub_vf_f16m4_tum(vbool4_t mask, vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) { vfloat16m4_t test_vfnmsub_vf_f16m4_tum(vbool4_t mask, vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfnmsub_tum(mask, vd, rs1, vs2, vl); return __riscv_vfnmsub_tum(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmsub_vv_f16m8_tum // CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmsub_vv_f16m8_tum
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmsub.mask.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmsub.mask.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
// //
vfloat16m8_t test_vfnmsub_vv_f16m8_tum(vbool2_t mask, vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) { vfloat16m8_t test_vfnmsub_vv_f16m8_tum(vbool2_t mask, vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfnmsub_tum(mask, vd, vs1, vs2, vl); return __riscv_vfnmsub_tum(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmsub_vf_f16m8_tum // CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmsub_vf_f16m8_tum
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmsub.mask.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmsub.mask.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
// //
vfloat16m8_t test_vfnmsub_vf_f16m8_tum(vbool2_t mask, vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) { vfloat16m8_t test_vfnmsub_vf_f16m8_tum(vbool2_t mask, vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfnmsub_tum(mask, vd, rs1, vs2, vl); return __riscv_vfnmsub_tum(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmsub_vv_f32mf2_tum // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmsub_vv_f32mf2_tum
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmsub.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmsub.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfnmsub_vv_f32mf2_tum(vbool64_t mask, vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) { vfloat32mf2_t test_vfnmsub_vv_f32mf2_tum(vbool64_t mask, vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfnmsub_tum(mask, vd, vs1, vs2, vl); return __riscv_vfnmsub_tum(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmsub_vf_f32mf2_tum // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmsub_vf_f32mf2_tum
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmsub.mask.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmsub.mask.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfnmsub_vf_f32mf2_tum(vbool64_t mask, vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) { vfloat32mf2_t test_vfnmsub_vf_f32mf2_tum(vbool64_t mask, vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfnmsub_tum(mask, vd, rs1, vs2, vl); return __riscv_vfnmsub_tum(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmsub_vv_f32m1_tum // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmsub_vv_f32m1_tum
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmsub.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmsub.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfnmsub_vv_f32m1_tum(vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) { vfloat32m1_t test_vfnmsub_vv_f32m1_tum(vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfnmsub_tum(mask, vd, vs1, vs2, vl); return __riscv_vfnmsub_tum(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmsub_vf_f32m1_tum // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmsub_vf_f32m1_tum
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmsub.mask.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmsub.mask.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfnmsub_vf_f32m1_tum(vbool32_t mask, vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) { vfloat32m1_t test_vfnmsub_vf_f32m1_tum(vbool32_t mask, vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfnmsub_tum(mask, vd, rs1, vs2, vl); return __riscv_vfnmsub_tum(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmsub_vv_f32m2_tum // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmsub_vv_f32m2_tum
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmsub.mask.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmsub.mask.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfnmsub_vv_f32m2_tum(vbool16_t mask, vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) { vfloat32m2_t test_vfnmsub_vv_f32m2_tum(vbool16_t mask, vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfnmsub_tum(mask, vd, vs1, vs2, vl); return __riscv_vfnmsub_tum(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmsub_vf_f32m2_tum // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmsub_vf_f32m2_tum
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmsub.mask.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmsub.mask.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfnmsub_vf_f32m2_tum(vbool16_t mask, vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) { vfloat32m2_t test_vfnmsub_vf_f32m2_tum(vbool16_t mask, vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfnmsub_tum(mask, vd, rs1, vs2, vl); return __riscv_vfnmsub_tum(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmsub_vv_f32m4_tum // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmsub_vv_f32m4_tum
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmsub.mask.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmsub.mask.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfnmsub_vv_f32m4_tum(vbool8_t mask, vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) { vfloat32m4_t test_vfnmsub_vv_f32m4_tum(vbool8_t mask, vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfnmsub_tum(mask, vd, vs1, vs2, vl); return __riscv_vfnmsub_tum(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmsub_vf_f32m4_tum // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmsub_vf_f32m4_tum
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmsub.mask.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmsub.mask.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfnmsub_vf_f32m4_tum(vbool8_t mask, vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) { vfloat32m4_t test_vfnmsub_vf_f32m4_tum(vbool8_t mask, vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfnmsub_tum(mask, vd, rs1, vs2, vl); return __riscv_vfnmsub_tum(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmsub_vv_f32m8_tum // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmsub_vv_f32m8_tum
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmsub.mask.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmsub.mask.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfnmsub_vv_f32m8_tum(vbool4_t mask, vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) { vfloat32m8_t test_vfnmsub_vv_f32m8_tum(vbool4_t mask, vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfnmsub_tum(mask, vd, vs1, vs2, vl); return __riscv_vfnmsub_tum(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmsub_vf_f32m8_tum // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmsub_vf_f32m8_tum
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmsub.mask.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmsub.mask.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfnmsub_vf_f32m8_tum(vbool4_t mask, vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) { vfloat32m8_t test_vfnmsub_vf_f32m8_tum(vbool4_t mask, vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfnmsub_tum(mask, vd, rs1, vs2, vl); return __riscv_vfnmsub_tum(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmsub_vv_f64m1_tum // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmsub_vv_f64m1_tum
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmsub.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmsub.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfnmsub_vv_f64m1_tum(vbool64_t mask, vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) { vfloat64m1_t test_vfnmsub_vv_f64m1_tum(vbool64_t mask, vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfnmsub_tum(mask, vd, vs1, vs2, vl); return __riscv_vfnmsub_tum(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmsub_vf_f64m1_tum // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmsub_vf_f64m1_tum
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmsub.mask.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmsub.mask.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfnmsub_vf_f64m1_tum(vbool64_t mask, vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) { vfloat64m1_t test_vfnmsub_vf_f64m1_tum(vbool64_t mask, vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfnmsub_tum(mask, vd, rs1, vs2, vl); return __riscv_vfnmsub_tum(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmsub_vv_f64m2_tum // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmsub_vv_f64m2_tum
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmsub.mask.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmsub.mask.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfnmsub_vv_f64m2_tum(vbool32_t mask, vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) { vfloat64m2_t test_vfnmsub_vv_f64m2_tum(vbool32_t mask, vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfnmsub_tum(mask, vd, vs1, vs2, vl); return __riscv_vfnmsub_tum(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmsub_vf_f64m2_tum // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmsub_vf_f64m2_tum
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmsub.mask.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmsub.mask.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfnmsub_vf_f64m2_tum(vbool32_t mask, vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) { vfloat64m2_t test_vfnmsub_vf_f64m2_tum(vbool32_t mask, vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfnmsub_tum(mask, vd, rs1, vs2, vl); return __riscv_vfnmsub_tum(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmsub_vv_f64m4_tum // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmsub_vv_f64m4_tum
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmsub.mask.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmsub.mask.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfnmsub_vv_f64m4_tum(vbool16_t mask, vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) { vfloat64m4_t test_vfnmsub_vv_f64m4_tum(vbool16_t mask, vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfnmsub_tum(mask, vd, vs1, vs2, vl); return __riscv_vfnmsub_tum(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmsub_vf_f64m4_tum // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmsub_vf_f64m4_tum
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmsub.mask.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmsub.mask.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfnmsub_vf_f64m4_tum(vbool16_t mask, vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) { vfloat64m4_t test_vfnmsub_vf_f64m4_tum(vbool16_t mask, vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfnmsub_tum(mask, vd, rs1, vs2, vl); return __riscv_vfnmsub_tum(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmsub_vv_f64m8_tum // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmsub_vv_f64m8_tum
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmsub.mask.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmsub.mask.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfnmsub_vv_f64m8_tum(vbool8_t mask, vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) { vfloat64m8_t test_vfnmsub_vv_f64m8_tum(vbool8_t mask, vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfnmsub_tum(mask, vd, vs1, vs2, vl); return __riscv_vfnmsub_tum(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmsub_vf_f64m8_tum // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmsub_vf_f64m8_tum
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmsub.mask.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 2) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmsub.mask.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfnmsub_vf_f64m8_tum(vbool8_t mask, vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) { vfloat64m8_t test_vfnmsub_vf_f64m8_tum(vbool8_t mask, vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfnmsub_tum(mask, vd, rs1, vs2, vl); return __riscv_vfnmsub_tum(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmsub_vv_f16mf4_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmsub_vv_f16mf4_tumu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmsub.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmsub.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
// //
vfloat16mf4_t test_vfnmsub_vv_f16mf4_tumu(vbool64_t mask, vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) { vfloat16mf4_t test_vfnmsub_vv_f16mf4_tumu(vbool64_t mask, vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfnmsub_tumu(mask, vd, vs1, vs2, vl); return __riscv_vfnmsub_tumu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmsub_vf_f16mf4_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmsub_vf_f16mf4_tumu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmsub.mask.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmsub.mask.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
// //
vfloat16mf4_t test_vfnmsub_vf_f16mf4_tumu(vbool64_t mask, vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) { vfloat16mf4_t test_vfnmsub_vf_f16mf4_tumu(vbool64_t mask, vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfnmsub_tumu(mask, vd, rs1, vs2, vl); return __riscv_vfnmsub_tumu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmsub_vv_f16mf2_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmsub_vv_f16mf2_tumu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmsub.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmsub.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
// //
vfloat16mf2_t test_vfnmsub_vv_f16mf2_tumu(vbool32_t mask, vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) { vfloat16mf2_t test_vfnmsub_vv_f16mf2_tumu(vbool32_t mask, vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfnmsub_tumu(mask, vd, vs1, vs2, vl); return __riscv_vfnmsub_tumu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmsub_vf_f16mf2_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmsub_vf_f16mf2_tumu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmsub.mask.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmsub.mask.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
// //
vfloat16mf2_t test_vfnmsub_vf_f16mf2_tumu(vbool32_t mask, vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) { vfloat16mf2_t test_vfnmsub_vf_f16mf2_tumu(vbool32_t mask, vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfnmsub_tumu(mask, vd, rs1, vs2, vl); return __riscv_vfnmsub_tumu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmsub_vv_f16m1_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmsub_vv_f16m1_tumu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmsub.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmsub.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
// //
vfloat16m1_t test_vfnmsub_vv_f16m1_tumu(vbool16_t mask, vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) { vfloat16m1_t test_vfnmsub_vv_f16m1_tumu(vbool16_t mask, vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfnmsub_tumu(mask, vd, vs1, vs2, vl); return __riscv_vfnmsub_tumu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmsub_vf_f16m1_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmsub_vf_f16m1_tumu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmsub.mask.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmsub.mask.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
// //
vfloat16m1_t test_vfnmsub_vf_f16m1_tumu(vbool16_t mask, vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) { vfloat16m1_t test_vfnmsub_vf_f16m1_tumu(vbool16_t mask, vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfnmsub_tumu(mask, vd, rs1, vs2, vl); return __riscv_vfnmsub_tumu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmsub_vv_f16m2_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmsub_vv_f16m2_tumu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmsub.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmsub.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
// //
vfloat16m2_t test_vfnmsub_vv_f16m2_tumu(vbool8_t mask, vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) { vfloat16m2_t test_vfnmsub_vv_f16m2_tumu(vbool8_t mask, vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfnmsub_tumu(mask, vd, vs1, vs2, vl); return __riscv_vfnmsub_tumu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmsub_vf_f16m2_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmsub_vf_f16m2_tumu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmsub.mask.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmsub.mask.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
// //
vfloat16m2_t test_vfnmsub_vf_f16m2_tumu(vbool8_t mask, vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) { vfloat16m2_t test_vfnmsub_vf_f16m2_tumu(vbool8_t mask, vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfnmsub_tumu(mask, vd, rs1, vs2, vl); return __riscv_vfnmsub_tumu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmsub_vv_f16m4_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmsub_vv_f16m4_tumu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmsub.mask.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmsub.mask.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
// //
vfloat16m4_t test_vfnmsub_vv_f16m4_tumu(vbool4_t mask, vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) { vfloat16m4_t test_vfnmsub_vv_f16m4_tumu(vbool4_t mask, vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfnmsub_tumu(mask, vd, vs1, vs2, vl); return __riscv_vfnmsub_tumu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmsub_vf_f16m4_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmsub_vf_f16m4_tumu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmsub.mask.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmsub.mask.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
// //
vfloat16m4_t test_vfnmsub_vf_f16m4_tumu(vbool4_t mask, vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) { vfloat16m4_t test_vfnmsub_vf_f16m4_tumu(vbool4_t mask, vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfnmsub_tumu(mask, vd, rs1, vs2, vl); return __riscv_vfnmsub_tumu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmsub_vv_f16m8_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmsub_vv_f16m8_tumu
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmsub.mask.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmsub.mask.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
// //
vfloat16m8_t test_vfnmsub_vv_f16m8_tumu(vbool2_t mask, vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) { vfloat16m8_t test_vfnmsub_vv_f16m8_tumu(vbool2_t mask, vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfnmsub_tumu(mask, vd, vs1, vs2, vl); return __riscv_vfnmsub_tumu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmsub_vf_f16m8_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmsub_vf_f16m8_tumu
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmsub.mask.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmsub.mask.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
// //
vfloat16m8_t test_vfnmsub_vf_f16m8_tumu(vbool2_t mask, vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) { vfloat16m8_t test_vfnmsub_vf_f16m8_tumu(vbool2_t mask, vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfnmsub_tumu(mask, vd, rs1, vs2, vl); return __riscv_vfnmsub_tumu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmsub_vv_f32mf2_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmsub_vv_f32mf2_tumu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmsub.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmsub.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfnmsub_vv_f32mf2_tumu(vbool64_t mask, vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) { vfloat32mf2_t test_vfnmsub_vv_f32mf2_tumu(vbool64_t mask, vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfnmsub_tumu(mask, vd, vs1, vs2, vl); return __riscv_vfnmsub_tumu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmsub_vf_f32mf2_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmsub_vf_f32mf2_tumu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmsub.mask.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmsub.mask.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfnmsub_vf_f32mf2_tumu(vbool64_t mask, vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) { vfloat32mf2_t test_vfnmsub_vf_f32mf2_tumu(vbool64_t mask, vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfnmsub_tumu(mask, vd, rs1, vs2, vl); return __riscv_vfnmsub_tumu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmsub_vv_f32m1_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmsub_vv_f32m1_tumu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmsub.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmsub.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfnmsub_vv_f32m1_tumu(vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) { vfloat32m1_t test_vfnmsub_vv_f32m1_tumu(vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfnmsub_tumu(mask, vd, vs1, vs2, vl); return __riscv_vfnmsub_tumu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmsub_vf_f32m1_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmsub_vf_f32m1_tumu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmsub.mask.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmsub.mask.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfnmsub_vf_f32m1_tumu(vbool32_t mask, vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) { vfloat32m1_t test_vfnmsub_vf_f32m1_tumu(vbool32_t mask, vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfnmsub_tumu(mask, vd, rs1, vs2, vl); return __riscv_vfnmsub_tumu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmsub_vv_f32m2_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmsub_vv_f32m2_tumu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmsub.mask.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmsub.mask.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfnmsub_vv_f32m2_tumu(vbool16_t mask, vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) { vfloat32m2_t test_vfnmsub_vv_f32m2_tumu(vbool16_t mask, vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfnmsub_tumu(mask, vd, vs1, vs2, vl); return __riscv_vfnmsub_tumu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmsub_vf_f32m2_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmsub_vf_f32m2_tumu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmsub.mask.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmsub.mask.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfnmsub_vf_f32m2_tumu(vbool16_t mask, vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) { vfloat32m2_t test_vfnmsub_vf_f32m2_tumu(vbool16_t mask, vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfnmsub_tumu(mask, vd, rs1, vs2, vl); return __riscv_vfnmsub_tumu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmsub_vv_f32m4_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmsub_vv_f32m4_tumu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmsub.mask.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmsub.mask.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfnmsub_vv_f32m4_tumu(vbool8_t mask, vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) { vfloat32m4_t test_vfnmsub_vv_f32m4_tumu(vbool8_t mask, vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfnmsub_tumu(mask, vd, vs1, vs2, vl); return __riscv_vfnmsub_tumu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmsub_vf_f32m4_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmsub_vf_f32m4_tumu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmsub.mask.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmsub.mask.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfnmsub_vf_f32m4_tumu(vbool8_t mask, vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) { vfloat32m4_t test_vfnmsub_vf_f32m4_tumu(vbool8_t mask, vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfnmsub_tumu(mask, vd, rs1, vs2, vl); return __riscv_vfnmsub_tumu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmsub_vv_f32m8_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmsub_vv_f32m8_tumu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmsub.mask.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmsub.mask.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfnmsub_vv_f32m8_tumu(vbool4_t mask, vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) { vfloat32m8_t test_vfnmsub_vv_f32m8_tumu(vbool4_t mask, vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfnmsub_tumu(mask, vd, vs1, vs2, vl); return __riscv_vfnmsub_tumu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmsub_vf_f32m8_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmsub_vf_f32m8_tumu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmsub.mask.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmsub.mask.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfnmsub_vf_f32m8_tumu(vbool4_t mask, vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) { vfloat32m8_t test_vfnmsub_vf_f32m8_tumu(vbool4_t mask, vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfnmsub_tumu(mask, vd, rs1, vs2, vl); return __riscv_vfnmsub_tumu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmsub_vv_f64m1_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmsub_vv_f64m1_tumu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmsub.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmsub.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfnmsub_vv_f64m1_tumu(vbool64_t mask, vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) { vfloat64m1_t test_vfnmsub_vv_f64m1_tumu(vbool64_t mask, vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfnmsub_tumu(mask, vd, vs1, vs2, vl); return __riscv_vfnmsub_tumu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmsub_vf_f64m1_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmsub_vf_f64m1_tumu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmsub.mask.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmsub.mask.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfnmsub_vf_f64m1_tumu(vbool64_t mask, vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) { vfloat64m1_t test_vfnmsub_vf_f64m1_tumu(vbool64_t mask, vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfnmsub_tumu(mask, vd, rs1, vs2, vl); return __riscv_vfnmsub_tumu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmsub_vv_f64m2_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmsub_vv_f64m2_tumu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmsub.mask.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmsub.mask.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfnmsub_vv_f64m2_tumu(vbool32_t mask, vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) { vfloat64m2_t test_vfnmsub_vv_f64m2_tumu(vbool32_t mask, vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfnmsub_tumu(mask, vd, vs1, vs2, vl); return __riscv_vfnmsub_tumu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmsub_vf_f64m2_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmsub_vf_f64m2_tumu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmsub.mask.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmsub.mask.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfnmsub_vf_f64m2_tumu(vbool32_t mask, vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) { vfloat64m2_t test_vfnmsub_vf_f64m2_tumu(vbool32_t mask, vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfnmsub_tumu(mask, vd, rs1, vs2, vl); return __riscv_vfnmsub_tumu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmsub_vv_f64m4_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmsub_vv_f64m4_tumu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmsub.mask.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmsub.mask.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfnmsub_vv_f64m4_tumu(vbool16_t mask, vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) { vfloat64m4_t test_vfnmsub_vv_f64m4_tumu(vbool16_t mask, vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfnmsub_tumu(mask, vd, vs1, vs2, vl); return __riscv_vfnmsub_tumu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmsub_vf_f64m4_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmsub_vf_f64m4_tumu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmsub.mask.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmsub.mask.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfnmsub_vf_f64m4_tumu(vbool16_t mask, vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) { vfloat64m4_t test_vfnmsub_vf_f64m4_tumu(vbool16_t mask, vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfnmsub_tumu(mask, vd, rs1, vs2, vl); return __riscv_vfnmsub_tumu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmsub_vv_f64m8_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmsub_vv_f64m8_tumu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmsub.mask.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmsub.mask.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfnmsub_vv_f64m8_tumu(vbool8_t mask, vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) { vfloat64m8_t test_vfnmsub_vv_f64m8_tumu(vbool8_t mask, vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfnmsub_tumu(mask, vd, vs1, vs2, vl); return __riscv_vfnmsub_tumu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmsub_vf_f64m8_tumu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmsub_vf_f64m8_tumu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmsub.mask.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 0) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmsub.mask.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfnmsub_vf_f64m8_tumu(vbool8_t mask, vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) { vfloat64m8_t test_vfnmsub_vf_f64m8_tumu(vbool8_t mask, vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfnmsub_tumu(mask, vd, rs1, vs2, vl); return __riscv_vfnmsub_tumu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmsub_vv_f16mf4_mu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmsub_vv_f16mf4_mu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmsub.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmsub.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
// //
vfloat16mf4_t test_vfnmsub_vv_f16mf4_mu(vbool64_t mask, vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) { vfloat16mf4_t test_vfnmsub_vv_f16mf4_mu(vbool64_t mask, vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfnmsub_mu(mask, vd, vs1, vs2, vl); return __riscv_vfnmsub_mu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmsub_vf_f16mf4_mu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmsub_vf_f16mf4_mu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmsub.mask.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmsub.mask.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
// //
vfloat16mf4_t test_vfnmsub_vf_f16mf4_mu(vbool64_t mask, vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) { vfloat16mf4_t test_vfnmsub_vf_f16mf4_mu(vbool64_t mask, vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfnmsub_mu(mask, vd, rs1, vs2, vl); return __riscv_vfnmsub_mu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmsub_vv_f16mf2_mu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmsub_vv_f16mf2_mu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmsub.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmsub.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
// //
vfloat16mf2_t test_vfnmsub_vv_f16mf2_mu(vbool32_t mask, vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) { vfloat16mf2_t test_vfnmsub_vv_f16mf2_mu(vbool32_t mask, vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfnmsub_mu(mask, vd, vs1, vs2, vl); return __riscv_vfnmsub_mu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmsub_vf_f16mf2_mu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmsub_vf_f16mf2_mu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmsub.mask.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmsub.mask.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
// //
vfloat16mf2_t test_vfnmsub_vf_f16mf2_mu(vbool32_t mask, vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) { vfloat16mf2_t test_vfnmsub_vf_f16mf2_mu(vbool32_t mask, vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfnmsub_mu(mask, vd, rs1, vs2, vl); return __riscv_vfnmsub_mu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmsub_vv_f16m1_mu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmsub_vv_f16m1_mu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmsub.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmsub.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
// //
vfloat16m1_t test_vfnmsub_vv_f16m1_mu(vbool16_t mask, vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) { vfloat16m1_t test_vfnmsub_vv_f16m1_mu(vbool16_t mask, vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfnmsub_mu(mask, vd, vs1, vs2, vl); return __riscv_vfnmsub_mu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmsub_vf_f16m1_mu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmsub_vf_f16m1_mu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmsub.mask.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmsub.mask.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
// //
vfloat16m1_t test_vfnmsub_vf_f16m1_mu(vbool16_t mask, vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) { vfloat16m1_t test_vfnmsub_vf_f16m1_mu(vbool16_t mask, vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfnmsub_mu(mask, vd, rs1, vs2, vl); return __riscv_vfnmsub_mu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmsub_vv_f16m2_mu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmsub_vv_f16m2_mu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmsub.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmsub.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
// //
vfloat16m2_t test_vfnmsub_vv_f16m2_mu(vbool8_t mask, vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) { vfloat16m2_t test_vfnmsub_vv_f16m2_mu(vbool8_t mask, vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfnmsub_mu(mask, vd, vs1, vs2, vl); return __riscv_vfnmsub_mu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmsub_vf_f16m2_mu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmsub_vf_f16m2_mu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmsub.mask.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmsub.mask.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
// //
vfloat16m2_t test_vfnmsub_vf_f16m2_mu(vbool8_t mask, vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) { vfloat16m2_t test_vfnmsub_vf_f16m2_mu(vbool8_t mask, vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfnmsub_mu(mask, vd, rs1, vs2, vl); return __riscv_vfnmsub_mu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmsub_vv_f16m4_mu // CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmsub_vv_f16m4_mu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmsub.mask.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmsub.mask.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
// //
vfloat16m4_t test_vfnmsub_vv_f16m4_mu(vbool4_t mask, vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) { vfloat16m4_t test_vfnmsub_vv_f16m4_mu(vbool4_t mask, vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfnmsub_mu(mask, vd, vs1, vs2, vl); return __riscv_vfnmsub_mu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmsub_vf_f16m4_mu // CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmsub_vf_f16m4_mu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmsub.mask.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmsub.mask.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
// //
vfloat16m4_t test_vfnmsub_vf_f16m4_mu(vbool4_t mask, vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) { vfloat16m4_t test_vfnmsub_vf_f16m4_mu(vbool4_t mask, vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfnmsub_mu(mask, vd, rs1, vs2, vl); return __riscv_vfnmsub_mu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmsub_vv_f16m8_mu // CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmsub_vv_f16m8_mu
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmsub.mask.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmsub.mask.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
// //
vfloat16m8_t test_vfnmsub_vv_f16m8_mu(vbool2_t mask, vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) { vfloat16m8_t test_vfnmsub_vv_f16m8_mu(vbool2_t mask, vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfnmsub_mu(mask, vd, vs1, vs2, vl); return __riscv_vfnmsub_mu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmsub_vf_f16m8_mu // CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmsub_vf_f16m8_mu
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmsub.mask.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmsub.mask.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
// //
vfloat16m8_t test_vfnmsub_vf_f16m8_mu(vbool2_t mask, vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) { vfloat16m8_t test_vfnmsub_vf_f16m8_mu(vbool2_t mask, vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfnmsub_mu(mask, vd, rs1, vs2, vl); return __riscv_vfnmsub_mu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmsub_vv_f32mf2_mu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmsub_vv_f32mf2_mu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmsub.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmsub.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfnmsub_vv_f32mf2_mu(vbool64_t mask, vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) { vfloat32mf2_t test_vfnmsub_vv_f32mf2_mu(vbool64_t mask, vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfnmsub_mu(mask, vd, vs1, vs2, vl); return __riscv_vfnmsub_mu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmsub_vf_f32mf2_mu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmsub_vf_f32mf2_mu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmsub.mask.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmsub.mask.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
// //
vfloat32mf2_t test_vfnmsub_vf_f32mf2_mu(vbool64_t mask, vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) { vfloat32mf2_t test_vfnmsub_vf_f32mf2_mu(vbool64_t mask, vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfnmsub_mu(mask, vd, rs1, vs2, vl); return __riscv_vfnmsub_mu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmsub_vv_f32m1_mu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmsub_vv_f32m1_mu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmsub.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmsub.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfnmsub_vv_f32m1_mu(vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) { vfloat32m1_t test_vfnmsub_vv_f32m1_mu(vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfnmsub_mu(mask, vd, vs1, vs2, vl); return __riscv_vfnmsub_mu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmsub_vf_f32m1_mu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmsub_vf_f32m1_mu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmsub.mask.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmsub.mask.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
// //
vfloat32m1_t test_vfnmsub_vf_f32m1_mu(vbool32_t mask, vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) { vfloat32m1_t test_vfnmsub_vf_f32m1_mu(vbool32_t mask, vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfnmsub_mu(mask, vd, rs1, vs2, vl); return __riscv_vfnmsub_mu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmsub_vv_f32m2_mu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmsub_vv_f32m2_mu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmsub.mask.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmsub.mask.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfnmsub_vv_f32m2_mu(vbool16_t mask, vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) { vfloat32m2_t test_vfnmsub_vv_f32m2_mu(vbool16_t mask, vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfnmsub_mu(mask, vd, vs1, vs2, vl); return __riscv_vfnmsub_mu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmsub_vf_f32m2_mu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmsub_vf_f32m2_mu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmsub.mask.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmsub.mask.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
// //
vfloat32m2_t test_vfnmsub_vf_f32m2_mu(vbool16_t mask, vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) { vfloat32m2_t test_vfnmsub_vf_f32m2_mu(vbool16_t mask, vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfnmsub_mu(mask, vd, rs1, vs2, vl); return __riscv_vfnmsub_mu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmsub_vv_f32m4_mu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmsub_vv_f32m4_mu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmsub.mask.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmsub.mask.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfnmsub_vv_f32m4_mu(vbool8_t mask, vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) { vfloat32m4_t test_vfnmsub_vv_f32m4_mu(vbool8_t mask, vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfnmsub_mu(mask, vd, vs1, vs2, vl); return __riscv_vfnmsub_mu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmsub_vf_f32m4_mu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmsub_vf_f32m4_mu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmsub.mask.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmsub.mask.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
// //
vfloat32m4_t test_vfnmsub_vf_f32m4_mu(vbool8_t mask, vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) { vfloat32m4_t test_vfnmsub_vf_f32m4_mu(vbool8_t mask, vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfnmsub_mu(mask, vd, rs1, vs2, vl); return __riscv_vfnmsub_mu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmsub_vv_f32m8_mu // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmsub_vv_f32m8_mu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmsub.mask.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmsub.mask.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfnmsub_vv_f32m8_mu(vbool4_t mask, vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) { vfloat32m8_t test_vfnmsub_vv_f32m8_mu(vbool4_t mask, vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfnmsub_mu(mask, vd, vs1, vs2, vl); return __riscv_vfnmsub_mu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmsub_vf_f32m8_mu // CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmsub_vf_f32m8_mu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmsub.mask.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmsub.mask.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
// //
vfloat32m8_t test_vfnmsub_vf_f32m8_mu(vbool4_t mask, vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) { vfloat32m8_t test_vfnmsub_vf_f32m8_mu(vbool4_t mask, vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfnmsub_mu(mask, vd, rs1, vs2, vl); return __riscv_vfnmsub_mu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmsub_vv_f64m1_mu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmsub_vv_f64m1_mu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmsub.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmsub.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfnmsub_vv_f64m1_mu(vbool64_t mask, vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) { vfloat64m1_t test_vfnmsub_vv_f64m1_mu(vbool64_t mask, vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfnmsub_mu(mask, vd, vs1, vs2, vl); return __riscv_vfnmsub_mu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmsub_vf_f64m1_mu // CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmsub_vf_f64m1_mu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmsub.mask.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmsub.mask.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
// //
vfloat64m1_t test_vfnmsub_vf_f64m1_mu(vbool64_t mask, vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) { vfloat64m1_t test_vfnmsub_vf_f64m1_mu(vbool64_t mask, vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfnmsub_mu(mask, vd, rs1, vs2, vl); return __riscv_vfnmsub_mu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmsub_vv_f64m2_mu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmsub_vv_f64m2_mu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmsub.mask.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmsub.mask.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfnmsub_vv_f64m2_mu(vbool32_t mask, vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) { vfloat64m2_t test_vfnmsub_vv_f64m2_mu(vbool32_t mask, vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfnmsub_mu(mask, vd, vs1, vs2, vl); return __riscv_vfnmsub_mu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmsub_vf_f64m2_mu // CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmsub_vf_f64m2_mu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmsub.mask.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmsub.mask.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
// //
vfloat64m2_t test_vfnmsub_vf_f64m2_mu(vbool32_t mask, vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) { vfloat64m2_t test_vfnmsub_vf_f64m2_mu(vbool32_t mask, vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfnmsub_mu(mask, vd, rs1, vs2, vl); return __riscv_vfnmsub_mu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmsub_vv_f64m4_mu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmsub_vv_f64m4_mu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmsub.mask.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmsub.mask.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfnmsub_vv_f64m4_mu(vbool16_t mask, vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) { vfloat64m4_t test_vfnmsub_vv_f64m4_mu(vbool16_t mask, vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfnmsub_mu(mask, vd, vs1, vs2, vl); return __riscv_vfnmsub_mu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmsub_vf_f64m4_mu // CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmsub_vf_f64m4_mu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmsub.mask.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmsub.mask.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
// //
vfloat64m4_t test_vfnmsub_vf_f64m4_mu(vbool16_t mask, vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) { vfloat64m4_t test_vfnmsub_vf_f64m4_mu(vbool16_t mask, vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfnmsub_mu(mask, vd, rs1, vs2, vl); return __riscv_vfnmsub_mu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmsub_vv_f64m8_mu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmsub_vv_f64m8_mu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmsub.mask.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmsub.mask.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfnmsub_vv_f64m8_mu(vbool8_t mask, vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) { vfloat64m8_t test_vfnmsub_vv_f64m8_mu(vbool8_t mask, vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfnmsub_mu(mask, vd, vs1, vs2, vl); return __riscv_vfnmsub_mu(mask, vd, vs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmsub_vf_f64m8_mu // CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmsub_vf_f64m8_mu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] { // CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry: // CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmsub.mask.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 [[VL]], i64 1) // CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmsub.mask.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 7, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]] // CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
// //
vfloat64m8_t test_vfnmsub_vf_f64m8_mu(vbool8_t mask, vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) { vfloat64m8_t test_vfnmsub_vf_f64m8_mu(vbool8_t mask, vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfnmsub_mu(mask, vd, rs1, vs2, vl); return __riscv_vfnmsub_mu(mask, vd, rs1, vs2, vl);
} }
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmsub_vv_f16mf4_rm_tu
// CHECK-RV64-SAME: (<vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmsub.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
//
vfloat16mf4_t test_vfnmsub_vv_f16mf4_rm_tu(vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfnmsub_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmsub_vf_f16mf4_rm_tu
// CHECK-RV64-SAME: (<vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmsub.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
//
vfloat16mf4_t test_vfnmsub_vf_f16mf4_rm_tu(vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfnmsub_tu(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmsub_vv_f16mf2_rm_tu
// CHECK-RV64-SAME: (<vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmsub.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
//
vfloat16mf2_t test_vfnmsub_vv_f16mf2_rm_tu(vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfnmsub_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmsub_vf_f16mf2_rm_tu
// CHECK-RV64-SAME: (<vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmsub.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
//
vfloat16mf2_t test_vfnmsub_vf_f16mf2_rm_tu(vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfnmsub_tu(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmsub_vv_f16m1_rm_tu
// CHECK-RV64-SAME: (<vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmsub.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfnmsub_vv_f16m1_rm_tu(vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfnmsub_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmsub_vf_f16m1_rm_tu
// CHECK-RV64-SAME: (<vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmsub.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfnmsub_vf_f16m1_rm_tu(vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfnmsub_tu(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmsub_vv_f16m2_rm_tu
// CHECK-RV64-SAME: (<vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmsub.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
//
vfloat16m2_t test_vfnmsub_vv_f16m2_rm_tu(vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfnmsub_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmsub_vf_f16m2_rm_tu
// CHECK-RV64-SAME: (<vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmsub.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
//
vfloat16m2_t test_vfnmsub_vf_f16m2_rm_tu(vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfnmsub_tu(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmsub_vv_f16m4_rm_tu
// CHECK-RV64-SAME: (<vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmsub.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
//
vfloat16m4_t test_vfnmsub_vv_f16m4_rm_tu(vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfnmsub_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmsub_vf_f16m4_rm_tu
// CHECK-RV64-SAME: (<vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmsub.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
//
vfloat16m4_t test_vfnmsub_vf_f16m4_rm_tu(vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfnmsub_tu(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmsub_vv_f16m8_rm_tu
// CHECK-RV64-SAME: (<vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmsub.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
//
vfloat16m8_t test_vfnmsub_vv_f16m8_rm_tu(vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfnmsub_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmsub_vf_f16m8_rm_tu
// CHECK-RV64-SAME: (<vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmsub.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
//
vfloat16m8_t test_vfnmsub_vf_f16m8_rm_tu(vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfnmsub_tu(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmsub_vv_f32mf2_rm_tu
// CHECK-RV64-SAME: (<vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmsub.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
//
vfloat32mf2_t test_vfnmsub_vv_f32mf2_rm_tu(vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfnmsub_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmsub_vf_f32mf2_rm_tu
// CHECK-RV64-SAME: (<vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmsub.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
//
vfloat32mf2_t test_vfnmsub_vf_f32mf2_rm_tu(vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfnmsub_tu(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmsub_vv_f32m1_rm_tu
// CHECK-RV64-SAME: (<vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmsub.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfnmsub_vv_f32m1_rm_tu(vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfnmsub_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmsub_vf_f32m1_rm_tu
// CHECK-RV64-SAME: (<vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmsub.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfnmsub_vf_f32m1_rm_tu(vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfnmsub_tu(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmsub_vv_f32m2_rm_tu
// CHECK-RV64-SAME: (<vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmsub.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
//
vfloat32m2_t test_vfnmsub_vv_f32m2_rm_tu(vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfnmsub_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmsub_vf_f32m2_rm_tu
// CHECK-RV64-SAME: (<vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmsub.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
//
vfloat32m2_t test_vfnmsub_vf_f32m2_rm_tu(vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfnmsub_tu(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmsub_vv_f32m4_rm_tu
// CHECK-RV64-SAME: (<vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmsub.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
//
vfloat32m4_t test_vfnmsub_vv_f32m4_rm_tu(vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfnmsub_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmsub_vf_f32m4_rm_tu
// CHECK-RV64-SAME: (<vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmsub.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
//
vfloat32m4_t test_vfnmsub_vf_f32m4_rm_tu(vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfnmsub_tu(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmsub_vv_f32m8_rm_tu
// CHECK-RV64-SAME: (<vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmsub.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
//
vfloat32m8_t test_vfnmsub_vv_f32m8_rm_tu(vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfnmsub_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmsub_vf_f32m8_rm_tu
// CHECK-RV64-SAME: (<vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmsub.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
//
vfloat32m8_t test_vfnmsub_vf_f32m8_rm_tu(vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfnmsub_tu(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmsub_vv_f64m1_rm_tu
// CHECK-RV64-SAME: (<vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmsub.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfnmsub_vv_f64m1_rm_tu(vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfnmsub_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmsub_vf_f64m1_rm_tu
// CHECK-RV64-SAME: (<vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmsub.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfnmsub_vf_f64m1_rm_tu(vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfnmsub_tu(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmsub_vv_f64m2_rm_tu
// CHECK-RV64-SAME: (<vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmsub.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
//
vfloat64m2_t test_vfnmsub_vv_f64m2_rm_tu(vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfnmsub_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmsub_vf_f64m2_rm_tu
// CHECK-RV64-SAME: (<vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmsub.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
//
vfloat64m2_t test_vfnmsub_vf_f64m2_rm_tu(vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfnmsub_tu(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmsub_vv_f64m4_rm_tu
// CHECK-RV64-SAME: (<vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmsub.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
//
vfloat64m4_t test_vfnmsub_vv_f64m4_rm_tu(vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfnmsub_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmsub_vf_f64m4_rm_tu
// CHECK-RV64-SAME: (<vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmsub.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
//
vfloat64m4_t test_vfnmsub_vf_f64m4_rm_tu(vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfnmsub_tu(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmsub_vv_f64m8_rm_tu
// CHECK-RV64-SAME: (<vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmsub.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
//
vfloat64m8_t test_vfnmsub_vv_f64m8_rm_tu(vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfnmsub_tu(vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmsub_vf_f64m8_rm_tu
// CHECK-RV64-SAME: (<vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmsub.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
//
vfloat64m8_t test_vfnmsub_vf_f64m8_rm_tu(vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfnmsub_tu(vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmsub_vv_f16mf4_rm_tum
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmsub.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
//
vfloat16mf4_t test_vfnmsub_vv_f16mf4_rm_tum(vbool64_t mask, vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfnmsub_tum(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmsub_vf_f16mf4_rm_tum
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmsub.mask.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
//
vfloat16mf4_t test_vfnmsub_vf_f16mf4_rm_tum(vbool64_t mask, vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfnmsub_tum(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmsub_vv_f16mf2_rm_tum
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmsub.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
//
vfloat16mf2_t test_vfnmsub_vv_f16mf2_rm_tum(vbool32_t mask, vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfnmsub_tum(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmsub_vf_f16mf2_rm_tum
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmsub.mask.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
//
vfloat16mf2_t test_vfnmsub_vf_f16mf2_rm_tum(vbool32_t mask, vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfnmsub_tum(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmsub_vv_f16m1_rm_tum
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmsub.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfnmsub_vv_f16m1_rm_tum(vbool16_t mask, vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfnmsub_tum(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmsub_vf_f16m1_rm_tum
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmsub.mask.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfnmsub_vf_f16m1_rm_tum(vbool16_t mask, vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfnmsub_tum(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmsub_vv_f16m2_rm_tum
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmsub.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
//
vfloat16m2_t test_vfnmsub_vv_f16m2_rm_tum(vbool8_t mask, vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfnmsub_tum(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmsub_vf_f16m2_rm_tum
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmsub.mask.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
//
vfloat16m2_t test_vfnmsub_vf_f16m2_rm_tum(vbool8_t mask, vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfnmsub_tum(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmsub_vv_f16m4_rm_tum
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmsub.mask.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
//
vfloat16m4_t test_vfnmsub_vv_f16m4_rm_tum(vbool4_t mask, vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfnmsub_tum(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmsub_vf_f16m4_rm_tum
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmsub.mask.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
//
vfloat16m4_t test_vfnmsub_vf_f16m4_rm_tum(vbool4_t mask, vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfnmsub_tum(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmsub_vv_f16m8_rm_tum
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmsub.mask.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
//
vfloat16m8_t test_vfnmsub_vv_f16m8_rm_tum(vbool2_t mask, vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfnmsub_tum(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmsub_vf_f16m8_rm_tum
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmsub.mask.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
//
vfloat16m8_t test_vfnmsub_vf_f16m8_rm_tum(vbool2_t mask, vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfnmsub_tum(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmsub_vv_f32mf2_rm_tum
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmsub.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
//
vfloat32mf2_t test_vfnmsub_vv_f32mf2_rm_tum(vbool64_t mask, vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfnmsub_tum(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmsub_vf_f32mf2_rm_tum
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmsub.mask.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
//
vfloat32mf2_t test_vfnmsub_vf_f32mf2_rm_tum(vbool64_t mask, vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfnmsub_tum(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmsub_vv_f32m1_rm_tum
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmsub.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfnmsub_vv_f32m1_rm_tum(vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfnmsub_tum(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmsub_vf_f32m1_rm_tum
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmsub.mask.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfnmsub_vf_f32m1_rm_tum(vbool32_t mask, vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfnmsub_tum(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmsub_vv_f32m2_rm_tum
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmsub.mask.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
//
vfloat32m2_t test_vfnmsub_vv_f32m2_rm_tum(vbool16_t mask, vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfnmsub_tum(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmsub_vf_f32m2_rm_tum
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmsub.mask.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
//
vfloat32m2_t test_vfnmsub_vf_f32m2_rm_tum(vbool16_t mask, vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfnmsub_tum(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmsub_vv_f32m4_rm_tum
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmsub.mask.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
//
vfloat32m4_t test_vfnmsub_vv_f32m4_rm_tum(vbool8_t mask, vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfnmsub_tum(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmsub_vf_f32m4_rm_tum
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmsub.mask.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
//
vfloat32m4_t test_vfnmsub_vf_f32m4_rm_tum(vbool8_t mask, vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfnmsub_tum(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmsub_vv_f32m8_rm_tum
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmsub.mask.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
//
vfloat32m8_t test_vfnmsub_vv_f32m8_rm_tum(vbool4_t mask, vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfnmsub_tum(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmsub_vf_f32m8_rm_tum
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmsub.mask.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
//
vfloat32m8_t test_vfnmsub_vf_f32m8_rm_tum(vbool4_t mask, vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfnmsub_tum(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmsub_vv_f64m1_rm_tum
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmsub.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfnmsub_vv_f64m1_rm_tum(vbool64_t mask, vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfnmsub_tum(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmsub_vf_f64m1_rm_tum
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmsub.mask.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfnmsub_vf_f64m1_rm_tum(vbool64_t mask, vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfnmsub_tum(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmsub_vv_f64m2_rm_tum
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmsub.mask.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
//
vfloat64m2_t test_vfnmsub_vv_f64m2_rm_tum(vbool32_t mask, vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfnmsub_tum(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmsub_vf_f64m2_rm_tum
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmsub.mask.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
//
vfloat64m2_t test_vfnmsub_vf_f64m2_rm_tum(vbool32_t mask, vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfnmsub_tum(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmsub_vv_f64m4_rm_tum
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmsub.mask.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
//
vfloat64m4_t test_vfnmsub_vv_f64m4_rm_tum(vbool16_t mask, vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfnmsub_tum(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmsub_vf_f64m4_rm_tum
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmsub.mask.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
//
vfloat64m4_t test_vfnmsub_vf_f64m4_rm_tum(vbool16_t mask, vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfnmsub_tum(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmsub_vv_f64m8_rm_tum
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmsub.mask.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
//
vfloat64m8_t test_vfnmsub_vv_f64m8_rm_tum(vbool8_t mask, vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfnmsub_tum(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmsub_vf_f64m8_rm_tum
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmsub.mask.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 2)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
//
vfloat64m8_t test_vfnmsub_vf_f64m8_rm_tum(vbool8_t mask, vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfnmsub_tum(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmsub_vv_f16mf4_rm_tumu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmsub.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
//
vfloat16mf4_t test_vfnmsub_vv_f16mf4_rm_tumu(vbool64_t mask, vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfnmsub_tumu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmsub_vf_f16mf4_rm_tumu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmsub.mask.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
//
vfloat16mf4_t test_vfnmsub_vf_f16mf4_rm_tumu(vbool64_t mask, vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfnmsub_tumu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmsub_vv_f16mf2_rm_tumu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmsub.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
//
vfloat16mf2_t test_vfnmsub_vv_f16mf2_rm_tumu(vbool32_t mask, vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfnmsub_tumu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmsub_vf_f16mf2_rm_tumu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmsub.mask.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
//
vfloat16mf2_t test_vfnmsub_vf_f16mf2_rm_tumu(vbool32_t mask, vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfnmsub_tumu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmsub_vv_f16m1_rm_tumu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmsub.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfnmsub_vv_f16m1_rm_tumu(vbool16_t mask, vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfnmsub_tumu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmsub_vf_f16m1_rm_tumu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmsub.mask.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfnmsub_vf_f16m1_rm_tumu(vbool16_t mask, vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfnmsub_tumu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmsub_vv_f16m2_rm_tumu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmsub.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
//
vfloat16m2_t test_vfnmsub_vv_f16m2_rm_tumu(vbool8_t mask, vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfnmsub_tumu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmsub_vf_f16m2_rm_tumu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmsub.mask.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
//
vfloat16m2_t test_vfnmsub_vf_f16m2_rm_tumu(vbool8_t mask, vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfnmsub_tumu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmsub_vv_f16m4_rm_tumu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmsub.mask.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
//
vfloat16m4_t test_vfnmsub_vv_f16m4_rm_tumu(vbool4_t mask, vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfnmsub_tumu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmsub_vf_f16m4_rm_tumu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmsub.mask.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
//
vfloat16m4_t test_vfnmsub_vf_f16m4_rm_tumu(vbool4_t mask, vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfnmsub_tumu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmsub_vv_f16m8_rm_tumu
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmsub.mask.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
//
vfloat16m8_t test_vfnmsub_vv_f16m8_rm_tumu(vbool2_t mask, vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfnmsub_tumu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmsub_vf_f16m8_rm_tumu
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmsub.mask.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
//
vfloat16m8_t test_vfnmsub_vf_f16m8_rm_tumu(vbool2_t mask, vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfnmsub_tumu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmsub_vv_f32mf2_rm_tumu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmsub.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
//
vfloat32mf2_t test_vfnmsub_vv_f32mf2_rm_tumu(vbool64_t mask, vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfnmsub_tumu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmsub_vf_f32mf2_rm_tumu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmsub.mask.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
//
vfloat32mf2_t test_vfnmsub_vf_f32mf2_rm_tumu(vbool64_t mask, vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfnmsub_tumu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmsub_vv_f32m1_rm_tumu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmsub.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfnmsub_vv_f32m1_rm_tumu(vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfnmsub_tumu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmsub_vf_f32m1_rm_tumu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmsub.mask.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfnmsub_vf_f32m1_rm_tumu(vbool32_t mask, vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfnmsub_tumu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmsub_vv_f32m2_rm_tumu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmsub.mask.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
//
vfloat32m2_t test_vfnmsub_vv_f32m2_rm_tumu(vbool16_t mask, vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfnmsub_tumu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmsub_vf_f32m2_rm_tumu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmsub.mask.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
//
vfloat32m2_t test_vfnmsub_vf_f32m2_rm_tumu(vbool16_t mask, vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfnmsub_tumu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmsub_vv_f32m4_rm_tumu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmsub.mask.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
//
vfloat32m4_t test_vfnmsub_vv_f32m4_rm_tumu(vbool8_t mask, vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfnmsub_tumu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmsub_vf_f32m4_rm_tumu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmsub.mask.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
//
vfloat32m4_t test_vfnmsub_vf_f32m4_rm_tumu(vbool8_t mask, vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfnmsub_tumu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmsub_vv_f32m8_rm_tumu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmsub.mask.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
//
vfloat32m8_t test_vfnmsub_vv_f32m8_rm_tumu(vbool4_t mask, vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfnmsub_tumu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmsub_vf_f32m8_rm_tumu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmsub.mask.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
//
vfloat32m8_t test_vfnmsub_vf_f32m8_rm_tumu(vbool4_t mask, vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfnmsub_tumu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmsub_vv_f64m1_rm_tumu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmsub.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfnmsub_vv_f64m1_rm_tumu(vbool64_t mask, vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfnmsub_tumu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmsub_vf_f64m1_rm_tumu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmsub.mask.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfnmsub_vf_f64m1_rm_tumu(vbool64_t mask, vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfnmsub_tumu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmsub_vv_f64m2_rm_tumu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmsub.mask.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
//
vfloat64m2_t test_vfnmsub_vv_f64m2_rm_tumu(vbool32_t mask, vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfnmsub_tumu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmsub_vf_f64m2_rm_tumu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmsub.mask.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
//
vfloat64m2_t test_vfnmsub_vf_f64m2_rm_tumu(vbool32_t mask, vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfnmsub_tumu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmsub_vv_f64m4_rm_tumu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmsub.mask.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
//
vfloat64m4_t test_vfnmsub_vv_f64m4_rm_tumu(vbool16_t mask, vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfnmsub_tumu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmsub_vf_f64m4_rm_tumu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmsub.mask.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
//
vfloat64m4_t test_vfnmsub_vf_f64m4_rm_tumu(vbool16_t mask, vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfnmsub_tumu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmsub_vv_f64m8_rm_tumu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmsub.mask.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
//
vfloat64m8_t test_vfnmsub_vv_f64m8_rm_tumu(vbool8_t mask, vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfnmsub_tumu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmsub_vf_f64m8_rm_tumu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmsub.mask.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 0)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
//
vfloat64m8_t test_vfnmsub_vf_f64m8_rm_tumu(vbool8_t mask, vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfnmsub_tumu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmsub_vv_f16mf4_rm_mu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], <vscale x 1 x half> [[VS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmsub.mask.nxv1f16.nxv1f16.i64(<vscale x 1 x half> [[VD]], <vscale x 1 x half> [[VS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
//
vfloat16mf4_t test_vfnmsub_vv_f16mf4_rm_mu(vbool64_t mask, vfloat16mf4_t vd, vfloat16mf4_t vs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfnmsub_mu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x half> @test_vfnmsub_vf_f16mf4_rm_mu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 1 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x half> @llvm.riscv.vfnmsub.mask.nxv1f16.f16.i64(<vscale x 1 x half> [[VD]], half [[RS1]], <vscale x 1 x half> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x half> [[TMP0]]
//
vfloat16mf4_t test_vfnmsub_vf_f16mf4_rm_mu(vbool64_t mask, vfloat16mf4_t vd, _Float16 rs1, vfloat16mf4_t vs2, size_t vl) {
return __riscv_vfnmsub_mu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmsub_vv_f16mf2_rm_mu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], <vscale x 2 x half> [[VS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmsub.mask.nxv2f16.nxv2f16.i64(<vscale x 2 x half> [[VD]], <vscale x 2 x half> [[VS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
//
vfloat16mf2_t test_vfnmsub_vv_f16mf2_rm_mu(vbool32_t mask, vfloat16mf2_t vd, vfloat16mf2_t vs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfnmsub_mu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x half> @test_vfnmsub_vf_f16mf2_rm_mu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 2 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x half> @llvm.riscv.vfnmsub.mask.nxv2f16.f16.i64(<vscale x 2 x half> [[VD]], half [[RS1]], <vscale x 2 x half> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x half> [[TMP0]]
//
vfloat16mf2_t test_vfnmsub_vf_f16mf2_rm_mu(vbool32_t mask, vfloat16mf2_t vd, _Float16 rs1, vfloat16mf2_t vs2, size_t vl) {
return __riscv_vfnmsub_mu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmsub_vv_f16m1_rm_mu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], <vscale x 4 x half> [[VS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmsub.mask.nxv4f16.nxv4f16.i64(<vscale x 4 x half> [[VD]], <vscale x 4 x half> [[VS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfnmsub_vv_f16m1_rm_mu(vbool16_t mask, vfloat16m1_t vd, vfloat16m1_t vs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfnmsub_mu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x half> @test_vfnmsub_vf_f16m1_rm_mu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 4 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.riscv.vfnmsub.mask.nxv4f16.f16.i64(<vscale x 4 x half> [[VD]], half [[RS1]], <vscale x 4 x half> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]]
//
vfloat16m1_t test_vfnmsub_vf_f16m1_rm_mu(vbool16_t mask, vfloat16m1_t vd, _Float16 rs1, vfloat16m1_t vs2, size_t vl) {
return __riscv_vfnmsub_mu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmsub_vv_f16m2_rm_mu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], <vscale x 8 x half> [[VS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmsub.mask.nxv8f16.nxv8f16.i64(<vscale x 8 x half> [[VD]], <vscale x 8 x half> [[VS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
//
vfloat16m2_t test_vfnmsub_vv_f16m2_rm_mu(vbool8_t mask, vfloat16m2_t vd, vfloat16m2_t vs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfnmsub_mu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x half> @test_vfnmsub_vf_f16m2_rm_mu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 8 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.riscv.vfnmsub.mask.nxv8f16.f16.i64(<vscale x 8 x half> [[VD]], half [[RS1]], <vscale x 8 x half> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]]
//
vfloat16m2_t test_vfnmsub_vf_f16m2_rm_mu(vbool8_t mask, vfloat16m2_t vd, _Float16 rs1, vfloat16m2_t vs2, size_t vl) {
return __riscv_vfnmsub_mu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmsub_vv_f16m4_rm_mu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], <vscale x 16 x half> [[VS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmsub.mask.nxv16f16.nxv16f16.i64(<vscale x 16 x half> [[VD]], <vscale x 16 x half> [[VS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
//
vfloat16m4_t test_vfnmsub_vv_f16m4_rm_mu(vbool4_t mask, vfloat16m4_t vd, vfloat16m4_t vs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfnmsub_mu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x half> @test_vfnmsub_vf_f16m4_rm_mu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 16 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.riscv.vfnmsub.mask.nxv16f16.f16.i64(<vscale x 16 x half> [[VD]], half [[RS1]], <vscale x 16 x half> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]]
//
vfloat16m4_t test_vfnmsub_vf_f16m4_rm_mu(vbool4_t mask, vfloat16m4_t vd, _Float16 rs1, vfloat16m4_t vs2, size_t vl) {
return __riscv_vfnmsub_mu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmsub_vv_f16m8_rm_mu
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], <vscale x 32 x half> [[VS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmsub.mask.nxv32f16.nxv32f16.i64(<vscale x 32 x half> [[VD]], <vscale x 32 x half> [[VS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
//
vfloat16m8_t test_vfnmsub_vv_f16m8_rm_mu(vbool2_t mask, vfloat16m8_t vd, vfloat16m8_t vs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfnmsub_mu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 32 x half> @test_vfnmsub_vf_f16m8_rm_mu
// CHECK-RV64-SAME: (<vscale x 32 x i1> [[MASK:%.*]], <vscale x 32 x half> [[VD:%.*]], half noundef [[RS1:%.*]], <vscale x 32 x half> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.riscv.vfnmsub.mask.nxv32f16.f16.i64(<vscale x 32 x half> [[VD]], half [[RS1]], <vscale x 32 x half> [[VS2]], <vscale x 32 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]]
//
vfloat16m8_t test_vfnmsub_vf_f16m8_rm_mu(vbool2_t mask, vfloat16m8_t vd, _Float16 rs1, vfloat16m8_t vs2, size_t vl) {
return __riscv_vfnmsub_mu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmsub_vv_f32mf2_rm_mu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], <vscale x 1 x float> [[VS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmsub.mask.nxv1f32.nxv1f32.i64(<vscale x 1 x float> [[VD]], <vscale x 1 x float> [[VS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
//
vfloat32mf2_t test_vfnmsub_vv_f32mf2_rm_mu(vbool64_t mask, vfloat32mf2_t vd, vfloat32mf2_t vs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfnmsub_mu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x float> @test_vfnmsub_vf_f32mf2_rm_mu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 1 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x float> @llvm.riscv.vfnmsub.mask.nxv1f32.f32.i64(<vscale x 1 x float> [[VD]], float [[RS1]], <vscale x 1 x float> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x float> [[TMP0]]
//
vfloat32mf2_t test_vfnmsub_vf_f32mf2_rm_mu(vbool64_t mask, vfloat32mf2_t vd, float rs1, vfloat32mf2_t vs2, size_t vl) {
return __riscv_vfnmsub_mu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmsub_vv_f32m1_rm_mu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], <vscale x 2 x float> [[VS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmsub.mask.nxv2f32.nxv2f32.i64(<vscale x 2 x float> [[VD]], <vscale x 2 x float> [[VS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfnmsub_vv_f32m1_rm_mu(vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfnmsub_mu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x float> @test_vfnmsub_vf_f32m1_rm_mu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 2 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfnmsub.mask.nxv2f32.f32.i64(<vscale x 2 x float> [[VD]], float [[RS1]], <vscale x 2 x float> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]]
//
vfloat32m1_t test_vfnmsub_vf_f32m1_rm_mu(vbool32_t mask, vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
return __riscv_vfnmsub_mu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmsub_vv_f32m2_rm_mu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], <vscale x 4 x float> [[VS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmsub.mask.nxv4f32.nxv4f32.i64(<vscale x 4 x float> [[VD]], <vscale x 4 x float> [[VS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
//
vfloat32m2_t test_vfnmsub_vv_f32m2_rm_mu(vbool16_t mask, vfloat32m2_t vd, vfloat32m2_t vs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfnmsub_mu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x float> @test_vfnmsub_vf_f32m2_rm_mu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 4 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x float> @llvm.riscv.vfnmsub.mask.nxv4f32.f32.i64(<vscale x 4 x float> [[VD]], float [[RS1]], <vscale x 4 x float> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x float> [[TMP0]]
//
vfloat32m2_t test_vfnmsub_vf_f32m2_rm_mu(vbool16_t mask, vfloat32m2_t vd, float rs1, vfloat32m2_t vs2, size_t vl) {
return __riscv_vfnmsub_mu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmsub_vv_f32m4_rm_mu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], <vscale x 8 x float> [[VS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmsub.mask.nxv8f32.nxv8f32.i64(<vscale x 8 x float> [[VD]], <vscale x 8 x float> [[VS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
//
vfloat32m4_t test_vfnmsub_vv_f32m4_rm_mu(vbool8_t mask, vfloat32m4_t vd, vfloat32m4_t vs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfnmsub_mu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x float> @test_vfnmsub_vf_f32m4_rm_mu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 8 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x float> @llvm.riscv.vfnmsub.mask.nxv8f32.f32.i64(<vscale x 8 x float> [[VD]], float [[RS1]], <vscale x 8 x float> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x float> [[TMP0]]
//
vfloat32m4_t test_vfnmsub_vf_f32m4_rm_mu(vbool8_t mask, vfloat32m4_t vd, float rs1, vfloat32m4_t vs2, size_t vl) {
return __riscv_vfnmsub_mu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmsub_vv_f32m8_rm_mu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], <vscale x 16 x float> [[VS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmsub.mask.nxv16f32.nxv16f32.i64(<vscale x 16 x float> [[VD]], <vscale x 16 x float> [[VS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
//
vfloat32m8_t test_vfnmsub_vv_f32m8_rm_mu(vbool4_t mask, vfloat32m8_t vd, vfloat32m8_t vs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfnmsub_mu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 16 x float> @test_vfnmsub_vf_f32m8_rm_mu
// CHECK-RV64-SAME: (<vscale x 16 x i1> [[MASK:%.*]], <vscale x 16 x float> [[VD:%.*]], float noundef [[RS1:%.*]], <vscale x 16 x float> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x float> @llvm.riscv.vfnmsub.mask.nxv16f32.f32.i64(<vscale x 16 x float> [[VD]], float [[RS1]], <vscale x 16 x float> [[VS2]], <vscale x 16 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 16 x float> [[TMP0]]
//
vfloat32m8_t test_vfnmsub_vf_f32m8_rm_mu(vbool4_t mask, vfloat32m8_t vd, float rs1, vfloat32m8_t vs2, size_t vl) {
return __riscv_vfnmsub_mu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmsub_vv_f64m1_rm_mu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], <vscale x 1 x double> [[VS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmsub.mask.nxv1f64.nxv1f64.i64(<vscale x 1 x double> [[VD]], <vscale x 1 x double> [[VS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfnmsub_vv_f64m1_rm_mu(vbool64_t mask, vfloat64m1_t vd, vfloat64m1_t vs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfnmsub_mu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 1 x double> @test_vfnmsub_vf_f64m1_rm_mu
// CHECK-RV64-SAME: (<vscale x 1 x i1> [[MASK:%.*]], <vscale x 1 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 1 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfnmsub.mask.nxv1f64.f64.i64(<vscale x 1 x double> [[VD]], double [[RS1]], <vscale x 1 x double> [[VS2]], <vscale x 1 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]]
//
vfloat64m1_t test_vfnmsub_vf_f64m1_rm_mu(vbool64_t mask, vfloat64m1_t vd, double rs1, vfloat64m1_t vs2, size_t vl) {
return __riscv_vfnmsub_mu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmsub_vv_f64m2_rm_mu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], <vscale x 2 x double> [[VS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmsub.mask.nxv2f64.nxv2f64.i64(<vscale x 2 x double> [[VD]], <vscale x 2 x double> [[VS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
//
vfloat64m2_t test_vfnmsub_vv_f64m2_rm_mu(vbool32_t mask, vfloat64m2_t vd, vfloat64m2_t vs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfnmsub_mu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 2 x double> @test_vfnmsub_vf_f64m2_rm_mu
// CHECK-RV64-SAME: (<vscale x 2 x i1> [[MASK:%.*]], <vscale x 2 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 2 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x double> @llvm.riscv.vfnmsub.mask.nxv2f64.f64.i64(<vscale x 2 x double> [[VD]], double [[RS1]], <vscale x 2 x double> [[VS2]], <vscale x 2 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 2 x double> [[TMP0]]
//
vfloat64m2_t test_vfnmsub_vf_f64m2_rm_mu(vbool32_t mask, vfloat64m2_t vd, double rs1, vfloat64m2_t vs2, size_t vl) {
return __riscv_vfnmsub_mu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmsub_vv_f64m4_rm_mu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], <vscale x 4 x double> [[VS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmsub.mask.nxv4f64.nxv4f64.i64(<vscale x 4 x double> [[VD]], <vscale x 4 x double> [[VS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
//
vfloat64m4_t test_vfnmsub_vv_f64m4_rm_mu(vbool16_t mask, vfloat64m4_t vd, vfloat64m4_t vs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfnmsub_mu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 4 x double> @test_vfnmsub_vf_f64m4_rm_mu
// CHECK-RV64-SAME: (<vscale x 4 x i1> [[MASK:%.*]], <vscale x 4 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 4 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x double> @llvm.riscv.vfnmsub.mask.nxv4f64.f64.i64(<vscale x 4 x double> [[VD]], double [[RS1]], <vscale x 4 x double> [[VS2]], <vscale x 4 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 4 x double> [[TMP0]]
//
vfloat64m4_t test_vfnmsub_vf_f64m4_rm_mu(vbool16_t mask, vfloat64m4_t vd, double rs1, vfloat64m4_t vs2, size_t vl) {
return __riscv_vfnmsub_mu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmsub_vv_f64m8_rm_mu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], <vscale x 8 x double> [[VS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmsub.mask.nxv8f64.nxv8f64.i64(<vscale x 8 x double> [[VD]], <vscale x 8 x double> [[VS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
//
vfloat64m8_t test_vfnmsub_vv_f64m8_rm_mu(vbool8_t mask, vfloat64m8_t vd, vfloat64m8_t vs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfnmsub_mu(mask, vd, vs1, vs2, __RISCV_FRM_RNE, vl);
}
// CHECK-RV64-LABEL: define dso_local <vscale x 8 x double> @test_vfnmsub_vf_f64m8_rm_mu
// CHECK-RV64-SAME: (<vscale x 8 x i1> [[MASK:%.*]], <vscale x 8 x double> [[VD:%.*]], double noundef [[RS1:%.*]], <vscale x 8 x double> [[VS2:%.*]], i64 noundef [[VL:%.*]]) #[[ATTR0]] {
// CHECK-RV64-NEXT: entry:
// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x double> @llvm.riscv.vfnmsub.mask.nxv8f64.f64.i64(<vscale x 8 x double> [[VD]], double [[RS1]], <vscale x 8 x double> [[VS2]], <vscale x 8 x i1> [[MASK]], i64 0, i64 [[VL]], i64 1)
// CHECK-RV64-NEXT: ret <vscale x 8 x double> [[TMP0]]
//
vfloat64m8_t test_vfnmsub_vf_f64m8_rm_mu(vbool8_t mask, vfloat64m8_t vd, double rs1, vfloat64m8_t vs2, size_t vl) {
return __riscv_vfnmsub_mu(mask, vd, rs1, vs2, __RISCV_FRM_RNE, vl);
}

clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vfmacc-out-of-range.c

  • This file was added.
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \
// RUN: -target-feature +v -target-feature +zfh -target-feature +experimental-zvfh \
// RUN: -fsyntax-only -verify %s
#include <riscv_vector.h>
vfloat32m1_t test_vfmacc_vv_f32m1_rm(vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
// expected-error@+1 {{argument value 5 is outside the valid range [0, 4]}}
return __riscv_vfmacc_vv_f32m1_rm(vd, vs1, vs2, 5, vl);
}
vfloat32m1_t test_vfmacc_vf_f32m1_rm(vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
// expected-error@+1 {{argument value 5 is outside the valid range [0, 4]}}
return __riscv_vfmacc_vf_f32m1_rm(vd, rs1, vs2, 5, vl);
}
vfloat32m1_t test_vfmacc_vv_f32m1_rm_m(vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
// expected-error@+1 {{argument value 5 is outside the valid range [0, 4]}}
return __riscv_vfmacc_vv_f32m1_rm_m(mask, vd, vs1, vs2, 5, vl);
}
vfloat32m1_t test_vfmacc_vf_f32m1_rm_m(vbool32_t mask, vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
// expected-error@+1 {{argument value 5 is outside the valid range [0, 4]}}
return __riscv_vfmacc_vf_f32m1_rm_m(mask, vd, rs1, vs2, 5, vl);
}
vfloat32m1_t test_vfmacc_vv_f32m1_rm_tu(vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
// expected-error@+1 {{argument value 5 is outside the valid range [0, 4]}}
return __riscv_vfmacc_vv_f32m1_rm_tu(vd, vs1, vs2, 5, vl);
}
vfloat32m1_t test_vfmacc_vf_f32m1_rm_tu(vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
// expected-error@+1 {{argument value 5 is outside the valid range [0, 4]}}
return __riscv_vfmacc_vf_f32m1_rm_tu(vd, rs1, vs2, 5, vl);
}
vfloat32m1_t test_vfmacc_vv_f32m1_rm_tum(vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
// expected-error@+1 {{argument value 5 is outside the valid range [0, 4]}}
return __riscv_vfmacc_vv_f32m1_rm_tum(mask, vd, vs1, vs2, 5, vl);
}
vfloat32m1_t test_vfmacc_vf_f32m1_rm_tum(vbool32_t mask, vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
// expected-error@+1 {{argument value 5 is outside the valid range [0, 4]}}
return __riscv_vfmacc_vf_f32m1_rm_tum(mask, vd, rs1, vs2, 5, vl);
}
vfloat32m1_t test_vfmacc_vv_f32m1_rm_tumu(vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
// expected-error@+1 {{argument value 5 is outside the valid range [0, 4]}}
return __riscv_vfmacc_vv_f32m1_rm_tumu(mask, vd, vs1, vs2, 5, vl);
}
vfloat32m1_t test_vfmacc_vf_f32m1_rm_tumu(vbool32_t mask, vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
// expected-error@+1 {{argument value 5 is outside the valid range [0, 4]}}
return __riscv_vfmacc_vf_f32m1_rm_tumu(mask, vd, rs1, vs2, 5, vl);
}
vfloat32m1_t test_vfmacc_vv_f32m1_rm_mu(vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
// expected-error@+1 {{argument value 5 is outside the valid range [0, 4]}}
return __riscv_vfmacc_vv_f32m1_rm_mu(mask, vd, vs1, vs2, 5, vl);
}
vfloat32m1_t test_vfmacc_vf_f32m1_rm_mu(vbool32_t mask, vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
// expected-error@+1 {{argument value 5 is outside the valid range [0, 4]}}
return __riscv_vfmacc_vf_f32m1_rm_mu(mask, vd, rs1, vs2, 5, vl);
}

clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vfmadd-out-of-range.c

  • This file was added.
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \
// RUN: -target-feature +v -target-feature +zfh -target-feature +experimental-zvfh \
// RUN: -fsyntax-only -verify %s
#include <riscv_vector.h>
vfloat32m1_t test_vfmadd_vv_f32m1_rm(vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
// expected-error@+1 {{argument value 5 is outside the valid range [0, 4]}}
return __riscv_vfmadd_vv_f32m1_rm(vd, vs1, vs2, 5, vl);
}
vfloat32m1_t test_vfmadd_vf_f32m1_rm(vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
// expected-error@+1 {{argument value 5 is outside the valid range [0, 4]}}
return __riscv_vfmadd_vf_f32m1_rm(vd, rs1, vs2, 5, vl);
}
vfloat32m1_t test_vfmadd_vv_f32m1_rm_m(vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
// expected-error@+1 {{argument value 5 is outside the valid range [0, 4]}}
return __riscv_vfmadd_vv_f32m1_rm_m(mask, vd, vs1, vs2, 5, vl);
}
vfloat32m1_t test_vfmadd_vf_f32m1_rm_m(vbool32_t mask, vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
// expected-error@+1 {{argument value 5 is outside the valid range [0, 4]}}
return __riscv_vfmadd_vf_f32m1_rm_m(mask, vd, rs1, vs2, 5, vl);
}
vfloat32m1_t test_vfmadd_vv_f32m1_rm_tu(vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
// expected-error@+1 {{argument value 5 is outside the valid range [0, 4]}}
return __riscv_vfmadd_vv_f32m1_rm_tu(vd, vs1, vs2, 5, vl);
}
vfloat32m1_t test_vfmadd_vf_f32m1_rm_tu(vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
// expected-error@+1 {{argument value 5 is outside the valid range [0, 4]}}
return __riscv_vfmadd_vf_f32m1_rm_tu(vd, rs1, vs2, 5, vl);
}
vfloat32m1_t test_vfmadd_vv_f32m1_rm_tum(vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
// expected-error@+1 {{argument value 5 is outside the valid range [0, 4]}}
return __riscv_vfmadd_vv_f32m1_rm_tum(mask, vd, vs1, vs2, 5, vl);
}
vfloat32m1_t test_vfmadd_vf_f32m1_rm_tum(vbool32_t mask, vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
// expected-error@+1 {{argument value 5 is outside the valid range [0, 4]}}
return __riscv_vfmadd_vf_f32m1_rm_tum(mask, vd, rs1, vs2, 5, vl);
}
vfloat32m1_t test_vfmadd_vv_f32m1_rm_tumu(vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
// expected-error@+1 {{argument value 5 is outside the valid range [0, 4]}}
return __riscv_vfmadd_vv_f32m1_rm_tumu(mask, vd, vs1, vs2, 5, vl);
}
vfloat32m1_t test_vfmadd_vf_f32m1_rm_tumu(vbool32_t mask, vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
// expected-error@+1 {{argument value 5 is outside the valid range [0, 4]}}
return __riscv_vfmadd_vf_f32m1_rm_tumu(mask, vd, rs1, vs2, 5, vl);
}
vfloat32m1_t test_vfmadd_vv_f32m1_rm_mu(vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
// expected-error@+1 {{argument value 5 is outside the valid range [0, 4]}}
return __riscv_vfmadd_vv_f32m1_rm_mu(mask, vd, vs1, vs2, 5, vl);
}
vfloat32m1_t test_vfmadd_vf_f32m1_rm_mu(vbool32_t mask, vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
// expected-error@+1 {{argument value 5 is outside the valid range [0, 4]}}
return __riscv_vfmadd_vf_f32m1_rm_mu(mask, vd, rs1, vs2, 5, vl);
}

clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vfmsac-out-of-range.c

  • This file was added.
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \
// RUN: -target-feature +v -target-feature +zfh -target-feature +experimental-zvfh \
// RUN: -fsyntax-only -verify %s
#include <riscv_vector.h>
vfloat32m1_t test_vfmsac_vv_f32m1_rm(vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
// expected-error@+1 {{argument value 5 is outside the valid range [0, 4]}}
return __riscv_vfmsac_vv_f32m1_rm(vd, vs1, vs2, 5, vl);
}
vfloat32m1_t test_vfmsac_vf_f32m1_rm(vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
// expected-error@+1 {{argument value 5 is outside the valid range [0, 4]}}
return __riscv_vfmsac_vf_f32m1_rm(vd, rs1, vs2, 5, vl);
}
vfloat32m1_t test_vfmsac_vv_f32m1_rm_m(vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
// expected-error@+1 {{argument value 5 is outside the valid range [0, 4]}}
return __riscv_vfmsac_vv_f32m1_rm_m(mask, vd, vs1, vs2, 5, vl);
}
vfloat32m1_t test_vfmsac_vf_f32m1_rm_m(vbool32_t mask, vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
// expected-error@+1 {{argument value 5 is outside the valid range [0, 4]}}
return __riscv_vfmsac_vf_f32m1_rm_m(mask, vd, rs1, vs2, 5, vl);
}
vfloat32m1_t test_vfmsac_vv_f32m1_rm_tu(vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
// expected-error@+1 {{argument value 5 is outside the valid range [0, 4]}}
return __riscv_vfmsac_vv_f32m1_rm_tu(vd, vs1, vs2, 5, vl);
}
vfloat32m1_t test_vfmsac_vf_f32m1_rm_tu(vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
// expected-error@+1 {{argument value 5 is outside the valid range [0, 4]}}
return __riscv_vfmsac_vf_f32m1_rm_tu(vd, rs1, vs2, 5, vl);
}
vfloat32m1_t test_vfmsac_vv_f32m1_rm_tum(vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
// expected-error@+1 {{argument value 5 is outside the valid range [0, 4]}}
return __riscv_vfmsac_vv_f32m1_rm_tum(mask, vd, vs1, vs2, 5, vl);
}
vfloat32m1_t test_vfmsac_vf_f32m1_rm_tum(vbool32_t mask, vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
// expected-error@+1 {{argument value 5 is outside the valid range [0, 4]}}
return __riscv_vfmsac_vf_f32m1_rm_tum(mask, vd, rs1, vs2, 5, vl);
}
vfloat32m1_t test_vfmsac_vv_f32m1_rm_tumu(vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
// expected-error@+1 {{argument value 5 is outside the valid range [0, 4]}}
return __riscv_vfmsac_vv_f32m1_rm_tumu(mask, vd, vs1, vs2, 5, vl);
}
vfloat32m1_t test_vfmsac_vf_f32m1_rm_tumu(vbool32_t mask, vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
// expected-error@+1 {{argument value 5 is outside the valid range [0, 4]}}
return __riscv_vfmsac_vf_f32m1_rm_tumu(mask, vd, rs1, vs2, 5, vl);
}
vfloat32m1_t test_vfmsac_vv_f32m1_rm_mu(vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
// expected-error@+1 {{argument value 5 is outside the valid range [0, 4]}}
return __riscv_vfmsac_vv_f32m1_rm_mu(mask, vd, vs1, vs2, 5, vl);
}
vfloat32m1_t test_vfmsac_vf_f32m1_rm_mu(vbool32_t mask, vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
// expected-error@+1 {{argument value 5 is outside the valid range [0, 4]}}
return __riscv_vfmsac_vf_f32m1_rm_mu(mask, vd, rs1, vs2, 5, vl);
}

clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vfmsub-out-of-range.c

  • This file was added.
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \
// RUN: -target-feature +v -target-feature +zfh -target-feature +experimental-zvfh \
// RUN: -fsyntax-only -verify %s
#include <riscv_vector.h>
vfloat32m1_t test_vfmsub_vv_f32m1_rm(vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
// expected-error@+1 {{argument value 5 is outside the valid range [0, 4]}}
return __riscv_vfmsub_vv_f32m1_rm(vd, vs1, vs2, 5, vl);
}
vfloat32m1_t test_vfmsub_vf_f32m1_rm(vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
// expected-error@+1 {{argument value 5 is outside the valid range [0, 4]}}
return __riscv_vfmsub_vf_f32m1_rm(vd, rs1, vs2, 5, vl);
}
vfloat32m1_t test_vfmsub_vv_f32m1_rm_m(vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
// expected-error@+1 {{argument value 5 is outside the valid range [0, 4]}}
return __riscv_vfmsub_vv_f32m1_rm_m(mask, vd, vs1, vs2, 5, vl);
}
vfloat32m1_t test_vfmsub_vf_f32m1_rm_m(vbool32_t mask, vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
// expected-error@+1 {{argument value 5 is outside the valid range [0, 4]}}
return __riscv_vfmsub_vf_f32m1_rm_m(mask, vd, rs1, vs2, 5, vl);
}
vfloat32m1_t test_vfmsub_vv_f32m1_rm_tu(vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
// expected-error@+1 {{argument value 5 is outside the valid range [0, 4]}}
return __riscv_vfmsub_vv_f32m1_rm_tu(vd, vs1, vs2, 5, vl);
}
vfloat32m1_t test_vfmsub_vf_f32m1_rm_tu(vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
// expected-error@+1 {{argument value 5 is outside the valid range [0, 4]}}
return __riscv_vfmsub_vf_f32m1_rm_tu(vd, rs1, vs2, 5, vl);
}
vfloat32m1_t test_vfmsub_vv_f32m1_rm_tum(vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
// expected-error@+1 {{argument value 5 is outside the valid range [0, 4]}}
return __riscv_vfmsub_vv_f32m1_rm_tum(mask, vd, vs1, vs2, 5, vl);
}
vfloat32m1_t test_vfmsub_vf_f32m1_rm_tum(vbool32_t mask, vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
// expected-error@+1 {{argument value 5 is outside the valid range [0, 4]}}
return __riscv_vfmsub_vf_f32m1_rm_tum(mask, vd, rs1, vs2, 5, vl);
}
vfloat32m1_t test_vfmsub_vv_f32m1_rm_tumu(vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
// expected-error@+1 {{argument value 5 is outside the valid range [0, 4]}}
return __riscv_vfmsub_vv_f32m1_rm_tumu(mask, vd, vs1, vs2, 5, vl);
}
vfloat32m1_t test_vfmsub_vf_f32m1_rm_tumu(vbool32_t mask, vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
// expected-error@+1 {{argument value 5 is outside the valid range [0, 4]}}
return __riscv_vfmsub_vf_f32m1_rm_tumu(mask, vd, rs1, vs2, 5, vl);
}
vfloat32m1_t test_vfmsub_vv_f32m1_rm_mu(vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
// expected-error@+1 {{argument value 5 is outside the valid range [0, 4]}}
return __riscv_vfmsub_vv_f32m1_rm_mu(mask, vd, vs1, vs2, 5, vl);
}
vfloat32m1_t test_vfmsub_vf_f32m1_rm_mu(vbool32_t mask, vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
// expected-error@+1 {{argument value 5 is outside the valid range [0, 4]}}
return __riscv_vfmsub_vf_f32m1_rm_mu(mask, vd, rs1, vs2, 5, vl);
}

clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vfnmacc-out-of-range.c

  • This file was added.
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \
// RUN: -target-feature +v -target-feature +zfh -target-feature +experimental-zvfh \
// RUN: -fsyntax-only -verify %s
#include <riscv_vector.h>
vfloat32m1_t test_vfnmacc_vv_f32m1_rm(vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
// expected-error@+1 {{argument value 5 is outside the valid range [0, 4]}}
return __riscv_vfnmacc_vv_f32m1_rm(vd, vs1, vs2, 5, vl);
}
vfloat32m1_t test_vfnmacc_vf_f32m1_rm(vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
// expected-error@+1 {{argument value 5 is outside the valid range [0, 4]}}
return __riscv_vfnmacc_vf_f32m1_rm(vd, rs1, vs2, 5, vl);
}
vfloat32m1_t test_vfnmacc_vv_f32m1_rm_m(vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
// expected-error@+1 {{argument value 5 is outside the valid range [0, 4]}}
return __riscv_vfnmacc_vv_f32m1_rm_m(mask, vd, vs1, vs2, 5, vl);
}
vfloat32m1_t test_vfnmacc_vf_f32m1_rm_m(vbool32_t mask, vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
// expected-error@+1 {{argument value 5 is outside the valid range [0, 4]}}
return __riscv_vfnmacc_vf_f32m1_rm_m(mask, vd, rs1, vs2, 5, vl);
}
vfloat32m1_t test_vfnmacc_vv_f32m1_rm_tu(vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
// expected-error@+1 {{argument value 5 is outside the valid range [0, 4]}}
return __riscv_vfnmacc_vv_f32m1_rm_tu(vd, vs1, vs2, 5, vl);
}
vfloat32m1_t test_vfnmacc_vf_f32m1_rm_tu(vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
// expected-error@+1 {{argument value 5 is outside the valid range [0, 4]}}
return __riscv_vfnmacc_vf_f32m1_rm_tu(vd, rs1, vs2, 5, vl);
}
vfloat32m1_t test_vfnmacc_vv_f32m1_rm_tum(vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
// expected-error@+1 {{argument value 5 is outside the valid range [0, 4]}}
return __riscv_vfnmacc_vv_f32m1_rm_tum(mask, vd, vs1, vs2, 5, vl);
}
vfloat32m1_t test_vfnmacc_vf_f32m1_rm_tum(vbool32_t mask, vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
// expected-error@+1 {{argument value 5 is outside the valid range [0, 4]}}
return __riscv_vfnmacc_vf_f32m1_rm_tum(mask, vd, rs1, vs2, 5, vl);
}
vfloat32m1_t test_vfnmacc_vv_f32m1_rm_tumu(vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
// expected-error@+1 {{argument value 5 is outside the valid range [0, 4]}}
return __riscv_vfnmacc_vv_f32m1_rm_tumu(mask, vd, vs1, vs2, 5, vl);
}
vfloat32m1_t test_vfnmacc_vf_f32m1_rm_tumu(vbool32_t mask, vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
// expected-error@+1 {{argument value 5 is outside the valid range [0, 4]}}
return __riscv_vfnmacc_vf_f32m1_rm_tumu(mask, vd, rs1, vs2, 5, vl);
}
vfloat32m1_t test_vfnmacc_vv_f32m1_rm_mu(vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
// expected-error@+1 {{argument value 5 is outside the valid range [0, 4]}}
return __riscv_vfnmacc_vv_f32m1_rm_mu(mask, vd, vs1, vs2, 5, vl);
}
vfloat32m1_t test_vfnmacc_vf_f32m1_rm_mu(vbool32_t mask, vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
// expected-error@+1 {{argument value 5 is outside the valid range [0, 4]}}
return __riscv_vfnmacc_vf_f32m1_rm_mu(mask, vd, rs1, vs2, 5, vl);
}

clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vfnmadd-out-of-range.c

  • This file was added.
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \
// RUN: -target-feature +v -target-feature +zfh -target-feature +experimental-zvfh \
// RUN: -fsyntax-only -verify %s
#include <riscv_vector.h>
vfloat32m1_t test_vfnmadd_vv_f32m1_rm(vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
// expected-error@+1 {{argument value 5 is outside the valid range [0, 4]}}
return __riscv_vfnmadd_vv_f32m1_rm(vd, vs1, vs2, 5, vl);
}
vfloat32m1_t test_vfnmadd_vf_f32m1_rm(vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
// expected-error@+1 {{argument value 5 is outside the valid range [0, 4]}}
return __riscv_vfnmadd_vf_f32m1_rm(vd, rs1, vs2, 5, vl);
}
vfloat32m1_t test_vfnmadd_vv_f32m1_rm_m(vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
// expected-error@+1 {{argument value 5 is outside the valid range [0, 4]}}
return __riscv_vfnmadd_vv_f32m1_rm_m(mask, vd, vs1, vs2, 5, vl);
}
vfloat32m1_t test_vfnmadd_vf_f32m1_rm_m(vbool32_t mask, vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
// expected-error@+1 {{argument value 5 is outside the valid range [0, 4]}}
return __riscv_vfnmadd_vf_f32m1_rm_m(mask, vd, rs1, vs2, 5, vl);
}
vfloat32m1_t test_vfnmadd_vv_f32m1_rm_tu(vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
// expected-error@+1 {{argument value 5 is outside the valid range [0, 4]}}
return __riscv_vfnmadd_vv_f32m1_rm_tu(vd, vs1, vs2, 5, vl);
}
vfloat32m1_t test_vfnmadd_vf_f32m1_rm_tu(vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
// expected-error@+1 {{argument value 5 is outside the valid range [0, 4]}}
return __riscv_vfnmadd_vf_f32m1_rm_tu(vd, rs1, vs2, 5, vl);
}
vfloat32m1_t test_vfnmadd_vv_f32m1_rm_tum(vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
// expected-error@+1 {{argument value 5 is outside the valid range [0, 4]}}
return __riscv_vfnmadd_vv_f32m1_rm_tum(mask, vd, vs1, vs2, 5, vl);
}
vfloat32m1_t test_vfnmadd_vf_f32m1_rm_tum(vbool32_t mask, vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
// expected-error@+1 {{argument value 5 is outside the valid range [0, 4]}}
return __riscv_vfnmadd_vf_f32m1_rm_tum(mask, vd, rs1, vs2, 5, vl);
}
vfloat32m1_t test_vfnmadd_vv_f32m1_rm_tumu(vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
// expected-error@+1 {{argument value 5 is outside the valid range [0, 4]}}
return __riscv_vfnmadd_vv_f32m1_rm_tumu(mask, vd, vs1, vs2, 5, vl);
}
vfloat32m1_t test_vfnmadd_vf_f32m1_rm_tumu(vbool32_t mask, vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
// expected-error@+1 {{argument value 5 is outside the valid range [0, 4]}}
return __riscv_vfnmadd_vf_f32m1_rm_tumu(mask, vd, rs1, vs2, 5, vl);
}
vfloat32m1_t test_vfnmadd_vv_f32m1_rm_mu(vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
// expected-error@+1 {{argument value 5 is outside the valid range [0, 4]}}
return __riscv_vfnmadd_vv_f32m1_rm_mu(mask, vd, vs1, vs2, 5, vl);
}
vfloat32m1_t test_vfnmadd_vf_f32m1_rm_mu(vbool32_t mask, vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
// expected-error@+1 {{argument value 5 is outside the valid range [0, 4]}}
return __riscv_vfnmadd_vf_f32m1_rm_mu(mask, vd, rs1, vs2, 5, vl);
}

clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vfnmsac-out-of-range.c

  • This file was added.
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \
// RUN: -target-feature +v -target-feature +zfh -target-feature +experimental-zvfh \
// RUN: -fsyntax-only -verify %s
#include <riscv_vector.h>
vfloat32m1_t test_vfnmsac_vv_f32m1_rm(vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
// expected-error@+1 {{argument value 5 is outside the valid range [0, 4]}}
return __riscv_vfnmsac_vv_f32m1_rm(vd, vs1, vs2, 5, vl);
}
vfloat32m1_t test_vfnmsac_vf_f32m1_rm(vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
// expected-error@+1 {{argument value 5 is outside the valid range [0, 4]}}
return __riscv_vfnmsac_vf_f32m1_rm(vd, rs1, vs2, 5, vl);
}
vfloat32m1_t test_vfnmsac_vv_f32m1_rm_m(vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
// expected-error@+1 {{argument value 5 is outside the valid range [0, 4]}}
return __riscv_vfnmsac_vv_f32m1_rm_m(mask, vd, vs1, vs2, 5, vl);
}
vfloat32m1_t test_vfnmsac_vf_f32m1_rm_m(vbool32_t mask, vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
// expected-error@+1 {{argument value 5 is outside the valid range [0, 4]}}
return __riscv_vfnmsac_vf_f32m1_rm_m(mask, vd, rs1, vs2, 5, vl);
}
vfloat32m1_t test_vfnmsac_vv_f32m1_rm_tu(vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
// expected-error@+1 {{argument value 5 is outside the valid range [0, 4]}}
return __riscv_vfnmsac_vv_f32m1_rm_tu(vd, vs1, vs2, 5, vl);
}
vfloat32m1_t test_vfnmsac_vf_f32m1_rm_tu(vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
// expected-error@+1 {{argument value 5 is outside the valid range [0, 4]}}
return __riscv_vfnmsac_vf_f32m1_rm_tu(vd, rs1, vs2, 5, vl);
}
vfloat32m1_t test_vfnmsac_vv_f32m1_rm_tum(vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
// expected-error@+1 {{argument value 5 is outside the valid range [0, 4]}}
return __riscv_vfnmsac_vv_f32m1_rm_tum(mask, vd, vs1, vs2, 5, vl);
}
vfloat32m1_t test_vfnmsac_vf_f32m1_rm_tum(vbool32_t mask, vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
// expected-error@+1 {{argument value 5 is outside the valid range [0, 4]}}
return __riscv_vfnmsac_vf_f32m1_rm_tum(mask, vd, rs1, vs2, 5, vl);
}
vfloat32m1_t test_vfnmsac_vv_f32m1_rm_tumu(vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
// expected-error@+1 {{argument value 5 is outside the valid range [0, 4]}}
return __riscv_vfnmsac_vv_f32m1_rm_tumu(mask, vd, vs1, vs2, 5, vl);
}
vfloat32m1_t test_vfnmsac_vf_f32m1_rm_tumu(vbool32_t mask, vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
// expected-error@+1 {{argument value 5 is outside the valid range [0, 4]}}
return __riscv_vfnmsac_vf_f32m1_rm_tumu(mask, vd, rs1, vs2, 5, vl);
}
vfloat32m1_t test_vfnmsac_vv_f32m1_rm_mu(vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
// expected-error@+1 {{argument value 5 is outside the valid range [0, 4]}}
return __riscv_vfnmsac_vv_f32m1_rm_mu(mask, vd, vs1, vs2, 5, vl);
}
vfloat32m1_t test_vfnmsac_vf_f32m1_rm_mu(vbool32_t mask, vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
// expected-error@+1 {{argument value 5 is outside the valid range [0, 4]}}
return __riscv_vfnmsac_vf_f32m1_rm_mu(mask, vd, rs1, vs2, 5, vl);
}

clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/vfnmsub-out-of-range.c

  • This file was added.
// REQUIRES: riscv-registered-target
// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \
// RUN: -target-feature +v -target-feature +zfh -target-feature +experimental-zvfh \
// RUN: -fsyntax-only -verify %s
#include <riscv_vector.h>
vfloat32m1_t test_vfnmsub_vv_f32m1_rm(vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
// expected-error@+1 {{argument value 5 is outside the valid range [0, 4]}}
return __riscv_vfnmsub_vv_f32m1_rm(vd, vs1, vs2, 5, vl);
}
vfloat32m1_t test_vfnmsub_vf_f32m1_rm(vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
// expected-error@+1 {{argument value 5 is outside the valid range [0, 4]}}
return __riscv_vfnmsub_vf_f32m1_rm(vd, rs1, vs2, 5, vl);
}
vfloat32m1_t test_vfnmsub_vv_f32m1_rm_m(vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
// expected-error@+1 {{argument value 5 is outside the valid range [0, 4]}}
return __riscv_vfnmsub_vv_f32m1_rm_m(mask, vd, vs1, vs2, 5, vl);
}
vfloat32m1_t test_vfnmsub_vf_f32m1_rm_m(vbool32_t mask, vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
// expected-error@+1 {{argument value 5 is outside the valid range [0, 4]}}
return __riscv_vfnmsub_vf_f32m1_rm_m(mask, vd, rs1, vs2, 5, vl);
}
vfloat32m1_t test_vfnmsub_vv_f32m1_rm_tu(vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
// expected-error@+1 {{argument value 5 is outside the valid range [0, 4]}}
return __riscv_vfnmsub_vv_f32m1_rm_tu(vd, vs1, vs2, 5, vl);
}
vfloat32m1_t test_vfnmsub_vf_f32m1_rm_tu(vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
// expected-error@+1 {{argument value 5 is outside the valid range [0, 4]}}
return __riscv_vfnmsub_vf_f32m1_rm_tu(vd, rs1, vs2, 5, vl);
}
vfloat32m1_t test_vfnmsub_vv_f32m1_rm_tum(vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
// expected-error@+1 {{argument value 5 is outside the valid range [0, 4]}}
return __riscv_vfnmsub_vv_f32m1_rm_tum(mask, vd, vs1, vs2, 5, vl);
}
vfloat32m1_t test_vfnmsub_vf_f32m1_rm_tum(vbool32_t mask, vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
// expected-error@+1 {{argument value 5 is outside the valid range [0, 4]}}
return __riscv_vfnmsub_vf_f32m1_rm_tum(mask, vd, rs1, vs2, 5, vl);
}
vfloat32m1_t test_vfnmsub_vv_f32m1_rm_tumu(vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
// expected-error@+1 {{argument value 5 is outside the valid range [0, 4]}}
return __riscv_vfnmsub_vv_f32m1_rm_tumu(mask, vd, vs1, vs2, 5, vl);
}
vfloat32m1_t test_vfnmsub_vf_f32m1_rm_tumu(vbool32_t mask, vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
// expected-error@+1 {{argument value 5 is outside the valid range [0, 4]}}
return __riscv_vfnmsub_vf_f32m1_rm_tumu(mask, vd, rs1, vs2, 5, vl);
}
vfloat32m1_t test_vfnmsub_vv_f32m1_rm_mu(vbool32_t mask, vfloat32m1_t vd, vfloat32m1_t vs1, vfloat32m1_t vs2, size_t vl) {
// expected-error@+1 {{argument value 5 is outside the valid range [0, 4]}}
return __riscv_vfnmsub_vv_f32m1_rm_mu(mask, vd, vs1, vs2, 5, vl);
}
vfloat32m1_t test_vfnmsub_vf_f32m1_rm_mu(vbool32_t mask, vfloat32m1_t vd, float rs1, vfloat32m1_t vs2, size_t vl) {
// expected-error@+1 {{argument value 5 is outside the valid range [0, 4]}}
return __riscv_vfnmsub_vf_f32m1_rm_mu(mask, vd, rs1, vs2, 5, vl);
}

llvm/include/llvm/IR/IntrinsicsRISCV.td

Show First 20 Lines • Show All 775 Lines • ▼ Show 20 Lines class RISCVTernaryAAXAMasked
: DefaultAttrsIntrinsic<[llvm_anyvector_ty], : DefaultAttrsIntrinsic<[llvm_anyvector_ty],
[LLVMMatchType<0>, llvm_any_ty, LLVMMatchType<0>, [LLVMMatchType<0>, llvm_any_ty, LLVMMatchType<0>,
LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>, LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
llvm_anyint_ty, LLVMMatchType<2>], llvm_anyint_ty, LLVMMatchType<2>],
[ImmArg<ArgIndex<5>>, IntrNoMem]>, RISCVVIntrinsic { [ImmArg<ArgIndex<5>>, IntrNoMem]>, RISCVVIntrinsic {
let ScalarOperand = 1; let ScalarOperand = 1;
let VLOperand = 4; let VLOperand = 4;
} }
// UnMasked Vector Multiply-Add operations, its first operand can not be undef.
// Input: (vector_in, vector_in/scalar, vector_in, frm, vl, policy)
class RISCVTernaryAAXAUnMaskedRoundingMode
: DefaultAttrsIntrinsic<[llvm_anyvector_ty],
[LLVMMatchType<0>, llvm_any_ty, LLVMMatchType<0>,
llvm_anyint_ty, LLVMMatchType<2>, LLVMMatchType<2>],
[ImmArg<ArgIndex<3>>, ImmArg<ArgIndex<5>>, IntrNoMem]>,
RISCVVIntrinsic {
let ScalarOperand = 1;
let VLOperand = 4;
}
// Masked Vector Multiply-Add operations, its first operand can not be undef.
// Input: (vector_in, vector_in/scalar, vector_in, mask, frm, vl, policy
class RISCVTernaryAAXAMaskedRoundingMode
: DefaultAttrsIntrinsic<[llvm_anyvector_ty],
[LLVMMatchType<0>, llvm_any_ty, LLVMMatchType<0>,
LLVMScalarOrSameVectorWidth<0, llvm_i1_ty>,
llvm_anyint_ty, LLVMMatchType<2>, LLVMMatchType<2>],
[ImmArg<ArgIndex<4>>, ImmArg<ArgIndex<6>>, IntrNoMem]>,
RISCVVIntrinsic {
let ScalarOperand = 1;
let VLOperand = 5;
}
// UnMasked Widening Vector Multiply-Add operations, its first operand can not be undef. // UnMasked Widening Vector Multiply-Add operations, its first operand can not be undef.
// Input: (vector_in, vector_in/scalar, vector_in, vl, policy) // Input: (vector_in, vector_in/scalar, vector_in, vl, policy)
class RISCVTernaryWideUnMasked class RISCVTernaryWideUnMasked
: DefaultAttrsIntrinsic< [llvm_anyvector_ty], : DefaultAttrsIntrinsic< [llvm_anyvector_ty],
[LLVMMatchType<0>, llvm_any_ty, llvm_anyvector_ty, [LLVMMatchType<0>, llvm_any_ty, llvm_anyvector_ty,
llvm_anyint_ty, LLVMMatchType<3>], llvm_anyint_ty, LLVMMatchType<3>],
[ImmArg<ArgIndex<4>>, IntrNoMem] >, RISCVVIntrinsic { [ImmArg<ArgIndex<4>>, IntrNoMem] >, RISCVVIntrinsic {
let ScalarOperand = 1; let ScalarOperand = 1;
▲ Show 20 Lines • Show All 404 Lines • ▼ Show 20 Lines
multiclass RVVSlide { multiclass RVVSlide {
def "int_riscv_" # NAME : RVVSlideUnMasked; def "int_riscv_" # NAME : RVVSlideUnMasked;
def "int_riscv_" # NAME # "_mask" : RVVSlideMasked; def "int_riscv_" # NAME # "_mask" : RVVSlideMasked;
} }
multiclass RISCVTernaryAAXA { multiclass RISCVTernaryAAXA {
def "int_riscv_" # NAME : RISCVTernaryAAXAUnMasked; def "int_riscv_" # NAME : RISCVTernaryAAXAUnMasked;
def "int_riscv_" # NAME # "_mask" : RISCVTernaryAAXAMasked; def "int_riscv_" # NAME # "_mask" : RISCVTernaryAAXAMasked;
} }
multiclass RISCVTernaryAAXARoundingMode {
def "int_riscv_" # NAME : RISCVTernaryAAXAUnMaskedRoundingMode;
def "int_riscv_" # NAME # "_mask" : RISCVTernaryAAXAMaskedRoundingMode;
}
multiclass RISCVCompare { multiclass RISCVCompare {
def "int_riscv_" # NAME : RISCVCompareUnMasked; def "int_riscv_" # NAME : RISCVCompareUnMasked;
def "int_riscv_" # NAME # "_mask" : RISCVCompareMasked; def "int_riscv_" # NAME # "_mask" : RISCVCompareMasked;
} }
multiclass RISCVClassify { multiclass RISCVClassify {
def "int_riscv_" # NAME : RISCVClassifyUnMasked; def "int_riscv_" # NAME : RISCVClassifyUnMasked;
def "int_riscv_" # NAME # "_mask" : RISCVClassifyMasked; def "int_riscv_" # NAME # "_mask" : RISCVClassifyMasked;
} }
▲ Show 20 Lines • Show All 201 Lines • ▼ Show 20 Lines
} }
defm vfmul : RISCVBinaryAAXRoundingMode; defm vfmul : RISCVBinaryAAXRoundingMode;
defm vfdiv : RISCVBinaryAAXRoundingMode; defm vfdiv : RISCVBinaryAAXRoundingMode;
defm vfrdiv : RISCVBinaryAAXRoundingMode; defm vfrdiv : RISCVBinaryAAXRoundingMode;
defm vfwmul : RISCVBinaryABXRoundingMode; defm vfwmul : RISCVBinaryABXRoundingMode;
defm vfmacc : RISCVTernaryAAXA; defm vfmacc : RISCVTernaryAAXARoundingMode;
defm vfnmacc : RISCVTernaryAAXA; defm vfnmacc : RISCVTernaryAAXARoundingMode;
defm vfmsac : RISCVTernaryAAXA; defm vfmsac : RISCVTernaryAAXARoundingMode;
defm vfnmsac : RISCVTernaryAAXA; defm vfnmsac : RISCVTernaryAAXARoundingMode;
defm vfmadd : RISCVTernaryAAXA; defm vfmadd : RISCVTernaryAAXARoundingMode;
defm vfnmadd : RISCVTernaryAAXA; defm vfnmadd : RISCVTernaryAAXARoundingMode;
defm vfmsub : RISCVTernaryAAXA; defm vfmsub : RISCVTernaryAAXARoundingMode;
defm vfnmsub : RISCVTernaryAAXA; defm vfnmsub : RISCVTernaryAAXARoundingMode;
defm vfwmacc : RISCVTernaryWide; defm vfwmacc : RISCVTernaryWide;
defm vfwnmacc : RISCVTernaryWide; defm vfwnmacc : RISCVTernaryWide;
defm vfwmsac : RISCVTernaryWide; defm vfwmsac : RISCVTernaryWide;
defm vfwnmsac : RISCVTernaryWide; defm vfwnmsac : RISCVTernaryWide;
defm vfsqrt : RISCVUnaryAA; defm vfsqrt : RISCVUnaryAA;
defm vfrsqrt7 : RISCVUnaryAA; defm vfrsqrt7 : RISCVUnaryAA;
▲ Show 20 Lines • Show All 304 Lines • Show Last 20 Lines

llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 1,407 Lines • ▼ Show 20 Linesclass VPseudoTernaryNoMaskWithPolicy<VReg RetClass,
let mayStore = 0; let mayStore = 0;
let hasSideEffects = 0; let hasSideEffects = 0;
let Constraints = !interleave([Constraint, "$rd = $rs3"], ","); let Constraints = !interleave([Constraint, "$rd = $rs3"], ",");
let HasVecPolicyOp = 1; let HasVecPolicyOp = 1;
let HasVLOp = 1; let HasVLOp = 1;
let HasSEWOp = 1; let HasSEWOp = 1;
} }
class VPseudoTernaryNoMaskWithPolicyRoundingMode<VReg RetClass,
RegisterClass Op1Class,
DAGOperand Op2Class,
string Constraint> :
Pseudo<(outs RetClass:$rd),
(ins RetClass:$rs3, Op1Class:$rs1, Op2Class:$rs2,
ixlenimm:$rm, AVL:$vl, ixlenimm:$sew, ixlenimm:$policy),
[]>,
RISCVVPseudo {
let mayLoad = 0;
let mayStore = 0;
let hasSideEffects = 0;
let Constraints = !interleave([Constraint, "$rd = $rs3"], ",");
let HasVecPolicyOp = 1;
let HasVLOp = 1;
let HasSEWOp = 1;
let HasRoundModeOp = 1;
let UsesVXRM = 0;
}
class VPseudoUSSegLoadNoMask<VReg RetClass, int EEW, bits<4> NF>: class VPseudoUSSegLoadNoMask<VReg RetClass, int EEW, bits<4> NF>:
Pseudo<(outs RetClass:$rd), Pseudo<(outs RetClass:$rd),
(ins RetClass:$dest, GPRMem:$rs1, AVL:$vl, (ins RetClass:$dest, GPRMem:$rs1, AVL:$vl,
ixlenimm:$sew, ixlenimm:$policy),[]>, ixlenimm:$sew, ixlenimm:$policy),[]>,
RISCVVPseudo, RISCVVPseudo,
RISCVVLSEG<NF, /*Masked*/0, /*Strided*/0, /*FF*/0, !logtwo(EEW), VLMul> { RISCVVLSEG<NF, /*Masked*/0, /*Strided*/0, /*FF*/0, !logtwo(EEW), VLMul> {
let mayLoad = 1; let mayLoad = 1;
let mayStore = 0; let mayStore = 0;
▲ Show 20 Lines • Show All 1,744 Lines • ▼ Show 20 Linesmulticlass VPseudoTernaryWithPolicy<VReg RetClass,
let VLMul = MInfo.value in { let VLMul = MInfo.value in {
let isCommutable = Commutable in let isCommutable = Commutable in
def "_" # MInfo.MX : VPseudoTernaryNoMaskWithPolicy<RetClass, Op1Class, Op2Class, Constraint>; def "_" # MInfo.MX : VPseudoTernaryNoMaskWithPolicy<RetClass, Op1Class, Op2Class, Constraint>;
def "_" # MInfo.MX # "_MASK" : VPseudoBinaryMaskPolicy<RetClass, Op1Class, Op2Class, Constraint>, def "_" # MInfo.MX # "_MASK" : VPseudoBinaryMaskPolicy<RetClass, Op1Class, Op2Class, Constraint>,
RISCVMaskedPseudo</*MaskOpIdx*/ 3>; RISCVMaskedPseudo</*MaskOpIdx*/ 3>;
} }
} }
multiclass VPseudoTernaryWithPolicyRoundingMode<VReg RetClass,
RegisterClass Op1Class,
DAGOperand Op2Class,
LMULInfo MInfo,
string Constraint = "",
bit Commutable = 0> {
let VLMul = MInfo.value in {
let isCommutable = Commutable in
def "_" # MInfo.MX :
VPseudoTernaryNoMaskWithPolicyRoundingMode<RetClass, Op1Class,
Op2Class, Constraint>;
def "_" # MInfo.MX # "_MASK" :
VPseudoBinaryMaskPolicyRoundingMode<RetClass, Op1Class,
Op2Class, Constraint,
/* UsesVXRM = */ 0>,
RISCVMaskedPseudo</*MaskOpIdx*/ 3>;
}
}
multiclass VPseudoTernaryV_VV_AAXA<LMULInfo m, string Constraint = ""> { multiclass VPseudoTernaryV_VV_AAXA<LMULInfo m, string Constraint = ""> {
defm _VV : VPseudoTernaryWithPolicy<m.vrclass, m.vrclass, m.vrclass, m, defm _VV : VPseudoTernaryWithPolicy<m.vrclass, m.vrclass, m.vrclass, m,
Constraint, /*Commutable*/1>; Constraint, /*Commutable*/1>;
} }
multiclass VPseudoTernaryV_VV_AAXA_RM<LMULInfo m, string Constraint = ""> {
defm _VV : VPseudoTernaryWithPolicyRoundingMode<m.vrclass, m.vrclass, m.vrclass, m,
Constraint, /*Commutable*/1>;
}
multiclass VPseudoTernaryV_VX_AAXA<LMULInfo m, string Constraint = ""> { multiclass VPseudoTernaryV_VX_AAXA<LMULInfo m, string Constraint = ""> {
defm "_VX" : VPseudoTernaryWithPolicy<m.vrclass, GPR, m.vrclass, m, defm "_VX" : VPseudoTernaryWithPolicy<m.vrclass, GPR, m.vrclass, m,
Constraint, /*Commutable*/1>; Constraint, /*Commutable*/1>;
} }
multiclass VPseudoTernaryV_VF_AAXA<LMULInfo m, FPR_Info f, string Constraint = ""> { multiclass VPseudoTernaryV_VF_AAXA<LMULInfo m, FPR_Info f, string Constraint = ""> {
defm "_V" # f.FX : VPseudoTernaryWithPolicy<m.vrclass, f.fprclass, defm "_V" # f.FX : VPseudoTernaryWithPolicy<m.vrclass, f.fprclass,
m.vrclass, m, Constraint, m.vrclass, m, Constraint,
/*Commutable*/1>; /*Commutable*/1>;
} }
multiclass VPseudoTernaryV_VF_AAXA_RM<LMULInfo m, FPR_Info f, string Constraint = ""> {
defm "_V" # f.FX : VPseudoTernaryWithPolicyRoundingMode<m.vrclass, f.fprclass,
m.vrclass, m, Constraint,
/*Commutable*/1>;
}
multiclass VPseudoTernaryW_VV<LMULInfo m> { multiclass VPseudoTernaryW_VV<LMULInfo m> {
defvar constraint = "@earlyclobber $rd"; defvar constraint = "@earlyclobber $rd";
defm _VV : VPseudoTernaryWithPolicy<m.wvrclass, m.vrclass, m.vrclass, m, defm _VV : VPseudoTernaryWithPolicy<m.wvrclass, m.vrclass, m.vrclass, m,
constraint>; constraint>;
} }
multiclass VPseudoTernaryW_VX<LMULInfo m> { multiclass VPseudoTernaryW_VX<LMULInfo m> {
defvar constraint = "@earlyclobber $rd"; defvar constraint = "@earlyclobber $rd";
▲ Show 20 Lines • Show All 62 Lines • ▼ Show 20 Lines foreach m = f.MxList in {
defvar ReadVFMulAddF_MX = !cast<SchedRead>("ReadVFMulAddF_" # mx); defvar ReadVFMulAddF_MX = !cast<SchedRead>("ReadVFMulAddF_" # mx);
defm "" : VPseudoTernaryV_VF_AAXA<m, f, Constraint>, defm "" : VPseudoTernaryV_VF_AAXA<m, f, Constraint>,
Sched<[WriteVFMulAddF_MX, ReadVFMulAddV_MX, ReadVFMulAddV_MX, ReadVFMulAddF_MX, ReadVMask]>; Sched<[WriteVFMulAddF_MX, ReadVFMulAddV_MX, ReadVFMulAddV_MX, ReadVFMulAddF_MX, ReadVMask]>;
} }
} }
} }
multiclass VPseudoVMAC_VV_VF_AAXA_RM<string Constraint = ""> {
foreach m = MxListF in {
defvar mx = m.MX;
defvar WriteVFMulAddV_MX = !cast<SchedWrite>("WriteVFMulAddV_" # mx);
defvar ReadVFMulAddV_MX = !cast<SchedRead>("ReadVFMulAddV_" # mx);
defm "" : VPseudoTernaryV_VV_AAXA_RM<m, Constraint>,
Sched<[WriteVFMulAddV_MX, ReadVFMulAddV_MX, ReadVFMulAddV_MX, ReadVFMulAddV_MX, ReadVMask]>;
}
foreach f = FPList in {
foreach m = f.MxList in {
defvar mx = m.MX;
defvar WriteVFMulAddF_MX = !cast<SchedWrite>("WriteVFMulAddF_" # mx);
defvar ReadVFMulAddV_MX = !cast<SchedRead>("ReadVFMulAddV_" # mx);
defvar ReadVFMulAddF_MX = !cast<SchedRead>("ReadVFMulAddF_" # mx);
defm "" : VPseudoTernaryV_VF_AAXA_RM<m, f, Constraint>,
Sched<[WriteVFMulAddF_MX, ReadVFMulAddV_MX, ReadVFMulAddV_MX, ReadVFMulAddF_MX, ReadVMask]>;
}
}
}
multiclass VPseudoVSLD_VX_VI<Operand ImmType = simm5, string Constraint = ""> { multiclass VPseudoVSLD_VX_VI<Operand ImmType = simm5, string Constraint = ""> {
foreach m = MxList in { foreach m = MxList in {
defvar mx = m.MX; defvar mx = m.MX;
defvar WriteVISlideX_MX = !cast<SchedWrite>("WriteVISlideX_" # mx); defvar WriteVISlideX_MX = !cast<SchedWrite>("WriteVISlideX_" # mx);
defvar WriteVISlideI_MX = !cast<SchedWrite>("WriteVISlideI_" # mx); defvar WriteVISlideI_MX = !cast<SchedWrite>("WriteVISlideI_" # mx);
defvar ReadVISlideV_MX = !cast<SchedRead>("ReadVISlideV_" # mx); defvar ReadVISlideV_MX = !cast<SchedRead>("ReadVISlideV_" # mx);
defvar ReadVISlideX_MX = !cast<SchedRead>("ReadVISlideX_" # mx); defvar ReadVISlideX_MX = !cast<SchedRead>("ReadVISlideX_" # mx);
▲ Show 20 Lines • Show All 1,043 Lines • ▼ Show 20 Lines Pat<(result_type (!cast<Intrinsic>(intrinsic)
(op2_type op2_kind:$rs2), (op2_type op2_kind:$rs2),
VLOpFrag, (XLenVT timm:$policy))), VLOpFrag, (XLenVT timm:$policy))),
(!cast<Instruction>(inst#"_"#kind#"_"#vlmul.MX) (!cast<Instruction>(inst#"_"#kind#"_"#vlmul.MX)
result_reg_class:$rs3, result_reg_class:$rs3,
(op1_type op1_reg_class:$rs1), (op1_type op1_reg_class:$rs1),
op2_kind:$rs2, op2_kind:$rs2,
GPR:$vl, sew, (XLenVT timm:$policy))>; GPR:$vl, sew, (XLenVT timm:$policy))>;
class VPatTernaryNoMaskWithPolicyRoundingMode<string intrinsic,
string inst,
string kind,
ValueType result_type,
ValueType op1_type,
ValueType op2_type,
int sew,
LMULInfo vlmul,
VReg result_reg_class,
RegisterClass op1_reg_class,
DAGOperand op2_kind> :
Pat<(result_type (!cast<Intrinsic>(intrinsic)
(result_type result_reg_class:$rs3),
(op1_type op1_reg_class:$rs1),
(op2_type op2_kind:$rs2),
(XLenVT timm:$round),
VLOpFrag, (XLenVT timm:$policy))),
(!cast<Instruction>(inst#"_"#kind#"_"#vlmul.MX)
result_reg_class:$rs3,
(op1_type op1_reg_class:$rs1),
op2_kind:$rs2,
(XLenVT timm:$round),
GPR:$vl, sew, (XLenVT timm:$policy))>;
class VPatTernaryMask<string intrinsic, class VPatTernaryMask<string intrinsic,
string inst, string inst,
string kind, string kind,
ValueType result_type, ValueType result_type,
ValueType op1_type, ValueType op1_type,
ValueType op2_type, ValueType op2_type,
ValueType mask_type, ValueType mask_type,
int sew, int sew,
Show All 34 Lines Pat<(result_type (!cast<Intrinsic>(intrinsic#"_mask")
VLOpFrag, (XLenVT timm:$policy))), VLOpFrag, (XLenVT timm:$policy))),
(!cast<Instruction>(inst#"_"#kind#"_"#vlmul.MX # "_MASK") (!cast<Instruction>(inst#"_"#kind#"_"#vlmul.MX # "_MASK")
result_reg_class:$rs3, result_reg_class:$rs3,
(op1_type op1_reg_class:$rs1), (op1_type op1_reg_class:$rs1),
op2_kind:$rs2, op2_kind:$rs2,
(mask_type V0), (mask_type V0),
GPR:$vl, sew, (XLenVT timm:$policy))>; GPR:$vl, sew, (XLenVT timm:$policy))>;
class VPatTernaryMaskPolicyRoundingMode<string intrinsic,
string inst,
string kind,
ValueType result_type,
ValueType op1_type,
ValueType op2_type,
ValueType mask_type,
int sew,
LMULInfo vlmul,
VReg result_reg_class,
RegisterClass op1_reg_class,
DAGOperand op2_kind> :
Pat<(result_type (!cast<Intrinsic>(intrinsic#"_mask")
(result_type result_reg_class:$rs3),
(op1_type op1_reg_class:$rs1),
(op2_type op2_kind:$rs2),
(mask_type V0),
(XLenVT timm:$round),
VLOpFrag, (XLenVT timm:$policy))),
(!cast<Instruction>(inst#"_"#kind#"_"#vlmul.MX # "_MASK")
result_reg_class:$rs3,
(op1_type op1_reg_class:$rs1),
op2_kind:$rs2,
(mask_type V0),
(XLenVT timm:$round),
GPR:$vl, sew, (XLenVT timm:$policy))>;
class VPatTernaryMaskTA<string intrinsic, class VPatTernaryMaskTA<string intrinsic,
string inst, string inst,
string kind, string kind,
ValueType result_type, ValueType result_type,
ValueType op1_type, ValueType op1_type,
ValueType op2_type, ValueType op2_type,
ValueType mask_type, ValueType mask_type,
int log2sew, int log2sew,
▲ Show 20 Lines • Show All 910 Lines • ▼ Show 20 Linesmulticlass VPatTernaryWithPolicy<string intrinsic,
def : VPatTernaryNoMaskWithPolicy<intrinsic, inst, kind, result_type, op1_type, def : VPatTernaryNoMaskWithPolicy<intrinsic, inst, kind, result_type, op1_type,
op2_type, sew, vlmul, result_reg_class, op2_type, sew, vlmul, result_reg_class,
op1_reg_class, op2_kind>; op1_reg_class, op2_kind>;
def : VPatTernaryMaskPolicy<intrinsic, inst, kind, result_type, op1_type, op2_type, def : VPatTernaryMaskPolicy<intrinsic, inst, kind, result_type, op1_type, op2_type,
mask_type, sew, vlmul, result_reg_class, op1_reg_class, mask_type, sew, vlmul, result_reg_class, op1_reg_class,
op2_kind>; op2_kind>;
} }
multiclass VPatTernaryWithPolicyRoundingMode<string intrinsic,
string inst,
string kind,
ValueType result_type,
ValueType op1_type,
ValueType op2_type,
ValueType mask_type,
int sew,
LMULInfo vlmul,
VReg result_reg_class,
RegisterClass op1_reg_class,
DAGOperand op2_kind> {
def : VPatTernaryNoMaskWithPolicyRoundingMode<intrinsic, inst, kind, result_type,
op1_type, op2_type, sew, vlmul,
result_reg_class, op1_reg_class,
op2_kind>;
def : VPatTernaryMaskPolicyRoundingMode<intrinsic, inst, kind, result_type, op1_type,
op2_type, mask_type, sew, vlmul,
result_reg_class, op1_reg_class,
op2_kind>;
}
multiclass VPatTernaryTA<string intrinsic, multiclass VPatTernaryTA<string intrinsic,
string inst, string inst,
string kind, string kind,
ValueType result_type, ValueType result_type,
ValueType op1_type, ValueType op1_type,
ValueType op2_type, ValueType op2_type,
ValueType mask_type, ValueType mask_type,
int log2sew, int log2sew,
Show All 14 Linesmulticlass VPatTernaryV_VV_AAXA<string intrinsic, string instruction,
foreach vti = vtilist in foreach vti = vtilist in
let Predicates = GetVTypePredicates<vti>.Predicates in let Predicates = GetVTypePredicates<vti>.Predicates in
defm : VPatTernaryWithPolicy<intrinsic, instruction, "VV", defm : VPatTernaryWithPolicy<intrinsic, instruction, "VV",
vti.Vector, vti.Vector, vti.Vector, vti.Mask, vti.Vector, vti.Vector, vti.Vector, vti.Mask,
vti.Log2SEW, vti.LMul, vti.RegClass, vti.Log2SEW, vti.LMul, vti.RegClass,
vti.RegClass, vti.RegClass>; vti.RegClass, vti.RegClass>;
} }
multiclass VPatTernaryV_VV_AAXA_RM<string intrinsic, string instruction,
list<VTypeInfo> vtilist> {
foreach vti = vtilist in
let Predicates = GetVTypePredicates<vti>.Predicates in
defm : VPatTernaryWithPolicyRoundingMode<intrinsic, instruction, "VV",
vti.Vector, vti.Vector, vti.Vector, vti.Mask,
vti.Log2SEW, vti.LMul, vti.RegClass,
vti.RegClass, vti.RegClass>;
}
multiclass VPatTernaryV_VX<string intrinsic, string instruction, multiclass VPatTernaryV_VX<string intrinsic, string instruction,
list<VTypeInfo> vtilist> { list<VTypeInfo> vtilist> {
foreach vti = vtilist in foreach vti = vtilist in
let Predicates = GetVTypePredicates<vti>.Predicates in let Predicates = GetVTypePredicates<vti>.Predicates in
defm : VPatTernaryWithPolicy<intrinsic, instruction, "VX", defm : VPatTernaryWithPolicy<intrinsic, instruction, "VX",
vti.Vector, vti.Vector, XLenVT, vti.Mask, vti.Vector, vti.Vector, XLenVT, vti.Mask,
vti.Log2SEW, vti.LMul, vti.RegClass, vti.Log2SEW, vti.LMul, vti.RegClass,
vti.RegClass, GPR>; vti.RegClass, GPR>;
} }
multiclass VPatTernaryV_VX_AAXA<string intrinsic, string instruction, multiclass VPatTernaryV_VX_AAXA<string intrinsic, string instruction,
list<VTypeInfo> vtilist> { list<VTypeInfo> vtilist> {
foreach vti = vtilist in foreach vti = vtilist in
let Predicates = GetVTypePredicates<vti>.Predicates in let Predicates = GetVTypePredicates<vti>.Predicates in
defm : VPatTernaryWithPolicy<intrinsic, instruction, defm : VPatTernaryWithPolicy<intrinsic, instruction,
"V"#vti.ScalarSuffix, "V"#vti.ScalarSuffix,
vti.Vector, vti.Scalar, vti.Vector, vti.Mask, vti.Vector, vti.Scalar, vti.Vector, vti.Mask,
vti.Log2SEW, vti.LMul, vti.RegClass, vti.Log2SEW, vti.LMul, vti.RegClass,
vti.ScalarRegClass, vti.RegClass>; vti.ScalarRegClass, vti.RegClass>;
} }
multiclass VPatTernaryV_VX_AAXA_RM<string intrinsic, string instruction,
list<VTypeInfo> vtilist> {
foreach vti = vtilist in
let Predicates = GetVTypePredicates<vti>.Predicates in
defm : VPatTernaryWithPolicyRoundingMode<intrinsic, instruction,
"V"#vti.ScalarSuffix,
vti.Vector, vti.Scalar, vti.Vector, vti.Mask,
vti.Log2SEW, vti.LMul, vti.RegClass,
vti.ScalarRegClass, vti.RegClass>;
}
multiclass VPatTernaryV_VI<string intrinsic, string instruction, multiclass VPatTernaryV_VI<string intrinsic, string instruction,
list<VTypeInfo> vtilist, Operand Imm_type> { list<VTypeInfo> vtilist, Operand Imm_type> {
foreach vti = vtilist in foreach vti = vtilist in
let Predicates = GetVTypePredicates<vti>.Predicates in let Predicates = GetVTypePredicates<vti>.Predicates in
defm : VPatTernaryWithPolicy<intrinsic, instruction, "VI", defm : VPatTernaryWithPolicy<intrinsic, instruction, "VI",
vti.Vector, vti.Vector, XLenVT, vti.Mask, vti.Vector, vti.Vector, XLenVT, vti.Mask,
vti.Log2SEW, vti.LMul, vti.RegClass, vti.Log2SEW, vti.LMul, vti.RegClass,
vti.RegClass, Imm_type>; vti.RegClass, Imm_type>;
Show All 28 Linesmulticlass VPatTernaryW_VX<string intrinsic, string instruction,
} }
} }
multiclass VPatTernaryV_VV_VX_AAXA<string intrinsic, string instruction, multiclass VPatTernaryV_VV_VX_AAXA<string intrinsic, string instruction,
list<VTypeInfo> vtilist> list<VTypeInfo> vtilist>
: VPatTernaryV_VV_AAXA<intrinsic, instruction, vtilist>, : VPatTernaryV_VV_AAXA<intrinsic, instruction, vtilist>,
VPatTernaryV_VX_AAXA<intrinsic, instruction, vtilist>; VPatTernaryV_VX_AAXA<intrinsic, instruction, vtilist>;
multiclass VPatTernaryV_VV_VX_AAXA_RM<string intrinsic, string instruction,
list<VTypeInfo> vtilist>
: VPatTernaryV_VV_AAXA_RM<intrinsic, instruction, vtilist>,
VPatTernaryV_VX_AAXA_RM<intrinsic, instruction, vtilist>;
multiclass VPatTernaryV_VX_VI<string intrinsic, string instruction, multiclass VPatTernaryV_VX_VI<string intrinsic, string instruction,
list<VTypeInfo> vtilist, Operand Imm_type = simm5> list<VTypeInfo> vtilist, Operand Imm_type = simm5>
: VPatTernaryV_VX<intrinsic, instruction, vtilist>, : VPatTernaryV_VX<intrinsic, instruction, vtilist>,
VPatTernaryV_VI<intrinsic, instruction, vtilist, Imm_type>; VPatTernaryV_VI<intrinsic, instruction, vtilist, Imm_type>;
multiclass VPatBinaryM_VV_VX_VI<string intrinsic, string instruction, multiclass VPatBinaryM_VV_VX_VI<string intrinsic, string instruction,
list<VTypeInfo> vtilist> list<VTypeInfo> vtilist>
▲ Show 20 Lines • Show All 578 Lines • ▼ Show 20 Lines
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
let mayRaiseFPException = true, hasSideEffects = 0 in { let mayRaiseFPException = true, hasSideEffects = 0 in {
defm PseudoVFWMUL : VPseudoVWMUL_VV_VF_RM; defm PseudoVFWMUL : VPseudoVWMUL_VV_VF_RM;
} }
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// 13.6. Vector Single-Width Floating-Point Fused Multiply-Add Instructions // 13.6. Vector Single-Width Floating-Point Fused Multiply-Add Instructions
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
let Uses = [FRM], mayRaiseFPException = true in { let mayRaiseFPException = true, hasSideEffects = 0,
defm PseudoVFMACC : VPseudoVMAC_VV_VF_AAXA; hasPostISelHook = 1 in {
defm PseudoVFNMACC : VPseudoVMAC_VV_VF_AAXA; defm PseudoVFMACC : VPseudoVMAC_VV_VF_AAXA_RM;
defm PseudoVFMSAC : VPseudoVMAC_VV_VF_AAXA; defm PseudoVFNMACC : VPseudoVMAC_VV_VF_AAXA_RM;
defm PseudoVFNMSAC : VPseudoVMAC_VV_VF_AAXA; defm PseudoVFMSAC : VPseudoVMAC_VV_VF_AAXA_RM;
defm PseudoVFMADD : VPseudoVMAC_VV_VF_AAXA; defm PseudoVFNMSAC : VPseudoVMAC_VV_VF_AAXA_RM;
defm PseudoVFNMADD : VPseudoVMAC_VV_VF_AAXA; defm PseudoVFMADD : VPseudoVMAC_VV_VF_AAXA_RM;
defm PseudoVFMSUB : VPseudoVMAC_VV_VF_AAXA; defm PseudoVFNMADD : VPseudoVMAC_VV_VF_AAXA_RM;
defm PseudoVFNMSUB : VPseudoVMAC_VV_VF_AAXA; defm PseudoVFMSUB : VPseudoVMAC_VV_VF_AAXA_RM;
defm PseudoVFNMSUB : VPseudoVMAC_VV_VF_AAXA_RM;
} }
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// 13.7. Vector Widening Floating-Point Fused Multiply-Add Instructions // 13.7. Vector Widening Floating-Point Fused Multiply-Add Instructions
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
let Uses = [FRM], mayRaiseFPException = true in { let Uses = [FRM], mayRaiseFPException = true in {
defm PseudoVFWMACC : VPseudoVWMAC_VV_VF; defm PseudoVFWMACC : VPseudoVWMAC_VV_VF;
defm PseudoVFWNMACC : VPseudoVWMAC_VV_VF; defm PseudoVFWNMACC : VPseudoVWMAC_VV_VF;
▲ Show 20 Lines • Show All 637 Lines • ▼ Show 20 Lines
// 13.5. Vector Widening Floating-Point Multiply // 13.5. Vector Widening Floating-Point Multiply
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
defm : VPatBinaryW_VV_VX_RM<"int_riscv_vfwmul", "PseudoVFWMUL", defm : VPatBinaryW_VV_VX_RM<"int_riscv_vfwmul", "PseudoVFWMUL",
AllWidenableFloatVectors>; AllWidenableFloatVectors>;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// 13.6. Vector Single-Width Floating-Point Fused Multiply-Add Instructions // 13.6. Vector Single-Width Floating-Point Fused Multiply-Add Instructions
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
defm : VPatTernaryV_VV_VX_AAXA<"int_riscv_vfmacc", "PseudoVFMACC", AllFloatVectors>; defm : VPatTernaryV_VV_VX_AAXA_RM<"int_riscv_vfmacc", "PseudoVFMACC", AllFloatVectors>;
defm : VPatTernaryV_VV_VX_AAXA<"int_riscv_vfnmacc", "PseudoVFNMACC", AllFloatVectors>; defm : VPatTernaryV_VV_VX_AAXA_RM<"int_riscv_vfnmacc", "PseudoVFNMACC", AllFloatVectors>;
defm : VPatTernaryV_VV_VX_AAXA<"int_riscv_vfmsac", "PseudoVFMSAC", AllFloatVectors>; defm : VPatTernaryV_VV_VX_AAXA_RM<"int_riscv_vfmsac", "PseudoVFMSAC", AllFloatVectors>;
defm : VPatTernaryV_VV_VX_AAXA<"int_riscv_vfnmsac", "PseudoVFNMSAC", AllFloatVectors>; defm : VPatTernaryV_VV_VX_AAXA_RM<"int_riscv_vfnmsac", "PseudoVFNMSAC", AllFloatVectors>;
defm : VPatTernaryV_VV_VX_AAXA<"int_riscv_vfmadd", "PseudoVFMADD", AllFloatVectors>; defm : VPatTernaryV_VV_VX_AAXA_RM<"int_riscv_vfmadd", "PseudoVFMADD", AllFloatVectors>;
defm : VPatTernaryV_VV_VX_AAXA<"int_riscv_vfnmadd", "PseudoVFNMADD", AllFloatVectors>; defm : VPatTernaryV_VV_VX_AAXA_RM<"int_riscv_vfnmadd", "PseudoVFNMADD", AllFloatVectors>;
defm : VPatTernaryV_VV_VX_AAXA<"int_riscv_vfmsub", "PseudoVFMSUB", AllFloatVectors>; defm : VPatTernaryV_VV_VX_AAXA_RM<"int_riscv_vfmsub", "PseudoVFMSUB", AllFloatVectors>;
defm : VPatTernaryV_VV_VX_AAXA<"int_riscv_vfnmsub", "PseudoVFNMSUB", AllFloatVectors>; defm : VPatTernaryV_VV_VX_AAXA_RM<"int_riscv_vfnmsub", "PseudoVFNMSUB", AllFloatVectors>;
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// 13.7. Vector Widening Floating-Point Fused Multiply-Add Instructions // 13.7. Vector Widening Floating-Point Fused Multiply-Add Instructions
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
defm : VPatTernaryW_VV_VX<"int_riscv_vfwmacc", "PseudoVFWMACC", AllWidenableFloatVectors>; defm : VPatTernaryW_VV_VX<"int_riscv_vfwmacc", "PseudoVFWMACC", AllWidenableFloatVectors>;
defm : VPatTernaryW_VV_VX<"int_riscv_vfwnmacc", "PseudoVFWNMACC", AllWidenableFloatVectors>; defm : VPatTernaryW_VV_VX<"int_riscv_vfwnmacc", "PseudoVFWNMACC", AllWidenableFloatVectors>;
defm : VPatTernaryW_VV_VX<"int_riscv_vfwmsac", "PseudoVFWMSAC", AllWidenableFloatVectors>; defm : VPatTernaryW_VV_VX<"int_riscv_vfwmsac", "PseudoVFWMSAC", AllWidenableFloatVectors>;
defm : VPatTernaryW_VV_VX<"int_riscv_vfwnmsac", "PseudoVFWNMSAC", AllWidenableFloatVectors>; defm : VPatTernaryW_VV_VX<"int_riscv_vfwnmsac", "PseudoVFWNMSAC", AllWidenableFloatVectors>;
▲ Show 20 Lines • Show All 283 Lines • Show Last 20 Lines

llvm/lib/Target/RISCV/RISCVInstrInfoVSDPatterns.td

Show First 20 Lines • Show All 1,133 Lines • ▼ Show 20 Linesforeach fvti = AllFloatVectors in {
// NOTE: We choose VFMADD because it has the most commuting freedom. So it // NOTE: We choose VFMADD because it has the most commuting freedom. So it
// works best with how TwoAddressInstructionPass tries commuting. // works best with how TwoAddressInstructionPass tries commuting.
defvar suffix = fvti.LMul.MX; defvar suffix = fvti.LMul.MX;
let Predicates = GetVTypePredicates<fvti>.Predicates in { let Predicates = GetVTypePredicates<fvti>.Predicates in {
def : Pat<(fvti.Vector (any_fma fvti.RegClass:$rs1, fvti.RegClass:$rd, def : Pat<(fvti.Vector (any_fma fvti.RegClass:$rs1, fvti.RegClass:$rd,
fvti.RegClass:$rs2)), fvti.RegClass:$rs2)),
(!cast<Instruction>("PseudoVFMADD_VV_"# suffix) (!cast<Instruction>("PseudoVFMADD_VV_"# suffix)
fvti.RegClass:$rd, fvti.RegClass:$rs1, fvti.RegClass:$rs2, fvti.RegClass:$rd, fvti.RegClass:$rs1, fvti.RegClass:$rs2,
// Value to indicate no rounding mode change in
// RISCVInsertReadWriteCSR
FRM_DYN,
fvti.AVL, fvti.Log2SEW, TAIL_AGNOSTIC)>; fvti.AVL, fvti.Log2SEW, TAIL_AGNOSTIC)>;
def : Pat<(fvti.Vector (any_fma fvti.RegClass:$rs1, fvti.RegClass:$rd, def : Pat<(fvti.Vector (any_fma fvti.RegClass:$rs1, fvti.RegClass:$rd,
(fneg fvti.RegClass:$rs2))), (fneg fvti.RegClass:$rs2))),
(!cast<Instruction>("PseudoVFMSUB_VV_"# suffix) (!cast<Instruction>("PseudoVFMSUB_VV_"# suffix)
fvti.RegClass:$rd, fvti.RegClass:$rs1, fvti.RegClass:$rs2, fvti.RegClass:$rd, fvti.RegClass:$rs1, fvti.RegClass:$rs2,
// Value to indicate no rounding mode change in
// RISCVInsertReadWriteCSR
FRM_DYN,
fvti.AVL, fvti.Log2SEW, TAIL_AGNOSTIC)>; fvti.AVL, fvti.Log2SEW, TAIL_AGNOSTIC)>;
def : Pat<(fvti.Vector (any_fma (fneg fvti.RegClass:$rs1), fvti.RegClass:$rd, def : Pat<(fvti.Vector (any_fma (fneg fvti.RegClass:$rs1), fvti.RegClass:$rd,
(fneg fvti.RegClass:$rs2))), (fneg fvti.RegClass:$rs2))),
(!cast<Instruction>("PseudoVFNMADD_VV_"# suffix) (!cast<Instruction>("PseudoVFNMADD_VV_"# suffix)
fvti.RegClass:$rd, fvti.RegClass:$rs1, fvti.RegClass:$rs2, fvti.RegClass:$rd, fvti.RegClass:$rs1, fvti.RegClass:$rs2,
// Value to indicate no rounding mode change in
// RISCVInsertReadWriteCSR
FRM_DYN,
fvti.AVL, fvti.Log2SEW, TAIL_AGNOSTIC)>; fvti.AVL, fvti.Log2SEW, TAIL_AGNOSTIC)>;
def : Pat<(fvti.Vector (any_fma (fneg fvti.RegClass:$rs1), fvti.RegClass:$rd, def : Pat<(fvti.Vector (any_fma (fneg fvti.RegClass:$rs1), fvti.RegClass:$rd,
fvti.RegClass:$rs2)), fvti.RegClass:$rs2)),
(!cast<Instruction>("PseudoVFNMSUB_VV_"# suffix) (!cast<Instruction>("PseudoVFNMSUB_VV_"# suffix)
fvti.RegClass:$rd, fvti.RegClass:$rs1, fvti.RegClass:$rs2, fvti.RegClass:$rd, fvti.RegClass:$rs1, fvti.RegClass:$rs2,
// Value to indicate no rounding mode change in
// RISCVInsertReadWriteCSR
FRM_DYN,
fvti.AVL, fvti.Log2SEW, TAIL_AGNOSTIC)>; fvti.AVL, fvti.Log2SEW, TAIL_AGNOSTIC)>;
// The choice of VFMADD here is arbitrary, vfmadd.vf and vfmacc.vf are equally // The choice of VFMADD here is arbitrary, vfmadd.vf and vfmacc.vf are equally
// commutable. // commutable.
def : Pat<(fvti.Vector (any_fma (SplatFPOp fvti.ScalarRegClass:$rs1), def : Pat<(fvti.Vector (any_fma (SplatFPOp fvti.ScalarRegClass:$rs1),
fvti.RegClass:$rd, fvti.RegClass:$rs2)), fvti.RegClass:$rd, fvti.RegClass:$rs2)),
(!cast<Instruction>("PseudoVFMADD_V" # fvti.ScalarSuffix # "_" # suffix) (!cast<Instruction>("PseudoVFMADD_V" # fvti.ScalarSuffix # "_" # suffix)
fvti.RegClass:$rd, fvti.ScalarRegClass:$rs1, fvti.RegClass:$rs2, fvti.RegClass:$rd, fvti.ScalarRegClass:$rs1, fvti.RegClass:$rs2,
// Value to indicate no rounding mode change in
// RISCVInsertReadWriteCSR
FRM_DYN,
fvti.AVL, fvti.Log2SEW, TAIL_AGNOSTIC)>; fvti.AVL, fvti.Log2SEW, TAIL_AGNOSTIC)>;
def : Pat<(fvti.Vector (any_fma (SplatFPOp fvti.ScalarRegClass:$rs1), def : Pat<(fvti.Vector (any_fma (SplatFPOp fvti.ScalarRegClass:$rs1),
fvti.RegClass:$rd, (fneg fvti.RegClass:$rs2))), fvti.RegClass:$rd, (fneg fvti.RegClass:$rs2))),
(!cast<Instruction>("PseudoVFMSUB_V" # fvti.ScalarSuffix # "_" # suffix) (!cast<Instruction>("PseudoVFMSUB_V" # fvti.ScalarSuffix # "_" # suffix)
fvti.RegClass:$rd, fvti.ScalarRegClass:$rs1, fvti.RegClass:$rs2, fvti.RegClass:$rd, fvti.ScalarRegClass:$rs1, fvti.RegClass:$rs2,
// Value to indicate no rounding mode change in
// RISCVInsertReadWriteCSR
FRM_DYN,
fvti.AVL, fvti.Log2SEW, TAIL_AGNOSTIC)>; fvti.AVL, fvti.Log2SEW, TAIL_AGNOSTIC)>;
def : Pat<(fvti.Vector (any_fma (SplatFPOp fvti.ScalarRegClass:$rs1), def : Pat<(fvti.Vector (any_fma (SplatFPOp fvti.ScalarRegClass:$rs1),
(fneg fvti.RegClass:$rd), (fneg fvti.RegClass:$rs2))), (fneg fvti.RegClass:$rd), (fneg fvti.RegClass:$rs2))),
(!cast<Instruction>("PseudoVFNMADD_V" # fvti.ScalarSuffix # "_" # suffix) (!cast<Instruction>("PseudoVFNMADD_V" # fvti.ScalarSuffix # "_" # suffix)
fvti.RegClass:$rd, fvti.ScalarRegClass:$rs1, fvti.RegClass:$rs2, fvti.RegClass:$rd, fvti.ScalarRegClass:$rs1, fvti.RegClass:$rs2,
// Value to indicate no rounding mode change in
// RISCVInsertReadWriteCSR
FRM_DYN,
fvti.AVL, fvti.Log2SEW, TAIL_AGNOSTIC)>; fvti.AVL, fvti.Log2SEW, TAIL_AGNOSTIC)>;
def : Pat<(fvti.Vector (any_fma (SplatFPOp fvti.ScalarRegClass:$rs1), def : Pat<(fvti.Vector (any_fma (SplatFPOp fvti.ScalarRegClass:$rs1),
(fneg fvti.RegClass:$rd), fvti.RegClass:$rs2)), (fneg fvti.RegClass:$rd), fvti.RegClass:$rs2)),
(!cast<Instruction>("PseudoVFNMSUB_V" # fvti.ScalarSuffix # "_" # suffix) (!cast<Instruction>("PseudoVFNMSUB_V" # fvti.ScalarSuffix # "_" # suffix)
fvti.RegClass:$rd, fvti.ScalarRegClass:$rs1, fvti.RegClass:$rs2, fvti.RegClass:$rd, fvti.ScalarRegClass:$rs1, fvti.RegClass:$rs2,
// Value to indicate no rounding mode change in
// RISCVInsertReadWriteCSR
FRM_DYN,
fvti.AVL, fvti.Log2SEW, TAIL_AGNOSTIC)>; fvti.AVL, fvti.Log2SEW, TAIL_AGNOSTIC)>;
// The splat might be negated. // The splat might be negated.
def : Pat<(fvti.Vector (any_fma (fneg (SplatFPOp fvti.ScalarRegClass:$rs1)), def : Pat<(fvti.Vector (any_fma (fneg (SplatFPOp fvti.ScalarRegClass:$rs1)),
fvti.RegClass:$rd, (fneg fvti.RegClass:$rs2))), fvti.RegClass:$rd, (fneg fvti.RegClass:$rs2))),
(!cast<Instruction>("PseudoVFNMADD_V" # fvti.ScalarSuffix # "_" # suffix) (!cast<Instruction>("PseudoVFNMADD_V" # fvti.ScalarSuffix # "_" # suffix)
fvti.RegClass:$rd, fvti.ScalarRegClass:$rs1, fvti.RegClass:$rs2, fvti.RegClass:$rd, fvti.ScalarRegClass:$rs1, fvti.RegClass:$rs2,
// Value to indicate no rounding mode change in
// RISCVInsertReadWriteCSR
FRM_DYN,
fvti.AVL, fvti.Log2SEW, TAIL_AGNOSTIC)>; fvti.AVL, fvti.Log2SEW, TAIL_AGNOSTIC)>;
def : Pat<(fvti.Vector (any_fma (fneg (SplatFPOp fvti.ScalarRegClass:$rs1)), def : Pat<(fvti.Vector (any_fma (fneg (SplatFPOp fvti.ScalarRegClass:$rs1)),
fvti.RegClass:$rd, fvti.RegClass:$rs2)), fvti.RegClass:$rd, fvti.RegClass:$rs2)),
(!cast<Instruction>("PseudoVFNMSUB_V" # fvti.ScalarSuffix # "_" # suffix) (!cast<Instruction>("PseudoVFNMSUB_V" # fvti.ScalarSuffix # "_" # suffix)
fvti.RegClass:$rd, fvti.ScalarRegClass:$rs1, fvti.RegClass:$rs2, fvti.RegClass:$rd, fvti.ScalarRegClass:$rs1, fvti.RegClass:$rs2,
// Value to indicate no rounding mode change in
// RISCVInsertReadWriteCSR
FRM_DYN,
fvti.AVL, fvti.Log2SEW, TAIL_AGNOSTIC)>; fvti.AVL, fvti.Log2SEW, TAIL_AGNOSTIC)>;
} }
} }
// 13.7. Vector Widening Floating-Point Fused Multiply-Add Instructions // 13.7. Vector Widening Floating-Point Fused Multiply-Add Instructions
defm : VPatWidenFPMulAccSDNode_VV_VF<"PseudoVFWMACC">; defm : VPatWidenFPMulAccSDNode_VV_VF<"PseudoVFWMACC">;
defm : VPatWidenFPNegMulAccSDNode_VV_VF<"PseudoVFWNMACC">; defm : VPatWidenFPNegMulAccSDNode_VV_VF<"PseudoVFWNMACC">;
defm : VPatWidenFPMulSacSDNode_VV_VF<"PseudoVFWMSAC">; defm : VPatWidenFPMulSacSDNode_VV_VF<"PseudoVFWMSAC">;
▲ Show 20 Lines • Show All 153 Lines • Show Last 20 Lines

llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td

Show First 20 Lines • Show All 1,653 Lines • ▼ Show 20 Lines def : Pat<(vti.Vector (vop (SplatFPOp vti.ScalarRegClass:$rs1),
VLOpFrag)), VLOpFrag)),
(!cast<Instruction>(instruction_name#"_V" # vti.ScalarSuffix # "_" # suffix # "_MASK") (!cast<Instruction>(instruction_name#"_V" # vti.ScalarSuffix # "_" # suffix # "_MASK")
vti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2, vti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2,
(vti.Mask V0), GPR:$vl, vti.Log2SEW, TA_MA)>; (vti.Mask V0), GPR:$vl, vti.Log2SEW, TA_MA)>;
} }
} }
} }
multiclass VPatFPMulAddVL_VV_VF_RM<SDPatternOperator vop, string instruction_name> {
foreach vti = AllFloatVectors in {
defvar suffix = vti.LMul.MX;
let Predicates = GetVTypePredicates<vti>.Predicates in {
def : Pat<(vti.Vector (vop vti.RegClass:$rs1, vti.RegClass:$rd,
vti.RegClass:$rs2, (vti.Mask V0),
VLOpFrag)),
(!cast<Instruction>(instruction_name#"_VV_"# suffix #"_MASK")
vti.RegClass:$rd, vti.RegClass:$rs1, vti.RegClass:$rs2,
(vti.Mask V0),
// Value to indicate no rounding mode change in
// RISCVInsertReadWriteCSR
FRM_DYN,
GPR:$vl, vti.Log2SEW, TA_MA)>;
def : Pat<(vti.Vector (vop (SplatFPOp vti.ScalarRegClass:$rs1),
vti.RegClass:$rd, vti.RegClass:$rs2,
(vti.Mask V0),
VLOpFrag)),
(!cast<Instruction>(instruction_name#"_V" # vti.ScalarSuffix # "_" # suffix # "_MASK")
vti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2,
(vti.Mask V0),
// Value to indicate no rounding mode change in
// RISCVInsertReadWriteCSR
FRM_DYN,
GPR:$vl, vti.Log2SEW, TA_MA)>;
}
}
}
multiclass VPatFPMulAccVL_VV_VF<PatFrag vop, string instruction_name> { multiclass VPatFPMulAccVL_VV_VF<PatFrag vop, string instruction_name> {
foreach vti = AllFloatVectors in { foreach vti = AllFloatVectors in {
defvar suffix = vti.LMul.MX; defvar suffix = vti.LMul.MX;
let Predicates = GetVTypePredicates<vti>.Predicates in { let Predicates = GetVTypePredicates<vti>.Predicates in {
def : Pat<(riscv_vp_merge_vl (vti.Mask V0), def : Pat<(riscv_vp_merge_vl (vti.Mask V0),
(vti.Vector (vop vti.RegClass:$rs1, vti.RegClass:$rs2, (vti.Vector (vop vti.RegClass:$rs1, vti.RegClass:$rs2,
vti.RegClass:$rd, (vti.Mask true_mask), VLOpFrag)), vti.RegClass:$rd, (vti.Mask true_mask), VLOpFrag)),
vti.RegClass:$rd, VLOpFrag), vti.RegClass:$rd, VLOpFrag),
Show All 20 Lines def : Pat<(riscv_vselect_vl (vti.Mask V0),
vti.RegClass:$rd, VLOpFrag), vti.RegClass:$rd, VLOpFrag),
(!cast<Instruction>(instruction_name#"_V" # vti.ScalarSuffix # "_" # suffix # "_MASK") (!cast<Instruction>(instruction_name#"_V" # vti.ScalarSuffix # "_" # suffix # "_MASK")
vti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2, vti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2,
(vti.Mask V0), GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>; (vti.Mask V0), GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>;
} }
} }
} }
multiclass VPatFPMulAccVL_VV_VF_RM<PatFrag vop, string instruction_name> {
foreach vti = AllFloatVectors in {
defvar suffix = vti.LMul.MX;
let Predicates = GetVTypePredicates<vti>.Predicates in {
def : Pat<(riscv_vp_merge_vl (vti.Mask V0),
(vti.Vector (vop vti.RegClass:$rs1, vti.RegClass:$rs2,
vti.RegClass:$rd, (vti.Mask true_mask), VLOpFrag)),
vti.RegClass:$rd, VLOpFrag),
(!cast<Instruction>(instruction_name#"_VV_"# suffix #"_MASK")
vti.RegClass:$rd, vti.RegClass:$rs1, vti.RegClass:$rs2,
(vti.Mask V0),
// Value to indicate no rounding mode change in
// RISCVInsertReadWriteCSR
FRM_DYN,
GPR:$vl, vti.Log2SEW, TU_MU)>;
def : Pat<(riscv_vp_merge_vl (vti.Mask V0),
(vti.Vector (vop (SplatFPOp vti.ScalarRegClass:$rs1), vti.RegClass:$rs2,
vti.RegClass:$rd, (vti.Mask true_mask), VLOpFrag)),
vti.RegClass:$rd, VLOpFrag),
(!cast<Instruction>(instruction_name#"_V" # vti.ScalarSuffix # "_" # suffix # "_MASK")
vti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2,
(vti.Mask V0),
// Value to indicate no rounding mode change in
// RISCVInsertReadWriteCSR
FRM_DYN,
GPR:$vl, vti.Log2SEW, TU_MU)>;
def : Pat<(riscv_vselect_vl (vti.Mask V0),
(vti.Vector (vop vti.RegClass:$rs1, vti.RegClass:$rs2,
vti.RegClass:$rd, (vti.Mask true_mask), VLOpFrag)),
vti.RegClass:$rd, VLOpFrag),
(!cast<Instruction>(instruction_name#"_VV_"# suffix #"_MASK")
vti.RegClass:$rd, vti.RegClass:$rs1, vti.RegClass:$rs2,
(vti.Mask V0),
// Value to indicate no rounding mode change in
// RISCVInsertReadWriteCSR
FRM_DYN,
GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>;
def : Pat<(riscv_vselect_vl (vti.Mask V0),
(vti.Vector (vop (SplatFPOp vti.ScalarRegClass:$rs1), vti.RegClass:$rs2,
vti.RegClass:$rd, (vti.Mask true_mask), VLOpFrag)),
vti.RegClass:$rd, VLOpFrag),
(!cast<Instruction>(instruction_name#"_V" # vti.ScalarSuffix # "_" # suffix # "_MASK")
vti.RegClass:$rd, vti.ScalarRegClass:$rs1, vti.RegClass:$rs2,
(vti.Mask V0),
// Value to indicate no rounding mode change in
// RISCVInsertReadWriteCSR
FRM_DYN,
GPR:$vl, vti.Log2SEW, TAIL_AGNOSTIC)>;
}
}
}
multiclass VPatWidenFPMulAccVL_VV_VF<SDNode vop, string instruction_name> { multiclass VPatWidenFPMulAccVL_VV_VF<SDNode vop, string instruction_name> {
foreach vtiToWti = AllWidenableFloatVectors in { foreach vtiToWti = AllWidenableFloatVectors in {
defvar vti = vtiToWti.Vti; defvar vti = vtiToWti.Vti;
defvar wti = vtiToWti.Wti; defvar wti = vtiToWti.Wti;
let Predicates = !listconcat(GetVTypePredicates<vti>.Predicates, let Predicates = !listconcat(GetVTypePredicates<vti>.Predicates,
GetVTypePredicates<wti>.Predicates) in { GetVTypePredicates<wti>.Predicates) in {
def : Pat<(vop (vti.Vector vti.RegClass:$rs1), def : Pat<(vop (vti.Vector vti.RegClass:$rs1),
(vti.Vector vti.RegClass:$rs2), (vti.Vector vti.RegClass:$rs2),
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defm : VPatBinaryFPVL_VV_VF_RM<any_riscv_fmul_vl, "PseudoVFMUL">; defm : VPatBinaryFPVL_VV_VF_RM<any_riscv_fmul_vl, "PseudoVFMUL">;
defm : VPatBinaryFPVL_VV_VF_RM<any_riscv_fdiv_vl, "PseudoVFDIV", /*isSEWAware*/ 1>; defm : VPatBinaryFPVL_VV_VF_RM<any_riscv_fdiv_vl, "PseudoVFDIV", /*isSEWAware*/ 1>;
defm : VPatBinaryFPVL_R_VF_RM<any_riscv_fdiv_vl, "PseudoVFRDIV", /*isSEWAware*/ 1>; defm : VPatBinaryFPVL_R_VF_RM<any_riscv_fdiv_vl, "PseudoVFRDIV", /*isSEWAware*/ 1>;
// 13.5. Vector Widening Floating-Point Multiply Instructions // 13.5. Vector Widening Floating-Point Multiply Instructions
defm : VPatBinaryFPWVL_VV_VF_RM<riscv_vfwmul_vl, "PseudoVFWMUL">; defm : VPatBinaryFPWVL_VV_VF_RM<riscv_vfwmul_vl, "PseudoVFWMUL">;
// 13.6 Vector Single-Width Floating-Point Fused Multiply-Add Instructions. // 13.6 Vector Single-Width Floating-Point Fused Multiply-Add Instructions.
defm : VPatFPMulAddVL_VV_VF<any_riscv_vfmadd_vl, "PseudoVFMADD">; defm : VPatFPMulAddVL_VV_VF_RM<any_riscv_vfmadd_vl, "PseudoVFMADD">;
defm : VPatFPMulAddVL_VV_VF<any_riscv_vfmsub_vl, "PseudoVFMSUB">; defm : VPatFPMulAddVL_VV_VF_RM<any_riscv_vfmsub_vl, "PseudoVFMSUB">;
defm : VPatFPMulAddVL_VV_VF<any_riscv_vfnmadd_vl, "PseudoVFNMADD">; defm : VPatFPMulAddVL_VV_VF_RM<any_riscv_vfnmadd_vl, "PseudoVFNMADD">;
defm : VPatFPMulAddVL_VV_VF<any_riscv_vfnmsub_vl, "PseudoVFNMSUB">; defm : VPatFPMulAddVL_VV_VF_RM<any_riscv_vfnmsub_vl, "PseudoVFNMSUB">;
defm : VPatFPMulAccVL_VV_VF<riscv_vfmadd_vl_oneuse, "PseudoVFMACC">; defm : VPatFPMulAccVL_VV_VF_RM<riscv_vfmadd_vl_oneuse, "PseudoVFMACC">;
defm : VPatFPMulAccVL_VV_VF<riscv_vfmsub_vl_oneuse, "PseudoVFMSAC">; defm : VPatFPMulAccVL_VV_VF_RM<riscv_vfmsub_vl_oneuse, "PseudoVFMSAC">;
defm : VPatFPMulAccVL_VV_VF<riscv_vfnmadd_vl_oneuse, "PseudoVFNMACC">; defm : VPatFPMulAccVL_VV_VF_RM<riscv_vfnmadd_vl_oneuse, "PseudoVFNMACC">;
defm : VPatFPMulAccVL_VV_VF<riscv_vfnmsub_vl_oneuse, "PseudoVFNMSAC">; defm : VPatFPMulAccVL_VV_VF_RM<riscv_vfnmsub_vl_oneuse, "PseudoVFNMSAC">;
// 13.7. Vector Widening Floating-Point Fused Multiply-Add Instructions // 13.7. Vector Widening Floating-Point Fused Multiply-Add Instructions
defm : VPatWidenFPMulAccVL_VV_VF<riscv_vfwmadd_vl, "PseudoVFWMACC">; defm : VPatWidenFPMulAccVL_VV_VF<riscv_vfwmadd_vl, "PseudoVFWMACC">;
defm : VPatWidenFPMulAccVL_VV_VF<riscv_vfwnmadd_vl, "PseudoVFWNMACC">; defm : VPatWidenFPMulAccVL_VV_VF<riscv_vfwnmadd_vl, "PseudoVFWNMACC">;
defm : VPatWidenFPMulAccVL_VV_VF<riscv_vfwmsub_vl, "PseudoVFWMSAC">; defm : VPatWidenFPMulAccVL_VV_VF<riscv_vfwmsub_vl, "PseudoVFWMSAC">;
defm : VPatWidenFPMulAccVL_VV_VF<riscv_vfwnmsub_vl, "PseudoVFWNMSAC">; defm : VPatWidenFPMulAccVL_VV_VF<riscv_vfwnmsub_vl, "PseudoVFWNMSAC">;
// 13.11. Vector Floating-Point MIN/MAX Instructions // 13.11. Vector Floating-Point MIN/MAX Instructions
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llvm/test/CodeGen/RISCV/rvv/masked-tama.ll

Show First 20 Lines • Show All 757 Lines • ▼ Show 20 Linesentry:
ret <vscale x 1 x float> %a ret <vscale x 1 x float> %a
} }
declare <vscale x 1 x half> @llvm.riscv.vfmacc.mask.nxv1f16.nxv1f16( declare <vscale x 1 x half> @llvm.riscv.vfmacc.mask.nxv1f16.nxv1f16(
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
iXLen, iXLen); iXLen, iXLen, iXLen);
define <vscale x 1 x half> @intrinsic_vfmacc_mask_vv_nxv1f16_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x i1> %2, iXLen %3) nounwind { define <vscale x 1 x half> @intrinsic_vfmacc_mask_vv_nxv1f16_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x i1> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfmacc_mask_vv_nxv1f16_nxv1f16_nxv1f16: ; CHECK-LABEL: intrinsic_vfmacc_mask_vv_nxv1f16_nxv1f16_nxv1f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, ma
; CHECK-NEXT: vfmacc.vv v8, v8, v9, v0.t ; CHECK-NEXT: vfmacc.vv v8, v8, v9, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x half> @llvm.riscv.vfmacc.mask.nxv1f16.nxv1f16( %a = call <vscale x 1 x half> @llvm.riscv.vfmacc.mask.nxv1f16.nxv1f16(
<vscale x 1 x half> undef, <vscale x 1 x half> undef,
<vscale x 1 x half> %0, <vscale x 1 x half> %0,
<vscale x 1 x half> %1, <vscale x 1 x half> %1,
<vscale x 1 x i1> %2, <vscale x 1 x i1> %2,
iXLen %3, iXLen 3) iXLen 7, iXLen %3, iXLen 3)
ret <vscale x 1 x half> %a ret <vscale x 1 x half> %a
} }
declare <vscale x 1 x float> @llvm.riscv.vfwmacc.mask.nxv1f32.nxv1f16( declare <vscale x 1 x float> @llvm.riscv.vfwmacc.mask.nxv1f32.nxv1f16(
<vscale x 1 x float>, <vscale x 1 x float>,
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x half>, <vscale x 1 x half>,
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llvm/test/CodeGen/RISCV/rvv/masked-tamu.ll

Show First 20 Lines • Show All 719 Lines • ▼ Show 20 Linesentry:
ret <vscale x 1 x float> %a ret <vscale x 1 x float> %a
} }
declare <vscale x 1 x half> @llvm.riscv.vfmacc.mask.nxv1f16.nxv1f16( declare <vscale x 1 x half> @llvm.riscv.vfmacc.mask.nxv1f16.nxv1f16(
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
iXLen, iXLen) iXLen, iXLen, iXLen)
define <vscale x 1 x half> @intrinsic_vfmacc_mask_vv_nxv1f16_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind { define <vscale x 1 x half> @intrinsic_vfmacc_mask_vv_nxv1f16_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfmacc_mask_vv_nxv1f16_nxv1f16_nxv1f16: ; CHECK-LABEL: intrinsic_vfmacc_mask_vv_nxv1f16_nxv1f16_nxv1f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, ta, mu
; CHECK-NEXT: vfmacc.vv v8, v9, v10, v0.t ; CHECK-NEXT: vfmacc.vv v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x half> @llvm.riscv.vfmacc.mask.nxv1f16.nxv1f16( %a = call <vscale x 1 x half> @llvm.riscv.vfmacc.mask.nxv1f16.nxv1f16(
<vscale x 1 x half> %0, <vscale x 1 x half> %0,
<vscale x 1 x half> %1, <vscale x 1 x half> %1,
<vscale x 1 x half> %2, <vscale x 1 x half> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
iXLen %4, iXLen 1) iXLen 7, iXLen %4, iXLen 1)
ret <vscale x 1 x half> %a ret <vscale x 1 x half> %a
} }
declare <vscale x 1 x float> @llvm.riscv.vfwmacc.mask.nxv1f32.nxv1f16( declare <vscale x 1 x float> @llvm.riscv.vfwmacc.mask.nxv1f32.nxv1f16(
<vscale x 1 x float>, <vscale x 1 x float>,
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x half>, <vscale x 1 x half>,
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llvm/test/CodeGen/RISCV/rvv/masked-tuma.ll

Show First 20 Lines • Show All 719 Lines • ▼ Show 20 Linesentry:
ret <vscale x 1 x float> %a ret <vscale x 1 x float> %a
} }
declare <vscale x 1 x half> @llvm.riscv.vfmacc.mask.nxv1f16.nxv1f16( declare <vscale x 1 x half> @llvm.riscv.vfmacc.mask.nxv1f16.nxv1f16(
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
iXLen, iXLen) iXLen, iXLen, iXLen)
define <vscale x 1 x half> @intrinsic_vfmacc_mask_vv_nxv1f16_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind { define <vscale x 1 x half> @intrinsic_vfmacc_mask_vv_nxv1f16_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfmacc_mask_vv_nxv1f16_nxv1f16_nxv1f16: ; CHECK-LABEL: intrinsic_vfmacc_mask_vv_nxv1f16_nxv1f16_nxv1f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, ma ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, ma
; CHECK-NEXT: vfmacc.vv v8, v9, v10, v0.t ; CHECK-NEXT: vfmacc.vv v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x half> @llvm.riscv.vfmacc.mask.nxv1f16.nxv1f16( %a = call <vscale x 1 x half> @llvm.riscv.vfmacc.mask.nxv1f16.nxv1f16(
<vscale x 1 x half> %0, <vscale x 1 x half> %0,
<vscale x 1 x half> %1, <vscale x 1 x half> %1,
<vscale x 1 x half> %2, <vscale x 1 x half> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
iXLen %4, iXLen 2) iXLen 7, iXLen %4, iXLen 2)
ret <vscale x 1 x half> %a ret <vscale x 1 x half> %a
} }
declare <vscale x 1 x float> @llvm.riscv.vfwmacc.mask.nxv1f32.nxv1f16( declare <vscale x 1 x float> @llvm.riscv.vfwmacc.mask.nxv1f32.nxv1f16(
<vscale x 1 x float>, <vscale x 1 x float>,
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x half>, <vscale x 1 x half>,
▲ Show 20 Lines • Show All 493 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/masked-tumu.ll

Show First 20 Lines • Show All 719 Lines • ▼ Show 20 Linesentry:
ret <vscale x 1 x float> %a ret <vscale x 1 x float> %a
} }
declare <vscale x 1 x half> @llvm.riscv.vfmacc.mask.nxv1f16.nxv1f16( declare <vscale x 1 x half> @llvm.riscv.vfmacc.mask.nxv1f16.nxv1f16(
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
iXLen, iXLen) iXLen, iXLen, iXLen)
define <vscale x 1 x half> @intrinsic_vfmacc_mask_vv_nxv1f16_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind { define <vscale x 1 x half> @intrinsic_vfmacc_mask_vv_nxv1f16_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfmacc_mask_vv_nxv1f16_nxv1f16_nxv1f16: ; CHECK-LABEL: intrinsic_vfmacc_mask_vv_nxv1f16_nxv1f16_nxv1f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu
; CHECK-NEXT: vfmacc.vv v8, v9, v10, v0.t ; CHECK-NEXT: vfmacc.vv v8, v9, v10, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x half> @llvm.riscv.vfmacc.mask.nxv1f16.nxv1f16( %a = call <vscale x 1 x half> @llvm.riscv.vfmacc.mask.nxv1f16.nxv1f16(
<vscale x 1 x half> %0, <vscale x 1 x half> %0,
<vscale x 1 x half> %1, <vscale x 1 x half> %1,
<vscale x 1 x half> %2, <vscale x 1 x half> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
iXLen %4, iXLen 0) iXLen 7, iXLen %4, iXLen 0)
ret <vscale x 1 x half> %a ret <vscale x 1 x half> %a
} }
declare <vscale x 1 x float> @llvm.riscv.vfwmacc.mask.nxv1f32.nxv1f16( declare <vscale x 1 x float> @llvm.riscv.vfwmacc.mask.nxv1f32.nxv1f16(
<vscale x 1 x float>, <vscale x 1 x float>,
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x half>, <vscale x 1 x half>,
▲ Show 20 Lines • Show All 493 Lines • Show Last 20 Lines

llvm/test/CodeGen/RISCV/rvv/unmasked-ta.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zfh,+experimental-zvfh \ ; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zfh,+experimental-zvfh \
; RUN: -verify-machineinstrs -target-abi=ilp32d | FileCheck %s --check-prefixes=CHECK,RV32 ; RUN: -verify-machineinstrs -target-abi=ilp32d | FileCheck %s --check-prefixes=CHECK,RV32
; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zfh,+experimental-zvfh \ ; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zfh,+experimental-zvfh \
; RUN: -verify-machineinstrs -target-abi=lp64d | FileCheck %s --check-prefixes=CHECK,RV64 ; RUN: -verify-machineinstrs -target-abi=lp64d | FileCheck %s --check-prefixes=CHECK,RV64
declare <vscale x 1 x float> @llvm.riscv.vfmacc.nxv1f32.nxv1f32( declare <vscale x 1 x float> @llvm.riscv.vfmacc.nxv1f32.nxv1f32(
<vscale x 1 x float>, <vscale x 1 x float>,
<vscale x 1 x float>, <vscale x 1 x float>,
<vscale x 1 x float>, <vscale x 1 x float>,
iXLen, iXLen, iXLen, iXLen);
iXLen);
define <vscale x 1 x float> @intrinsic_vfmacc_vv_nxv1f32_nxv1f32_nxv1f32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, iXLen %3) nounwind { define <vscale x 1 x float> @intrinsic_vfmacc_vv_nxv1f32_nxv1f32_nxv1f32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfmacc_vv_nxv1f32_nxv1f32_nxv1f32: ; CHECK-LABEL: intrinsic_vfmacc_vv_nxv1f32_nxv1f32_nxv1f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
; CHECK-NEXT: vfmacc.vv v8, v10, v9 ; CHECK-NEXT: vfmacc.vv v8, v10, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x float> @llvm.riscv.vfmacc.nxv1f32.nxv1f32( %a = call <vscale x 1 x float> @llvm.riscv.vfmacc.nxv1f32.nxv1f32(
<vscale x 1 x float> %0, <vscale x 1 x float> %0,
<vscale x 1 x float> %1, <vscale x 1 x float> %1,
<vscale x 1 x float> %2, <vscale x 1 x float> %2,
iXLen %3, iXLen 1) iXLen 7, iXLen %3, iXLen 1)
ret <vscale x 1 x float> %a ret <vscale x 1 x float> %a
} }
declare <vscale x 1 x float> @llvm.riscv.vfmadd.nxv1f32.nxv1f32( declare <vscale x 1 x float> @llvm.riscv.vfmadd.nxv1f32.nxv1f32(
<vscale x 1 x float>, <vscale x 1 x float>,
<vscale x 1 x float>, <vscale x 1 x float>,
<vscale x 1 x float>, <vscale x 1 x float>,
iXLen, iXLen, iXLen, iXLen);
iXLen);
define <vscale x 1 x float> @intrinsic_vfmadd_vv_nxv1f32_nxv1f32_nxv1f32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, iXLen %3) nounwind { define <vscale x 1 x float> @intrinsic_vfmadd_vv_nxv1f32_nxv1f32_nxv1f32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfmadd_vv_nxv1f32_nxv1f32_nxv1f32: ; CHECK-LABEL: intrinsic_vfmadd_vv_nxv1f32_nxv1f32_nxv1f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
; CHECK-NEXT: vfmadd.vv v8, v9, v10 ; CHECK-NEXT: vfmadd.vv v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x float> @llvm.riscv.vfmadd.nxv1f32.nxv1f32( %a = call <vscale x 1 x float> @llvm.riscv.vfmadd.nxv1f32.nxv1f32(
<vscale x 1 x float> %0, <vscale x 1 x float> %0,
<vscale x 1 x float> %1, <vscale x 1 x float> %1,
<vscale x 1 x float> %2, <vscale x 1 x float> %2,
iXLen %3, iXLen 1) iXLen 7, iXLen %3, iXLen 1)
ret <vscale x 1 x float> %a ret <vscale x 1 x float> %a
} }
declare <vscale x 1 x float> @llvm.riscv.vfmsac.nxv1f32.nxv1f32( declare <vscale x 1 x float> @llvm.riscv.vfmsac.nxv1f32.nxv1f32(
<vscale x 1 x float>, <vscale x 1 x float>,
<vscale x 1 x float>, <vscale x 1 x float>,
<vscale x 1 x float>, <vscale x 1 x float>,
iXLen, iXLen, iXLen, iXLen);
iXLen);
define <vscale x 1 x float> @intrinsic_vfmsac_vv_nxv1f32_nxv1f32_nxv1f32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, iXLen %3) nounwind { define <vscale x 1 x float> @intrinsic_vfmsac_vv_nxv1f32_nxv1f32_nxv1f32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfmsac_vv_nxv1f32_nxv1f32_nxv1f32: ; CHECK-LABEL: intrinsic_vfmsac_vv_nxv1f32_nxv1f32_nxv1f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
; CHECK-NEXT: vfmsac.vv v8, v10, v9 ; CHECK-NEXT: vfmsac.vv v8, v10, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x float> @llvm.riscv.vfmsac.nxv1f32.nxv1f32( %a = call <vscale x 1 x float> @llvm.riscv.vfmsac.nxv1f32.nxv1f32(
<vscale x 1 x float> %0, <vscale x 1 x float> %0,
<vscale x 1 x float> %1, <vscale x 1 x float> %1,
<vscale x 1 x float> %2, <vscale x 1 x float> %2,
iXLen %3, iXLen 1) iXLen 7, iXLen %3, iXLen 1)
ret <vscale x 1 x float> %a ret <vscale x 1 x float> %a
} }
declare <vscale x 1 x float> @llvm.riscv.vfmsub.nxv1f32.nxv1f32( declare <vscale x 1 x float> @llvm.riscv.vfmsub.nxv1f32.nxv1f32(
<vscale x 1 x float>, <vscale x 1 x float>,
<vscale x 1 x float>, <vscale x 1 x float>,
<vscale x 1 x float>, <vscale x 1 x float>,
iXLen, iXLen, iXLen, iXLen);
iXLen);
define <vscale x 1 x float> @intrinsic_vfmsub_vv_nxv1f32_nxv1f32_nxv1f32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, iXLen %3) nounwind { define <vscale x 1 x float> @intrinsic_vfmsub_vv_nxv1f32_nxv1f32_nxv1f32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfmsub_vv_nxv1f32_nxv1f32_nxv1f32: ; CHECK-LABEL: intrinsic_vfmsub_vv_nxv1f32_nxv1f32_nxv1f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
; CHECK-NEXT: vfmsub.vv v8, v9, v10 ; CHECK-NEXT: vfmsub.vv v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x float> @llvm.riscv.vfmsub.nxv1f32.nxv1f32( %a = call <vscale x 1 x float> @llvm.riscv.vfmsub.nxv1f32.nxv1f32(
<vscale x 1 x float> %0, <vscale x 1 x float> %0,
<vscale x 1 x float> %1, <vscale x 1 x float> %1,
<vscale x 1 x float> %2, <vscale x 1 x float> %2,
iXLen %3, iXLen 1) iXLen 7, iXLen %3, iXLen 1)
ret <vscale x 1 x float> %a ret <vscale x 1 x float> %a
} }
declare <vscale x 1 x float> @llvm.riscv.vfnmacc.nxv1f32.nxv1f32( declare <vscale x 1 x float> @llvm.riscv.vfnmacc.nxv1f32.nxv1f32(
<vscale x 1 x float>, <vscale x 1 x float>,
<vscale x 1 x float>, <vscale x 1 x float>,
<vscale x 1 x float>, <vscale x 1 x float>,
iXLen, iXLen, iXLen, iXLen);
iXLen);
define <vscale x 1 x float> @intrinsic_vfnmacc_vv_nxv1f32_nxv1f32_nxv1f32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, iXLen %3) nounwind { define <vscale x 1 x float> @intrinsic_vfnmacc_vv_nxv1f32_nxv1f32_nxv1f32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfnmacc_vv_nxv1f32_nxv1f32_nxv1f32: ; CHECK-LABEL: intrinsic_vfnmacc_vv_nxv1f32_nxv1f32_nxv1f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
; CHECK-NEXT: vfnmacc.vv v8, v10, v9 ; CHECK-NEXT: vfnmacc.vv v8, v10, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x float> @llvm.riscv.vfnmacc.nxv1f32.nxv1f32( %a = call <vscale x 1 x float> @llvm.riscv.vfnmacc.nxv1f32.nxv1f32(
<vscale x 1 x float> %0, <vscale x 1 x float> %0,
<vscale x 1 x float> %1, <vscale x 1 x float> %1,
<vscale x 1 x float> %2, <vscale x 1 x float> %2,
iXLen %3, iXLen 1) iXLen 7, iXLen %3, iXLen 1)
ret <vscale x 1 x float> %a ret <vscale x 1 x float> %a
} }
declare <vscale x 1 x float> @llvm.riscv.vfnmadd.nxv1f32.nxv1f32( declare <vscale x 1 x float> @llvm.riscv.vfnmadd.nxv1f32.nxv1f32(
<vscale x 1 x float>, <vscale x 1 x float>,
<vscale x 1 x float>, <vscale x 1 x float>,
<vscale x 1 x float>, <vscale x 1 x float>,
iXLen, iXLen, iXLen, iXLen);
iXLen);
define <vscale x 1 x float> @intrinsic_vfnmadd_vv_nxv1f32_nxv1f32_nxv1f32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, iXLen %3) nounwind { define <vscale x 1 x float> @intrinsic_vfnmadd_vv_nxv1f32_nxv1f32_nxv1f32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfnmadd_vv_nxv1f32_nxv1f32_nxv1f32: ; CHECK-LABEL: intrinsic_vfnmadd_vv_nxv1f32_nxv1f32_nxv1f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
; CHECK-NEXT: vfnmadd.vv v8, v9, v10 ; CHECK-NEXT: vfnmadd.vv v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x float> @llvm.riscv.vfnmadd.nxv1f32.nxv1f32( %a = call <vscale x 1 x float> @llvm.riscv.vfnmadd.nxv1f32.nxv1f32(
<vscale x 1 x float> %0, <vscale x 1 x float> %0,
<vscale x 1 x float> %1, <vscale x 1 x float> %1,
<vscale x 1 x float> %2, <vscale x 1 x float> %2,
iXLen %3, iXLen 1) iXLen 7, iXLen %3, iXLen 1)
ret <vscale x 1 x float> %a ret <vscale x 1 x float> %a
} }
declare <vscale x 1 x float> @llvm.riscv.vfnmsac.nxv1f32.nxv1f32( declare <vscale x 1 x float> @llvm.riscv.vfnmsac.nxv1f32.nxv1f32(
<vscale x 1 x float>, <vscale x 1 x float>,
<vscale x 1 x float>, <vscale x 1 x float>,
<vscale x 1 x float>, <vscale x 1 x float>,
iXLen, iXLen, iXLen, iXLen);
iXLen);
define <vscale x 1 x float> @intrinsic_vfnmsac_vv_nxv1f32_nxv1f32_nxv1f32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, iXLen %3) nounwind { define <vscale x 1 x float> @intrinsic_vfnmsac_vv_nxv1f32_nxv1f32_nxv1f32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfnmsac_vv_nxv1f32_nxv1f32_nxv1f32: ; CHECK-LABEL: intrinsic_vfnmsac_vv_nxv1f32_nxv1f32_nxv1f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
; CHECK-NEXT: vfnmsac.vv v8, v10, v9 ; CHECK-NEXT: vfnmsac.vv v8, v10, v9
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x float> @llvm.riscv.vfnmsac.nxv1f32.nxv1f32( %a = call <vscale x 1 x float> @llvm.riscv.vfnmsac.nxv1f32.nxv1f32(
<vscale x 1 x float> %0, <vscale x 1 x float> %0,
<vscale x 1 x float> %1, <vscale x 1 x float> %1,
<vscale x 1 x float> %2, <vscale x 1 x float> %2,
iXLen %3, iXLen 1) iXLen 7, iXLen %3, iXLen 1)
ret <vscale x 1 x float> %a ret <vscale x 1 x float> %a
} }
declare <vscale x 1 x float> @llvm.riscv.vfnmsub.nxv1f32.nxv1f32( declare <vscale x 1 x float> @llvm.riscv.vfnmsub.nxv1f32.nxv1f32(
<vscale x 1 x float>, <vscale x 1 x float>,
<vscale x 1 x float>, <vscale x 1 x float>,
<vscale x 1 x float>, <vscale x 1 x float>,
iXLen, iXLen, iXLen, iXLen);
iXLen);
define <vscale x 1 x float> @intrinsic_vfnmsub_vv_nxv1f32_nxv1f32_nxv1f32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, iXLen %3) nounwind { define <vscale x 1 x float> @intrinsic_vfnmsub_vv_nxv1f32_nxv1f32_nxv1f32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfnmsub_vv_nxv1f32_nxv1f32_nxv1f32: ; CHECK-LABEL: intrinsic_vfnmsub_vv_nxv1f32_nxv1f32_nxv1f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, ta, ma
; CHECK-NEXT: vfnmsub.vv v8, v9, v10 ; CHECK-NEXT: vfnmsub.vv v8, v9, v10
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x float> @llvm.riscv.vfnmsub.nxv1f32.nxv1f32( %a = call <vscale x 1 x float> @llvm.riscv.vfnmsub.nxv1f32.nxv1f32(
<vscale x 1 x float> %0, <vscale x 1 x float> %0,
<vscale x 1 x float> %1, <vscale x 1 x float> %1,
<vscale x 1 x float> %2, <vscale x 1 x float> %2,
iXLen %3, iXLen 1) iXLen 7, iXLen %3, iXLen 1)
ret <vscale x 1 x float> %a ret <vscale x 1 x float> %a
} }
declare <vscale x 1 x float> @llvm.riscv.vfwmacc.nxv1f32.nxv1f16( declare <vscale x 1 x float> @llvm.riscv.vfwmacc.nxv1f32.nxv1f16(
<vscale x 1 x float>, <vscale x 1 x float>,
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x half>, <vscale x 1 x half>,
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llvm/test/CodeGen/RISCV/rvv/vfmacc.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zfh,+experimental-zvfh \ ; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zfh,+experimental-zvfh \
; RUN: -verify-machineinstrs -target-abi=ilp32d | FileCheck %s ; RUN: -verify-machineinstrs -target-abi=ilp32d | FileCheck %s
; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zfh,+experimental-zvfh \ ; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zfh,+experimental-zvfh \
; RUN: -verify-machineinstrs -target-abi=lp64d | FileCheck %s ; RUN: -verify-machineinstrs -target-abi=lp64d | FileCheck %s
declare <vscale x 1 x half> @llvm.riscv.vfmacc.nxv1f16.nxv1f16( declare <vscale x 1 x half> @llvm.riscv.vfmacc.nxv1f16.nxv1f16(
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x half>, <vscale x 1 x half>,
iXLen, iXLen, iXLen, iXLen);
iXLen);
define <vscale x 1 x half> @intrinsic_vfmacc_vv_nxv1f16_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, iXLen %3) nounwind { define <vscale x 1 x half> @intrinsic_vfmacc_vv_nxv1f16_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfmacc_vv_nxv1f16_nxv1f16_nxv1f16: ; CHECK-LABEL: intrinsic_vfmacc_vv_nxv1f16_nxv1f16_nxv1f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, ma ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, ma
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfmacc.vv v8, v9, v10 ; CHECK-NEXT: vfmacc.vv v8, v9, v10
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x half> @llvm.riscv.vfmacc.nxv1f16.nxv1f16( %a = call <vscale x 1 x half> @llvm.riscv.vfmacc.nxv1f16.nxv1f16(
<vscale x 1 x half> %0, <vscale x 1 x half> %0,
<vscale x 1 x half> %1, <vscale x 1 x half> %1,
<vscale x 1 x half> %2, <vscale x 1 x half> %2,
iXLen %3, iXLen 0) iXLen 0, iXLen %3, iXLen 0)
ret <vscale x 1 x half> %a ret <vscale x 1 x half> %a
} }
declare <vscale x 1 x half> @llvm.riscv.vfmacc.mask.nxv1f16.nxv1f16( declare <vscale x 1 x half> @llvm.riscv.vfmacc.mask.nxv1f16.nxv1f16(
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
iXLen, iXLen); iXLen, iXLen, iXLen);
define <vscale x 1 x half> @intrinsic_vfmacc_mask_vv_nxv1f16_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind { define <vscale x 1 x half> @intrinsic_vfmacc_mask_vv_nxv1f16_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfmacc_mask_vv_nxv1f16_nxv1f16_nxv1f16: ; CHECK-LABEL: intrinsic_vfmacc_mask_vv_nxv1f16_nxv1f16_nxv1f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfmacc.vv v8, v9, v10, v0.t ; CHECK-NEXT: vfmacc.vv v8, v9, v10, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x half> @llvm.riscv.vfmacc.mask.nxv1f16.nxv1f16( %a = call <vscale x 1 x half> @llvm.riscv.vfmacc.mask.nxv1f16.nxv1f16(
<vscale x 1 x half> %0, <vscale x 1 x half> %0,
<vscale x 1 x half> %1, <vscale x 1 x half> %1,
<vscale x 1 x half> %2, <vscale x 1 x half> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
iXLen %4, iXLen 0) iXLen 0, iXLen %4, iXLen 0)
ret <vscale x 1 x half> %a ret <vscale x 1 x half> %a
} }
declare <vscale x 2 x half> @llvm.riscv.vfmacc.nxv2f16.nxv2f16( declare <vscale x 2 x half> @llvm.riscv.vfmacc.nxv2f16.nxv2f16(
<vscale x 2 x half>, <vscale x 2 x half>,
<vscale x 2 x half>, <vscale x 2 x half>,
<vscale x 2 x half>, <vscale x 2 x half>,
iXLen, iXLen, iXLen, iXLen);
iXLen);
define <vscale x 2 x half> @intrinsic_vfmacc_vv_nxv2f16_nxv2f16_nxv2f16(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, iXLen %3) nounwind { define <vscale x 2 x half> @intrinsic_vfmacc_vv_nxv2f16_nxv2f16_nxv2f16(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfmacc_vv_nxv2f16_nxv2f16_nxv2f16: ; CHECK-LABEL: intrinsic_vfmacc_vv_nxv2f16_nxv2f16_nxv2f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, ma ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, ma
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfmacc.vv v8, v9, v10 ; CHECK-NEXT: vfmacc.vv v8, v9, v10
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x half> @llvm.riscv.vfmacc.nxv2f16.nxv2f16( %a = call <vscale x 2 x half> @llvm.riscv.vfmacc.nxv2f16.nxv2f16(
<vscale x 2 x half> %0, <vscale x 2 x half> %0,
<vscale x 2 x half> %1, <vscale x 2 x half> %1,
<vscale x 2 x half> %2, <vscale x 2 x half> %2,
iXLen %3, iXLen 0) iXLen 0, iXLen %3, iXLen 0)
ret <vscale x 2 x half> %a ret <vscale x 2 x half> %a
} }
declare <vscale x 2 x half> @llvm.riscv.vfmacc.mask.nxv2f16.nxv2f16( declare <vscale x 2 x half> @llvm.riscv.vfmacc.mask.nxv2f16.nxv2f16(
<vscale x 2 x half>, <vscale x 2 x half>,
<vscale x 2 x half>, <vscale x 2 x half>,
<vscale x 2 x half>, <vscale x 2 x half>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
iXLen, iXLen); iXLen, iXLen, iXLen);
define <vscale x 2 x half> @intrinsic_vfmacc_mask_vv_nxv2f16_nxv2f16_nxv2f16(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind { define <vscale x 2 x half> @intrinsic_vfmacc_mask_vv_nxv2f16_nxv2f16_nxv2f16(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfmacc_mask_vv_nxv2f16_nxv2f16_nxv2f16: ; CHECK-LABEL: intrinsic_vfmacc_mask_vv_nxv2f16_nxv2f16_nxv2f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfmacc.vv v8, v9, v10, v0.t ; CHECK-NEXT: vfmacc.vv v8, v9, v10, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x half> @llvm.riscv.vfmacc.mask.nxv2f16.nxv2f16( %a = call <vscale x 2 x half> @llvm.riscv.vfmacc.mask.nxv2f16.nxv2f16(
<vscale x 2 x half> %0, <vscale x 2 x half> %0,
<vscale x 2 x half> %1, <vscale x 2 x half> %1,
<vscale x 2 x half> %2, <vscale x 2 x half> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
iXLen %4, iXLen 0) iXLen 0, iXLen %4, iXLen 0)
ret <vscale x 2 x half> %a ret <vscale x 2 x half> %a
} }
declare <vscale x 4 x half> @llvm.riscv.vfmacc.nxv4f16.nxv4f16( declare <vscale x 4 x half> @llvm.riscv.vfmacc.nxv4f16.nxv4f16(
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 4 x half>, <vscale x 4 x half>,
iXLen, iXLen, iXLen, iXLen);
iXLen);
define <vscale x 4 x half> @intrinsic_vfmacc_vv_nxv4f16_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, iXLen %3) nounwind { define <vscale x 4 x half> @intrinsic_vfmacc_vv_nxv4f16_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfmacc_vv_nxv4f16_nxv4f16_nxv4f16: ; CHECK-LABEL: intrinsic_vfmacc_vv_nxv4f16_nxv4f16_nxv4f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, ma ; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, ma
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfmacc.vv v8, v9, v10 ; CHECK-NEXT: vfmacc.vv v8, v9, v10
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x half> @llvm.riscv.vfmacc.nxv4f16.nxv4f16( %a = call <vscale x 4 x half> @llvm.riscv.vfmacc.nxv4f16.nxv4f16(
<vscale x 4 x half> %0, <vscale x 4 x half> %0,
<vscale x 4 x half> %1, <vscale x 4 x half> %1,
<vscale x 4 x half> %2, <vscale x 4 x half> %2,
iXLen %3, iXLen 0) iXLen 0, iXLen %3, iXLen 0)
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 4 x half> @llvm.riscv.vfmacc.mask.nxv4f16.nxv4f16( declare <vscale x 4 x half> @llvm.riscv.vfmacc.mask.nxv4f16.nxv4f16(
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
iXLen, iXLen); iXLen, iXLen, iXLen);
define <vscale x 4 x half> @intrinsic_vfmacc_mask_vv_nxv4f16_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind { define <vscale x 4 x half> @intrinsic_vfmacc_mask_vv_nxv4f16_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfmacc_mask_vv_nxv4f16_nxv4f16_nxv4f16: ; CHECK-LABEL: intrinsic_vfmacc_mask_vv_nxv4f16_nxv4f16_nxv4f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfmacc.vv v8, v9, v10, v0.t ; CHECK-NEXT: vfmacc.vv v8, v9, v10, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x half> @llvm.riscv.vfmacc.mask.nxv4f16.nxv4f16( %a = call <vscale x 4 x half> @llvm.riscv.vfmacc.mask.nxv4f16.nxv4f16(
<vscale x 4 x half> %0, <vscale x 4 x half> %0,
<vscale x 4 x half> %1, <vscale x 4 x half> %1,
<vscale x 4 x half> %2, <vscale x 4 x half> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
iXLen %4, iXLen 0) iXLen 0, iXLen %4, iXLen 0)
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 8 x half> @llvm.riscv.vfmacc.nxv8f16.nxv8f16( declare <vscale x 8 x half> @llvm.riscv.vfmacc.nxv8f16.nxv8f16(
<vscale x 8 x half>, <vscale x 8 x half>,
<vscale x 8 x half>, <vscale x 8 x half>,
<vscale x 8 x half>, <vscale x 8 x half>,
iXLen, iXLen, iXLen, iXLen);
iXLen);
define <vscale x 8 x half> @intrinsic_vfmacc_vv_nxv8f16_nxv8f16_nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, iXLen %3) nounwind { define <vscale x 8 x half> @intrinsic_vfmacc_vv_nxv8f16_nxv8f16_nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfmacc_vv_nxv8f16_nxv8f16_nxv8f16: ; CHECK-LABEL: intrinsic_vfmacc_vv_nxv8f16_nxv8f16_nxv8f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, ma ; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, ma
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfmacc.vv v8, v10, v12 ; CHECK-NEXT: vfmacc.vv v8, v10, v12
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x half> @llvm.riscv.vfmacc.nxv8f16.nxv8f16( %a = call <vscale x 8 x half> @llvm.riscv.vfmacc.nxv8f16.nxv8f16(
<vscale x 8 x half> %0, <vscale x 8 x half> %0,
<vscale x 8 x half> %1, <vscale x 8 x half> %1,
<vscale x 8 x half> %2, <vscale x 8 x half> %2,
iXLen %3, iXLen 0) iXLen 0, iXLen %3, iXLen 0)
ret <vscale x 8 x half> %a ret <vscale x 8 x half> %a
} }
declare <vscale x 8 x half> @llvm.riscv.vfmacc.mask.nxv8f16.nxv8f16( declare <vscale x 8 x half> @llvm.riscv.vfmacc.mask.nxv8f16.nxv8f16(
<vscale x 8 x half>, <vscale x 8 x half>,
<vscale x 8 x half>, <vscale x 8 x half>,
<vscale x 8 x half>, <vscale x 8 x half>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
iXLen, iXLen); iXLen, iXLen, iXLen);
define <vscale x 8 x half> @intrinsic_vfmacc_mask_vv_nxv8f16_nxv8f16_nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind { define <vscale x 8 x half> @intrinsic_vfmacc_mask_vv_nxv8f16_nxv8f16_nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfmacc_mask_vv_nxv8f16_nxv8f16_nxv8f16: ; CHECK-LABEL: intrinsic_vfmacc_mask_vv_nxv8f16_nxv8f16_nxv8f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, mu
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfmacc.vv v8, v10, v12, v0.t ; CHECK-NEXT: vfmacc.vv v8, v10, v12, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x half> @llvm.riscv.vfmacc.mask.nxv8f16.nxv8f16( %a = call <vscale x 8 x half> @llvm.riscv.vfmacc.mask.nxv8f16.nxv8f16(
<vscale x 8 x half> %0, <vscale x 8 x half> %0,
<vscale x 8 x half> %1, <vscale x 8 x half> %1,
<vscale x 8 x half> %2, <vscale x 8 x half> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
iXLen %4, iXLen 0) iXLen 0, iXLen %4, iXLen 0)
ret <vscale x 8 x half> %a ret <vscale x 8 x half> %a
} }
declare <vscale x 16 x half> @llvm.riscv.vfmacc.nxv16f16.nxv16f16( declare <vscale x 16 x half> @llvm.riscv.vfmacc.nxv16f16.nxv16f16(
<vscale x 16 x half>, <vscale x 16 x half>,
<vscale x 16 x half>, <vscale x 16 x half>,
<vscale x 16 x half>, <vscale x 16 x half>,
iXLen, iXLen, iXLen, iXLen);
iXLen);
define <vscale x 16 x half> @intrinsic_vfmacc_vv_nxv16f16_nxv16f16_nxv16f16(<vscale x 16 x half> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %2, iXLen %3) nounwind { define <vscale x 16 x half> @intrinsic_vfmacc_vv_nxv16f16_nxv16f16_nxv16f16(<vscale x 16 x half> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfmacc_vv_nxv16f16_nxv16f16_nxv16f16: ; CHECK-LABEL: intrinsic_vfmacc_vv_nxv16f16_nxv16f16_nxv16f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, ma ; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, ma
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfmacc.vv v8, v12, v16 ; CHECK-NEXT: vfmacc.vv v8, v12, v16
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x half> @llvm.riscv.vfmacc.nxv16f16.nxv16f16( %a = call <vscale x 16 x half> @llvm.riscv.vfmacc.nxv16f16.nxv16f16(
<vscale x 16 x half> %0, <vscale x 16 x half> %0,
<vscale x 16 x half> %1, <vscale x 16 x half> %1,
<vscale x 16 x half> %2, <vscale x 16 x half> %2,
iXLen %3, iXLen 0) iXLen 0, iXLen %3, iXLen 0)
ret <vscale x 16 x half> %a ret <vscale x 16 x half> %a
} }
declare <vscale x 16 x half> @llvm.riscv.vfmacc.mask.nxv16f16.nxv16f16( declare <vscale x 16 x half> @llvm.riscv.vfmacc.mask.nxv16f16.nxv16f16(
<vscale x 16 x half>, <vscale x 16 x half>,
<vscale x 16 x half>, <vscale x 16 x half>,
<vscale x 16 x half>, <vscale x 16 x half>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
iXLen, iXLen); iXLen, iXLen, iXLen);
define <vscale x 16 x half> @intrinsic_vfmacc_mask_vv_nxv16f16_nxv16f16_nxv16f16(<vscale x 16 x half> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind { define <vscale x 16 x half> @intrinsic_vfmacc_mask_vv_nxv16f16_nxv16f16_nxv16f16(<vscale x 16 x half> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfmacc_mask_vv_nxv16f16_nxv16f16_nxv16f16: ; CHECK-LABEL: intrinsic_vfmacc_mask_vv_nxv16f16_nxv16f16_nxv16f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfmacc.vv v8, v12, v16, v0.t ; CHECK-NEXT: vfmacc.vv v8, v12, v16, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x half> @llvm.riscv.vfmacc.mask.nxv16f16.nxv16f16( %a = call <vscale x 16 x half> @llvm.riscv.vfmacc.mask.nxv16f16.nxv16f16(
<vscale x 16 x half> %0, <vscale x 16 x half> %0,
<vscale x 16 x half> %1, <vscale x 16 x half> %1,
<vscale x 16 x half> %2, <vscale x 16 x half> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
iXLen %4, iXLen 0) iXLen 0, iXLen %4, iXLen 0)
ret <vscale x 16 x half> %a ret <vscale x 16 x half> %a
} }
declare <vscale x 1 x float> @llvm.riscv.vfmacc.nxv1f32.nxv1f32( declare <vscale x 1 x float> @llvm.riscv.vfmacc.nxv1f32.nxv1f32(
<vscale x 1 x float>, <vscale x 1 x float>,
<vscale x 1 x float>, <vscale x 1 x float>,
<vscale x 1 x float>, <vscale x 1 x float>,
iXLen, iXLen, iXLen, iXLen);
iXLen);
define <vscale x 1 x float> @intrinsic_vfmacc_vv_nxv1f32_nxv1f32_nxv1f32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, iXLen %3) nounwind { define <vscale x 1 x float> @intrinsic_vfmacc_vv_nxv1f32_nxv1f32_nxv1f32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfmacc_vv_nxv1f32_nxv1f32_nxv1f32: ; CHECK-LABEL: intrinsic_vfmacc_vv_nxv1f32_nxv1f32_nxv1f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, ma ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, ma
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfmacc.vv v8, v9, v10 ; CHECK-NEXT: vfmacc.vv v8, v9, v10
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x float> @llvm.riscv.vfmacc.nxv1f32.nxv1f32( %a = call <vscale x 1 x float> @llvm.riscv.vfmacc.nxv1f32.nxv1f32(
<vscale x 1 x float> %0, <vscale x 1 x float> %0,
<vscale x 1 x float> %1, <vscale x 1 x float> %1,
<vscale x 1 x float> %2, <vscale x 1 x float> %2,
iXLen %3, iXLen 0) iXLen 0, iXLen %3, iXLen 0)
ret <vscale x 1 x float> %a ret <vscale x 1 x float> %a
} }
declare <vscale x 1 x float> @llvm.riscv.vfmacc.mask.nxv1f32.nxv1f32( declare <vscale x 1 x float> @llvm.riscv.vfmacc.mask.nxv1f32.nxv1f32(
<vscale x 1 x float>, <vscale x 1 x float>,
<vscale x 1 x float>, <vscale x 1 x float>,
<vscale x 1 x float>, <vscale x 1 x float>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
iXLen, iXLen); iXLen, iXLen, iXLen);
define <vscale x 1 x float> @intrinsic_vfmacc_mask_vv_nxv1f32_nxv1f32_nxv1f32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind { define <vscale x 1 x float> @intrinsic_vfmacc_mask_vv_nxv1f32_nxv1f32_nxv1f32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfmacc_mask_vv_nxv1f32_nxv1f32_nxv1f32: ; CHECK-LABEL: intrinsic_vfmacc_mask_vv_nxv1f32_nxv1f32_nxv1f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfmacc.vv v8, v9, v10, v0.t ; CHECK-NEXT: vfmacc.vv v8, v9, v10, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x float> @llvm.riscv.vfmacc.mask.nxv1f32.nxv1f32( %a = call <vscale x 1 x float> @llvm.riscv.vfmacc.mask.nxv1f32.nxv1f32(
<vscale x 1 x float> %0, <vscale x 1 x float> %0,
<vscale x 1 x float> %1, <vscale x 1 x float> %1,
<vscale x 1 x float> %2, <vscale x 1 x float> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
iXLen %4, iXLen 0) iXLen 0, iXLen %4, iXLen 0)
ret <vscale x 1 x float> %a ret <vscale x 1 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vfmacc.nxv2f32.nxv2f32( declare <vscale x 2 x float> @llvm.riscv.vfmacc.nxv2f32.nxv2f32(
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 2 x float>, <vscale x 2 x float>,
iXLen, iXLen, iXLen, iXLen);
iXLen);
define <vscale x 2 x float> @intrinsic_vfmacc_vv_nxv2f32_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, iXLen %3) nounwind { define <vscale x 2 x float> @intrinsic_vfmacc_vv_nxv2f32_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfmacc_vv_nxv2f32_nxv2f32_nxv2f32: ; CHECK-LABEL: intrinsic_vfmacc_vv_nxv2f32_nxv2f32_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, ma ; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, ma
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfmacc.vv v8, v9, v10 ; CHECK-NEXT: vfmacc.vv v8, v9, v10
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfmacc.nxv2f32.nxv2f32( %a = call <vscale x 2 x float> @llvm.riscv.vfmacc.nxv2f32.nxv2f32(
<vscale x 2 x float> %0, <vscale x 2 x float> %0,
<vscale x 2 x float> %1, <vscale x 2 x float> %1,
<vscale x 2 x float> %2, <vscale x 2 x float> %2,
iXLen %3, iXLen 0) iXLen 0, iXLen %3, iXLen 0)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vfmacc.mask.nxv2f32.nxv2f32( declare <vscale x 2 x float> @llvm.riscv.vfmacc.mask.nxv2f32.nxv2f32(
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
iXLen, iXLen); iXLen, iXLen, iXLen);
define <vscale x 2 x float> @intrinsic_vfmacc_mask_vv_nxv2f32_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind { define <vscale x 2 x float> @intrinsic_vfmacc_mask_vv_nxv2f32_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfmacc_mask_vv_nxv2f32_nxv2f32_nxv2f32: ; CHECK-LABEL: intrinsic_vfmacc_mask_vv_nxv2f32_nxv2f32_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfmacc.vv v8, v9, v10, v0.t ; CHECK-NEXT: vfmacc.vv v8, v9, v10, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfmacc.mask.nxv2f32.nxv2f32( %a = call <vscale x 2 x float> @llvm.riscv.vfmacc.mask.nxv2f32.nxv2f32(
<vscale x 2 x float> %0, <vscale x 2 x float> %0,
<vscale x 2 x float> %1, <vscale x 2 x float> %1,
<vscale x 2 x float> %2, <vscale x 2 x float> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
iXLen %4, iXLen 0) iXLen 0, iXLen %4, iXLen 0)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 4 x float> @llvm.riscv.vfmacc.nxv4f32.nxv4f32( declare <vscale x 4 x float> @llvm.riscv.vfmacc.nxv4f32.nxv4f32(
<vscale x 4 x float>, <vscale x 4 x float>,
<vscale x 4 x float>, <vscale x 4 x float>,
<vscale x 4 x float>, <vscale x 4 x float>,
iXLen, iXLen, iXLen, iXLen);
iXLen);
define <vscale x 4 x float> @intrinsic_vfmacc_vv_nxv4f32_nxv4f32_nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, <vscale x 4 x float> %2, iXLen %3) nounwind { define <vscale x 4 x float> @intrinsic_vfmacc_vv_nxv4f32_nxv4f32_nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, <vscale x 4 x float> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfmacc_vv_nxv4f32_nxv4f32_nxv4f32: ; CHECK-LABEL: intrinsic_vfmacc_vv_nxv4f32_nxv4f32_nxv4f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, ma ; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, ma
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfmacc.vv v8, v10, v12 ; CHECK-NEXT: vfmacc.vv v8, v10, v12
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x float> @llvm.riscv.vfmacc.nxv4f32.nxv4f32( %a = call <vscale x 4 x float> @llvm.riscv.vfmacc.nxv4f32.nxv4f32(
<vscale x 4 x float> %0, <vscale x 4 x float> %0,
<vscale x 4 x float> %1, <vscale x 4 x float> %1,
<vscale x 4 x float> %2, <vscale x 4 x float> %2,
iXLen %3, iXLen 0) iXLen 0, iXLen %3, iXLen 0)
ret <vscale x 4 x float> %a ret <vscale x 4 x float> %a
} }
declare <vscale x 4 x float> @llvm.riscv.vfmacc.mask.nxv4f32.nxv4f32( declare <vscale x 4 x float> @llvm.riscv.vfmacc.mask.nxv4f32.nxv4f32(
<vscale x 4 x float>, <vscale x 4 x float>,
<vscale x 4 x float>, <vscale x 4 x float>,
<vscale x 4 x float>, <vscale x 4 x float>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
iXLen, iXLen); iXLen, iXLen, iXLen);
define <vscale x 4 x float> @intrinsic_vfmacc_mask_vv_nxv4f32_nxv4f32_nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, <vscale x 4 x float> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind { define <vscale x 4 x float> @intrinsic_vfmacc_mask_vv_nxv4f32_nxv4f32_nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, <vscale x 4 x float> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfmacc_mask_vv_nxv4f32_nxv4f32_nxv4f32: ; CHECK-LABEL: intrinsic_vfmacc_mask_vv_nxv4f32_nxv4f32_nxv4f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfmacc.vv v8, v10, v12, v0.t ; CHECK-NEXT: vfmacc.vv v8, v10, v12, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x float> @llvm.riscv.vfmacc.mask.nxv4f32.nxv4f32( %a = call <vscale x 4 x float> @llvm.riscv.vfmacc.mask.nxv4f32.nxv4f32(
<vscale x 4 x float> %0, <vscale x 4 x float> %0,
<vscale x 4 x float> %1, <vscale x 4 x float> %1,
<vscale x 4 x float> %2, <vscale x 4 x float> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
iXLen %4, iXLen 0) iXLen 0, iXLen %4, iXLen 0)
ret <vscale x 4 x float> %a ret <vscale x 4 x float> %a
} }
declare <vscale x 8 x float> @llvm.riscv.vfmacc.nxv8f32.nxv8f32( declare <vscale x 8 x float> @llvm.riscv.vfmacc.nxv8f32.nxv8f32(
<vscale x 8 x float>, <vscale x 8 x float>,
<vscale x 8 x float>, <vscale x 8 x float>,
<vscale x 8 x float>, <vscale x 8 x float>,
iXLen, iXLen, iXLen, iXLen);
iXLen);
define <vscale x 8 x float> @intrinsic_vfmacc_vv_nxv8f32_nxv8f32_nxv8f32(<vscale x 8 x float> %0, <vscale x 8 x float> %1, <vscale x 8 x float> %2, iXLen %3) nounwind { define <vscale x 8 x float> @intrinsic_vfmacc_vv_nxv8f32_nxv8f32_nxv8f32(<vscale x 8 x float> %0, <vscale x 8 x float> %1, <vscale x 8 x float> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfmacc_vv_nxv8f32_nxv8f32_nxv8f32: ; CHECK-LABEL: intrinsic_vfmacc_vv_nxv8f32_nxv8f32_nxv8f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, ma ; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, ma
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfmacc.vv v8, v12, v16 ; CHECK-NEXT: vfmacc.vv v8, v12, v16
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x float> @llvm.riscv.vfmacc.nxv8f32.nxv8f32( %a = call <vscale x 8 x float> @llvm.riscv.vfmacc.nxv8f32.nxv8f32(
<vscale x 8 x float> %0, <vscale x 8 x float> %0,
<vscale x 8 x float> %1, <vscale x 8 x float> %1,
<vscale x 8 x float> %2, <vscale x 8 x float> %2,
iXLen %3, iXLen 0) iXLen 0, iXLen %3, iXLen 0)
ret <vscale x 8 x float> %a ret <vscale x 8 x float> %a
} }
declare <vscale x 8 x float> @llvm.riscv.vfmacc.mask.nxv8f32.nxv8f32( declare <vscale x 8 x float> @llvm.riscv.vfmacc.mask.nxv8f32.nxv8f32(
<vscale x 8 x float>, <vscale x 8 x float>,
<vscale x 8 x float>, <vscale x 8 x float>,
<vscale x 8 x float>, <vscale x 8 x float>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
iXLen, iXLen); iXLen, iXLen, iXLen);
define <vscale x 8 x float> @intrinsic_vfmacc_mask_vv_nxv8f32_nxv8f32_nxv8f32(<vscale x 8 x float> %0, <vscale x 8 x float> %1, <vscale x 8 x float> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind { define <vscale x 8 x float> @intrinsic_vfmacc_mask_vv_nxv8f32_nxv8f32_nxv8f32(<vscale x 8 x float> %0, <vscale x 8 x float> %1, <vscale x 8 x float> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfmacc_mask_vv_nxv8f32_nxv8f32_nxv8f32: ; CHECK-LABEL: intrinsic_vfmacc_mask_vv_nxv8f32_nxv8f32_nxv8f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfmacc.vv v8, v12, v16, v0.t ; CHECK-NEXT: vfmacc.vv v8, v12, v16, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x float> @llvm.riscv.vfmacc.mask.nxv8f32.nxv8f32( %a = call <vscale x 8 x float> @llvm.riscv.vfmacc.mask.nxv8f32.nxv8f32(
<vscale x 8 x float> %0, <vscale x 8 x float> %0,
<vscale x 8 x float> %1, <vscale x 8 x float> %1,
<vscale x 8 x float> %2, <vscale x 8 x float> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
iXLen %4, iXLen 0) iXLen 0, iXLen %4, iXLen 0)
ret <vscale x 8 x float> %a ret <vscale x 8 x float> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vfmacc.nxv1f64.nxv1f64( declare <vscale x 1 x double> @llvm.riscv.vfmacc.nxv1f64.nxv1f64(
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 1 x double>, <vscale x 1 x double>,
iXLen, iXLen, iXLen, iXLen);
iXLen);
define <vscale x 1 x double> @intrinsic_vfmacc_vv_nxv1f64_nxv1f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 1 x double> %1, <vscale x 1 x double> %2, iXLen %3) nounwind { define <vscale x 1 x double> @intrinsic_vfmacc_vv_nxv1f64_nxv1f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 1 x double> %1, <vscale x 1 x double> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfmacc_vv_nxv1f64_nxv1f64_nxv1f64: ; CHECK-LABEL: intrinsic_vfmacc_vv_nxv1f64_nxv1f64_nxv1f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, ma ; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, ma
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfmacc.vv v8, v9, v10 ; CHECK-NEXT: vfmacc.vv v8, v9, v10
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfmacc.nxv1f64.nxv1f64( %a = call <vscale x 1 x double> @llvm.riscv.vfmacc.nxv1f64.nxv1f64(
<vscale x 1 x double> %0, <vscale x 1 x double> %0,
<vscale x 1 x double> %1, <vscale x 1 x double> %1,
<vscale x 1 x double> %2, <vscale x 1 x double> %2,
iXLen %3, iXLen 0) iXLen 0, iXLen %3, iXLen 0)
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vfmacc.mask.nxv1f64.nxv1f64( declare <vscale x 1 x double> @llvm.riscv.vfmacc.mask.nxv1f64.nxv1f64(
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
iXLen, iXLen); iXLen, iXLen, iXLen);
define <vscale x 1 x double> @intrinsic_vfmacc_mask_vv_nxv1f64_nxv1f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 1 x double> %1, <vscale x 1 x double> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind { define <vscale x 1 x double> @intrinsic_vfmacc_mask_vv_nxv1f64_nxv1f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 1 x double> %1, <vscale x 1 x double> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfmacc_mask_vv_nxv1f64_nxv1f64_nxv1f64: ; CHECK-LABEL: intrinsic_vfmacc_mask_vv_nxv1f64_nxv1f64_nxv1f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, mu
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfmacc.vv v8, v9, v10, v0.t ; CHECK-NEXT: vfmacc.vv v8, v9, v10, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfmacc.mask.nxv1f64.nxv1f64( %a = call <vscale x 1 x double> @llvm.riscv.vfmacc.mask.nxv1f64.nxv1f64(
<vscale x 1 x double> %0, <vscale x 1 x double> %0,
<vscale x 1 x double> %1, <vscale x 1 x double> %1,
<vscale x 1 x double> %2, <vscale x 1 x double> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
iXLen %4, iXLen 0) iXLen 0, iXLen %4, iXLen 0)
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 2 x double> @llvm.riscv.vfmacc.nxv2f64.nxv2f64( declare <vscale x 2 x double> @llvm.riscv.vfmacc.nxv2f64.nxv2f64(
<vscale x 2 x double>, <vscale x 2 x double>,
<vscale x 2 x double>, <vscale x 2 x double>,
<vscale x 2 x double>, <vscale x 2 x double>,
iXLen, iXLen, iXLen, iXLen);
iXLen);
define <vscale x 2 x double> @intrinsic_vfmacc_vv_nxv2f64_nxv2f64_nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1, <vscale x 2 x double> %2, iXLen %3) nounwind { define <vscale x 2 x double> @intrinsic_vfmacc_vv_nxv2f64_nxv2f64_nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1, <vscale x 2 x double> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfmacc_vv_nxv2f64_nxv2f64_nxv2f64: ; CHECK-LABEL: intrinsic_vfmacc_vv_nxv2f64_nxv2f64_nxv2f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, ma ; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, ma
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfmacc.vv v8, v10, v12 ; CHECK-NEXT: vfmacc.vv v8, v10, v12
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x double> @llvm.riscv.vfmacc.nxv2f64.nxv2f64( %a = call <vscale x 2 x double> @llvm.riscv.vfmacc.nxv2f64.nxv2f64(
<vscale x 2 x double> %0, <vscale x 2 x double> %0,
<vscale x 2 x double> %1, <vscale x 2 x double> %1,
<vscale x 2 x double> %2, <vscale x 2 x double> %2,
iXLen %3, iXLen 0) iXLen 0, iXLen %3, iXLen 0)
ret <vscale x 2 x double> %a ret <vscale x 2 x double> %a
} }
declare <vscale x 2 x double> @llvm.riscv.vfmacc.mask.nxv2f64.nxv2f64( declare <vscale x 2 x double> @llvm.riscv.vfmacc.mask.nxv2f64.nxv2f64(
<vscale x 2 x double>, <vscale x 2 x double>,
<vscale x 2 x double>, <vscale x 2 x double>,
<vscale x 2 x double>, <vscale x 2 x double>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
iXLen, iXLen); iXLen, iXLen, iXLen);
define <vscale x 2 x double> @intrinsic_vfmacc_mask_vv_nxv2f64_nxv2f64_nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1, <vscale x 2 x double> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind { define <vscale x 2 x double> @intrinsic_vfmacc_mask_vv_nxv2f64_nxv2f64_nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1, <vscale x 2 x double> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfmacc_mask_vv_nxv2f64_nxv2f64_nxv2f64: ; CHECK-LABEL: intrinsic_vfmacc_mask_vv_nxv2f64_nxv2f64_nxv2f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, mu
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfmacc.vv v8, v10, v12, v0.t ; CHECK-NEXT: vfmacc.vv v8, v10, v12, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x double> @llvm.riscv.vfmacc.mask.nxv2f64.nxv2f64( %a = call <vscale x 2 x double> @llvm.riscv.vfmacc.mask.nxv2f64.nxv2f64(
<vscale x 2 x double> %0, <vscale x 2 x double> %0,
<vscale x 2 x double> %1, <vscale x 2 x double> %1,
<vscale x 2 x double> %2, <vscale x 2 x double> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
iXLen %4, iXLen 0) iXLen 0, iXLen %4, iXLen 0)
ret <vscale x 2 x double> %a ret <vscale x 2 x double> %a
} }
declare <vscale x 4 x double> @llvm.riscv.vfmacc.nxv4f64.nxv4f64( declare <vscale x 4 x double> @llvm.riscv.vfmacc.nxv4f64.nxv4f64(
<vscale x 4 x double>, <vscale x 4 x double>,
<vscale x 4 x double>, <vscale x 4 x double>,
<vscale x 4 x double>, <vscale x 4 x double>,
iXLen, iXLen, iXLen, iXLen);
iXLen);
define <vscale x 4 x double> @intrinsic_vfmacc_vv_nxv4f64_nxv4f64_nxv4f64(<vscale x 4 x double> %0, <vscale x 4 x double> %1, <vscale x 4 x double> %2, iXLen %3) nounwind { define <vscale x 4 x double> @intrinsic_vfmacc_vv_nxv4f64_nxv4f64_nxv4f64(<vscale x 4 x double> %0, <vscale x 4 x double> %1, <vscale x 4 x double> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfmacc_vv_nxv4f64_nxv4f64_nxv4f64: ; CHECK-LABEL: intrinsic_vfmacc_vv_nxv4f64_nxv4f64_nxv4f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, ma ; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, ma
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfmacc.vv v8, v12, v16 ; CHECK-NEXT: vfmacc.vv v8, v12, v16
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x double> @llvm.riscv.vfmacc.nxv4f64.nxv4f64( %a = call <vscale x 4 x double> @llvm.riscv.vfmacc.nxv4f64.nxv4f64(
<vscale x 4 x double> %0, <vscale x 4 x double> %0,
<vscale x 4 x double> %1, <vscale x 4 x double> %1,
<vscale x 4 x double> %2, <vscale x 4 x double> %2,
iXLen %3, iXLen 0) iXLen 0, iXLen %3, iXLen 0)
ret <vscale x 4 x double> %a ret <vscale x 4 x double> %a
} }
declare <vscale x 4 x double> @llvm.riscv.vfmacc.mask.nxv4f64.nxv4f64( declare <vscale x 4 x double> @llvm.riscv.vfmacc.mask.nxv4f64.nxv4f64(
<vscale x 4 x double>, <vscale x 4 x double>,
<vscale x 4 x double>, <vscale x 4 x double>,
<vscale x 4 x double>, <vscale x 4 x double>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
iXLen, iXLen); iXLen, iXLen, iXLen);
define <vscale x 4 x double> @intrinsic_vfmacc_mask_vv_nxv4f64_nxv4f64_nxv4f64(<vscale x 4 x double> %0, <vscale x 4 x double> %1, <vscale x 4 x double> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind { define <vscale x 4 x double> @intrinsic_vfmacc_mask_vv_nxv4f64_nxv4f64_nxv4f64(<vscale x 4 x double> %0, <vscale x 4 x double> %1, <vscale x 4 x double> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfmacc_mask_vv_nxv4f64_nxv4f64_nxv4f64: ; CHECK-LABEL: intrinsic_vfmacc_mask_vv_nxv4f64_nxv4f64_nxv4f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, mu
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfmacc.vv v8, v12, v16, v0.t ; CHECK-NEXT: vfmacc.vv v8, v12, v16, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x double> @llvm.riscv.vfmacc.mask.nxv4f64.nxv4f64( %a = call <vscale x 4 x double> @llvm.riscv.vfmacc.mask.nxv4f64.nxv4f64(
<vscale x 4 x double> %0, <vscale x 4 x double> %0,
<vscale x 4 x double> %1, <vscale x 4 x double> %1,
<vscale x 4 x double> %2, <vscale x 4 x double> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
iXLen %4, iXLen 0) iXLen 0, iXLen %4, iXLen 0)
ret <vscale x 4 x double> %a ret <vscale x 4 x double> %a
} }
declare <vscale x 1 x half> @llvm.riscv.vfmacc.nxv1f16.f16( declare <vscale x 1 x half> @llvm.riscv.vfmacc.nxv1f16.f16(
<vscale x 1 x half>, <vscale x 1 x half>,
half, half,
<vscale x 1 x half>, <vscale x 1 x half>,
iXLen, iXLen, iXLen, iXLen);
iXLen);
define <vscale x 1 x half> @intrinsic_vfmacc_vf_nxv1f16_f16_nxv1f16(<vscale x 1 x half> %0, half %1, <vscale x 1 x half> %2, iXLen %3) nounwind { define <vscale x 1 x half> @intrinsic_vfmacc_vf_nxv1f16_f16_nxv1f16(<vscale x 1 x half> %0, half %1, <vscale x 1 x half> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfmacc_vf_nxv1f16_f16_nxv1f16: ; CHECK-LABEL: intrinsic_vfmacc_vf_nxv1f16_f16_nxv1f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, ma ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, ma
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfmacc.vf v8, fa0, v9 ; CHECK-NEXT: vfmacc.vf v8, fa0, v9
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x half> @llvm.riscv.vfmacc.nxv1f16.f16( %a = call <vscale x 1 x half> @llvm.riscv.vfmacc.nxv1f16.f16(
<vscale x 1 x half> %0, <vscale x 1 x half> %0,
half %1, half %1,
<vscale x 1 x half> %2, <vscale x 1 x half> %2,
iXLen %3, iXLen 0) iXLen 0, iXLen %3, iXLen 0)
ret <vscale x 1 x half> %a ret <vscale x 1 x half> %a
} }
declare <vscale x 1 x half> @llvm.riscv.vfmacc.mask.nxv1f16.f16( declare <vscale x 1 x half> @llvm.riscv.vfmacc.mask.nxv1f16.f16(
<vscale x 1 x half>, <vscale x 1 x half>,
half, half,
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
iXLen, iXLen); iXLen, iXLen, iXLen);
define <vscale x 1 x half> @intrinsic_vfmacc_mask_vf_nxv1f16_f16_nxv1f16(<vscale x 1 x half> %0, half %1, <vscale x 1 x half> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind { define <vscale x 1 x half> @intrinsic_vfmacc_mask_vf_nxv1f16_f16_nxv1f16(<vscale x 1 x half> %0, half %1, <vscale x 1 x half> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfmacc_mask_vf_nxv1f16_f16_nxv1f16: ; CHECK-LABEL: intrinsic_vfmacc_mask_vf_nxv1f16_f16_nxv1f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfmacc.vf v8, fa0, v9, v0.t ; CHECK-NEXT: vfmacc.vf v8, fa0, v9, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x half> @llvm.riscv.vfmacc.mask.nxv1f16.f16( %a = call <vscale x 1 x half> @llvm.riscv.vfmacc.mask.nxv1f16.f16(
<vscale x 1 x half> %0, <vscale x 1 x half> %0,
half %1, half %1,
<vscale x 1 x half> %2, <vscale x 1 x half> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
iXLen %4, iXLen 0) iXLen 0, iXLen %4, iXLen 0)
ret <vscale x 1 x half> %a ret <vscale x 1 x half> %a
} }
declare <vscale x 2 x half> @llvm.riscv.vfmacc.nxv2f16.f16( declare <vscale x 2 x half> @llvm.riscv.vfmacc.nxv2f16.f16(
<vscale x 2 x half>, <vscale x 2 x half>,
half, half,
<vscale x 2 x half>, <vscale x 2 x half>,
iXLen, iXLen, iXLen, iXLen);
iXLen);
define <vscale x 2 x half> @intrinsic_vfmacc_vf_nxv2f16_f16_nxv2f16(<vscale x 2 x half> %0, half %1, <vscale x 2 x half> %2, iXLen %3) nounwind { define <vscale x 2 x half> @intrinsic_vfmacc_vf_nxv2f16_f16_nxv2f16(<vscale x 2 x half> %0, half %1, <vscale x 2 x half> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfmacc_vf_nxv2f16_f16_nxv2f16: ; CHECK-LABEL: intrinsic_vfmacc_vf_nxv2f16_f16_nxv2f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, ma ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, ma
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfmacc.vf v8, fa0, v9 ; CHECK-NEXT: vfmacc.vf v8, fa0, v9
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x half> @llvm.riscv.vfmacc.nxv2f16.f16( %a = call <vscale x 2 x half> @llvm.riscv.vfmacc.nxv2f16.f16(
<vscale x 2 x half> %0, <vscale x 2 x half> %0,
half %1, half %1,
<vscale x 2 x half> %2, <vscale x 2 x half> %2,
iXLen %3, iXLen 0) iXLen 0, iXLen %3, iXLen 0)
ret <vscale x 2 x half> %a ret <vscale x 2 x half> %a
} }
declare <vscale x 2 x half> @llvm.riscv.vfmacc.mask.nxv2f16.f16( declare <vscale x 2 x half> @llvm.riscv.vfmacc.mask.nxv2f16.f16(
<vscale x 2 x half>, <vscale x 2 x half>,
half, half,
<vscale x 2 x half>, <vscale x 2 x half>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
iXLen, iXLen); iXLen, iXLen, iXLen);
define <vscale x 2 x half> @intrinsic_vfmacc_mask_vf_nxv2f16_f16_nxv2f16(<vscale x 2 x half> %0, half %1, <vscale x 2 x half> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind { define <vscale x 2 x half> @intrinsic_vfmacc_mask_vf_nxv2f16_f16_nxv2f16(<vscale x 2 x half> %0, half %1, <vscale x 2 x half> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfmacc_mask_vf_nxv2f16_f16_nxv2f16: ; CHECK-LABEL: intrinsic_vfmacc_mask_vf_nxv2f16_f16_nxv2f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfmacc.vf v8, fa0, v9, v0.t ; CHECK-NEXT: vfmacc.vf v8, fa0, v9, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x half> @llvm.riscv.vfmacc.mask.nxv2f16.f16( %a = call <vscale x 2 x half> @llvm.riscv.vfmacc.mask.nxv2f16.f16(
<vscale x 2 x half> %0, <vscale x 2 x half> %0,
half %1, half %1,
<vscale x 2 x half> %2, <vscale x 2 x half> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
iXLen %4, iXLen 0) iXLen 0, iXLen %4, iXLen 0)
ret <vscale x 2 x half> %a ret <vscale x 2 x half> %a
} }
declare <vscale x 4 x half> @llvm.riscv.vfmacc.nxv4f16.f16( declare <vscale x 4 x half> @llvm.riscv.vfmacc.nxv4f16.f16(
<vscale x 4 x half>, <vscale x 4 x half>,
half, half,
<vscale x 4 x half>, <vscale x 4 x half>,
iXLen, iXLen, iXLen, iXLen);
iXLen);
define <vscale x 4 x half> @intrinsic_vfmacc_vf_nxv4f16_f16_nxv4f16(<vscale x 4 x half> %0, half %1, <vscale x 4 x half> %2, iXLen %3) nounwind { define <vscale x 4 x half> @intrinsic_vfmacc_vf_nxv4f16_f16_nxv4f16(<vscale x 4 x half> %0, half %1, <vscale x 4 x half> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfmacc_vf_nxv4f16_f16_nxv4f16: ; CHECK-LABEL: intrinsic_vfmacc_vf_nxv4f16_f16_nxv4f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, ma ; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, ma
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfmacc.vf v8, fa0, v9 ; CHECK-NEXT: vfmacc.vf v8, fa0, v9
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x half> @llvm.riscv.vfmacc.nxv4f16.f16( %a = call <vscale x 4 x half> @llvm.riscv.vfmacc.nxv4f16.f16(
<vscale x 4 x half> %0, <vscale x 4 x half> %0,
half %1, half %1,
<vscale x 4 x half> %2, <vscale x 4 x half> %2,
iXLen %3, iXLen 0) iXLen 0, iXLen %3, iXLen 0)
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 4 x half> @llvm.riscv.vfmacc.mask.nxv4f16.f16( declare <vscale x 4 x half> @llvm.riscv.vfmacc.mask.nxv4f16.f16(
<vscale x 4 x half>, <vscale x 4 x half>,
half, half,
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
iXLen, iXLen); iXLen, iXLen, iXLen);
define <vscale x 4 x half> @intrinsic_vfmacc_mask_vf_nxv4f16_f16_nxv4f16(<vscale x 4 x half> %0, half %1, <vscale x 4 x half> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind { define <vscale x 4 x half> @intrinsic_vfmacc_mask_vf_nxv4f16_f16_nxv4f16(<vscale x 4 x half> %0, half %1, <vscale x 4 x half> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfmacc_mask_vf_nxv4f16_f16_nxv4f16: ; CHECK-LABEL: intrinsic_vfmacc_mask_vf_nxv4f16_f16_nxv4f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfmacc.vf v8, fa0, v9, v0.t ; CHECK-NEXT: vfmacc.vf v8, fa0, v9, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x half> @llvm.riscv.vfmacc.mask.nxv4f16.f16( %a = call <vscale x 4 x half> @llvm.riscv.vfmacc.mask.nxv4f16.f16(
<vscale x 4 x half> %0, <vscale x 4 x half> %0,
half %1, half %1,
<vscale x 4 x half> %2, <vscale x 4 x half> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
iXLen %4, iXLen 0) iXLen 0, iXLen %4, iXLen 0)
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 8 x half> @llvm.riscv.vfmacc.nxv8f16.f16( declare <vscale x 8 x half> @llvm.riscv.vfmacc.nxv8f16.f16(
<vscale x 8 x half>, <vscale x 8 x half>,
half, half,
<vscale x 8 x half>, <vscale x 8 x half>,
iXLen, iXLen, iXLen, iXLen);
iXLen);
define <vscale x 8 x half> @intrinsic_vfmacc_vf_nxv8f16_f16_nxv8f16(<vscale x 8 x half> %0, half %1, <vscale x 8 x half> %2, iXLen %3) nounwind { define <vscale x 8 x half> @intrinsic_vfmacc_vf_nxv8f16_f16_nxv8f16(<vscale x 8 x half> %0, half %1, <vscale x 8 x half> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfmacc_vf_nxv8f16_f16_nxv8f16: ; CHECK-LABEL: intrinsic_vfmacc_vf_nxv8f16_f16_nxv8f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, ma ; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, ma
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfmacc.vf v8, fa0, v10 ; CHECK-NEXT: vfmacc.vf v8, fa0, v10
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x half> @llvm.riscv.vfmacc.nxv8f16.f16( %a = call <vscale x 8 x half> @llvm.riscv.vfmacc.nxv8f16.f16(
<vscale x 8 x half> %0, <vscale x 8 x half> %0,
half %1, half %1,
<vscale x 8 x half> %2, <vscale x 8 x half> %2,
iXLen %3, iXLen 0) iXLen 0, iXLen %3, iXLen 0)
ret <vscale x 8 x half> %a ret <vscale x 8 x half> %a
} }
declare <vscale x 8 x half> @llvm.riscv.vfmacc.mask.nxv8f16.f16( declare <vscale x 8 x half> @llvm.riscv.vfmacc.mask.nxv8f16.f16(
<vscale x 8 x half>, <vscale x 8 x half>,
half, half,
<vscale x 8 x half>, <vscale x 8 x half>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
iXLen, iXLen); iXLen, iXLen, iXLen);
define <vscale x 8 x half> @intrinsic_vfmacc_mask_vf_nxv8f16_f16_nxv8f16(<vscale x 8 x half> %0, half %1, <vscale x 8 x half> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind { define <vscale x 8 x half> @intrinsic_vfmacc_mask_vf_nxv8f16_f16_nxv8f16(<vscale x 8 x half> %0, half %1, <vscale x 8 x half> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfmacc_mask_vf_nxv8f16_f16_nxv8f16: ; CHECK-LABEL: intrinsic_vfmacc_mask_vf_nxv8f16_f16_nxv8f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, mu
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfmacc.vf v8, fa0, v10, v0.t ; CHECK-NEXT: vfmacc.vf v8, fa0, v10, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x half> @llvm.riscv.vfmacc.mask.nxv8f16.f16( %a = call <vscale x 8 x half> @llvm.riscv.vfmacc.mask.nxv8f16.f16(
<vscale x 8 x half> %0, <vscale x 8 x half> %0,
half %1, half %1,
<vscale x 8 x half> %2, <vscale x 8 x half> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
iXLen %4, iXLen 0) iXLen 0, iXLen %4, iXLen 0)
ret <vscale x 8 x half> %a ret <vscale x 8 x half> %a
} }
declare <vscale x 16 x half> @llvm.riscv.vfmacc.nxv16f16.f16( declare <vscale x 16 x half> @llvm.riscv.vfmacc.nxv16f16.f16(
<vscale x 16 x half>, <vscale x 16 x half>,
half, half,
<vscale x 16 x half>, <vscale x 16 x half>,
iXLen, iXLen, iXLen, iXLen);
iXLen);
define <vscale x 16 x half> @intrinsic_vfmacc_vf_nxv16f16_f16_nxv16f16(<vscale x 16 x half> %0, half %1, <vscale x 16 x half> %2, iXLen %3) nounwind { define <vscale x 16 x half> @intrinsic_vfmacc_vf_nxv16f16_f16_nxv16f16(<vscale x 16 x half> %0, half %1, <vscale x 16 x half> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfmacc_vf_nxv16f16_f16_nxv16f16: ; CHECK-LABEL: intrinsic_vfmacc_vf_nxv16f16_f16_nxv16f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, ma ; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, ma
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfmacc.vf v8, fa0, v12 ; CHECK-NEXT: vfmacc.vf v8, fa0, v12
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x half> @llvm.riscv.vfmacc.nxv16f16.f16( %a = call <vscale x 16 x half> @llvm.riscv.vfmacc.nxv16f16.f16(
<vscale x 16 x half> %0, <vscale x 16 x half> %0,
half %1, half %1,
<vscale x 16 x half> %2, <vscale x 16 x half> %2,
iXLen %3, iXLen 0) iXLen 0, iXLen %3, iXLen 0)
ret <vscale x 16 x half> %a ret <vscale x 16 x half> %a
} }
declare <vscale x 16 x half> @llvm.riscv.vfmacc.mask.nxv16f16.f16( declare <vscale x 16 x half> @llvm.riscv.vfmacc.mask.nxv16f16.f16(
<vscale x 16 x half>, <vscale x 16 x half>,
half, half,
<vscale x 16 x half>, <vscale x 16 x half>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
iXLen, iXLen); iXLen, iXLen, iXLen);
define <vscale x 16 x half> @intrinsic_vfmacc_mask_vf_nxv16f16_f16_nxv16f16(<vscale x 16 x half> %0, half %1, <vscale x 16 x half> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind { define <vscale x 16 x half> @intrinsic_vfmacc_mask_vf_nxv16f16_f16_nxv16f16(<vscale x 16 x half> %0, half %1, <vscale x 16 x half> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfmacc_mask_vf_nxv16f16_f16_nxv16f16: ; CHECK-LABEL: intrinsic_vfmacc_mask_vf_nxv16f16_f16_nxv16f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfmacc.vf v8, fa0, v12, v0.t ; CHECK-NEXT: vfmacc.vf v8, fa0, v12, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x half> @llvm.riscv.vfmacc.mask.nxv16f16.f16( %a = call <vscale x 16 x half> @llvm.riscv.vfmacc.mask.nxv16f16.f16(
<vscale x 16 x half> %0, <vscale x 16 x half> %0,
half %1, half %1,
<vscale x 16 x half> %2, <vscale x 16 x half> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
iXLen %4, iXLen 0) iXLen 0, iXLen %4, iXLen 0)
ret <vscale x 16 x half> %a ret <vscale x 16 x half> %a
} }
declare <vscale x 1 x float> @llvm.riscv.vfmacc.nxv1f32.f32( declare <vscale x 1 x float> @llvm.riscv.vfmacc.nxv1f32.f32(
<vscale x 1 x float>, <vscale x 1 x float>,
float, float,
<vscale x 1 x float>, <vscale x 1 x float>,
iXLen, iXLen, iXLen, iXLen);
iXLen);
define <vscale x 1 x float> @intrinsic_vfmacc_vf_nxv1f32_f32_nxv1f32(<vscale x 1 x float> %0, float %1, <vscale x 1 x float> %2, iXLen %3) nounwind { define <vscale x 1 x float> @intrinsic_vfmacc_vf_nxv1f32_f32_nxv1f32(<vscale x 1 x float> %0, float %1, <vscale x 1 x float> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfmacc_vf_nxv1f32_f32_nxv1f32: ; CHECK-LABEL: intrinsic_vfmacc_vf_nxv1f32_f32_nxv1f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, ma ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, ma
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfmacc.vf v8, fa0, v9 ; CHECK-NEXT: vfmacc.vf v8, fa0, v9
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x float> @llvm.riscv.vfmacc.nxv1f32.f32( %a = call <vscale x 1 x float> @llvm.riscv.vfmacc.nxv1f32.f32(
<vscale x 1 x float> %0, <vscale x 1 x float> %0,
float %1, float %1,
<vscale x 1 x float> %2, <vscale x 1 x float> %2,
iXLen %3, iXLen 0) iXLen 0, iXLen %3, iXLen 0)
ret <vscale x 1 x float> %a ret <vscale x 1 x float> %a
} }
declare <vscale x 1 x float> @llvm.riscv.vfmacc.mask.nxv1f32.f32( declare <vscale x 1 x float> @llvm.riscv.vfmacc.mask.nxv1f32.f32(
<vscale x 1 x float>, <vscale x 1 x float>,
float, float,
<vscale x 1 x float>, <vscale x 1 x float>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
iXLen, iXLen); iXLen, iXLen, iXLen);
define <vscale x 1 x float> @intrinsic_vfmacc_mask_vf_nxv1f32_f32_nxv1f32(<vscale x 1 x float> %0, float %1, <vscale x 1 x float> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind { define <vscale x 1 x float> @intrinsic_vfmacc_mask_vf_nxv1f32_f32_nxv1f32(<vscale x 1 x float> %0, float %1, <vscale x 1 x float> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfmacc_mask_vf_nxv1f32_f32_nxv1f32: ; CHECK-LABEL: intrinsic_vfmacc_mask_vf_nxv1f32_f32_nxv1f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfmacc.vf v8, fa0, v9, v0.t ; CHECK-NEXT: vfmacc.vf v8, fa0, v9, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x float> @llvm.riscv.vfmacc.mask.nxv1f32.f32( %a = call <vscale x 1 x float> @llvm.riscv.vfmacc.mask.nxv1f32.f32(
<vscale x 1 x float> %0, <vscale x 1 x float> %0,
float %1, float %1,
<vscale x 1 x float> %2, <vscale x 1 x float> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
iXLen %4, iXLen 0) iXLen 0, iXLen %4, iXLen 0)
ret <vscale x 1 x float> %a ret <vscale x 1 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vfmacc.nxv2f32.f32( declare <vscale x 2 x float> @llvm.riscv.vfmacc.nxv2f32.f32(
<vscale x 2 x float>, <vscale x 2 x float>,
float, float,
<vscale x 2 x float>, <vscale x 2 x float>,
iXLen, iXLen, iXLen, iXLen);
iXLen);
define <vscale x 2 x float> @intrinsic_vfmacc_vf_nxv2f32_f32_nxv2f32(<vscale x 2 x float> %0, float %1, <vscale x 2 x float> %2, iXLen %3) nounwind { define <vscale x 2 x float> @intrinsic_vfmacc_vf_nxv2f32_f32_nxv2f32(<vscale x 2 x float> %0, float %1, <vscale x 2 x float> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfmacc_vf_nxv2f32_f32_nxv2f32: ; CHECK-LABEL: intrinsic_vfmacc_vf_nxv2f32_f32_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, ma ; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, ma
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfmacc.vf v8, fa0, v9 ; CHECK-NEXT: vfmacc.vf v8, fa0, v9
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfmacc.nxv2f32.f32( %a = call <vscale x 2 x float> @llvm.riscv.vfmacc.nxv2f32.f32(
<vscale x 2 x float> %0, <vscale x 2 x float> %0,
float %1, float %1,
<vscale x 2 x float> %2, <vscale x 2 x float> %2,
iXLen %3, iXLen 0) iXLen 0, iXLen %3, iXLen 0)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vfmacc.mask.nxv2f32.f32( declare <vscale x 2 x float> @llvm.riscv.vfmacc.mask.nxv2f32.f32(
<vscale x 2 x float>, <vscale x 2 x float>,
float, float,
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
iXLen, iXLen); iXLen, iXLen, iXLen);
define <vscale x 2 x float> @intrinsic_vfmacc_mask_vf_nxv2f32_f32_nxv2f32(<vscale x 2 x float> %0, float %1, <vscale x 2 x float> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind { define <vscale x 2 x float> @intrinsic_vfmacc_mask_vf_nxv2f32_f32_nxv2f32(<vscale x 2 x float> %0, float %1, <vscale x 2 x float> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfmacc_mask_vf_nxv2f32_f32_nxv2f32: ; CHECK-LABEL: intrinsic_vfmacc_mask_vf_nxv2f32_f32_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfmacc.vf v8, fa0, v9, v0.t ; CHECK-NEXT: vfmacc.vf v8, fa0, v9, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfmacc.mask.nxv2f32.f32( %a = call <vscale x 2 x float> @llvm.riscv.vfmacc.mask.nxv2f32.f32(
<vscale x 2 x float> %0, <vscale x 2 x float> %0,
float %1, float %1,
<vscale x 2 x float> %2, <vscale x 2 x float> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
iXLen %4, iXLen 0) iXLen 0, iXLen %4, iXLen 0)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 4 x float> @llvm.riscv.vfmacc.nxv4f32.f32( declare <vscale x 4 x float> @llvm.riscv.vfmacc.nxv4f32.f32(
<vscale x 4 x float>, <vscale x 4 x float>,
float, float,
<vscale x 4 x float>, <vscale x 4 x float>,
iXLen, iXLen, iXLen, iXLen);
iXLen);
define <vscale x 4 x float> @intrinsic_vfmacc_vf_nxv4f32_f32_nxv4f32(<vscale x 4 x float> %0, float %1, <vscale x 4 x float> %2, iXLen %3) nounwind { define <vscale x 4 x float> @intrinsic_vfmacc_vf_nxv4f32_f32_nxv4f32(<vscale x 4 x float> %0, float %1, <vscale x 4 x float> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfmacc_vf_nxv4f32_f32_nxv4f32: ; CHECK-LABEL: intrinsic_vfmacc_vf_nxv4f32_f32_nxv4f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, ma ; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, ma
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfmacc.vf v8, fa0, v10 ; CHECK-NEXT: vfmacc.vf v8, fa0, v10
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x float> @llvm.riscv.vfmacc.nxv4f32.f32( %a = call <vscale x 4 x float> @llvm.riscv.vfmacc.nxv4f32.f32(
<vscale x 4 x float> %0, <vscale x 4 x float> %0,
float %1, float %1,
<vscale x 4 x float> %2, <vscale x 4 x float> %2,
iXLen %3, iXLen 0) iXLen 0, iXLen %3, iXLen 0)
ret <vscale x 4 x float> %a ret <vscale x 4 x float> %a
} }
declare <vscale x 4 x float> @llvm.riscv.vfmacc.mask.nxv4f32.f32( declare <vscale x 4 x float> @llvm.riscv.vfmacc.mask.nxv4f32.f32(
<vscale x 4 x float>, <vscale x 4 x float>,
float, float,
<vscale x 4 x float>, <vscale x 4 x float>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
iXLen, iXLen); iXLen, iXLen, iXLen);
define <vscale x 4 x float> @intrinsic_vfmacc_mask_vf_nxv4f32_f32_nxv4f32(<vscale x 4 x float> %0, float %1, <vscale x 4 x float> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind { define <vscale x 4 x float> @intrinsic_vfmacc_mask_vf_nxv4f32_f32_nxv4f32(<vscale x 4 x float> %0, float %1, <vscale x 4 x float> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfmacc_mask_vf_nxv4f32_f32_nxv4f32: ; CHECK-LABEL: intrinsic_vfmacc_mask_vf_nxv4f32_f32_nxv4f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfmacc.vf v8, fa0, v10, v0.t ; CHECK-NEXT: vfmacc.vf v8, fa0, v10, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x float> @llvm.riscv.vfmacc.mask.nxv4f32.f32( %a = call <vscale x 4 x float> @llvm.riscv.vfmacc.mask.nxv4f32.f32(
<vscale x 4 x float> %0, <vscale x 4 x float> %0,
float %1, float %1,
<vscale x 4 x float> %2, <vscale x 4 x float> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
iXLen %4, iXLen 0) iXLen 0, iXLen %4, iXLen 0)
ret <vscale x 4 x float> %a ret <vscale x 4 x float> %a
} }
declare <vscale x 8 x float> @llvm.riscv.vfmacc.nxv8f32.f32( declare <vscale x 8 x float> @llvm.riscv.vfmacc.nxv8f32.f32(
<vscale x 8 x float>, <vscale x 8 x float>,
float, float,
<vscale x 8 x float>, <vscale x 8 x float>,
iXLen, iXLen, iXLen, iXLen);
iXLen);
define <vscale x 8 x float> @intrinsic_vfmacc_vf_nxv8f32_f32_nxv8f32(<vscale x 8 x float> %0, float %1, <vscale x 8 x float> %2, iXLen %3) nounwind { define <vscale x 8 x float> @intrinsic_vfmacc_vf_nxv8f32_f32_nxv8f32(<vscale x 8 x float> %0, float %1, <vscale x 8 x float> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfmacc_vf_nxv8f32_f32_nxv8f32: ; CHECK-LABEL: intrinsic_vfmacc_vf_nxv8f32_f32_nxv8f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, ma ; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, ma
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfmacc.vf v8, fa0, v12 ; CHECK-NEXT: vfmacc.vf v8, fa0, v12
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x float> @llvm.riscv.vfmacc.nxv8f32.f32( %a = call <vscale x 8 x float> @llvm.riscv.vfmacc.nxv8f32.f32(
<vscale x 8 x float> %0, <vscale x 8 x float> %0,
float %1, float %1,
<vscale x 8 x float> %2, <vscale x 8 x float> %2,
iXLen %3, iXLen 0) iXLen 0, iXLen %3, iXLen 0)
ret <vscale x 8 x float> %a ret <vscale x 8 x float> %a
} }
declare <vscale x 8 x float> @llvm.riscv.vfmacc.mask.nxv8f32.f32( declare <vscale x 8 x float> @llvm.riscv.vfmacc.mask.nxv8f32.f32(
<vscale x 8 x float>, <vscale x 8 x float>,
float, float,
<vscale x 8 x float>, <vscale x 8 x float>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
iXLen, iXLen); iXLen, iXLen, iXLen);
define <vscale x 8 x float> @intrinsic_vfmacc_mask_vf_nxv8f32_f32_nxv8f32(<vscale x 8 x float> %0, float %1, <vscale x 8 x float> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind { define <vscale x 8 x float> @intrinsic_vfmacc_mask_vf_nxv8f32_f32_nxv8f32(<vscale x 8 x float> %0, float %1, <vscale x 8 x float> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfmacc_mask_vf_nxv8f32_f32_nxv8f32: ; CHECK-LABEL: intrinsic_vfmacc_mask_vf_nxv8f32_f32_nxv8f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfmacc.vf v8, fa0, v12, v0.t ; CHECK-NEXT: vfmacc.vf v8, fa0, v12, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x float> @llvm.riscv.vfmacc.mask.nxv8f32.f32( %a = call <vscale x 8 x float> @llvm.riscv.vfmacc.mask.nxv8f32.f32(
<vscale x 8 x float> %0, <vscale x 8 x float> %0,
float %1, float %1,
<vscale x 8 x float> %2, <vscale x 8 x float> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
iXLen %4, iXLen 0) iXLen 0, iXLen %4, iXLen 0)
ret <vscale x 8 x float> %a ret <vscale x 8 x float> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vfmacc.nxv1f64.f64( declare <vscale x 1 x double> @llvm.riscv.vfmacc.nxv1f64.f64(
<vscale x 1 x double>, <vscale x 1 x double>,
double, double,
<vscale x 1 x double>, <vscale x 1 x double>,
iXLen, iXLen, iXLen, iXLen);
iXLen);
define <vscale x 1 x double> @intrinsic_vfmacc_vf_nxv1f64_f64_nxv1f64(<vscale x 1 x double> %0, double %1, <vscale x 1 x double> %2, iXLen %3) nounwind { define <vscale x 1 x double> @intrinsic_vfmacc_vf_nxv1f64_f64_nxv1f64(<vscale x 1 x double> %0, double %1, <vscale x 1 x double> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfmacc_vf_nxv1f64_f64_nxv1f64: ; CHECK-LABEL: intrinsic_vfmacc_vf_nxv1f64_f64_nxv1f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, ma ; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, ma
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfmacc.vf v8, fa0, v9 ; CHECK-NEXT: vfmacc.vf v8, fa0, v9
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfmacc.nxv1f64.f64( %a = call <vscale x 1 x double> @llvm.riscv.vfmacc.nxv1f64.f64(
<vscale x 1 x double> %0, <vscale x 1 x double> %0,
double %1, double %1,
<vscale x 1 x double> %2, <vscale x 1 x double> %2,
iXLen %3, iXLen 0) iXLen 0, iXLen %3, iXLen 0)
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vfmacc.mask.nxv1f64.f64( declare <vscale x 1 x double> @llvm.riscv.vfmacc.mask.nxv1f64.f64(
<vscale x 1 x double>, <vscale x 1 x double>,
double, double,
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
iXLen, iXLen); iXLen, iXLen, iXLen);
define <vscale x 1 x double> @intrinsic_vfmacc_mask_vf_nxv1f64_f64_nxv1f64(<vscale x 1 x double> %0, double %1, <vscale x 1 x double> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind { define <vscale x 1 x double> @intrinsic_vfmacc_mask_vf_nxv1f64_f64_nxv1f64(<vscale x 1 x double> %0, double %1, <vscale x 1 x double> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfmacc_mask_vf_nxv1f64_f64_nxv1f64: ; CHECK-LABEL: intrinsic_vfmacc_mask_vf_nxv1f64_f64_nxv1f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, mu
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfmacc.vf v8, fa0, v9, v0.t ; CHECK-NEXT: vfmacc.vf v8, fa0, v9, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfmacc.mask.nxv1f64.f64( %a = call <vscale x 1 x double> @llvm.riscv.vfmacc.mask.nxv1f64.f64(
<vscale x 1 x double> %0, <vscale x 1 x double> %0,
double %1, double %1,
<vscale x 1 x double> %2, <vscale x 1 x double> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
iXLen %4, iXLen 0) iXLen 0, iXLen %4, iXLen 0)
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 2 x double> @llvm.riscv.vfmacc.nxv2f64.f64( declare <vscale x 2 x double> @llvm.riscv.vfmacc.nxv2f64.f64(
<vscale x 2 x double>, <vscale x 2 x double>,
double, double,
<vscale x 2 x double>, <vscale x 2 x double>,
iXLen, iXLen, iXLen, iXLen);
iXLen);
define <vscale x 2 x double> @intrinsic_vfmacc_vf_nxv2f64_f64_nxv2f64(<vscale x 2 x double> %0, double %1, <vscale x 2 x double> %2, iXLen %3) nounwind { define <vscale x 2 x double> @intrinsic_vfmacc_vf_nxv2f64_f64_nxv2f64(<vscale x 2 x double> %0, double %1, <vscale x 2 x double> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfmacc_vf_nxv2f64_f64_nxv2f64: ; CHECK-LABEL: intrinsic_vfmacc_vf_nxv2f64_f64_nxv2f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, ma ; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, ma
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfmacc.vf v8, fa0, v10 ; CHECK-NEXT: vfmacc.vf v8, fa0, v10
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x double> @llvm.riscv.vfmacc.nxv2f64.f64( %a = call <vscale x 2 x double> @llvm.riscv.vfmacc.nxv2f64.f64(
<vscale x 2 x double> %0, <vscale x 2 x double> %0,
double %1, double %1,
<vscale x 2 x double> %2, <vscale x 2 x double> %2,
iXLen %3, iXLen 0) iXLen 0, iXLen %3, iXLen 0)
ret <vscale x 2 x double> %a ret <vscale x 2 x double> %a
} }
declare <vscale x 2 x double> @llvm.riscv.vfmacc.mask.nxv2f64.f64( declare <vscale x 2 x double> @llvm.riscv.vfmacc.mask.nxv2f64.f64(
<vscale x 2 x double>, <vscale x 2 x double>,
double, double,
<vscale x 2 x double>, <vscale x 2 x double>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
iXLen, iXLen); iXLen, iXLen, iXLen);
define <vscale x 2 x double> @intrinsic_vfmacc_mask_vf_nxv2f64_f64_nxv2f64(<vscale x 2 x double> %0, double %1, <vscale x 2 x double> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind { define <vscale x 2 x double> @intrinsic_vfmacc_mask_vf_nxv2f64_f64_nxv2f64(<vscale x 2 x double> %0, double %1, <vscale x 2 x double> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfmacc_mask_vf_nxv2f64_f64_nxv2f64: ; CHECK-LABEL: intrinsic_vfmacc_mask_vf_nxv2f64_f64_nxv2f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, mu
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfmacc.vf v8, fa0, v10, v0.t ; CHECK-NEXT: vfmacc.vf v8, fa0, v10, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x double> @llvm.riscv.vfmacc.mask.nxv2f64.f64( %a = call <vscale x 2 x double> @llvm.riscv.vfmacc.mask.nxv2f64.f64(
<vscale x 2 x double> %0, <vscale x 2 x double> %0,
double %1, double %1,
<vscale x 2 x double> %2, <vscale x 2 x double> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
iXLen %4, iXLen 0) iXLen 0, iXLen %4, iXLen 0)
ret <vscale x 2 x double> %a ret <vscale x 2 x double> %a
} }
declare <vscale x 4 x double> @llvm.riscv.vfmacc.nxv4f64.f64( declare <vscale x 4 x double> @llvm.riscv.vfmacc.nxv4f64.f64(
<vscale x 4 x double>, <vscale x 4 x double>,
double, double,
<vscale x 4 x double>, <vscale x 4 x double>,
iXLen, iXLen, iXLen, iXLen);
iXLen);
define <vscale x 4 x double> @intrinsic_vfmacc_vf_nxv4f64_f64_nxv4f64(<vscale x 4 x double> %0, double %1, <vscale x 4 x double> %2, iXLen %3) nounwind { define <vscale x 4 x double> @intrinsic_vfmacc_vf_nxv4f64_f64_nxv4f64(<vscale x 4 x double> %0, double %1, <vscale x 4 x double> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfmacc_vf_nxv4f64_f64_nxv4f64: ; CHECK-LABEL: intrinsic_vfmacc_vf_nxv4f64_f64_nxv4f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, ma ; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, ma
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfmacc.vf v8, fa0, v12 ; CHECK-NEXT: vfmacc.vf v8, fa0, v12
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x double> @llvm.riscv.vfmacc.nxv4f64.f64( %a = call <vscale x 4 x double> @llvm.riscv.vfmacc.nxv4f64.f64(
<vscale x 4 x double> %0, <vscale x 4 x double> %0,
double %1, double %1,
<vscale x 4 x double> %2, <vscale x 4 x double> %2,
iXLen %3, iXLen 0) iXLen 0, iXLen %3, iXLen 0)
ret <vscale x 4 x double> %a ret <vscale x 4 x double> %a
} }
declare <vscale x 4 x double> @llvm.riscv.vfmacc.mask.nxv4f64.f64( declare <vscale x 4 x double> @llvm.riscv.vfmacc.mask.nxv4f64.f64(
<vscale x 4 x double>, <vscale x 4 x double>,
double, double,
<vscale x 4 x double>, <vscale x 4 x double>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
iXLen, iXLen); iXLen, iXLen, iXLen);
define <vscale x 4 x double> @intrinsic_vfmacc_mask_vf_nxv4f64_f64_nxv4f64(<vscale x 4 x double> %0, double %1, <vscale x 4 x double> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind { define <vscale x 4 x double> @intrinsic_vfmacc_mask_vf_nxv4f64_f64_nxv4f64(<vscale x 4 x double> %0, double %1, <vscale x 4 x double> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfmacc_mask_vf_nxv4f64_f64_nxv4f64: ; CHECK-LABEL: intrinsic_vfmacc_mask_vf_nxv4f64_f64_nxv4f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, mu
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfmacc.vf v8, fa0, v12, v0.t ; CHECK-NEXT: vfmacc.vf v8, fa0, v12, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x double> @llvm.riscv.vfmacc.mask.nxv4f64.f64( %a = call <vscale x 4 x double> @llvm.riscv.vfmacc.mask.nxv4f64.f64(
<vscale x 4 x double> %0, <vscale x 4 x double> %0,
double %1, double %1,
<vscale x 4 x double> %2, <vscale x 4 x double> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
iXLen %4, iXLen 0) iXLen 0, iXLen %4, iXLen 0)
ret <vscale x 4 x double> %a ret <vscale x 4 x double> %a
} }

llvm/test/CodeGen/RISCV/rvv/vfmadd.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zfh,+experimental-zvfh \ ; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zfh,+experimental-zvfh \
; RUN: -verify-machineinstrs -target-abi=ilp32d | FileCheck %s ; RUN: -verify-machineinstrs -target-abi=ilp32d | FileCheck %s
; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zfh,+experimental-zvfh \ ; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zfh,+experimental-zvfh \
; RUN: -verify-machineinstrs -target-abi=lp64d | FileCheck %s ; RUN: -verify-machineinstrs -target-abi=lp64d | FileCheck %s
declare <vscale x 1 x half> @llvm.riscv.vfmadd.nxv1f16.nxv1f16( declare <vscale x 1 x half> @llvm.riscv.vfmadd.nxv1f16.nxv1f16(
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x half>, <vscale x 1 x half>,
iXLen, iXLen, iXLen, iXLen);
iXLen);
define <vscale x 1 x half> @intrinsic_vfmadd_vv_nxv1f16_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, iXLen %3) nounwind { define <vscale x 1 x half> @intrinsic_vfmadd_vv_nxv1f16_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfmadd_vv_nxv1f16_nxv1f16_nxv1f16: ; CHECK-LABEL: intrinsic_vfmadd_vv_nxv1f16_nxv1f16_nxv1f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, ma ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, ma
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfmadd.vv v8, v9, v10 ; CHECK-NEXT: vfmadd.vv v8, v9, v10
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x half> @llvm.riscv.vfmadd.nxv1f16.nxv1f16( %a = call <vscale x 1 x half> @llvm.riscv.vfmadd.nxv1f16.nxv1f16(
<vscale x 1 x half> %0, <vscale x 1 x half> %0,
<vscale x 1 x half> %1, <vscale x 1 x half> %1,
<vscale x 1 x half> %2, <vscale x 1 x half> %2,
iXLen %3, iXLen 0) iXLen 0, iXLen %3, iXLen 0)
ret <vscale x 1 x half> %a ret <vscale x 1 x half> %a
} }
declare <vscale x 1 x half> @llvm.riscv.vfmadd.mask.nxv1f16.nxv1f16( declare <vscale x 1 x half> @llvm.riscv.vfmadd.mask.nxv1f16.nxv1f16(
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
iXLen, iXLen); iXLen, iXLen, iXLen);
define <vscale x 1 x half> @intrinsic_vfmadd_mask_vv_nxv1f16_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind { define <vscale x 1 x half> @intrinsic_vfmadd_mask_vv_nxv1f16_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfmadd_mask_vv_nxv1f16_nxv1f16_nxv1f16: ; CHECK-LABEL: intrinsic_vfmadd_mask_vv_nxv1f16_nxv1f16_nxv1f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfmadd.vv v8, v9, v10, v0.t ; CHECK-NEXT: vfmadd.vv v8, v9, v10, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x half> @llvm.riscv.vfmadd.mask.nxv1f16.nxv1f16( %a = call <vscale x 1 x half> @llvm.riscv.vfmadd.mask.nxv1f16.nxv1f16(
<vscale x 1 x half> %0, <vscale x 1 x half> %0,
<vscale x 1 x half> %1, <vscale x 1 x half> %1,
<vscale x 1 x half> %2, <vscale x 1 x half> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
iXLen %4, iXLen 0); iXLen 0, iXLen %4, iXLen 0);
ret <vscale x 1 x half> %a ret <vscale x 1 x half> %a
} }
declare <vscale x 2 x half> @llvm.riscv.vfmadd.nxv2f16.nxv2f16( declare <vscale x 2 x half> @llvm.riscv.vfmadd.nxv2f16.nxv2f16(
<vscale x 2 x half>, <vscale x 2 x half>,
<vscale x 2 x half>, <vscale x 2 x half>,
<vscale x 2 x half>, <vscale x 2 x half>,
iXLen, iXLen, iXLen, iXLen);
iXLen);
define <vscale x 2 x half> @intrinsic_vfmadd_vv_nxv2f16_nxv2f16_nxv2f16(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, iXLen %3) nounwind { define <vscale x 2 x half> @intrinsic_vfmadd_vv_nxv2f16_nxv2f16_nxv2f16(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfmadd_vv_nxv2f16_nxv2f16_nxv2f16: ; CHECK-LABEL: intrinsic_vfmadd_vv_nxv2f16_nxv2f16_nxv2f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, ma ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, ma
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfmadd.vv v8, v9, v10 ; CHECK-NEXT: vfmadd.vv v8, v9, v10
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x half> @llvm.riscv.vfmadd.nxv2f16.nxv2f16( %a = call <vscale x 2 x half> @llvm.riscv.vfmadd.nxv2f16.nxv2f16(
<vscale x 2 x half> %0, <vscale x 2 x half> %0,
<vscale x 2 x half> %1, <vscale x 2 x half> %1,
<vscale x 2 x half> %2, <vscale x 2 x half> %2,
iXLen %3, iXLen 0) iXLen 0, iXLen %3, iXLen 0)
ret <vscale x 2 x half> %a ret <vscale x 2 x half> %a
} }
declare <vscale x 2 x half> @llvm.riscv.vfmadd.mask.nxv2f16.nxv2f16( declare <vscale x 2 x half> @llvm.riscv.vfmadd.mask.nxv2f16.nxv2f16(
<vscale x 2 x half>, <vscale x 2 x half>,
<vscale x 2 x half>, <vscale x 2 x half>,
<vscale x 2 x half>, <vscale x 2 x half>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
iXLen, iXLen); iXLen, iXLen, iXLen);
define <vscale x 2 x half> @intrinsic_vfmadd_mask_vv_nxv2f16_nxv2f16_nxv2f16(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind { define <vscale x 2 x half> @intrinsic_vfmadd_mask_vv_nxv2f16_nxv2f16_nxv2f16(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfmadd_mask_vv_nxv2f16_nxv2f16_nxv2f16: ; CHECK-LABEL: intrinsic_vfmadd_mask_vv_nxv2f16_nxv2f16_nxv2f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfmadd.vv v8, v9, v10, v0.t ; CHECK-NEXT: vfmadd.vv v8, v9, v10, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x half> @llvm.riscv.vfmadd.mask.nxv2f16.nxv2f16( %a = call <vscale x 2 x half> @llvm.riscv.vfmadd.mask.nxv2f16.nxv2f16(
<vscale x 2 x half> %0, <vscale x 2 x half> %0,
<vscale x 2 x half> %1, <vscale x 2 x half> %1,
<vscale x 2 x half> %2, <vscale x 2 x half> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
iXLen %4, iXLen 0); iXLen 0, iXLen %4, iXLen 0);
ret <vscale x 2 x half> %a ret <vscale x 2 x half> %a
} }
declare <vscale x 4 x half> @llvm.riscv.vfmadd.nxv4f16.nxv4f16( declare <vscale x 4 x half> @llvm.riscv.vfmadd.nxv4f16.nxv4f16(
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 4 x half>, <vscale x 4 x half>,
iXLen, iXLen, iXLen, iXLen);
iXLen);
define <vscale x 4 x half> @intrinsic_vfmadd_vv_nxv4f16_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, iXLen %3) nounwind { define <vscale x 4 x half> @intrinsic_vfmadd_vv_nxv4f16_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfmadd_vv_nxv4f16_nxv4f16_nxv4f16: ; CHECK-LABEL: intrinsic_vfmadd_vv_nxv4f16_nxv4f16_nxv4f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, ma ; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, ma
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfmadd.vv v8, v9, v10 ; CHECK-NEXT: vfmadd.vv v8, v9, v10
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x half> @llvm.riscv.vfmadd.nxv4f16.nxv4f16( %a = call <vscale x 4 x half> @llvm.riscv.vfmadd.nxv4f16.nxv4f16(
<vscale x 4 x half> %0, <vscale x 4 x half> %0,
<vscale x 4 x half> %1, <vscale x 4 x half> %1,
<vscale x 4 x half> %2, <vscale x 4 x half> %2,
iXLen %3, iXLen 0) iXLen 0, iXLen %3, iXLen 0)
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 4 x half> @llvm.riscv.vfmadd.mask.nxv4f16.nxv4f16( declare <vscale x 4 x half> @llvm.riscv.vfmadd.mask.nxv4f16.nxv4f16(
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
iXLen, iXLen); iXLen, iXLen, iXLen);
define <vscale x 4 x half> @intrinsic_vfmadd_mask_vv_nxv4f16_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind { define <vscale x 4 x half> @intrinsic_vfmadd_mask_vv_nxv4f16_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfmadd_mask_vv_nxv4f16_nxv4f16_nxv4f16: ; CHECK-LABEL: intrinsic_vfmadd_mask_vv_nxv4f16_nxv4f16_nxv4f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfmadd.vv v8, v9, v10, v0.t ; CHECK-NEXT: vfmadd.vv v8, v9, v10, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x half> @llvm.riscv.vfmadd.mask.nxv4f16.nxv4f16( %a = call <vscale x 4 x half> @llvm.riscv.vfmadd.mask.nxv4f16.nxv4f16(
<vscale x 4 x half> %0, <vscale x 4 x half> %0,
<vscale x 4 x half> %1, <vscale x 4 x half> %1,
<vscale x 4 x half> %2, <vscale x 4 x half> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
iXLen %4, iXLen 0); iXLen 0, iXLen %4, iXLen 0);
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 8 x half> @llvm.riscv.vfmadd.nxv8f16.nxv8f16( declare <vscale x 8 x half> @llvm.riscv.vfmadd.nxv8f16.nxv8f16(
<vscale x 8 x half>, <vscale x 8 x half>,
<vscale x 8 x half>, <vscale x 8 x half>,
<vscale x 8 x half>, <vscale x 8 x half>,
iXLen, iXLen, iXLen, iXLen);
iXLen);
define <vscale x 8 x half> @intrinsic_vfmadd_vv_nxv8f16_nxv8f16_nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, iXLen %3) nounwind { define <vscale x 8 x half> @intrinsic_vfmadd_vv_nxv8f16_nxv8f16_nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfmadd_vv_nxv8f16_nxv8f16_nxv8f16: ; CHECK-LABEL: intrinsic_vfmadd_vv_nxv8f16_nxv8f16_nxv8f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, ma ; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, ma
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfmadd.vv v8, v10, v12 ; CHECK-NEXT: vfmadd.vv v8, v10, v12
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x half> @llvm.riscv.vfmadd.nxv8f16.nxv8f16( %a = call <vscale x 8 x half> @llvm.riscv.vfmadd.nxv8f16.nxv8f16(
<vscale x 8 x half> %0, <vscale x 8 x half> %0,
<vscale x 8 x half> %1, <vscale x 8 x half> %1,
<vscale x 8 x half> %2, <vscale x 8 x half> %2,
iXLen %3, iXLen 0) iXLen 0, iXLen %3, iXLen 0)
ret <vscale x 8 x half> %a ret <vscale x 8 x half> %a
} }
declare <vscale x 8 x half> @llvm.riscv.vfmadd.mask.nxv8f16.nxv8f16( declare <vscale x 8 x half> @llvm.riscv.vfmadd.mask.nxv8f16.nxv8f16(
<vscale x 8 x half>, <vscale x 8 x half>,
<vscale x 8 x half>, <vscale x 8 x half>,
<vscale x 8 x half>, <vscale x 8 x half>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
iXLen, iXLen); iXLen, iXLen, iXLen);
define <vscale x 8 x half> @intrinsic_vfmadd_mask_vv_nxv8f16_nxv8f16_nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind { define <vscale x 8 x half> @intrinsic_vfmadd_mask_vv_nxv8f16_nxv8f16_nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfmadd_mask_vv_nxv8f16_nxv8f16_nxv8f16: ; CHECK-LABEL: intrinsic_vfmadd_mask_vv_nxv8f16_nxv8f16_nxv8f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, mu
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfmadd.vv v8, v10, v12, v0.t ; CHECK-NEXT: vfmadd.vv v8, v10, v12, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x half> @llvm.riscv.vfmadd.mask.nxv8f16.nxv8f16( %a = call <vscale x 8 x half> @llvm.riscv.vfmadd.mask.nxv8f16.nxv8f16(
<vscale x 8 x half> %0, <vscale x 8 x half> %0,
<vscale x 8 x half> %1, <vscale x 8 x half> %1,
<vscale x 8 x half> %2, <vscale x 8 x half> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
iXLen %4, iXLen 0); iXLen 0, iXLen %4, iXLen 0);
ret <vscale x 8 x half> %a ret <vscale x 8 x half> %a
} }
declare <vscale x 16 x half> @llvm.riscv.vfmadd.nxv16f16.nxv16f16( declare <vscale x 16 x half> @llvm.riscv.vfmadd.nxv16f16.nxv16f16(
<vscale x 16 x half>, <vscale x 16 x half>,
<vscale x 16 x half>, <vscale x 16 x half>,
<vscale x 16 x half>, <vscale x 16 x half>,
iXLen, iXLen, iXLen, iXLen);
iXLen);
define <vscale x 16 x half> @intrinsic_vfmadd_vv_nxv16f16_nxv16f16_nxv16f16(<vscale x 16 x half> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %2, iXLen %3) nounwind { define <vscale x 16 x half> @intrinsic_vfmadd_vv_nxv16f16_nxv16f16_nxv16f16(<vscale x 16 x half> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfmadd_vv_nxv16f16_nxv16f16_nxv16f16: ; CHECK-LABEL: intrinsic_vfmadd_vv_nxv16f16_nxv16f16_nxv16f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, ma ; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, ma
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfmadd.vv v8, v12, v16 ; CHECK-NEXT: vfmadd.vv v8, v12, v16
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x half> @llvm.riscv.vfmadd.nxv16f16.nxv16f16( %a = call <vscale x 16 x half> @llvm.riscv.vfmadd.nxv16f16.nxv16f16(
<vscale x 16 x half> %0, <vscale x 16 x half> %0,
<vscale x 16 x half> %1, <vscale x 16 x half> %1,
<vscale x 16 x half> %2, <vscale x 16 x half> %2,
iXLen %3, iXLen 0) iXLen 0, iXLen %3, iXLen 0)
ret <vscale x 16 x half> %a ret <vscale x 16 x half> %a
} }
declare <vscale x 16 x half> @llvm.riscv.vfmadd.mask.nxv16f16.nxv16f16( declare <vscale x 16 x half> @llvm.riscv.vfmadd.mask.nxv16f16.nxv16f16(
<vscale x 16 x half>, <vscale x 16 x half>,
<vscale x 16 x half>, <vscale x 16 x half>,
<vscale x 16 x half>, <vscale x 16 x half>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
iXLen, iXLen); iXLen, iXLen, iXLen);
define <vscale x 16 x half> @intrinsic_vfmadd_mask_vv_nxv16f16_nxv16f16_nxv16f16(<vscale x 16 x half> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind { define <vscale x 16 x half> @intrinsic_vfmadd_mask_vv_nxv16f16_nxv16f16_nxv16f16(<vscale x 16 x half> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfmadd_mask_vv_nxv16f16_nxv16f16_nxv16f16: ; CHECK-LABEL: intrinsic_vfmadd_mask_vv_nxv16f16_nxv16f16_nxv16f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfmadd.vv v8, v12, v16, v0.t ; CHECK-NEXT: vfmadd.vv v8, v12, v16, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x half> @llvm.riscv.vfmadd.mask.nxv16f16.nxv16f16( %a = call <vscale x 16 x half> @llvm.riscv.vfmadd.mask.nxv16f16.nxv16f16(
<vscale x 16 x half> %0, <vscale x 16 x half> %0,
<vscale x 16 x half> %1, <vscale x 16 x half> %1,
<vscale x 16 x half> %2, <vscale x 16 x half> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
iXLen %4, iXLen 0); iXLen 0, iXLen %4, iXLen 0);
ret <vscale x 16 x half> %a ret <vscale x 16 x half> %a
} }
declare <vscale x 1 x float> @llvm.riscv.vfmadd.nxv1f32.nxv1f32( declare <vscale x 1 x float> @llvm.riscv.vfmadd.nxv1f32.nxv1f32(
<vscale x 1 x float>, <vscale x 1 x float>,
<vscale x 1 x float>, <vscale x 1 x float>,
<vscale x 1 x float>, <vscale x 1 x float>,
iXLen, iXLen, iXLen, iXLen);
iXLen);
define <vscale x 1 x float> @intrinsic_vfmadd_vv_nxv1f32_nxv1f32_nxv1f32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, iXLen %3) nounwind { define <vscale x 1 x float> @intrinsic_vfmadd_vv_nxv1f32_nxv1f32_nxv1f32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfmadd_vv_nxv1f32_nxv1f32_nxv1f32: ; CHECK-LABEL: intrinsic_vfmadd_vv_nxv1f32_nxv1f32_nxv1f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, ma ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, ma
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfmadd.vv v8, v9, v10 ; CHECK-NEXT: vfmadd.vv v8, v9, v10
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x float> @llvm.riscv.vfmadd.nxv1f32.nxv1f32( %a = call <vscale x 1 x float> @llvm.riscv.vfmadd.nxv1f32.nxv1f32(
<vscale x 1 x float> %0, <vscale x 1 x float> %0,
<vscale x 1 x float> %1, <vscale x 1 x float> %1,
<vscale x 1 x float> %2, <vscale x 1 x float> %2,
iXLen %3, iXLen 0) iXLen 0, iXLen %3, iXLen 0)
ret <vscale x 1 x float> %a ret <vscale x 1 x float> %a
} }
declare <vscale x 1 x float> @llvm.riscv.vfmadd.mask.nxv1f32.nxv1f32( declare <vscale x 1 x float> @llvm.riscv.vfmadd.mask.nxv1f32.nxv1f32(
<vscale x 1 x float>, <vscale x 1 x float>,
<vscale x 1 x float>, <vscale x 1 x float>,
<vscale x 1 x float>, <vscale x 1 x float>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
iXLen, iXLen); iXLen, iXLen, iXLen);
define <vscale x 1 x float> @intrinsic_vfmadd_mask_vv_nxv1f32_nxv1f32_nxv1f32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind { define <vscale x 1 x float> @intrinsic_vfmadd_mask_vv_nxv1f32_nxv1f32_nxv1f32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfmadd_mask_vv_nxv1f32_nxv1f32_nxv1f32: ; CHECK-LABEL: intrinsic_vfmadd_mask_vv_nxv1f32_nxv1f32_nxv1f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfmadd.vv v8, v9, v10, v0.t ; CHECK-NEXT: vfmadd.vv v8, v9, v10, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x float> @llvm.riscv.vfmadd.mask.nxv1f32.nxv1f32( %a = call <vscale x 1 x float> @llvm.riscv.vfmadd.mask.nxv1f32.nxv1f32(
<vscale x 1 x float> %0, <vscale x 1 x float> %0,
<vscale x 1 x float> %1, <vscale x 1 x float> %1,
<vscale x 1 x float> %2, <vscale x 1 x float> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
iXLen %4, iXLen 0); iXLen 0, iXLen %4, iXLen 0);
ret <vscale x 1 x float> %a ret <vscale x 1 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vfmadd.nxv2f32.nxv2f32( declare <vscale x 2 x float> @llvm.riscv.vfmadd.nxv2f32.nxv2f32(
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 2 x float>, <vscale x 2 x float>,
iXLen, iXLen, iXLen, iXLen);
iXLen);
define <vscale x 2 x float> @intrinsic_vfmadd_vv_nxv2f32_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, iXLen %3) nounwind { define <vscale x 2 x float> @intrinsic_vfmadd_vv_nxv2f32_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfmadd_vv_nxv2f32_nxv2f32_nxv2f32: ; CHECK-LABEL: intrinsic_vfmadd_vv_nxv2f32_nxv2f32_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, ma ; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, ma
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfmadd.vv v8, v9, v10 ; CHECK-NEXT: vfmadd.vv v8, v9, v10
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfmadd.nxv2f32.nxv2f32( %a = call <vscale x 2 x float> @llvm.riscv.vfmadd.nxv2f32.nxv2f32(
<vscale x 2 x float> %0, <vscale x 2 x float> %0,
<vscale x 2 x float> %1, <vscale x 2 x float> %1,
<vscale x 2 x float> %2, <vscale x 2 x float> %2,
iXLen %3, iXLen 0) iXLen 0, iXLen %3, iXLen 0)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vfmadd.mask.nxv2f32.nxv2f32( declare <vscale x 2 x float> @llvm.riscv.vfmadd.mask.nxv2f32.nxv2f32(
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
iXLen, iXLen); iXLen, iXLen, iXLen);
define <vscale x 2 x float> @intrinsic_vfmadd_mask_vv_nxv2f32_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind { define <vscale x 2 x float> @intrinsic_vfmadd_mask_vv_nxv2f32_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfmadd_mask_vv_nxv2f32_nxv2f32_nxv2f32: ; CHECK-LABEL: intrinsic_vfmadd_mask_vv_nxv2f32_nxv2f32_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfmadd.vv v8, v9, v10, v0.t ; CHECK-NEXT: vfmadd.vv v8, v9, v10, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfmadd.mask.nxv2f32.nxv2f32( %a = call <vscale x 2 x float> @llvm.riscv.vfmadd.mask.nxv2f32.nxv2f32(
<vscale x 2 x float> %0, <vscale x 2 x float> %0,
<vscale x 2 x float> %1, <vscale x 2 x float> %1,
<vscale x 2 x float> %2, <vscale x 2 x float> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
iXLen %4, iXLen 0); iXLen 0, iXLen %4, iXLen 0);
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 4 x float> @llvm.riscv.vfmadd.nxv4f32.nxv4f32( declare <vscale x 4 x float> @llvm.riscv.vfmadd.nxv4f32.nxv4f32(
<vscale x 4 x float>, <vscale x 4 x float>,
<vscale x 4 x float>, <vscale x 4 x float>,
<vscale x 4 x float>, <vscale x 4 x float>,
iXLen, iXLen, iXLen, iXLen);
iXLen);
define <vscale x 4 x float> @intrinsic_vfmadd_vv_nxv4f32_nxv4f32_nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, <vscale x 4 x float> %2, iXLen %3) nounwind { define <vscale x 4 x float> @intrinsic_vfmadd_vv_nxv4f32_nxv4f32_nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, <vscale x 4 x float> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfmadd_vv_nxv4f32_nxv4f32_nxv4f32: ; CHECK-LABEL: intrinsic_vfmadd_vv_nxv4f32_nxv4f32_nxv4f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, ma ; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, ma
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfmadd.vv v8, v10, v12 ; CHECK-NEXT: vfmadd.vv v8, v10, v12
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x float> @llvm.riscv.vfmadd.nxv4f32.nxv4f32( %a = call <vscale x 4 x float> @llvm.riscv.vfmadd.nxv4f32.nxv4f32(
<vscale x 4 x float> %0, <vscale x 4 x float> %0,
<vscale x 4 x float> %1, <vscale x 4 x float> %1,
<vscale x 4 x float> %2, <vscale x 4 x float> %2,
iXLen %3, iXLen 0) iXLen 0, iXLen %3, iXLen 0)
ret <vscale x 4 x float> %a ret <vscale x 4 x float> %a
} }
declare <vscale x 4 x float> @llvm.riscv.vfmadd.mask.nxv4f32.nxv4f32( declare <vscale x 4 x float> @llvm.riscv.vfmadd.mask.nxv4f32.nxv4f32(
<vscale x 4 x float>, <vscale x 4 x float>,
<vscale x 4 x float>, <vscale x 4 x float>,
<vscale x 4 x float>, <vscale x 4 x float>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
iXLen, iXLen); iXLen, iXLen, iXLen);
define <vscale x 4 x float> @intrinsic_vfmadd_mask_vv_nxv4f32_nxv4f32_nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, <vscale x 4 x float> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind { define <vscale x 4 x float> @intrinsic_vfmadd_mask_vv_nxv4f32_nxv4f32_nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, <vscale x 4 x float> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfmadd_mask_vv_nxv4f32_nxv4f32_nxv4f32: ; CHECK-LABEL: intrinsic_vfmadd_mask_vv_nxv4f32_nxv4f32_nxv4f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfmadd.vv v8, v10, v12, v0.t ; CHECK-NEXT: vfmadd.vv v8, v10, v12, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x float> @llvm.riscv.vfmadd.mask.nxv4f32.nxv4f32( %a = call <vscale x 4 x float> @llvm.riscv.vfmadd.mask.nxv4f32.nxv4f32(
<vscale x 4 x float> %0, <vscale x 4 x float> %0,
<vscale x 4 x float> %1, <vscale x 4 x float> %1,
<vscale x 4 x float> %2, <vscale x 4 x float> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
iXLen %4, iXLen 0); iXLen 0, iXLen %4, iXLen 0);
ret <vscale x 4 x float> %a ret <vscale x 4 x float> %a
} }
declare <vscale x 8 x float> @llvm.riscv.vfmadd.nxv8f32.nxv8f32( declare <vscale x 8 x float> @llvm.riscv.vfmadd.nxv8f32.nxv8f32(
<vscale x 8 x float>, <vscale x 8 x float>,
<vscale x 8 x float>, <vscale x 8 x float>,
<vscale x 8 x float>, <vscale x 8 x float>,
iXLen, iXLen, iXLen, iXLen);
iXLen);
define <vscale x 8 x float> @intrinsic_vfmadd_vv_nxv8f32_nxv8f32_nxv8f32(<vscale x 8 x float> %0, <vscale x 8 x float> %1, <vscale x 8 x float> %2, iXLen %3) nounwind { define <vscale x 8 x float> @intrinsic_vfmadd_vv_nxv8f32_nxv8f32_nxv8f32(<vscale x 8 x float> %0, <vscale x 8 x float> %1, <vscale x 8 x float> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfmadd_vv_nxv8f32_nxv8f32_nxv8f32: ; CHECK-LABEL: intrinsic_vfmadd_vv_nxv8f32_nxv8f32_nxv8f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, ma ; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, ma
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfmadd.vv v8, v12, v16 ; CHECK-NEXT: vfmadd.vv v8, v12, v16
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x float> @llvm.riscv.vfmadd.nxv8f32.nxv8f32( %a = call <vscale x 8 x float> @llvm.riscv.vfmadd.nxv8f32.nxv8f32(
<vscale x 8 x float> %0, <vscale x 8 x float> %0,
<vscale x 8 x float> %1, <vscale x 8 x float> %1,
<vscale x 8 x float> %2, <vscale x 8 x float> %2,
iXLen %3, iXLen 0) iXLen 0, iXLen %3, iXLen 0)
ret <vscale x 8 x float> %a ret <vscale x 8 x float> %a
} }
declare <vscale x 8 x float> @llvm.riscv.vfmadd.mask.nxv8f32.nxv8f32( declare <vscale x 8 x float> @llvm.riscv.vfmadd.mask.nxv8f32.nxv8f32(
<vscale x 8 x float>, <vscale x 8 x float>,
<vscale x 8 x float>, <vscale x 8 x float>,
<vscale x 8 x float>, <vscale x 8 x float>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
iXLen, iXLen); iXLen, iXLen, iXLen);
define <vscale x 8 x float> @intrinsic_vfmadd_mask_vv_nxv8f32_nxv8f32_nxv8f32(<vscale x 8 x float> %0, <vscale x 8 x float> %1, <vscale x 8 x float> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind { define <vscale x 8 x float> @intrinsic_vfmadd_mask_vv_nxv8f32_nxv8f32_nxv8f32(<vscale x 8 x float> %0, <vscale x 8 x float> %1, <vscale x 8 x float> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfmadd_mask_vv_nxv8f32_nxv8f32_nxv8f32: ; CHECK-LABEL: intrinsic_vfmadd_mask_vv_nxv8f32_nxv8f32_nxv8f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfmadd.vv v8, v12, v16, v0.t ; CHECK-NEXT: vfmadd.vv v8, v12, v16, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x float> @llvm.riscv.vfmadd.mask.nxv8f32.nxv8f32( %a = call <vscale x 8 x float> @llvm.riscv.vfmadd.mask.nxv8f32.nxv8f32(
<vscale x 8 x float> %0, <vscale x 8 x float> %0,
<vscale x 8 x float> %1, <vscale x 8 x float> %1,
<vscale x 8 x float> %2, <vscale x 8 x float> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
iXLen %4, iXLen 0); iXLen 0, iXLen %4, iXLen 0);
ret <vscale x 8 x float> %a ret <vscale x 8 x float> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vfmadd.nxv1f64.nxv1f64( declare <vscale x 1 x double> @llvm.riscv.vfmadd.nxv1f64.nxv1f64(
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 1 x double>, <vscale x 1 x double>,
iXLen, iXLen, iXLen, iXLen);
iXLen);
define <vscale x 1 x double> @intrinsic_vfmadd_vv_nxv1f64_nxv1f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 1 x double> %1, <vscale x 1 x double> %2, iXLen %3) nounwind { define <vscale x 1 x double> @intrinsic_vfmadd_vv_nxv1f64_nxv1f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 1 x double> %1, <vscale x 1 x double> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfmadd_vv_nxv1f64_nxv1f64_nxv1f64: ; CHECK-LABEL: intrinsic_vfmadd_vv_nxv1f64_nxv1f64_nxv1f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, ma ; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, ma
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfmadd.vv v8, v9, v10 ; CHECK-NEXT: vfmadd.vv v8, v9, v10
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfmadd.nxv1f64.nxv1f64( %a = call <vscale x 1 x double> @llvm.riscv.vfmadd.nxv1f64.nxv1f64(
<vscale x 1 x double> %0, <vscale x 1 x double> %0,
<vscale x 1 x double> %1, <vscale x 1 x double> %1,
<vscale x 1 x double> %2, <vscale x 1 x double> %2,
iXLen %3, iXLen 0) iXLen 0, iXLen %3, iXLen 0)
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vfmadd.mask.nxv1f64.nxv1f64( declare <vscale x 1 x double> @llvm.riscv.vfmadd.mask.nxv1f64.nxv1f64(
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
iXLen, iXLen); iXLen, iXLen, iXLen);
define <vscale x 1 x double> @intrinsic_vfmadd_mask_vv_nxv1f64_nxv1f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 1 x double> %1, <vscale x 1 x double> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind { define <vscale x 1 x double> @intrinsic_vfmadd_mask_vv_nxv1f64_nxv1f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 1 x double> %1, <vscale x 1 x double> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfmadd_mask_vv_nxv1f64_nxv1f64_nxv1f64: ; CHECK-LABEL: intrinsic_vfmadd_mask_vv_nxv1f64_nxv1f64_nxv1f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, mu
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfmadd.vv v8, v9, v10, v0.t ; CHECK-NEXT: vfmadd.vv v8, v9, v10, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfmadd.mask.nxv1f64.nxv1f64( %a = call <vscale x 1 x double> @llvm.riscv.vfmadd.mask.nxv1f64.nxv1f64(
<vscale x 1 x double> %0, <vscale x 1 x double> %0,
<vscale x 1 x double> %1, <vscale x 1 x double> %1,
<vscale x 1 x double> %2, <vscale x 1 x double> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
iXLen %4, iXLen 0); iXLen 0, iXLen %4, iXLen 0);
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 2 x double> @llvm.riscv.vfmadd.nxv2f64.nxv2f64( declare <vscale x 2 x double> @llvm.riscv.vfmadd.nxv2f64.nxv2f64(
<vscale x 2 x double>, <vscale x 2 x double>,
<vscale x 2 x double>, <vscale x 2 x double>,
<vscale x 2 x double>, <vscale x 2 x double>,
iXLen, iXLen, iXLen, iXLen);
iXLen);
define <vscale x 2 x double> @intrinsic_vfmadd_vv_nxv2f64_nxv2f64_nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1, <vscale x 2 x double> %2, iXLen %3) nounwind { define <vscale x 2 x double> @intrinsic_vfmadd_vv_nxv2f64_nxv2f64_nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1, <vscale x 2 x double> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfmadd_vv_nxv2f64_nxv2f64_nxv2f64: ; CHECK-LABEL: intrinsic_vfmadd_vv_nxv2f64_nxv2f64_nxv2f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, ma ; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, ma
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfmadd.vv v8, v10, v12 ; CHECK-NEXT: vfmadd.vv v8, v10, v12
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x double> @llvm.riscv.vfmadd.nxv2f64.nxv2f64( %a = call <vscale x 2 x double> @llvm.riscv.vfmadd.nxv2f64.nxv2f64(
<vscale x 2 x double> %0, <vscale x 2 x double> %0,
<vscale x 2 x double> %1, <vscale x 2 x double> %1,
<vscale x 2 x double> %2, <vscale x 2 x double> %2,
iXLen %3, iXLen 0) iXLen 0, iXLen %3, iXLen 0)
ret <vscale x 2 x double> %a ret <vscale x 2 x double> %a
} }
declare <vscale x 2 x double> @llvm.riscv.vfmadd.mask.nxv2f64.nxv2f64( declare <vscale x 2 x double> @llvm.riscv.vfmadd.mask.nxv2f64.nxv2f64(
<vscale x 2 x double>, <vscale x 2 x double>,
<vscale x 2 x double>, <vscale x 2 x double>,
<vscale x 2 x double>, <vscale x 2 x double>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
iXLen, iXLen); iXLen, iXLen, iXLen);
define <vscale x 2 x double> @intrinsic_vfmadd_mask_vv_nxv2f64_nxv2f64_nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1, <vscale x 2 x double> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind { define <vscale x 2 x double> @intrinsic_vfmadd_mask_vv_nxv2f64_nxv2f64_nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1, <vscale x 2 x double> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfmadd_mask_vv_nxv2f64_nxv2f64_nxv2f64: ; CHECK-LABEL: intrinsic_vfmadd_mask_vv_nxv2f64_nxv2f64_nxv2f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, mu
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfmadd.vv v8, v10, v12, v0.t ; CHECK-NEXT: vfmadd.vv v8, v10, v12, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x double> @llvm.riscv.vfmadd.mask.nxv2f64.nxv2f64( %a = call <vscale x 2 x double> @llvm.riscv.vfmadd.mask.nxv2f64.nxv2f64(
<vscale x 2 x double> %0, <vscale x 2 x double> %0,
<vscale x 2 x double> %1, <vscale x 2 x double> %1,
<vscale x 2 x double> %2, <vscale x 2 x double> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
iXLen %4, iXLen 0); iXLen 0, iXLen %4, iXLen 0);
ret <vscale x 2 x double> %a ret <vscale x 2 x double> %a
} }
declare <vscale x 4 x double> @llvm.riscv.vfmadd.nxv4f64.nxv4f64( declare <vscale x 4 x double> @llvm.riscv.vfmadd.nxv4f64.nxv4f64(
<vscale x 4 x double>, <vscale x 4 x double>,
<vscale x 4 x double>, <vscale x 4 x double>,
<vscale x 4 x double>, <vscale x 4 x double>,
iXLen, iXLen, iXLen, iXLen);
iXLen);
define <vscale x 4 x double> @intrinsic_vfmadd_vv_nxv4f64_nxv4f64_nxv4f64(<vscale x 4 x double> %0, <vscale x 4 x double> %1, <vscale x 4 x double> %2, iXLen %3) nounwind { define <vscale x 4 x double> @intrinsic_vfmadd_vv_nxv4f64_nxv4f64_nxv4f64(<vscale x 4 x double> %0, <vscale x 4 x double> %1, <vscale x 4 x double> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfmadd_vv_nxv4f64_nxv4f64_nxv4f64: ; CHECK-LABEL: intrinsic_vfmadd_vv_nxv4f64_nxv4f64_nxv4f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, ma ; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, ma
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfmadd.vv v8, v12, v16 ; CHECK-NEXT: vfmadd.vv v8, v12, v16
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x double> @llvm.riscv.vfmadd.nxv4f64.nxv4f64( %a = call <vscale x 4 x double> @llvm.riscv.vfmadd.nxv4f64.nxv4f64(
<vscale x 4 x double> %0, <vscale x 4 x double> %0,
<vscale x 4 x double> %1, <vscale x 4 x double> %1,
<vscale x 4 x double> %2, <vscale x 4 x double> %2,
iXLen %3, iXLen 0) iXLen 0, iXLen %3, iXLen 0)
ret <vscale x 4 x double> %a ret <vscale x 4 x double> %a
} }
declare <vscale x 4 x double> @llvm.riscv.vfmadd.mask.nxv4f64.nxv4f64( declare <vscale x 4 x double> @llvm.riscv.vfmadd.mask.nxv4f64.nxv4f64(
<vscale x 4 x double>, <vscale x 4 x double>,
<vscale x 4 x double>, <vscale x 4 x double>,
<vscale x 4 x double>, <vscale x 4 x double>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
iXLen, iXLen); iXLen, iXLen, iXLen);
define <vscale x 4 x double> @intrinsic_vfmadd_mask_vv_nxv4f64_nxv4f64_nxv4f64(<vscale x 4 x double> %0, <vscale x 4 x double> %1, <vscale x 4 x double> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind { define <vscale x 4 x double> @intrinsic_vfmadd_mask_vv_nxv4f64_nxv4f64_nxv4f64(<vscale x 4 x double> %0, <vscale x 4 x double> %1, <vscale x 4 x double> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfmadd_mask_vv_nxv4f64_nxv4f64_nxv4f64: ; CHECK-LABEL: intrinsic_vfmadd_mask_vv_nxv4f64_nxv4f64_nxv4f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, mu
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfmadd.vv v8, v12, v16, v0.t ; CHECK-NEXT: vfmadd.vv v8, v12, v16, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x double> @llvm.riscv.vfmadd.mask.nxv4f64.nxv4f64( %a = call <vscale x 4 x double> @llvm.riscv.vfmadd.mask.nxv4f64.nxv4f64(
<vscale x 4 x double> %0, <vscale x 4 x double> %0,
<vscale x 4 x double> %1, <vscale x 4 x double> %1,
<vscale x 4 x double> %2, <vscale x 4 x double> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
iXLen %4, iXLen 0); iXLen 0, iXLen %4, iXLen 0);
ret <vscale x 4 x double> %a ret <vscale x 4 x double> %a
} }
declare <vscale x 1 x half> @llvm.riscv.vfmadd.nxv1f16.f16( declare <vscale x 1 x half> @llvm.riscv.vfmadd.nxv1f16.f16(
<vscale x 1 x half>, <vscale x 1 x half>,
half, half,
<vscale x 1 x half>, <vscale x 1 x half>,
iXLen, iXLen, iXLen, iXLen);
iXLen);
define <vscale x 1 x half> @intrinsic_vfmadd_vf_nxv1f16_f16_nxv1f16(<vscale x 1 x half> %0, half %1, <vscale x 1 x half> %2, iXLen %3) nounwind { define <vscale x 1 x half> @intrinsic_vfmadd_vf_nxv1f16_f16_nxv1f16(<vscale x 1 x half> %0, half %1, <vscale x 1 x half> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfmadd_vf_nxv1f16_f16_nxv1f16: ; CHECK-LABEL: intrinsic_vfmadd_vf_nxv1f16_f16_nxv1f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, ma ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, ma
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfmadd.vf v8, fa0, v9 ; CHECK-NEXT: vfmadd.vf v8, fa0, v9
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x half> @llvm.riscv.vfmadd.nxv1f16.f16( %a = call <vscale x 1 x half> @llvm.riscv.vfmadd.nxv1f16.f16(
<vscale x 1 x half> %0, <vscale x 1 x half> %0,
half %1, half %1,
<vscale x 1 x half> %2, <vscale x 1 x half> %2,
iXLen %3, iXLen 0) iXLen 0, iXLen %3, iXLen 0)
ret <vscale x 1 x half> %a ret <vscale x 1 x half> %a
} }
declare <vscale x 1 x half> @llvm.riscv.vfmadd.mask.nxv1f16.f16( declare <vscale x 1 x half> @llvm.riscv.vfmadd.mask.nxv1f16.f16(
<vscale x 1 x half>, <vscale x 1 x half>,
half, half,
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
iXLen, iXLen); iXLen, iXLen, iXLen);
define <vscale x 1 x half> @intrinsic_vfmadd_mask_vf_nxv1f16_f16_nxv1f16(<vscale x 1 x half> %0, half %1, <vscale x 1 x half> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind { define <vscale x 1 x half> @intrinsic_vfmadd_mask_vf_nxv1f16_f16_nxv1f16(<vscale x 1 x half> %0, half %1, <vscale x 1 x half> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfmadd_mask_vf_nxv1f16_f16_nxv1f16: ; CHECK-LABEL: intrinsic_vfmadd_mask_vf_nxv1f16_f16_nxv1f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfmadd.vf v8, fa0, v9, v0.t ; CHECK-NEXT: vfmadd.vf v8, fa0, v9, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x half> @llvm.riscv.vfmadd.mask.nxv1f16.f16( %a = call <vscale x 1 x half> @llvm.riscv.vfmadd.mask.nxv1f16.f16(
<vscale x 1 x half> %0, <vscale x 1 x half> %0,
half %1, half %1,
<vscale x 1 x half> %2, <vscale x 1 x half> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
iXLen %4, iXLen 0); iXLen 0, iXLen %4, iXLen 0);
ret <vscale x 1 x half> %a ret <vscale x 1 x half> %a
} }
declare <vscale x 2 x half> @llvm.riscv.vfmadd.nxv2f16.f16( declare <vscale x 2 x half> @llvm.riscv.vfmadd.nxv2f16.f16(
<vscale x 2 x half>, <vscale x 2 x half>,
half, half,
<vscale x 2 x half>, <vscale x 2 x half>,
iXLen, iXLen, iXLen, iXLen);
iXLen);
define <vscale x 2 x half> @intrinsic_vfmadd_vf_nxv2f16_f16_nxv2f16(<vscale x 2 x half> %0, half %1, <vscale x 2 x half> %2, iXLen %3) nounwind { define <vscale x 2 x half> @intrinsic_vfmadd_vf_nxv2f16_f16_nxv2f16(<vscale x 2 x half> %0, half %1, <vscale x 2 x half> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfmadd_vf_nxv2f16_f16_nxv2f16: ; CHECK-LABEL: intrinsic_vfmadd_vf_nxv2f16_f16_nxv2f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, ma ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, ma
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfmadd.vf v8, fa0, v9 ; CHECK-NEXT: vfmadd.vf v8, fa0, v9
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x half> @llvm.riscv.vfmadd.nxv2f16.f16( %a = call <vscale x 2 x half> @llvm.riscv.vfmadd.nxv2f16.f16(
<vscale x 2 x half> %0, <vscale x 2 x half> %0,
half %1, half %1,
<vscale x 2 x half> %2, <vscale x 2 x half> %2,
iXLen %3, iXLen 0) iXLen 0, iXLen %3, iXLen 0)
ret <vscale x 2 x half> %a ret <vscale x 2 x half> %a
} }
declare <vscale x 2 x half> @llvm.riscv.vfmadd.mask.nxv2f16.f16( declare <vscale x 2 x half> @llvm.riscv.vfmadd.mask.nxv2f16.f16(
<vscale x 2 x half>, <vscale x 2 x half>,
half, half,
<vscale x 2 x half>, <vscale x 2 x half>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
iXLen, iXLen); iXLen, iXLen, iXLen);
define <vscale x 2 x half> @intrinsic_vfmadd_mask_vf_nxv2f16_f16_nxv2f16(<vscale x 2 x half> %0, half %1, <vscale x 2 x half> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind { define <vscale x 2 x half> @intrinsic_vfmadd_mask_vf_nxv2f16_f16_nxv2f16(<vscale x 2 x half> %0, half %1, <vscale x 2 x half> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfmadd_mask_vf_nxv2f16_f16_nxv2f16: ; CHECK-LABEL: intrinsic_vfmadd_mask_vf_nxv2f16_f16_nxv2f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfmadd.vf v8, fa0, v9, v0.t ; CHECK-NEXT: vfmadd.vf v8, fa0, v9, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x half> @llvm.riscv.vfmadd.mask.nxv2f16.f16( %a = call <vscale x 2 x half> @llvm.riscv.vfmadd.mask.nxv2f16.f16(
<vscale x 2 x half> %0, <vscale x 2 x half> %0,
half %1, half %1,
<vscale x 2 x half> %2, <vscale x 2 x half> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
iXLen %4, iXLen 0); iXLen 0, iXLen %4, iXLen 0);
ret <vscale x 2 x half> %a ret <vscale x 2 x half> %a
} }
declare <vscale x 4 x half> @llvm.riscv.vfmadd.nxv4f16.f16( declare <vscale x 4 x half> @llvm.riscv.vfmadd.nxv4f16.f16(
<vscale x 4 x half>, <vscale x 4 x half>,
half, half,
<vscale x 4 x half>, <vscale x 4 x half>,
iXLen, iXLen, iXLen, iXLen);
iXLen);
define <vscale x 4 x half> @intrinsic_vfmadd_vf_nxv4f16_f16_nxv4f16(<vscale x 4 x half> %0, half %1, <vscale x 4 x half> %2, iXLen %3) nounwind { define <vscale x 4 x half> @intrinsic_vfmadd_vf_nxv4f16_f16_nxv4f16(<vscale x 4 x half> %0, half %1, <vscale x 4 x half> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfmadd_vf_nxv4f16_f16_nxv4f16: ; CHECK-LABEL: intrinsic_vfmadd_vf_nxv4f16_f16_nxv4f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, ma ; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, ma
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfmadd.vf v8, fa0, v9 ; CHECK-NEXT: vfmadd.vf v8, fa0, v9
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x half> @llvm.riscv.vfmadd.nxv4f16.f16( %a = call <vscale x 4 x half> @llvm.riscv.vfmadd.nxv4f16.f16(
<vscale x 4 x half> %0, <vscale x 4 x half> %0,
half %1, half %1,
<vscale x 4 x half> %2, <vscale x 4 x half> %2,
iXLen %3, iXLen 0) iXLen 0, iXLen %3, iXLen 0)
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 4 x half> @llvm.riscv.vfmadd.mask.nxv4f16.f16( declare <vscale x 4 x half> @llvm.riscv.vfmadd.mask.nxv4f16.f16(
<vscale x 4 x half>, <vscale x 4 x half>,
half, half,
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
iXLen, iXLen); iXLen, iXLen, iXLen);
define <vscale x 4 x half> @intrinsic_vfmadd_mask_vf_nxv4f16_f16_nxv4f16(<vscale x 4 x half> %0, half %1, <vscale x 4 x half> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind { define <vscale x 4 x half> @intrinsic_vfmadd_mask_vf_nxv4f16_f16_nxv4f16(<vscale x 4 x half> %0, half %1, <vscale x 4 x half> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfmadd_mask_vf_nxv4f16_f16_nxv4f16: ; CHECK-LABEL: intrinsic_vfmadd_mask_vf_nxv4f16_f16_nxv4f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfmadd.vf v8, fa0, v9, v0.t ; CHECK-NEXT: vfmadd.vf v8, fa0, v9, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x half> @llvm.riscv.vfmadd.mask.nxv4f16.f16( %a = call <vscale x 4 x half> @llvm.riscv.vfmadd.mask.nxv4f16.f16(
<vscale x 4 x half> %0, <vscale x 4 x half> %0,
half %1, half %1,
<vscale x 4 x half> %2, <vscale x 4 x half> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
iXLen %4, iXLen 0); iXLen 0, iXLen %4, iXLen 0);
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 8 x half> @llvm.riscv.vfmadd.nxv8f16.f16( declare <vscale x 8 x half> @llvm.riscv.vfmadd.nxv8f16.f16(
<vscale x 8 x half>, <vscale x 8 x half>,
half, half,
<vscale x 8 x half>, <vscale x 8 x half>,
iXLen, iXLen, iXLen, iXLen);
iXLen);
define <vscale x 8 x half> @intrinsic_vfmadd_vf_nxv8f16_f16_nxv8f16(<vscale x 8 x half> %0, half %1, <vscale x 8 x half> %2, iXLen %3) nounwind { define <vscale x 8 x half> @intrinsic_vfmadd_vf_nxv8f16_f16_nxv8f16(<vscale x 8 x half> %0, half %1, <vscale x 8 x half> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfmadd_vf_nxv8f16_f16_nxv8f16: ; CHECK-LABEL: intrinsic_vfmadd_vf_nxv8f16_f16_nxv8f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, ma ; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, ma
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfmadd.vf v8, fa0, v10 ; CHECK-NEXT: vfmadd.vf v8, fa0, v10
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x half> @llvm.riscv.vfmadd.nxv8f16.f16( %a = call <vscale x 8 x half> @llvm.riscv.vfmadd.nxv8f16.f16(
<vscale x 8 x half> %0, <vscale x 8 x half> %0,
half %1, half %1,
<vscale x 8 x half> %2, <vscale x 8 x half> %2,
iXLen %3, iXLen 0) iXLen 0, iXLen %3, iXLen 0)
ret <vscale x 8 x half> %a ret <vscale x 8 x half> %a
} }
declare <vscale x 8 x half> @llvm.riscv.vfmadd.mask.nxv8f16.f16( declare <vscale x 8 x half> @llvm.riscv.vfmadd.mask.nxv8f16.f16(
<vscale x 8 x half>, <vscale x 8 x half>,
half, half,
<vscale x 8 x half>, <vscale x 8 x half>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
iXLen, iXLen); iXLen, iXLen, iXLen);
define <vscale x 8 x half> @intrinsic_vfmadd_mask_vf_nxv8f16_f16_nxv8f16(<vscale x 8 x half> %0, half %1, <vscale x 8 x half> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind { define <vscale x 8 x half> @intrinsic_vfmadd_mask_vf_nxv8f16_f16_nxv8f16(<vscale x 8 x half> %0, half %1, <vscale x 8 x half> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfmadd_mask_vf_nxv8f16_f16_nxv8f16: ; CHECK-LABEL: intrinsic_vfmadd_mask_vf_nxv8f16_f16_nxv8f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, mu
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfmadd.vf v8, fa0, v10, v0.t ; CHECK-NEXT: vfmadd.vf v8, fa0, v10, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x half> @llvm.riscv.vfmadd.mask.nxv8f16.f16( %a = call <vscale x 8 x half> @llvm.riscv.vfmadd.mask.nxv8f16.f16(
<vscale x 8 x half> %0, <vscale x 8 x half> %0,
half %1, half %1,
<vscale x 8 x half> %2, <vscale x 8 x half> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
iXLen %4, iXLen 0); iXLen 0, iXLen %4, iXLen 0);
ret <vscale x 8 x half> %a ret <vscale x 8 x half> %a
} }
declare <vscale x 16 x half> @llvm.riscv.vfmadd.nxv16f16.f16( declare <vscale x 16 x half> @llvm.riscv.vfmadd.nxv16f16.f16(
<vscale x 16 x half>, <vscale x 16 x half>,
half, half,
<vscale x 16 x half>, <vscale x 16 x half>,
iXLen, iXLen, iXLen, iXLen);
iXLen);
define <vscale x 16 x half> @intrinsic_vfmadd_vf_nxv16f16_f16_nxv16f16(<vscale x 16 x half> %0, half %1, <vscale x 16 x half> %2, iXLen %3) nounwind { define <vscale x 16 x half> @intrinsic_vfmadd_vf_nxv16f16_f16_nxv16f16(<vscale x 16 x half> %0, half %1, <vscale x 16 x half> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfmadd_vf_nxv16f16_f16_nxv16f16: ; CHECK-LABEL: intrinsic_vfmadd_vf_nxv16f16_f16_nxv16f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, ma ; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, ma
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfmadd.vf v8, fa0, v12 ; CHECK-NEXT: vfmadd.vf v8, fa0, v12
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x half> @llvm.riscv.vfmadd.nxv16f16.f16( %a = call <vscale x 16 x half> @llvm.riscv.vfmadd.nxv16f16.f16(
<vscale x 16 x half> %0, <vscale x 16 x half> %0,
half %1, half %1,
<vscale x 16 x half> %2, <vscale x 16 x half> %2,
iXLen %3, iXLen 0) iXLen 0, iXLen %3, iXLen 0)
ret <vscale x 16 x half> %a ret <vscale x 16 x half> %a
} }
declare <vscale x 16 x half> @llvm.riscv.vfmadd.mask.nxv16f16.f16( declare <vscale x 16 x half> @llvm.riscv.vfmadd.mask.nxv16f16.f16(
<vscale x 16 x half>, <vscale x 16 x half>,
half, half,
<vscale x 16 x half>, <vscale x 16 x half>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
iXLen, iXLen); iXLen, iXLen, iXLen);
define <vscale x 16 x half> @intrinsic_vfmadd_mask_vf_nxv16f16_f16_nxv16f16(<vscale x 16 x half> %0, half %1, <vscale x 16 x half> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind { define <vscale x 16 x half> @intrinsic_vfmadd_mask_vf_nxv16f16_f16_nxv16f16(<vscale x 16 x half> %0, half %1, <vscale x 16 x half> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfmadd_mask_vf_nxv16f16_f16_nxv16f16: ; CHECK-LABEL: intrinsic_vfmadd_mask_vf_nxv16f16_f16_nxv16f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfmadd.vf v8, fa0, v12, v0.t ; CHECK-NEXT: vfmadd.vf v8, fa0, v12, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x half> @llvm.riscv.vfmadd.mask.nxv16f16.f16( %a = call <vscale x 16 x half> @llvm.riscv.vfmadd.mask.nxv16f16.f16(
<vscale x 16 x half> %0, <vscale x 16 x half> %0,
half %1, half %1,
<vscale x 16 x half> %2, <vscale x 16 x half> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
iXLen %4, iXLen 0); iXLen 0, iXLen %4, iXLen 0);
ret <vscale x 16 x half> %a ret <vscale x 16 x half> %a
} }
declare <vscale x 1 x float> @llvm.riscv.vfmadd.nxv1f32.f32( declare <vscale x 1 x float> @llvm.riscv.vfmadd.nxv1f32.f32(
<vscale x 1 x float>, <vscale x 1 x float>,
float, float,
<vscale x 1 x float>, <vscale x 1 x float>,
iXLen, iXLen, iXLen, iXLen);
iXLen);
define <vscale x 1 x float> @intrinsic_vfmadd_vf_nxv1f32_f32_nxv1f32(<vscale x 1 x float> %0, float %1, <vscale x 1 x float> %2, iXLen %3) nounwind { define <vscale x 1 x float> @intrinsic_vfmadd_vf_nxv1f32_f32_nxv1f32(<vscale x 1 x float> %0, float %1, <vscale x 1 x float> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfmadd_vf_nxv1f32_f32_nxv1f32: ; CHECK-LABEL: intrinsic_vfmadd_vf_nxv1f32_f32_nxv1f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, ma ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, ma
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfmadd.vf v8, fa0, v9 ; CHECK-NEXT: vfmadd.vf v8, fa0, v9
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x float> @llvm.riscv.vfmadd.nxv1f32.f32( %a = call <vscale x 1 x float> @llvm.riscv.vfmadd.nxv1f32.f32(
<vscale x 1 x float> %0, <vscale x 1 x float> %0,
float %1, float %1,
<vscale x 1 x float> %2, <vscale x 1 x float> %2,
iXLen %3, iXLen 0) iXLen 0, iXLen %3, iXLen 0)
ret <vscale x 1 x float> %a ret <vscale x 1 x float> %a
} }
declare <vscale x 1 x float> @llvm.riscv.vfmadd.mask.nxv1f32.f32( declare <vscale x 1 x float> @llvm.riscv.vfmadd.mask.nxv1f32.f32(
<vscale x 1 x float>, <vscale x 1 x float>,
float, float,
<vscale x 1 x float>, <vscale x 1 x float>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
iXLen, iXLen); iXLen, iXLen, iXLen);
define <vscale x 1 x float> @intrinsic_vfmadd_mask_vf_nxv1f32_f32_nxv1f32(<vscale x 1 x float> %0, float %1, <vscale x 1 x float> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind { define <vscale x 1 x float> @intrinsic_vfmadd_mask_vf_nxv1f32_f32_nxv1f32(<vscale x 1 x float> %0, float %1, <vscale x 1 x float> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfmadd_mask_vf_nxv1f32_f32_nxv1f32: ; CHECK-LABEL: intrinsic_vfmadd_mask_vf_nxv1f32_f32_nxv1f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfmadd.vf v8, fa0, v9, v0.t ; CHECK-NEXT: vfmadd.vf v8, fa0, v9, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x float> @llvm.riscv.vfmadd.mask.nxv1f32.f32( %a = call <vscale x 1 x float> @llvm.riscv.vfmadd.mask.nxv1f32.f32(
<vscale x 1 x float> %0, <vscale x 1 x float> %0,
float %1, float %1,
<vscale x 1 x float> %2, <vscale x 1 x float> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
iXLen %4, iXLen 0); iXLen 0, iXLen %4, iXLen 0);
ret <vscale x 1 x float> %a ret <vscale x 1 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vfmadd.nxv2f32.f32( declare <vscale x 2 x float> @llvm.riscv.vfmadd.nxv2f32.f32(
<vscale x 2 x float>, <vscale x 2 x float>,
float, float,
<vscale x 2 x float>, <vscale x 2 x float>,
iXLen, iXLen, iXLen, iXLen);
iXLen);
define <vscale x 2 x float> @intrinsic_vfmadd_vf_nxv2f32_f32_nxv2f32(<vscale x 2 x float> %0, float %1, <vscale x 2 x float> %2, iXLen %3) nounwind { define <vscale x 2 x float> @intrinsic_vfmadd_vf_nxv2f32_f32_nxv2f32(<vscale x 2 x float> %0, float %1, <vscale x 2 x float> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfmadd_vf_nxv2f32_f32_nxv2f32: ; CHECK-LABEL: intrinsic_vfmadd_vf_nxv2f32_f32_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, ma ; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, ma
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfmadd.vf v8, fa0, v9 ; CHECK-NEXT: vfmadd.vf v8, fa0, v9
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfmadd.nxv2f32.f32( %a = call <vscale x 2 x float> @llvm.riscv.vfmadd.nxv2f32.f32(
<vscale x 2 x float> %0, <vscale x 2 x float> %0,
float %1, float %1,
<vscale x 2 x float> %2, <vscale x 2 x float> %2,
iXLen %3, iXLen 0) iXLen 0, iXLen %3, iXLen 0)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vfmadd.mask.nxv2f32.f32( declare <vscale x 2 x float> @llvm.riscv.vfmadd.mask.nxv2f32.f32(
<vscale x 2 x float>, <vscale x 2 x float>,
float, float,
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
iXLen, iXLen); iXLen, iXLen, iXLen);
define <vscale x 2 x float> @intrinsic_vfmadd_mask_vf_nxv2f32_f32_nxv2f32(<vscale x 2 x float> %0, float %1, <vscale x 2 x float> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind { define <vscale x 2 x float> @intrinsic_vfmadd_mask_vf_nxv2f32_f32_nxv2f32(<vscale x 2 x float> %0, float %1, <vscale x 2 x float> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfmadd_mask_vf_nxv2f32_f32_nxv2f32: ; CHECK-LABEL: intrinsic_vfmadd_mask_vf_nxv2f32_f32_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfmadd.vf v8, fa0, v9, v0.t ; CHECK-NEXT: vfmadd.vf v8, fa0, v9, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfmadd.mask.nxv2f32.f32( %a = call <vscale x 2 x float> @llvm.riscv.vfmadd.mask.nxv2f32.f32(
<vscale x 2 x float> %0, <vscale x 2 x float> %0,
float %1, float %1,
<vscale x 2 x float> %2, <vscale x 2 x float> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
iXLen %4, iXLen 0); iXLen 0, iXLen %4, iXLen 0);
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 4 x float> @llvm.riscv.vfmadd.nxv4f32.f32( declare <vscale x 4 x float> @llvm.riscv.vfmadd.nxv4f32.f32(
<vscale x 4 x float>, <vscale x 4 x float>,
float, float,
<vscale x 4 x float>, <vscale x 4 x float>,
iXLen, iXLen, iXLen, iXLen);
iXLen);
define <vscale x 4 x float> @intrinsic_vfmadd_vf_nxv4f32_f32_nxv4f32(<vscale x 4 x float> %0, float %1, <vscale x 4 x float> %2, iXLen %3) nounwind { define <vscale x 4 x float> @intrinsic_vfmadd_vf_nxv4f32_f32_nxv4f32(<vscale x 4 x float> %0, float %1, <vscale x 4 x float> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfmadd_vf_nxv4f32_f32_nxv4f32: ; CHECK-LABEL: intrinsic_vfmadd_vf_nxv4f32_f32_nxv4f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, ma ; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, ma
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfmadd.vf v8, fa0, v10 ; CHECK-NEXT: vfmadd.vf v8, fa0, v10
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x float> @llvm.riscv.vfmadd.nxv4f32.f32( %a = call <vscale x 4 x float> @llvm.riscv.vfmadd.nxv4f32.f32(
<vscale x 4 x float> %0, <vscale x 4 x float> %0,
float %1, float %1,
<vscale x 4 x float> %2, <vscale x 4 x float> %2,
iXLen %3, iXLen 0) iXLen 0, iXLen %3, iXLen 0)
ret <vscale x 4 x float> %a ret <vscale x 4 x float> %a
} }
declare <vscale x 4 x float> @llvm.riscv.vfmadd.mask.nxv4f32.f32( declare <vscale x 4 x float> @llvm.riscv.vfmadd.mask.nxv4f32.f32(
<vscale x 4 x float>, <vscale x 4 x float>,
float, float,
<vscale x 4 x float>, <vscale x 4 x float>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
iXLen, iXLen); iXLen, iXLen, iXLen);
define <vscale x 4 x float> @intrinsic_vfmadd_mask_vf_nxv4f32_f32_nxv4f32(<vscale x 4 x float> %0, float %1, <vscale x 4 x float> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind { define <vscale x 4 x float> @intrinsic_vfmadd_mask_vf_nxv4f32_f32_nxv4f32(<vscale x 4 x float> %0, float %1, <vscale x 4 x float> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfmadd_mask_vf_nxv4f32_f32_nxv4f32: ; CHECK-LABEL: intrinsic_vfmadd_mask_vf_nxv4f32_f32_nxv4f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfmadd.vf v8, fa0, v10, v0.t ; CHECK-NEXT: vfmadd.vf v8, fa0, v10, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x float> @llvm.riscv.vfmadd.mask.nxv4f32.f32( %a = call <vscale x 4 x float> @llvm.riscv.vfmadd.mask.nxv4f32.f32(
<vscale x 4 x float> %0, <vscale x 4 x float> %0,
float %1, float %1,
<vscale x 4 x float> %2, <vscale x 4 x float> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
iXLen %4, iXLen 0); iXLen 0, iXLen %4, iXLen 0);
ret <vscale x 4 x float> %a ret <vscale x 4 x float> %a
} }
declare <vscale x 8 x float> @llvm.riscv.vfmadd.nxv8f32.f32( declare <vscale x 8 x float> @llvm.riscv.vfmadd.nxv8f32.f32(
<vscale x 8 x float>, <vscale x 8 x float>,
float, float,
<vscale x 8 x float>, <vscale x 8 x float>,
iXLen, iXLen, iXLen, iXLen);
iXLen);
define <vscale x 8 x float> @intrinsic_vfmadd_vf_nxv8f32_f32_nxv8f32(<vscale x 8 x float> %0, float %1, <vscale x 8 x float> %2, iXLen %3) nounwind { define <vscale x 8 x float> @intrinsic_vfmadd_vf_nxv8f32_f32_nxv8f32(<vscale x 8 x float> %0, float %1, <vscale x 8 x float> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfmadd_vf_nxv8f32_f32_nxv8f32: ; CHECK-LABEL: intrinsic_vfmadd_vf_nxv8f32_f32_nxv8f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, ma ; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, ma
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfmadd.vf v8, fa0, v12 ; CHECK-NEXT: vfmadd.vf v8, fa0, v12
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x float> @llvm.riscv.vfmadd.nxv8f32.f32( %a = call <vscale x 8 x float> @llvm.riscv.vfmadd.nxv8f32.f32(
<vscale x 8 x float> %0, <vscale x 8 x float> %0,
float %1, float %1,
<vscale x 8 x float> %2, <vscale x 8 x float> %2,
iXLen %3, iXLen 0) iXLen 0, iXLen %3, iXLen 0)
ret <vscale x 8 x float> %a ret <vscale x 8 x float> %a
} }
declare <vscale x 8 x float> @llvm.riscv.vfmadd.mask.nxv8f32.f32( declare <vscale x 8 x float> @llvm.riscv.vfmadd.mask.nxv8f32.f32(
<vscale x 8 x float>, <vscale x 8 x float>,
float, float,
<vscale x 8 x float>, <vscale x 8 x float>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
iXLen, iXLen); iXLen, iXLen, iXLen);
define <vscale x 8 x float> @intrinsic_vfmadd_mask_vf_nxv8f32_f32_nxv8f32(<vscale x 8 x float> %0, float %1, <vscale x 8 x float> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind { define <vscale x 8 x float> @intrinsic_vfmadd_mask_vf_nxv8f32_f32_nxv8f32(<vscale x 8 x float> %0, float %1, <vscale x 8 x float> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfmadd_mask_vf_nxv8f32_f32_nxv8f32: ; CHECK-LABEL: intrinsic_vfmadd_mask_vf_nxv8f32_f32_nxv8f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfmadd.vf v8, fa0, v12, v0.t ; CHECK-NEXT: vfmadd.vf v8, fa0, v12, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x float> @llvm.riscv.vfmadd.mask.nxv8f32.f32( %a = call <vscale x 8 x float> @llvm.riscv.vfmadd.mask.nxv8f32.f32(
<vscale x 8 x float> %0, <vscale x 8 x float> %0,
float %1, float %1,
<vscale x 8 x float> %2, <vscale x 8 x float> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
iXLen %4, iXLen 0); iXLen 0, iXLen %4, iXLen 0);
ret <vscale x 8 x float> %a ret <vscale x 8 x float> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vfmadd.nxv1f64.f64( declare <vscale x 1 x double> @llvm.riscv.vfmadd.nxv1f64.f64(
<vscale x 1 x double>, <vscale x 1 x double>,
double, double,
<vscale x 1 x double>, <vscale x 1 x double>,
iXLen, iXLen, iXLen, iXLen);
iXLen);
define <vscale x 1 x double> @intrinsic_vfmadd_vf_nxv1f64_f64_nxv1f64(<vscale x 1 x double> %0, double %1, <vscale x 1 x double> %2, iXLen %3) nounwind { define <vscale x 1 x double> @intrinsic_vfmadd_vf_nxv1f64_f64_nxv1f64(<vscale x 1 x double> %0, double %1, <vscale x 1 x double> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfmadd_vf_nxv1f64_f64_nxv1f64: ; CHECK-LABEL: intrinsic_vfmadd_vf_nxv1f64_f64_nxv1f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, ma ; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, ma
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfmadd.vf v8, fa0, v9 ; CHECK-NEXT: vfmadd.vf v8, fa0, v9
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfmadd.nxv1f64.f64( %a = call <vscale x 1 x double> @llvm.riscv.vfmadd.nxv1f64.f64(
<vscale x 1 x double> %0, <vscale x 1 x double> %0,
double %1, double %1,
<vscale x 1 x double> %2, <vscale x 1 x double> %2,
iXLen %3, iXLen 0) iXLen 0, iXLen %3, iXLen 0)
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vfmadd.mask.nxv1f64.f64( declare <vscale x 1 x double> @llvm.riscv.vfmadd.mask.nxv1f64.f64(
<vscale x 1 x double>, <vscale x 1 x double>,
double, double,
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
iXLen, iXLen); iXLen, iXLen, iXLen);
define <vscale x 1 x double> @intrinsic_vfmadd_mask_vf_nxv1f64_f64_nxv1f64(<vscale x 1 x double> %0, double %1, <vscale x 1 x double> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind { define <vscale x 1 x double> @intrinsic_vfmadd_mask_vf_nxv1f64_f64_nxv1f64(<vscale x 1 x double> %0, double %1, <vscale x 1 x double> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfmadd_mask_vf_nxv1f64_f64_nxv1f64: ; CHECK-LABEL: intrinsic_vfmadd_mask_vf_nxv1f64_f64_nxv1f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, mu
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfmadd.vf v8, fa0, v9, v0.t ; CHECK-NEXT: vfmadd.vf v8, fa0, v9, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfmadd.mask.nxv1f64.f64( %a = call <vscale x 1 x double> @llvm.riscv.vfmadd.mask.nxv1f64.f64(
<vscale x 1 x double> %0, <vscale x 1 x double> %0,
double %1, double %1,
<vscale x 1 x double> %2, <vscale x 1 x double> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
iXLen %4, iXLen 0); iXLen 0, iXLen %4, iXLen 0);
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 2 x double> @llvm.riscv.vfmadd.nxv2f64.f64( declare <vscale x 2 x double> @llvm.riscv.vfmadd.nxv2f64.f64(
<vscale x 2 x double>, <vscale x 2 x double>,
double, double,
<vscale x 2 x double>, <vscale x 2 x double>,
iXLen, iXLen, iXLen, iXLen);
iXLen);
define <vscale x 2 x double> @intrinsic_vfmadd_vf_nxv2f64_f64_nxv2f64(<vscale x 2 x double> %0, double %1, <vscale x 2 x double> %2, iXLen %3) nounwind { define <vscale x 2 x double> @intrinsic_vfmadd_vf_nxv2f64_f64_nxv2f64(<vscale x 2 x double> %0, double %1, <vscale x 2 x double> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfmadd_vf_nxv2f64_f64_nxv2f64: ; CHECK-LABEL: intrinsic_vfmadd_vf_nxv2f64_f64_nxv2f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, ma ; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, ma
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfmadd.vf v8, fa0, v10 ; CHECK-NEXT: vfmadd.vf v8, fa0, v10
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x double> @llvm.riscv.vfmadd.nxv2f64.f64( %a = call <vscale x 2 x double> @llvm.riscv.vfmadd.nxv2f64.f64(
<vscale x 2 x double> %0, <vscale x 2 x double> %0,
double %1, double %1,
<vscale x 2 x double> %2, <vscale x 2 x double> %2,
iXLen %3, iXLen 0) iXLen 0, iXLen %3, iXLen 0)
ret <vscale x 2 x double> %a ret <vscale x 2 x double> %a
} }
declare <vscale x 2 x double> @llvm.riscv.vfmadd.mask.nxv2f64.f64( declare <vscale x 2 x double> @llvm.riscv.vfmadd.mask.nxv2f64.f64(
<vscale x 2 x double>, <vscale x 2 x double>,
double, double,
<vscale x 2 x double>, <vscale x 2 x double>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
iXLen, iXLen); iXLen, iXLen, iXLen);
define <vscale x 2 x double> @intrinsic_vfmadd_mask_vf_nxv2f64_f64_nxv2f64(<vscale x 2 x double> %0, double %1, <vscale x 2 x double> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind { define <vscale x 2 x double> @intrinsic_vfmadd_mask_vf_nxv2f64_f64_nxv2f64(<vscale x 2 x double> %0, double %1, <vscale x 2 x double> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfmadd_mask_vf_nxv2f64_f64_nxv2f64: ; CHECK-LABEL: intrinsic_vfmadd_mask_vf_nxv2f64_f64_nxv2f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, mu
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfmadd.vf v8, fa0, v10, v0.t ; CHECK-NEXT: vfmadd.vf v8, fa0, v10, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x double> @llvm.riscv.vfmadd.mask.nxv2f64.f64( %a = call <vscale x 2 x double> @llvm.riscv.vfmadd.mask.nxv2f64.f64(
<vscale x 2 x double> %0, <vscale x 2 x double> %0,
double %1, double %1,
<vscale x 2 x double> %2, <vscale x 2 x double> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
iXLen %4, iXLen 0); iXLen 0, iXLen %4, iXLen 0);
ret <vscale x 2 x double> %a ret <vscale x 2 x double> %a
} }
declare <vscale x 4 x double> @llvm.riscv.vfmadd.nxv4f64.f64( declare <vscale x 4 x double> @llvm.riscv.vfmadd.nxv4f64.f64(
<vscale x 4 x double>, <vscale x 4 x double>,
double, double,
<vscale x 4 x double>, <vscale x 4 x double>,
iXLen, iXLen, iXLen, iXLen);
iXLen);
define <vscale x 4 x double> @intrinsic_vfmadd_vf_nxv4f64_f64_nxv4f64(<vscale x 4 x double> %0, double %1, <vscale x 4 x double> %2, iXLen %3) nounwind { define <vscale x 4 x double> @intrinsic_vfmadd_vf_nxv4f64_f64_nxv4f64(<vscale x 4 x double> %0, double %1, <vscale x 4 x double> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfmadd_vf_nxv4f64_f64_nxv4f64: ; CHECK-LABEL: intrinsic_vfmadd_vf_nxv4f64_f64_nxv4f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, ma ; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, ma
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfmadd.vf v8, fa0, v12 ; CHECK-NEXT: vfmadd.vf v8, fa0, v12
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x double> @llvm.riscv.vfmadd.nxv4f64.f64( %a = call <vscale x 4 x double> @llvm.riscv.vfmadd.nxv4f64.f64(
<vscale x 4 x double> %0, <vscale x 4 x double> %0,
double %1, double %1,
<vscale x 4 x double> %2, <vscale x 4 x double> %2,
iXLen %3, iXLen 0) iXLen 0, iXLen %3, iXLen 0)
ret <vscale x 4 x double> %a ret <vscale x 4 x double> %a
} }
declare <vscale x 4 x double> @llvm.riscv.vfmadd.mask.nxv4f64.f64( declare <vscale x 4 x double> @llvm.riscv.vfmadd.mask.nxv4f64.f64(
<vscale x 4 x double>, <vscale x 4 x double>,
double, double,
<vscale x 4 x double>, <vscale x 4 x double>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
iXLen, iXLen); iXLen, iXLen, iXLen);
define <vscale x 4 x double> @intrinsic_vfmadd_mask_vf_nxv4f64_f64_nxv4f64(<vscale x 4 x double> %0, double %1, <vscale x 4 x double> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind { define <vscale x 4 x double> @intrinsic_vfmadd_mask_vf_nxv4f64_f64_nxv4f64(<vscale x 4 x double> %0, double %1, <vscale x 4 x double> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfmadd_mask_vf_nxv4f64_f64_nxv4f64: ; CHECK-LABEL: intrinsic_vfmadd_mask_vf_nxv4f64_f64_nxv4f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, mu
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfmadd.vf v8, fa0, v12, v0.t ; CHECK-NEXT: vfmadd.vf v8, fa0, v12, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x double> @llvm.riscv.vfmadd.mask.nxv4f64.f64( %a = call <vscale x 4 x double> @llvm.riscv.vfmadd.mask.nxv4f64.f64(
<vscale x 4 x double> %0, <vscale x 4 x double> %0,
double %1, double %1,
<vscale x 4 x double> %2, <vscale x 4 x double> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
iXLen %4, iXLen 0); iXLen 0, iXLen %4, iXLen 0);
ret <vscale x 4 x double> %a ret <vscale x 4 x double> %a
} }

llvm/test/CodeGen/RISCV/rvv/vfmsac.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zfh,+experimental-zvfh \ ; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zfh,+experimental-zvfh \
; RUN: -verify-machineinstrs -target-abi=ilp32d | FileCheck %s ; RUN: -verify-machineinstrs -target-abi=ilp32d | FileCheck %s
; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zfh,+experimental-zvfh \ ; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zfh,+experimental-zvfh \
; RUN: -verify-machineinstrs -target-abi=lp64d | FileCheck %s ; RUN: -verify-machineinstrs -target-abi=lp64d | FileCheck %s
declare <vscale x 1 x half> @llvm.riscv.vfmsac.nxv1f16.nxv1f16( declare <vscale x 1 x half> @llvm.riscv.vfmsac.nxv1f16.nxv1f16(
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x half>, <vscale x 1 x half>,
iXLen, iXLen, iXLen, iXLen);
iXLen);
define <vscale x 1 x half> @intrinsic_vfmsac_vv_nxv1f16_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, iXLen %3) nounwind { define <vscale x 1 x half> @intrinsic_vfmsac_vv_nxv1f16_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfmsac_vv_nxv1f16_nxv1f16_nxv1f16: ; CHECK-LABEL: intrinsic_vfmsac_vv_nxv1f16_nxv1f16_nxv1f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, ma ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, ma
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfmsac.vv v8, v9, v10 ; CHECK-NEXT: vfmsac.vv v8, v9, v10
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x half> @llvm.riscv.vfmsac.nxv1f16.nxv1f16( %a = call <vscale x 1 x half> @llvm.riscv.vfmsac.nxv1f16.nxv1f16(
<vscale x 1 x half> %0, <vscale x 1 x half> %0,
<vscale x 1 x half> %1, <vscale x 1 x half> %1,
<vscale x 1 x half> %2, <vscale x 1 x half> %2,
iXLen %3, iXLen 0) iXLen 0, iXLen %3, iXLen 0)
ret <vscale x 1 x half> %a ret <vscale x 1 x half> %a
} }
declare <vscale x 1 x half> @llvm.riscv.vfmsac.mask.nxv1f16.nxv1f16( declare <vscale x 1 x half> @llvm.riscv.vfmsac.mask.nxv1f16.nxv1f16(
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
iXLen, iXLen); iXLen, iXLen, iXLen);
define <vscale x 1 x half> @intrinsic_vfmsac_mask_vv_nxv1f16_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind { define <vscale x 1 x half> @intrinsic_vfmsac_mask_vv_nxv1f16_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfmsac_mask_vv_nxv1f16_nxv1f16_nxv1f16: ; CHECK-LABEL: intrinsic_vfmsac_mask_vv_nxv1f16_nxv1f16_nxv1f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfmsac.vv v8, v9, v10, v0.t ; CHECK-NEXT: vfmsac.vv v8, v9, v10, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x half> @llvm.riscv.vfmsac.mask.nxv1f16.nxv1f16( %a = call <vscale x 1 x half> @llvm.riscv.vfmsac.mask.nxv1f16.nxv1f16(
<vscale x 1 x half> %0, <vscale x 1 x half> %0,
<vscale x 1 x half> %1, <vscale x 1 x half> %1,
<vscale x 1 x half> %2, <vscale x 1 x half> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
iXLen %4, iXLen 0); iXLen 0, iXLen %4, iXLen 0);
ret <vscale x 1 x half> %a ret <vscale x 1 x half> %a
} }
declare <vscale x 2 x half> @llvm.riscv.vfmsac.nxv2f16.nxv2f16( declare <vscale x 2 x half> @llvm.riscv.vfmsac.nxv2f16.nxv2f16(
<vscale x 2 x half>, <vscale x 2 x half>,
<vscale x 2 x half>, <vscale x 2 x half>,
<vscale x 2 x half>, <vscale x 2 x half>,
iXLen, iXLen, iXLen, iXLen);
iXLen);
define <vscale x 2 x half> @intrinsic_vfmsac_vv_nxv2f16_nxv2f16_nxv2f16(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, iXLen %3) nounwind { define <vscale x 2 x half> @intrinsic_vfmsac_vv_nxv2f16_nxv2f16_nxv2f16(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfmsac_vv_nxv2f16_nxv2f16_nxv2f16: ; CHECK-LABEL: intrinsic_vfmsac_vv_nxv2f16_nxv2f16_nxv2f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, ma ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, ma
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfmsac.vv v8, v9, v10 ; CHECK-NEXT: vfmsac.vv v8, v9, v10
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x half> @llvm.riscv.vfmsac.nxv2f16.nxv2f16( %a = call <vscale x 2 x half> @llvm.riscv.vfmsac.nxv2f16.nxv2f16(
<vscale x 2 x half> %0, <vscale x 2 x half> %0,
<vscale x 2 x half> %1, <vscale x 2 x half> %1,
<vscale x 2 x half> %2, <vscale x 2 x half> %2,
iXLen %3, iXLen 0) iXLen 0, iXLen %3, iXLen 0)
ret <vscale x 2 x half> %a ret <vscale x 2 x half> %a
} }
declare <vscale x 2 x half> @llvm.riscv.vfmsac.mask.nxv2f16.nxv2f16( declare <vscale x 2 x half> @llvm.riscv.vfmsac.mask.nxv2f16.nxv2f16(
<vscale x 2 x half>, <vscale x 2 x half>,
<vscale x 2 x half>, <vscale x 2 x half>,
<vscale x 2 x half>, <vscale x 2 x half>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
iXLen, iXLen); iXLen, iXLen, iXLen);
define <vscale x 2 x half> @intrinsic_vfmsac_mask_vv_nxv2f16_nxv2f16_nxv2f16(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind { define <vscale x 2 x half> @intrinsic_vfmsac_mask_vv_nxv2f16_nxv2f16_nxv2f16(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfmsac_mask_vv_nxv2f16_nxv2f16_nxv2f16: ; CHECK-LABEL: intrinsic_vfmsac_mask_vv_nxv2f16_nxv2f16_nxv2f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfmsac.vv v8, v9, v10, v0.t ; CHECK-NEXT: vfmsac.vv v8, v9, v10, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x half> @llvm.riscv.vfmsac.mask.nxv2f16.nxv2f16( %a = call <vscale x 2 x half> @llvm.riscv.vfmsac.mask.nxv2f16.nxv2f16(
<vscale x 2 x half> %0, <vscale x 2 x half> %0,
<vscale x 2 x half> %1, <vscale x 2 x half> %1,
<vscale x 2 x half> %2, <vscale x 2 x half> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
iXLen %4, iXLen 0); iXLen 0, iXLen %4, iXLen 0);
ret <vscale x 2 x half> %a ret <vscale x 2 x half> %a
} }
declare <vscale x 4 x half> @llvm.riscv.vfmsac.nxv4f16.nxv4f16( declare <vscale x 4 x half> @llvm.riscv.vfmsac.nxv4f16.nxv4f16(
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 4 x half>, <vscale x 4 x half>,
iXLen, iXLen, iXLen, iXLen);
iXLen);
define <vscale x 4 x half> @intrinsic_vfmsac_vv_nxv4f16_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, iXLen %3) nounwind { define <vscale x 4 x half> @intrinsic_vfmsac_vv_nxv4f16_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfmsac_vv_nxv4f16_nxv4f16_nxv4f16: ; CHECK-LABEL: intrinsic_vfmsac_vv_nxv4f16_nxv4f16_nxv4f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, ma ; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, ma
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfmsac.vv v8, v9, v10 ; CHECK-NEXT: vfmsac.vv v8, v9, v10
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x half> @llvm.riscv.vfmsac.nxv4f16.nxv4f16( %a = call <vscale x 4 x half> @llvm.riscv.vfmsac.nxv4f16.nxv4f16(
<vscale x 4 x half> %0, <vscale x 4 x half> %0,
<vscale x 4 x half> %1, <vscale x 4 x half> %1,
<vscale x 4 x half> %2, <vscale x 4 x half> %2,
iXLen %3, iXLen 0) iXLen 0, iXLen %3, iXLen 0)
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 4 x half> @llvm.riscv.vfmsac.mask.nxv4f16.nxv4f16( declare <vscale x 4 x half> @llvm.riscv.vfmsac.mask.nxv4f16.nxv4f16(
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
iXLen, iXLen); iXLen, iXLen, iXLen);
define <vscale x 4 x half> @intrinsic_vfmsac_mask_vv_nxv4f16_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind { define <vscale x 4 x half> @intrinsic_vfmsac_mask_vv_nxv4f16_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfmsac_mask_vv_nxv4f16_nxv4f16_nxv4f16: ; CHECK-LABEL: intrinsic_vfmsac_mask_vv_nxv4f16_nxv4f16_nxv4f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfmsac.vv v8, v9, v10, v0.t ; CHECK-NEXT: vfmsac.vv v8, v9, v10, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x half> @llvm.riscv.vfmsac.mask.nxv4f16.nxv4f16( %a = call <vscale x 4 x half> @llvm.riscv.vfmsac.mask.nxv4f16.nxv4f16(
<vscale x 4 x half> %0, <vscale x 4 x half> %0,
<vscale x 4 x half> %1, <vscale x 4 x half> %1,
<vscale x 4 x half> %2, <vscale x 4 x half> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
iXLen %4, iXLen 0); iXLen 0, iXLen %4, iXLen 0);
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 8 x half> @llvm.riscv.vfmsac.nxv8f16.nxv8f16( declare <vscale x 8 x half> @llvm.riscv.vfmsac.nxv8f16.nxv8f16(
<vscale x 8 x half>, <vscale x 8 x half>,
<vscale x 8 x half>, <vscale x 8 x half>,
<vscale x 8 x half>, <vscale x 8 x half>,
iXLen, iXLen, iXLen, iXLen);
iXLen);
define <vscale x 8 x half> @intrinsic_vfmsac_vv_nxv8f16_nxv8f16_nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, iXLen %3) nounwind { define <vscale x 8 x half> @intrinsic_vfmsac_vv_nxv8f16_nxv8f16_nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfmsac_vv_nxv8f16_nxv8f16_nxv8f16: ; CHECK-LABEL: intrinsic_vfmsac_vv_nxv8f16_nxv8f16_nxv8f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, ma ; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, ma
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfmsac.vv v8, v10, v12 ; CHECK-NEXT: vfmsac.vv v8, v10, v12
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x half> @llvm.riscv.vfmsac.nxv8f16.nxv8f16( %a = call <vscale x 8 x half> @llvm.riscv.vfmsac.nxv8f16.nxv8f16(
<vscale x 8 x half> %0, <vscale x 8 x half> %0,
<vscale x 8 x half> %1, <vscale x 8 x half> %1,
<vscale x 8 x half> %2, <vscale x 8 x half> %2,
iXLen %3, iXLen 0) iXLen 0, iXLen %3, iXLen 0)
ret <vscale x 8 x half> %a ret <vscale x 8 x half> %a
} }
declare <vscale x 8 x half> @llvm.riscv.vfmsac.mask.nxv8f16.nxv8f16( declare <vscale x 8 x half> @llvm.riscv.vfmsac.mask.nxv8f16.nxv8f16(
<vscale x 8 x half>, <vscale x 8 x half>,
<vscale x 8 x half>, <vscale x 8 x half>,
<vscale x 8 x half>, <vscale x 8 x half>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
iXLen, iXLen); iXLen, iXLen, iXLen);
define <vscale x 8 x half> @intrinsic_vfmsac_mask_vv_nxv8f16_nxv8f16_nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind { define <vscale x 8 x half> @intrinsic_vfmsac_mask_vv_nxv8f16_nxv8f16_nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfmsac_mask_vv_nxv8f16_nxv8f16_nxv8f16: ; CHECK-LABEL: intrinsic_vfmsac_mask_vv_nxv8f16_nxv8f16_nxv8f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, mu
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfmsac.vv v8, v10, v12, v0.t ; CHECK-NEXT: vfmsac.vv v8, v10, v12, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x half> @llvm.riscv.vfmsac.mask.nxv8f16.nxv8f16( %a = call <vscale x 8 x half> @llvm.riscv.vfmsac.mask.nxv8f16.nxv8f16(
<vscale x 8 x half> %0, <vscale x 8 x half> %0,
<vscale x 8 x half> %1, <vscale x 8 x half> %1,
<vscale x 8 x half> %2, <vscale x 8 x half> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
iXLen %4, iXLen 0); iXLen 0, iXLen %4, iXLen 0);
ret <vscale x 8 x half> %a ret <vscale x 8 x half> %a
} }
declare <vscale x 16 x half> @llvm.riscv.vfmsac.nxv16f16.nxv16f16( declare <vscale x 16 x half> @llvm.riscv.vfmsac.nxv16f16.nxv16f16(
<vscale x 16 x half>, <vscale x 16 x half>,
<vscale x 16 x half>, <vscale x 16 x half>,
<vscale x 16 x half>, <vscale x 16 x half>,
iXLen, iXLen, iXLen, iXLen);
iXLen);
define <vscale x 16 x half> @intrinsic_vfmsac_vv_nxv16f16_nxv16f16_nxv16f16(<vscale x 16 x half> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %2, iXLen %3) nounwind { define <vscale x 16 x half> @intrinsic_vfmsac_vv_nxv16f16_nxv16f16_nxv16f16(<vscale x 16 x half> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfmsac_vv_nxv16f16_nxv16f16_nxv16f16: ; CHECK-LABEL: intrinsic_vfmsac_vv_nxv16f16_nxv16f16_nxv16f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, ma ; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, ma
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfmsac.vv v8, v12, v16 ; CHECK-NEXT: vfmsac.vv v8, v12, v16
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x half> @llvm.riscv.vfmsac.nxv16f16.nxv16f16( %a = call <vscale x 16 x half> @llvm.riscv.vfmsac.nxv16f16.nxv16f16(
<vscale x 16 x half> %0, <vscale x 16 x half> %0,
<vscale x 16 x half> %1, <vscale x 16 x half> %1,
<vscale x 16 x half> %2, <vscale x 16 x half> %2,
iXLen %3, iXLen 0) iXLen 0, iXLen %3, iXLen 0)
ret <vscale x 16 x half> %a ret <vscale x 16 x half> %a
} }
declare <vscale x 16 x half> @llvm.riscv.vfmsac.mask.nxv16f16.nxv16f16( declare <vscale x 16 x half> @llvm.riscv.vfmsac.mask.nxv16f16.nxv16f16(
<vscale x 16 x half>, <vscale x 16 x half>,
<vscale x 16 x half>, <vscale x 16 x half>,
<vscale x 16 x half>, <vscale x 16 x half>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
iXLen, iXLen); iXLen, iXLen, iXLen);
define <vscale x 16 x half> @intrinsic_vfmsac_mask_vv_nxv16f16_nxv16f16_nxv16f16(<vscale x 16 x half> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind { define <vscale x 16 x half> @intrinsic_vfmsac_mask_vv_nxv16f16_nxv16f16_nxv16f16(<vscale x 16 x half> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfmsac_mask_vv_nxv16f16_nxv16f16_nxv16f16: ; CHECK-LABEL: intrinsic_vfmsac_mask_vv_nxv16f16_nxv16f16_nxv16f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfmsac.vv v8, v12, v16, v0.t ; CHECK-NEXT: vfmsac.vv v8, v12, v16, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x half> @llvm.riscv.vfmsac.mask.nxv16f16.nxv16f16( %a = call <vscale x 16 x half> @llvm.riscv.vfmsac.mask.nxv16f16.nxv16f16(
<vscale x 16 x half> %0, <vscale x 16 x half> %0,
<vscale x 16 x half> %1, <vscale x 16 x half> %1,
<vscale x 16 x half> %2, <vscale x 16 x half> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
iXLen %4, iXLen 0); iXLen 0, iXLen %4, iXLen 0);
ret <vscale x 16 x half> %a ret <vscale x 16 x half> %a
} }
declare <vscale x 1 x float> @llvm.riscv.vfmsac.nxv1f32.nxv1f32( declare <vscale x 1 x float> @llvm.riscv.vfmsac.nxv1f32.nxv1f32(
<vscale x 1 x float>, <vscale x 1 x float>,
<vscale x 1 x float>, <vscale x 1 x float>,
<vscale x 1 x float>, <vscale x 1 x float>,
iXLen, iXLen, iXLen, iXLen);
iXLen);
define <vscale x 1 x float> @intrinsic_vfmsac_vv_nxv1f32_nxv1f32_nxv1f32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, iXLen %3) nounwind { define <vscale x 1 x float> @intrinsic_vfmsac_vv_nxv1f32_nxv1f32_nxv1f32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfmsac_vv_nxv1f32_nxv1f32_nxv1f32: ; CHECK-LABEL: intrinsic_vfmsac_vv_nxv1f32_nxv1f32_nxv1f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, ma ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, ma
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfmsac.vv v8, v9, v10 ; CHECK-NEXT: vfmsac.vv v8, v9, v10
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x float> @llvm.riscv.vfmsac.nxv1f32.nxv1f32( %a = call <vscale x 1 x float> @llvm.riscv.vfmsac.nxv1f32.nxv1f32(
<vscale x 1 x float> %0, <vscale x 1 x float> %0,
<vscale x 1 x float> %1, <vscale x 1 x float> %1,
<vscale x 1 x float> %2, <vscale x 1 x float> %2,
iXLen %3, iXLen 0) iXLen 0, iXLen %3, iXLen 0)
ret <vscale x 1 x float> %a ret <vscale x 1 x float> %a
} }
declare <vscale x 1 x float> @llvm.riscv.vfmsac.mask.nxv1f32.nxv1f32( declare <vscale x 1 x float> @llvm.riscv.vfmsac.mask.nxv1f32.nxv1f32(
<vscale x 1 x float>, <vscale x 1 x float>,
<vscale x 1 x float>, <vscale x 1 x float>,
<vscale x 1 x float>, <vscale x 1 x float>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
iXLen, iXLen); iXLen, iXLen, iXLen);
define <vscale x 1 x float> @intrinsic_vfmsac_mask_vv_nxv1f32_nxv1f32_nxv1f32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind { define <vscale x 1 x float> @intrinsic_vfmsac_mask_vv_nxv1f32_nxv1f32_nxv1f32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfmsac_mask_vv_nxv1f32_nxv1f32_nxv1f32: ; CHECK-LABEL: intrinsic_vfmsac_mask_vv_nxv1f32_nxv1f32_nxv1f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfmsac.vv v8, v9, v10, v0.t ; CHECK-NEXT: vfmsac.vv v8, v9, v10, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x float> @llvm.riscv.vfmsac.mask.nxv1f32.nxv1f32( %a = call <vscale x 1 x float> @llvm.riscv.vfmsac.mask.nxv1f32.nxv1f32(
<vscale x 1 x float> %0, <vscale x 1 x float> %0,
<vscale x 1 x float> %1, <vscale x 1 x float> %1,
<vscale x 1 x float> %2, <vscale x 1 x float> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
iXLen %4, iXLen 0); iXLen 0, iXLen %4, iXLen 0);
ret <vscale x 1 x float> %a ret <vscale x 1 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vfmsac.nxv2f32.nxv2f32( declare <vscale x 2 x float> @llvm.riscv.vfmsac.nxv2f32.nxv2f32(
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 2 x float>, <vscale x 2 x float>,
iXLen, iXLen, iXLen, iXLen);
iXLen);
define <vscale x 2 x float> @intrinsic_vfmsac_vv_nxv2f32_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, iXLen %3) nounwind { define <vscale x 2 x float> @intrinsic_vfmsac_vv_nxv2f32_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfmsac_vv_nxv2f32_nxv2f32_nxv2f32: ; CHECK-LABEL: intrinsic_vfmsac_vv_nxv2f32_nxv2f32_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, ma ; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, ma
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfmsac.vv v8, v9, v10 ; CHECK-NEXT: vfmsac.vv v8, v9, v10
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfmsac.nxv2f32.nxv2f32( %a = call <vscale x 2 x float> @llvm.riscv.vfmsac.nxv2f32.nxv2f32(
<vscale x 2 x float> %0, <vscale x 2 x float> %0,
<vscale x 2 x float> %1, <vscale x 2 x float> %1,
<vscale x 2 x float> %2, <vscale x 2 x float> %2,
iXLen %3, iXLen 0) iXLen 0, iXLen %3, iXLen 0)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vfmsac.mask.nxv2f32.nxv2f32( declare <vscale x 2 x float> @llvm.riscv.vfmsac.mask.nxv2f32.nxv2f32(
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
iXLen, iXLen); iXLen, iXLen, iXLen);
define <vscale x 2 x float> @intrinsic_vfmsac_mask_vv_nxv2f32_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind { define <vscale x 2 x float> @intrinsic_vfmsac_mask_vv_nxv2f32_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfmsac_mask_vv_nxv2f32_nxv2f32_nxv2f32: ; CHECK-LABEL: intrinsic_vfmsac_mask_vv_nxv2f32_nxv2f32_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfmsac.vv v8, v9, v10, v0.t ; CHECK-NEXT: vfmsac.vv v8, v9, v10, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfmsac.mask.nxv2f32.nxv2f32( %a = call <vscale x 2 x float> @llvm.riscv.vfmsac.mask.nxv2f32.nxv2f32(
<vscale x 2 x float> %0, <vscale x 2 x float> %0,
<vscale x 2 x float> %1, <vscale x 2 x float> %1,
<vscale x 2 x float> %2, <vscale x 2 x float> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
iXLen %4, iXLen 0); iXLen 0, iXLen %4, iXLen 0);
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 4 x float> @llvm.riscv.vfmsac.nxv4f32.nxv4f32( declare <vscale x 4 x float> @llvm.riscv.vfmsac.nxv4f32.nxv4f32(
<vscale x 4 x float>, <vscale x 4 x float>,
<vscale x 4 x float>, <vscale x 4 x float>,
<vscale x 4 x float>, <vscale x 4 x float>,
iXLen, iXLen, iXLen, iXLen);
iXLen);
define <vscale x 4 x float> @intrinsic_vfmsac_vv_nxv4f32_nxv4f32_nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, <vscale x 4 x float> %2, iXLen %3) nounwind { define <vscale x 4 x float> @intrinsic_vfmsac_vv_nxv4f32_nxv4f32_nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, <vscale x 4 x float> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfmsac_vv_nxv4f32_nxv4f32_nxv4f32: ; CHECK-LABEL: intrinsic_vfmsac_vv_nxv4f32_nxv4f32_nxv4f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, ma ; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, ma
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfmsac.vv v8, v10, v12 ; CHECK-NEXT: vfmsac.vv v8, v10, v12
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x float> @llvm.riscv.vfmsac.nxv4f32.nxv4f32( %a = call <vscale x 4 x float> @llvm.riscv.vfmsac.nxv4f32.nxv4f32(
<vscale x 4 x float> %0, <vscale x 4 x float> %0,
<vscale x 4 x float> %1, <vscale x 4 x float> %1,
<vscale x 4 x float> %2, <vscale x 4 x float> %2,
iXLen %3, iXLen 0) iXLen 0, iXLen %3, iXLen 0)
ret <vscale x 4 x float> %a ret <vscale x 4 x float> %a
} }
declare <vscale x 4 x float> @llvm.riscv.vfmsac.mask.nxv4f32.nxv4f32( declare <vscale x 4 x float> @llvm.riscv.vfmsac.mask.nxv4f32.nxv4f32(
<vscale x 4 x float>, <vscale x 4 x float>,
<vscale x 4 x float>, <vscale x 4 x float>,
<vscale x 4 x float>, <vscale x 4 x float>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
iXLen, iXLen); iXLen, iXLen, iXLen);
define <vscale x 4 x float> @intrinsic_vfmsac_mask_vv_nxv4f32_nxv4f32_nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, <vscale x 4 x float> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind { define <vscale x 4 x float> @intrinsic_vfmsac_mask_vv_nxv4f32_nxv4f32_nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, <vscale x 4 x float> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfmsac_mask_vv_nxv4f32_nxv4f32_nxv4f32: ; CHECK-LABEL: intrinsic_vfmsac_mask_vv_nxv4f32_nxv4f32_nxv4f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfmsac.vv v8, v10, v12, v0.t ; CHECK-NEXT: vfmsac.vv v8, v10, v12, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x float> @llvm.riscv.vfmsac.mask.nxv4f32.nxv4f32( %a = call <vscale x 4 x float> @llvm.riscv.vfmsac.mask.nxv4f32.nxv4f32(
<vscale x 4 x float> %0, <vscale x 4 x float> %0,
<vscale x 4 x float> %1, <vscale x 4 x float> %1,
<vscale x 4 x float> %2, <vscale x 4 x float> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
iXLen %4, iXLen 0); iXLen 0, iXLen %4, iXLen 0);
ret <vscale x 4 x float> %a ret <vscale x 4 x float> %a
} }
declare <vscale x 8 x float> @llvm.riscv.vfmsac.nxv8f32.nxv8f32( declare <vscale x 8 x float> @llvm.riscv.vfmsac.nxv8f32.nxv8f32(
<vscale x 8 x float>, <vscale x 8 x float>,
<vscale x 8 x float>, <vscale x 8 x float>,
<vscale x 8 x float>, <vscale x 8 x float>,
iXLen, iXLen, iXLen, iXLen);
iXLen);
define <vscale x 8 x float> @intrinsic_vfmsac_vv_nxv8f32_nxv8f32_nxv8f32(<vscale x 8 x float> %0, <vscale x 8 x float> %1, <vscale x 8 x float> %2, iXLen %3) nounwind { define <vscale x 8 x float> @intrinsic_vfmsac_vv_nxv8f32_nxv8f32_nxv8f32(<vscale x 8 x float> %0, <vscale x 8 x float> %1, <vscale x 8 x float> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfmsac_vv_nxv8f32_nxv8f32_nxv8f32: ; CHECK-LABEL: intrinsic_vfmsac_vv_nxv8f32_nxv8f32_nxv8f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, ma ; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, ma
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfmsac.vv v8, v12, v16 ; CHECK-NEXT: vfmsac.vv v8, v12, v16
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x float> @llvm.riscv.vfmsac.nxv8f32.nxv8f32( %a = call <vscale x 8 x float> @llvm.riscv.vfmsac.nxv8f32.nxv8f32(
<vscale x 8 x float> %0, <vscale x 8 x float> %0,
<vscale x 8 x float> %1, <vscale x 8 x float> %1,
<vscale x 8 x float> %2, <vscale x 8 x float> %2,
iXLen %3, iXLen 0) iXLen 0, iXLen %3, iXLen 0)
ret <vscale x 8 x float> %a ret <vscale x 8 x float> %a
} }
declare <vscale x 8 x float> @llvm.riscv.vfmsac.mask.nxv8f32.nxv8f32( declare <vscale x 8 x float> @llvm.riscv.vfmsac.mask.nxv8f32.nxv8f32(
<vscale x 8 x float>, <vscale x 8 x float>,
<vscale x 8 x float>, <vscale x 8 x float>,
<vscale x 8 x float>, <vscale x 8 x float>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
iXLen, iXLen); iXLen, iXLen, iXLen);
define <vscale x 8 x float> @intrinsic_vfmsac_mask_vv_nxv8f32_nxv8f32_nxv8f32(<vscale x 8 x float> %0, <vscale x 8 x float> %1, <vscale x 8 x float> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind { define <vscale x 8 x float> @intrinsic_vfmsac_mask_vv_nxv8f32_nxv8f32_nxv8f32(<vscale x 8 x float> %0, <vscale x 8 x float> %1, <vscale x 8 x float> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfmsac_mask_vv_nxv8f32_nxv8f32_nxv8f32: ; CHECK-LABEL: intrinsic_vfmsac_mask_vv_nxv8f32_nxv8f32_nxv8f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfmsac.vv v8, v12, v16, v0.t ; CHECK-NEXT: vfmsac.vv v8, v12, v16, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x float> @llvm.riscv.vfmsac.mask.nxv8f32.nxv8f32( %a = call <vscale x 8 x float> @llvm.riscv.vfmsac.mask.nxv8f32.nxv8f32(
<vscale x 8 x float> %0, <vscale x 8 x float> %0,
<vscale x 8 x float> %1, <vscale x 8 x float> %1,
<vscale x 8 x float> %2, <vscale x 8 x float> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
iXLen %4, iXLen 0); iXLen 0, iXLen %4, iXLen 0);
ret <vscale x 8 x float> %a ret <vscale x 8 x float> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vfmsac.nxv1f64.nxv1f64( declare <vscale x 1 x double> @llvm.riscv.vfmsac.nxv1f64.nxv1f64(
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 1 x double>, <vscale x 1 x double>,
iXLen, iXLen, iXLen, iXLen);
iXLen);
define <vscale x 1 x double> @intrinsic_vfmsac_vv_nxv1f64_nxv1f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 1 x double> %1, <vscale x 1 x double> %2, iXLen %3) nounwind { define <vscale x 1 x double> @intrinsic_vfmsac_vv_nxv1f64_nxv1f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 1 x double> %1, <vscale x 1 x double> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfmsac_vv_nxv1f64_nxv1f64_nxv1f64: ; CHECK-LABEL: intrinsic_vfmsac_vv_nxv1f64_nxv1f64_nxv1f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, ma ; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, ma
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfmsac.vv v8, v9, v10 ; CHECK-NEXT: vfmsac.vv v8, v9, v10
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfmsac.nxv1f64.nxv1f64( %a = call <vscale x 1 x double> @llvm.riscv.vfmsac.nxv1f64.nxv1f64(
<vscale x 1 x double> %0, <vscale x 1 x double> %0,
<vscale x 1 x double> %1, <vscale x 1 x double> %1,
<vscale x 1 x double> %2, <vscale x 1 x double> %2,
iXLen %3, iXLen 0) iXLen 0, iXLen %3, iXLen 0)
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vfmsac.mask.nxv1f64.nxv1f64( declare <vscale x 1 x double> @llvm.riscv.vfmsac.mask.nxv1f64.nxv1f64(
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
iXLen, iXLen); iXLen, iXLen, iXLen);
define <vscale x 1 x double> @intrinsic_vfmsac_mask_vv_nxv1f64_nxv1f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 1 x double> %1, <vscale x 1 x double> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind { define <vscale x 1 x double> @intrinsic_vfmsac_mask_vv_nxv1f64_nxv1f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 1 x double> %1, <vscale x 1 x double> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfmsac_mask_vv_nxv1f64_nxv1f64_nxv1f64: ; CHECK-LABEL: intrinsic_vfmsac_mask_vv_nxv1f64_nxv1f64_nxv1f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, mu
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfmsac.vv v8, v9, v10, v0.t ; CHECK-NEXT: vfmsac.vv v8, v9, v10, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfmsac.mask.nxv1f64.nxv1f64( %a = call <vscale x 1 x double> @llvm.riscv.vfmsac.mask.nxv1f64.nxv1f64(
<vscale x 1 x double> %0, <vscale x 1 x double> %0,
<vscale x 1 x double> %1, <vscale x 1 x double> %1,
<vscale x 1 x double> %2, <vscale x 1 x double> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
iXLen %4, iXLen 0); iXLen 0, iXLen %4, iXLen 0);
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 2 x double> @llvm.riscv.vfmsac.nxv2f64.nxv2f64( declare <vscale x 2 x double> @llvm.riscv.vfmsac.nxv2f64.nxv2f64(
<vscale x 2 x double>, <vscale x 2 x double>,
<vscale x 2 x double>, <vscale x 2 x double>,
<vscale x 2 x double>, <vscale x 2 x double>,
iXLen, iXLen, iXLen, iXLen);
iXLen);
define <vscale x 2 x double> @intrinsic_vfmsac_vv_nxv2f64_nxv2f64_nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1, <vscale x 2 x double> %2, iXLen %3) nounwind { define <vscale x 2 x double> @intrinsic_vfmsac_vv_nxv2f64_nxv2f64_nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1, <vscale x 2 x double> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfmsac_vv_nxv2f64_nxv2f64_nxv2f64: ; CHECK-LABEL: intrinsic_vfmsac_vv_nxv2f64_nxv2f64_nxv2f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, ma ; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, ma
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfmsac.vv v8, v10, v12 ; CHECK-NEXT: vfmsac.vv v8, v10, v12
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x double> @llvm.riscv.vfmsac.nxv2f64.nxv2f64( %a = call <vscale x 2 x double> @llvm.riscv.vfmsac.nxv2f64.nxv2f64(
<vscale x 2 x double> %0, <vscale x 2 x double> %0,
<vscale x 2 x double> %1, <vscale x 2 x double> %1,
<vscale x 2 x double> %2, <vscale x 2 x double> %2,
iXLen %3, iXLen 0) iXLen 0, iXLen %3, iXLen 0)
ret <vscale x 2 x double> %a ret <vscale x 2 x double> %a
} }
declare <vscale x 2 x double> @llvm.riscv.vfmsac.mask.nxv2f64.nxv2f64( declare <vscale x 2 x double> @llvm.riscv.vfmsac.mask.nxv2f64.nxv2f64(
<vscale x 2 x double>, <vscale x 2 x double>,
<vscale x 2 x double>, <vscale x 2 x double>,
<vscale x 2 x double>, <vscale x 2 x double>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
iXLen, iXLen); iXLen, iXLen, iXLen);
define <vscale x 2 x double> @intrinsic_vfmsac_mask_vv_nxv2f64_nxv2f64_nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1, <vscale x 2 x double> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind { define <vscale x 2 x double> @intrinsic_vfmsac_mask_vv_nxv2f64_nxv2f64_nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1, <vscale x 2 x double> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfmsac_mask_vv_nxv2f64_nxv2f64_nxv2f64: ; CHECK-LABEL: intrinsic_vfmsac_mask_vv_nxv2f64_nxv2f64_nxv2f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, mu
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfmsac.vv v8, v10, v12, v0.t ; CHECK-NEXT: vfmsac.vv v8, v10, v12, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x double> @llvm.riscv.vfmsac.mask.nxv2f64.nxv2f64( %a = call <vscale x 2 x double> @llvm.riscv.vfmsac.mask.nxv2f64.nxv2f64(
<vscale x 2 x double> %0, <vscale x 2 x double> %0,
<vscale x 2 x double> %1, <vscale x 2 x double> %1,
<vscale x 2 x double> %2, <vscale x 2 x double> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
iXLen %4, iXLen 0); iXLen 0, iXLen %4, iXLen 0);
ret <vscale x 2 x double> %a ret <vscale x 2 x double> %a
} }
declare <vscale x 4 x double> @llvm.riscv.vfmsac.nxv4f64.nxv4f64( declare <vscale x 4 x double> @llvm.riscv.vfmsac.nxv4f64.nxv4f64(
<vscale x 4 x double>, <vscale x 4 x double>,
<vscale x 4 x double>, <vscale x 4 x double>,
<vscale x 4 x double>, <vscale x 4 x double>,
iXLen, iXLen, iXLen, iXLen);
iXLen);
define <vscale x 4 x double> @intrinsic_vfmsac_vv_nxv4f64_nxv4f64_nxv4f64(<vscale x 4 x double> %0, <vscale x 4 x double> %1, <vscale x 4 x double> %2, iXLen %3) nounwind { define <vscale x 4 x double> @intrinsic_vfmsac_vv_nxv4f64_nxv4f64_nxv4f64(<vscale x 4 x double> %0, <vscale x 4 x double> %1, <vscale x 4 x double> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfmsac_vv_nxv4f64_nxv4f64_nxv4f64: ; CHECK-LABEL: intrinsic_vfmsac_vv_nxv4f64_nxv4f64_nxv4f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, ma ; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, ma
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfmsac.vv v8, v12, v16 ; CHECK-NEXT: vfmsac.vv v8, v12, v16
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x double> @llvm.riscv.vfmsac.nxv4f64.nxv4f64( %a = call <vscale x 4 x double> @llvm.riscv.vfmsac.nxv4f64.nxv4f64(
<vscale x 4 x double> %0, <vscale x 4 x double> %0,
<vscale x 4 x double> %1, <vscale x 4 x double> %1,
<vscale x 4 x double> %2, <vscale x 4 x double> %2,
iXLen %3, iXLen 0) iXLen 0, iXLen %3, iXLen 0)
ret <vscale x 4 x double> %a ret <vscale x 4 x double> %a
} }
declare <vscale x 4 x double> @llvm.riscv.vfmsac.mask.nxv4f64.nxv4f64( declare <vscale x 4 x double> @llvm.riscv.vfmsac.mask.nxv4f64.nxv4f64(
<vscale x 4 x double>, <vscale x 4 x double>,
<vscale x 4 x double>, <vscale x 4 x double>,
<vscale x 4 x double>, <vscale x 4 x double>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
iXLen, iXLen); iXLen, iXLen, iXLen);
define <vscale x 4 x double> @intrinsic_vfmsac_mask_vv_nxv4f64_nxv4f64_nxv4f64(<vscale x 4 x double> %0, <vscale x 4 x double> %1, <vscale x 4 x double> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind { define <vscale x 4 x double> @intrinsic_vfmsac_mask_vv_nxv4f64_nxv4f64_nxv4f64(<vscale x 4 x double> %0, <vscale x 4 x double> %1, <vscale x 4 x double> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfmsac_mask_vv_nxv4f64_nxv4f64_nxv4f64: ; CHECK-LABEL: intrinsic_vfmsac_mask_vv_nxv4f64_nxv4f64_nxv4f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, mu
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfmsac.vv v8, v12, v16, v0.t ; CHECK-NEXT: vfmsac.vv v8, v12, v16, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x double> @llvm.riscv.vfmsac.mask.nxv4f64.nxv4f64( %a = call <vscale x 4 x double> @llvm.riscv.vfmsac.mask.nxv4f64.nxv4f64(
<vscale x 4 x double> %0, <vscale x 4 x double> %0,
<vscale x 4 x double> %1, <vscale x 4 x double> %1,
<vscale x 4 x double> %2, <vscale x 4 x double> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
iXLen %4, iXLen 0); iXLen 0, iXLen %4, iXLen 0);
ret <vscale x 4 x double> %a ret <vscale x 4 x double> %a
} }
declare <vscale x 1 x half> @llvm.riscv.vfmsac.nxv1f16.f16( declare <vscale x 1 x half> @llvm.riscv.vfmsac.nxv1f16.f16(
<vscale x 1 x half>, <vscale x 1 x half>,
half, half,
<vscale x 1 x half>, <vscale x 1 x half>,
iXLen, iXLen, iXLen, iXLen);
iXLen);
define <vscale x 1 x half> @intrinsic_vfmsac_vf_nxv1f16_f16_nxv1f16(<vscale x 1 x half> %0, half %1, <vscale x 1 x half> %2, iXLen %3) nounwind { define <vscale x 1 x half> @intrinsic_vfmsac_vf_nxv1f16_f16_nxv1f16(<vscale x 1 x half> %0, half %1, <vscale x 1 x half> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfmsac_vf_nxv1f16_f16_nxv1f16: ; CHECK-LABEL: intrinsic_vfmsac_vf_nxv1f16_f16_nxv1f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, ma ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, ma
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfmsac.vf v8, fa0, v9 ; CHECK-NEXT: vfmsac.vf v8, fa0, v9
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x half> @llvm.riscv.vfmsac.nxv1f16.f16( %a = call <vscale x 1 x half> @llvm.riscv.vfmsac.nxv1f16.f16(
<vscale x 1 x half> %0, <vscale x 1 x half> %0,
half %1, half %1,
<vscale x 1 x half> %2, <vscale x 1 x half> %2,
iXLen %3, iXLen 0) iXLen 0, iXLen %3, iXLen 0)
ret <vscale x 1 x half> %a ret <vscale x 1 x half> %a
} }
declare <vscale x 1 x half> @llvm.riscv.vfmsac.mask.nxv1f16.f16( declare <vscale x 1 x half> @llvm.riscv.vfmsac.mask.nxv1f16.f16(
<vscale x 1 x half>, <vscale x 1 x half>,
half, half,
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
iXLen, iXLen); iXLen, iXLen, iXLen);
define <vscale x 1 x half> @intrinsic_vfmsac_mask_vf_nxv1f16_f16_nxv1f16(<vscale x 1 x half> %0, half %1, <vscale x 1 x half> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind { define <vscale x 1 x half> @intrinsic_vfmsac_mask_vf_nxv1f16_f16_nxv1f16(<vscale x 1 x half> %0, half %1, <vscale x 1 x half> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfmsac_mask_vf_nxv1f16_f16_nxv1f16: ; CHECK-LABEL: intrinsic_vfmsac_mask_vf_nxv1f16_f16_nxv1f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfmsac.vf v8, fa0, v9, v0.t ; CHECK-NEXT: vfmsac.vf v8, fa0, v9, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x half> @llvm.riscv.vfmsac.mask.nxv1f16.f16( %a = call <vscale x 1 x half> @llvm.riscv.vfmsac.mask.nxv1f16.f16(
<vscale x 1 x half> %0, <vscale x 1 x half> %0,
half %1, half %1,
<vscale x 1 x half> %2, <vscale x 1 x half> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
iXLen %4, iXLen 0); iXLen 0, iXLen %4, iXLen 0);
ret <vscale x 1 x half> %a ret <vscale x 1 x half> %a
} }
declare <vscale x 2 x half> @llvm.riscv.vfmsac.nxv2f16.f16( declare <vscale x 2 x half> @llvm.riscv.vfmsac.nxv2f16.f16(
<vscale x 2 x half>, <vscale x 2 x half>,
half, half,
<vscale x 2 x half>, <vscale x 2 x half>,
iXLen, iXLen, iXLen, iXLen);
iXLen);
define <vscale x 2 x half> @intrinsic_vfmsac_vf_nxv2f16_f16_nxv2f16(<vscale x 2 x half> %0, half %1, <vscale x 2 x half> %2, iXLen %3) nounwind { define <vscale x 2 x half> @intrinsic_vfmsac_vf_nxv2f16_f16_nxv2f16(<vscale x 2 x half> %0, half %1, <vscale x 2 x half> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfmsac_vf_nxv2f16_f16_nxv2f16: ; CHECK-LABEL: intrinsic_vfmsac_vf_nxv2f16_f16_nxv2f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, ma ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, ma
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfmsac.vf v8, fa0, v9 ; CHECK-NEXT: vfmsac.vf v8, fa0, v9
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x half> @llvm.riscv.vfmsac.nxv2f16.f16( %a = call <vscale x 2 x half> @llvm.riscv.vfmsac.nxv2f16.f16(
<vscale x 2 x half> %0, <vscale x 2 x half> %0,
half %1, half %1,
<vscale x 2 x half> %2, <vscale x 2 x half> %2,
iXLen %3, iXLen 0) iXLen 0, iXLen %3, iXLen 0)
ret <vscale x 2 x half> %a ret <vscale x 2 x half> %a
} }
declare <vscale x 2 x half> @llvm.riscv.vfmsac.mask.nxv2f16.f16( declare <vscale x 2 x half> @llvm.riscv.vfmsac.mask.nxv2f16.f16(
<vscale x 2 x half>, <vscale x 2 x half>,
half, half,
<vscale x 2 x half>, <vscale x 2 x half>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
iXLen, iXLen); iXLen, iXLen, iXLen);
define <vscale x 2 x half> @intrinsic_vfmsac_mask_vf_nxv2f16_f16_nxv2f16(<vscale x 2 x half> %0, half %1, <vscale x 2 x half> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind { define <vscale x 2 x half> @intrinsic_vfmsac_mask_vf_nxv2f16_f16_nxv2f16(<vscale x 2 x half> %0, half %1, <vscale x 2 x half> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfmsac_mask_vf_nxv2f16_f16_nxv2f16: ; CHECK-LABEL: intrinsic_vfmsac_mask_vf_nxv2f16_f16_nxv2f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfmsac.vf v8, fa0, v9, v0.t ; CHECK-NEXT: vfmsac.vf v8, fa0, v9, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x half> @llvm.riscv.vfmsac.mask.nxv2f16.f16( %a = call <vscale x 2 x half> @llvm.riscv.vfmsac.mask.nxv2f16.f16(
<vscale x 2 x half> %0, <vscale x 2 x half> %0,
half %1, half %1,
<vscale x 2 x half> %2, <vscale x 2 x half> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
iXLen %4, iXLen 0); iXLen 0, iXLen %4, iXLen 0);
ret <vscale x 2 x half> %a ret <vscale x 2 x half> %a
} }
declare <vscale x 4 x half> @llvm.riscv.vfmsac.nxv4f16.f16( declare <vscale x 4 x half> @llvm.riscv.vfmsac.nxv4f16.f16(
<vscale x 4 x half>, <vscale x 4 x half>,
half, half,
<vscale x 4 x half>, <vscale x 4 x half>,
iXLen, iXLen, iXLen, iXLen);
iXLen);
define <vscale x 4 x half> @intrinsic_vfmsac_vf_nxv4f16_f16_nxv4f16(<vscale x 4 x half> %0, half %1, <vscale x 4 x half> %2, iXLen %3) nounwind { define <vscale x 4 x half> @intrinsic_vfmsac_vf_nxv4f16_f16_nxv4f16(<vscale x 4 x half> %0, half %1, <vscale x 4 x half> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfmsac_vf_nxv4f16_f16_nxv4f16: ; CHECK-LABEL: intrinsic_vfmsac_vf_nxv4f16_f16_nxv4f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, ma ; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, ma
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfmsac.vf v8, fa0, v9 ; CHECK-NEXT: vfmsac.vf v8, fa0, v9
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x half> @llvm.riscv.vfmsac.nxv4f16.f16( %a = call <vscale x 4 x half> @llvm.riscv.vfmsac.nxv4f16.f16(
<vscale x 4 x half> %0, <vscale x 4 x half> %0,
half %1, half %1,
<vscale x 4 x half> %2, <vscale x 4 x half> %2,
iXLen %3, iXLen 0) iXLen 0, iXLen %3, iXLen 0)
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 4 x half> @llvm.riscv.vfmsac.mask.nxv4f16.f16( declare <vscale x 4 x half> @llvm.riscv.vfmsac.mask.nxv4f16.f16(
<vscale x 4 x half>, <vscale x 4 x half>,
half, half,
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
iXLen, iXLen); iXLen, iXLen, iXLen);
define <vscale x 4 x half> @intrinsic_vfmsac_mask_vf_nxv4f16_f16_nxv4f16(<vscale x 4 x half> %0, half %1, <vscale x 4 x half> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind { define <vscale x 4 x half> @intrinsic_vfmsac_mask_vf_nxv4f16_f16_nxv4f16(<vscale x 4 x half> %0, half %1, <vscale x 4 x half> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfmsac_mask_vf_nxv4f16_f16_nxv4f16: ; CHECK-LABEL: intrinsic_vfmsac_mask_vf_nxv4f16_f16_nxv4f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfmsac.vf v8, fa0, v9, v0.t ; CHECK-NEXT: vfmsac.vf v8, fa0, v9, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x half> @llvm.riscv.vfmsac.mask.nxv4f16.f16( %a = call <vscale x 4 x half> @llvm.riscv.vfmsac.mask.nxv4f16.f16(
<vscale x 4 x half> %0, <vscale x 4 x half> %0,
half %1, half %1,
<vscale x 4 x half> %2, <vscale x 4 x half> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
iXLen %4, iXLen 0); iXLen 0, iXLen %4, iXLen 0);
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 8 x half> @llvm.riscv.vfmsac.nxv8f16.f16( declare <vscale x 8 x half> @llvm.riscv.vfmsac.nxv8f16.f16(
<vscale x 8 x half>, <vscale x 8 x half>,
half, half,
<vscale x 8 x half>, <vscale x 8 x half>,
iXLen, iXLen, iXLen, iXLen);
iXLen);
define <vscale x 8 x half> @intrinsic_vfmsac_vf_nxv8f16_f16_nxv8f16(<vscale x 8 x half> %0, half %1, <vscale x 8 x half> %2, iXLen %3) nounwind { define <vscale x 8 x half> @intrinsic_vfmsac_vf_nxv8f16_f16_nxv8f16(<vscale x 8 x half> %0, half %1, <vscale x 8 x half> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfmsac_vf_nxv8f16_f16_nxv8f16: ; CHECK-LABEL: intrinsic_vfmsac_vf_nxv8f16_f16_nxv8f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, ma ; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, ma
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfmsac.vf v8, fa0, v10 ; CHECK-NEXT: vfmsac.vf v8, fa0, v10
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x half> @llvm.riscv.vfmsac.nxv8f16.f16( %a = call <vscale x 8 x half> @llvm.riscv.vfmsac.nxv8f16.f16(
<vscale x 8 x half> %0, <vscale x 8 x half> %0,
half %1, half %1,
<vscale x 8 x half> %2, <vscale x 8 x half> %2,
iXLen %3, iXLen 0) iXLen 0, iXLen %3, iXLen 0)
ret <vscale x 8 x half> %a ret <vscale x 8 x half> %a
} }
declare <vscale x 8 x half> @llvm.riscv.vfmsac.mask.nxv8f16.f16( declare <vscale x 8 x half> @llvm.riscv.vfmsac.mask.nxv8f16.f16(
<vscale x 8 x half>, <vscale x 8 x half>,
half, half,
<vscale x 8 x half>, <vscale x 8 x half>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
iXLen, iXLen); iXLen, iXLen, iXLen);
define <vscale x 8 x half> @intrinsic_vfmsac_mask_vf_nxv8f16_f16_nxv8f16(<vscale x 8 x half> %0, half %1, <vscale x 8 x half> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind { define <vscale x 8 x half> @intrinsic_vfmsac_mask_vf_nxv8f16_f16_nxv8f16(<vscale x 8 x half> %0, half %1, <vscale x 8 x half> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfmsac_mask_vf_nxv8f16_f16_nxv8f16: ; CHECK-LABEL: intrinsic_vfmsac_mask_vf_nxv8f16_f16_nxv8f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, mu
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfmsac.vf v8, fa0, v10, v0.t ; CHECK-NEXT: vfmsac.vf v8, fa0, v10, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x half> @llvm.riscv.vfmsac.mask.nxv8f16.f16( %a = call <vscale x 8 x half> @llvm.riscv.vfmsac.mask.nxv8f16.f16(
<vscale x 8 x half> %0, <vscale x 8 x half> %0,
half %1, half %1,
<vscale x 8 x half> %2, <vscale x 8 x half> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
iXLen %4, iXLen 0); iXLen 0, iXLen %4, iXLen 0);
ret <vscale x 8 x half> %a ret <vscale x 8 x half> %a
} }
declare <vscale x 16 x half> @llvm.riscv.vfmsac.nxv16f16.f16( declare <vscale x 16 x half> @llvm.riscv.vfmsac.nxv16f16.f16(
<vscale x 16 x half>, <vscale x 16 x half>,
half, half,
<vscale x 16 x half>, <vscale x 16 x half>,
iXLen, iXLen, iXLen, iXLen);
iXLen);
define <vscale x 16 x half> @intrinsic_vfmsac_vf_nxv16f16_f16_nxv16f16(<vscale x 16 x half> %0, half %1, <vscale x 16 x half> %2, iXLen %3) nounwind { define <vscale x 16 x half> @intrinsic_vfmsac_vf_nxv16f16_f16_nxv16f16(<vscale x 16 x half> %0, half %1, <vscale x 16 x half> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfmsac_vf_nxv16f16_f16_nxv16f16: ; CHECK-LABEL: intrinsic_vfmsac_vf_nxv16f16_f16_nxv16f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, ma ; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, ma
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfmsac.vf v8, fa0, v12 ; CHECK-NEXT: vfmsac.vf v8, fa0, v12
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x half> @llvm.riscv.vfmsac.nxv16f16.f16( %a = call <vscale x 16 x half> @llvm.riscv.vfmsac.nxv16f16.f16(
<vscale x 16 x half> %0, <vscale x 16 x half> %0,
half %1, half %1,
<vscale x 16 x half> %2, <vscale x 16 x half> %2,
iXLen %3, iXLen 0) iXLen 0, iXLen %3, iXLen 0)
ret <vscale x 16 x half> %a ret <vscale x 16 x half> %a
} }
declare <vscale x 16 x half> @llvm.riscv.vfmsac.mask.nxv16f16.f16( declare <vscale x 16 x half> @llvm.riscv.vfmsac.mask.nxv16f16.f16(
<vscale x 16 x half>, <vscale x 16 x half>,
half, half,
<vscale x 16 x half>, <vscale x 16 x half>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
iXLen, iXLen); iXLen, iXLen, iXLen);
define <vscale x 16 x half> @intrinsic_vfmsac_mask_vf_nxv16f16_f16_nxv16f16(<vscale x 16 x half> %0, half %1, <vscale x 16 x half> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind { define <vscale x 16 x half> @intrinsic_vfmsac_mask_vf_nxv16f16_f16_nxv16f16(<vscale x 16 x half> %0, half %1, <vscale x 16 x half> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfmsac_mask_vf_nxv16f16_f16_nxv16f16: ; CHECK-LABEL: intrinsic_vfmsac_mask_vf_nxv16f16_f16_nxv16f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfmsac.vf v8, fa0, v12, v0.t ; CHECK-NEXT: vfmsac.vf v8, fa0, v12, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x half> @llvm.riscv.vfmsac.mask.nxv16f16.f16( %a = call <vscale x 16 x half> @llvm.riscv.vfmsac.mask.nxv16f16.f16(
<vscale x 16 x half> %0, <vscale x 16 x half> %0,
half %1, half %1,
<vscale x 16 x half> %2, <vscale x 16 x half> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
iXLen %4, iXLen 0); iXLen 0, iXLen %4, iXLen 0);
ret <vscale x 16 x half> %a ret <vscale x 16 x half> %a
} }
declare <vscale x 1 x float> @llvm.riscv.vfmsac.nxv1f32.f32( declare <vscale x 1 x float> @llvm.riscv.vfmsac.nxv1f32.f32(
<vscale x 1 x float>, <vscale x 1 x float>,
float, float,
<vscale x 1 x float>, <vscale x 1 x float>,
iXLen, iXLen, iXLen, iXLen);
iXLen);
define <vscale x 1 x float> @intrinsic_vfmsac_vf_nxv1f32_f32_nxv1f32(<vscale x 1 x float> %0, float %1, <vscale x 1 x float> %2, iXLen %3) nounwind { define <vscale x 1 x float> @intrinsic_vfmsac_vf_nxv1f32_f32_nxv1f32(<vscale x 1 x float> %0, float %1, <vscale x 1 x float> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfmsac_vf_nxv1f32_f32_nxv1f32: ; CHECK-LABEL: intrinsic_vfmsac_vf_nxv1f32_f32_nxv1f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, ma ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, ma
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfmsac.vf v8, fa0, v9 ; CHECK-NEXT: vfmsac.vf v8, fa0, v9
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x float> @llvm.riscv.vfmsac.nxv1f32.f32( %a = call <vscale x 1 x float> @llvm.riscv.vfmsac.nxv1f32.f32(
<vscale x 1 x float> %0, <vscale x 1 x float> %0,
float %1, float %1,
<vscale x 1 x float> %2, <vscale x 1 x float> %2,
iXLen %3, iXLen 0) iXLen 0, iXLen %3, iXLen 0)
ret <vscale x 1 x float> %a ret <vscale x 1 x float> %a
} }
declare <vscale x 1 x float> @llvm.riscv.vfmsac.mask.nxv1f32.f32( declare <vscale x 1 x float> @llvm.riscv.vfmsac.mask.nxv1f32.f32(
<vscale x 1 x float>, <vscale x 1 x float>,
float, float,
<vscale x 1 x float>, <vscale x 1 x float>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
iXLen, iXLen); iXLen, iXLen, iXLen);
define <vscale x 1 x float> @intrinsic_vfmsac_mask_vf_nxv1f32_f32_nxv1f32(<vscale x 1 x float> %0, float %1, <vscale x 1 x float> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind { define <vscale x 1 x float> @intrinsic_vfmsac_mask_vf_nxv1f32_f32_nxv1f32(<vscale x 1 x float> %0, float %1, <vscale x 1 x float> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfmsac_mask_vf_nxv1f32_f32_nxv1f32: ; CHECK-LABEL: intrinsic_vfmsac_mask_vf_nxv1f32_f32_nxv1f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfmsac.vf v8, fa0, v9, v0.t ; CHECK-NEXT: vfmsac.vf v8, fa0, v9, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x float> @llvm.riscv.vfmsac.mask.nxv1f32.f32( %a = call <vscale x 1 x float> @llvm.riscv.vfmsac.mask.nxv1f32.f32(
<vscale x 1 x float> %0, <vscale x 1 x float> %0,
float %1, float %1,
<vscale x 1 x float> %2, <vscale x 1 x float> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
iXLen %4, iXLen 0); iXLen 0, iXLen %4, iXLen 0);
ret <vscale x 1 x float> %a ret <vscale x 1 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vfmsac.nxv2f32.f32( declare <vscale x 2 x float> @llvm.riscv.vfmsac.nxv2f32.f32(
<vscale x 2 x float>, <vscale x 2 x float>,
float, float,
<vscale x 2 x float>, <vscale x 2 x float>,
iXLen, iXLen, iXLen, iXLen);
iXLen);
define <vscale x 2 x float> @intrinsic_vfmsac_vf_nxv2f32_f32_nxv2f32(<vscale x 2 x float> %0, float %1, <vscale x 2 x float> %2, iXLen %3) nounwind { define <vscale x 2 x float> @intrinsic_vfmsac_vf_nxv2f32_f32_nxv2f32(<vscale x 2 x float> %0, float %1, <vscale x 2 x float> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfmsac_vf_nxv2f32_f32_nxv2f32: ; CHECK-LABEL: intrinsic_vfmsac_vf_nxv2f32_f32_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, ma ; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, ma
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfmsac.vf v8, fa0, v9 ; CHECK-NEXT: vfmsac.vf v8, fa0, v9
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfmsac.nxv2f32.f32( %a = call <vscale x 2 x float> @llvm.riscv.vfmsac.nxv2f32.f32(
<vscale x 2 x float> %0, <vscale x 2 x float> %0,
float %1, float %1,
<vscale x 2 x float> %2, <vscale x 2 x float> %2,
iXLen %3, iXLen 0) iXLen 0, iXLen %3, iXLen 0)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vfmsac.mask.nxv2f32.f32( declare <vscale x 2 x float> @llvm.riscv.vfmsac.mask.nxv2f32.f32(
<vscale x 2 x float>, <vscale x 2 x float>,
float, float,
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
iXLen, iXLen); iXLen, iXLen, iXLen);
define <vscale x 2 x float> @intrinsic_vfmsac_mask_vf_nxv2f32_f32_nxv2f32(<vscale x 2 x float> %0, float %1, <vscale x 2 x float> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind { define <vscale x 2 x float> @intrinsic_vfmsac_mask_vf_nxv2f32_f32_nxv2f32(<vscale x 2 x float> %0, float %1, <vscale x 2 x float> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfmsac_mask_vf_nxv2f32_f32_nxv2f32: ; CHECK-LABEL: intrinsic_vfmsac_mask_vf_nxv2f32_f32_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfmsac.vf v8, fa0, v9, v0.t ; CHECK-NEXT: vfmsac.vf v8, fa0, v9, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfmsac.mask.nxv2f32.f32( %a = call <vscale x 2 x float> @llvm.riscv.vfmsac.mask.nxv2f32.f32(
<vscale x 2 x float> %0, <vscale x 2 x float> %0,
float %1, float %1,
<vscale x 2 x float> %2, <vscale x 2 x float> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
iXLen %4, iXLen 0); iXLen 0, iXLen %4, iXLen 0);
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 4 x float> @llvm.riscv.vfmsac.nxv4f32.f32( declare <vscale x 4 x float> @llvm.riscv.vfmsac.nxv4f32.f32(
<vscale x 4 x float>, <vscale x 4 x float>,
float, float,
<vscale x 4 x float>, <vscale x 4 x float>,
iXLen, iXLen, iXLen, iXLen);
iXLen);
define <vscale x 4 x float> @intrinsic_vfmsac_vf_nxv4f32_f32_nxv4f32(<vscale x 4 x float> %0, float %1, <vscale x 4 x float> %2, iXLen %3) nounwind { define <vscale x 4 x float> @intrinsic_vfmsac_vf_nxv4f32_f32_nxv4f32(<vscale x 4 x float> %0, float %1, <vscale x 4 x float> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfmsac_vf_nxv4f32_f32_nxv4f32: ; CHECK-LABEL: intrinsic_vfmsac_vf_nxv4f32_f32_nxv4f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, ma ; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, ma
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfmsac.vf v8, fa0, v10 ; CHECK-NEXT: vfmsac.vf v8, fa0, v10
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x float> @llvm.riscv.vfmsac.nxv4f32.f32( %a = call <vscale x 4 x float> @llvm.riscv.vfmsac.nxv4f32.f32(
<vscale x 4 x float> %0, <vscale x 4 x float> %0,
float %1, float %1,
<vscale x 4 x float> %2, <vscale x 4 x float> %2,
iXLen %3, iXLen 0) iXLen 0, iXLen %3, iXLen 0)
ret <vscale x 4 x float> %a ret <vscale x 4 x float> %a
} }
declare <vscale x 4 x float> @llvm.riscv.vfmsac.mask.nxv4f32.f32( declare <vscale x 4 x float> @llvm.riscv.vfmsac.mask.nxv4f32.f32(
<vscale x 4 x float>, <vscale x 4 x float>,
float, float,
<vscale x 4 x float>, <vscale x 4 x float>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
iXLen, iXLen); iXLen, iXLen, iXLen);
define <vscale x 4 x float> @intrinsic_vfmsac_mask_vf_nxv4f32_f32_nxv4f32(<vscale x 4 x float> %0, float %1, <vscale x 4 x float> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind { define <vscale x 4 x float> @intrinsic_vfmsac_mask_vf_nxv4f32_f32_nxv4f32(<vscale x 4 x float> %0, float %1, <vscale x 4 x float> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfmsac_mask_vf_nxv4f32_f32_nxv4f32: ; CHECK-LABEL: intrinsic_vfmsac_mask_vf_nxv4f32_f32_nxv4f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfmsac.vf v8, fa0, v10, v0.t ; CHECK-NEXT: vfmsac.vf v8, fa0, v10, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x float> @llvm.riscv.vfmsac.mask.nxv4f32.f32( %a = call <vscale x 4 x float> @llvm.riscv.vfmsac.mask.nxv4f32.f32(
<vscale x 4 x float> %0, <vscale x 4 x float> %0,
float %1, float %1,
<vscale x 4 x float> %2, <vscale x 4 x float> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
iXLen %4, iXLen 0); iXLen 0, iXLen %4, iXLen 0);
ret <vscale x 4 x float> %a ret <vscale x 4 x float> %a
} }
declare <vscale x 8 x float> @llvm.riscv.vfmsac.nxv8f32.f32( declare <vscale x 8 x float> @llvm.riscv.vfmsac.nxv8f32.f32(
<vscale x 8 x float>, <vscale x 8 x float>,
float, float,
<vscale x 8 x float>, <vscale x 8 x float>,
iXLen, iXLen, iXLen, iXLen);
iXLen);
define <vscale x 8 x float> @intrinsic_vfmsac_vf_nxv8f32_f32_nxv8f32(<vscale x 8 x float> %0, float %1, <vscale x 8 x float> %2, iXLen %3) nounwind { define <vscale x 8 x float> @intrinsic_vfmsac_vf_nxv8f32_f32_nxv8f32(<vscale x 8 x float> %0, float %1, <vscale x 8 x float> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfmsac_vf_nxv8f32_f32_nxv8f32: ; CHECK-LABEL: intrinsic_vfmsac_vf_nxv8f32_f32_nxv8f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, ma ; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, ma
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfmsac.vf v8, fa0, v12 ; CHECK-NEXT: vfmsac.vf v8, fa0, v12
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x float> @llvm.riscv.vfmsac.nxv8f32.f32( %a = call <vscale x 8 x float> @llvm.riscv.vfmsac.nxv8f32.f32(
<vscale x 8 x float> %0, <vscale x 8 x float> %0,
float %1, float %1,
<vscale x 8 x float> %2, <vscale x 8 x float> %2,
iXLen %3, iXLen 0) iXLen 0, iXLen %3, iXLen 0)
ret <vscale x 8 x float> %a ret <vscale x 8 x float> %a
} }
declare <vscale x 8 x float> @llvm.riscv.vfmsac.mask.nxv8f32.f32( declare <vscale x 8 x float> @llvm.riscv.vfmsac.mask.nxv8f32.f32(
<vscale x 8 x float>, <vscale x 8 x float>,
float, float,
<vscale x 8 x float>, <vscale x 8 x float>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
iXLen, iXLen); iXLen, iXLen, iXLen);
define <vscale x 8 x float> @intrinsic_vfmsac_mask_vf_nxv8f32_f32_nxv8f32(<vscale x 8 x float> %0, float %1, <vscale x 8 x float> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind { define <vscale x 8 x float> @intrinsic_vfmsac_mask_vf_nxv8f32_f32_nxv8f32(<vscale x 8 x float> %0, float %1, <vscale x 8 x float> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfmsac_mask_vf_nxv8f32_f32_nxv8f32: ; CHECK-LABEL: intrinsic_vfmsac_mask_vf_nxv8f32_f32_nxv8f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfmsac.vf v8, fa0, v12, v0.t ; CHECK-NEXT: vfmsac.vf v8, fa0, v12, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x float> @llvm.riscv.vfmsac.mask.nxv8f32.f32( %a = call <vscale x 8 x float> @llvm.riscv.vfmsac.mask.nxv8f32.f32(
<vscale x 8 x float> %0, <vscale x 8 x float> %0,
float %1, float %1,
<vscale x 8 x float> %2, <vscale x 8 x float> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
iXLen %4, iXLen 0); iXLen 0, iXLen %4, iXLen 0);
ret <vscale x 8 x float> %a ret <vscale x 8 x float> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vfmsac.nxv1f64.f64( declare <vscale x 1 x double> @llvm.riscv.vfmsac.nxv1f64.f64(
<vscale x 1 x double>, <vscale x 1 x double>,
double, double,
<vscale x 1 x double>, <vscale x 1 x double>,
iXLen, iXLen, iXLen, iXLen);
iXLen);
define <vscale x 1 x double> @intrinsic_vfmsac_vf_nxv1f64_f64_nxv1f64(<vscale x 1 x double> %0, double %1, <vscale x 1 x double> %2, iXLen %3) nounwind { define <vscale x 1 x double> @intrinsic_vfmsac_vf_nxv1f64_f64_nxv1f64(<vscale x 1 x double> %0, double %1, <vscale x 1 x double> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfmsac_vf_nxv1f64_f64_nxv1f64: ; CHECK-LABEL: intrinsic_vfmsac_vf_nxv1f64_f64_nxv1f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, ma ; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, ma
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfmsac.vf v8, fa0, v9 ; CHECK-NEXT: vfmsac.vf v8, fa0, v9
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfmsac.nxv1f64.f64( %a = call <vscale x 1 x double> @llvm.riscv.vfmsac.nxv1f64.f64(
<vscale x 1 x double> %0, <vscale x 1 x double> %0,
double %1, double %1,
<vscale x 1 x double> %2, <vscale x 1 x double> %2,
iXLen %3, iXLen 0) iXLen 0, iXLen %3, iXLen 0)
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vfmsac.mask.nxv1f64.f64( declare <vscale x 1 x double> @llvm.riscv.vfmsac.mask.nxv1f64.f64(
<vscale x 1 x double>, <vscale x 1 x double>,
double, double,
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
iXLen, iXLen); iXLen, iXLen, iXLen);
define <vscale x 1 x double> @intrinsic_vfmsac_mask_vf_nxv1f64_f64_nxv1f64(<vscale x 1 x double> %0, double %1, <vscale x 1 x double> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind { define <vscale x 1 x double> @intrinsic_vfmsac_mask_vf_nxv1f64_f64_nxv1f64(<vscale x 1 x double> %0, double %1, <vscale x 1 x double> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfmsac_mask_vf_nxv1f64_f64_nxv1f64: ; CHECK-LABEL: intrinsic_vfmsac_mask_vf_nxv1f64_f64_nxv1f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, mu
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfmsac.vf v8, fa0, v9, v0.t ; CHECK-NEXT: vfmsac.vf v8, fa0, v9, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfmsac.mask.nxv1f64.f64( %a = call <vscale x 1 x double> @llvm.riscv.vfmsac.mask.nxv1f64.f64(
<vscale x 1 x double> %0, <vscale x 1 x double> %0,
double %1, double %1,
<vscale x 1 x double> %2, <vscale x 1 x double> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
iXLen %4, iXLen 0); iXLen 0, iXLen %4, iXLen 0);
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 2 x double> @llvm.riscv.vfmsac.nxv2f64.f64( declare <vscale x 2 x double> @llvm.riscv.vfmsac.nxv2f64.f64(
<vscale x 2 x double>, <vscale x 2 x double>,
double, double,
<vscale x 2 x double>, <vscale x 2 x double>,
iXLen, iXLen, iXLen, iXLen);
iXLen);
define <vscale x 2 x double> @intrinsic_vfmsac_vf_nxv2f64_f64_nxv2f64(<vscale x 2 x double> %0, double %1, <vscale x 2 x double> %2, iXLen %3) nounwind { define <vscale x 2 x double> @intrinsic_vfmsac_vf_nxv2f64_f64_nxv2f64(<vscale x 2 x double> %0, double %1, <vscale x 2 x double> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfmsac_vf_nxv2f64_f64_nxv2f64: ; CHECK-LABEL: intrinsic_vfmsac_vf_nxv2f64_f64_nxv2f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, ma ; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, ma
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfmsac.vf v8, fa0, v10 ; CHECK-NEXT: vfmsac.vf v8, fa0, v10
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x double> @llvm.riscv.vfmsac.nxv2f64.f64( %a = call <vscale x 2 x double> @llvm.riscv.vfmsac.nxv2f64.f64(
<vscale x 2 x double> %0, <vscale x 2 x double> %0,
double %1, double %1,
<vscale x 2 x double> %2, <vscale x 2 x double> %2,
iXLen %3, iXLen 0) iXLen 0, iXLen %3, iXLen 0)
ret <vscale x 2 x double> %a ret <vscale x 2 x double> %a
} }
declare <vscale x 2 x double> @llvm.riscv.vfmsac.mask.nxv2f64.f64( declare <vscale x 2 x double> @llvm.riscv.vfmsac.mask.nxv2f64.f64(
<vscale x 2 x double>, <vscale x 2 x double>,
double, double,
<vscale x 2 x double>, <vscale x 2 x double>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
iXLen, iXLen); iXLen, iXLen, iXLen);
define <vscale x 2 x double> @intrinsic_vfmsac_mask_vf_nxv2f64_f64_nxv2f64(<vscale x 2 x double> %0, double %1, <vscale x 2 x double> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind { define <vscale x 2 x double> @intrinsic_vfmsac_mask_vf_nxv2f64_f64_nxv2f64(<vscale x 2 x double> %0, double %1, <vscale x 2 x double> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfmsac_mask_vf_nxv2f64_f64_nxv2f64: ; CHECK-LABEL: intrinsic_vfmsac_mask_vf_nxv2f64_f64_nxv2f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, mu
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfmsac.vf v8, fa0, v10, v0.t ; CHECK-NEXT: vfmsac.vf v8, fa0, v10, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x double> @llvm.riscv.vfmsac.mask.nxv2f64.f64( %a = call <vscale x 2 x double> @llvm.riscv.vfmsac.mask.nxv2f64.f64(
<vscale x 2 x double> %0, <vscale x 2 x double> %0,
double %1, double %1,
<vscale x 2 x double> %2, <vscale x 2 x double> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
iXLen %4, iXLen 0); iXLen 0, iXLen %4, iXLen 0);
ret <vscale x 2 x double> %a ret <vscale x 2 x double> %a
} }
declare <vscale x 4 x double> @llvm.riscv.vfmsac.nxv4f64.f64( declare <vscale x 4 x double> @llvm.riscv.vfmsac.nxv4f64.f64(
<vscale x 4 x double>, <vscale x 4 x double>,
double, double,
<vscale x 4 x double>, <vscale x 4 x double>,
iXLen, iXLen, iXLen, iXLen);
iXLen);
define <vscale x 4 x double> @intrinsic_vfmsac_vf_nxv4f64_f64_nxv4f64(<vscale x 4 x double> %0, double %1, <vscale x 4 x double> %2, iXLen %3) nounwind { define <vscale x 4 x double> @intrinsic_vfmsac_vf_nxv4f64_f64_nxv4f64(<vscale x 4 x double> %0, double %1, <vscale x 4 x double> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfmsac_vf_nxv4f64_f64_nxv4f64: ; CHECK-LABEL: intrinsic_vfmsac_vf_nxv4f64_f64_nxv4f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, ma ; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, ma
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfmsac.vf v8, fa0, v12 ; CHECK-NEXT: vfmsac.vf v8, fa0, v12
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x double> @llvm.riscv.vfmsac.nxv4f64.f64( %a = call <vscale x 4 x double> @llvm.riscv.vfmsac.nxv4f64.f64(
<vscale x 4 x double> %0, <vscale x 4 x double> %0,
double %1, double %1,
<vscale x 4 x double> %2, <vscale x 4 x double> %2,
iXLen %3, iXLen 0) iXLen 0, iXLen %3, iXLen 0)
ret <vscale x 4 x double> %a ret <vscale x 4 x double> %a
} }
declare <vscale x 4 x double> @llvm.riscv.vfmsac.mask.nxv4f64.f64( declare <vscale x 4 x double> @llvm.riscv.vfmsac.mask.nxv4f64.f64(
<vscale x 4 x double>, <vscale x 4 x double>,
double, double,
<vscale x 4 x double>, <vscale x 4 x double>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
iXLen, iXLen); iXLen, iXLen, iXLen);
define <vscale x 4 x double> @intrinsic_vfmsac_mask_vf_nxv4f64_f64_nxv4f64(<vscale x 4 x double> %0, double %1, <vscale x 4 x double> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind { define <vscale x 4 x double> @intrinsic_vfmsac_mask_vf_nxv4f64_f64_nxv4f64(<vscale x 4 x double> %0, double %1, <vscale x 4 x double> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfmsac_mask_vf_nxv4f64_f64_nxv4f64: ; CHECK-LABEL: intrinsic_vfmsac_mask_vf_nxv4f64_f64_nxv4f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, mu
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfmsac.vf v8, fa0, v12, v0.t ; CHECK-NEXT: vfmsac.vf v8, fa0, v12, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x double> @llvm.riscv.vfmsac.mask.nxv4f64.f64( %a = call <vscale x 4 x double> @llvm.riscv.vfmsac.mask.nxv4f64.f64(
<vscale x 4 x double> %0, <vscale x 4 x double> %0,
double %1, double %1,
<vscale x 4 x double> %2, <vscale x 4 x double> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
iXLen %4, iXLen 0); iXLen 0, iXLen %4, iXLen 0);
ret <vscale x 4 x double> %a ret <vscale x 4 x double> %a
} }

llvm/test/CodeGen/RISCV/rvv/vfmsub.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zfh,+experimental-zvfh \ ; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zfh,+experimental-zvfh \
; RUN: -verify-machineinstrs -target-abi=ilp32d | FileCheck %s ; RUN: -verify-machineinstrs -target-abi=ilp32d | FileCheck %s
; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zfh,+experimental-zvfh \ ; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zfh,+experimental-zvfh \
; RUN: -verify-machineinstrs -target-abi=lp64d | FileCheck %s ; RUN: -verify-machineinstrs -target-abi=lp64d | FileCheck %s
declare <vscale x 1 x half> @llvm.riscv.vfmsub.nxv1f16.nxv1f16( declare <vscale x 1 x half> @llvm.riscv.vfmsub.nxv1f16.nxv1f16(
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x half>, <vscale x 1 x half>,
iXLen, iXLen, iXLen, iXLen);
iXLen);
define <vscale x 1 x half> @intrinsic_vfmsub_vv_nxv1f16_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, iXLen %3) nounwind { define <vscale x 1 x half> @intrinsic_vfmsub_vv_nxv1f16_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfmsub_vv_nxv1f16_nxv1f16_nxv1f16: ; CHECK-LABEL: intrinsic_vfmsub_vv_nxv1f16_nxv1f16_nxv1f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, ma ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, ma
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfmsub.vv v8, v9, v10 ; CHECK-NEXT: vfmsub.vv v8, v9, v10
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x half> @llvm.riscv.vfmsub.nxv1f16.nxv1f16( %a = call <vscale x 1 x half> @llvm.riscv.vfmsub.nxv1f16.nxv1f16(
<vscale x 1 x half> %0, <vscale x 1 x half> %0,
<vscale x 1 x half> %1, <vscale x 1 x half> %1,
<vscale x 1 x half> %2, <vscale x 1 x half> %2,
iXLen %3, iXLen 0) iXLen 0, iXLen %3, iXLen 0)
ret <vscale x 1 x half> %a ret <vscale x 1 x half> %a
} }
declare <vscale x 1 x half> @llvm.riscv.vfmsub.mask.nxv1f16.nxv1f16( declare <vscale x 1 x half> @llvm.riscv.vfmsub.mask.nxv1f16.nxv1f16(
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
iXLen, iXLen); iXLen, iXLen, iXLen);
define <vscale x 1 x half> @intrinsic_vfmsub_mask_vv_nxv1f16_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind { define <vscale x 1 x half> @intrinsic_vfmsub_mask_vv_nxv1f16_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfmsub_mask_vv_nxv1f16_nxv1f16_nxv1f16: ; CHECK-LABEL: intrinsic_vfmsub_mask_vv_nxv1f16_nxv1f16_nxv1f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfmsub.vv v8, v9, v10, v0.t ; CHECK-NEXT: vfmsub.vv v8, v9, v10, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x half> @llvm.riscv.vfmsub.mask.nxv1f16.nxv1f16( %a = call <vscale x 1 x half> @llvm.riscv.vfmsub.mask.nxv1f16.nxv1f16(
<vscale x 1 x half> %0, <vscale x 1 x half> %0,
<vscale x 1 x half> %1, <vscale x 1 x half> %1,
<vscale x 1 x half> %2, <vscale x 1 x half> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
iXLen %4, iXLen 0); iXLen 0, iXLen %4, iXLen 0);
ret <vscale x 1 x half> %a ret <vscale x 1 x half> %a
} }
declare <vscale x 2 x half> @llvm.riscv.vfmsub.nxv2f16.nxv2f16( declare <vscale x 2 x half> @llvm.riscv.vfmsub.nxv2f16.nxv2f16(
<vscale x 2 x half>, <vscale x 2 x half>,
<vscale x 2 x half>, <vscale x 2 x half>,
<vscale x 2 x half>, <vscale x 2 x half>,
iXLen, iXLen, iXLen, iXLen);
iXLen);
define <vscale x 2 x half> @intrinsic_vfmsub_vv_nxv2f16_nxv2f16_nxv2f16(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, iXLen %3) nounwind { define <vscale x 2 x half> @intrinsic_vfmsub_vv_nxv2f16_nxv2f16_nxv2f16(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfmsub_vv_nxv2f16_nxv2f16_nxv2f16: ; CHECK-LABEL: intrinsic_vfmsub_vv_nxv2f16_nxv2f16_nxv2f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, ma ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, ma
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfmsub.vv v8, v9, v10 ; CHECK-NEXT: vfmsub.vv v8, v9, v10
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x half> @llvm.riscv.vfmsub.nxv2f16.nxv2f16( %a = call <vscale x 2 x half> @llvm.riscv.vfmsub.nxv2f16.nxv2f16(
<vscale x 2 x half> %0, <vscale x 2 x half> %0,
<vscale x 2 x half> %1, <vscale x 2 x half> %1,
<vscale x 2 x half> %2, <vscale x 2 x half> %2,
iXLen %3, iXLen 0) iXLen 0, iXLen %3, iXLen 0)
ret <vscale x 2 x half> %a ret <vscale x 2 x half> %a
} }
declare <vscale x 2 x half> @llvm.riscv.vfmsub.mask.nxv2f16.nxv2f16( declare <vscale x 2 x half> @llvm.riscv.vfmsub.mask.nxv2f16.nxv2f16(
<vscale x 2 x half>, <vscale x 2 x half>,
<vscale x 2 x half>, <vscale x 2 x half>,
<vscale x 2 x half>, <vscale x 2 x half>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
iXLen, iXLen); iXLen, iXLen, iXLen);
define <vscale x 2 x half> @intrinsic_vfmsub_mask_vv_nxv2f16_nxv2f16_nxv2f16(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind { define <vscale x 2 x half> @intrinsic_vfmsub_mask_vv_nxv2f16_nxv2f16_nxv2f16(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfmsub_mask_vv_nxv2f16_nxv2f16_nxv2f16: ; CHECK-LABEL: intrinsic_vfmsub_mask_vv_nxv2f16_nxv2f16_nxv2f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfmsub.vv v8, v9, v10, v0.t ; CHECK-NEXT: vfmsub.vv v8, v9, v10, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x half> @llvm.riscv.vfmsub.mask.nxv2f16.nxv2f16( %a = call <vscale x 2 x half> @llvm.riscv.vfmsub.mask.nxv2f16.nxv2f16(
<vscale x 2 x half> %0, <vscale x 2 x half> %0,
<vscale x 2 x half> %1, <vscale x 2 x half> %1,
<vscale x 2 x half> %2, <vscale x 2 x half> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
iXLen %4, iXLen 0); iXLen 0, iXLen %4, iXLen 0);
ret <vscale x 2 x half> %a ret <vscale x 2 x half> %a
} }
declare <vscale x 4 x half> @llvm.riscv.vfmsub.nxv4f16.nxv4f16( declare <vscale x 4 x half> @llvm.riscv.vfmsub.nxv4f16.nxv4f16(
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 4 x half>, <vscale x 4 x half>,
iXLen, iXLen, iXLen, iXLen);
iXLen);
define <vscale x 4 x half> @intrinsic_vfmsub_vv_nxv4f16_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, iXLen %3) nounwind { define <vscale x 4 x half> @intrinsic_vfmsub_vv_nxv4f16_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfmsub_vv_nxv4f16_nxv4f16_nxv4f16: ; CHECK-LABEL: intrinsic_vfmsub_vv_nxv4f16_nxv4f16_nxv4f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, ma ; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, ma
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfmsub.vv v8, v9, v10 ; CHECK-NEXT: vfmsub.vv v8, v9, v10
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x half> @llvm.riscv.vfmsub.nxv4f16.nxv4f16( %a = call <vscale x 4 x half> @llvm.riscv.vfmsub.nxv4f16.nxv4f16(
<vscale x 4 x half> %0, <vscale x 4 x half> %0,
<vscale x 4 x half> %1, <vscale x 4 x half> %1,
<vscale x 4 x half> %2, <vscale x 4 x half> %2,
iXLen %3, iXLen 0) iXLen 0, iXLen %3, iXLen 0)
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 4 x half> @llvm.riscv.vfmsub.mask.nxv4f16.nxv4f16( declare <vscale x 4 x half> @llvm.riscv.vfmsub.mask.nxv4f16.nxv4f16(
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
iXLen, iXLen); iXLen, iXLen, iXLen);
define <vscale x 4 x half> @intrinsic_vfmsub_mask_vv_nxv4f16_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind { define <vscale x 4 x half> @intrinsic_vfmsub_mask_vv_nxv4f16_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfmsub_mask_vv_nxv4f16_nxv4f16_nxv4f16: ; CHECK-LABEL: intrinsic_vfmsub_mask_vv_nxv4f16_nxv4f16_nxv4f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfmsub.vv v8, v9, v10, v0.t ; CHECK-NEXT: vfmsub.vv v8, v9, v10, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x half> @llvm.riscv.vfmsub.mask.nxv4f16.nxv4f16( %a = call <vscale x 4 x half> @llvm.riscv.vfmsub.mask.nxv4f16.nxv4f16(
<vscale x 4 x half> %0, <vscale x 4 x half> %0,
<vscale x 4 x half> %1, <vscale x 4 x half> %1,
<vscale x 4 x half> %2, <vscale x 4 x half> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
iXLen %4, iXLen 0); iXLen 0, iXLen %4, iXLen 0);
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 8 x half> @llvm.riscv.vfmsub.nxv8f16.nxv8f16( declare <vscale x 8 x half> @llvm.riscv.vfmsub.nxv8f16.nxv8f16(
<vscale x 8 x half>, <vscale x 8 x half>,
<vscale x 8 x half>, <vscale x 8 x half>,
<vscale x 8 x half>, <vscale x 8 x half>,
iXLen, iXLen, iXLen, iXLen);
iXLen);
define <vscale x 8 x half> @intrinsic_vfmsub_vv_nxv8f16_nxv8f16_nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, iXLen %3) nounwind { define <vscale x 8 x half> @intrinsic_vfmsub_vv_nxv8f16_nxv8f16_nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfmsub_vv_nxv8f16_nxv8f16_nxv8f16: ; CHECK-LABEL: intrinsic_vfmsub_vv_nxv8f16_nxv8f16_nxv8f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, ma ; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, ma
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfmsub.vv v8, v10, v12 ; CHECK-NEXT: vfmsub.vv v8, v10, v12
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x half> @llvm.riscv.vfmsub.nxv8f16.nxv8f16( %a = call <vscale x 8 x half> @llvm.riscv.vfmsub.nxv8f16.nxv8f16(
<vscale x 8 x half> %0, <vscale x 8 x half> %0,
<vscale x 8 x half> %1, <vscale x 8 x half> %1,
<vscale x 8 x half> %2, <vscale x 8 x half> %2,
iXLen %3, iXLen 0) iXLen 0, iXLen %3, iXLen 0)
ret <vscale x 8 x half> %a ret <vscale x 8 x half> %a
} }
declare <vscale x 8 x half> @llvm.riscv.vfmsub.mask.nxv8f16.nxv8f16( declare <vscale x 8 x half> @llvm.riscv.vfmsub.mask.nxv8f16.nxv8f16(
<vscale x 8 x half>, <vscale x 8 x half>,
<vscale x 8 x half>, <vscale x 8 x half>,
<vscale x 8 x half>, <vscale x 8 x half>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
iXLen, iXLen); iXLen, iXLen, iXLen);
define <vscale x 8 x half> @intrinsic_vfmsub_mask_vv_nxv8f16_nxv8f16_nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind { define <vscale x 8 x half> @intrinsic_vfmsub_mask_vv_nxv8f16_nxv8f16_nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfmsub_mask_vv_nxv8f16_nxv8f16_nxv8f16: ; CHECK-LABEL: intrinsic_vfmsub_mask_vv_nxv8f16_nxv8f16_nxv8f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, mu
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfmsub.vv v8, v10, v12, v0.t ; CHECK-NEXT: vfmsub.vv v8, v10, v12, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x half> @llvm.riscv.vfmsub.mask.nxv8f16.nxv8f16( %a = call <vscale x 8 x half> @llvm.riscv.vfmsub.mask.nxv8f16.nxv8f16(
<vscale x 8 x half> %0, <vscale x 8 x half> %0,
<vscale x 8 x half> %1, <vscale x 8 x half> %1,
<vscale x 8 x half> %2, <vscale x 8 x half> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
iXLen %4, iXLen 0); iXLen 0, iXLen %4, iXLen 0);
ret <vscale x 8 x half> %a ret <vscale x 8 x half> %a
} }
declare <vscale x 16 x half> @llvm.riscv.vfmsub.nxv16f16.nxv16f16( declare <vscale x 16 x half> @llvm.riscv.vfmsub.nxv16f16.nxv16f16(
<vscale x 16 x half>, <vscale x 16 x half>,
<vscale x 16 x half>, <vscale x 16 x half>,
<vscale x 16 x half>, <vscale x 16 x half>,
iXLen, iXLen, iXLen, iXLen);
iXLen);
define <vscale x 16 x half> @intrinsic_vfmsub_vv_nxv16f16_nxv16f16_nxv16f16(<vscale x 16 x half> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %2, iXLen %3) nounwind { define <vscale x 16 x half> @intrinsic_vfmsub_vv_nxv16f16_nxv16f16_nxv16f16(<vscale x 16 x half> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfmsub_vv_nxv16f16_nxv16f16_nxv16f16: ; CHECK-LABEL: intrinsic_vfmsub_vv_nxv16f16_nxv16f16_nxv16f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, ma ; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, ma
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfmsub.vv v8, v12, v16 ; CHECK-NEXT: vfmsub.vv v8, v12, v16
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x half> @llvm.riscv.vfmsub.nxv16f16.nxv16f16( %a = call <vscale x 16 x half> @llvm.riscv.vfmsub.nxv16f16.nxv16f16(
<vscale x 16 x half> %0, <vscale x 16 x half> %0,
<vscale x 16 x half> %1, <vscale x 16 x half> %1,
<vscale x 16 x half> %2, <vscale x 16 x half> %2,
iXLen %3, iXLen 0) iXLen 0, iXLen %3, iXLen 0)
ret <vscale x 16 x half> %a ret <vscale x 16 x half> %a
} }
declare <vscale x 16 x half> @llvm.riscv.vfmsub.mask.nxv16f16.nxv16f16( declare <vscale x 16 x half> @llvm.riscv.vfmsub.mask.nxv16f16.nxv16f16(
<vscale x 16 x half>, <vscale x 16 x half>,
<vscale x 16 x half>, <vscale x 16 x half>,
<vscale x 16 x half>, <vscale x 16 x half>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
iXLen, iXLen); iXLen, iXLen, iXLen);
define <vscale x 16 x half> @intrinsic_vfmsub_mask_vv_nxv16f16_nxv16f16_nxv16f16(<vscale x 16 x half> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind { define <vscale x 16 x half> @intrinsic_vfmsub_mask_vv_nxv16f16_nxv16f16_nxv16f16(<vscale x 16 x half> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfmsub_mask_vv_nxv16f16_nxv16f16_nxv16f16: ; CHECK-LABEL: intrinsic_vfmsub_mask_vv_nxv16f16_nxv16f16_nxv16f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfmsub.vv v8, v12, v16, v0.t ; CHECK-NEXT: vfmsub.vv v8, v12, v16, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x half> @llvm.riscv.vfmsub.mask.nxv16f16.nxv16f16( %a = call <vscale x 16 x half> @llvm.riscv.vfmsub.mask.nxv16f16.nxv16f16(
<vscale x 16 x half> %0, <vscale x 16 x half> %0,
<vscale x 16 x half> %1, <vscale x 16 x half> %1,
<vscale x 16 x half> %2, <vscale x 16 x half> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
iXLen %4, iXLen 0); iXLen 0, iXLen %4, iXLen 0);
ret <vscale x 16 x half> %a ret <vscale x 16 x half> %a
} }
declare <vscale x 1 x float> @llvm.riscv.vfmsub.nxv1f32.nxv1f32( declare <vscale x 1 x float> @llvm.riscv.vfmsub.nxv1f32.nxv1f32(
<vscale x 1 x float>, <vscale x 1 x float>,
<vscale x 1 x float>, <vscale x 1 x float>,
<vscale x 1 x float>, <vscale x 1 x float>,
iXLen, iXLen, iXLen, iXLen);
iXLen);
define <vscale x 1 x float> @intrinsic_vfmsub_vv_nxv1f32_nxv1f32_nxv1f32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, iXLen %3) nounwind { define <vscale x 1 x float> @intrinsic_vfmsub_vv_nxv1f32_nxv1f32_nxv1f32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfmsub_vv_nxv1f32_nxv1f32_nxv1f32: ; CHECK-LABEL: intrinsic_vfmsub_vv_nxv1f32_nxv1f32_nxv1f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, ma ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, ma
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfmsub.vv v8, v9, v10 ; CHECK-NEXT: vfmsub.vv v8, v9, v10
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x float> @llvm.riscv.vfmsub.nxv1f32.nxv1f32( %a = call <vscale x 1 x float> @llvm.riscv.vfmsub.nxv1f32.nxv1f32(
<vscale x 1 x float> %0, <vscale x 1 x float> %0,
<vscale x 1 x float> %1, <vscale x 1 x float> %1,
<vscale x 1 x float> %2, <vscale x 1 x float> %2,
iXLen %3, iXLen 0) iXLen 0, iXLen %3, iXLen 0)
ret <vscale x 1 x float> %a ret <vscale x 1 x float> %a
} }
declare <vscale x 1 x float> @llvm.riscv.vfmsub.mask.nxv1f32.nxv1f32( declare <vscale x 1 x float> @llvm.riscv.vfmsub.mask.nxv1f32.nxv1f32(
<vscale x 1 x float>, <vscale x 1 x float>,
<vscale x 1 x float>, <vscale x 1 x float>,
<vscale x 1 x float>, <vscale x 1 x float>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
iXLen, iXLen); iXLen, iXLen, iXLen);
define <vscale x 1 x float> @intrinsic_vfmsub_mask_vv_nxv1f32_nxv1f32_nxv1f32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind { define <vscale x 1 x float> @intrinsic_vfmsub_mask_vv_nxv1f32_nxv1f32_nxv1f32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfmsub_mask_vv_nxv1f32_nxv1f32_nxv1f32: ; CHECK-LABEL: intrinsic_vfmsub_mask_vv_nxv1f32_nxv1f32_nxv1f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfmsub.vv v8, v9, v10, v0.t ; CHECK-NEXT: vfmsub.vv v8, v9, v10, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x float> @llvm.riscv.vfmsub.mask.nxv1f32.nxv1f32( %a = call <vscale x 1 x float> @llvm.riscv.vfmsub.mask.nxv1f32.nxv1f32(
<vscale x 1 x float> %0, <vscale x 1 x float> %0,
<vscale x 1 x float> %1, <vscale x 1 x float> %1,
<vscale x 1 x float> %2, <vscale x 1 x float> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
iXLen %4, iXLen 0); iXLen 0, iXLen %4, iXLen 0);
ret <vscale x 1 x float> %a ret <vscale x 1 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vfmsub.nxv2f32.nxv2f32( declare <vscale x 2 x float> @llvm.riscv.vfmsub.nxv2f32.nxv2f32(
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 2 x float>, <vscale x 2 x float>,
iXLen, iXLen, iXLen, iXLen);
iXLen);
define <vscale x 2 x float> @intrinsic_vfmsub_vv_nxv2f32_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, iXLen %3) nounwind { define <vscale x 2 x float> @intrinsic_vfmsub_vv_nxv2f32_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfmsub_vv_nxv2f32_nxv2f32_nxv2f32: ; CHECK-LABEL: intrinsic_vfmsub_vv_nxv2f32_nxv2f32_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, ma ; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, ma
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfmsub.vv v8, v9, v10 ; CHECK-NEXT: vfmsub.vv v8, v9, v10
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfmsub.nxv2f32.nxv2f32( %a = call <vscale x 2 x float> @llvm.riscv.vfmsub.nxv2f32.nxv2f32(
<vscale x 2 x float> %0, <vscale x 2 x float> %0,
<vscale x 2 x float> %1, <vscale x 2 x float> %1,
<vscale x 2 x float> %2, <vscale x 2 x float> %2,
iXLen %3, iXLen 0) iXLen 0, iXLen %3, iXLen 0)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vfmsub.mask.nxv2f32.nxv2f32( declare <vscale x 2 x float> @llvm.riscv.vfmsub.mask.nxv2f32.nxv2f32(
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
iXLen, iXLen); iXLen, iXLen, iXLen);
define <vscale x 2 x float> @intrinsic_vfmsub_mask_vv_nxv2f32_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind { define <vscale x 2 x float> @intrinsic_vfmsub_mask_vv_nxv2f32_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfmsub_mask_vv_nxv2f32_nxv2f32_nxv2f32: ; CHECK-LABEL: intrinsic_vfmsub_mask_vv_nxv2f32_nxv2f32_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfmsub.vv v8, v9, v10, v0.t ; CHECK-NEXT: vfmsub.vv v8, v9, v10, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfmsub.mask.nxv2f32.nxv2f32( %a = call <vscale x 2 x float> @llvm.riscv.vfmsub.mask.nxv2f32.nxv2f32(
<vscale x 2 x float> %0, <vscale x 2 x float> %0,
<vscale x 2 x float> %1, <vscale x 2 x float> %1,
<vscale x 2 x float> %2, <vscale x 2 x float> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
iXLen %4, iXLen 0); iXLen 0, iXLen %4, iXLen 0);
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 4 x float> @llvm.riscv.vfmsub.nxv4f32.nxv4f32( declare <vscale x 4 x float> @llvm.riscv.vfmsub.nxv4f32.nxv4f32(
<vscale x 4 x float>, <vscale x 4 x float>,
<vscale x 4 x float>, <vscale x 4 x float>,
<vscale x 4 x float>, <vscale x 4 x float>,
iXLen, iXLen, iXLen, iXLen);
iXLen);
define <vscale x 4 x float> @intrinsic_vfmsub_vv_nxv4f32_nxv4f32_nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, <vscale x 4 x float> %2, iXLen %3) nounwind { define <vscale x 4 x float> @intrinsic_vfmsub_vv_nxv4f32_nxv4f32_nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, <vscale x 4 x float> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfmsub_vv_nxv4f32_nxv4f32_nxv4f32: ; CHECK-LABEL: intrinsic_vfmsub_vv_nxv4f32_nxv4f32_nxv4f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, ma ; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, ma
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfmsub.vv v8, v10, v12 ; CHECK-NEXT: vfmsub.vv v8, v10, v12
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x float> @llvm.riscv.vfmsub.nxv4f32.nxv4f32( %a = call <vscale x 4 x float> @llvm.riscv.vfmsub.nxv4f32.nxv4f32(
<vscale x 4 x float> %0, <vscale x 4 x float> %0,
<vscale x 4 x float> %1, <vscale x 4 x float> %1,
<vscale x 4 x float> %2, <vscale x 4 x float> %2,
iXLen %3, iXLen 0) iXLen 0, iXLen %3, iXLen 0)
ret <vscale x 4 x float> %a ret <vscale x 4 x float> %a
} }
declare <vscale x 4 x float> @llvm.riscv.vfmsub.mask.nxv4f32.nxv4f32( declare <vscale x 4 x float> @llvm.riscv.vfmsub.mask.nxv4f32.nxv4f32(
<vscale x 4 x float>, <vscale x 4 x float>,
<vscale x 4 x float>, <vscale x 4 x float>,
<vscale x 4 x float>, <vscale x 4 x float>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
iXLen, iXLen); iXLen, iXLen, iXLen);
define <vscale x 4 x float> @intrinsic_vfmsub_mask_vv_nxv4f32_nxv4f32_nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, <vscale x 4 x float> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind { define <vscale x 4 x float> @intrinsic_vfmsub_mask_vv_nxv4f32_nxv4f32_nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, <vscale x 4 x float> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfmsub_mask_vv_nxv4f32_nxv4f32_nxv4f32: ; CHECK-LABEL: intrinsic_vfmsub_mask_vv_nxv4f32_nxv4f32_nxv4f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfmsub.vv v8, v10, v12, v0.t ; CHECK-NEXT: vfmsub.vv v8, v10, v12, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x float> @llvm.riscv.vfmsub.mask.nxv4f32.nxv4f32( %a = call <vscale x 4 x float> @llvm.riscv.vfmsub.mask.nxv4f32.nxv4f32(
<vscale x 4 x float> %0, <vscale x 4 x float> %0,
<vscale x 4 x float> %1, <vscale x 4 x float> %1,
<vscale x 4 x float> %2, <vscale x 4 x float> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
iXLen %4, iXLen 0); iXLen 0, iXLen %4, iXLen 0);
ret <vscale x 4 x float> %a ret <vscale x 4 x float> %a
} }
declare <vscale x 8 x float> @llvm.riscv.vfmsub.nxv8f32.nxv8f32( declare <vscale x 8 x float> @llvm.riscv.vfmsub.nxv8f32.nxv8f32(
<vscale x 8 x float>, <vscale x 8 x float>,
<vscale x 8 x float>, <vscale x 8 x float>,
<vscale x 8 x float>, <vscale x 8 x float>,
iXLen, iXLen, iXLen, iXLen);
iXLen);
define <vscale x 8 x float> @intrinsic_vfmsub_vv_nxv8f32_nxv8f32_nxv8f32(<vscale x 8 x float> %0, <vscale x 8 x float> %1, <vscale x 8 x float> %2, iXLen %3) nounwind { define <vscale x 8 x float> @intrinsic_vfmsub_vv_nxv8f32_nxv8f32_nxv8f32(<vscale x 8 x float> %0, <vscale x 8 x float> %1, <vscale x 8 x float> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfmsub_vv_nxv8f32_nxv8f32_nxv8f32: ; CHECK-LABEL: intrinsic_vfmsub_vv_nxv8f32_nxv8f32_nxv8f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, ma ; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, ma
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfmsub.vv v8, v12, v16 ; CHECK-NEXT: vfmsub.vv v8, v12, v16
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x float> @llvm.riscv.vfmsub.nxv8f32.nxv8f32( %a = call <vscale x 8 x float> @llvm.riscv.vfmsub.nxv8f32.nxv8f32(
<vscale x 8 x float> %0, <vscale x 8 x float> %0,
<vscale x 8 x float> %1, <vscale x 8 x float> %1,
<vscale x 8 x float> %2, <vscale x 8 x float> %2,
iXLen %3, iXLen 0) iXLen 0, iXLen %3, iXLen 0)
ret <vscale x 8 x float> %a ret <vscale x 8 x float> %a
} }
declare <vscale x 8 x float> @llvm.riscv.vfmsub.mask.nxv8f32.nxv8f32( declare <vscale x 8 x float> @llvm.riscv.vfmsub.mask.nxv8f32.nxv8f32(
<vscale x 8 x float>, <vscale x 8 x float>,
<vscale x 8 x float>, <vscale x 8 x float>,
<vscale x 8 x float>, <vscale x 8 x float>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
iXLen, iXLen); iXLen, iXLen, iXLen);
define <vscale x 8 x float> @intrinsic_vfmsub_mask_vv_nxv8f32_nxv8f32_nxv8f32(<vscale x 8 x float> %0, <vscale x 8 x float> %1, <vscale x 8 x float> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind { define <vscale x 8 x float> @intrinsic_vfmsub_mask_vv_nxv8f32_nxv8f32_nxv8f32(<vscale x 8 x float> %0, <vscale x 8 x float> %1, <vscale x 8 x float> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfmsub_mask_vv_nxv8f32_nxv8f32_nxv8f32: ; CHECK-LABEL: intrinsic_vfmsub_mask_vv_nxv8f32_nxv8f32_nxv8f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfmsub.vv v8, v12, v16, v0.t ; CHECK-NEXT: vfmsub.vv v8, v12, v16, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x float> @llvm.riscv.vfmsub.mask.nxv8f32.nxv8f32( %a = call <vscale x 8 x float> @llvm.riscv.vfmsub.mask.nxv8f32.nxv8f32(
<vscale x 8 x float> %0, <vscale x 8 x float> %0,
<vscale x 8 x float> %1, <vscale x 8 x float> %1,
<vscale x 8 x float> %2, <vscale x 8 x float> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
iXLen %4, iXLen 0); iXLen 0, iXLen %4, iXLen 0);
ret <vscale x 8 x float> %a ret <vscale x 8 x float> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vfmsub.nxv1f64.nxv1f64( declare <vscale x 1 x double> @llvm.riscv.vfmsub.nxv1f64.nxv1f64(
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 1 x double>, <vscale x 1 x double>,
iXLen, iXLen, iXLen, iXLen);
iXLen);
define <vscale x 1 x double> @intrinsic_vfmsub_vv_nxv1f64_nxv1f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 1 x double> %1, <vscale x 1 x double> %2, iXLen %3) nounwind { define <vscale x 1 x double> @intrinsic_vfmsub_vv_nxv1f64_nxv1f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 1 x double> %1, <vscale x 1 x double> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfmsub_vv_nxv1f64_nxv1f64_nxv1f64: ; CHECK-LABEL: intrinsic_vfmsub_vv_nxv1f64_nxv1f64_nxv1f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, ma ; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, ma
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfmsub.vv v8, v9, v10 ; CHECK-NEXT: vfmsub.vv v8, v9, v10
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfmsub.nxv1f64.nxv1f64( %a = call <vscale x 1 x double> @llvm.riscv.vfmsub.nxv1f64.nxv1f64(
<vscale x 1 x double> %0, <vscale x 1 x double> %0,
<vscale x 1 x double> %1, <vscale x 1 x double> %1,
<vscale x 1 x double> %2, <vscale x 1 x double> %2,
iXLen %3, iXLen 0) iXLen 0, iXLen %3, iXLen 0)
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vfmsub.mask.nxv1f64.nxv1f64( declare <vscale x 1 x double> @llvm.riscv.vfmsub.mask.nxv1f64.nxv1f64(
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
iXLen, iXLen); iXLen, iXLen, iXLen);
define <vscale x 1 x double> @intrinsic_vfmsub_mask_vv_nxv1f64_nxv1f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 1 x double> %1, <vscale x 1 x double> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind { define <vscale x 1 x double> @intrinsic_vfmsub_mask_vv_nxv1f64_nxv1f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 1 x double> %1, <vscale x 1 x double> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfmsub_mask_vv_nxv1f64_nxv1f64_nxv1f64: ; CHECK-LABEL: intrinsic_vfmsub_mask_vv_nxv1f64_nxv1f64_nxv1f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, mu
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfmsub.vv v8, v9, v10, v0.t ; CHECK-NEXT: vfmsub.vv v8, v9, v10, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfmsub.mask.nxv1f64.nxv1f64( %a = call <vscale x 1 x double> @llvm.riscv.vfmsub.mask.nxv1f64.nxv1f64(
<vscale x 1 x double> %0, <vscale x 1 x double> %0,
<vscale x 1 x double> %1, <vscale x 1 x double> %1,
<vscale x 1 x double> %2, <vscale x 1 x double> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
iXLen %4, iXLen 0); iXLen 0, iXLen %4, iXLen 0);
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 2 x double> @llvm.riscv.vfmsub.nxv2f64.nxv2f64( declare <vscale x 2 x double> @llvm.riscv.vfmsub.nxv2f64.nxv2f64(
<vscale x 2 x double>, <vscale x 2 x double>,
<vscale x 2 x double>, <vscale x 2 x double>,
<vscale x 2 x double>, <vscale x 2 x double>,
iXLen, iXLen, iXLen, iXLen);
iXLen);
define <vscale x 2 x double> @intrinsic_vfmsub_vv_nxv2f64_nxv2f64_nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1, <vscale x 2 x double> %2, iXLen %3) nounwind { define <vscale x 2 x double> @intrinsic_vfmsub_vv_nxv2f64_nxv2f64_nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1, <vscale x 2 x double> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfmsub_vv_nxv2f64_nxv2f64_nxv2f64: ; CHECK-LABEL: intrinsic_vfmsub_vv_nxv2f64_nxv2f64_nxv2f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, ma ; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, ma
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfmsub.vv v8, v10, v12 ; CHECK-NEXT: vfmsub.vv v8, v10, v12
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x double> @llvm.riscv.vfmsub.nxv2f64.nxv2f64( %a = call <vscale x 2 x double> @llvm.riscv.vfmsub.nxv2f64.nxv2f64(
<vscale x 2 x double> %0, <vscale x 2 x double> %0,
<vscale x 2 x double> %1, <vscale x 2 x double> %1,
<vscale x 2 x double> %2, <vscale x 2 x double> %2,
iXLen %3, iXLen 0) iXLen 0, iXLen %3, iXLen 0)
ret <vscale x 2 x double> %a ret <vscale x 2 x double> %a
} }
declare <vscale x 2 x double> @llvm.riscv.vfmsub.mask.nxv2f64.nxv2f64( declare <vscale x 2 x double> @llvm.riscv.vfmsub.mask.nxv2f64.nxv2f64(
<vscale x 2 x double>, <vscale x 2 x double>,
<vscale x 2 x double>, <vscale x 2 x double>,
<vscale x 2 x double>, <vscale x 2 x double>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
iXLen, iXLen); iXLen, iXLen, iXLen);
define <vscale x 2 x double> @intrinsic_vfmsub_mask_vv_nxv2f64_nxv2f64_nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1, <vscale x 2 x double> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind { define <vscale x 2 x double> @intrinsic_vfmsub_mask_vv_nxv2f64_nxv2f64_nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1, <vscale x 2 x double> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfmsub_mask_vv_nxv2f64_nxv2f64_nxv2f64: ; CHECK-LABEL: intrinsic_vfmsub_mask_vv_nxv2f64_nxv2f64_nxv2f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, mu
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfmsub.vv v8, v10, v12, v0.t ; CHECK-NEXT: vfmsub.vv v8, v10, v12, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x double> @llvm.riscv.vfmsub.mask.nxv2f64.nxv2f64( %a = call <vscale x 2 x double> @llvm.riscv.vfmsub.mask.nxv2f64.nxv2f64(
<vscale x 2 x double> %0, <vscale x 2 x double> %0,
<vscale x 2 x double> %1, <vscale x 2 x double> %1,
<vscale x 2 x double> %2, <vscale x 2 x double> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
iXLen %4, iXLen 0); iXLen 0, iXLen %4, iXLen 0);
ret <vscale x 2 x double> %a ret <vscale x 2 x double> %a
} }
declare <vscale x 4 x double> @llvm.riscv.vfmsub.nxv4f64.nxv4f64( declare <vscale x 4 x double> @llvm.riscv.vfmsub.nxv4f64.nxv4f64(
<vscale x 4 x double>, <vscale x 4 x double>,
<vscale x 4 x double>, <vscale x 4 x double>,
<vscale x 4 x double>, <vscale x 4 x double>,
iXLen, iXLen, iXLen, iXLen);
iXLen);
define <vscale x 4 x double> @intrinsic_vfmsub_vv_nxv4f64_nxv4f64_nxv4f64(<vscale x 4 x double> %0, <vscale x 4 x double> %1, <vscale x 4 x double> %2, iXLen %3) nounwind { define <vscale x 4 x double> @intrinsic_vfmsub_vv_nxv4f64_nxv4f64_nxv4f64(<vscale x 4 x double> %0, <vscale x 4 x double> %1, <vscale x 4 x double> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfmsub_vv_nxv4f64_nxv4f64_nxv4f64: ; CHECK-LABEL: intrinsic_vfmsub_vv_nxv4f64_nxv4f64_nxv4f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, ma ; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, ma
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfmsub.vv v8, v12, v16 ; CHECK-NEXT: vfmsub.vv v8, v12, v16
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x double> @llvm.riscv.vfmsub.nxv4f64.nxv4f64( %a = call <vscale x 4 x double> @llvm.riscv.vfmsub.nxv4f64.nxv4f64(
<vscale x 4 x double> %0, <vscale x 4 x double> %0,
<vscale x 4 x double> %1, <vscale x 4 x double> %1,
<vscale x 4 x double> %2, <vscale x 4 x double> %2,
iXLen %3, iXLen 0) iXLen 0, iXLen %3, iXLen 0)
ret <vscale x 4 x double> %a ret <vscale x 4 x double> %a
} }
declare <vscale x 4 x double> @llvm.riscv.vfmsub.mask.nxv4f64.nxv4f64( declare <vscale x 4 x double> @llvm.riscv.vfmsub.mask.nxv4f64.nxv4f64(
<vscale x 4 x double>, <vscale x 4 x double>,
<vscale x 4 x double>, <vscale x 4 x double>,
<vscale x 4 x double>, <vscale x 4 x double>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
iXLen, iXLen); iXLen, iXLen, iXLen);
define <vscale x 4 x double> @intrinsic_vfmsub_mask_vv_nxv4f64_nxv4f64_nxv4f64(<vscale x 4 x double> %0, <vscale x 4 x double> %1, <vscale x 4 x double> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind { define <vscale x 4 x double> @intrinsic_vfmsub_mask_vv_nxv4f64_nxv4f64_nxv4f64(<vscale x 4 x double> %0, <vscale x 4 x double> %1, <vscale x 4 x double> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfmsub_mask_vv_nxv4f64_nxv4f64_nxv4f64: ; CHECK-LABEL: intrinsic_vfmsub_mask_vv_nxv4f64_nxv4f64_nxv4f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, mu
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfmsub.vv v8, v12, v16, v0.t ; CHECK-NEXT: vfmsub.vv v8, v12, v16, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x double> @llvm.riscv.vfmsub.mask.nxv4f64.nxv4f64( %a = call <vscale x 4 x double> @llvm.riscv.vfmsub.mask.nxv4f64.nxv4f64(
<vscale x 4 x double> %0, <vscale x 4 x double> %0,
<vscale x 4 x double> %1, <vscale x 4 x double> %1,
<vscale x 4 x double> %2, <vscale x 4 x double> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
iXLen %4, iXLen 0); iXLen 0, iXLen %4, iXLen 0);
ret <vscale x 4 x double> %a ret <vscale x 4 x double> %a
} }
declare <vscale x 1 x half> @llvm.riscv.vfmsub.nxv1f16.f16( declare <vscale x 1 x half> @llvm.riscv.vfmsub.nxv1f16.f16(
<vscale x 1 x half>, <vscale x 1 x half>,
half, half,
<vscale x 1 x half>, <vscale x 1 x half>,
iXLen, iXLen, iXLen, iXLen);
iXLen);
define <vscale x 1 x half> @intrinsic_vfmsub_vf_nxv1f16_f16_nxv1f16(<vscale x 1 x half> %0, half %1, <vscale x 1 x half> %2, iXLen %3) nounwind { define <vscale x 1 x half> @intrinsic_vfmsub_vf_nxv1f16_f16_nxv1f16(<vscale x 1 x half> %0, half %1, <vscale x 1 x half> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfmsub_vf_nxv1f16_f16_nxv1f16: ; CHECK-LABEL: intrinsic_vfmsub_vf_nxv1f16_f16_nxv1f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, ma ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, ma
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfmsub.vf v8, fa0, v9 ; CHECK-NEXT: vfmsub.vf v8, fa0, v9
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x half> @llvm.riscv.vfmsub.nxv1f16.f16( %a = call <vscale x 1 x half> @llvm.riscv.vfmsub.nxv1f16.f16(
<vscale x 1 x half> %0, <vscale x 1 x half> %0,
half %1, half %1,
<vscale x 1 x half> %2, <vscale x 1 x half> %2,
iXLen %3, iXLen 0) iXLen 0, iXLen %3, iXLen 0)
ret <vscale x 1 x half> %a ret <vscale x 1 x half> %a
} }
declare <vscale x 1 x half> @llvm.riscv.vfmsub.mask.nxv1f16.f16( declare <vscale x 1 x half> @llvm.riscv.vfmsub.mask.nxv1f16.f16(
<vscale x 1 x half>, <vscale x 1 x half>,
half, half,
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
iXLen, iXLen); iXLen, iXLen, iXLen);
define <vscale x 1 x half> @intrinsic_vfmsub_mask_vf_nxv1f16_f16_nxv1f16(<vscale x 1 x half> %0, half %1, <vscale x 1 x half> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind { define <vscale x 1 x half> @intrinsic_vfmsub_mask_vf_nxv1f16_f16_nxv1f16(<vscale x 1 x half> %0, half %1, <vscale x 1 x half> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfmsub_mask_vf_nxv1f16_f16_nxv1f16: ; CHECK-LABEL: intrinsic_vfmsub_mask_vf_nxv1f16_f16_nxv1f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfmsub.vf v8, fa0, v9, v0.t ; CHECK-NEXT: vfmsub.vf v8, fa0, v9, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x half> @llvm.riscv.vfmsub.mask.nxv1f16.f16( %a = call <vscale x 1 x half> @llvm.riscv.vfmsub.mask.nxv1f16.f16(
<vscale x 1 x half> %0, <vscale x 1 x half> %0,
half %1, half %1,
<vscale x 1 x half> %2, <vscale x 1 x half> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
iXLen %4, iXLen 0); iXLen 0, iXLen %4, iXLen 0);
ret <vscale x 1 x half> %a ret <vscale x 1 x half> %a
} }
declare <vscale x 2 x half> @llvm.riscv.vfmsub.nxv2f16.f16( declare <vscale x 2 x half> @llvm.riscv.vfmsub.nxv2f16.f16(
<vscale x 2 x half>, <vscale x 2 x half>,
half, half,
<vscale x 2 x half>, <vscale x 2 x half>,
iXLen, iXLen, iXLen, iXLen);
iXLen);
define <vscale x 2 x half> @intrinsic_vfmsub_vf_nxv2f16_f16_nxv2f16(<vscale x 2 x half> %0, half %1, <vscale x 2 x half> %2, iXLen %3) nounwind { define <vscale x 2 x half> @intrinsic_vfmsub_vf_nxv2f16_f16_nxv2f16(<vscale x 2 x half> %0, half %1, <vscale x 2 x half> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfmsub_vf_nxv2f16_f16_nxv2f16: ; CHECK-LABEL: intrinsic_vfmsub_vf_nxv2f16_f16_nxv2f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, ma ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, ma
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfmsub.vf v8, fa0, v9 ; CHECK-NEXT: vfmsub.vf v8, fa0, v9
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x half> @llvm.riscv.vfmsub.nxv2f16.f16( %a = call <vscale x 2 x half> @llvm.riscv.vfmsub.nxv2f16.f16(
<vscale x 2 x half> %0, <vscale x 2 x half> %0,
half %1, half %1,
<vscale x 2 x half> %2, <vscale x 2 x half> %2,
iXLen %3, iXLen 0) iXLen 0, iXLen %3, iXLen 0)
ret <vscale x 2 x half> %a ret <vscale x 2 x half> %a
} }
declare <vscale x 2 x half> @llvm.riscv.vfmsub.mask.nxv2f16.f16( declare <vscale x 2 x half> @llvm.riscv.vfmsub.mask.nxv2f16.f16(
<vscale x 2 x half>, <vscale x 2 x half>,
half, half,
<vscale x 2 x half>, <vscale x 2 x half>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
iXLen, iXLen); iXLen, iXLen, iXLen);
define <vscale x 2 x half> @intrinsic_vfmsub_mask_vf_nxv2f16_f16_nxv2f16(<vscale x 2 x half> %0, half %1, <vscale x 2 x half> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind { define <vscale x 2 x half> @intrinsic_vfmsub_mask_vf_nxv2f16_f16_nxv2f16(<vscale x 2 x half> %0, half %1, <vscale x 2 x half> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfmsub_mask_vf_nxv2f16_f16_nxv2f16: ; CHECK-LABEL: intrinsic_vfmsub_mask_vf_nxv2f16_f16_nxv2f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfmsub.vf v8, fa0, v9, v0.t ; CHECK-NEXT: vfmsub.vf v8, fa0, v9, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x half> @llvm.riscv.vfmsub.mask.nxv2f16.f16( %a = call <vscale x 2 x half> @llvm.riscv.vfmsub.mask.nxv2f16.f16(
<vscale x 2 x half> %0, <vscale x 2 x half> %0,
half %1, half %1,
<vscale x 2 x half> %2, <vscale x 2 x half> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
iXLen %4, iXLen 0); iXLen 0, iXLen %4, iXLen 0);
ret <vscale x 2 x half> %a ret <vscale x 2 x half> %a
} }
declare <vscale x 4 x half> @llvm.riscv.vfmsub.nxv4f16.f16( declare <vscale x 4 x half> @llvm.riscv.vfmsub.nxv4f16.f16(
<vscale x 4 x half>, <vscale x 4 x half>,
half, half,
<vscale x 4 x half>, <vscale x 4 x half>,
iXLen, iXLen, iXLen, iXLen);
iXLen);
define <vscale x 4 x half> @intrinsic_vfmsub_vf_nxv4f16_f16_nxv4f16(<vscale x 4 x half> %0, half %1, <vscale x 4 x half> %2, iXLen %3) nounwind { define <vscale x 4 x half> @intrinsic_vfmsub_vf_nxv4f16_f16_nxv4f16(<vscale x 4 x half> %0, half %1, <vscale x 4 x half> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfmsub_vf_nxv4f16_f16_nxv4f16: ; CHECK-LABEL: intrinsic_vfmsub_vf_nxv4f16_f16_nxv4f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, ma ; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, ma
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfmsub.vf v8, fa0, v9 ; CHECK-NEXT: vfmsub.vf v8, fa0, v9
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x half> @llvm.riscv.vfmsub.nxv4f16.f16( %a = call <vscale x 4 x half> @llvm.riscv.vfmsub.nxv4f16.f16(
<vscale x 4 x half> %0, <vscale x 4 x half> %0,
half %1, half %1,
<vscale x 4 x half> %2, <vscale x 4 x half> %2,
iXLen %3, iXLen 0) iXLen 0, iXLen %3, iXLen 0)
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 4 x half> @llvm.riscv.vfmsub.mask.nxv4f16.f16( declare <vscale x 4 x half> @llvm.riscv.vfmsub.mask.nxv4f16.f16(
<vscale x 4 x half>, <vscale x 4 x half>,
half, half,
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
iXLen, iXLen); iXLen, iXLen, iXLen);
define <vscale x 4 x half> @intrinsic_vfmsub_mask_vf_nxv4f16_f16_nxv4f16(<vscale x 4 x half> %0, half %1, <vscale x 4 x half> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind { define <vscale x 4 x half> @intrinsic_vfmsub_mask_vf_nxv4f16_f16_nxv4f16(<vscale x 4 x half> %0, half %1, <vscale x 4 x half> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfmsub_mask_vf_nxv4f16_f16_nxv4f16: ; CHECK-LABEL: intrinsic_vfmsub_mask_vf_nxv4f16_f16_nxv4f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfmsub.vf v8, fa0, v9, v0.t ; CHECK-NEXT: vfmsub.vf v8, fa0, v9, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x half> @llvm.riscv.vfmsub.mask.nxv4f16.f16( %a = call <vscale x 4 x half> @llvm.riscv.vfmsub.mask.nxv4f16.f16(
<vscale x 4 x half> %0, <vscale x 4 x half> %0,
half %1, half %1,
<vscale x 4 x half> %2, <vscale x 4 x half> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
iXLen %4, iXLen 0); iXLen 0, iXLen %4, iXLen 0);
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 8 x half> @llvm.riscv.vfmsub.nxv8f16.f16( declare <vscale x 8 x half> @llvm.riscv.vfmsub.nxv8f16.f16(
<vscale x 8 x half>, <vscale x 8 x half>,
half, half,
<vscale x 8 x half>, <vscale x 8 x half>,
iXLen, iXLen, iXLen, iXLen);
iXLen);
define <vscale x 8 x half> @intrinsic_vfmsub_vf_nxv8f16_f16_nxv8f16(<vscale x 8 x half> %0, half %1, <vscale x 8 x half> %2, iXLen %3) nounwind { define <vscale x 8 x half> @intrinsic_vfmsub_vf_nxv8f16_f16_nxv8f16(<vscale x 8 x half> %0, half %1, <vscale x 8 x half> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfmsub_vf_nxv8f16_f16_nxv8f16: ; CHECK-LABEL: intrinsic_vfmsub_vf_nxv8f16_f16_nxv8f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, ma ; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, ma
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfmsub.vf v8, fa0, v10 ; CHECK-NEXT: vfmsub.vf v8, fa0, v10
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x half> @llvm.riscv.vfmsub.nxv8f16.f16( %a = call <vscale x 8 x half> @llvm.riscv.vfmsub.nxv8f16.f16(
<vscale x 8 x half> %0, <vscale x 8 x half> %0,
half %1, half %1,
<vscale x 8 x half> %2, <vscale x 8 x half> %2,
iXLen %3, iXLen 0) iXLen 0, iXLen %3, iXLen 0)
ret <vscale x 8 x half> %a ret <vscale x 8 x half> %a
} }
declare <vscale x 8 x half> @llvm.riscv.vfmsub.mask.nxv8f16.f16( declare <vscale x 8 x half> @llvm.riscv.vfmsub.mask.nxv8f16.f16(
<vscale x 8 x half>, <vscale x 8 x half>,
half, half,
<vscale x 8 x half>, <vscale x 8 x half>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
iXLen, iXLen); iXLen, iXLen, iXLen);
define <vscale x 8 x half> @intrinsic_vfmsub_mask_vf_nxv8f16_f16_nxv8f16(<vscale x 8 x half> %0, half %1, <vscale x 8 x half> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind { define <vscale x 8 x half> @intrinsic_vfmsub_mask_vf_nxv8f16_f16_nxv8f16(<vscale x 8 x half> %0, half %1, <vscale x 8 x half> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfmsub_mask_vf_nxv8f16_f16_nxv8f16: ; CHECK-LABEL: intrinsic_vfmsub_mask_vf_nxv8f16_f16_nxv8f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, mu
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfmsub.vf v8, fa0, v10, v0.t ; CHECK-NEXT: vfmsub.vf v8, fa0, v10, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x half> @llvm.riscv.vfmsub.mask.nxv8f16.f16( %a = call <vscale x 8 x half> @llvm.riscv.vfmsub.mask.nxv8f16.f16(
<vscale x 8 x half> %0, <vscale x 8 x half> %0,
half %1, half %1,
<vscale x 8 x half> %2, <vscale x 8 x half> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
iXLen %4, iXLen 0); iXLen 0, iXLen %4, iXLen 0);
ret <vscale x 8 x half> %a ret <vscale x 8 x half> %a
} }
declare <vscale x 16 x half> @llvm.riscv.vfmsub.nxv16f16.f16( declare <vscale x 16 x half> @llvm.riscv.vfmsub.nxv16f16.f16(
<vscale x 16 x half>, <vscale x 16 x half>,
half, half,
<vscale x 16 x half>, <vscale x 16 x half>,
iXLen, iXLen, iXLen, iXLen);
iXLen);
define <vscale x 16 x half> @intrinsic_vfmsub_vf_nxv16f16_f16_nxv16f16(<vscale x 16 x half> %0, half %1, <vscale x 16 x half> %2, iXLen %3) nounwind { define <vscale x 16 x half> @intrinsic_vfmsub_vf_nxv16f16_f16_nxv16f16(<vscale x 16 x half> %0, half %1, <vscale x 16 x half> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfmsub_vf_nxv16f16_f16_nxv16f16: ; CHECK-LABEL: intrinsic_vfmsub_vf_nxv16f16_f16_nxv16f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, ma ; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, ma
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfmsub.vf v8, fa0, v12 ; CHECK-NEXT: vfmsub.vf v8, fa0, v12
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x half> @llvm.riscv.vfmsub.nxv16f16.f16( %a = call <vscale x 16 x half> @llvm.riscv.vfmsub.nxv16f16.f16(
<vscale x 16 x half> %0, <vscale x 16 x half> %0,
half %1, half %1,
<vscale x 16 x half> %2, <vscale x 16 x half> %2,
iXLen %3, iXLen 0) iXLen 0, iXLen %3, iXLen 0)
ret <vscale x 16 x half> %a ret <vscale x 16 x half> %a
} }
declare <vscale x 16 x half> @llvm.riscv.vfmsub.mask.nxv16f16.f16( declare <vscale x 16 x half> @llvm.riscv.vfmsub.mask.nxv16f16.f16(
<vscale x 16 x half>, <vscale x 16 x half>,
half, half,
<vscale x 16 x half>, <vscale x 16 x half>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
iXLen, iXLen); iXLen, iXLen, iXLen);
define <vscale x 16 x half> @intrinsic_vfmsub_mask_vf_nxv16f16_f16_nxv16f16(<vscale x 16 x half> %0, half %1, <vscale x 16 x half> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind { define <vscale x 16 x half> @intrinsic_vfmsub_mask_vf_nxv16f16_f16_nxv16f16(<vscale x 16 x half> %0, half %1, <vscale x 16 x half> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfmsub_mask_vf_nxv16f16_f16_nxv16f16: ; CHECK-LABEL: intrinsic_vfmsub_mask_vf_nxv16f16_f16_nxv16f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfmsub.vf v8, fa0, v12, v0.t ; CHECK-NEXT: vfmsub.vf v8, fa0, v12, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x half> @llvm.riscv.vfmsub.mask.nxv16f16.f16( %a = call <vscale x 16 x half> @llvm.riscv.vfmsub.mask.nxv16f16.f16(
<vscale x 16 x half> %0, <vscale x 16 x half> %0,
half %1, half %1,
<vscale x 16 x half> %2, <vscale x 16 x half> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
iXLen %4, iXLen 0); iXLen 0, iXLen %4, iXLen 0);
ret <vscale x 16 x half> %a ret <vscale x 16 x half> %a
} }
declare <vscale x 1 x float> @llvm.riscv.vfmsub.nxv1f32.f32( declare <vscale x 1 x float> @llvm.riscv.vfmsub.nxv1f32.f32(
<vscale x 1 x float>, <vscale x 1 x float>,
float, float,
<vscale x 1 x float>, <vscale x 1 x float>,
iXLen, iXLen, iXLen, iXLen);
iXLen);
define <vscale x 1 x float> @intrinsic_vfmsub_vf_nxv1f32_f32_nxv1f32(<vscale x 1 x float> %0, float %1, <vscale x 1 x float> %2, iXLen %3) nounwind { define <vscale x 1 x float> @intrinsic_vfmsub_vf_nxv1f32_f32_nxv1f32(<vscale x 1 x float> %0, float %1, <vscale x 1 x float> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfmsub_vf_nxv1f32_f32_nxv1f32: ; CHECK-LABEL: intrinsic_vfmsub_vf_nxv1f32_f32_nxv1f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, ma ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, ma
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfmsub.vf v8, fa0, v9 ; CHECK-NEXT: vfmsub.vf v8, fa0, v9
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x float> @llvm.riscv.vfmsub.nxv1f32.f32( %a = call <vscale x 1 x float> @llvm.riscv.vfmsub.nxv1f32.f32(
<vscale x 1 x float> %0, <vscale x 1 x float> %0,
float %1, float %1,
<vscale x 1 x float> %2, <vscale x 1 x float> %2,
iXLen %3, iXLen 0) iXLen 0, iXLen %3, iXLen 0)
ret <vscale x 1 x float> %a ret <vscale x 1 x float> %a
} }
declare <vscale x 1 x float> @llvm.riscv.vfmsub.mask.nxv1f32.f32( declare <vscale x 1 x float> @llvm.riscv.vfmsub.mask.nxv1f32.f32(
<vscale x 1 x float>, <vscale x 1 x float>,
float, float,
<vscale x 1 x float>, <vscale x 1 x float>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
iXLen, iXLen); iXLen, iXLen, iXLen);
define <vscale x 1 x float> @intrinsic_vfmsub_mask_vf_nxv1f32_f32_nxv1f32(<vscale x 1 x float> %0, float %1, <vscale x 1 x float> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind { define <vscale x 1 x float> @intrinsic_vfmsub_mask_vf_nxv1f32_f32_nxv1f32(<vscale x 1 x float> %0, float %1, <vscale x 1 x float> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfmsub_mask_vf_nxv1f32_f32_nxv1f32: ; CHECK-LABEL: intrinsic_vfmsub_mask_vf_nxv1f32_f32_nxv1f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfmsub.vf v8, fa0, v9, v0.t ; CHECK-NEXT: vfmsub.vf v8, fa0, v9, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x float> @llvm.riscv.vfmsub.mask.nxv1f32.f32( %a = call <vscale x 1 x float> @llvm.riscv.vfmsub.mask.nxv1f32.f32(
<vscale x 1 x float> %0, <vscale x 1 x float> %0,
float %1, float %1,
<vscale x 1 x float> %2, <vscale x 1 x float> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
iXLen %4, iXLen 0); iXLen 0, iXLen %4, iXLen 0);
ret <vscale x 1 x float> %a ret <vscale x 1 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vfmsub.nxv2f32.f32( declare <vscale x 2 x float> @llvm.riscv.vfmsub.nxv2f32.f32(
<vscale x 2 x float>, <vscale x 2 x float>,
float, float,
<vscale x 2 x float>, <vscale x 2 x float>,
iXLen, iXLen, iXLen, iXLen);
iXLen);
define <vscale x 2 x float> @intrinsic_vfmsub_vf_nxv2f32_f32_nxv2f32(<vscale x 2 x float> %0, float %1, <vscale x 2 x float> %2, iXLen %3) nounwind { define <vscale x 2 x float> @intrinsic_vfmsub_vf_nxv2f32_f32_nxv2f32(<vscale x 2 x float> %0, float %1, <vscale x 2 x float> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfmsub_vf_nxv2f32_f32_nxv2f32: ; CHECK-LABEL: intrinsic_vfmsub_vf_nxv2f32_f32_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, ma ; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, ma
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfmsub.vf v8, fa0, v9 ; CHECK-NEXT: vfmsub.vf v8, fa0, v9
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfmsub.nxv2f32.f32( %a = call <vscale x 2 x float> @llvm.riscv.vfmsub.nxv2f32.f32(
<vscale x 2 x float> %0, <vscale x 2 x float> %0,
float %1, float %1,
<vscale x 2 x float> %2, <vscale x 2 x float> %2,
iXLen %3, iXLen 0) iXLen 0, iXLen %3, iXLen 0)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vfmsub.mask.nxv2f32.f32( declare <vscale x 2 x float> @llvm.riscv.vfmsub.mask.nxv2f32.f32(
<vscale x 2 x float>, <vscale x 2 x float>,
float, float,
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
iXLen, iXLen); iXLen, iXLen, iXLen);
define <vscale x 2 x float> @intrinsic_vfmsub_mask_vf_nxv2f32_f32_nxv2f32(<vscale x 2 x float> %0, float %1, <vscale x 2 x float> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind { define <vscale x 2 x float> @intrinsic_vfmsub_mask_vf_nxv2f32_f32_nxv2f32(<vscale x 2 x float> %0, float %1, <vscale x 2 x float> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfmsub_mask_vf_nxv2f32_f32_nxv2f32: ; CHECK-LABEL: intrinsic_vfmsub_mask_vf_nxv2f32_f32_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfmsub.vf v8, fa0, v9, v0.t ; CHECK-NEXT: vfmsub.vf v8, fa0, v9, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfmsub.mask.nxv2f32.f32( %a = call <vscale x 2 x float> @llvm.riscv.vfmsub.mask.nxv2f32.f32(
<vscale x 2 x float> %0, <vscale x 2 x float> %0,
float %1, float %1,
<vscale x 2 x float> %2, <vscale x 2 x float> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
iXLen %4, iXLen 0); iXLen 0, iXLen %4, iXLen 0);
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 4 x float> @llvm.riscv.vfmsub.nxv4f32.f32( declare <vscale x 4 x float> @llvm.riscv.vfmsub.nxv4f32.f32(
<vscale x 4 x float>, <vscale x 4 x float>,
float, float,
<vscale x 4 x float>, <vscale x 4 x float>,
iXLen, iXLen, iXLen, iXLen);
iXLen);
define <vscale x 4 x float> @intrinsic_vfmsub_vf_nxv4f32_f32_nxv4f32(<vscale x 4 x float> %0, float %1, <vscale x 4 x float> %2, iXLen %3) nounwind { define <vscale x 4 x float> @intrinsic_vfmsub_vf_nxv4f32_f32_nxv4f32(<vscale x 4 x float> %0, float %1, <vscale x 4 x float> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfmsub_vf_nxv4f32_f32_nxv4f32: ; CHECK-LABEL: intrinsic_vfmsub_vf_nxv4f32_f32_nxv4f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, ma ; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, ma
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfmsub.vf v8, fa0, v10 ; CHECK-NEXT: vfmsub.vf v8, fa0, v10
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x float> @llvm.riscv.vfmsub.nxv4f32.f32( %a = call <vscale x 4 x float> @llvm.riscv.vfmsub.nxv4f32.f32(
<vscale x 4 x float> %0, <vscale x 4 x float> %0,
float %1, float %1,
<vscale x 4 x float> %2, <vscale x 4 x float> %2,
iXLen %3, iXLen 0) iXLen 0, iXLen %3, iXLen 0)
ret <vscale x 4 x float> %a ret <vscale x 4 x float> %a
} }
declare <vscale x 4 x float> @llvm.riscv.vfmsub.mask.nxv4f32.f32( declare <vscale x 4 x float> @llvm.riscv.vfmsub.mask.nxv4f32.f32(
<vscale x 4 x float>, <vscale x 4 x float>,
float, float,
<vscale x 4 x float>, <vscale x 4 x float>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
iXLen, iXLen); iXLen, iXLen, iXLen);
define <vscale x 4 x float> @intrinsic_vfmsub_mask_vf_nxv4f32_f32_nxv4f32(<vscale x 4 x float> %0, float %1, <vscale x 4 x float> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind { define <vscale x 4 x float> @intrinsic_vfmsub_mask_vf_nxv4f32_f32_nxv4f32(<vscale x 4 x float> %0, float %1, <vscale x 4 x float> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfmsub_mask_vf_nxv4f32_f32_nxv4f32: ; CHECK-LABEL: intrinsic_vfmsub_mask_vf_nxv4f32_f32_nxv4f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfmsub.vf v8, fa0, v10, v0.t ; CHECK-NEXT: vfmsub.vf v8, fa0, v10, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x float> @llvm.riscv.vfmsub.mask.nxv4f32.f32( %a = call <vscale x 4 x float> @llvm.riscv.vfmsub.mask.nxv4f32.f32(
<vscale x 4 x float> %0, <vscale x 4 x float> %0,
float %1, float %1,
<vscale x 4 x float> %2, <vscale x 4 x float> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
iXLen %4, iXLen 0); iXLen 0, iXLen %4, iXLen 0);
ret <vscale x 4 x float> %a ret <vscale x 4 x float> %a
} }
declare <vscale x 8 x float> @llvm.riscv.vfmsub.nxv8f32.f32( declare <vscale x 8 x float> @llvm.riscv.vfmsub.nxv8f32.f32(
<vscale x 8 x float>, <vscale x 8 x float>,
float, float,
<vscale x 8 x float>, <vscale x 8 x float>,
iXLen, iXLen, iXLen, iXLen);
iXLen);
define <vscale x 8 x float> @intrinsic_vfmsub_vf_nxv8f32_f32_nxv8f32(<vscale x 8 x float> %0, float %1, <vscale x 8 x float> %2, iXLen %3) nounwind { define <vscale x 8 x float> @intrinsic_vfmsub_vf_nxv8f32_f32_nxv8f32(<vscale x 8 x float> %0, float %1, <vscale x 8 x float> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfmsub_vf_nxv8f32_f32_nxv8f32: ; CHECK-LABEL: intrinsic_vfmsub_vf_nxv8f32_f32_nxv8f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, ma ; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, ma
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfmsub.vf v8, fa0, v12 ; CHECK-NEXT: vfmsub.vf v8, fa0, v12
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x float> @llvm.riscv.vfmsub.nxv8f32.f32( %a = call <vscale x 8 x float> @llvm.riscv.vfmsub.nxv8f32.f32(
<vscale x 8 x float> %0, <vscale x 8 x float> %0,
float %1, float %1,
<vscale x 8 x float> %2, <vscale x 8 x float> %2,
iXLen %3, iXLen 0) iXLen 0, iXLen %3, iXLen 0)
ret <vscale x 8 x float> %a ret <vscale x 8 x float> %a
} }
declare <vscale x 8 x float> @llvm.riscv.vfmsub.mask.nxv8f32.f32( declare <vscale x 8 x float> @llvm.riscv.vfmsub.mask.nxv8f32.f32(
<vscale x 8 x float>, <vscale x 8 x float>,
float, float,
<vscale x 8 x float>, <vscale x 8 x float>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
iXLen, iXLen); iXLen, iXLen, iXLen);
define <vscale x 8 x float> @intrinsic_vfmsub_mask_vf_nxv8f32_f32_nxv8f32(<vscale x 8 x float> %0, float %1, <vscale x 8 x float> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind { define <vscale x 8 x float> @intrinsic_vfmsub_mask_vf_nxv8f32_f32_nxv8f32(<vscale x 8 x float> %0, float %1, <vscale x 8 x float> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfmsub_mask_vf_nxv8f32_f32_nxv8f32: ; CHECK-LABEL: intrinsic_vfmsub_mask_vf_nxv8f32_f32_nxv8f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfmsub.vf v8, fa0, v12, v0.t ; CHECK-NEXT: vfmsub.vf v8, fa0, v12, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x float> @llvm.riscv.vfmsub.mask.nxv8f32.f32( %a = call <vscale x 8 x float> @llvm.riscv.vfmsub.mask.nxv8f32.f32(
<vscale x 8 x float> %0, <vscale x 8 x float> %0,
float %1, float %1,
<vscale x 8 x float> %2, <vscale x 8 x float> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
iXLen %4, iXLen 0); iXLen 0, iXLen %4, iXLen 0);
ret <vscale x 8 x float> %a ret <vscale x 8 x float> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vfmsub.nxv1f64.f64( declare <vscale x 1 x double> @llvm.riscv.vfmsub.nxv1f64.f64(
<vscale x 1 x double>, <vscale x 1 x double>,
double, double,
<vscale x 1 x double>, <vscale x 1 x double>,
iXLen, iXLen, iXLen, iXLen);
iXLen);
define <vscale x 1 x double> @intrinsic_vfmsub_vf_nxv1f64_f64_nxv1f64(<vscale x 1 x double> %0, double %1, <vscale x 1 x double> %2, iXLen %3) nounwind { define <vscale x 1 x double> @intrinsic_vfmsub_vf_nxv1f64_f64_nxv1f64(<vscale x 1 x double> %0, double %1, <vscale x 1 x double> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfmsub_vf_nxv1f64_f64_nxv1f64: ; CHECK-LABEL: intrinsic_vfmsub_vf_nxv1f64_f64_nxv1f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, ma ; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, ma
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfmsub.vf v8, fa0, v9 ; CHECK-NEXT: vfmsub.vf v8, fa0, v9
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfmsub.nxv1f64.f64( %a = call <vscale x 1 x double> @llvm.riscv.vfmsub.nxv1f64.f64(
<vscale x 1 x double> %0, <vscale x 1 x double> %0,
double %1, double %1,
<vscale x 1 x double> %2, <vscale x 1 x double> %2,
iXLen %3, iXLen 0) iXLen 0, iXLen %3, iXLen 0)
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vfmsub.mask.nxv1f64.f64( declare <vscale x 1 x double> @llvm.riscv.vfmsub.mask.nxv1f64.f64(
<vscale x 1 x double>, <vscale x 1 x double>,
double, double,
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
iXLen, iXLen); iXLen, iXLen, iXLen);
define <vscale x 1 x double> @intrinsic_vfmsub_mask_vf_nxv1f64_f64_nxv1f64(<vscale x 1 x double> %0, double %1, <vscale x 1 x double> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind { define <vscale x 1 x double> @intrinsic_vfmsub_mask_vf_nxv1f64_f64_nxv1f64(<vscale x 1 x double> %0, double %1, <vscale x 1 x double> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfmsub_mask_vf_nxv1f64_f64_nxv1f64: ; CHECK-LABEL: intrinsic_vfmsub_mask_vf_nxv1f64_f64_nxv1f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, mu
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfmsub.vf v8, fa0, v9, v0.t ; CHECK-NEXT: vfmsub.vf v8, fa0, v9, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfmsub.mask.nxv1f64.f64( %a = call <vscale x 1 x double> @llvm.riscv.vfmsub.mask.nxv1f64.f64(
<vscale x 1 x double> %0, <vscale x 1 x double> %0,
double %1, double %1,
<vscale x 1 x double> %2, <vscale x 1 x double> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
iXLen %4, iXLen 0); iXLen 0, iXLen %4, iXLen 0);
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 2 x double> @llvm.riscv.vfmsub.nxv2f64.f64( declare <vscale x 2 x double> @llvm.riscv.vfmsub.nxv2f64.f64(
<vscale x 2 x double>, <vscale x 2 x double>,
double, double,
<vscale x 2 x double>, <vscale x 2 x double>,
iXLen, iXLen, iXLen, iXLen);
iXLen);
define <vscale x 2 x double> @intrinsic_vfmsub_vf_nxv2f64_f64_nxv2f64(<vscale x 2 x double> %0, double %1, <vscale x 2 x double> %2, iXLen %3) nounwind { define <vscale x 2 x double> @intrinsic_vfmsub_vf_nxv2f64_f64_nxv2f64(<vscale x 2 x double> %0, double %1, <vscale x 2 x double> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfmsub_vf_nxv2f64_f64_nxv2f64: ; CHECK-LABEL: intrinsic_vfmsub_vf_nxv2f64_f64_nxv2f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, ma ; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, ma
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfmsub.vf v8, fa0, v10 ; CHECK-NEXT: vfmsub.vf v8, fa0, v10
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x double> @llvm.riscv.vfmsub.nxv2f64.f64( %a = call <vscale x 2 x double> @llvm.riscv.vfmsub.nxv2f64.f64(
<vscale x 2 x double> %0, <vscale x 2 x double> %0,
double %1, double %1,
<vscale x 2 x double> %2, <vscale x 2 x double> %2,
iXLen %3, iXLen 0) iXLen 0, iXLen %3, iXLen 0)
ret <vscale x 2 x double> %a ret <vscale x 2 x double> %a
} }
declare <vscale x 2 x double> @llvm.riscv.vfmsub.mask.nxv2f64.f64( declare <vscale x 2 x double> @llvm.riscv.vfmsub.mask.nxv2f64.f64(
<vscale x 2 x double>, <vscale x 2 x double>,
double, double,
<vscale x 2 x double>, <vscale x 2 x double>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
iXLen, iXLen); iXLen, iXLen, iXLen);
define <vscale x 2 x double> @intrinsic_vfmsub_mask_vf_nxv2f64_f64_nxv2f64(<vscale x 2 x double> %0, double %1, <vscale x 2 x double> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind { define <vscale x 2 x double> @intrinsic_vfmsub_mask_vf_nxv2f64_f64_nxv2f64(<vscale x 2 x double> %0, double %1, <vscale x 2 x double> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfmsub_mask_vf_nxv2f64_f64_nxv2f64: ; CHECK-LABEL: intrinsic_vfmsub_mask_vf_nxv2f64_f64_nxv2f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, mu
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfmsub.vf v8, fa0, v10, v0.t ; CHECK-NEXT: vfmsub.vf v8, fa0, v10, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x double> @llvm.riscv.vfmsub.mask.nxv2f64.f64( %a = call <vscale x 2 x double> @llvm.riscv.vfmsub.mask.nxv2f64.f64(
<vscale x 2 x double> %0, <vscale x 2 x double> %0,
double %1, double %1,
<vscale x 2 x double> %2, <vscale x 2 x double> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
iXLen %4, iXLen 0); iXLen 0, iXLen %4, iXLen 0);
ret <vscale x 2 x double> %a ret <vscale x 2 x double> %a
} }
declare <vscale x 4 x double> @llvm.riscv.vfmsub.nxv4f64.f64( declare <vscale x 4 x double> @llvm.riscv.vfmsub.nxv4f64.f64(
<vscale x 4 x double>, <vscale x 4 x double>,
double, double,
<vscale x 4 x double>, <vscale x 4 x double>,
iXLen, iXLen, iXLen, iXLen);
iXLen);
define <vscale x 4 x double> @intrinsic_vfmsub_vf_nxv4f64_f64_nxv4f64(<vscale x 4 x double> %0, double %1, <vscale x 4 x double> %2, iXLen %3) nounwind { define <vscale x 4 x double> @intrinsic_vfmsub_vf_nxv4f64_f64_nxv4f64(<vscale x 4 x double> %0, double %1, <vscale x 4 x double> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfmsub_vf_nxv4f64_f64_nxv4f64: ; CHECK-LABEL: intrinsic_vfmsub_vf_nxv4f64_f64_nxv4f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, ma ; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, ma
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfmsub.vf v8, fa0, v12 ; CHECK-NEXT: vfmsub.vf v8, fa0, v12
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x double> @llvm.riscv.vfmsub.nxv4f64.f64( %a = call <vscale x 4 x double> @llvm.riscv.vfmsub.nxv4f64.f64(
<vscale x 4 x double> %0, <vscale x 4 x double> %0,
double %1, double %1,
<vscale x 4 x double> %2, <vscale x 4 x double> %2,
iXLen %3, iXLen 0) iXLen 0, iXLen %3, iXLen 0)
ret <vscale x 4 x double> %a ret <vscale x 4 x double> %a
} }
declare <vscale x 4 x double> @llvm.riscv.vfmsub.mask.nxv4f64.f64( declare <vscale x 4 x double> @llvm.riscv.vfmsub.mask.nxv4f64.f64(
<vscale x 4 x double>, <vscale x 4 x double>,
double, double,
<vscale x 4 x double>, <vscale x 4 x double>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
iXLen, iXLen); iXLen, iXLen, iXLen);
define <vscale x 4 x double> @intrinsic_vfmsub_mask_vf_nxv4f64_f64_nxv4f64(<vscale x 4 x double> %0, double %1, <vscale x 4 x double> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind { define <vscale x 4 x double> @intrinsic_vfmsub_mask_vf_nxv4f64_f64_nxv4f64(<vscale x 4 x double> %0, double %1, <vscale x 4 x double> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfmsub_mask_vf_nxv4f64_f64_nxv4f64: ; CHECK-LABEL: intrinsic_vfmsub_mask_vf_nxv4f64_f64_nxv4f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, mu
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfmsub.vf v8, fa0, v12, v0.t ; CHECK-NEXT: vfmsub.vf v8, fa0, v12, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x double> @llvm.riscv.vfmsub.mask.nxv4f64.f64( %a = call <vscale x 4 x double> @llvm.riscv.vfmsub.mask.nxv4f64.f64(
<vscale x 4 x double> %0, <vscale x 4 x double> %0,
double %1, double %1,
<vscale x 4 x double> %2, <vscale x 4 x double> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
iXLen %4, iXLen 0); iXLen 0, iXLen %4, iXLen 0);
ret <vscale x 4 x double> %a ret <vscale x 4 x double> %a
} }

llvm/test/CodeGen/RISCV/rvv/vfnmacc.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zfh,+experimental-zvfh \ ; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zfh,+experimental-zvfh \
; RUN: -verify-machineinstrs -target-abi=ilp32d | FileCheck %s ; RUN: -verify-machineinstrs -target-abi=ilp32d | FileCheck %s
; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zfh,+experimental-zvfh \ ; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zfh,+experimental-zvfh \
; RUN: -verify-machineinstrs -target-abi=lp64d | FileCheck %s ; RUN: -verify-machineinstrs -target-abi=lp64d | FileCheck %s
declare <vscale x 1 x half> @llvm.riscv.vfnmacc.nxv1f16.nxv1f16( declare <vscale x 1 x half> @llvm.riscv.vfnmacc.nxv1f16.nxv1f16(
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x half>, <vscale x 1 x half>,
iXLen, iXLen, iXLen, iXLen);
iXLen);
define <vscale x 1 x half> @intrinsic_vfnmacc_vv_nxv1f16_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, iXLen %3) nounwind { define <vscale x 1 x half> @intrinsic_vfnmacc_vv_nxv1f16_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfnmacc_vv_nxv1f16_nxv1f16_nxv1f16: ; CHECK-LABEL: intrinsic_vfnmacc_vv_nxv1f16_nxv1f16_nxv1f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, ma ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, ma
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfnmacc.vv v8, v9, v10 ; CHECK-NEXT: vfnmacc.vv v8, v9, v10
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x half> @llvm.riscv.vfnmacc.nxv1f16.nxv1f16( %a = call <vscale x 1 x half> @llvm.riscv.vfnmacc.nxv1f16.nxv1f16(
<vscale x 1 x half> %0, <vscale x 1 x half> %0,
<vscale x 1 x half> %1, <vscale x 1 x half> %1,
<vscale x 1 x half> %2, <vscale x 1 x half> %2,
iXLen %3, iXLen 0) iXLen 0, iXLen %3, iXLen 0)
ret <vscale x 1 x half> %a ret <vscale x 1 x half> %a
} }
declare <vscale x 1 x half> @llvm.riscv.vfnmacc.mask.nxv1f16.nxv1f16( declare <vscale x 1 x half> @llvm.riscv.vfnmacc.mask.nxv1f16.nxv1f16(
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
iXLen, iXLen); iXLen, iXLen, iXLen);
define <vscale x 1 x half> @intrinsic_vfnmacc_mask_vv_nxv1f16_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind { define <vscale x 1 x half> @intrinsic_vfnmacc_mask_vv_nxv1f16_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfnmacc_mask_vv_nxv1f16_nxv1f16_nxv1f16: ; CHECK-LABEL: intrinsic_vfnmacc_mask_vv_nxv1f16_nxv1f16_nxv1f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfnmacc.vv v8, v9, v10, v0.t ; CHECK-NEXT: vfnmacc.vv v8, v9, v10, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x half> @llvm.riscv.vfnmacc.mask.nxv1f16.nxv1f16( %a = call <vscale x 1 x half> @llvm.riscv.vfnmacc.mask.nxv1f16.nxv1f16(
<vscale x 1 x half> %0, <vscale x 1 x half> %0,
<vscale x 1 x half> %1, <vscale x 1 x half> %1,
<vscale x 1 x half> %2, <vscale x 1 x half> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
iXLen %4, iXLen 0); iXLen 0, iXLen %4, iXLen 0);
ret <vscale x 1 x half> %a ret <vscale x 1 x half> %a
} }
declare <vscale x 2 x half> @llvm.riscv.vfnmacc.nxv2f16.nxv2f16( declare <vscale x 2 x half> @llvm.riscv.vfnmacc.nxv2f16.nxv2f16(
<vscale x 2 x half>, <vscale x 2 x half>,
<vscale x 2 x half>, <vscale x 2 x half>,
<vscale x 2 x half>, <vscale x 2 x half>,
iXLen, iXLen, iXLen, iXLen);
iXLen);
define <vscale x 2 x half> @intrinsic_vfnmacc_vv_nxv2f16_nxv2f16_nxv2f16(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, iXLen %3) nounwind { define <vscale x 2 x half> @intrinsic_vfnmacc_vv_nxv2f16_nxv2f16_nxv2f16(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfnmacc_vv_nxv2f16_nxv2f16_nxv2f16: ; CHECK-LABEL: intrinsic_vfnmacc_vv_nxv2f16_nxv2f16_nxv2f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, ma ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, ma
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfnmacc.vv v8, v9, v10 ; CHECK-NEXT: vfnmacc.vv v8, v9, v10
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x half> @llvm.riscv.vfnmacc.nxv2f16.nxv2f16( %a = call <vscale x 2 x half> @llvm.riscv.vfnmacc.nxv2f16.nxv2f16(
<vscale x 2 x half> %0, <vscale x 2 x half> %0,
<vscale x 2 x half> %1, <vscale x 2 x half> %1,
<vscale x 2 x half> %2, <vscale x 2 x half> %2,
iXLen %3, iXLen 0) iXLen 0, iXLen %3, iXLen 0)
ret <vscale x 2 x half> %a ret <vscale x 2 x half> %a
} }
declare <vscale x 2 x half> @llvm.riscv.vfnmacc.mask.nxv2f16.nxv2f16( declare <vscale x 2 x half> @llvm.riscv.vfnmacc.mask.nxv2f16.nxv2f16(
<vscale x 2 x half>, <vscale x 2 x half>,
<vscale x 2 x half>, <vscale x 2 x half>,
<vscale x 2 x half>, <vscale x 2 x half>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
iXLen, iXLen); iXLen, iXLen, iXLen);
define <vscale x 2 x half> @intrinsic_vfnmacc_mask_vv_nxv2f16_nxv2f16_nxv2f16(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind { define <vscale x 2 x half> @intrinsic_vfnmacc_mask_vv_nxv2f16_nxv2f16_nxv2f16(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfnmacc_mask_vv_nxv2f16_nxv2f16_nxv2f16: ; CHECK-LABEL: intrinsic_vfnmacc_mask_vv_nxv2f16_nxv2f16_nxv2f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfnmacc.vv v8, v9, v10, v0.t ; CHECK-NEXT: vfnmacc.vv v8, v9, v10, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x half> @llvm.riscv.vfnmacc.mask.nxv2f16.nxv2f16( %a = call <vscale x 2 x half> @llvm.riscv.vfnmacc.mask.nxv2f16.nxv2f16(
<vscale x 2 x half> %0, <vscale x 2 x half> %0,
<vscale x 2 x half> %1, <vscale x 2 x half> %1,
<vscale x 2 x half> %2, <vscale x 2 x half> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
iXLen %4, iXLen 0); iXLen 0, iXLen %4, iXLen 0);
ret <vscale x 2 x half> %a ret <vscale x 2 x half> %a
} }
declare <vscale x 4 x half> @llvm.riscv.vfnmacc.nxv4f16.nxv4f16( declare <vscale x 4 x half> @llvm.riscv.vfnmacc.nxv4f16.nxv4f16(
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 4 x half>, <vscale x 4 x half>,
iXLen, iXLen, iXLen, iXLen);
iXLen);
define <vscale x 4 x half> @intrinsic_vfnmacc_vv_nxv4f16_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, iXLen %3) nounwind { define <vscale x 4 x half> @intrinsic_vfnmacc_vv_nxv4f16_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfnmacc_vv_nxv4f16_nxv4f16_nxv4f16: ; CHECK-LABEL: intrinsic_vfnmacc_vv_nxv4f16_nxv4f16_nxv4f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, ma ; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, ma
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfnmacc.vv v8, v9, v10 ; CHECK-NEXT: vfnmacc.vv v8, v9, v10
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x half> @llvm.riscv.vfnmacc.nxv4f16.nxv4f16( %a = call <vscale x 4 x half> @llvm.riscv.vfnmacc.nxv4f16.nxv4f16(
<vscale x 4 x half> %0, <vscale x 4 x half> %0,
<vscale x 4 x half> %1, <vscale x 4 x half> %1,
<vscale x 4 x half> %2, <vscale x 4 x half> %2,
iXLen %3, iXLen 0) iXLen 0, iXLen %3, iXLen 0)
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 4 x half> @llvm.riscv.vfnmacc.mask.nxv4f16.nxv4f16( declare <vscale x 4 x half> @llvm.riscv.vfnmacc.mask.nxv4f16.nxv4f16(
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
iXLen, iXLen); iXLen, iXLen, iXLen);
define <vscale x 4 x half> @intrinsic_vfnmacc_mask_vv_nxv4f16_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind { define <vscale x 4 x half> @intrinsic_vfnmacc_mask_vv_nxv4f16_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfnmacc_mask_vv_nxv4f16_nxv4f16_nxv4f16: ; CHECK-LABEL: intrinsic_vfnmacc_mask_vv_nxv4f16_nxv4f16_nxv4f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfnmacc.vv v8, v9, v10, v0.t ; CHECK-NEXT: vfnmacc.vv v8, v9, v10, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x half> @llvm.riscv.vfnmacc.mask.nxv4f16.nxv4f16( %a = call <vscale x 4 x half> @llvm.riscv.vfnmacc.mask.nxv4f16.nxv4f16(
<vscale x 4 x half> %0, <vscale x 4 x half> %0,
<vscale x 4 x half> %1, <vscale x 4 x half> %1,
<vscale x 4 x half> %2, <vscale x 4 x half> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
iXLen %4, iXLen 0); iXLen 0, iXLen %4, iXLen 0);
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 8 x half> @llvm.riscv.vfnmacc.nxv8f16.nxv8f16( declare <vscale x 8 x half> @llvm.riscv.vfnmacc.nxv8f16.nxv8f16(
<vscale x 8 x half>, <vscale x 8 x half>,
<vscale x 8 x half>, <vscale x 8 x half>,
<vscale x 8 x half>, <vscale x 8 x half>,
iXLen, iXLen, iXLen, iXLen);
iXLen);
define <vscale x 8 x half> @intrinsic_vfnmacc_vv_nxv8f16_nxv8f16_nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, iXLen %3) nounwind { define <vscale x 8 x half> @intrinsic_vfnmacc_vv_nxv8f16_nxv8f16_nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfnmacc_vv_nxv8f16_nxv8f16_nxv8f16: ; CHECK-LABEL: intrinsic_vfnmacc_vv_nxv8f16_nxv8f16_nxv8f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, ma ; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, ma
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfnmacc.vv v8, v10, v12 ; CHECK-NEXT: vfnmacc.vv v8, v10, v12
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x half> @llvm.riscv.vfnmacc.nxv8f16.nxv8f16( %a = call <vscale x 8 x half> @llvm.riscv.vfnmacc.nxv8f16.nxv8f16(
<vscale x 8 x half> %0, <vscale x 8 x half> %0,
<vscale x 8 x half> %1, <vscale x 8 x half> %1,
<vscale x 8 x half> %2, <vscale x 8 x half> %2,
iXLen %3, iXLen 0) iXLen 0, iXLen %3, iXLen 0)
ret <vscale x 8 x half> %a ret <vscale x 8 x half> %a
} }
declare <vscale x 8 x half> @llvm.riscv.vfnmacc.mask.nxv8f16.nxv8f16( declare <vscale x 8 x half> @llvm.riscv.vfnmacc.mask.nxv8f16.nxv8f16(
<vscale x 8 x half>, <vscale x 8 x half>,
<vscale x 8 x half>, <vscale x 8 x half>,
<vscale x 8 x half>, <vscale x 8 x half>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
iXLen, iXLen); iXLen, iXLen, iXLen);
define <vscale x 8 x half> @intrinsic_vfnmacc_mask_vv_nxv8f16_nxv8f16_nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind { define <vscale x 8 x half> @intrinsic_vfnmacc_mask_vv_nxv8f16_nxv8f16_nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfnmacc_mask_vv_nxv8f16_nxv8f16_nxv8f16: ; CHECK-LABEL: intrinsic_vfnmacc_mask_vv_nxv8f16_nxv8f16_nxv8f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, mu
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfnmacc.vv v8, v10, v12, v0.t ; CHECK-NEXT: vfnmacc.vv v8, v10, v12, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x half> @llvm.riscv.vfnmacc.mask.nxv8f16.nxv8f16( %a = call <vscale x 8 x half> @llvm.riscv.vfnmacc.mask.nxv8f16.nxv8f16(
<vscale x 8 x half> %0, <vscale x 8 x half> %0,
<vscale x 8 x half> %1, <vscale x 8 x half> %1,
<vscale x 8 x half> %2, <vscale x 8 x half> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
iXLen %4, iXLen 0); iXLen 0, iXLen %4, iXLen 0);
ret <vscale x 8 x half> %a ret <vscale x 8 x half> %a
} }
declare <vscale x 16 x half> @llvm.riscv.vfnmacc.nxv16f16.nxv16f16( declare <vscale x 16 x half> @llvm.riscv.vfnmacc.nxv16f16.nxv16f16(
<vscale x 16 x half>, <vscale x 16 x half>,
<vscale x 16 x half>, <vscale x 16 x half>,
<vscale x 16 x half>, <vscale x 16 x half>,
iXLen, iXLen, iXLen, iXLen);
iXLen);
define <vscale x 16 x half> @intrinsic_vfnmacc_vv_nxv16f16_nxv16f16_nxv16f16(<vscale x 16 x half> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %2, iXLen %3) nounwind { define <vscale x 16 x half> @intrinsic_vfnmacc_vv_nxv16f16_nxv16f16_nxv16f16(<vscale x 16 x half> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfnmacc_vv_nxv16f16_nxv16f16_nxv16f16: ; CHECK-LABEL: intrinsic_vfnmacc_vv_nxv16f16_nxv16f16_nxv16f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, ma ; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, ma
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfnmacc.vv v8, v12, v16 ; CHECK-NEXT: vfnmacc.vv v8, v12, v16
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x half> @llvm.riscv.vfnmacc.nxv16f16.nxv16f16( %a = call <vscale x 16 x half> @llvm.riscv.vfnmacc.nxv16f16.nxv16f16(
<vscale x 16 x half> %0, <vscale x 16 x half> %0,
<vscale x 16 x half> %1, <vscale x 16 x half> %1,
<vscale x 16 x half> %2, <vscale x 16 x half> %2,
iXLen %3, iXLen 0) iXLen 0, iXLen %3, iXLen 0)
ret <vscale x 16 x half> %a ret <vscale x 16 x half> %a
} }
declare <vscale x 16 x half> @llvm.riscv.vfnmacc.mask.nxv16f16.nxv16f16( declare <vscale x 16 x half> @llvm.riscv.vfnmacc.mask.nxv16f16.nxv16f16(
<vscale x 16 x half>, <vscale x 16 x half>,
<vscale x 16 x half>, <vscale x 16 x half>,
<vscale x 16 x half>, <vscale x 16 x half>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
iXLen, iXLen); iXLen, iXLen, iXLen);
define <vscale x 16 x half> @intrinsic_vfnmacc_mask_vv_nxv16f16_nxv16f16_nxv16f16(<vscale x 16 x half> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind { define <vscale x 16 x half> @intrinsic_vfnmacc_mask_vv_nxv16f16_nxv16f16_nxv16f16(<vscale x 16 x half> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfnmacc_mask_vv_nxv16f16_nxv16f16_nxv16f16: ; CHECK-LABEL: intrinsic_vfnmacc_mask_vv_nxv16f16_nxv16f16_nxv16f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfnmacc.vv v8, v12, v16, v0.t ; CHECK-NEXT: vfnmacc.vv v8, v12, v16, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x half> @llvm.riscv.vfnmacc.mask.nxv16f16.nxv16f16( %a = call <vscale x 16 x half> @llvm.riscv.vfnmacc.mask.nxv16f16.nxv16f16(
<vscale x 16 x half> %0, <vscale x 16 x half> %0,
<vscale x 16 x half> %1, <vscale x 16 x half> %1,
<vscale x 16 x half> %2, <vscale x 16 x half> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
iXLen %4, iXLen 0); iXLen 0, iXLen %4, iXLen 0);
ret <vscale x 16 x half> %a ret <vscale x 16 x half> %a
} }
declare <vscale x 1 x float> @llvm.riscv.vfnmacc.nxv1f32.nxv1f32( declare <vscale x 1 x float> @llvm.riscv.vfnmacc.nxv1f32.nxv1f32(
<vscale x 1 x float>, <vscale x 1 x float>,
<vscale x 1 x float>, <vscale x 1 x float>,
<vscale x 1 x float>, <vscale x 1 x float>,
iXLen, iXLen, iXLen, iXLen);
iXLen);
define <vscale x 1 x float> @intrinsic_vfnmacc_vv_nxv1f32_nxv1f32_nxv1f32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, iXLen %3) nounwind { define <vscale x 1 x float> @intrinsic_vfnmacc_vv_nxv1f32_nxv1f32_nxv1f32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfnmacc_vv_nxv1f32_nxv1f32_nxv1f32: ; CHECK-LABEL: intrinsic_vfnmacc_vv_nxv1f32_nxv1f32_nxv1f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, ma ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, ma
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfnmacc.vv v8, v9, v10 ; CHECK-NEXT: vfnmacc.vv v8, v9, v10
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x float> @llvm.riscv.vfnmacc.nxv1f32.nxv1f32( %a = call <vscale x 1 x float> @llvm.riscv.vfnmacc.nxv1f32.nxv1f32(
<vscale x 1 x float> %0, <vscale x 1 x float> %0,
<vscale x 1 x float> %1, <vscale x 1 x float> %1,
<vscale x 1 x float> %2, <vscale x 1 x float> %2,
iXLen %3, iXLen 0) iXLen 0, iXLen %3, iXLen 0)
ret <vscale x 1 x float> %a ret <vscale x 1 x float> %a
} }
declare <vscale x 1 x float> @llvm.riscv.vfnmacc.mask.nxv1f32.nxv1f32( declare <vscale x 1 x float> @llvm.riscv.vfnmacc.mask.nxv1f32.nxv1f32(
<vscale x 1 x float>, <vscale x 1 x float>,
<vscale x 1 x float>, <vscale x 1 x float>,
<vscale x 1 x float>, <vscale x 1 x float>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
iXLen, iXLen); iXLen, iXLen, iXLen);
define <vscale x 1 x float> @intrinsic_vfnmacc_mask_vv_nxv1f32_nxv1f32_nxv1f32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind { define <vscale x 1 x float> @intrinsic_vfnmacc_mask_vv_nxv1f32_nxv1f32_nxv1f32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfnmacc_mask_vv_nxv1f32_nxv1f32_nxv1f32: ; CHECK-LABEL: intrinsic_vfnmacc_mask_vv_nxv1f32_nxv1f32_nxv1f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfnmacc.vv v8, v9, v10, v0.t ; CHECK-NEXT: vfnmacc.vv v8, v9, v10, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x float> @llvm.riscv.vfnmacc.mask.nxv1f32.nxv1f32( %a = call <vscale x 1 x float> @llvm.riscv.vfnmacc.mask.nxv1f32.nxv1f32(
<vscale x 1 x float> %0, <vscale x 1 x float> %0,
<vscale x 1 x float> %1, <vscale x 1 x float> %1,
<vscale x 1 x float> %2, <vscale x 1 x float> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
iXLen %4, iXLen 0); iXLen 0, iXLen %4, iXLen 0);
ret <vscale x 1 x float> %a ret <vscale x 1 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vfnmacc.nxv2f32.nxv2f32( declare <vscale x 2 x float> @llvm.riscv.vfnmacc.nxv2f32.nxv2f32(
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 2 x float>, <vscale x 2 x float>,
iXLen, iXLen, iXLen, iXLen);
iXLen);
define <vscale x 2 x float> @intrinsic_vfnmacc_vv_nxv2f32_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, iXLen %3) nounwind { define <vscale x 2 x float> @intrinsic_vfnmacc_vv_nxv2f32_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfnmacc_vv_nxv2f32_nxv2f32_nxv2f32: ; CHECK-LABEL: intrinsic_vfnmacc_vv_nxv2f32_nxv2f32_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, ma ; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, ma
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfnmacc.vv v8, v9, v10 ; CHECK-NEXT: vfnmacc.vv v8, v9, v10
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfnmacc.nxv2f32.nxv2f32( %a = call <vscale x 2 x float> @llvm.riscv.vfnmacc.nxv2f32.nxv2f32(
<vscale x 2 x float> %0, <vscale x 2 x float> %0,
<vscale x 2 x float> %1, <vscale x 2 x float> %1,
<vscale x 2 x float> %2, <vscale x 2 x float> %2,
iXLen %3, iXLen 0) iXLen 0, iXLen %3, iXLen 0)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vfnmacc.mask.nxv2f32.nxv2f32( declare <vscale x 2 x float> @llvm.riscv.vfnmacc.mask.nxv2f32.nxv2f32(
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
iXLen, iXLen); iXLen, iXLen, iXLen);
define <vscale x 2 x float> @intrinsic_vfnmacc_mask_vv_nxv2f32_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind { define <vscale x 2 x float> @intrinsic_vfnmacc_mask_vv_nxv2f32_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfnmacc_mask_vv_nxv2f32_nxv2f32_nxv2f32: ; CHECK-LABEL: intrinsic_vfnmacc_mask_vv_nxv2f32_nxv2f32_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfnmacc.vv v8, v9, v10, v0.t ; CHECK-NEXT: vfnmacc.vv v8, v9, v10, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfnmacc.mask.nxv2f32.nxv2f32( %a = call <vscale x 2 x float> @llvm.riscv.vfnmacc.mask.nxv2f32.nxv2f32(
<vscale x 2 x float> %0, <vscale x 2 x float> %0,
<vscale x 2 x float> %1, <vscale x 2 x float> %1,
<vscale x 2 x float> %2, <vscale x 2 x float> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
iXLen %4, iXLen 0); iXLen 0, iXLen %4, iXLen 0);
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 4 x float> @llvm.riscv.vfnmacc.nxv4f32.nxv4f32( declare <vscale x 4 x float> @llvm.riscv.vfnmacc.nxv4f32.nxv4f32(
<vscale x 4 x float>, <vscale x 4 x float>,
<vscale x 4 x float>, <vscale x 4 x float>,
<vscale x 4 x float>, <vscale x 4 x float>,
iXLen, iXLen, iXLen, iXLen);
iXLen);
define <vscale x 4 x float> @intrinsic_vfnmacc_vv_nxv4f32_nxv4f32_nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, <vscale x 4 x float> %2, iXLen %3) nounwind { define <vscale x 4 x float> @intrinsic_vfnmacc_vv_nxv4f32_nxv4f32_nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, <vscale x 4 x float> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfnmacc_vv_nxv4f32_nxv4f32_nxv4f32: ; CHECK-LABEL: intrinsic_vfnmacc_vv_nxv4f32_nxv4f32_nxv4f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, ma ; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, ma
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfnmacc.vv v8, v10, v12 ; CHECK-NEXT: vfnmacc.vv v8, v10, v12
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x float> @llvm.riscv.vfnmacc.nxv4f32.nxv4f32( %a = call <vscale x 4 x float> @llvm.riscv.vfnmacc.nxv4f32.nxv4f32(
<vscale x 4 x float> %0, <vscale x 4 x float> %0,
<vscale x 4 x float> %1, <vscale x 4 x float> %1,
<vscale x 4 x float> %2, <vscale x 4 x float> %2,
iXLen %3, iXLen 0) iXLen 0, iXLen %3, iXLen 0)
ret <vscale x 4 x float> %a ret <vscale x 4 x float> %a
} }
declare <vscale x 4 x float> @llvm.riscv.vfnmacc.mask.nxv4f32.nxv4f32( declare <vscale x 4 x float> @llvm.riscv.vfnmacc.mask.nxv4f32.nxv4f32(
<vscale x 4 x float>, <vscale x 4 x float>,
<vscale x 4 x float>, <vscale x 4 x float>,
<vscale x 4 x float>, <vscale x 4 x float>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
iXLen, iXLen); iXLen, iXLen, iXLen);
define <vscale x 4 x float> @intrinsic_vfnmacc_mask_vv_nxv4f32_nxv4f32_nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, <vscale x 4 x float> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind { define <vscale x 4 x float> @intrinsic_vfnmacc_mask_vv_nxv4f32_nxv4f32_nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, <vscale x 4 x float> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfnmacc_mask_vv_nxv4f32_nxv4f32_nxv4f32: ; CHECK-LABEL: intrinsic_vfnmacc_mask_vv_nxv4f32_nxv4f32_nxv4f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfnmacc.vv v8, v10, v12, v0.t ; CHECK-NEXT: vfnmacc.vv v8, v10, v12, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x float> @llvm.riscv.vfnmacc.mask.nxv4f32.nxv4f32( %a = call <vscale x 4 x float> @llvm.riscv.vfnmacc.mask.nxv4f32.nxv4f32(
<vscale x 4 x float> %0, <vscale x 4 x float> %0,
<vscale x 4 x float> %1, <vscale x 4 x float> %1,
<vscale x 4 x float> %2, <vscale x 4 x float> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
iXLen %4, iXLen 0); iXLen 0, iXLen %4, iXLen 0);
ret <vscale x 4 x float> %a ret <vscale x 4 x float> %a
} }
declare <vscale x 8 x float> @llvm.riscv.vfnmacc.nxv8f32.nxv8f32( declare <vscale x 8 x float> @llvm.riscv.vfnmacc.nxv8f32.nxv8f32(
<vscale x 8 x float>, <vscale x 8 x float>,
<vscale x 8 x float>, <vscale x 8 x float>,
<vscale x 8 x float>, <vscale x 8 x float>,
iXLen, iXLen, iXLen, iXLen);
iXLen);
define <vscale x 8 x float> @intrinsic_vfnmacc_vv_nxv8f32_nxv8f32_nxv8f32(<vscale x 8 x float> %0, <vscale x 8 x float> %1, <vscale x 8 x float> %2, iXLen %3) nounwind { define <vscale x 8 x float> @intrinsic_vfnmacc_vv_nxv8f32_nxv8f32_nxv8f32(<vscale x 8 x float> %0, <vscale x 8 x float> %1, <vscale x 8 x float> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfnmacc_vv_nxv8f32_nxv8f32_nxv8f32: ; CHECK-LABEL: intrinsic_vfnmacc_vv_nxv8f32_nxv8f32_nxv8f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, ma ; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, ma
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfnmacc.vv v8, v12, v16 ; CHECK-NEXT: vfnmacc.vv v8, v12, v16
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x float> @llvm.riscv.vfnmacc.nxv8f32.nxv8f32( %a = call <vscale x 8 x float> @llvm.riscv.vfnmacc.nxv8f32.nxv8f32(
<vscale x 8 x float> %0, <vscale x 8 x float> %0,
<vscale x 8 x float> %1, <vscale x 8 x float> %1,
<vscale x 8 x float> %2, <vscale x 8 x float> %2,
iXLen %3, iXLen 0) iXLen 0, iXLen %3, iXLen 0)
ret <vscale x 8 x float> %a ret <vscale x 8 x float> %a
} }
declare <vscale x 8 x float> @llvm.riscv.vfnmacc.mask.nxv8f32.nxv8f32( declare <vscale x 8 x float> @llvm.riscv.vfnmacc.mask.nxv8f32.nxv8f32(
<vscale x 8 x float>, <vscale x 8 x float>,
<vscale x 8 x float>, <vscale x 8 x float>,
<vscale x 8 x float>, <vscale x 8 x float>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
iXLen, iXLen); iXLen, iXLen, iXLen);
define <vscale x 8 x float> @intrinsic_vfnmacc_mask_vv_nxv8f32_nxv8f32_nxv8f32(<vscale x 8 x float> %0, <vscale x 8 x float> %1, <vscale x 8 x float> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind { define <vscale x 8 x float> @intrinsic_vfnmacc_mask_vv_nxv8f32_nxv8f32_nxv8f32(<vscale x 8 x float> %0, <vscale x 8 x float> %1, <vscale x 8 x float> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfnmacc_mask_vv_nxv8f32_nxv8f32_nxv8f32: ; CHECK-LABEL: intrinsic_vfnmacc_mask_vv_nxv8f32_nxv8f32_nxv8f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfnmacc.vv v8, v12, v16, v0.t ; CHECK-NEXT: vfnmacc.vv v8, v12, v16, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x float> @llvm.riscv.vfnmacc.mask.nxv8f32.nxv8f32( %a = call <vscale x 8 x float> @llvm.riscv.vfnmacc.mask.nxv8f32.nxv8f32(
<vscale x 8 x float> %0, <vscale x 8 x float> %0,
<vscale x 8 x float> %1, <vscale x 8 x float> %1,
<vscale x 8 x float> %2, <vscale x 8 x float> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
iXLen %4, iXLen 0); iXLen 0, iXLen %4, iXLen 0);
ret <vscale x 8 x float> %a ret <vscale x 8 x float> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vfnmacc.nxv1f64.nxv1f64( declare <vscale x 1 x double> @llvm.riscv.vfnmacc.nxv1f64.nxv1f64(
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 1 x double>, <vscale x 1 x double>,
iXLen, iXLen, iXLen, iXLen);
iXLen);
define <vscale x 1 x double> @intrinsic_vfnmacc_vv_nxv1f64_nxv1f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 1 x double> %1, <vscale x 1 x double> %2, iXLen %3) nounwind { define <vscale x 1 x double> @intrinsic_vfnmacc_vv_nxv1f64_nxv1f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 1 x double> %1, <vscale x 1 x double> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfnmacc_vv_nxv1f64_nxv1f64_nxv1f64: ; CHECK-LABEL: intrinsic_vfnmacc_vv_nxv1f64_nxv1f64_nxv1f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, ma ; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, ma
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfnmacc.vv v8, v9, v10 ; CHECK-NEXT: vfnmacc.vv v8, v9, v10
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfnmacc.nxv1f64.nxv1f64( %a = call <vscale x 1 x double> @llvm.riscv.vfnmacc.nxv1f64.nxv1f64(
<vscale x 1 x double> %0, <vscale x 1 x double> %0,
<vscale x 1 x double> %1, <vscale x 1 x double> %1,
<vscale x 1 x double> %2, <vscale x 1 x double> %2,
iXLen %3, iXLen 0) iXLen 0, iXLen %3, iXLen 0)
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vfnmacc.mask.nxv1f64.nxv1f64( declare <vscale x 1 x double> @llvm.riscv.vfnmacc.mask.nxv1f64.nxv1f64(
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
iXLen, iXLen); iXLen, iXLen, iXLen);
define <vscale x 1 x double> @intrinsic_vfnmacc_mask_vv_nxv1f64_nxv1f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 1 x double> %1, <vscale x 1 x double> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind { define <vscale x 1 x double> @intrinsic_vfnmacc_mask_vv_nxv1f64_nxv1f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 1 x double> %1, <vscale x 1 x double> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfnmacc_mask_vv_nxv1f64_nxv1f64_nxv1f64: ; CHECK-LABEL: intrinsic_vfnmacc_mask_vv_nxv1f64_nxv1f64_nxv1f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, mu
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfnmacc.vv v8, v9, v10, v0.t ; CHECK-NEXT: vfnmacc.vv v8, v9, v10, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfnmacc.mask.nxv1f64.nxv1f64( %a = call <vscale x 1 x double> @llvm.riscv.vfnmacc.mask.nxv1f64.nxv1f64(
<vscale x 1 x double> %0, <vscale x 1 x double> %0,
<vscale x 1 x double> %1, <vscale x 1 x double> %1,
<vscale x 1 x double> %2, <vscale x 1 x double> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
iXLen %4, iXLen 0); iXLen 0, iXLen %4, iXLen 0);
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 2 x double> @llvm.riscv.vfnmacc.nxv2f64.nxv2f64( declare <vscale x 2 x double> @llvm.riscv.vfnmacc.nxv2f64.nxv2f64(
<vscale x 2 x double>, <vscale x 2 x double>,
<vscale x 2 x double>, <vscale x 2 x double>,
<vscale x 2 x double>, <vscale x 2 x double>,
iXLen, iXLen, iXLen, iXLen);
iXLen);
define <vscale x 2 x double> @intrinsic_vfnmacc_vv_nxv2f64_nxv2f64_nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1, <vscale x 2 x double> %2, iXLen %3) nounwind { define <vscale x 2 x double> @intrinsic_vfnmacc_vv_nxv2f64_nxv2f64_nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1, <vscale x 2 x double> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfnmacc_vv_nxv2f64_nxv2f64_nxv2f64: ; CHECK-LABEL: intrinsic_vfnmacc_vv_nxv2f64_nxv2f64_nxv2f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, ma ; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, ma
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfnmacc.vv v8, v10, v12 ; CHECK-NEXT: vfnmacc.vv v8, v10, v12
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x double> @llvm.riscv.vfnmacc.nxv2f64.nxv2f64( %a = call <vscale x 2 x double> @llvm.riscv.vfnmacc.nxv2f64.nxv2f64(
<vscale x 2 x double> %0, <vscale x 2 x double> %0,
<vscale x 2 x double> %1, <vscale x 2 x double> %1,
<vscale x 2 x double> %2, <vscale x 2 x double> %2,
iXLen %3, iXLen 0) iXLen 0, iXLen %3, iXLen 0)
ret <vscale x 2 x double> %a ret <vscale x 2 x double> %a
} }
declare <vscale x 2 x double> @llvm.riscv.vfnmacc.mask.nxv2f64.nxv2f64( declare <vscale x 2 x double> @llvm.riscv.vfnmacc.mask.nxv2f64.nxv2f64(
<vscale x 2 x double>, <vscale x 2 x double>,
<vscale x 2 x double>, <vscale x 2 x double>,
<vscale x 2 x double>, <vscale x 2 x double>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
iXLen, iXLen); iXLen, iXLen, iXLen);
define <vscale x 2 x double> @intrinsic_vfnmacc_mask_vv_nxv2f64_nxv2f64_nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1, <vscale x 2 x double> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind { define <vscale x 2 x double> @intrinsic_vfnmacc_mask_vv_nxv2f64_nxv2f64_nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1, <vscale x 2 x double> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfnmacc_mask_vv_nxv2f64_nxv2f64_nxv2f64: ; CHECK-LABEL: intrinsic_vfnmacc_mask_vv_nxv2f64_nxv2f64_nxv2f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, mu
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfnmacc.vv v8, v10, v12, v0.t ; CHECK-NEXT: vfnmacc.vv v8, v10, v12, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x double> @llvm.riscv.vfnmacc.mask.nxv2f64.nxv2f64( %a = call <vscale x 2 x double> @llvm.riscv.vfnmacc.mask.nxv2f64.nxv2f64(
<vscale x 2 x double> %0, <vscale x 2 x double> %0,
<vscale x 2 x double> %1, <vscale x 2 x double> %1,
<vscale x 2 x double> %2, <vscale x 2 x double> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
iXLen %4, iXLen 0); iXLen 0, iXLen %4, iXLen 0);
ret <vscale x 2 x double> %a ret <vscale x 2 x double> %a
} }
declare <vscale x 4 x double> @llvm.riscv.vfnmacc.nxv4f64.nxv4f64( declare <vscale x 4 x double> @llvm.riscv.vfnmacc.nxv4f64.nxv4f64(
<vscale x 4 x double>, <vscale x 4 x double>,
<vscale x 4 x double>, <vscale x 4 x double>,
<vscale x 4 x double>, <vscale x 4 x double>,
iXLen, iXLen, iXLen, iXLen);
iXLen);
define <vscale x 4 x double> @intrinsic_vfnmacc_vv_nxv4f64_nxv4f64_nxv4f64(<vscale x 4 x double> %0, <vscale x 4 x double> %1, <vscale x 4 x double> %2, iXLen %3) nounwind { define <vscale x 4 x double> @intrinsic_vfnmacc_vv_nxv4f64_nxv4f64_nxv4f64(<vscale x 4 x double> %0, <vscale x 4 x double> %1, <vscale x 4 x double> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfnmacc_vv_nxv4f64_nxv4f64_nxv4f64: ; CHECK-LABEL: intrinsic_vfnmacc_vv_nxv4f64_nxv4f64_nxv4f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, ma ; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, ma
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfnmacc.vv v8, v12, v16 ; CHECK-NEXT: vfnmacc.vv v8, v12, v16
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x double> @llvm.riscv.vfnmacc.nxv4f64.nxv4f64( %a = call <vscale x 4 x double> @llvm.riscv.vfnmacc.nxv4f64.nxv4f64(
<vscale x 4 x double> %0, <vscale x 4 x double> %0,
<vscale x 4 x double> %1, <vscale x 4 x double> %1,
<vscale x 4 x double> %2, <vscale x 4 x double> %2,
iXLen %3, iXLen 0) iXLen 0, iXLen %3, iXLen 0)
ret <vscale x 4 x double> %a ret <vscale x 4 x double> %a
} }
declare <vscale x 4 x double> @llvm.riscv.vfnmacc.mask.nxv4f64.nxv4f64( declare <vscale x 4 x double> @llvm.riscv.vfnmacc.mask.nxv4f64.nxv4f64(
<vscale x 4 x double>, <vscale x 4 x double>,
<vscale x 4 x double>, <vscale x 4 x double>,
<vscale x 4 x double>, <vscale x 4 x double>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
iXLen, iXLen); iXLen, iXLen, iXLen);
define <vscale x 4 x double> @intrinsic_vfnmacc_mask_vv_nxv4f64_nxv4f64_nxv4f64(<vscale x 4 x double> %0, <vscale x 4 x double> %1, <vscale x 4 x double> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind { define <vscale x 4 x double> @intrinsic_vfnmacc_mask_vv_nxv4f64_nxv4f64_nxv4f64(<vscale x 4 x double> %0, <vscale x 4 x double> %1, <vscale x 4 x double> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfnmacc_mask_vv_nxv4f64_nxv4f64_nxv4f64: ; CHECK-LABEL: intrinsic_vfnmacc_mask_vv_nxv4f64_nxv4f64_nxv4f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, mu
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfnmacc.vv v8, v12, v16, v0.t ; CHECK-NEXT: vfnmacc.vv v8, v12, v16, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x double> @llvm.riscv.vfnmacc.mask.nxv4f64.nxv4f64( %a = call <vscale x 4 x double> @llvm.riscv.vfnmacc.mask.nxv4f64.nxv4f64(
<vscale x 4 x double> %0, <vscale x 4 x double> %0,
<vscale x 4 x double> %1, <vscale x 4 x double> %1,
<vscale x 4 x double> %2, <vscale x 4 x double> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
iXLen %4, iXLen 0); iXLen 0, iXLen %4, iXLen 0);
ret <vscale x 4 x double> %a ret <vscale x 4 x double> %a
} }
declare <vscale x 1 x half> @llvm.riscv.vfnmacc.nxv1f16.f16( declare <vscale x 1 x half> @llvm.riscv.vfnmacc.nxv1f16.f16(
<vscale x 1 x half>, <vscale x 1 x half>,
half, half,
<vscale x 1 x half>, <vscale x 1 x half>,
iXLen, iXLen, iXLen, iXLen);
iXLen);
define <vscale x 1 x half> @intrinsic_vfnmacc_vf_nxv1f16_f16_nxv1f16(<vscale x 1 x half> %0, half %1, <vscale x 1 x half> %2, iXLen %3) nounwind { define <vscale x 1 x half> @intrinsic_vfnmacc_vf_nxv1f16_f16_nxv1f16(<vscale x 1 x half> %0, half %1, <vscale x 1 x half> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfnmacc_vf_nxv1f16_f16_nxv1f16: ; CHECK-LABEL: intrinsic_vfnmacc_vf_nxv1f16_f16_nxv1f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, ma ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, ma
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfnmacc.vf v8, fa0, v9 ; CHECK-NEXT: vfnmacc.vf v8, fa0, v9
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x half> @llvm.riscv.vfnmacc.nxv1f16.f16( %a = call <vscale x 1 x half> @llvm.riscv.vfnmacc.nxv1f16.f16(
<vscale x 1 x half> %0, <vscale x 1 x half> %0,
half %1, half %1,
<vscale x 1 x half> %2, <vscale x 1 x half> %2,
iXLen %3, iXLen 0) iXLen 0, iXLen %3, iXLen 0)
ret <vscale x 1 x half> %a ret <vscale x 1 x half> %a
} }
declare <vscale x 1 x half> @llvm.riscv.vfnmacc.mask.nxv1f16.f16( declare <vscale x 1 x half> @llvm.riscv.vfnmacc.mask.nxv1f16.f16(
<vscale x 1 x half>, <vscale x 1 x half>,
half, half,
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
iXLen, iXLen); iXLen, iXLen, iXLen);
define <vscale x 1 x half> @intrinsic_vfnmacc_mask_vf_nxv1f16_f16_nxv1f16(<vscale x 1 x half> %0, half %1, <vscale x 1 x half> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind { define <vscale x 1 x half> @intrinsic_vfnmacc_mask_vf_nxv1f16_f16_nxv1f16(<vscale x 1 x half> %0, half %1, <vscale x 1 x half> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfnmacc_mask_vf_nxv1f16_f16_nxv1f16: ; CHECK-LABEL: intrinsic_vfnmacc_mask_vf_nxv1f16_f16_nxv1f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfnmacc.vf v8, fa0, v9, v0.t ; CHECK-NEXT: vfnmacc.vf v8, fa0, v9, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x half> @llvm.riscv.vfnmacc.mask.nxv1f16.f16( %a = call <vscale x 1 x half> @llvm.riscv.vfnmacc.mask.nxv1f16.f16(
<vscale x 1 x half> %0, <vscale x 1 x half> %0,
half %1, half %1,
<vscale x 1 x half> %2, <vscale x 1 x half> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
iXLen %4, iXLen 0); iXLen 0, iXLen %4, iXLen 0);
ret <vscale x 1 x half> %a ret <vscale x 1 x half> %a
} }
declare <vscale x 2 x half> @llvm.riscv.vfnmacc.nxv2f16.f16( declare <vscale x 2 x half> @llvm.riscv.vfnmacc.nxv2f16.f16(
<vscale x 2 x half>, <vscale x 2 x half>,
half, half,
<vscale x 2 x half>, <vscale x 2 x half>,
iXLen, iXLen, iXLen, iXLen);
iXLen);
define <vscale x 2 x half> @intrinsic_vfnmacc_vf_nxv2f16_f16_nxv2f16(<vscale x 2 x half> %0, half %1, <vscale x 2 x half> %2, iXLen %3) nounwind { define <vscale x 2 x half> @intrinsic_vfnmacc_vf_nxv2f16_f16_nxv2f16(<vscale x 2 x half> %0, half %1, <vscale x 2 x half> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfnmacc_vf_nxv2f16_f16_nxv2f16: ; CHECK-LABEL: intrinsic_vfnmacc_vf_nxv2f16_f16_nxv2f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, ma ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, ma
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfnmacc.vf v8, fa0, v9 ; CHECK-NEXT: vfnmacc.vf v8, fa0, v9
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x half> @llvm.riscv.vfnmacc.nxv2f16.f16( %a = call <vscale x 2 x half> @llvm.riscv.vfnmacc.nxv2f16.f16(
<vscale x 2 x half> %0, <vscale x 2 x half> %0,
half %1, half %1,
<vscale x 2 x half> %2, <vscale x 2 x half> %2,
iXLen %3, iXLen 0) iXLen 0, iXLen %3, iXLen 0)
ret <vscale x 2 x half> %a ret <vscale x 2 x half> %a
} }
declare <vscale x 2 x half> @llvm.riscv.vfnmacc.mask.nxv2f16.f16( declare <vscale x 2 x half> @llvm.riscv.vfnmacc.mask.nxv2f16.f16(
<vscale x 2 x half>, <vscale x 2 x half>,
half, half,
<vscale x 2 x half>, <vscale x 2 x half>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
iXLen, iXLen); iXLen, iXLen, iXLen);
define <vscale x 2 x half> @intrinsic_vfnmacc_mask_vf_nxv2f16_f16_nxv2f16(<vscale x 2 x half> %0, half %1, <vscale x 2 x half> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind { define <vscale x 2 x half> @intrinsic_vfnmacc_mask_vf_nxv2f16_f16_nxv2f16(<vscale x 2 x half> %0, half %1, <vscale x 2 x half> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfnmacc_mask_vf_nxv2f16_f16_nxv2f16: ; CHECK-LABEL: intrinsic_vfnmacc_mask_vf_nxv2f16_f16_nxv2f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfnmacc.vf v8, fa0, v9, v0.t ; CHECK-NEXT: vfnmacc.vf v8, fa0, v9, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x half> @llvm.riscv.vfnmacc.mask.nxv2f16.f16( %a = call <vscale x 2 x half> @llvm.riscv.vfnmacc.mask.nxv2f16.f16(
<vscale x 2 x half> %0, <vscale x 2 x half> %0,
half %1, half %1,
<vscale x 2 x half> %2, <vscale x 2 x half> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
iXLen %4, iXLen 0); iXLen 0, iXLen %4, iXLen 0);
ret <vscale x 2 x half> %a ret <vscale x 2 x half> %a
} }
declare <vscale x 4 x half> @llvm.riscv.vfnmacc.nxv4f16.f16( declare <vscale x 4 x half> @llvm.riscv.vfnmacc.nxv4f16.f16(
<vscale x 4 x half>, <vscale x 4 x half>,
half, half,
<vscale x 4 x half>, <vscale x 4 x half>,
iXLen, iXLen, iXLen, iXLen);
iXLen);
define <vscale x 4 x half> @intrinsic_vfnmacc_vf_nxv4f16_f16_nxv4f16(<vscale x 4 x half> %0, half %1, <vscale x 4 x half> %2, iXLen %3) nounwind { define <vscale x 4 x half> @intrinsic_vfnmacc_vf_nxv4f16_f16_nxv4f16(<vscale x 4 x half> %0, half %1, <vscale x 4 x half> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfnmacc_vf_nxv4f16_f16_nxv4f16: ; CHECK-LABEL: intrinsic_vfnmacc_vf_nxv4f16_f16_nxv4f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, ma ; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, ma
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfnmacc.vf v8, fa0, v9 ; CHECK-NEXT: vfnmacc.vf v8, fa0, v9
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x half> @llvm.riscv.vfnmacc.nxv4f16.f16( %a = call <vscale x 4 x half> @llvm.riscv.vfnmacc.nxv4f16.f16(
<vscale x 4 x half> %0, <vscale x 4 x half> %0,
half %1, half %1,
<vscale x 4 x half> %2, <vscale x 4 x half> %2,
iXLen %3, iXLen 0) iXLen 0, iXLen %3, iXLen 0)
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 4 x half> @llvm.riscv.vfnmacc.mask.nxv4f16.f16( declare <vscale x 4 x half> @llvm.riscv.vfnmacc.mask.nxv4f16.f16(
<vscale x 4 x half>, <vscale x 4 x half>,
half, half,
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
iXLen, iXLen); iXLen, iXLen, iXLen);
define <vscale x 4 x half> @intrinsic_vfnmacc_mask_vf_nxv4f16_f16_nxv4f16(<vscale x 4 x half> %0, half %1, <vscale x 4 x half> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind { define <vscale x 4 x half> @intrinsic_vfnmacc_mask_vf_nxv4f16_f16_nxv4f16(<vscale x 4 x half> %0, half %1, <vscale x 4 x half> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfnmacc_mask_vf_nxv4f16_f16_nxv4f16: ; CHECK-LABEL: intrinsic_vfnmacc_mask_vf_nxv4f16_f16_nxv4f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfnmacc.vf v8, fa0, v9, v0.t ; CHECK-NEXT: vfnmacc.vf v8, fa0, v9, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x half> @llvm.riscv.vfnmacc.mask.nxv4f16.f16( %a = call <vscale x 4 x half> @llvm.riscv.vfnmacc.mask.nxv4f16.f16(
<vscale x 4 x half> %0, <vscale x 4 x half> %0,
half %1, half %1,
<vscale x 4 x half> %2, <vscale x 4 x half> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
iXLen %4, iXLen 0); iXLen 0, iXLen %4, iXLen 0);
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 8 x half> @llvm.riscv.vfnmacc.nxv8f16.f16( declare <vscale x 8 x half> @llvm.riscv.vfnmacc.nxv8f16.f16(
<vscale x 8 x half>, <vscale x 8 x half>,
half, half,
<vscale x 8 x half>, <vscale x 8 x half>,
iXLen, iXLen, iXLen, iXLen);
iXLen);
define <vscale x 8 x half> @intrinsic_vfnmacc_vf_nxv8f16_f16_nxv8f16(<vscale x 8 x half> %0, half %1, <vscale x 8 x half> %2, iXLen %3) nounwind { define <vscale x 8 x half> @intrinsic_vfnmacc_vf_nxv8f16_f16_nxv8f16(<vscale x 8 x half> %0, half %1, <vscale x 8 x half> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfnmacc_vf_nxv8f16_f16_nxv8f16: ; CHECK-LABEL: intrinsic_vfnmacc_vf_nxv8f16_f16_nxv8f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, ma ; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, ma
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfnmacc.vf v8, fa0, v10 ; CHECK-NEXT: vfnmacc.vf v8, fa0, v10
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x half> @llvm.riscv.vfnmacc.nxv8f16.f16( %a = call <vscale x 8 x half> @llvm.riscv.vfnmacc.nxv8f16.f16(
<vscale x 8 x half> %0, <vscale x 8 x half> %0,
half %1, half %1,
<vscale x 8 x half> %2, <vscale x 8 x half> %2,
iXLen %3, iXLen 0) iXLen 0, iXLen %3, iXLen 0)
ret <vscale x 8 x half> %a ret <vscale x 8 x half> %a
} }
declare <vscale x 8 x half> @llvm.riscv.vfnmacc.mask.nxv8f16.f16( declare <vscale x 8 x half> @llvm.riscv.vfnmacc.mask.nxv8f16.f16(
<vscale x 8 x half>, <vscale x 8 x half>,
half, half,
<vscale x 8 x half>, <vscale x 8 x half>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
iXLen, iXLen); iXLen, iXLen, iXLen);
define <vscale x 8 x half> @intrinsic_vfnmacc_mask_vf_nxv8f16_f16_nxv8f16(<vscale x 8 x half> %0, half %1, <vscale x 8 x half> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind { define <vscale x 8 x half> @intrinsic_vfnmacc_mask_vf_nxv8f16_f16_nxv8f16(<vscale x 8 x half> %0, half %1, <vscale x 8 x half> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfnmacc_mask_vf_nxv8f16_f16_nxv8f16: ; CHECK-LABEL: intrinsic_vfnmacc_mask_vf_nxv8f16_f16_nxv8f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, mu
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfnmacc.vf v8, fa0, v10, v0.t ; CHECK-NEXT: vfnmacc.vf v8, fa0, v10, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x half> @llvm.riscv.vfnmacc.mask.nxv8f16.f16( %a = call <vscale x 8 x half> @llvm.riscv.vfnmacc.mask.nxv8f16.f16(
<vscale x 8 x half> %0, <vscale x 8 x half> %0,
half %1, half %1,
<vscale x 8 x half> %2, <vscale x 8 x half> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
iXLen %4, iXLen 0); iXLen 0, iXLen %4, iXLen 0);
ret <vscale x 8 x half> %a ret <vscale x 8 x half> %a
} }
declare <vscale x 16 x half> @llvm.riscv.vfnmacc.nxv16f16.f16( declare <vscale x 16 x half> @llvm.riscv.vfnmacc.nxv16f16.f16(
<vscale x 16 x half>, <vscale x 16 x half>,
half, half,
<vscale x 16 x half>, <vscale x 16 x half>,
iXLen, iXLen, iXLen, iXLen);
iXLen);
define <vscale x 16 x half> @intrinsic_vfnmacc_vf_nxv16f16_f16_nxv16f16(<vscale x 16 x half> %0, half %1, <vscale x 16 x half> %2, iXLen %3) nounwind { define <vscale x 16 x half> @intrinsic_vfnmacc_vf_nxv16f16_f16_nxv16f16(<vscale x 16 x half> %0, half %1, <vscale x 16 x half> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfnmacc_vf_nxv16f16_f16_nxv16f16: ; CHECK-LABEL: intrinsic_vfnmacc_vf_nxv16f16_f16_nxv16f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, ma ; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, ma
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfnmacc.vf v8, fa0, v12 ; CHECK-NEXT: vfnmacc.vf v8, fa0, v12
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x half> @llvm.riscv.vfnmacc.nxv16f16.f16( %a = call <vscale x 16 x half> @llvm.riscv.vfnmacc.nxv16f16.f16(
<vscale x 16 x half> %0, <vscale x 16 x half> %0,
half %1, half %1,
<vscale x 16 x half> %2, <vscale x 16 x half> %2,
iXLen %3, iXLen 0) iXLen 0, iXLen %3, iXLen 0)
ret <vscale x 16 x half> %a ret <vscale x 16 x half> %a
} }
declare <vscale x 16 x half> @llvm.riscv.vfnmacc.mask.nxv16f16.f16( declare <vscale x 16 x half> @llvm.riscv.vfnmacc.mask.nxv16f16.f16(
<vscale x 16 x half>, <vscale x 16 x half>,
half, half,
<vscale x 16 x half>, <vscale x 16 x half>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
iXLen, iXLen); iXLen, iXLen, iXLen);
define <vscale x 16 x half> @intrinsic_vfnmacc_mask_vf_nxv16f16_f16_nxv16f16(<vscale x 16 x half> %0, half %1, <vscale x 16 x half> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind { define <vscale x 16 x half> @intrinsic_vfnmacc_mask_vf_nxv16f16_f16_nxv16f16(<vscale x 16 x half> %0, half %1, <vscale x 16 x half> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfnmacc_mask_vf_nxv16f16_f16_nxv16f16: ; CHECK-LABEL: intrinsic_vfnmacc_mask_vf_nxv16f16_f16_nxv16f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfnmacc.vf v8, fa0, v12, v0.t ; CHECK-NEXT: vfnmacc.vf v8, fa0, v12, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x half> @llvm.riscv.vfnmacc.mask.nxv16f16.f16( %a = call <vscale x 16 x half> @llvm.riscv.vfnmacc.mask.nxv16f16.f16(
<vscale x 16 x half> %0, <vscale x 16 x half> %0,
half %1, half %1,
<vscale x 16 x half> %2, <vscale x 16 x half> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
iXLen %4, iXLen 0); iXLen 0, iXLen %4, iXLen 0);
ret <vscale x 16 x half> %a ret <vscale x 16 x half> %a
} }
declare <vscale x 1 x float> @llvm.riscv.vfnmacc.nxv1f32.f32( declare <vscale x 1 x float> @llvm.riscv.vfnmacc.nxv1f32.f32(
<vscale x 1 x float>, <vscale x 1 x float>,
float, float,
<vscale x 1 x float>, <vscale x 1 x float>,
iXLen, iXLen, iXLen, iXLen);
iXLen);
define <vscale x 1 x float> @intrinsic_vfnmacc_vf_nxv1f32_f32_nxv1f32(<vscale x 1 x float> %0, float %1, <vscale x 1 x float> %2, iXLen %3) nounwind { define <vscale x 1 x float> @intrinsic_vfnmacc_vf_nxv1f32_f32_nxv1f32(<vscale x 1 x float> %0, float %1, <vscale x 1 x float> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfnmacc_vf_nxv1f32_f32_nxv1f32: ; CHECK-LABEL: intrinsic_vfnmacc_vf_nxv1f32_f32_nxv1f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, ma ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, ma
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfnmacc.vf v8, fa0, v9 ; CHECK-NEXT: vfnmacc.vf v8, fa0, v9
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x float> @llvm.riscv.vfnmacc.nxv1f32.f32( %a = call <vscale x 1 x float> @llvm.riscv.vfnmacc.nxv1f32.f32(
<vscale x 1 x float> %0, <vscale x 1 x float> %0,
float %1, float %1,
<vscale x 1 x float> %2, <vscale x 1 x float> %2,
iXLen %3, iXLen 0) iXLen 0, iXLen %3, iXLen 0)
ret <vscale x 1 x float> %a ret <vscale x 1 x float> %a
} }
declare <vscale x 1 x float> @llvm.riscv.vfnmacc.mask.nxv1f32.f32( declare <vscale x 1 x float> @llvm.riscv.vfnmacc.mask.nxv1f32.f32(
<vscale x 1 x float>, <vscale x 1 x float>,
float, float,
<vscale x 1 x float>, <vscale x 1 x float>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
iXLen, iXLen); iXLen, iXLen, iXLen);
define <vscale x 1 x float> @intrinsic_vfnmacc_mask_vf_nxv1f32_f32_nxv1f32(<vscale x 1 x float> %0, float %1, <vscale x 1 x float> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind { define <vscale x 1 x float> @intrinsic_vfnmacc_mask_vf_nxv1f32_f32_nxv1f32(<vscale x 1 x float> %0, float %1, <vscale x 1 x float> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfnmacc_mask_vf_nxv1f32_f32_nxv1f32: ; CHECK-LABEL: intrinsic_vfnmacc_mask_vf_nxv1f32_f32_nxv1f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfnmacc.vf v8, fa0, v9, v0.t ; CHECK-NEXT: vfnmacc.vf v8, fa0, v9, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x float> @llvm.riscv.vfnmacc.mask.nxv1f32.f32( %a = call <vscale x 1 x float> @llvm.riscv.vfnmacc.mask.nxv1f32.f32(
<vscale x 1 x float> %0, <vscale x 1 x float> %0,
float %1, float %1,
<vscale x 1 x float> %2, <vscale x 1 x float> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
iXLen %4, iXLen 0); iXLen 0, iXLen %4, iXLen 0);
ret <vscale x 1 x float> %a ret <vscale x 1 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vfnmacc.nxv2f32.f32( declare <vscale x 2 x float> @llvm.riscv.vfnmacc.nxv2f32.f32(
<vscale x 2 x float>, <vscale x 2 x float>,
float, float,
<vscale x 2 x float>, <vscale x 2 x float>,
iXLen, iXLen, iXLen, iXLen);
iXLen);
define <vscale x 2 x float> @intrinsic_vfnmacc_vf_nxv2f32_f32_nxv2f32(<vscale x 2 x float> %0, float %1, <vscale x 2 x float> %2, iXLen %3) nounwind { define <vscale x 2 x float> @intrinsic_vfnmacc_vf_nxv2f32_f32_nxv2f32(<vscale x 2 x float> %0, float %1, <vscale x 2 x float> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfnmacc_vf_nxv2f32_f32_nxv2f32: ; CHECK-LABEL: intrinsic_vfnmacc_vf_nxv2f32_f32_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, ma ; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, ma
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfnmacc.vf v8, fa0, v9 ; CHECK-NEXT: vfnmacc.vf v8, fa0, v9
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfnmacc.nxv2f32.f32( %a = call <vscale x 2 x float> @llvm.riscv.vfnmacc.nxv2f32.f32(
<vscale x 2 x float> %0, <vscale x 2 x float> %0,
float %1, float %1,
<vscale x 2 x float> %2, <vscale x 2 x float> %2,
iXLen %3, iXLen 0) iXLen 0, iXLen %3, iXLen 0)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vfnmacc.mask.nxv2f32.f32( declare <vscale x 2 x float> @llvm.riscv.vfnmacc.mask.nxv2f32.f32(
<vscale x 2 x float>, <vscale x 2 x float>,
float, float,
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
iXLen, iXLen); iXLen, iXLen, iXLen);
define <vscale x 2 x float> @intrinsic_vfnmacc_mask_vf_nxv2f32_f32_nxv2f32(<vscale x 2 x float> %0, float %1, <vscale x 2 x float> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind { define <vscale x 2 x float> @intrinsic_vfnmacc_mask_vf_nxv2f32_f32_nxv2f32(<vscale x 2 x float> %0, float %1, <vscale x 2 x float> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfnmacc_mask_vf_nxv2f32_f32_nxv2f32: ; CHECK-LABEL: intrinsic_vfnmacc_mask_vf_nxv2f32_f32_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfnmacc.vf v8, fa0, v9, v0.t ; CHECK-NEXT: vfnmacc.vf v8, fa0, v9, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfnmacc.mask.nxv2f32.f32( %a = call <vscale x 2 x float> @llvm.riscv.vfnmacc.mask.nxv2f32.f32(
<vscale x 2 x float> %0, <vscale x 2 x float> %0,
float %1, float %1,
<vscale x 2 x float> %2, <vscale x 2 x float> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
iXLen %4, iXLen 0); iXLen 0, iXLen %4, iXLen 0);
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 4 x float> @llvm.riscv.vfnmacc.nxv4f32.f32( declare <vscale x 4 x float> @llvm.riscv.vfnmacc.nxv4f32.f32(
<vscale x 4 x float>, <vscale x 4 x float>,
float, float,
<vscale x 4 x float>, <vscale x 4 x float>,
iXLen, iXLen, iXLen, iXLen);
iXLen);
define <vscale x 4 x float> @intrinsic_vfnmacc_vf_nxv4f32_f32_nxv4f32(<vscale x 4 x float> %0, float %1, <vscale x 4 x float> %2, iXLen %3) nounwind { define <vscale x 4 x float> @intrinsic_vfnmacc_vf_nxv4f32_f32_nxv4f32(<vscale x 4 x float> %0, float %1, <vscale x 4 x float> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfnmacc_vf_nxv4f32_f32_nxv4f32: ; CHECK-LABEL: intrinsic_vfnmacc_vf_nxv4f32_f32_nxv4f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, ma ; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, ma
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfnmacc.vf v8, fa0, v10 ; CHECK-NEXT: vfnmacc.vf v8, fa0, v10
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x float> @llvm.riscv.vfnmacc.nxv4f32.f32( %a = call <vscale x 4 x float> @llvm.riscv.vfnmacc.nxv4f32.f32(
<vscale x 4 x float> %0, <vscale x 4 x float> %0,
float %1, float %1,
<vscale x 4 x float> %2, <vscale x 4 x float> %2,
iXLen %3, iXLen 0) iXLen 0, iXLen %3, iXLen 0)
ret <vscale x 4 x float> %a ret <vscale x 4 x float> %a
} }
declare <vscale x 4 x float> @llvm.riscv.vfnmacc.mask.nxv4f32.f32( declare <vscale x 4 x float> @llvm.riscv.vfnmacc.mask.nxv4f32.f32(
<vscale x 4 x float>, <vscale x 4 x float>,
float, float,
<vscale x 4 x float>, <vscale x 4 x float>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
iXLen, iXLen); iXLen, iXLen, iXLen);
define <vscale x 4 x float> @intrinsic_vfnmacc_mask_vf_nxv4f32_f32_nxv4f32(<vscale x 4 x float> %0, float %1, <vscale x 4 x float> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind { define <vscale x 4 x float> @intrinsic_vfnmacc_mask_vf_nxv4f32_f32_nxv4f32(<vscale x 4 x float> %0, float %1, <vscale x 4 x float> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfnmacc_mask_vf_nxv4f32_f32_nxv4f32: ; CHECK-LABEL: intrinsic_vfnmacc_mask_vf_nxv4f32_f32_nxv4f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfnmacc.vf v8, fa0, v10, v0.t ; CHECK-NEXT: vfnmacc.vf v8, fa0, v10, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x float> @llvm.riscv.vfnmacc.mask.nxv4f32.f32( %a = call <vscale x 4 x float> @llvm.riscv.vfnmacc.mask.nxv4f32.f32(
<vscale x 4 x float> %0, <vscale x 4 x float> %0,
float %1, float %1,
<vscale x 4 x float> %2, <vscale x 4 x float> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
iXLen %4, iXLen 0); iXLen 0, iXLen %4, iXLen 0);
ret <vscale x 4 x float> %a ret <vscale x 4 x float> %a
} }
declare <vscale x 8 x float> @llvm.riscv.vfnmacc.nxv8f32.f32( declare <vscale x 8 x float> @llvm.riscv.vfnmacc.nxv8f32.f32(
<vscale x 8 x float>, <vscale x 8 x float>,
float, float,
<vscale x 8 x float>, <vscale x 8 x float>,
iXLen, iXLen, iXLen, iXLen);
iXLen);
define <vscale x 8 x float> @intrinsic_vfnmacc_vf_nxv8f32_f32_nxv8f32(<vscale x 8 x float> %0, float %1, <vscale x 8 x float> %2, iXLen %3) nounwind { define <vscale x 8 x float> @intrinsic_vfnmacc_vf_nxv8f32_f32_nxv8f32(<vscale x 8 x float> %0, float %1, <vscale x 8 x float> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfnmacc_vf_nxv8f32_f32_nxv8f32: ; CHECK-LABEL: intrinsic_vfnmacc_vf_nxv8f32_f32_nxv8f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, ma ; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, ma
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfnmacc.vf v8, fa0, v12 ; CHECK-NEXT: vfnmacc.vf v8, fa0, v12
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x float> @llvm.riscv.vfnmacc.nxv8f32.f32( %a = call <vscale x 8 x float> @llvm.riscv.vfnmacc.nxv8f32.f32(
<vscale x 8 x float> %0, <vscale x 8 x float> %0,
float %1, float %1,
<vscale x 8 x float> %2, <vscale x 8 x float> %2,
iXLen %3, iXLen 0) iXLen 0, iXLen %3, iXLen 0)
ret <vscale x 8 x float> %a ret <vscale x 8 x float> %a
} }
declare <vscale x 8 x float> @llvm.riscv.vfnmacc.mask.nxv8f32.f32( declare <vscale x 8 x float> @llvm.riscv.vfnmacc.mask.nxv8f32.f32(
<vscale x 8 x float>, <vscale x 8 x float>,
float, float,
<vscale x 8 x float>, <vscale x 8 x float>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
iXLen, iXLen); iXLen, iXLen, iXLen);
define <vscale x 8 x float> @intrinsic_vfnmacc_mask_vf_nxv8f32_f32_nxv8f32(<vscale x 8 x float> %0, float %1, <vscale x 8 x float> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind { define <vscale x 8 x float> @intrinsic_vfnmacc_mask_vf_nxv8f32_f32_nxv8f32(<vscale x 8 x float> %0, float %1, <vscale x 8 x float> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfnmacc_mask_vf_nxv8f32_f32_nxv8f32: ; CHECK-LABEL: intrinsic_vfnmacc_mask_vf_nxv8f32_f32_nxv8f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfnmacc.vf v8, fa0, v12, v0.t ; CHECK-NEXT: vfnmacc.vf v8, fa0, v12, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x float> @llvm.riscv.vfnmacc.mask.nxv8f32.f32( %a = call <vscale x 8 x float> @llvm.riscv.vfnmacc.mask.nxv8f32.f32(
<vscale x 8 x float> %0, <vscale x 8 x float> %0,
float %1, float %1,
<vscale x 8 x float> %2, <vscale x 8 x float> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
iXLen %4, iXLen 0); iXLen 0, iXLen %4, iXLen 0);
ret <vscale x 8 x float> %a ret <vscale x 8 x float> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vfnmacc.nxv1f64.f64( declare <vscale x 1 x double> @llvm.riscv.vfnmacc.nxv1f64.f64(
<vscale x 1 x double>, <vscale x 1 x double>,
double, double,
<vscale x 1 x double>, <vscale x 1 x double>,
iXLen, iXLen, iXLen, iXLen);
iXLen);
define <vscale x 1 x double> @intrinsic_vfnmacc_vf_nxv1f64_f64_nxv1f64(<vscale x 1 x double> %0, double %1, <vscale x 1 x double> %2, iXLen %3) nounwind { define <vscale x 1 x double> @intrinsic_vfnmacc_vf_nxv1f64_f64_nxv1f64(<vscale x 1 x double> %0, double %1, <vscale x 1 x double> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfnmacc_vf_nxv1f64_f64_nxv1f64: ; CHECK-LABEL: intrinsic_vfnmacc_vf_nxv1f64_f64_nxv1f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, ma ; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, ma
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfnmacc.vf v8, fa0, v9 ; CHECK-NEXT: vfnmacc.vf v8, fa0, v9
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfnmacc.nxv1f64.f64( %a = call <vscale x 1 x double> @llvm.riscv.vfnmacc.nxv1f64.f64(
<vscale x 1 x double> %0, <vscale x 1 x double> %0,
double %1, double %1,
<vscale x 1 x double> %2, <vscale x 1 x double> %2,
iXLen %3, iXLen 0) iXLen 0, iXLen %3, iXLen 0)
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vfnmacc.mask.nxv1f64.f64( declare <vscale x 1 x double> @llvm.riscv.vfnmacc.mask.nxv1f64.f64(
<vscale x 1 x double>, <vscale x 1 x double>,
double, double,
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
iXLen, iXLen); iXLen, iXLen, iXLen);
define <vscale x 1 x double> @intrinsic_vfnmacc_mask_vf_nxv1f64_f64_nxv1f64(<vscale x 1 x double> %0, double %1, <vscale x 1 x double> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind { define <vscale x 1 x double> @intrinsic_vfnmacc_mask_vf_nxv1f64_f64_nxv1f64(<vscale x 1 x double> %0, double %1, <vscale x 1 x double> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfnmacc_mask_vf_nxv1f64_f64_nxv1f64: ; CHECK-LABEL: intrinsic_vfnmacc_mask_vf_nxv1f64_f64_nxv1f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, mu
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfnmacc.vf v8, fa0, v9, v0.t ; CHECK-NEXT: vfnmacc.vf v8, fa0, v9, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfnmacc.mask.nxv1f64.f64( %a = call <vscale x 1 x double> @llvm.riscv.vfnmacc.mask.nxv1f64.f64(
<vscale x 1 x double> %0, <vscale x 1 x double> %0,
double %1, double %1,
<vscale x 1 x double> %2, <vscale x 1 x double> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
iXLen %4, iXLen 0); iXLen 0, iXLen %4, iXLen 0);
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 2 x double> @llvm.riscv.vfnmacc.nxv2f64.f64( declare <vscale x 2 x double> @llvm.riscv.vfnmacc.nxv2f64.f64(
<vscale x 2 x double>, <vscale x 2 x double>,
double, double,
<vscale x 2 x double>, <vscale x 2 x double>,
iXLen, iXLen, iXLen, iXLen);
iXLen);
define <vscale x 2 x double> @intrinsic_vfnmacc_vf_nxv2f64_f64_nxv2f64(<vscale x 2 x double> %0, double %1, <vscale x 2 x double> %2, iXLen %3) nounwind { define <vscale x 2 x double> @intrinsic_vfnmacc_vf_nxv2f64_f64_nxv2f64(<vscale x 2 x double> %0, double %1, <vscale x 2 x double> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfnmacc_vf_nxv2f64_f64_nxv2f64: ; CHECK-LABEL: intrinsic_vfnmacc_vf_nxv2f64_f64_nxv2f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, ma ; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, ma
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfnmacc.vf v8, fa0, v10 ; CHECK-NEXT: vfnmacc.vf v8, fa0, v10
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x double> @llvm.riscv.vfnmacc.nxv2f64.f64( %a = call <vscale x 2 x double> @llvm.riscv.vfnmacc.nxv2f64.f64(
<vscale x 2 x double> %0, <vscale x 2 x double> %0,
double %1, double %1,
<vscale x 2 x double> %2, <vscale x 2 x double> %2,
iXLen %3, iXLen 0) iXLen 0, iXLen %3, iXLen 0)
ret <vscale x 2 x double> %a ret <vscale x 2 x double> %a
} }
declare <vscale x 2 x double> @llvm.riscv.vfnmacc.mask.nxv2f64.f64( declare <vscale x 2 x double> @llvm.riscv.vfnmacc.mask.nxv2f64.f64(
<vscale x 2 x double>, <vscale x 2 x double>,
double, double,
<vscale x 2 x double>, <vscale x 2 x double>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
iXLen, iXLen); iXLen, iXLen, iXLen);
define <vscale x 2 x double> @intrinsic_vfnmacc_mask_vf_nxv2f64_f64_nxv2f64(<vscale x 2 x double> %0, double %1, <vscale x 2 x double> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind { define <vscale x 2 x double> @intrinsic_vfnmacc_mask_vf_nxv2f64_f64_nxv2f64(<vscale x 2 x double> %0, double %1, <vscale x 2 x double> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfnmacc_mask_vf_nxv2f64_f64_nxv2f64: ; CHECK-LABEL: intrinsic_vfnmacc_mask_vf_nxv2f64_f64_nxv2f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, mu
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfnmacc.vf v8, fa0, v10, v0.t ; CHECK-NEXT: vfnmacc.vf v8, fa0, v10, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x double> @llvm.riscv.vfnmacc.mask.nxv2f64.f64( %a = call <vscale x 2 x double> @llvm.riscv.vfnmacc.mask.nxv2f64.f64(
<vscale x 2 x double> %0, <vscale x 2 x double> %0,
double %1, double %1,
<vscale x 2 x double> %2, <vscale x 2 x double> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
iXLen %4, iXLen 0); iXLen 0, iXLen %4, iXLen 0);
ret <vscale x 2 x double> %a ret <vscale x 2 x double> %a
} }
declare <vscale x 4 x double> @llvm.riscv.vfnmacc.nxv4f64.f64( declare <vscale x 4 x double> @llvm.riscv.vfnmacc.nxv4f64.f64(
<vscale x 4 x double>, <vscale x 4 x double>,
double, double,
<vscale x 4 x double>, <vscale x 4 x double>,
iXLen, iXLen, iXLen, iXLen);
iXLen);
define <vscale x 4 x double> @intrinsic_vfnmacc_vf_nxv4f64_f64_nxv4f64(<vscale x 4 x double> %0, double %1, <vscale x 4 x double> %2, iXLen %3) nounwind { define <vscale x 4 x double> @intrinsic_vfnmacc_vf_nxv4f64_f64_nxv4f64(<vscale x 4 x double> %0, double %1, <vscale x 4 x double> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfnmacc_vf_nxv4f64_f64_nxv4f64: ; CHECK-LABEL: intrinsic_vfnmacc_vf_nxv4f64_f64_nxv4f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, ma ; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, ma
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfnmacc.vf v8, fa0, v12 ; CHECK-NEXT: vfnmacc.vf v8, fa0, v12
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x double> @llvm.riscv.vfnmacc.nxv4f64.f64( %a = call <vscale x 4 x double> @llvm.riscv.vfnmacc.nxv4f64.f64(
<vscale x 4 x double> %0, <vscale x 4 x double> %0,
double %1, double %1,
<vscale x 4 x double> %2, <vscale x 4 x double> %2,
iXLen %3, iXLen 0) iXLen 0, iXLen %3, iXLen 0)
ret <vscale x 4 x double> %a ret <vscale x 4 x double> %a
} }
declare <vscale x 4 x double> @llvm.riscv.vfnmacc.mask.nxv4f64.f64( declare <vscale x 4 x double> @llvm.riscv.vfnmacc.mask.nxv4f64.f64(
<vscale x 4 x double>, <vscale x 4 x double>,
double, double,
<vscale x 4 x double>, <vscale x 4 x double>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
iXLen, iXLen); iXLen, iXLen, iXLen);
define <vscale x 4 x double> @intrinsic_vfnmacc_mask_vf_nxv4f64_f64_nxv4f64(<vscale x 4 x double> %0, double %1, <vscale x 4 x double> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind { define <vscale x 4 x double> @intrinsic_vfnmacc_mask_vf_nxv4f64_f64_nxv4f64(<vscale x 4 x double> %0, double %1, <vscale x 4 x double> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfnmacc_mask_vf_nxv4f64_f64_nxv4f64: ; CHECK-LABEL: intrinsic_vfnmacc_mask_vf_nxv4f64_f64_nxv4f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, mu
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfnmacc.vf v8, fa0, v12, v0.t ; CHECK-NEXT: vfnmacc.vf v8, fa0, v12, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x double> @llvm.riscv.vfnmacc.mask.nxv4f64.f64( %a = call <vscale x 4 x double> @llvm.riscv.vfnmacc.mask.nxv4f64.f64(
<vscale x 4 x double> %0, <vscale x 4 x double> %0,
double %1, double %1,
<vscale x 4 x double> %2, <vscale x 4 x double> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
iXLen %4, iXLen 0); iXLen 0, iXLen %4, iXLen 0);
ret <vscale x 4 x double> %a ret <vscale x 4 x double> %a
} }

llvm/test/CodeGen/RISCV/rvv/vfnmadd.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zfh,+experimental-zvfh \ ; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zfh,+experimental-zvfh \
; RUN: -verify-machineinstrs -target-abi=ilp32d | FileCheck %s ; RUN: -verify-machineinstrs -target-abi=ilp32d | FileCheck %s
; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zfh,+experimental-zvfh \ ; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zfh,+experimental-zvfh \
; RUN: -verify-machineinstrs -target-abi=lp64d | FileCheck %s ; RUN: -verify-machineinstrs -target-abi=lp64d | FileCheck %s
declare <vscale x 1 x half> @llvm.riscv.vfnmadd.nxv1f16.nxv1f16( declare <vscale x 1 x half> @llvm.riscv.vfnmadd.nxv1f16.nxv1f16(
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x half>, <vscale x 1 x half>,
iXLen, iXLen, iXLen, iXLen);
iXLen);
define <vscale x 1 x half> @intrinsic_vfnmadd_vv_nxv1f16_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, iXLen %3) nounwind { define <vscale x 1 x half> @intrinsic_vfnmadd_vv_nxv1f16_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfnmadd_vv_nxv1f16_nxv1f16_nxv1f16: ; CHECK-LABEL: intrinsic_vfnmadd_vv_nxv1f16_nxv1f16_nxv1f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, ma ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, ma
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfnmadd.vv v8, v9, v10 ; CHECK-NEXT: vfnmadd.vv v8, v9, v10
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x half> @llvm.riscv.vfnmadd.nxv1f16.nxv1f16( %a = call <vscale x 1 x half> @llvm.riscv.vfnmadd.nxv1f16.nxv1f16(
<vscale x 1 x half> %0, <vscale x 1 x half> %0,
<vscale x 1 x half> %1, <vscale x 1 x half> %1,
<vscale x 1 x half> %2, <vscale x 1 x half> %2,
iXLen %3, iXLen 0) iXLen 0, iXLen %3, iXLen 0)
ret <vscale x 1 x half> %a ret <vscale x 1 x half> %a
} }
declare <vscale x 1 x half> @llvm.riscv.vfnmadd.mask.nxv1f16.nxv1f16( declare <vscale x 1 x half> @llvm.riscv.vfnmadd.mask.nxv1f16.nxv1f16(
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
iXLen, iXLen); iXLen, iXLen, iXLen);
define <vscale x 1 x half> @intrinsic_vfnmadd_mask_vv_nxv1f16_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind { define <vscale x 1 x half> @intrinsic_vfnmadd_mask_vv_nxv1f16_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfnmadd_mask_vv_nxv1f16_nxv1f16_nxv1f16: ; CHECK-LABEL: intrinsic_vfnmadd_mask_vv_nxv1f16_nxv1f16_nxv1f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfnmadd.vv v8, v9, v10, v0.t ; CHECK-NEXT: vfnmadd.vv v8, v9, v10, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x half> @llvm.riscv.vfnmadd.mask.nxv1f16.nxv1f16( %a = call <vscale x 1 x half> @llvm.riscv.vfnmadd.mask.nxv1f16.nxv1f16(
<vscale x 1 x half> %0, <vscale x 1 x half> %0,
<vscale x 1 x half> %1, <vscale x 1 x half> %1,
<vscale x 1 x half> %2, <vscale x 1 x half> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
iXLen %4, iXLen 0); iXLen 0, iXLen %4, iXLen 0);
ret <vscale x 1 x half> %a ret <vscale x 1 x half> %a
} }
declare <vscale x 2 x half> @llvm.riscv.vfnmadd.nxv2f16.nxv2f16( declare <vscale x 2 x half> @llvm.riscv.vfnmadd.nxv2f16.nxv2f16(
<vscale x 2 x half>, <vscale x 2 x half>,
<vscale x 2 x half>, <vscale x 2 x half>,
<vscale x 2 x half>, <vscale x 2 x half>,
iXLen, iXLen, iXLen, iXLen);
iXLen);
define <vscale x 2 x half> @intrinsic_vfnmadd_vv_nxv2f16_nxv2f16_nxv2f16(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, iXLen %3) nounwind { define <vscale x 2 x half> @intrinsic_vfnmadd_vv_nxv2f16_nxv2f16_nxv2f16(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfnmadd_vv_nxv2f16_nxv2f16_nxv2f16: ; CHECK-LABEL: intrinsic_vfnmadd_vv_nxv2f16_nxv2f16_nxv2f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, ma ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, ma
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfnmadd.vv v8, v9, v10 ; CHECK-NEXT: vfnmadd.vv v8, v9, v10
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x half> @llvm.riscv.vfnmadd.nxv2f16.nxv2f16( %a = call <vscale x 2 x half> @llvm.riscv.vfnmadd.nxv2f16.nxv2f16(
<vscale x 2 x half> %0, <vscale x 2 x half> %0,
<vscale x 2 x half> %1, <vscale x 2 x half> %1,
<vscale x 2 x half> %2, <vscale x 2 x half> %2,
iXLen %3, iXLen 0) iXLen 0, iXLen %3, iXLen 0)
ret <vscale x 2 x half> %a ret <vscale x 2 x half> %a
} }
declare <vscale x 2 x half> @llvm.riscv.vfnmadd.mask.nxv2f16.nxv2f16( declare <vscale x 2 x half> @llvm.riscv.vfnmadd.mask.nxv2f16.nxv2f16(
<vscale x 2 x half>, <vscale x 2 x half>,
<vscale x 2 x half>, <vscale x 2 x half>,
<vscale x 2 x half>, <vscale x 2 x half>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
iXLen, iXLen); iXLen, iXLen, iXLen);
define <vscale x 2 x half> @intrinsic_vfnmadd_mask_vv_nxv2f16_nxv2f16_nxv2f16(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind { define <vscale x 2 x half> @intrinsic_vfnmadd_mask_vv_nxv2f16_nxv2f16_nxv2f16(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfnmadd_mask_vv_nxv2f16_nxv2f16_nxv2f16: ; CHECK-LABEL: intrinsic_vfnmadd_mask_vv_nxv2f16_nxv2f16_nxv2f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfnmadd.vv v8, v9, v10, v0.t ; CHECK-NEXT: vfnmadd.vv v8, v9, v10, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x half> @llvm.riscv.vfnmadd.mask.nxv2f16.nxv2f16( %a = call <vscale x 2 x half> @llvm.riscv.vfnmadd.mask.nxv2f16.nxv2f16(
<vscale x 2 x half> %0, <vscale x 2 x half> %0,
<vscale x 2 x half> %1, <vscale x 2 x half> %1,
<vscale x 2 x half> %2, <vscale x 2 x half> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
iXLen %4, iXLen 0); iXLen 0, iXLen %4, iXLen 0);
ret <vscale x 2 x half> %a ret <vscale x 2 x half> %a
} }
declare <vscale x 4 x half> @llvm.riscv.vfnmadd.nxv4f16.nxv4f16( declare <vscale x 4 x half> @llvm.riscv.vfnmadd.nxv4f16.nxv4f16(
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 4 x half>, <vscale x 4 x half>,
iXLen, iXLen, iXLen, iXLen);
iXLen);
define <vscale x 4 x half> @intrinsic_vfnmadd_vv_nxv4f16_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, iXLen %3) nounwind { define <vscale x 4 x half> @intrinsic_vfnmadd_vv_nxv4f16_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfnmadd_vv_nxv4f16_nxv4f16_nxv4f16: ; CHECK-LABEL: intrinsic_vfnmadd_vv_nxv4f16_nxv4f16_nxv4f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, ma ; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, ma
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfnmadd.vv v8, v9, v10 ; CHECK-NEXT: vfnmadd.vv v8, v9, v10
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x half> @llvm.riscv.vfnmadd.nxv4f16.nxv4f16( %a = call <vscale x 4 x half> @llvm.riscv.vfnmadd.nxv4f16.nxv4f16(
<vscale x 4 x half> %0, <vscale x 4 x half> %0,
<vscale x 4 x half> %1, <vscale x 4 x half> %1,
<vscale x 4 x half> %2, <vscale x 4 x half> %2,
iXLen %3, iXLen 0) iXLen 0, iXLen %3, iXLen 0)
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 4 x half> @llvm.riscv.vfnmadd.mask.nxv4f16.nxv4f16( declare <vscale x 4 x half> @llvm.riscv.vfnmadd.mask.nxv4f16.nxv4f16(
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
iXLen, iXLen); iXLen, iXLen, iXLen);
define <vscale x 4 x half> @intrinsic_vfnmadd_mask_vv_nxv4f16_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind { define <vscale x 4 x half> @intrinsic_vfnmadd_mask_vv_nxv4f16_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfnmadd_mask_vv_nxv4f16_nxv4f16_nxv4f16: ; CHECK-LABEL: intrinsic_vfnmadd_mask_vv_nxv4f16_nxv4f16_nxv4f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfnmadd.vv v8, v9, v10, v0.t ; CHECK-NEXT: vfnmadd.vv v8, v9, v10, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x half> @llvm.riscv.vfnmadd.mask.nxv4f16.nxv4f16( %a = call <vscale x 4 x half> @llvm.riscv.vfnmadd.mask.nxv4f16.nxv4f16(
<vscale x 4 x half> %0, <vscale x 4 x half> %0,
<vscale x 4 x half> %1, <vscale x 4 x half> %1,
<vscale x 4 x half> %2, <vscale x 4 x half> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
iXLen %4, iXLen 0); iXLen 0, iXLen %4, iXLen 0);
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 8 x half> @llvm.riscv.vfnmadd.nxv8f16.nxv8f16( declare <vscale x 8 x half> @llvm.riscv.vfnmadd.nxv8f16.nxv8f16(
<vscale x 8 x half>, <vscale x 8 x half>,
<vscale x 8 x half>, <vscale x 8 x half>,
<vscale x 8 x half>, <vscale x 8 x half>,
iXLen, iXLen, iXLen, iXLen);
iXLen);
define <vscale x 8 x half> @intrinsic_vfnmadd_vv_nxv8f16_nxv8f16_nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, iXLen %3) nounwind { define <vscale x 8 x half> @intrinsic_vfnmadd_vv_nxv8f16_nxv8f16_nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfnmadd_vv_nxv8f16_nxv8f16_nxv8f16: ; CHECK-LABEL: intrinsic_vfnmadd_vv_nxv8f16_nxv8f16_nxv8f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, ma ; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, ma
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfnmadd.vv v8, v10, v12 ; CHECK-NEXT: vfnmadd.vv v8, v10, v12
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x half> @llvm.riscv.vfnmadd.nxv8f16.nxv8f16( %a = call <vscale x 8 x half> @llvm.riscv.vfnmadd.nxv8f16.nxv8f16(
<vscale x 8 x half> %0, <vscale x 8 x half> %0,
<vscale x 8 x half> %1, <vscale x 8 x half> %1,
<vscale x 8 x half> %2, <vscale x 8 x half> %2,
iXLen %3, iXLen 0) iXLen 0, iXLen %3, iXLen 0)
ret <vscale x 8 x half> %a ret <vscale x 8 x half> %a
} }
declare <vscale x 8 x half> @llvm.riscv.vfnmadd.mask.nxv8f16.nxv8f16( declare <vscale x 8 x half> @llvm.riscv.vfnmadd.mask.nxv8f16.nxv8f16(
<vscale x 8 x half>, <vscale x 8 x half>,
<vscale x 8 x half>, <vscale x 8 x half>,
<vscale x 8 x half>, <vscale x 8 x half>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
iXLen, iXLen); iXLen, iXLen, iXLen);
define <vscale x 8 x half> @intrinsic_vfnmadd_mask_vv_nxv8f16_nxv8f16_nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind { define <vscale x 8 x half> @intrinsic_vfnmadd_mask_vv_nxv8f16_nxv8f16_nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfnmadd_mask_vv_nxv8f16_nxv8f16_nxv8f16: ; CHECK-LABEL: intrinsic_vfnmadd_mask_vv_nxv8f16_nxv8f16_nxv8f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, mu
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfnmadd.vv v8, v10, v12, v0.t ; CHECK-NEXT: vfnmadd.vv v8, v10, v12, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x half> @llvm.riscv.vfnmadd.mask.nxv8f16.nxv8f16( %a = call <vscale x 8 x half> @llvm.riscv.vfnmadd.mask.nxv8f16.nxv8f16(
<vscale x 8 x half> %0, <vscale x 8 x half> %0,
<vscale x 8 x half> %1, <vscale x 8 x half> %1,
<vscale x 8 x half> %2, <vscale x 8 x half> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
iXLen %4, iXLen 0); iXLen 0, iXLen %4, iXLen 0);
ret <vscale x 8 x half> %a ret <vscale x 8 x half> %a
} }
declare <vscale x 16 x half> @llvm.riscv.vfnmadd.nxv16f16.nxv16f16( declare <vscale x 16 x half> @llvm.riscv.vfnmadd.nxv16f16.nxv16f16(
<vscale x 16 x half>, <vscale x 16 x half>,
<vscale x 16 x half>, <vscale x 16 x half>,
<vscale x 16 x half>, <vscale x 16 x half>,
iXLen, iXLen, iXLen, iXLen);
iXLen);
define <vscale x 16 x half> @intrinsic_vfnmadd_vv_nxv16f16_nxv16f16_nxv16f16(<vscale x 16 x half> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %2, iXLen %3) nounwind { define <vscale x 16 x half> @intrinsic_vfnmadd_vv_nxv16f16_nxv16f16_nxv16f16(<vscale x 16 x half> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfnmadd_vv_nxv16f16_nxv16f16_nxv16f16: ; CHECK-LABEL: intrinsic_vfnmadd_vv_nxv16f16_nxv16f16_nxv16f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, ma ; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, ma
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfnmadd.vv v8, v12, v16 ; CHECK-NEXT: vfnmadd.vv v8, v12, v16
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x half> @llvm.riscv.vfnmadd.nxv16f16.nxv16f16( %a = call <vscale x 16 x half> @llvm.riscv.vfnmadd.nxv16f16.nxv16f16(
<vscale x 16 x half> %0, <vscale x 16 x half> %0,
<vscale x 16 x half> %1, <vscale x 16 x half> %1,
<vscale x 16 x half> %2, <vscale x 16 x half> %2,
iXLen %3, iXLen 0) iXLen 0, iXLen %3, iXLen 0)
ret <vscale x 16 x half> %a ret <vscale x 16 x half> %a
} }
declare <vscale x 16 x half> @llvm.riscv.vfnmadd.mask.nxv16f16.nxv16f16( declare <vscale x 16 x half> @llvm.riscv.vfnmadd.mask.nxv16f16.nxv16f16(
<vscale x 16 x half>, <vscale x 16 x half>,
<vscale x 16 x half>, <vscale x 16 x half>,
<vscale x 16 x half>, <vscale x 16 x half>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
iXLen, iXLen); iXLen, iXLen, iXLen);
define <vscale x 16 x half> @intrinsic_vfnmadd_mask_vv_nxv16f16_nxv16f16_nxv16f16(<vscale x 16 x half> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind { define <vscale x 16 x half> @intrinsic_vfnmadd_mask_vv_nxv16f16_nxv16f16_nxv16f16(<vscale x 16 x half> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfnmadd_mask_vv_nxv16f16_nxv16f16_nxv16f16: ; CHECK-LABEL: intrinsic_vfnmadd_mask_vv_nxv16f16_nxv16f16_nxv16f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfnmadd.vv v8, v12, v16, v0.t ; CHECK-NEXT: vfnmadd.vv v8, v12, v16, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x half> @llvm.riscv.vfnmadd.mask.nxv16f16.nxv16f16( %a = call <vscale x 16 x half> @llvm.riscv.vfnmadd.mask.nxv16f16.nxv16f16(
<vscale x 16 x half> %0, <vscale x 16 x half> %0,
<vscale x 16 x half> %1, <vscale x 16 x half> %1,
<vscale x 16 x half> %2, <vscale x 16 x half> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
iXLen %4, iXLen 0); iXLen 0, iXLen %4, iXLen 0);
ret <vscale x 16 x half> %a ret <vscale x 16 x half> %a
} }
declare <vscale x 1 x float> @llvm.riscv.vfnmadd.nxv1f32.nxv1f32( declare <vscale x 1 x float> @llvm.riscv.vfnmadd.nxv1f32.nxv1f32(
<vscale x 1 x float>, <vscale x 1 x float>,
<vscale x 1 x float>, <vscale x 1 x float>,
<vscale x 1 x float>, <vscale x 1 x float>,
iXLen, iXLen, iXLen, iXLen);
iXLen);
define <vscale x 1 x float> @intrinsic_vfnmadd_vv_nxv1f32_nxv1f32_nxv1f32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, iXLen %3) nounwind { define <vscale x 1 x float> @intrinsic_vfnmadd_vv_nxv1f32_nxv1f32_nxv1f32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfnmadd_vv_nxv1f32_nxv1f32_nxv1f32: ; CHECK-LABEL: intrinsic_vfnmadd_vv_nxv1f32_nxv1f32_nxv1f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, ma ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, ma
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfnmadd.vv v8, v9, v10 ; CHECK-NEXT: vfnmadd.vv v8, v9, v10
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x float> @llvm.riscv.vfnmadd.nxv1f32.nxv1f32( %a = call <vscale x 1 x float> @llvm.riscv.vfnmadd.nxv1f32.nxv1f32(
<vscale x 1 x float> %0, <vscale x 1 x float> %0,
<vscale x 1 x float> %1, <vscale x 1 x float> %1,
<vscale x 1 x float> %2, <vscale x 1 x float> %2,
iXLen %3, iXLen 0) iXLen 0, iXLen %3, iXLen 0)
ret <vscale x 1 x float> %a ret <vscale x 1 x float> %a
} }
declare <vscale x 1 x float> @llvm.riscv.vfnmadd.mask.nxv1f32.nxv1f32( declare <vscale x 1 x float> @llvm.riscv.vfnmadd.mask.nxv1f32.nxv1f32(
<vscale x 1 x float>, <vscale x 1 x float>,
<vscale x 1 x float>, <vscale x 1 x float>,
<vscale x 1 x float>, <vscale x 1 x float>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
iXLen, iXLen); iXLen, iXLen, iXLen);
define <vscale x 1 x float> @intrinsic_vfnmadd_mask_vv_nxv1f32_nxv1f32_nxv1f32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind { define <vscale x 1 x float> @intrinsic_vfnmadd_mask_vv_nxv1f32_nxv1f32_nxv1f32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfnmadd_mask_vv_nxv1f32_nxv1f32_nxv1f32: ; CHECK-LABEL: intrinsic_vfnmadd_mask_vv_nxv1f32_nxv1f32_nxv1f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfnmadd.vv v8, v9, v10, v0.t ; CHECK-NEXT: vfnmadd.vv v8, v9, v10, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x float> @llvm.riscv.vfnmadd.mask.nxv1f32.nxv1f32( %a = call <vscale x 1 x float> @llvm.riscv.vfnmadd.mask.nxv1f32.nxv1f32(
<vscale x 1 x float> %0, <vscale x 1 x float> %0,
<vscale x 1 x float> %1, <vscale x 1 x float> %1,
<vscale x 1 x float> %2, <vscale x 1 x float> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
iXLen %4, iXLen 0); iXLen 0, iXLen %4, iXLen 0);
ret <vscale x 1 x float> %a ret <vscale x 1 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vfnmadd.nxv2f32.nxv2f32( declare <vscale x 2 x float> @llvm.riscv.vfnmadd.nxv2f32.nxv2f32(
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 2 x float>, <vscale x 2 x float>,
iXLen, iXLen, iXLen, iXLen);
iXLen);
define <vscale x 2 x float> @intrinsic_vfnmadd_vv_nxv2f32_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, iXLen %3) nounwind { define <vscale x 2 x float> @intrinsic_vfnmadd_vv_nxv2f32_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfnmadd_vv_nxv2f32_nxv2f32_nxv2f32: ; CHECK-LABEL: intrinsic_vfnmadd_vv_nxv2f32_nxv2f32_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, ma ; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, ma
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfnmadd.vv v8, v9, v10 ; CHECK-NEXT: vfnmadd.vv v8, v9, v10
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfnmadd.nxv2f32.nxv2f32( %a = call <vscale x 2 x float> @llvm.riscv.vfnmadd.nxv2f32.nxv2f32(
<vscale x 2 x float> %0, <vscale x 2 x float> %0,
<vscale x 2 x float> %1, <vscale x 2 x float> %1,
<vscale x 2 x float> %2, <vscale x 2 x float> %2,
iXLen %3, iXLen 0) iXLen 0, iXLen %3, iXLen 0)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vfnmadd.mask.nxv2f32.nxv2f32( declare <vscale x 2 x float> @llvm.riscv.vfnmadd.mask.nxv2f32.nxv2f32(
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
iXLen, iXLen); iXLen, iXLen, iXLen);
define <vscale x 2 x float> @intrinsic_vfnmadd_mask_vv_nxv2f32_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind { define <vscale x 2 x float> @intrinsic_vfnmadd_mask_vv_nxv2f32_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfnmadd_mask_vv_nxv2f32_nxv2f32_nxv2f32: ; CHECK-LABEL: intrinsic_vfnmadd_mask_vv_nxv2f32_nxv2f32_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfnmadd.vv v8, v9, v10, v0.t ; CHECK-NEXT: vfnmadd.vv v8, v9, v10, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfnmadd.mask.nxv2f32.nxv2f32( %a = call <vscale x 2 x float> @llvm.riscv.vfnmadd.mask.nxv2f32.nxv2f32(
<vscale x 2 x float> %0, <vscale x 2 x float> %0,
<vscale x 2 x float> %1, <vscale x 2 x float> %1,
<vscale x 2 x float> %2, <vscale x 2 x float> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
iXLen %4, iXLen 0); iXLen 0, iXLen %4, iXLen 0);
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 4 x float> @llvm.riscv.vfnmadd.nxv4f32.nxv4f32( declare <vscale x 4 x float> @llvm.riscv.vfnmadd.nxv4f32.nxv4f32(
<vscale x 4 x float>, <vscale x 4 x float>,
<vscale x 4 x float>, <vscale x 4 x float>,
<vscale x 4 x float>, <vscale x 4 x float>,
iXLen, iXLen, iXLen, iXLen);
iXLen);
define <vscale x 4 x float> @intrinsic_vfnmadd_vv_nxv4f32_nxv4f32_nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, <vscale x 4 x float> %2, iXLen %3) nounwind { define <vscale x 4 x float> @intrinsic_vfnmadd_vv_nxv4f32_nxv4f32_nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, <vscale x 4 x float> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfnmadd_vv_nxv4f32_nxv4f32_nxv4f32: ; CHECK-LABEL: intrinsic_vfnmadd_vv_nxv4f32_nxv4f32_nxv4f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, ma ; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, ma
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfnmadd.vv v8, v10, v12 ; CHECK-NEXT: vfnmadd.vv v8, v10, v12
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x float> @llvm.riscv.vfnmadd.nxv4f32.nxv4f32( %a = call <vscale x 4 x float> @llvm.riscv.vfnmadd.nxv4f32.nxv4f32(
<vscale x 4 x float> %0, <vscale x 4 x float> %0,
<vscale x 4 x float> %1, <vscale x 4 x float> %1,
<vscale x 4 x float> %2, <vscale x 4 x float> %2,
iXLen %3, iXLen 0) iXLen 0, iXLen %3, iXLen 0)
ret <vscale x 4 x float> %a ret <vscale x 4 x float> %a
} }
declare <vscale x 4 x float> @llvm.riscv.vfnmadd.mask.nxv4f32.nxv4f32( declare <vscale x 4 x float> @llvm.riscv.vfnmadd.mask.nxv4f32.nxv4f32(
<vscale x 4 x float>, <vscale x 4 x float>,
<vscale x 4 x float>, <vscale x 4 x float>,
<vscale x 4 x float>, <vscale x 4 x float>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
iXLen, iXLen); iXLen, iXLen, iXLen);
define <vscale x 4 x float> @intrinsic_vfnmadd_mask_vv_nxv4f32_nxv4f32_nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, <vscale x 4 x float> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind { define <vscale x 4 x float> @intrinsic_vfnmadd_mask_vv_nxv4f32_nxv4f32_nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, <vscale x 4 x float> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfnmadd_mask_vv_nxv4f32_nxv4f32_nxv4f32: ; CHECK-LABEL: intrinsic_vfnmadd_mask_vv_nxv4f32_nxv4f32_nxv4f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfnmadd.vv v8, v10, v12, v0.t ; CHECK-NEXT: vfnmadd.vv v8, v10, v12, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x float> @llvm.riscv.vfnmadd.mask.nxv4f32.nxv4f32( %a = call <vscale x 4 x float> @llvm.riscv.vfnmadd.mask.nxv4f32.nxv4f32(
<vscale x 4 x float> %0, <vscale x 4 x float> %0,
<vscale x 4 x float> %1, <vscale x 4 x float> %1,
<vscale x 4 x float> %2, <vscale x 4 x float> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
iXLen %4, iXLen 0); iXLen 0, iXLen %4, iXLen 0);
ret <vscale x 4 x float> %a ret <vscale x 4 x float> %a
} }
declare <vscale x 8 x float> @llvm.riscv.vfnmadd.nxv8f32.nxv8f32( declare <vscale x 8 x float> @llvm.riscv.vfnmadd.nxv8f32.nxv8f32(
<vscale x 8 x float>, <vscale x 8 x float>,
<vscale x 8 x float>, <vscale x 8 x float>,
<vscale x 8 x float>, <vscale x 8 x float>,
iXLen, iXLen, iXLen, iXLen);
iXLen);
define <vscale x 8 x float> @intrinsic_vfnmadd_vv_nxv8f32_nxv8f32_nxv8f32(<vscale x 8 x float> %0, <vscale x 8 x float> %1, <vscale x 8 x float> %2, iXLen %3) nounwind { define <vscale x 8 x float> @intrinsic_vfnmadd_vv_nxv8f32_nxv8f32_nxv8f32(<vscale x 8 x float> %0, <vscale x 8 x float> %1, <vscale x 8 x float> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfnmadd_vv_nxv8f32_nxv8f32_nxv8f32: ; CHECK-LABEL: intrinsic_vfnmadd_vv_nxv8f32_nxv8f32_nxv8f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, ma ; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, ma
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfnmadd.vv v8, v12, v16 ; CHECK-NEXT: vfnmadd.vv v8, v12, v16
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x float> @llvm.riscv.vfnmadd.nxv8f32.nxv8f32( %a = call <vscale x 8 x float> @llvm.riscv.vfnmadd.nxv8f32.nxv8f32(
<vscale x 8 x float> %0, <vscale x 8 x float> %0,
<vscale x 8 x float> %1, <vscale x 8 x float> %1,
<vscale x 8 x float> %2, <vscale x 8 x float> %2,
iXLen %3, iXLen 0) iXLen 0, iXLen %3, iXLen 0)
ret <vscale x 8 x float> %a ret <vscale x 8 x float> %a
} }
declare <vscale x 8 x float> @llvm.riscv.vfnmadd.mask.nxv8f32.nxv8f32( declare <vscale x 8 x float> @llvm.riscv.vfnmadd.mask.nxv8f32.nxv8f32(
<vscale x 8 x float>, <vscale x 8 x float>,
<vscale x 8 x float>, <vscale x 8 x float>,
<vscale x 8 x float>, <vscale x 8 x float>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
iXLen, iXLen); iXLen, iXLen, iXLen);
define <vscale x 8 x float> @intrinsic_vfnmadd_mask_vv_nxv8f32_nxv8f32_nxv8f32(<vscale x 8 x float> %0, <vscale x 8 x float> %1, <vscale x 8 x float> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind { define <vscale x 8 x float> @intrinsic_vfnmadd_mask_vv_nxv8f32_nxv8f32_nxv8f32(<vscale x 8 x float> %0, <vscale x 8 x float> %1, <vscale x 8 x float> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfnmadd_mask_vv_nxv8f32_nxv8f32_nxv8f32: ; CHECK-LABEL: intrinsic_vfnmadd_mask_vv_nxv8f32_nxv8f32_nxv8f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfnmadd.vv v8, v12, v16, v0.t ; CHECK-NEXT: vfnmadd.vv v8, v12, v16, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x float> @llvm.riscv.vfnmadd.mask.nxv8f32.nxv8f32( %a = call <vscale x 8 x float> @llvm.riscv.vfnmadd.mask.nxv8f32.nxv8f32(
<vscale x 8 x float> %0, <vscale x 8 x float> %0,
<vscale x 8 x float> %1, <vscale x 8 x float> %1,
<vscale x 8 x float> %2, <vscale x 8 x float> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
iXLen %4, iXLen 0); iXLen 0, iXLen %4, iXLen 0);
ret <vscale x 8 x float> %a ret <vscale x 8 x float> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vfnmadd.nxv1f64.nxv1f64( declare <vscale x 1 x double> @llvm.riscv.vfnmadd.nxv1f64.nxv1f64(
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 1 x double>, <vscale x 1 x double>,
iXLen, iXLen, iXLen, iXLen);
iXLen);
define <vscale x 1 x double> @intrinsic_vfnmadd_vv_nxv1f64_nxv1f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 1 x double> %1, <vscale x 1 x double> %2, iXLen %3) nounwind { define <vscale x 1 x double> @intrinsic_vfnmadd_vv_nxv1f64_nxv1f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 1 x double> %1, <vscale x 1 x double> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfnmadd_vv_nxv1f64_nxv1f64_nxv1f64: ; CHECK-LABEL: intrinsic_vfnmadd_vv_nxv1f64_nxv1f64_nxv1f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, ma ; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, ma
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfnmadd.vv v8, v9, v10 ; CHECK-NEXT: vfnmadd.vv v8, v9, v10
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfnmadd.nxv1f64.nxv1f64( %a = call <vscale x 1 x double> @llvm.riscv.vfnmadd.nxv1f64.nxv1f64(
<vscale x 1 x double> %0, <vscale x 1 x double> %0,
<vscale x 1 x double> %1, <vscale x 1 x double> %1,
<vscale x 1 x double> %2, <vscale x 1 x double> %2,
iXLen %3, iXLen 0) iXLen 0, iXLen %3, iXLen 0)
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vfnmadd.mask.nxv1f64.nxv1f64( declare <vscale x 1 x double> @llvm.riscv.vfnmadd.mask.nxv1f64.nxv1f64(
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
iXLen, iXLen); iXLen, iXLen, iXLen);
define <vscale x 1 x double> @intrinsic_vfnmadd_mask_vv_nxv1f64_nxv1f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 1 x double> %1, <vscale x 1 x double> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind { define <vscale x 1 x double> @intrinsic_vfnmadd_mask_vv_nxv1f64_nxv1f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 1 x double> %1, <vscale x 1 x double> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfnmadd_mask_vv_nxv1f64_nxv1f64_nxv1f64: ; CHECK-LABEL: intrinsic_vfnmadd_mask_vv_nxv1f64_nxv1f64_nxv1f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, mu
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfnmadd.vv v8, v9, v10, v0.t ; CHECK-NEXT: vfnmadd.vv v8, v9, v10, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfnmadd.mask.nxv1f64.nxv1f64( %a = call <vscale x 1 x double> @llvm.riscv.vfnmadd.mask.nxv1f64.nxv1f64(
<vscale x 1 x double> %0, <vscale x 1 x double> %0,
<vscale x 1 x double> %1, <vscale x 1 x double> %1,
<vscale x 1 x double> %2, <vscale x 1 x double> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
iXLen %4, iXLen 0); iXLen 0, iXLen %4, iXLen 0);
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 2 x double> @llvm.riscv.vfnmadd.nxv2f64.nxv2f64( declare <vscale x 2 x double> @llvm.riscv.vfnmadd.nxv2f64.nxv2f64(
<vscale x 2 x double>, <vscale x 2 x double>,
<vscale x 2 x double>, <vscale x 2 x double>,
<vscale x 2 x double>, <vscale x 2 x double>,
iXLen, iXLen, iXLen, iXLen);
iXLen);
define <vscale x 2 x double> @intrinsic_vfnmadd_vv_nxv2f64_nxv2f64_nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1, <vscale x 2 x double> %2, iXLen %3) nounwind { define <vscale x 2 x double> @intrinsic_vfnmadd_vv_nxv2f64_nxv2f64_nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1, <vscale x 2 x double> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfnmadd_vv_nxv2f64_nxv2f64_nxv2f64: ; CHECK-LABEL: intrinsic_vfnmadd_vv_nxv2f64_nxv2f64_nxv2f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, ma ; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, ma
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfnmadd.vv v8, v10, v12 ; CHECK-NEXT: vfnmadd.vv v8, v10, v12
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x double> @llvm.riscv.vfnmadd.nxv2f64.nxv2f64( %a = call <vscale x 2 x double> @llvm.riscv.vfnmadd.nxv2f64.nxv2f64(
<vscale x 2 x double> %0, <vscale x 2 x double> %0,
<vscale x 2 x double> %1, <vscale x 2 x double> %1,
<vscale x 2 x double> %2, <vscale x 2 x double> %2,
iXLen %3, iXLen 0) iXLen 0, iXLen %3, iXLen 0)
ret <vscale x 2 x double> %a ret <vscale x 2 x double> %a
} }
declare <vscale x 2 x double> @llvm.riscv.vfnmadd.mask.nxv2f64.nxv2f64( declare <vscale x 2 x double> @llvm.riscv.vfnmadd.mask.nxv2f64.nxv2f64(
<vscale x 2 x double>, <vscale x 2 x double>,
<vscale x 2 x double>, <vscale x 2 x double>,
<vscale x 2 x double>, <vscale x 2 x double>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
iXLen, iXLen); iXLen, iXLen, iXLen);
define <vscale x 2 x double> @intrinsic_vfnmadd_mask_vv_nxv2f64_nxv2f64_nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1, <vscale x 2 x double> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind { define <vscale x 2 x double> @intrinsic_vfnmadd_mask_vv_nxv2f64_nxv2f64_nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1, <vscale x 2 x double> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfnmadd_mask_vv_nxv2f64_nxv2f64_nxv2f64: ; CHECK-LABEL: intrinsic_vfnmadd_mask_vv_nxv2f64_nxv2f64_nxv2f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, mu
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfnmadd.vv v8, v10, v12, v0.t ; CHECK-NEXT: vfnmadd.vv v8, v10, v12, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x double> @llvm.riscv.vfnmadd.mask.nxv2f64.nxv2f64( %a = call <vscale x 2 x double> @llvm.riscv.vfnmadd.mask.nxv2f64.nxv2f64(
<vscale x 2 x double> %0, <vscale x 2 x double> %0,
<vscale x 2 x double> %1, <vscale x 2 x double> %1,
<vscale x 2 x double> %2, <vscale x 2 x double> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
iXLen %4, iXLen 0); iXLen 0, iXLen %4, iXLen 0);
ret <vscale x 2 x double> %a ret <vscale x 2 x double> %a
} }
declare <vscale x 4 x double> @llvm.riscv.vfnmadd.nxv4f64.nxv4f64( declare <vscale x 4 x double> @llvm.riscv.vfnmadd.nxv4f64.nxv4f64(
<vscale x 4 x double>, <vscale x 4 x double>,
<vscale x 4 x double>, <vscale x 4 x double>,
<vscale x 4 x double>, <vscale x 4 x double>,
iXLen, iXLen, iXLen, iXLen);
iXLen);
define <vscale x 4 x double> @intrinsic_vfnmadd_vv_nxv4f64_nxv4f64_nxv4f64(<vscale x 4 x double> %0, <vscale x 4 x double> %1, <vscale x 4 x double> %2, iXLen %3) nounwind { define <vscale x 4 x double> @intrinsic_vfnmadd_vv_nxv4f64_nxv4f64_nxv4f64(<vscale x 4 x double> %0, <vscale x 4 x double> %1, <vscale x 4 x double> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfnmadd_vv_nxv4f64_nxv4f64_nxv4f64: ; CHECK-LABEL: intrinsic_vfnmadd_vv_nxv4f64_nxv4f64_nxv4f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, ma ; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, ma
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfnmadd.vv v8, v12, v16 ; CHECK-NEXT: vfnmadd.vv v8, v12, v16
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x double> @llvm.riscv.vfnmadd.nxv4f64.nxv4f64( %a = call <vscale x 4 x double> @llvm.riscv.vfnmadd.nxv4f64.nxv4f64(
<vscale x 4 x double> %0, <vscale x 4 x double> %0,
<vscale x 4 x double> %1, <vscale x 4 x double> %1,
<vscale x 4 x double> %2, <vscale x 4 x double> %2,
iXLen %3, iXLen 0) iXLen 0, iXLen %3, iXLen 0)
ret <vscale x 4 x double> %a ret <vscale x 4 x double> %a
} }
declare <vscale x 4 x double> @llvm.riscv.vfnmadd.mask.nxv4f64.nxv4f64( declare <vscale x 4 x double> @llvm.riscv.vfnmadd.mask.nxv4f64.nxv4f64(
<vscale x 4 x double>, <vscale x 4 x double>,
<vscale x 4 x double>, <vscale x 4 x double>,
<vscale x 4 x double>, <vscale x 4 x double>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
iXLen, iXLen); iXLen, iXLen, iXLen);
define <vscale x 4 x double> @intrinsic_vfnmadd_mask_vv_nxv4f64_nxv4f64_nxv4f64(<vscale x 4 x double> %0, <vscale x 4 x double> %1, <vscale x 4 x double> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind { define <vscale x 4 x double> @intrinsic_vfnmadd_mask_vv_nxv4f64_nxv4f64_nxv4f64(<vscale x 4 x double> %0, <vscale x 4 x double> %1, <vscale x 4 x double> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfnmadd_mask_vv_nxv4f64_nxv4f64_nxv4f64: ; CHECK-LABEL: intrinsic_vfnmadd_mask_vv_nxv4f64_nxv4f64_nxv4f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, mu
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfnmadd.vv v8, v12, v16, v0.t ; CHECK-NEXT: vfnmadd.vv v8, v12, v16, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x double> @llvm.riscv.vfnmadd.mask.nxv4f64.nxv4f64( %a = call <vscale x 4 x double> @llvm.riscv.vfnmadd.mask.nxv4f64.nxv4f64(
<vscale x 4 x double> %0, <vscale x 4 x double> %0,
<vscale x 4 x double> %1, <vscale x 4 x double> %1,
<vscale x 4 x double> %2, <vscale x 4 x double> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
iXLen %4, iXLen 0); iXLen 0, iXLen %4, iXLen 0);
ret <vscale x 4 x double> %a ret <vscale x 4 x double> %a
} }
declare <vscale x 1 x half> @llvm.riscv.vfnmadd.nxv1f16.f16( declare <vscale x 1 x half> @llvm.riscv.vfnmadd.nxv1f16.f16(
<vscale x 1 x half>, <vscale x 1 x half>,
half, half,
<vscale x 1 x half>, <vscale x 1 x half>,
iXLen, iXLen, iXLen, iXLen);
iXLen);
define <vscale x 1 x half> @intrinsic_vfnmadd_vf_nxv1f16_f16_nxv1f16(<vscale x 1 x half> %0, half %1, <vscale x 1 x half> %2, iXLen %3) nounwind { define <vscale x 1 x half> @intrinsic_vfnmadd_vf_nxv1f16_f16_nxv1f16(<vscale x 1 x half> %0, half %1, <vscale x 1 x half> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfnmadd_vf_nxv1f16_f16_nxv1f16: ; CHECK-LABEL: intrinsic_vfnmadd_vf_nxv1f16_f16_nxv1f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, ma ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, ma
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfnmadd.vf v8, fa0, v9 ; CHECK-NEXT: vfnmadd.vf v8, fa0, v9
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x half> @llvm.riscv.vfnmadd.nxv1f16.f16( %a = call <vscale x 1 x half> @llvm.riscv.vfnmadd.nxv1f16.f16(
<vscale x 1 x half> %0, <vscale x 1 x half> %0,
half %1, half %1,
<vscale x 1 x half> %2, <vscale x 1 x half> %2,
iXLen %3, iXLen 0) iXLen 0, iXLen %3, iXLen 0)
ret <vscale x 1 x half> %a ret <vscale x 1 x half> %a
} }
declare <vscale x 1 x half> @llvm.riscv.vfnmadd.mask.nxv1f16.f16( declare <vscale x 1 x half> @llvm.riscv.vfnmadd.mask.nxv1f16.f16(
<vscale x 1 x half>, <vscale x 1 x half>,
half, half,
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
iXLen, iXLen); iXLen, iXLen, iXLen);
define <vscale x 1 x half> @intrinsic_vfnmadd_mask_vf_nxv1f16_f16_nxv1f16(<vscale x 1 x half> %0, half %1, <vscale x 1 x half> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind { define <vscale x 1 x half> @intrinsic_vfnmadd_mask_vf_nxv1f16_f16_nxv1f16(<vscale x 1 x half> %0, half %1, <vscale x 1 x half> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfnmadd_mask_vf_nxv1f16_f16_nxv1f16: ; CHECK-LABEL: intrinsic_vfnmadd_mask_vf_nxv1f16_f16_nxv1f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfnmadd.vf v8, fa0, v9, v0.t ; CHECK-NEXT: vfnmadd.vf v8, fa0, v9, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x half> @llvm.riscv.vfnmadd.mask.nxv1f16.f16( %a = call <vscale x 1 x half> @llvm.riscv.vfnmadd.mask.nxv1f16.f16(
<vscale x 1 x half> %0, <vscale x 1 x half> %0,
half %1, half %1,
<vscale x 1 x half> %2, <vscale x 1 x half> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
iXLen %4, iXLen 0); iXLen 0, iXLen %4, iXLen 0);
ret <vscale x 1 x half> %a ret <vscale x 1 x half> %a
} }
declare <vscale x 2 x half> @llvm.riscv.vfnmadd.nxv2f16.f16( declare <vscale x 2 x half> @llvm.riscv.vfnmadd.nxv2f16.f16(
<vscale x 2 x half>, <vscale x 2 x half>,
half, half,
<vscale x 2 x half>, <vscale x 2 x half>,
iXLen, iXLen, iXLen, iXLen);
iXLen);
define <vscale x 2 x half> @intrinsic_vfnmadd_vf_nxv2f16_f16_nxv2f16(<vscale x 2 x half> %0, half %1, <vscale x 2 x half> %2, iXLen %3) nounwind { define <vscale x 2 x half> @intrinsic_vfnmadd_vf_nxv2f16_f16_nxv2f16(<vscale x 2 x half> %0, half %1, <vscale x 2 x half> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfnmadd_vf_nxv2f16_f16_nxv2f16: ; CHECK-LABEL: intrinsic_vfnmadd_vf_nxv2f16_f16_nxv2f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, ma ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, ma
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfnmadd.vf v8, fa0, v9 ; CHECK-NEXT: vfnmadd.vf v8, fa0, v9
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x half> @llvm.riscv.vfnmadd.nxv2f16.f16( %a = call <vscale x 2 x half> @llvm.riscv.vfnmadd.nxv2f16.f16(
<vscale x 2 x half> %0, <vscale x 2 x half> %0,
half %1, half %1,
<vscale x 2 x half> %2, <vscale x 2 x half> %2,
iXLen %3, iXLen 0) iXLen 0, iXLen %3, iXLen 0)
ret <vscale x 2 x half> %a ret <vscale x 2 x half> %a
} }
declare <vscale x 2 x half> @llvm.riscv.vfnmadd.mask.nxv2f16.f16( declare <vscale x 2 x half> @llvm.riscv.vfnmadd.mask.nxv2f16.f16(
<vscale x 2 x half>, <vscale x 2 x half>,
half, half,
<vscale x 2 x half>, <vscale x 2 x half>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
iXLen, iXLen); iXLen, iXLen, iXLen);
define <vscale x 2 x half> @intrinsic_vfnmadd_mask_vf_nxv2f16_f16_nxv2f16(<vscale x 2 x half> %0, half %1, <vscale x 2 x half> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind { define <vscale x 2 x half> @intrinsic_vfnmadd_mask_vf_nxv2f16_f16_nxv2f16(<vscale x 2 x half> %0, half %1, <vscale x 2 x half> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfnmadd_mask_vf_nxv2f16_f16_nxv2f16: ; CHECK-LABEL: intrinsic_vfnmadd_mask_vf_nxv2f16_f16_nxv2f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfnmadd.vf v8, fa0, v9, v0.t ; CHECK-NEXT: vfnmadd.vf v8, fa0, v9, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x half> @llvm.riscv.vfnmadd.mask.nxv2f16.f16( %a = call <vscale x 2 x half> @llvm.riscv.vfnmadd.mask.nxv2f16.f16(
<vscale x 2 x half> %0, <vscale x 2 x half> %0,
half %1, half %1,
<vscale x 2 x half> %2, <vscale x 2 x half> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
iXLen %4, iXLen 0); iXLen 0, iXLen %4, iXLen 0);
ret <vscale x 2 x half> %a ret <vscale x 2 x half> %a
} }
declare <vscale x 4 x half> @llvm.riscv.vfnmadd.nxv4f16.f16( declare <vscale x 4 x half> @llvm.riscv.vfnmadd.nxv4f16.f16(
<vscale x 4 x half>, <vscale x 4 x half>,
half, half,
<vscale x 4 x half>, <vscale x 4 x half>,
iXLen, iXLen, iXLen, iXLen);
iXLen);
define <vscale x 4 x half> @intrinsic_vfnmadd_vf_nxv4f16_f16_nxv4f16(<vscale x 4 x half> %0, half %1, <vscale x 4 x half> %2, iXLen %3) nounwind { define <vscale x 4 x half> @intrinsic_vfnmadd_vf_nxv4f16_f16_nxv4f16(<vscale x 4 x half> %0, half %1, <vscale x 4 x half> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfnmadd_vf_nxv4f16_f16_nxv4f16: ; CHECK-LABEL: intrinsic_vfnmadd_vf_nxv4f16_f16_nxv4f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, ma ; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, ma
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfnmadd.vf v8, fa0, v9 ; CHECK-NEXT: vfnmadd.vf v8, fa0, v9
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x half> @llvm.riscv.vfnmadd.nxv4f16.f16( %a = call <vscale x 4 x half> @llvm.riscv.vfnmadd.nxv4f16.f16(
<vscale x 4 x half> %0, <vscale x 4 x half> %0,
half %1, half %1,
<vscale x 4 x half> %2, <vscale x 4 x half> %2,
iXLen %3, iXLen 0) iXLen 0, iXLen %3, iXLen 0)
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 4 x half> @llvm.riscv.vfnmadd.mask.nxv4f16.f16( declare <vscale x 4 x half> @llvm.riscv.vfnmadd.mask.nxv4f16.f16(
<vscale x 4 x half>, <vscale x 4 x half>,
half, half,
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
iXLen, iXLen); iXLen, iXLen, iXLen);
define <vscale x 4 x half> @intrinsic_vfnmadd_mask_vf_nxv4f16_f16_nxv4f16(<vscale x 4 x half> %0, half %1, <vscale x 4 x half> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind { define <vscale x 4 x half> @intrinsic_vfnmadd_mask_vf_nxv4f16_f16_nxv4f16(<vscale x 4 x half> %0, half %1, <vscale x 4 x half> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfnmadd_mask_vf_nxv4f16_f16_nxv4f16: ; CHECK-LABEL: intrinsic_vfnmadd_mask_vf_nxv4f16_f16_nxv4f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfnmadd.vf v8, fa0, v9, v0.t ; CHECK-NEXT: vfnmadd.vf v8, fa0, v9, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x half> @llvm.riscv.vfnmadd.mask.nxv4f16.f16( %a = call <vscale x 4 x half> @llvm.riscv.vfnmadd.mask.nxv4f16.f16(
<vscale x 4 x half> %0, <vscale x 4 x half> %0,
half %1, half %1,
<vscale x 4 x half> %2, <vscale x 4 x half> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
iXLen %4, iXLen 0); iXLen 0, iXLen %4, iXLen 0);
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 8 x half> @llvm.riscv.vfnmadd.nxv8f16.f16( declare <vscale x 8 x half> @llvm.riscv.vfnmadd.nxv8f16.f16(
<vscale x 8 x half>, <vscale x 8 x half>,
half, half,
<vscale x 8 x half>, <vscale x 8 x half>,
iXLen, iXLen, iXLen, iXLen);
iXLen);
define <vscale x 8 x half> @intrinsic_vfnmadd_vf_nxv8f16_f16_nxv8f16(<vscale x 8 x half> %0, half %1, <vscale x 8 x half> %2, iXLen %3) nounwind { define <vscale x 8 x half> @intrinsic_vfnmadd_vf_nxv8f16_f16_nxv8f16(<vscale x 8 x half> %0, half %1, <vscale x 8 x half> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfnmadd_vf_nxv8f16_f16_nxv8f16: ; CHECK-LABEL: intrinsic_vfnmadd_vf_nxv8f16_f16_nxv8f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, ma ; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, ma
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfnmadd.vf v8, fa0, v10 ; CHECK-NEXT: vfnmadd.vf v8, fa0, v10
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x half> @llvm.riscv.vfnmadd.nxv8f16.f16( %a = call <vscale x 8 x half> @llvm.riscv.vfnmadd.nxv8f16.f16(
<vscale x 8 x half> %0, <vscale x 8 x half> %0,
half %1, half %1,
<vscale x 8 x half> %2, <vscale x 8 x half> %2,
iXLen %3, iXLen 0) iXLen 0, iXLen %3, iXLen 0)
ret <vscale x 8 x half> %a ret <vscale x 8 x half> %a
} }
declare <vscale x 8 x half> @llvm.riscv.vfnmadd.mask.nxv8f16.f16( declare <vscale x 8 x half> @llvm.riscv.vfnmadd.mask.nxv8f16.f16(
<vscale x 8 x half>, <vscale x 8 x half>,
half, half,
<vscale x 8 x half>, <vscale x 8 x half>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
iXLen, iXLen); iXLen, iXLen, iXLen);
define <vscale x 8 x half> @intrinsic_vfnmadd_mask_vf_nxv8f16_f16_nxv8f16(<vscale x 8 x half> %0, half %1, <vscale x 8 x half> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind { define <vscale x 8 x half> @intrinsic_vfnmadd_mask_vf_nxv8f16_f16_nxv8f16(<vscale x 8 x half> %0, half %1, <vscale x 8 x half> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfnmadd_mask_vf_nxv8f16_f16_nxv8f16: ; CHECK-LABEL: intrinsic_vfnmadd_mask_vf_nxv8f16_f16_nxv8f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, mu
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfnmadd.vf v8, fa0, v10, v0.t ; CHECK-NEXT: vfnmadd.vf v8, fa0, v10, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x half> @llvm.riscv.vfnmadd.mask.nxv8f16.f16( %a = call <vscale x 8 x half> @llvm.riscv.vfnmadd.mask.nxv8f16.f16(
<vscale x 8 x half> %0, <vscale x 8 x half> %0,
half %1, half %1,
<vscale x 8 x half> %2, <vscale x 8 x half> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
iXLen %4, iXLen 0); iXLen 0, iXLen %4, iXLen 0);
ret <vscale x 8 x half> %a ret <vscale x 8 x half> %a
} }
declare <vscale x 16 x half> @llvm.riscv.vfnmadd.nxv16f16.f16( declare <vscale x 16 x half> @llvm.riscv.vfnmadd.nxv16f16.f16(
<vscale x 16 x half>, <vscale x 16 x half>,
half, half,
<vscale x 16 x half>, <vscale x 16 x half>,
iXLen, iXLen, iXLen, iXLen);
iXLen);
define <vscale x 16 x half> @intrinsic_vfnmadd_vf_nxv16f16_f16_nxv16f16(<vscale x 16 x half> %0, half %1, <vscale x 16 x half> %2, iXLen %3) nounwind { define <vscale x 16 x half> @intrinsic_vfnmadd_vf_nxv16f16_f16_nxv16f16(<vscale x 16 x half> %0, half %1, <vscale x 16 x half> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfnmadd_vf_nxv16f16_f16_nxv16f16: ; CHECK-LABEL: intrinsic_vfnmadd_vf_nxv16f16_f16_nxv16f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, ma ; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, ma
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfnmadd.vf v8, fa0, v12 ; CHECK-NEXT: vfnmadd.vf v8, fa0, v12
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x half> @llvm.riscv.vfnmadd.nxv16f16.f16( %a = call <vscale x 16 x half> @llvm.riscv.vfnmadd.nxv16f16.f16(
<vscale x 16 x half> %0, <vscale x 16 x half> %0,
half %1, half %1,
<vscale x 16 x half> %2, <vscale x 16 x half> %2,
iXLen %3, iXLen 0) iXLen 0, iXLen %3, iXLen 0)
ret <vscale x 16 x half> %a ret <vscale x 16 x half> %a
} }
declare <vscale x 16 x half> @llvm.riscv.vfnmadd.mask.nxv16f16.f16( declare <vscale x 16 x half> @llvm.riscv.vfnmadd.mask.nxv16f16.f16(
<vscale x 16 x half>, <vscale x 16 x half>,
half, half,
<vscale x 16 x half>, <vscale x 16 x half>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
iXLen, iXLen); iXLen, iXLen, iXLen);
define <vscale x 16 x half> @intrinsic_vfnmadd_mask_vf_nxv16f16_f16_nxv16f16(<vscale x 16 x half> %0, half %1, <vscale x 16 x half> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind { define <vscale x 16 x half> @intrinsic_vfnmadd_mask_vf_nxv16f16_f16_nxv16f16(<vscale x 16 x half> %0, half %1, <vscale x 16 x half> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfnmadd_mask_vf_nxv16f16_f16_nxv16f16: ; CHECK-LABEL: intrinsic_vfnmadd_mask_vf_nxv16f16_f16_nxv16f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfnmadd.vf v8, fa0, v12, v0.t ; CHECK-NEXT: vfnmadd.vf v8, fa0, v12, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x half> @llvm.riscv.vfnmadd.mask.nxv16f16.f16( %a = call <vscale x 16 x half> @llvm.riscv.vfnmadd.mask.nxv16f16.f16(
<vscale x 16 x half> %0, <vscale x 16 x half> %0,
half %1, half %1,
<vscale x 16 x half> %2, <vscale x 16 x half> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
iXLen %4, iXLen 0); iXLen 0, iXLen %4, iXLen 0);
ret <vscale x 16 x half> %a ret <vscale x 16 x half> %a
} }
declare <vscale x 1 x float> @llvm.riscv.vfnmadd.nxv1f32.f32( declare <vscale x 1 x float> @llvm.riscv.vfnmadd.nxv1f32.f32(
<vscale x 1 x float>, <vscale x 1 x float>,
float, float,
<vscale x 1 x float>, <vscale x 1 x float>,
iXLen, iXLen, iXLen, iXLen);
iXLen);
define <vscale x 1 x float> @intrinsic_vfnmadd_vf_nxv1f32_f32_nxv1f32(<vscale x 1 x float> %0, float %1, <vscale x 1 x float> %2, iXLen %3) nounwind { define <vscale x 1 x float> @intrinsic_vfnmadd_vf_nxv1f32_f32_nxv1f32(<vscale x 1 x float> %0, float %1, <vscale x 1 x float> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfnmadd_vf_nxv1f32_f32_nxv1f32: ; CHECK-LABEL: intrinsic_vfnmadd_vf_nxv1f32_f32_nxv1f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, ma ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, ma
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfnmadd.vf v8, fa0, v9 ; CHECK-NEXT: vfnmadd.vf v8, fa0, v9
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x float> @llvm.riscv.vfnmadd.nxv1f32.f32( %a = call <vscale x 1 x float> @llvm.riscv.vfnmadd.nxv1f32.f32(
<vscale x 1 x float> %0, <vscale x 1 x float> %0,
float %1, float %1,
<vscale x 1 x float> %2, <vscale x 1 x float> %2,
iXLen %3, iXLen 0) iXLen 0, iXLen %3, iXLen 0)
ret <vscale x 1 x float> %a ret <vscale x 1 x float> %a
} }
declare <vscale x 1 x float> @llvm.riscv.vfnmadd.mask.nxv1f32.f32( declare <vscale x 1 x float> @llvm.riscv.vfnmadd.mask.nxv1f32.f32(
<vscale x 1 x float>, <vscale x 1 x float>,
float, float,
<vscale x 1 x float>, <vscale x 1 x float>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
iXLen, iXLen); iXLen, iXLen, iXLen);
define <vscale x 1 x float> @intrinsic_vfnmadd_mask_vf_nxv1f32_f32_nxv1f32(<vscale x 1 x float> %0, float %1, <vscale x 1 x float> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind { define <vscale x 1 x float> @intrinsic_vfnmadd_mask_vf_nxv1f32_f32_nxv1f32(<vscale x 1 x float> %0, float %1, <vscale x 1 x float> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfnmadd_mask_vf_nxv1f32_f32_nxv1f32: ; CHECK-LABEL: intrinsic_vfnmadd_mask_vf_nxv1f32_f32_nxv1f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfnmadd.vf v8, fa0, v9, v0.t ; CHECK-NEXT: vfnmadd.vf v8, fa0, v9, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x float> @llvm.riscv.vfnmadd.mask.nxv1f32.f32( %a = call <vscale x 1 x float> @llvm.riscv.vfnmadd.mask.nxv1f32.f32(
<vscale x 1 x float> %0, <vscale x 1 x float> %0,
float %1, float %1,
<vscale x 1 x float> %2, <vscale x 1 x float> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
iXLen %4, iXLen 0); iXLen 0, iXLen %4, iXLen 0);
ret <vscale x 1 x float> %a ret <vscale x 1 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vfnmadd.nxv2f32.f32( declare <vscale x 2 x float> @llvm.riscv.vfnmadd.nxv2f32.f32(
<vscale x 2 x float>, <vscale x 2 x float>,
float, float,
<vscale x 2 x float>, <vscale x 2 x float>,
iXLen, iXLen, iXLen, iXLen);
iXLen);
define <vscale x 2 x float> @intrinsic_vfnmadd_vf_nxv2f32_f32_nxv2f32(<vscale x 2 x float> %0, float %1, <vscale x 2 x float> %2, iXLen %3) nounwind { define <vscale x 2 x float> @intrinsic_vfnmadd_vf_nxv2f32_f32_nxv2f32(<vscale x 2 x float> %0, float %1, <vscale x 2 x float> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfnmadd_vf_nxv2f32_f32_nxv2f32: ; CHECK-LABEL: intrinsic_vfnmadd_vf_nxv2f32_f32_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, ma ; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, ma
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfnmadd.vf v8, fa0, v9 ; CHECK-NEXT: vfnmadd.vf v8, fa0, v9
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfnmadd.nxv2f32.f32( %a = call <vscale x 2 x float> @llvm.riscv.vfnmadd.nxv2f32.f32(
<vscale x 2 x float> %0, <vscale x 2 x float> %0,
float %1, float %1,
<vscale x 2 x float> %2, <vscale x 2 x float> %2,
iXLen %3, iXLen 0) iXLen 0, iXLen %3, iXLen 0)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vfnmadd.mask.nxv2f32.f32( declare <vscale x 2 x float> @llvm.riscv.vfnmadd.mask.nxv2f32.f32(
<vscale x 2 x float>, <vscale x 2 x float>,
float, float,
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
iXLen, iXLen); iXLen, iXLen, iXLen);
define <vscale x 2 x float> @intrinsic_vfnmadd_mask_vf_nxv2f32_f32_nxv2f32(<vscale x 2 x float> %0, float %1, <vscale x 2 x float> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind { define <vscale x 2 x float> @intrinsic_vfnmadd_mask_vf_nxv2f32_f32_nxv2f32(<vscale x 2 x float> %0, float %1, <vscale x 2 x float> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfnmadd_mask_vf_nxv2f32_f32_nxv2f32: ; CHECK-LABEL: intrinsic_vfnmadd_mask_vf_nxv2f32_f32_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfnmadd.vf v8, fa0, v9, v0.t ; CHECK-NEXT: vfnmadd.vf v8, fa0, v9, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfnmadd.mask.nxv2f32.f32( %a = call <vscale x 2 x float> @llvm.riscv.vfnmadd.mask.nxv2f32.f32(
<vscale x 2 x float> %0, <vscale x 2 x float> %0,
float %1, float %1,
<vscale x 2 x float> %2, <vscale x 2 x float> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
iXLen %4, iXLen 0); iXLen 0, iXLen %4, iXLen 0);
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 4 x float> @llvm.riscv.vfnmadd.nxv4f32.f32( declare <vscale x 4 x float> @llvm.riscv.vfnmadd.nxv4f32.f32(
<vscale x 4 x float>, <vscale x 4 x float>,
float, float,
<vscale x 4 x float>, <vscale x 4 x float>,
iXLen, iXLen, iXLen, iXLen);
iXLen);
define <vscale x 4 x float> @intrinsic_vfnmadd_vf_nxv4f32_f32_nxv4f32(<vscale x 4 x float> %0, float %1, <vscale x 4 x float> %2, iXLen %3) nounwind { define <vscale x 4 x float> @intrinsic_vfnmadd_vf_nxv4f32_f32_nxv4f32(<vscale x 4 x float> %0, float %1, <vscale x 4 x float> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfnmadd_vf_nxv4f32_f32_nxv4f32: ; CHECK-LABEL: intrinsic_vfnmadd_vf_nxv4f32_f32_nxv4f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, ma ; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, ma
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfnmadd.vf v8, fa0, v10 ; CHECK-NEXT: vfnmadd.vf v8, fa0, v10
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x float> @llvm.riscv.vfnmadd.nxv4f32.f32( %a = call <vscale x 4 x float> @llvm.riscv.vfnmadd.nxv4f32.f32(
<vscale x 4 x float> %0, <vscale x 4 x float> %0,
float %1, float %1,
<vscale x 4 x float> %2, <vscale x 4 x float> %2,
iXLen %3, iXLen 0) iXLen 0, iXLen %3, iXLen 0)
ret <vscale x 4 x float> %a ret <vscale x 4 x float> %a
} }
declare <vscale x 4 x float> @llvm.riscv.vfnmadd.mask.nxv4f32.f32( declare <vscale x 4 x float> @llvm.riscv.vfnmadd.mask.nxv4f32.f32(
<vscale x 4 x float>, <vscale x 4 x float>,
float, float,
<vscale x 4 x float>, <vscale x 4 x float>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
iXLen, iXLen); iXLen, iXLen, iXLen);
define <vscale x 4 x float> @intrinsic_vfnmadd_mask_vf_nxv4f32_f32_nxv4f32(<vscale x 4 x float> %0, float %1, <vscale x 4 x float> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind { define <vscale x 4 x float> @intrinsic_vfnmadd_mask_vf_nxv4f32_f32_nxv4f32(<vscale x 4 x float> %0, float %1, <vscale x 4 x float> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfnmadd_mask_vf_nxv4f32_f32_nxv4f32: ; CHECK-LABEL: intrinsic_vfnmadd_mask_vf_nxv4f32_f32_nxv4f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfnmadd.vf v8, fa0, v10, v0.t ; CHECK-NEXT: vfnmadd.vf v8, fa0, v10, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x float> @llvm.riscv.vfnmadd.mask.nxv4f32.f32( %a = call <vscale x 4 x float> @llvm.riscv.vfnmadd.mask.nxv4f32.f32(
<vscale x 4 x float> %0, <vscale x 4 x float> %0,
float %1, float %1,
<vscale x 4 x float> %2, <vscale x 4 x float> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
iXLen %4, iXLen 0); iXLen 0, iXLen %4, iXLen 0);
ret <vscale x 4 x float> %a ret <vscale x 4 x float> %a
} }
declare <vscale x 8 x float> @llvm.riscv.vfnmadd.nxv8f32.f32( declare <vscale x 8 x float> @llvm.riscv.vfnmadd.nxv8f32.f32(
<vscale x 8 x float>, <vscale x 8 x float>,
float, float,
<vscale x 8 x float>, <vscale x 8 x float>,
iXLen, iXLen, iXLen, iXLen);
iXLen);
define <vscale x 8 x float> @intrinsic_vfnmadd_vf_nxv8f32_f32_nxv8f32(<vscale x 8 x float> %0, float %1, <vscale x 8 x float> %2, iXLen %3) nounwind { define <vscale x 8 x float> @intrinsic_vfnmadd_vf_nxv8f32_f32_nxv8f32(<vscale x 8 x float> %0, float %1, <vscale x 8 x float> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfnmadd_vf_nxv8f32_f32_nxv8f32: ; CHECK-LABEL: intrinsic_vfnmadd_vf_nxv8f32_f32_nxv8f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, ma ; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, ma
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfnmadd.vf v8, fa0, v12 ; CHECK-NEXT: vfnmadd.vf v8, fa0, v12
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x float> @llvm.riscv.vfnmadd.nxv8f32.f32( %a = call <vscale x 8 x float> @llvm.riscv.vfnmadd.nxv8f32.f32(
<vscale x 8 x float> %0, <vscale x 8 x float> %0,
float %1, float %1,
<vscale x 8 x float> %2, <vscale x 8 x float> %2,
iXLen %3, iXLen 0) iXLen 0, iXLen %3, iXLen 0)
ret <vscale x 8 x float> %a ret <vscale x 8 x float> %a
} }
declare <vscale x 8 x float> @llvm.riscv.vfnmadd.mask.nxv8f32.f32( declare <vscale x 8 x float> @llvm.riscv.vfnmadd.mask.nxv8f32.f32(
<vscale x 8 x float>, <vscale x 8 x float>,
float, float,
<vscale x 8 x float>, <vscale x 8 x float>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
iXLen, iXLen); iXLen, iXLen, iXLen);
define <vscale x 8 x float> @intrinsic_vfnmadd_mask_vf_nxv8f32_f32_nxv8f32(<vscale x 8 x float> %0, float %1, <vscale x 8 x float> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind { define <vscale x 8 x float> @intrinsic_vfnmadd_mask_vf_nxv8f32_f32_nxv8f32(<vscale x 8 x float> %0, float %1, <vscale x 8 x float> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfnmadd_mask_vf_nxv8f32_f32_nxv8f32: ; CHECK-LABEL: intrinsic_vfnmadd_mask_vf_nxv8f32_f32_nxv8f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfnmadd.vf v8, fa0, v12, v0.t ; CHECK-NEXT: vfnmadd.vf v8, fa0, v12, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x float> @llvm.riscv.vfnmadd.mask.nxv8f32.f32( %a = call <vscale x 8 x float> @llvm.riscv.vfnmadd.mask.nxv8f32.f32(
<vscale x 8 x float> %0, <vscale x 8 x float> %0,
float %1, float %1,
<vscale x 8 x float> %2, <vscale x 8 x float> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
iXLen %4, iXLen 0); iXLen 0, iXLen %4, iXLen 0);
ret <vscale x 8 x float> %a ret <vscale x 8 x float> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vfnmadd.nxv1f64.f64( declare <vscale x 1 x double> @llvm.riscv.vfnmadd.nxv1f64.f64(
<vscale x 1 x double>, <vscale x 1 x double>,
double, double,
<vscale x 1 x double>, <vscale x 1 x double>,
iXLen, iXLen, iXLen, iXLen);
iXLen);
define <vscale x 1 x double> @intrinsic_vfnmadd_vf_nxv1f64_f64_nxv1f64(<vscale x 1 x double> %0, double %1, <vscale x 1 x double> %2, iXLen %3) nounwind { define <vscale x 1 x double> @intrinsic_vfnmadd_vf_nxv1f64_f64_nxv1f64(<vscale x 1 x double> %0, double %1, <vscale x 1 x double> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfnmadd_vf_nxv1f64_f64_nxv1f64: ; CHECK-LABEL: intrinsic_vfnmadd_vf_nxv1f64_f64_nxv1f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, ma ; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, ma
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfnmadd.vf v8, fa0, v9 ; CHECK-NEXT: vfnmadd.vf v8, fa0, v9
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfnmadd.nxv1f64.f64( %a = call <vscale x 1 x double> @llvm.riscv.vfnmadd.nxv1f64.f64(
<vscale x 1 x double> %0, <vscale x 1 x double> %0,
double %1, double %1,
<vscale x 1 x double> %2, <vscale x 1 x double> %2,
iXLen %3, iXLen 0) iXLen 0, iXLen %3, iXLen 0)
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vfnmadd.mask.nxv1f64.f64( declare <vscale x 1 x double> @llvm.riscv.vfnmadd.mask.nxv1f64.f64(
<vscale x 1 x double>, <vscale x 1 x double>,
double, double,
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
iXLen, iXLen); iXLen, iXLen, iXLen);
define <vscale x 1 x double> @intrinsic_vfnmadd_mask_vf_nxv1f64_f64_nxv1f64(<vscale x 1 x double> %0, double %1, <vscale x 1 x double> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind { define <vscale x 1 x double> @intrinsic_vfnmadd_mask_vf_nxv1f64_f64_nxv1f64(<vscale x 1 x double> %0, double %1, <vscale x 1 x double> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfnmadd_mask_vf_nxv1f64_f64_nxv1f64: ; CHECK-LABEL: intrinsic_vfnmadd_mask_vf_nxv1f64_f64_nxv1f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, mu
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfnmadd.vf v8, fa0, v9, v0.t ; CHECK-NEXT: vfnmadd.vf v8, fa0, v9, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfnmadd.mask.nxv1f64.f64( %a = call <vscale x 1 x double> @llvm.riscv.vfnmadd.mask.nxv1f64.f64(
<vscale x 1 x double> %0, <vscale x 1 x double> %0,
double %1, double %1,
<vscale x 1 x double> %2, <vscale x 1 x double> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
iXLen %4, iXLen 0); iXLen 0, iXLen %4, iXLen 0);
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 2 x double> @llvm.riscv.vfnmadd.nxv2f64.f64( declare <vscale x 2 x double> @llvm.riscv.vfnmadd.nxv2f64.f64(
<vscale x 2 x double>, <vscale x 2 x double>,
double, double,
<vscale x 2 x double>, <vscale x 2 x double>,
iXLen, iXLen, iXLen, iXLen);
iXLen);
define <vscale x 2 x double> @intrinsic_vfnmadd_vf_nxv2f64_f64_nxv2f64(<vscale x 2 x double> %0, double %1, <vscale x 2 x double> %2, iXLen %3) nounwind { define <vscale x 2 x double> @intrinsic_vfnmadd_vf_nxv2f64_f64_nxv2f64(<vscale x 2 x double> %0, double %1, <vscale x 2 x double> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfnmadd_vf_nxv2f64_f64_nxv2f64: ; CHECK-LABEL: intrinsic_vfnmadd_vf_nxv2f64_f64_nxv2f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, ma ; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, ma
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfnmadd.vf v8, fa0, v10 ; CHECK-NEXT: vfnmadd.vf v8, fa0, v10
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x double> @llvm.riscv.vfnmadd.nxv2f64.f64( %a = call <vscale x 2 x double> @llvm.riscv.vfnmadd.nxv2f64.f64(
<vscale x 2 x double> %0, <vscale x 2 x double> %0,
double %1, double %1,
<vscale x 2 x double> %2, <vscale x 2 x double> %2,
iXLen %3, iXLen 0) iXLen 0, iXLen %3, iXLen 0)
ret <vscale x 2 x double> %a ret <vscale x 2 x double> %a
} }
declare <vscale x 2 x double> @llvm.riscv.vfnmadd.mask.nxv2f64.f64( declare <vscale x 2 x double> @llvm.riscv.vfnmadd.mask.nxv2f64.f64(
<vscale x 2 x double>, <vscale x 2 x double>,
double, double,
<vscale x 2 x double>, <vscale x 2 x double>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
iXLen, iXLen); iXLen, iXLen, iXLen);
define <vscale x 2 x double> @intrinsic_vfnmadd_mask_vf_nxv2f64_f64_nxv2f64(<vscale x 2 x double> %0, double %1, <vscale x 2 x double> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind { define <vscale x 2 x double> @intrinsic_vfnmadd_mask_vf_nxv2f64_f64_nxv2f64(<vscale x 2 x double> %0, double %1, <vscale x 2 x double> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfnmadd_mask_vf_nxv2f64_f64_nxv2f64: ; CHECK-LABEL: intrinsic_vfnmadd_mask_vf_nxv2f64_f64_nxv2f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, mu
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfnmadd.vf v8, fa0, v10, v0.t ; CHECK-NEXT: vfnmadd.vf v8, fa0, v10, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x double> @llvm.riscv.vfnmadd.mask.nxv2f64.f64( %a = call <vscale x 2 x double> @llvm.riscv.vfnmadd.mask.nxv2f64.f64(
<vscale x 2 x double> %0, <vscale x 2 x double> %0,
double %1, double %1,
<vscale x 2 x double> %2, <vscale x 2 x double> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
iXLen %4, iXLen 0); iXLen 0, iXLen %4, iXLen 0);
ret <vscale x 2 x double> %a ret <vscale x 2 x double> %a
} }
declare <vscale x 4 x double> @llvm.riscv.vfnmadd.nxv4f64.f64( declare <vscale x 4 x double> @llvm.riscv.vfnmadd.nxv4f64.f64(
<vscale x 4 x double>, <vscale x 4 x double>,
double, double,
<vscale x 4 x double>, <vscale x 4 x double>,
iXLen, iXLen, iXLen, iXLen);
iXLen);
define <vscale x 4 x double> @intrinsic_vfnmadd_vf_nxv4f64_f64_nxv4f64(<vscale x 4 x double> %0, double %1, <vscale x 4 x double> %2, iXLen %3) nounwind { define <vscale x 4 x double> @intrinsic_vfnmadd_vf_nxv4f64_f64_nxv4f64(<vscale x 4 x double> %0, double %1, <vscale x 4 x double> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfnmadd_vf_nxv4f64_f64_nxv4f64: ; CHECK-LABEL: intrinsic_vfnmadd_vf_nxv4f64_f64_nxv4f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, ma ; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, ma
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfnmadd.vf v8, fa0, v12 ; CHECK-NEXT: vfnmadd.vf v8, fa0, v12
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x double> @llvm.riscv.vfnmadd.nxv4f64.f64( %a = call <vscale x 4 x double> @llvm.riscv.vfnmadd.nxv4f64.f64(
<vscale x 4 x double> %0, <vscale x 4 x double> %0,
double %1, double %1,
<vscale x 4 x double> %2, <vscale x 4 x double> %2,
iXLen %3, iXLen 0) iXLen 0, iXLen %3, iXLen 0)
ret <vscale x 4 x double> %a ret <vscale x 4 x double> %a
} }
declare <vscale x 4 x double> @llvm.riscv.vfnmadd.mask.nxv4f64.f64( declare <vscale x 4 x double> @llvm.riscv.vfnmadd.mask.nxv4f64.f64(
<vscale x 4 x double>, <vscale x 4 x double>,
double, double,
<vscale x 4 x double>, <vscale x 4 x double>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
iXLen, iXLen); iXLen, iXLen, iXLen);
define <vscale x 4 x double> @intrinsic_vfnmadd_mask_vf_nxv4f64_f64_nxv4f64(<vscale x 4 x double> %0, double %1, <vscale x 4 x double> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind { define <vscale x 4 x double> @intrinsic_vfnmadd_mask_vf_nxv4f64_f64_nxv4f64(<vscale x 4 x double> %0, double %1, <vscale x 4 x double> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfnmadd_mask_vf_nxv4f64_f64_nxv4f64: ; CHECK-LABEL: intrinsic_vfnmadd_mask_vf_nxv4f64_f64_nxv4f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, mu
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfnmadd.vf v8, fa0, v12, v0.t ; CHECK-NEXT: vfnmadd.vf v8, fa0, v12, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x double> @llvm.riscv.vfnmadd.mask.nxv4f64.f64( %a = call <vscale x 4 x double> @llvm.riscv.vfnmadd.mask.nxv4f64.f64(
<vscale x 4 x double> %0, <vscale x 4 x double> %0,
double %1, double %1,
<vscale x 4 x double> %2, <vscale x 4 x double> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
iXLen %4, iXLen 0); iXLen 0, iXLen %4, iXLen 0);
ret <vscale x 4 x double> %a ret <vscale x 4 x double> %a
} }

llvm/test/CodeGen/RISCV/rvv/vfnmsac.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zfh,+experimental-zvfh \ ; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zfh,+experimental-zvfh \
; RUN: -verify-machineinstrs -target-abi=ilp32d | FileCheck %s ; RUN: -verify-machineinstrs -target-abi=ilp32d | FileCheck %s
; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zfh,+experimental-zvfh \ ; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zfh,+experimental-zvfh \
; RUN: -verify-machineinstrs -target-abi=lp64d | FileCheck %s ; RUN: -verify-machineinstrs -target-abi=lp64d | FileCheck %s
declare <vscale x 1 x half> @llvm.riscv.vfnmsac.nxv1f16.nxv1f16( declare <vscale x 1 x half> @llvm.riscv.vfnmsac.nxv1f16.nxv1f16(
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x half>, <vscale x 1 x half>,
iXLen, iXLen, iXLen, iXLen);
iXLen);
define <vscale x 1 x half> @intrinsic_vfnmsac_vv_nxv1f16_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, iXLen %3) nounwind { define <vscale x 1 x half> @intrinsic_vfnmsac_vv_nxv1f16_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfnmsac_vv_nxv1f16_nxv1f16_nxv1f16: ; CHECK-LABEL: intrinsic_vfnmsac_vv_nxv1f16_nxv1f16_nxv1f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, ma ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, ma
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfnmsac.vv v8, v9, v10 ; CHECK-NEXT: vfnmsac.vv v8, v9, v10
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x half> @llvm.riscv.vfnmsac.nxv1f16.nxv1f16( %a = call <vscale x 1 x half> @llvm.riscv.vfnmsac.nxv1f16.nxv1f16(
<vscale x 1 x half> %0, <vscale x 1 x half> %0,
<vscale x 1 x half> %1, <vscale x 1 x half> %1,
<vscale x 1 x half> %2, <vscale x 1 x half> %2,
iXLen %3, iXLen 0) iXLen 0, iXLen %3, iXLen 0)
ret <vscale x 1 x half> %a ret <vscale x 1 x half> %a
} }
declare <vscale x 1 x half> @llvm.riscv.vfnmsac.mask.nxv1f16.nxv1f16( declare <vscale x 1 x half> @llvm.riscv.vfnmsac.mask.nxv1f16.nxv1f16(
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
iXLen, iXLen); iXLen, iXLen, iXLen);
define <vscale x 1 x half> @intrinsic_vfnmsac_mask_vv_nxv1f16_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind { define <vscale x 1 x half> @intrinsic_vfnmsac_mask_vv_nxv1f16_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfnmsac_mask_vv_nxv1f16_nxv1f16_nxv1f16: ; CHECK-LABEL: intrinsic_vfnmsac_mask_vv_nxv1f16_nxv1f16_nxv1f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfnmsac.vv v8, v9, v10, v0.t ; CHECK-NEXT: vfnmsac.vv v8, v9, v10, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x half> @llvm.riscv.vfnmsac.mask.nxv1f16.nxv1f16( %a = call <vscale x 1 x half> @llvm.riscv.vfnmsac.mask.nxv1f16.nxv1f16(
<vscale x 1 x half> %0, <vscale x 1 x half> %0,
<vscale x 1 x half> %1, <vscale x 1 x half> %1,
<vscale x 1 x half> %2, <vscale x 1 x half> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
iXLen %4, iXLen 0); iXLen 0, iXLen %4, iXLen 0);
ret <vscale x 1 x half> %a ret <vscale x 1 x half> %a
} }
declare <vscale x 2 x half> @llvm.riscv.vfnmsac.nxv2f16.nxv2f16( declare <vscale x 2 x half> @llvm.riscv.vfnmsac.nxv2f16.nxv2f16(
<vscale x 2 x half>, <vscale x 2 x half>,
<vscale x 2 x half>, <vscale x 2 x half>,
<vscale x 2 x half>, <vscale x 2 x half>,
iXLen, iXLen, iXLen, iXLen);
iXLen);
define <vscale x 2 x half> @intrinsic_vfnmsac_vv_nxv2f16_nxv2f16_nxv2f16(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, iXLen %3) nounwind { define <vscale x 2 x half> @intrinsic_vfnmsac_vv_nxv2f16_nxv2f16_nxv2f16(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfnmsac_vv_nxv2f16_nxv2f16_nxv2f16: ; CHECK-LABEL: intrinsic_vfnmsac_vv_nxv2f16_nxv2f16_nxv2f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, ma ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, ma
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfnmsac.vv v8, v9, v10 ; CHECK-NEXT: vfnmsac.vv v8, v9, v10
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x half> @llvm.riscv.vfnmsac.nxv2f16.nxv2f16( %a = call <vscale x 2 x half> @llvm.riscv.vfnmsac.nxv2f16.nxv2f16(
<vscale x 2 x half> %0, <vscale x 2 x half> %0,
<vscale x 2 x half> %1, <vscale x 2 x half> %1,
<vscale x 2 x half> %2, <vscale x 2 x half> %2,
iXLen %3, iXLen 0) iXLen 0, iXLen %3, iXLen 0)
ret <vscale x 2 x half> %a ret <vscale x 2 x half> %a
} }
declare <vscale x 2 x half> @llvm.riscv.vfnmsac.mask.nxv2f16.nxv2f16( declare <vscale x 2 x half> @llvm.riscv.vfnmsac.mask.nxv2f16.nxv2f16(
<vscale x 2 x half>, <vscale x 2 x half>,
<vscale x 2 x half>, <vscale x 2 x half>,
<vscale x 2 x half>, <vscale x 2 x half>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
iXLen, iXLen); iXLen, iXLen, iXLen);
define <vscale x 2 x half> @intrinsic_vfnmsac_mask_vv_nxv2f16_nxv2f16_nxv2f16(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind { define <vscale x 2 x half> @intrinsic_vfnmsac_mask_vv_nxv2f16_nxv2f16_nxv2f16(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfnmsac_mask_vv_nxv2f16_nxv2f16_nxv2f16: ; CHECK-LABEL: intrinsic_vfnmsac_mask_vv_nxv2f16_nxv2f16_nxv2f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfnmsac.vv v8, v9, v10, v0.t ; CHECK-NEXT: vfnmsac.vv v8, v9, v10, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x half> @llvm.riscv.vfnmsac.mask.nxv2f16.nxv2f16( %a = call <vscale x 2 x half> @llvm.riscv.vfnmsac.mask.nxv2f16.nxv2f16(
<vscale x 2 x half> %0, <vscale x 2 x half> %0,
<vscale x 2 x half> %1, <vscale x 2 x half> %1,
<vscale x 2 x half> %2, <vscale x 2 x half> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
iXLen %4, iXLen 0); iXLen 0, iXLen %4, iXLen 0);
ret <vscale x 2 x half> %a ret <vscale x 2 x half> %a
} }
declare <vscale x 4 x half> @llvm.riscv.vfnmsac.nxv4f16.nxv4f16( declare <vscale x 4 x half> @llvm.riscv.vfnmsac.nxv4f16.nxv4f16(
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 4 x half>, <vscale x 4 x half>,
iXLen, iXLen, iXLen, iXLen);
iXLen);
define <vscale x 4 x half> @intrinsic_vfnmsac_vv_nxv4f16_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, iXLen %3) nounwind { define <vscale x 4 x half> @intrinsic_vfnmsac_vv_nxv4f16_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfnmsac_vv_nxv4f16_nxv4f16_nxv4f16: ; CHECK-LABEL: intrinsic_vfnmsac_vv_nxv4f16_nxv4f16_nxv4f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, ma ; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, ma
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfnmsac.vv v8, v9, v10 ; CHECK-NEXT: vfnmsac.vv v8, v9, v10
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x half> @llvm.riscv.vfnmsac.nxv4f16.nxv4f16( %a = call <vscale x 4 x half> @llvm.riscv.vfnmsac.nxv4f16.nxv4f16(
<vscale x 4 x half> %0, <vscale x 4 x half> %0,
<vscale x 4 x half> %1, <vscale x 4 x half> %1,
<vscale x 4 x half> %2, <vscale x 4 x half> %2,
iXLen %3, iXLen 0) iXLen 0, iXLen %3, iXLen 0)
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 4 x half> @llvm.riscv.vfnmsac.mask.nxv4f16.nxv4f16( declare <vscale x 4 x half> @llvm.riscv.vfnmsac.mask.nxv4f16.nxv4f16(
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
iXLen, iXLen); iXLen, iXLen, iXLen);
define <vscale x 4 x half> @intrinsic_vfnmsac_mask_vv_nxv4f16_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind { define <vscale x 4 x half> @intrinsic_vfnmsac_mask_vv_nxv4f16_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfnmsac_mask_vv_nxv4f16_nxv4f16_nxv4f16: ; CHECK-LABEL: intrinsic_vfnmsac_mask_vv_nxv4f16_nxv4f16_nxv4f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfnmsac.vv v8, v9, v10, v0.t ; CHECK-NEXT: vfnmsac.vv v8, v9, v10, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x half> @llvm.riscv.vfnmsac.mask.nxv4f16.nxv4f16( %a = call <vscale x 4 x half> @llvm.riscv.vfnmsac.mask.nxv4f16.nxv4f16(
<vscale x 4 x half> %0, <vscale x 4 x half> %0,
<vscale x 4 x half> %1, <vscale x 4 x half> %1,
<vscale x 4 x half> %2, <vscale x 4 x half> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
iXLen %4, iXLen 0); iXLen 0, iXLen %4, iXLen 0);
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 8 x half> @llvm.riscv.vfnmsac.nxv8f16.nxv8f16( declare <vscale x 8 x half> @llvm.riscv.vfnmsac.nxv8f16.nxv8f16(
<vscale x 8 x half>, <vscale x 8 x half>,
<vscale x 8 x half>, <vscale x 8 x half>,
<vscale x 8 x half>, <vscale x 8 x half>,
iXLen, iXLen, iXLen, iXLen);
iXLen);
define <vscale x 8 x half> @intrinsic_vfnmsac_vv_nxv8f16_nxv8f16_nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, iXLen %3) nounwind { define <vscale x 8 x half> @intrinsic_vfnmsac_vv_nxv8f16_nxv8f16_nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfnmsac_vv_nxv8f16_nxv8f16_nxv8f16: ; CHECK-LABEL: intrinsic_vfnmsac_vv_nxv8f16_nxv8f16_nxv8f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, ma ; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, ma
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfnmsac.vv v8, v10, v12 ; CHECK-NEXT: vfnmsac.vv v8, v10, v12
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x half> @llvm.riscv.vfnmsac.nxv8f16.nxv8f16( %a = call <vscale x 8 x half> @llvm.riscv.vfnmsac.nxv8f16.nxv8f16(
<vscale x 8 x half> %0, <vscale x 8 x half> %0,
<vscale x 8 x half> %1, <vscale x 8 x half> %1,
<vscale x 8 x half> %2, <vscale x 8 x half> %2,
iXLen %3, iXLen 0) iXLen 0, iXLen %3, iXLen 0)
ret <vscale x 8 x half> %a ret <vscale x 8 x half> %a
} }
declare <vscale x 8 x half> @llvm.riscv.vfnmsac.mask.nxv8f16.nxv8f16( declare <vscale x 8 x half> @llvm.riscv.vfnmsac.mask.nxv8f16.nxv8f16(
<vscale x 8 x half>, <vscale x 8 x half>,
<vscale x 8 x half>, <vscale x 8 x half>,
<vscale x 8 x half>, <vscale x 8 x half>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
iXLen, iXLen); iXLen, iXLen, iXLen);
define <vscale x 8 x half> @intrinsic_vfnmsac_mask_vv_nxv8f16_nxv8f16_nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind { define <vscale x 8 x half> @intrinsic_vfnmsac_mask_vv_nxv8f16_nxv8f16_nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfnmsac_mask_vv_nxv8f16_nxv8f16_nxv8f16: ; CHECK-LABEL: intrinsic_vfnmsac_mask_vv_nxv8f16_nxv8f16_nxv8f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, mu
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfnmsac.vv v8, v10, v12, v0.t ; CHECK-NEXT: vfnmsac.vv v8, v10, v12, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x half> @llvm.riscv.vfnmsac.mask.nxv8f16.nxv8f16( %a = call <vscale x 8 x half> @llvm.riscv.vfnmsac.mask.nxv8f16.nxv8f16(
<vscale x 8 x half> %0, <vscale x 8 x half> %0,
<vscale x 8 x half> %1, <vscale x 8 x half> %1,
<vscale x 8 x half> %2, <vscale x 8 x half> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
iXLen %4, iXLen 0); iXLen 0, iXLen %4, iXLen 0);
ret <vscale x 8 x half> %a ret <vscale x 8 x half> %a
} }
declare <vscale x 16 x half> @llvm.riscv.vfnmsac.nxv16f16.nxv16f16( declare <vscale x 16 x half> @llvm.riscv.vfnmsac.nxv16f16.nxv16f16(
<vscale x 16 x half>, <vscale x 16 x half>,
<vscale x 16 x half>, <vscale x 16 x half>,
<vscale x 16 x half>, <vscale x 16 x half>,
iXLen, iXLen, iXLen, iXLen);
iXLen);
define <vscale x 16 x half> @intrinsic_vfnmsac_vv_nxv16f16_nxv16f16_nxv16f16(<vscale x 16 x half> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %2, iXLen %3) nounwind { define <vscale x 16 x half> @intrinsic_vfnmsac_vv_nxv16f16_nxv16f16_nxv16f16(<vscale x 16 x half> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfnmsac_vv_nxv16f16_nxv16f16_nxv16f16: ; CHECK-LABEL: intrinsic_vfnmsac_vv_nxv16f16_nxv16f16_nxv16f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, ma ; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, ma
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfnmsac.vv v8, v12, v16 ; CHECK-NEXT: vfnmsac.vv v8, v12, v16
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x half> @llvm.riscv.vfnmsac.nxv16f16.nxv16f16( %a = call <vscale x 16 x half> @llvm.riscv.vfnmsac.nxv16f16.nxv16f16(
<vscale x 16 x half> %0, <vscale x 16 x half> %0,
<vscale x 16 x half> %1, <vscale x 16 x half> %1,
<vscale x 16 x half> %2, <vscale x 16 x half> %2,
iXLen %3, iXLen 0) iXLen 0, iXLen %3, iXLen 0)
ret <vscale x 16 x half> %a ret <vscale x 16 x half> %a
} }
declare <vscale x 16 x half> @llvm.riscv.vfnmsac.mask.nxv16f16.nxv16f16( declare <vscale x 16 x half> @llvm.riscv.vfnmsac.mask.nxv16f16.nxv16f16(
<vscale x 16 x half>, <vscale x 16 x half>,
<vscale x 16 x half>, <vscale x 16 x half>,
<vscale x 16 x half>, <vscale x 16 x half>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
iXLen, iXLen); iXLen, iXLen, iXLen);
define <vscale x 16 x half> @intrinsic_vfnmsac_mask_vv_nxv16f16_nxv16f16_nxv16f16(<vscale x 16 x half> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind { define <vscale x 16 x half> @intrinsic_vfnmsac_mask_vv_nxv16f16_nxv16f16_nxv16f16(<vscale x 16 x half> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfnmsac_mask_vv_nxv16f16_nxv16f16_nxv16f16: ; CHECK-LABEL: intrinsic_vfnmsac_mask_vv_nxv16f16_nxv16f16_nxv16f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfnmsac.vv v8, v12, v16, v0.t ; CHECK-NEXT: vfnmsac.vv v8, v12, v16, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x half> @llvm.riscv.vfnmsac.mask.nxv16f16.nxv16f16( %a = call <vscale x 16 x half> @llvm.riscv.vfnmsac.mask.nxv16f16.nxv16f16(
<vscale x 16 x half> %0, <vscale x 16 x half> %0,
<vscale x 16 x half> %1, <vscale x 16 x half> %1,
<vscale x 16 x half> %2, <vscale x 16 x half> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
iXLen %4, iXLen 0); iXLen 0, iXLen %4, iXLen 0);
ret <vscale x 16 x half> %a ret <vscale x 16 x half> %a
} }
declare <vscale x 1 x float> @llvm.riscv.vfnmsac.nxv1f32.nxv1f32( declare <vscale x 1 x float> @llvm.riscv.vfnmsac.nxv1f32.nxv1f32(
<vscale x 1 x float>, <vscale x 1 x float>,
<vscale x 1 x float>, <vscale x 1 x float>,
<vscale x 1 x float>, <vscale x 1 x float>,
iXLen, iXLen, iXLen, iXLen);
iXLen);
define <vscale x 1 x float> @intrinsic_vfnmsac_vv_nxv1f32_nxv1f32_nxv1f32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, iXLen %3) nounwind { define <vscale x 1 x float> @intrinsic_vfnmsac_vv_nxv1f32_nxv1f32_nxv1f32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfnmsac_vv_nxv1f32_nxv1f32_nxv1f32: ; CHECK-LABEL: intrinsic_vfnmsac_vv_nxv1f32_nxv1f32_nxv1f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, ma ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, ma
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfnmsac.vv v8, v9, v10 ; CHECK-NEXT: vfnmsac.vv v8, v9, v10
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x float> @llvm.riscv.vfnmsac.nxv1f32.nxv1f32( %a = call <vscale x 1 x float> @llvm.riscv.vfnmsac.nxv1f32.nxv1f32(
<vscale x 1 x float> %0, <vscale x 1 x float> %0,
<vscale x 1 x float> %1, <vscale x 1 x float> %1,
<vscale x 1 x float> %2, <vscale x 1 x float> %2,
iXLen %3, iXLen 0) iXLen 0, iXLen %3, iXLen 0)
ret <vscale x 1 x float> %a ret <vscale x 1 x float> %a
} }
declare <vscale x 1 x float> @llvm.riscv.vfnmsac.mask.nxv1f32.nxv1f32( declare <vscale x 1 x float> @llvm.riscv.vfnmsac.mask.nxv1f32.nxv1f32(
<vscale x 1 x float>, <vscale x 1 x float>,
<vscale x 1 x float>, <vscale x 1 x float>,
<vscale x 1 x float>, <vscale x 1 x float>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
iXLen, iXLen); iXLen, iXLen, iXLen);
define <vscale x 1 x float> @intrinsic_vfnmsac_mask_vv_nxv1f32_nxv1f32_nxv1f32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind { define <vscale x 1 x float> @intrinsic_vfnmsac_mask_vv_nxv1f32_nxv1f32_nxv1f32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfnmsac_mask_vv_nxv1f32_nxv1f32_nxv1f32: ; CHECK-LABEL: intrinsic_vfnmsac_mask_vv_nxv1f32_nxv1f32_nxv1f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfnmsac.vv v8, v9, v10, v0.t ; CHECK-NEXT: vfnmsac.vv v8, v9, v10, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x float> @llvm.riscv.vfnmsac.mask.nxv1f32.nxv1f32( %a = call <vscale x 1 x float> @llvm.riscv.vfnmsac.mask.nxv1f32.nxv1f32(
<vscale x 1 x float> %0, <vscale x 1 x float> %0,
<vscale x 1 x float> %1, <vscale x 1 x float> %1,
<vscale x 1 x float> %2, <vscale x 1 x float> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
iXLen %4, iXLen 0); iXLen 0, iXLen %4, iXLen 0);
ret <vscale x 1 x float> %a ret <vscale x 1 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vfnmsac.nxv2f32.nxv2f32( declare <vscale x 2 x float> @llvm.riscv.vfnmsac.nxv2f32.nxv2f32(
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 2 x float>, <vscale x 2 x float>,
iXLen, iXLen, iXLen, iXLen);
iXLen);
define <vscale x 2 x float> @intrinsic_vfnmsac_vv_nxv2f32_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, iXLen %3) nounwind { define <vscale x 2 x float> @intrinsic_vfnmsac_vv_nxv2f32_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfnmsac_vv_nxv2f32_nxv2f32_nxv2f32: ; CHECK-LABEL: intrinsic_vfnmsac_vv_nxv2f32_nxv2f32_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, ma ; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, ma
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfnmsac.vv v8, v9, v10 ; CHECK-NEXT: vfnmsac.vv v8, v9, v10
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfnmsac.nxv2f32.nxv2f32( %a = call <vscale x 2 x float> @llvm.riscv.vfnmsac.nxv2f32.nxv2f32(
<vscale x 2 x float> %0, <vscale x 2 x float> %0,
<vscale x 2 x float> %1, <vscale x 2 x float> %1,
<vscale x 2 x float> %2, <vscale x 2 x float> %2,
iXLen %3, iXLen 0) iXLen 0, iXLen %3, iXLen 0)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vfnmsac.mask.nxv2f32.nxv2f32( declare <vscale x 2 x float> @llvm.riscv.vfnmsac.mask.nxv2f32.nxv2f32(
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
iXLen, iXLen); iXLen, iXLen, iXLen);
define <vscale x 2 x float> @intrinsic_vfnmsac_mask_vv_nxv2f32_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind { define <vscale x 2 x float> @intrinsic_vfnmsac_mask_vv_nxv2f32_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfnmsac_mask_vv_nxv2f32_nxv2f32_nxv2f32: ; CHECK-LABEL: intrinsic_vfnmsac_mask_vv_nxv2f32_nxv2f32_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfnmsac.vv v8, v9, v10, v0.t ; CHECK-NEXT: vfnmsac.vv v8, v9, v10, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfnmsac.mask.nxv2f32.nxv2f32( %a = call <vscale x 2 x float> @llvm.riscv.vfnmsac.mask.nxv2f32.nxv2f32(
<vscale x 2 x float> %0, <vscale x 2 x float> %0,
<vscale x 2 x float> %1, <vscale x 2 x float> %1,
<vscale x 2 x float> %2, <vscale x 2 x float> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
iXLen %4, iXLen 0); iXLen 0, iXLen %4, iXLen 0);
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 4 x float> @llvm.riscv.vfnmsac.nxv4f32.nxv4f32( declare <vscale x 4 x float> @llvm.riscv.vfnmsac.nxv4f32.nxv4f32(
<vscale x 4 x float>, <vscale x 4 x float>,
<vscale x 4 x float>, <vscale x 4 x float>,
<vscale x 4 x float>, <vscale x 4 x float>,
iXLen, iXLen, iXLen, iXLen);
iXLen);
define <vscale x 4 x float> @intrinsic_vfnmsac_vv_nxv4f32_nxv4f32_nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, <vscale x 4 x float> %2, iXLen %3) nounwind { define <vscale x 4 x float> @intrinsic_vfnmsac_vv_nxv4f32_nxv4f32_nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, <vscale x 4 x float> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfnmsac_vv_nxv4f32_nxv4f32_nxv4f32: ; CHECK-LABEL: intrinsic_vfnmsac_vv_nxv4f32_nxv4f32_nxv4f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, ma ; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, ma
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfnmsac.vv v8, v10, v12 ; CHECK-NEXT: vfnmsac.vv v8, v10, v12
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x float> @llvm.riscv.vfnmsac.nxv4f32.nxv4f32( %a = call <vscale x 4 x float> @llvm.riscv.vfnmsac.nxv4f32.nxv4f32(
<vscale x 4 x float> %0, <vscale x 4 x float> %0,
<vscale x 4 x float> %1, <vscale x 4 x float> %1,
<vscale x 4 x float> %2, <vscale x 4 x float> %2,
iXLen %3, iXLen 0) iXLen 0, iXLen %3, iXLen 0)
ret <vscale x 4 x float> %a ret <vscale x 4 x float> %a
} }
declare <vscale x 4 x float> @llvm.riscv.vfnmsac.mask.nxv4f32.nxv4f32( declare <vscale x 4 x float> @llvm.riscv.vfnmsac.mask.nxv4f32.nxv4f32(
<vscale x 4 x float>, <vscale x 4 x float>,
<vscale x 4 x float>, <vscale x 4 x float>,
<vscale x 4 x float>, <vscale x 4 x float>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
iXLen, iXLen); iXLen, iXLen, iXLen);
define <vscale x 4 x float> @intrinsic_vfnmsac_mask_vv_nxv4f32_nxv4f32_nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, <vscale x 4 x float> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind { define <vscale x 4 x float> @intrinsic_vfnmsac_mask_vv_nxv4f32_nxv4f32_nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, <vscale x 4 x float> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfnmsac_mask_vv_nxv4f32_nxv4f32_nxv4f32: ; CHECK-LABEL: intrinsic_vfnmsac_mask_vv_nxv4f32_nxv4f32_nxv4f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfnmsac.vv v8, v10, v12, v0.t ; CHECK-NEXT: vfnmsac.vv v8, v10, v12, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x float> @llvm.riscv.vfnmsac.mask.nxv4f32.nxv4f32( %a = call <vscale x 4 x float> @llvm.riscv.vfnmsac.mask.nxv4f32.nxv4f32(
<vscale x 4 x float> %0, <vscale x 4 x float> %0,
<vscale x 4 x float> %1, <vscale x 4 x float> %1,
<vscale x 4 x float> %2, <vscale x 4 x float> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
iXLen %4, iXLen 0); iXLen 0, iXLen %4, iXLen 0);
ret <vscale x 4 x float> %a ret <vscale x 4 x float> %a
} }
declare <vscale x 8 x float> @llvm.riscv.vfnmsac.nxv8f32.nxv8f32( declare <vscale x 8 x float> @llvm.riscv.vfnmsac.nxv8f32.nxv8f32(
<vscale x 8 x float>, <vscale x 8 x float>,
<vscale x 8 x float>, <vscale x 8 x float>,
<vscale x 8 x float>, <vscale x 8 x float>,
iXLen, iXLen, iXLen, iXLen);
iXLen);
define <vscale x 8 x float> @intrinsic_vfnmsac_vv_nxv8f32_nxv8f32_nxv8f32(<vscale x 8 x float> %0, <vscale x 8 x float> %1, <vscale x 8 x float> %2, iXLen %3) nounwind { define <vscale x 8 x float> @intrinsic_vfnmsac_vv_nxv8f32_nxv8f32_nxv8f32(<vscale x 8 x float> %0, <vscale x 8 x float> %1, <vscale x 8 x float> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfnmsac_vv_nxv8f32_nxv8f32_nxv8f32: ; CHECK-LABEL: intrinsic_vfnmsac_vv_nxv8f32_nxv8f32_nxv8f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, ma ; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, ma
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfnmsac.vv v8, v12, v16 ; CHECK-NEXT: vfnmsac.vv v8, v12, v16
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x float> @llvm.riscv.vfnmsac.nxv8f32.nxv8f32( %a = call <vscale x 8 x float> @llvm.riscv.vfnmsac.nxv8f32.nxv8f32(
<vscale x 8 x float> %0, <vscale x 8 x float> %0,
<vscale x 8 x float> %1, <vscale x 8 x float> %1,
<vscale x 8 x float> %2, <vscale x 8 x float> %2,
iXLen %3, iXLen 0) iXLen 0, iXLen %3, iXLen 0)
ret <vscale x 8 x float> %a ret <vscale x 8 x float> %a
} }
declare <vscale x 8 x float> @llvm.riscv.vfnmsac.mask.nxv8f32.nxv8f32( declare <vscale x 8 x float> @llvm.riscv.vfnmsac.mask.nxv8f32.nxv8f32(
<vscale x 8 x float>, <vscale x 8 x float>,
<vscale x 8 x float>, <vscale x 8 x float>,
<vscale x 8 x float>, <vscale x 8 x float>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
iXLen, iXLen); iXLen, iXLen, iXLen);
define <vscale x 8 x float> @intrinsic_vfnmsac_mask_vv_nxv8f32_nxv8f32_nxv8f32(<vscale x 8 x float> %0, <vscale x 8 x float> %1, <vscale x 8 x float> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind { define <vscale x 8 x float> @intrinsic_vfnmsac_mask_vv_nxv8f32_nxv8f32_nxv8f32(<vscale x 8 x float> %0, <vscale x 8 x float> %1, <vscale x 8 x float> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfnmsac_mask_vv_nxv8f32_nxv8f32_nxv8f32: ; CHECK-LABEL: intrinsic_vfnmsac_mask_vv_nxv8f32_nxv8f32_nxv8f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfnmsac.vv v8, v12, v16, v0.t ; CHECK-NEXT: vfnmsac.vv v8, v12, v16, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x float> @llvm.riscv.vfnmsac.mask.nxv8f32.nxv8f32( %a = call <vscale x 8 x float> @llvm.riscv.vfnmsac.mask.nxv8f32.nxv8f32(
<vscale x 8 x float> %0, <vscale x 8 x float> %0,
<vscale x 8 x float> %1, <vscale x 8 x float> %1,
<vscale x 8 x float> %2, <vscale x 8 x float> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
iXLen %4, iXLen 0); iXLen 0, iXLen %4, iXLen 0);
ret <vscale x 8 x float> %a ret <vscale x 8 x float> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vfnmsac.nxv1f64.nxv1f64( declare <vscale x 1 x double> @llvm.riscv.vfnmsac.nxv1f64.nxv1f64(
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 1 x double>, <vscale x 1 x double>,
iXLen, iXLen, iXLen, iXLen);
iXLen);
define <vscale x 1 x double> @intrinsic_vfnmsac_vv_nxv1f64_nxv1f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 1 x double> %1, <vscale x 1 x double> %2, iXLen %3) nounwind { define <vscale x 1 x double> @intrinsic_vfnmsac_vv_nxv1f64_nxv1f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 1 x double> %1, <vscale x 1 x double> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfnmsac_vv_nxv1f64_nxv1f64_nxv1f64: ; CHECK-LABEL: intrinsic_vfnmsac_vv_nxv1f64_nxv1f64_nxv1f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, ma ; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, ma
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfnmsac.vv v8, v9, v10 ; CHECK-NEXT: vfnmsac.vv v8, v9, v10
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfnmsac.nxv1f64.nxv1f64( %a = call <vscale x 1 x double> @llvm.riscv.vfnmsac.nxv1f64.nxv1f64(
<vscale x 1 x double> %0, <vscale x 1 x double> %0,
<vscale x 1 x double> %1, <vscale x 1 x double> %1,
<vscale x 1 x double> %2, <vscale x 1 x double> %2,
iXLen %3, iXLen 0) iXLen 0, iXLen %3, iXLen 0)
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vfnmsac.mask.nxv1f64.nxv1f64( declare <vscale x 1 x double> @llvm.riscv.vfnmsac.mask.nxv1f64.nxv1f64(
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
iXLen, iXLen); iXLen, iXLen, iXLen);
define <vscale x 1 x double> @intrinsic_vfnmsac_mask_vv_nxv1f64_nxv1f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 1 x double> %1, <vscale x 1 x double> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind { define <vscale x 1 x double> @intrinsic_vfnmsac_mask_vv_nxv1f64_nxv1f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 1 x double> %1, <vscale x 1 x double> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfnmsac_mask_vv_nxv1f64_nxv1f64_nxv1f64: ; CHECK-LABEL: intrinsic_vfnmsac_mask_vv_nxv1f64_nxv1f64_nxv1f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, mu
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfnmsac.vv v8, v9, v10, v0.t ; CHECK-NEXT: vfnmsac.vv v8, v9, v10, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfnmsac.mask.nxv1f64.nxv1f64( %a = call <vscale x 1 x double> @llvm.riscv.vfnmsac.mask.nxv1f64.nxv1f64(
<vscale x 1 x double> %0, <vscale x 1 x double> %0,
<vscale x 1 x double> %1, <vscale x 1 x double> %1,
<vscale x 1 x double> %2, <vscale x 1 x double> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
iXLen %4, iXLen 0); iXLen 0, iXLen %4, iXLen 0);
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 2 x double> @llvm.riscv.vfnmsac.nxv2f64.nxv2f64( declare <vscale x 2 x double> @llvm.riscv.vfnmsac.nxv2f64.nxv2f64(
<vscale x 2 x double>, <vscale x 2 x double>,
<vscale x 2 x double>, <vscale x 2 x double>,
<vscale x 2 x double>, <vscale x 2 x double>,
iXLen, iXLen, iXLen, iXLen);
iXLen);
define <vscale x 2 x double> @intrinsic_vfnmsac_vv_nxv2f64_nxv2f64_nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1, <vscale x 2 x double> %2, iXLen %3) nounwind { define <vscale x 2 x double> @intrinsic_vfnmsac_vv_nxv2f64_nxv2f64_nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1, <vscale x 2 x double> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfnmsac_vv_nxv2f64_nxv2f64_nxv2f64: ; CHECK-LABEL: intrinsic_vfnmsac_vv_nxv2f64_nxv2f64_nxv2f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, ma ; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, ma
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfnmsac.vv v8, v10, v12 ; CHECK-NEXT: vfnmsac.vv v8, v10, v12
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x double> @llvm.riscv.vfnmsac.nxv2f64.nxv2f64( %a = call <vscale x 2 x double> @llvm.riscv.vfnmsac.nxv2f64.nxv2f64(
<vscale x 2 x double> %0, <vscale x 2 x double> %0,
<vscale x 2 x double> %1, <vscale x 2 x double> %1,
<vscale x 2 x double> %2, <vscale x 2 x double> %2,
iXLen %3, iXLen 0) iXLen 0, iXLen %3, iXLen 0)
ret <vscale x 2 x double> %a ret <vscale x 2 x double> %a
} }
declare <vscale x 2 x double> @llvm.riscv.vfnmsac.mask.nxv2f64.nxv2f64( declare <vscale x 2 x double> @llvm.riscv.vfnmsac.mask.nxv2f64.nxv2f64(
<vscale x 2 x double>, <vscale x 2 x double>,
<vscale x 2 x double>, <vscale x 2 x double>,
<vscale x 2 x double>, <vscale x 2 x double>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
iXLen, iXLen); iXLen, iXLen, iXLen);
define <vscale x 2 x double> @intrinsic_vfnmsac_mask_vv_nxv2f64_nxv2f64_nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1, <vscale x 2 x double> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind { define <vscale x 2 x double> @intrinsic_vfnmsac_mask_vv_nxv2f64_nxv2f64_nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1, <vscale x 2 x double> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfnmsac_mask_vv_nxv2f64_nxv2f64_nxv2f64: ; CHECK-LABEL: intrinsic_vfnmsac_mask_vv_nxv2f64_nxv2f64_nxv2f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, mu
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfnmsac.vv v8, v10, v12, v0.t ; CHECK-NEXT: vfnmsac.vv v8, v10, v12, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x double> @llvm.riscv.vfnmsac.mask.nxv2f64.nxv2f64( %a = call <vscale x 2 x double> @llvm.riscv.vfnmsac.mask.nxv2f64.nxv2f64(
<vscale x 2 x double> %0, <vscale x 2 x double> %0,
<vscale x 2 x double> %1, <vscale x 2 x double> %1,
<vscale x 2 x double> %2, <vscale x 2 x double> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
iXLen %4, iXLen 0); iXLen 0, iXLen %4, iXLen 0);
ret <vscale x 2 x double> %a ret <vscale x 2 x double> %a
} }
declare <vscale x 4 x double> @llvm.riscv.vfnmsac.nxv4f64.nxv4f64( declare <vscale x 4 x double> @llvm.riscv.vfnmsac.nxv4f64.nxv4f64(
<vscale x 4 x double>, <vscale x 4 x double>,
<vscale x 4 x double>, <vscale x 4 x double>,
<vscale x 4 x double>, <vscale x 4 x double>,
iXLen, iXLen, iXLen, iXLen);
iXLen);
define <vscale x 4 x double> @intrinsic_vfnmsac_vv_nxv4f64_nxv4f64_nxv4f64(<vscale x 4 x double> %0, <vscale x 4 x double> %1, <vscale x 4 x double> %2, iXLen %3) nounwind { define <vscale x 4 x double> @intrinsic_vfnmsac_vv_nxv4f64_nxv4f64_nxv4f64(<vscale x 4 x double> %0, <vscale x 4 x double> %1, <vscale x 4 x double> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfnmsac_vv_nxv4f64_nxv4f64_nxv4f64: ; CHECK-LABEL: intrinsic_vfnmsac_vv_nxv4f64_nxv4f64_nxv4f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, ma ; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, ma
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfnmsac.vv v8, v12, v16 ; CHECK-NEXT: vfnmsac.vv v8, v12, v16
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x double> @llvm.riscv.vfnmsac.nxv4f64.nxv4f64( %a = call <vscale x 4 x double> @llvm.riscv.vfnmsac.nxv4f64.nxv4f64(
<vscale x 4 x double> %0, <vscale x 4 x double> %0,
<vscale x 4 x double> %1, <vscale x 4 x double> %1,
<vscale x 4 x double> %2, <vscale x 4 x double> %2,
iXLen %3, iXLen 0) iXLen 0, iXLen %3, iXLen 0)
ret <vscale x 4 x double> %a ret <vscale x 4 x double> %a
} }
declare <vscale x 4 x double> @llvm.riscv.vfnmsac.mask.nxv4f64.nxv4f64( declare <vscale x 4 x double> @llvm.riscv.vfnmsac.mask.nxv4f64.nxv4f64(
<vscale x 4 x double>, <vscale x 4 x double>,
<vscale x 4 x double>, <vscale x 4 x double>,
<vscale x 4 x double>, <vscale x 4 x double>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
iXLen, iXLen); iXLen, iXLen, iXLen);
define <vscale x 4 x double> @intrinsic_vfnmsac_mask_vv_nxv4f64_nxv4f64_nxv4f64(<vscale x 4 x double> %0, <vscale x 4 x double> %1, <vscale x 4 x double> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind { define <vscale x 4 x double> @intrinsic_vfnmsac_mask_vv_nxv4f64_nxv4f64_nxv4f64(<vscale x 4 x double> %0, <vscale x 4 x double> %1, <vscale x 4 x double> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfnmsac_mask_vv_nxv4f64_nxv4f64_nxv4f64: ; CHECK-LABEL: intrinsic_vfnmsac_mask_vv_nxv4f64_nxv4f64_nxv4f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, mu
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfnmsac.vv v8, v12, v16, v0.t ; CHECK-NEXT: vfnmsac.vv v8, v12, v16, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x double> @llvm.riscv.vfnmsac.mask.nxv4f64.nxv4f64( %a = call <vscale x 4 x double> @llvm.riscv.vfnmsac.mask.nxv4f64.nxv4f64(
<vscale x 4 x double> %0, <vscale x 4 x double> %0,
<vscale x 4 x double> %1, <vscale x 4 x double> %1,
<vscale x 4 x double> %2, <vscale x 4 x double> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
iXLen %4, iXLen 0); iXLen 0, iXLen %4, iXLen 0);
ret <vscale x 4 x double> %a ret <vscale x 4 x double> %a
} }
declare <vscale x 1 x half> @llvm.riscv.vfnmsac.nxv1f16.f16( declare <vscale x 1 x half> @llvm.riscv.vfnmsac.nxv1f16.f16(
<vscale x 1 x half>, <vscale x 1 x half>,
half, half,
<vscale x 1 x half>, <vscale x 1 x half>,
iXLen, iXLen, iXLen, iXLen);
iXLen);
define <vscale x 1 x half> @intrinsic_vfnmsac_vf_nxv1f16_f16_nxv1f16(<vscale x 1 x half> %0, half %1, <vscale x 1 x half> %2, iXLen %3) nounwind { define <vscale x 1 x half> @intrinsic_vfnmsac_vf_nxv1f16_f16_nxv1f16(<vscale x 1 x half> %0, half %1, <vscale x 1 x half> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfnmsac_vf_nxv1f16_f16_nxv1f16: ; CHECK-LABEL: intrinsic_vfnmsac_vf_nxv1f16_f16_nxv1f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, ma ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, ma
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfnmsac.vf v8, fa0, v9 ; CHECK-NEXT: vfnmsac.vf v8, fa0, v9
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x half> @llvm.riscv.vfnmsac.nxv1f16.f16( %a = call <vscale x 1 x half> @llvm.riscv.vfnmsac.nxv1f16.f16(
<vscale x 1 x half> %0, <vscale x 1 x half> %0,
half %1, half %1,
<vscale x 1 x half> %2, <vscale x 1 x half> %2,
iXLen %3, iXLen 0) iXLen 0, iXLen %3, iXLen 0)
ret <vscale x 1 x half> %a ret <vscale x 1 x half> %a
} }
declare <vscale x 1 x half> @llvm.riscv.vfnmsac.mask.nxv1f16.f16( declare <vscale x 1 x half> @llvm.riscv.vfnmsac.mask.nxv1f16.f16(
<vscale x 1 x half>, <vscale x 1 x half>,
half, half,
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
iXLen, iXLen); iXLen, iXLen, iXLen);
define <vscale x 1 x half> @intrinsic_vfnmsac_mask_vf_nxv1f16_f16_nxv1f16(<vscale x 1 x half> %0, half %1, <vscale x 1 x half> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind { define <vscale x 1 x half> @intrinsic_vfnmsac_mask_vf_nxv1f16_f16_nxv1f16(<vscale x 1 x half> %0, half %1, <vscale x 1 x half> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfnmsac_mask_vf_nxv1f16_f16_nxv1f16: ; CHECK-LABEL: intrinsic_vfnmsac_mask_vf_nxv1f16_f16_nxv1f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfnmsac.vf v8, fa0, v9, v0.t ; CHECK-NEXT: vfnmsac.vf v8, fa0, v9, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x half> @llvm.riscv.vfnmsac.mask.nxv1f16.f16( %a = call <vscale x 1 x half> @llvm.riscv.vfnmsac.mask.nxv1f16.f16(
<vscale x 1 x half> %0, <vscale x 1 x half> %0,
half %1, half %1,
<vscale x 1 x half> %2, <vscale x 1 x half> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
iXLen %4, iXLen 0); iXLen 0, iXLen %4, iXLen 0);
ret <vscale x 1 x half> %a ret <vscale x 1 x half> %a
} }
declare <vscale x 2 x half> @llvm.riscv.vfnmsac.nxv2f16.f16( declare <vscale x 2 x half> @llvm.riscv.vfnmsac.nxv2f16.f16(
<vscale x 2 x half>, <vscale x 2 x half>,
half, half,
<vscale x 2 x half>, <vscale x 2 x half>,
iXLen, iXLen, iXLen, iXLen);
iXLen);
define <vscale x 2 x half> @intrinsic_vfnmsac_vf_nxv2f16_f16_nxv2f16(<vscale x 2 x half> %0, half %1, <vscale x 2 x half> %2, iXLen %3) nounwind { define <vscale x 2 x half> @intrinsic_vfnmsac_vf_nxv2f16_f16_nxv2f16(<vscale x 2 x half> %0, half %1, <vscale x 2 x half> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfnmsac_vf_nxv2f16_f16_nxv2f16: ; CHECK-LABEL: intrinsic_vfnmsac_vf_nxv2f16_f16_nxv2f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, ma ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, ma
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfnmsac.vf v8, fa0, v9 ; CHECK-NEXT: vfnmsac.vf v8, fa0, v9
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x half> @llvm.riscv.vfnmsac.nxv2f16.f16( %a = call <vscale x 2 x half> @llvm.riscv.vfnmsac.nxv2f16.f16(
<vscale x 2 x half> %0, <vscale x 2 x half> %0,
half %1, half %1,
<vscale x 2 x half> %2, <vscale x 2 x half> %2,
iXLen %3, iXLen 0) iXLen 0, iXLen %3, iXLen 0)
ret <vscale x 2 x half> %a ret <vscale x 2 x half> %a
} }
declare <vscale x 2 x half> @llvm.riscv.vfnmsac.mask.nxv2f16.f16( declare <vscale x 2 x half> @llvm.riscv.vfnmsac.mask.nxv2f16.f16(
<vscale x 2 x half>, <vscale x 2 x half>,
half, half,
<vscale x 2 x half>, <vscale x 2 x half>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
iXLen, iXLen); iXLen, iXLen, iXLen);
define <vscale x 2 x half> @intrinsic_vfnmsac_mask_vf_nxv2f16_f16_nxv2f16(<vscale x 2 x half> %0, half %1, <vscale x 2 x half> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind { define <vscale x 2 x half> @intrinsic_vfnmsac_mask_vf_nxv2f16_f16_nxv2f16(<vscale x 2 x half> %0, half %1, <vscale x 2 x half> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfnmsac_mask_vf_nxv2f16_f16_nxv2f16: ; CHECK-LABEL: intrinsic_vfnmsac_mask_vf_nxv2f16_f16_nxv2f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfnmsac.vf v8, fa0, v9, v0.t ; CHECK-NEXT: vfnmsac.vf v8, fa0, v9, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x half> @llvm.riscv.vfnmsac.mask.nxv2f16.f16( %a = call <vscale x 2 x half> @llvm.riscv.vfnmsac.mask.nxv2f16.f16(
<vscale x 2 x half> %0, <vscale x 2 x half> %0,
half %1, half %1,
<vscale x 2 x half> %2, <vscale x 2 x half> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
iXLen %4, iXLen 0); iXLen 0, iXLen %4, iXLen 0);
ret <vscale x 2 x half> %a ret <vscale x 2 x half> %a
} }
declare <vscale x 4 x half> @llvm.riscv.vfnmsac.nxv4f16.f16( declare <vscale x 4 x half> @llvm.riscv.vfnmsac.nxv4f16.f16(
<vscale x 4 x half>, <vscale x 4 x half>,
half, half,
<vscale x 4 x half>, <vscale x 4 x half>,
iXLen, iXLen, iXLen, iXLen);
iXLen);
define <vscale x 4 x half> @intrinsic_vfnmsac_vf_nxv4f16_f16_nxv4f16(<vscale x 4 x half> %0, half %1, <vscale x 4 x half> %2, iXLen %3) nounwind { define <vscale x 4 x half> @intrinsic_vfnmsac_vf_nxv4f16_f16_nxv4f16(<vscale x 4 x half> %0, half %1, <vscale x 4 x half> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfnmsac_vf_nxv4f16_f16_nxv4f16: ; CHECK-LABEL: intrinsic_vfnmsac_vf_nxv4f16_f16_nxv4f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, ma ; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, ma
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfnmsac.vf v8, fa0, v9 ; CHECK-NEXT: vfnmsac.vf v8, fa0, v9
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x half> @llvm.riscv.vfnmsac.nxv4f16.f16( %a = call <vscale x 4 x half> @llvm.riscv.vfnmsac.nxv4f16.f16(
<vscale x 4 x half> %0, <vscale x 4 x half> %0,
half %1, half %1,
<vscale x 4 x half> %2, <vscale x 4 x half> %2,
iXLen %3, iXLen 0) iXLen 0, iXLen %3, iXLen 0)
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 4 x half> @llvm.riscv.vfnmsac.mask.nxv4f16.f16( declare <vscale x 4 x half> @llvm.riscv.vfnmsac.mask.nxv4f16.f16(
<vscale x 4 x half>, <vscale x 4 x half>,
half, half,
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
iXLen, iXLen); iXLen, iXLen, iXLen);
define <vscale x 4 x half> @intrinsic_vfnmsac_mask_vf_nxv4f16_f16_nxv4f16(<vscale x 4 x half> %0, half %1, <vscale x 4 x half> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind { define <vscale x 4 x half> @intrinsic_vfnmsac_mask_vf_nxv4f16_f16_nxv4f16(<vscale x 4 x half> %0, half %1, <vscale x 4 x half> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfnmsac_mask_vf_nxv4f16_f16_nxv4f16: ; CHECK-LABEL: intrinsic_vfnmsac_mask_vf_nxv4f16_f16_nxv4f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfnmsac.vf v8, fa0, v9, v0.t ; CHECK-NEXT: vfnmsac.vf v8, fa0, v9, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x half> @llvm.riscv.vfnmsac.mask.nxv4f16.f16( %a = call <vscale x 4 x half> @llvm.riscv.vfnmsac.mask.nxv4f16.f16(
<vscale x 4 x half> %0, <vscale x 4 x half> %0,
half %1, half %1,
<vscale x 4 x half> %2, <vscale x 4 x half> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
iXLen %4, iXLen 0); iXLen 0, iXLen %4, iXLen 0);
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 8 x half> @llvm.riscv.vfnmsac.nxv8f16.f16( declare <vscale x 8 x half> @llvm.riscv.vfnmsac.nxv8f16.f16(
<vscale x 8 x half>, <vscale x 8 x half>,
half, half,
<vscale x 8 x half>, <vscale x 8 x half>,
iXLen, iXLen, iXLen, iXLen);
iXLen);
define <vscale x 8 x half> @intrinsic_vfnmsac_vf_nxv8f16_f16_nxv8f16(<vscale x 8 x half> %0, half %1, <vscale x 8 x half> %2, iXLen %3) nounwind { define <vscale x 8 x half> @intrinsic_vfnmsac_vf_nxv8f16_f16_nxv8f16(<vscale x 8 x half> %0, half %1, <vscale x 8 x half> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfnmsac_vf_nxv8f16_f16_nxv8f16: ; CHECK-LABEL: intrinsic_vfnmsac_vf_nxv8f16_f16_nxv8f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, ma ; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, ma
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfnmsac.vf v8, fa0, v10 ; CHECK-NEXT: vfnmsac.vf v8, fa0, v10
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x half> @llvm.riscv.vfnmsac.nxv8f16.f16( %a = call <vscale x 8 x half> @llvm.riscv.vfnmsac.nxv8f16.f16(
<vscale x 8 x half> %0, <vscale x 8 x half> %0,
half %1, half %1,
<vscale x 8 x half> %2, <vscale x 8 x half> %2,
iXLen %3, iXLen 0) iXLen 0, iXLen %3, iXLen 0)
ret <vscale x 8 x half> %a ret <vscale x 8 x half> %a
} }
declare <vscale x 8 x half> @llvm.riscv.vfnmsac.mask.nxv8f16.f16( declare <vscale x 8 x half> @llvm.riscv.vfnmsac.mask.nxv8f16.f16(
<vscale x 8 x half>, <vscale x 8 x half>,
half, half,
<vscale x 8 x half>, <vscale x 8 x half>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
iXLen, iXLen); iXLen, iXLen, iXLen);
define <vscale x 8 x half> @intrinsic_vfnmsac_mask_vf_nxv8f16_f16_nxv8f16(<vscale x 8 x half> %0, half %1, <vscale x 8 x half> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind { define <vscale x 8 x half> @intrinsic_vfnmsac_mask_vf_nxv8f16_f16_nxv8f16(<vscale x 8 x half> %0, half %1, <vscale x 8 x half> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfnmsac_mask_vf_nxv8f16_f16_nxv8f16: ; CHECK-LABEL: intrinsic_vfnmsac_mask_vf_nxv8f16_f16_nxv8f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, mu
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfnmsac.vf v8, fa0, v10, v0.t ; CHECK-NEXT: vfnmsac.vf v8, fa0, v10, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x half> @llvm.riscv.vfnmsac.mask.nxv8f16.f16( %a = call <vscale x 8 x half> @llvm.riscv.vfnmsac.mask.nxv8f16.f16(
<vscale x 8 x half> %0, <vscale x 8 x half> %0,
half %1, half %1,
<vscale x 8 x half> %2, <vscale x 8 x half> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
iXLen %4, iXLen 0); iXLen 0, iXLen %4, iXLen 0);
ret <vscale x 8 x half> %a ret <vscale x 8 x half> %a
} }
declare <vscale x 16 x half> @llvm.riscv.vfnmsac.nxv16f16.f16( declare <vscale x 16 x half> @llvm.riscv.vfnmsac.nxv16f16.f16(
<vscale x 16 x half>, <vscale x 16 x half>,
half, half,
<vscale x 16 x half>, <vscale x 16 x half>,
iXLen, iXLen, iXLen, iXLen);
iXLen);
define <vscale x 16 x half> @intrinsic_vfnmsac_vf_nxv16f16_f16_nxv16f16(<vscale x 16 x half> %0, half %1, <vscale x 16 x half> %2, iXLen %3) nounwind { define <vscale x 16 x half> @intrinsic_vfnmsac_vf_nxv16f16_f16_nxv16f16(<vscale x 16 x half> %0, half %1, <vscale x 16 x half> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfnmsac_vf_nxv16f16_f16_nxv16f16: ; CHECK-LABEL: intrinsic_vfnmsac_vf_nxv16f16_f16_nxv16f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, ma ; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, ma
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfnmsac.vf v8, fa0, v12 ; CHECK-NEXT: vfnmsac.vf v8, fa0, v12
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x half> @llvm.riscv.vfnmsac.nxv16f16.f16( %a = call <vscale x 16 x half> @llvm.riscv.vfnmsac.nxv16f16.f16(
<vscale x 16 x half> %0, <vscale x 16 x half> %0,
half %1, half %1,
<vscale x 16 x half> %2, <vscale x 16 x half> %2,
iXLen %3, iXLen 0) iXLen 0, iXLen %3, iXLen 0)
ret <vscale x 16 x half> %a ret <vscale x 16 x half> %a
} }
declare <vscale x 16 x half> @llvm.riscv.vfnmsac.mask.nxv16f16.f16( declare <vscale x 16 x half> @llvm.riscv.vfnmsac.mask.nxv16f16.f16(
<vscale x 16 x half>, <vscale x 16 x half>,
half, half,
<vscale x 16 x half>, <vscale x 16 x half>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
iXLen, iXLen); iXLen, iXLen, iXLen);
define <vscale x 16 x half> @intrinsic_vfnmsac_mask_vf_nxv16f16_f16_nxv16f16(<vscale x 16 x half> %0, half %1, <vscale x 16 x half> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind { define <vscale x 16 x half> @intrinsic_vfnmsac_mask_vf_nxv16f16_f16_nxv16f16(<vscale x 16 x half> %0, half %1, <vscale x 16 x half> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfnmsac_mask_vf_nxv16f16_f16_nxv16f16: ; CHECK-LABEL: intrinsic_vfnmsac_mask_vf_nxv16f16_f16_nxv16f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfnmsac.vf v8, fa0, v12, v0.t ; CHECK-NEXT: vfnmsac.vf v8, fa0, v12, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x half> @llvm.riscv.vfnmsac.mask.nxv16f16.f16( %a = call <vscale x 16 x half> @llvm.riscv.vfnmsac.mask.nxv16f16.f16(
<vscale x 16 x half> %0, <vscale x 16 x half> %0,
half %1, half %1,
<vscale x 16 x half> %2, <vscale x 16 x half> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
iXLen %4, iXLen 0); iXLen 0, iXLen %4, iXLen 0);
ret <vscale x 16 x half> %a ret <vscale x 16 x half> %a
} }
declare <vscale x 1 x float> @llvm.riscv.vfnmsac.nxv1f32.f32( declare <vscale x 1 x float> @llvm.riscv.vfnmsac.nxv1f32.f32(
<vscale x 1 x float>, <vscale x 1 x float>,
float, float,
<vscale x 1 x float>, <vscale x 1 x float>,
iXLen, iXLen, iXLen, iXLen);
iXLen);
define <vscale x 1 x float> @intrinsic_vfnmsac_vf_nxv1f32_f32_nxv1f32(<vscale x 1 x float> %0, float %1, <vscale x 1 x float> %2, iXLen %3) nounwind { define <vscale x 1 x float> @intrinsic_vfnmsac_vf_nxv1f32_f32_nxv1f32(<vscale x 1 x float> %0, float %1, <vscale x 1 x float> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfnmsac_vf_nxv1f32_f32_nxv1f32: ; CHECK-LABEL: intrinsic_vfnmsac_vf_nxv1f32_f32_nxv1f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, ma ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, ma
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfnmsac.vf v8, fa0, v9 ; CHECK-NEXT: vfnmsac.vf v8, fa0, v9
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x float> @llvm.riscv.vfnmsac.nxv1f32.f32( %a = call <vscale x 1 x float> @llvm.riscv.vfnmsac.nxv1f32.f32(
<vscale x 1 x float> %0, <vscale x 1 x float> %0,
float %1, float %1,
<vscale x 1 x float> %2, <vscale x 1 x float> %2,
iXLen %3, iXLen 0) iXLen 0, iXLen %3, iXLen 0)
ret <vscale x 1 x float> %a ret <vscale x 1 x float> %a
} }
declare <vscale x 1 x float> @llvm.riscv.vfnmsac.mask.nxv1f32.f32( declare <vscale x 1 x float> @llvm.riscv.vfnmsac.mask.nxv1f32.f32(
<vscale x 1 x float>, <vscale x 1 x float>,
float, float,
<vscale x 1 x float>, <vscale x 1 x float>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
iXLen, iXLen); iXLen, iXLen, iXLen);
define <vscale x 1 x float> @intrinsic_vfnmsac_mask_vf_nxv1f32_f32_nxv1f32(<vscale x 1 x float> %0, float %1, <vscale x 1 x float> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind { define <vscale x 1 x float> @intrinsic_vfnmsac_mask_vf_nxv1f32_f32_nxv1f32(<vscale x 1 x float> %0, float %1, <vscale x 1 x float> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfnmsac_mask_vf_nxv1f32_f32_nxv1f32: ; CHECK-LABEL: intrinsic_vfnmsac_mask_vf_nxv1f32_f32_nxv1f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfnmsac.vf v8, fa0, v9, v0.t ; CHECK-NEXT: vfnmsac.vf v8, fa0, v9, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x float> @llvm.riscv.vfnmsac.mask.nxv1f32.f32( %a = call <vscale x 1 x float> @llvm.riscv.vfnmsac.mask.nxv1f32.f32(
<vscale x 1 x float> %0, <vscale x 1 x float> %0,
float %1, float %1,
<vscale x 1 x float> %2, <vscale x 1 x float> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
iXLen %4, iXLen 0); iXLen 0, iXLen %4, iXLen 0);
ret <vscale x 1 x float> %a ret <vscale x 1 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vfnmsac.nxv2f32.f32( declare <vscale x 2 x float> @llvm.riscv.vfnmsac.nxv2f32.f32(
<vscale x 2 x float>, <vscale x 2 x float>,
float, float,
<vscale x 2 x float>, <vscale x 2 x float>,
iXLen, iXLen, iXLen, iXLen);
iXLen);
define <vscale x 2 x float> @intrinsic_vfnmsac_vf_nxv2f32_f32_nxv2f32(<vscale x 2 x float> %0, float %1, <vscale x 2 x float> %2, iXLen %3) nounwind { define <vscale x 2 x float> @intrinsic_vfnmsac_vf_nxv2f32_f32_nxv2f32(<vscale x 2 x float> %0, float %1, <vscale x 2 x float> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfnmsac_vf_nxv2f32_f32_nxv2f32: ; CHECK-LABEL: intrinsic_vfnmsac_vf_nxv2f32_f32_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, ma ; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, ma
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfnmsac.vf v8, fa0, v9 ; CHECK-NEXT: vfnmsac.vf v8, fa0, v9
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfnmsac.nxv2f32.f32( %a = call <vscale x 2 x float> @llvm.riscv.vfnmsac.nxv2f32.f32(
<vscale x 2 x float> %0, <vscale x 2 x float> %0,
float %1, float %1,
<vscale x 2 x float> %2, <vscale x 2 x float> %2,
iXLen %3, iXLen 0) iXLen 0, iXLen %3, iXLen 0)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vfnmsac.mask.nxv2f32.f32( declare <vscale x 2 x float> @llvm.riscv.vfnmsac.mask.nxv2f32.f32(
<vscale x 2 x float>, <vscale x 2 x float>,
float, float,
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
iXLen, iXLen); iXLen, iXLen, iXLen);
define <vscale x 2 x float> @intrinsic_vfnmsac_mask_vf_nxv2f32_f32_nxv2f32(<vscale x 2 x float> %0, float %1, <vscale x 2 x float> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind { define <vscale x 2 x float> @intrinsic_vfnmsac_mask_vf_nxv2f32_f32_nxv2f32(<vscale x 2 x float> %0, float %1, <vscale x 2 x float> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfnmsac_mask_vf_nxv2f32_f32_nxv2f32: ; CHECK-LABEL: intrinsic_vfnmsac_mask_vf_nxv2f32_f32_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfnmsac.vf v8, fa0, v9, v0.t ; CHECK-NEXT: vfnmsac.vf v8, fa0, v9, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfnmsac.mask.nxv2f32.f32( %a = call <vscale x 2 x float> @llvm.riscv.vfnmsac.mask.nxv2f32.f32(
<vscale x 2 x float> %0, <vscale x 2 x float> %0,
float %1, float %1,
<vscale x 2 x float> %2, <vscale x 2 x float> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
iXLen %4, iXLen 0); iXLen 0, iXLen %4, iXLen 0);
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 4 x float> @llvm.riscv.vfnmsac.nxv4f32.f32( declare <vscale x 4 x float> @llvm.riscv.vfnmsac.nxv4f32.f32(
<vscale x 4 x float>, <vscale x 4 x float>,
float, float,
<vscale x 4 x float>, <vscale x 4 x float>,
iXLen, iXLen, iXLen, iXLen);
iXLen);
define <vscale x 4 x float> @intrinsic_vfnmsac_vf_nxv4f32_f32_nxv4f32(<vscale x 4 x float> %0, float %1, <vscale x 4 x float> %2, iXLen %3) nounwind { define <vscale x 4 x float> @intrinsic_vfnmsac_vf_nxv4f32_f32_nxv4f32(<vscale x 4 x float> %0, float %1, <vscale x 4 x float> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfnmsac_vf_nxv4f32_f32_nxv4f32: ; CHECK-LABEL: intrinsic_vfnmsac_vf_nxv4f32_f32_nxv4f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, ma ; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, ma
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfnmsac.vf v8, fa0, v10 ; CHECK-NEXT: vfnmsac.vf v8, fa0, v10
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x float> @llvm.riscv.vfnmsac.nxv4f32.f32( %a = call <vscale x 4 x float> @llvm.riscv.vfnmsac.nxv4f32.f32(
<vscale x 4 x float> %0, <vscale x 4 x float> %0,
float %1, float %1,
<vscale x 4 x float> %2, <vscale x 4 x float> %2,
iXLen %3, iXLen 0) iXLen 0, iXLen %3, iXLen 0)
ret <vscale x 4 x float> %a ret <vscale x 4 x float> %a
} }
declare <vscale x 4 x float> @llvm.riscv.vfnmsac.mask.nxv4f32.f32( declare <vscale x 4 x float> @llvm.riscv.vfnmsac.mask.nxv4f32.f32(
<vscale x 4 x float>, <vscale x 4 x float>,
float, float,
<vscale x 4 x float>, <vscale x 4 x float>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
iXLen, iXLen); iXLen, iXLen, iXLen);
define <vscale x 4 x float> @intrinsic_vfnmsac_mask_vf_nxv4f32_f32_nxv4f32(<vscale x 4 x float> %0, float %1, <vscale x 4 x float> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind { define <vscale x 4 x float> @intrinsic_vfnmsac_mask_vf_nxv4f32_f32_nxv4f32(<vscale x 4 x float> %0, float %1, <vscale x 4 x float> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfnmsac_mask_vf_nxv4f32_f32_nxv4f32: ; CHECK-LABEL: intrinsic_vfnmsac_mask_vf_nxv4f32_f32_nxv4f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfnmsac.vf v8, fa0, v10, v0.t ; CHECK-NEXT: vfnmsac.vf v8, fa0, v10, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x float> @llvm.riscv.vfnmsac.mask.nxv4f32.f32( %a = call <vscale x 4 x float> @llvm.riscv.vfnmsac.mask.nxv4f32.f32(
<vscale x 4 x float> %0, <vscale x 4 x float> %0,
float %1, float %1,
<vscale x 4 x float> %2, <vscale x 4 x float> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
iXLen %4, iXLen 0); iXLen 0, iXLen %4, iXLen 0);
ret <vscale x 4 x float> %a ret <vscale x 4 x float> %a
} }
declare <vscale x 8 x float> @llvm.riscv.vfnmsac.nxv8f32.f32( declare <vscale x 8 x float> @llvm.riscv.vfnmsac.nxv8f32.f32(
<vscale x 8 x float>, <vscale x 8 x float>,
float, float,
<vscale x 8 x float>, <vscale x 8 x float>,
iXLen, iXLen, iXLen, iXLen);
iXLen);
define <vscale x 8 x float> @intrinsic_vfnmsac_vf_nxv8f32_f32_nxv8f32(<vscale x 8 x float> %0, float %1, <vscale x 8 x float> %2, iXLen %3) nounwind { define <vscale x 8 x float> @intrinsic_vfnmsac_vf_nxv8f32_f32_nxv8f32(<vscale x 8 x float> %0, float %1, <vscale x 8 x float> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfnmsac_vf_nxv8f32_f32_nxv8f32: ; CHECK-LABEL: intrinsic_vfnmsac_vf_nxv8f32_f32_nxv8f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, ma ; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, ma
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfnmsac.vf v8, fa0, v12 ; CHECK-NEXT: vfnmsac.vf v8, fa0, v12
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x float> @llvm.riscv.vfnmsac.nxv8f32.f32( %a = call <vscale x 8 x float> @llvm.riscv.vfnmsac.nxv8f32.f32(
<vscale x 8 x float> %0, <vscale x 8 x float> %0,
float %1, float %1,
<vscale x 8 x float> %2, <vscale x 8 x float> %2,
iXLen %3, iXLen 0) iXLen 0, iXLen %3, iXLen 0)
ret <vscale x 8 x float> %a ret <vscale x 8 x float> %a
} }
declare <vscale x 8 x float> @llvm.riscv.vfnmsac.mask.nxv8f32.f32( declare <vscale x 8 x float> @llvm.riscv.vfnmsac.mask.nxv8f32.f32(
<vscale x 8 x float>, <vscale x 8 x float>,
float, float,
<vscale x 8 x float>, <vscale x 8 x float>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
iXLen, iXLen); iXLen, iXLen, iXLen);
define <vscale x 8 x float> @intrinsic_vfnmsac_mask_vf_nxv8f32_f32_nxv8f32(<vscale x 8 x float> %0, float %1, <vscale x 8 x float> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind { define <vscale x 8 x float> @intrinsic_vfnmsac_mask_vf_nxv8f32_f32_nxv8f32(<vscale x 8 x float> %0, float %1, <vscale x 8 x float> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfnmsac_mask_vf_nxv8f32_f32_nxv8f32: ; CHECK-LABEL: intrinsic_vfnmsac_mask_vf_nxv8f32_f32_nxv8f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfnmsac.vf v8, fa0, v12, v0.t ; CHECK-NEXT: vfnmsac.vf v8, fa0, v12, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x float> @llvm.riscv.vfnmsac.mask.nxv8f32.f32( %a = call <vscale x 8 x float> @llvm.riscv.vfnmsac.mask.nxv8f32.f32(
<vscale x 8 x float> %0, <vscale x 8 x float> %0,
float %1, float %1,
<vscale x 8 x float> %2, <vscale x 8 x float> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
iXLen %4, iXLen 0); iXLen 0, iXLen %4, iXLen 0);
ret <vscale x 8 x float> %a ret <vscale x 8 x float> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vfnmsac.nxv1f64.f64( declare <vscale x 1 x double> @llvm.riscv.vfnmsac.nxv1f64.f64(
<vscale x 1 x double>, <vscale x 1 x double>,
double, double,
<vscale x 1 x double>, <vscale x 1 x double>,
iXLen, iXLen, iXLen, iXLen);
iXLen);
define <vscale x 1 x double> @intrinsic_vfnmsac_vf_nxv1f64_f64_nxv1f64(<vscale x 1 x double> %0, double %1, <vscale x 1 x double> %2, iXLen %3) nounwind { define <vscale x 1 x double> @intrinsic_vfnmsac_vf_nxv1f64_f64_nxv1f64(<vscale x 1 x double> %0, double %1, <vscale x 1 x double> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfnmsac_vf_nxv1f64_f64_nxv1f64: ; CHECK-LABEL: intrinsic_vfnmsac_vf_nxv1f64_f64_nxv1f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, ma ; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, ma
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfnmsac.vf v8, fa0, v9 ; CHECK-NEXT: vfnmsac.vf v8, fa0, v9
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfnmsac.nxv1f64.f64( %a = call <vscale x 1 x double> @llvm.riscv.vfnmsac.nxv1f64.f64(
<vscale x 1 x double> %0, <vscale x 1 x double> %0,
double %1, double %1,
<vscale x 1 x double> %2, <vscale x 1 x double> %2,
iXLen %3, iXLen 0) iXLen 0, iXLen %3, iXLen 0)
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vfnmsac.mask.nxv1f64.f64( declare <vscale x 1 x double> @llvm.riscv.vfnmsac.mask.nxv1f64.f64(
<vscale x 1 x double>, <vscale x 1 x double>,
double, double,
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
iXLen, iXLen); iXLen, iXLen, iXLen);
define <vscale x 1 x double> @intrinsic_vfnmsac_mask_vf_nxv1f64_f64_nxv1f64(<vscale x 1 x double> %0, double %1, <vscale x 1 x double> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind { define <vscale x 1 x double> @intrinsic_vfnmsac_mask_vf_nxv1f64_f64_nxv1f64(<vscale x 1 x double> %0, double %1, <vscale x 1 x double> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfnmsac_mask_vf_nxv1f64_f64_nxv1f64: ; CHECK-LABEL: intrinsic_vfnmsac_mask_vf_nxv1f64_f64_nxv1f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, mu
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfnmsac.vf v8, fa0, v9, v0.t ; CHECK-NEXT: vfnmsac.vf v8, fa0, v9, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfnmsac.mask.nxv1f64.f64( %a = call <vscale x 1 x double> @llvm.riscv.vfnmsac.mask.nxv1f64.f64(
<vscale x 1 x double> %0, <vscale x 1 x double> %0,
double %1, double %1,
<vscale x 1 x double> %2, <vscale x 1 x double> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
iXLen %4, iXLen 0); iXLen 0, iXLen %4, iXLen 0);
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 2 x double> @llvm.riscv.vfnmsac.nxv2f64.f64( declare <vscale x 2 x double> @llvm.riscv.vfnmsac.nxv2f64.f64(
<vscale x 2 x double>, <vscale x 2 x double>,
double, double,
<vscale x 2 x double>, <vscale x 2 x double>,
iXLen, iXLen, iXLen, iXLen);
iXLen);
define <vscale x 2 x double> @intrinsic_vfnmsac_vf_nxv2f64_f64_nxv2f64(<vscale x 2 x double> %0, double %1, <vscale x 2 x double> %2, iXLen %3) nounwind { define <vscale x 2 x double> @intrinsic_vfnmsac_vf_nxv2f64_f64_nxv2f64(<vscale x 2 x double> %0, double %1, <vscale x 2 x double> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfnmsac_vf_nxv2f64_f64_nxv2f64: ; CHECK-LABEL: intrinsic_vfnmsac_vf_nxv2f64_f64_nxv2f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, ma ; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, ma
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfnmsac.vf v8, fa0, v10 ; CHECK-NEXT: vfnmsac.vf v8, fa0, v10
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x double> @llvm.riscv.vfnmsac.nxv2f64.f64( %a = call <vscale x 2 x double> @llvm.riscv.vfnmsac.nxv2f64.f64(
<vscale x 2 x double> %0, <vscale x 2 x double> %0,
double %1, double %1,
<vscale x 2 x double> %2, <vscale x 2 x double> %2,
iXLen %3, iXLen 0) iXLen 0, iXLen %3, iXLen 0)
ret <vscale x 2 x double> %a ret <vscale x 2 x double> %a
} }
declare <vscale x 2 x double> @llvm.riscv.vfnmsac.mask.nxv2f64.f64( declare <vscale x 2 x double> @llvm.riscv.vfnmsac.mask.nxv2f64.f64(
<vscale x 2 x double>, <vscale x 2 x double>,
double, double,
<vscale x 2 x double>, <vscale x 2 x double>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
iXLen, iXLen); iXLen, iXLen, iXLen);
define <vscale x 2 x double> @intrinsic_vfnmsac_mask_vf_nxv2f64_f64_nxv2f64(<vscale x 2 x double> %0, double %1, <vscale x 2 x double> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind { define <vscale x 2 x double> @intrinsic_vfnmsac_mask_vf_nxv2f64_f64_nxv2f64(<vscale x 2 x double> %0, double %1, <vscale x 2 x double> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfnmsac_mask_vf_nxv2f64_f64_nxv2f64: ; CHECK-LABEL: intrinsic_vfnmsac_mask_vf_nxv2f64_f64_nxv2f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, mu
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfnmsac.vf v8, fa0, v10, v0.t ; CHECK-NEXT: vfnmsac.vf v8, fa0, v10, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x double> @llvm.riscv.vfnmsac.mask.nxv2f64.f64( %a = call <vscale x 2 x double> @llvm.riscv.vfnmsac.mask.nxv2f64.f64(
<vscale x 2 x double> %0, <vscale x 2 x double> %0,
double %1, double %1,
<vscale x 2 x double> %2, <vscale x 2 x double> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
iXLen %4, iXLen 0); iXLen 0, iXLen %4, iXLen 0);
ret <vscale x 2 x double> %a ret <vscale x 2 x double> %a
} }
declare <vscale x 4 x double> @llvm.riscv.vfnmsac.nxv4f64.f64( declare <vscale x 4 x double> @llvm.riscv.vfnmsac.nxv4f64.f64(
<vscale x 4 x double>, <vscale x 4 x double>,
double, double,
<vscale x 4 x double>, <vscale x 4 x double>,
iXLen, iXLen, iXLen, iXLen);
iXLen);
define <vscale x 4 x double> @intrinsic_vfnmsac_vf_nxv4f64_f64_nxv4f64(<vscale x 4 x double> %0, double %1, <vscale x 4 x double> %2, iXLen %3) nounwind { define <vscale x 4 x double> @intrinsic_vfnmsac_vf_nxv4f64_f64_nxv4f64(<vscale x 4 x double> %0, double %1, <vscale x 4 x double> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfnmsac_vf_nxv4f64_f64_nxv4f64: ; CHECK-LABEL: intrinsic_vfnmsac_vf_nxv4f64_f64_nxv4f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, ma ; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, ma
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfnmsac.vf v8, fa0, v12 ; CHECK-NEXT: vfnmsac.vf v8, fa0, v12
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x double> @llvm.riscv.vfnmsac.nxv4f64.f64( %a = call <vscale x 4 x double> @llvm.riscv.vfnmsac.nxv4f64.f64(
<vscale x 4 x double> %0, <vscale x 4 x double> %0,
double %1, double %1,
<vscale x 4 x double> %2, <vscale x 4 x double> %2,
iXLen %3, iXLen 0) iXLen 0, iXLen %3, iXLen 0)
ret <vscale x 4 x double> %a ret <vscale x 4 x double> %a
} }
declare <vscale x 4 x double> @llvm.riscv.vfnmsac.mask.nxv4f64.f64( declare <vscale x 4 x double> @llvm.riscv.vfnmsac.mask.nxv4f64.f64(
<vscale x 4 x double>, <vscale x 4 x double>,
double, double,
<vscale x 4 x double>, <vscale x 4 x double>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
iXLen, iXLen); iXLen, iXLen, iXLen);
define <vscale x 4 x double> @intrinsic_vfnmsac_mask_vf_nxv4f64_f64_nxv4f64(<vscale x 4 x double> %0, double %1, <vscale x 4 x double> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind { define <vscale x 4 x double> @intrinsic_vfnmsac_mask_vf_nxv4f64_f64_nxv4f64(<vscale x 4 x double> %0, double %1, <vscale x 4 x double> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfnmsac_mask_vf_nxv4f64_f64_nxv4f64: ; CHECK-LABEL: intrinsic_vfnmsac_mask_vf_nxv4f64_f64_nxv4f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, mu
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfnmsac.vf v8, fa0, v12, v0.t ; CHECK-NEXT: vfnmsac.vf v8, fa0, v12, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x double> @llvm.riscv.vfnmsac.mask.nxv4f64.f64( %a = call <vscale x 4 x double> @llvm.riscv.vfnmsac.mask.nxv4f64.f64(
<vscale x 4 x double> %0, <vscale x 4 x double> %0,
double %1, double %1,
<vscale x 4 x double> %2, <vscale x 4 x double> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
iXLen %4, iXLen 0); iXLen 0, iXLen %4, iXLen 0);
ret <vscale x 4 x double> %a ret <vscale x 4 x double> %a
} }

llvm/test/CodeGen/RISCV/rvv/vfnmsub.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zfh,+experimental-zvfh \ ; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+v,+zfh,+experimental-zvfh \
; RUN: -verify-machineinstrs -target-abi=ilp32d | FileCheck %s ; RUN: -verify-machineinstrs -target-abi=ilp32d | FileCheck %s
; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zfh,+experimental-zvfh \ ; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+v,+zfh,+experimental-zvfh \
; RUN: -verify-machineinstrs -target-abi=lp64d | FileCheck %s ; RUN: -verify-machineinstrs -target-abi=lp64d | FileCheck %s
declare <vscale x 1 x half> @llvm.riscv.vfnmsub.nxv1f16.nxv1f16( declare <vscale x 1 x half> @llvm.riscv.vfnmsub.nxv1f16.nxv1f16(
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x half>, <vscale x 1 x half>,
iXLen, iXLen, iXLen, iXLen);
iXLen);
define <vscale x 1 x half> @intrinsic_vfnmsub_vv_nxv1f16_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, iXLen %3) nounwind { define <vscale x 1 x half> @intrinsic_vfnmsub_vv_nxv1f16_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfnmsub_vv_nxv1f16_nxv1f16_nxv1f16: ; CHECK-LABEL: intrinsic_vfnmsub_vv_nxv1f16_nxv1f16_nxv1f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, ma ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, ma
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfnmsub.vv v8, v9, v10 ; CHECK-NEXT: vfnmsub.vv v8, v9, v10
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x half> @llvm.riscv.vfnmsub.nxv1f16.nxv1f16( %a = call <vscale x 1 x half> @llvm.riscv.vfnmsub.nxv1f16.nxv1f16(
<vscale x 1 x half> %0, <vscale x 1 x half> %0,
<vscale x 1 x half> %1, <vscale x 1 x half> %1,
<vscale x 1 x half> %2, <vscale x 1 x half> %2,
iXLen %3, iXLen 0) iXLen 0, iXLen %3, iXLen 0)
ret <vscale x 1 x half> %a ret <vscale x 1 x half> %a
} }
declare <vscale x 1 x half> @llvm.riscv.vfnmsub.mask.nxv1f16.nxv1f16( declare <vscale x 1 x half> @llvm.riscv.vfnmsub.mask.nxv1f16.nxv1f16(
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
iXLen, iXLen); iXLen, iXLen, iXLen);
define <vscale x 1 x half> @intrinsic_vfnmsub_mask_vv_nxv1f16_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind { define <vscale x 1 x half> @intrinsic_vfnmsub_mask_vv_nxv1f16_nxv1f16_nxv1f16(<vscale x 1 x half> %0, <vscale x 1 x half> %1, <vscale x 1 x half> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfnmsub_mask_vv_nxv1f16_nxv1f16_nxv1f16: ; CHECK-LABEL: intrinsic_vfnmsub_mask_vv_nxv1f16_nxv1f16_nxv1f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfnmsub.vv v8, v9, v10, v0.t ; CHECK-NEXT: vfnmsub.vv v8, v9, v10, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x half> @llvm.riscv.vfnmsub.mask.nxv1f16.nxv1f16( %a = call <vscale x 1 x half> @llvm.riscv.vfnmsub.mask.nxv1f16.nxv1f16(
<vscale x 1 x half> %0, <vscale x 1 x half> %0,
<vscale x 1 x half> %1, <vscale x 1 x half> %1,
<vscale x 1 x half> %2, <vscale x 1 x half> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
iXLen %4, iXLen 0); iXLen 0, iXLen %4, iXLen 0);
ret <vscale x 1 x half> %a ret <vscale x 1 x half> %a
} }
declare <vscale x 2 x half> @llvm.riscv.vfnmsub.nxv2f16.nxv2f16( declare <vscale x 2 x half> @llvm.riscv.vfnmsub.nxv2f16.nxv2f16(
<vscale x 2 x half>, <vscale x 2 x half>,
<vscale x 2 x half>, <vscale x 2 x half>,
<vscale x 2 x half>, <vscale x 2 x half>,
iXLen, iXLen, iXLen, iXLen);
iXLen);
define <vscale x 2 x half> @intrinsic_vfnmsub_vv_nxv2f16_nxv2f16_nxv2f16(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, iXLen %3) nounwind { define <vscale x 2 x half> @intrinsic_vfnmsub_vv_nxv2f16_nxv2f16_nxv2f16(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfnmsub_vv_nxv2f16_nxv2f16_nxv2f16: ; CHECK-LABEL: intrinsic_vfnmsub_vv_nxv2f16_nxv2f16_nxv2f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, ma ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, ma
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfnmsub.vv v8, v9, v10 ; CHECK-NEXT: vfnmsub.vv v8, v9, v10
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x half> @llvm.riscv.vfnmsub.nxv2f16.nxv2f16( %a = call <vscale x 2 x half> @llvm.riscv.vfnmsub.nxv2f16.nxv2f16(
<vscale x 2 x half> %0, <vscale x 2 x half> %0,
<vscale x 2 x half> %1, <vscale x 2 x half> %1,
<vscale x 2 x half> %2, <vscale x 2 x half> %2,
iXLen %3, iXLen 0) iXLen 0, iXLen %3, iXLen 0)
ret <vscale x 2 x half> %a ret <vscale x 2 x half> %a
} }
declare <vscale x 2 x half> @llvm.riscv.vfnmsub.mask.nxv2f16.nxv2f16( declare <vscale x 2 x half> @llvm.riscv.vfnmsub.mask.nxv2f16.nxv2f16(
<vscale x 2 x half>, <vscale x 2 x half>,
<vscale x 2 x half>, <vscale x 2 x half>,
<vscale x 2 x half>, <vscale x 2 x half>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
iXLen, iXLen); iXLen, iXLen, iXLen);
define <vscale x 2 x half> @intrinsic_vfnmsub_mask_vv_nxv2f16_nxv2f16_nxv2f16(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind { define <vscale x 2 x half> @intrinsic_vfnmsub_mask_vv_nxv2f16_nxv2f16_nxv2f16(<vscale x 2 x half> %0, <vscale x 2 x half> %1, <vscale x 2 x half> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfnmsub_mask_vv_nxv2f16_nxv2f16_nxv2f16: ; CHECK-LABEL: intrinsic_vfnmsub_mask_vv_nxv2f16_nxv2f16_nxv2f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfnmsub.vv v8, v9, v10, v0.t ; CHECK-NEXT: vfnmsub.vv v8, v9, v10, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x half> @llvm.riscv.vfnmsub.mask.nxv2f16.nxv2f16( %a = call <vscale x 2 x half> @llvm.riscv.vfnmsub.mask.nxv2f16.nxv2f16(
<vscale x 2 x half> %0, <vscale x 2 x half> %0,
<vscale x 2 x half> %1, <vscale x 2 x half> %1,
<vscale x 2 x half> %2, <vscale x 2 x half> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
iXLen %4, iXLen 0); iXLen 0, iXLen %4, iXLen 0);
ret <vscale x 2 x half> %a ret <vscale x 2 x half> %a
} }
declare <vscale x 4 x half> @llvm.riscv.vfnmsub.nxv4f16.nxv4f16( declare <vscale x 4 x half> @llvm.riscv.vfnmsub.nxv4f16.nxv4f16(
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 4 x half>, <vscale x 4 x half>,
iXLen, iXLen, iXLen, iXLen);
iXLen);
define <vscale x 4 x half> @intrinsic_vfnmsub_vv_nxv4f16_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, iXLen %3) nounwind { define <vscale x 4 x half> @intrinsic_vfnmsub_vv_nxv4f16_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfnmsub_vv_nxv4f16_nxv4f16_nxv4f16: ; CHECK-LABEL: intrinsic_vfnmsub_vv_nxv4f16_nxv4f16_nxv4f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, ma ; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, ma
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfnmsub.vv v8, v9, v10 ; CHECK-NEXT: vfnmsub.vv v8, v9, v10
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x half> @llvm.riscv.vfnmsub.nxv4f16.nxv4f16( %a = call <vscale x 4 x half> @llvm.riscv.vfnmsub.nxv4f16.nxv4f16(
<vscale x 4 x half> %0, <vscale x 4 x half> %0,
<vscale x 4 x half> %1, <vscale x 4 x half> %1,
<vscale x 4 x half> %2, <vscale x 4 x half> %2,
iXLen %3, iXLen 0) iXLen 0, iXLen %3, iXLen 0)
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 4 x half> @llvm.riscv.vfnmsub.mask.nxv4f16.nxv4f16( declare <vscale x 4 x half> @llvm.riscv.vfnmsub.mask.nxv4f16.nxv4f16(
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
iXLen, iXLen); iXLen, iXLen, iXLen);
define <vscale x 4 x half> @intrinsic_vfnmsub_mask_vv_nxv4f16_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind { define <vscale x 4 x half> @intrinsic_vfnmsub_mask_vv_nxv4f16_nxv4f16_nxv4f16(<vscale x 4 x half> %0, <vscale x 4 x half> %1, <vscale x 4 x half> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfnmsub_mask_vv_nxv4f16_nxv4f16_nxv4f16: ; CHECK-LABEL: intrinsic_vfnmsub_mask_vv_nxv4f16_nxv4f16_nxv4f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfnmsub.vv v8, v9, v10, v0.t ; CHECK-NEXT: vfnmsub.vv v8, v9, v10, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x half> @llvm.riscv.vfnmsub.mask.nxv4f16.nxv4f16( %a = call <vscale x 4 x half> @llvm.riscv.vfnmsub.mask.nxv4f16.nxv4f16(
<vscale x 4 x half> %0, <vscale x 4 x half> %0,
<vscale x 4 x half> %1, <vscale x 4 x half> %1,
<vscale x 4 x half> %2, <vscale x 4 x half> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
iXLen %4, iXLen 0); iXLen 0, iXLen %4, iXLen 0);
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 8 x half> @llvm.riscv.vfnmsub.nxv8f16.nxv8f16( declare <vscale x 8 x half> @llvm.riscv.vfnmsub.nxv8f16.nxv8f16(
<vscale x 8 x half>, <vscale x 8 x half>,
<vscale x 8 x half>, <vscale x 8 x half>,
<vscale x 8 x half>, <vscale x 8 x half>,
iXLen, iXLen, iXLen, iXLen);
iXLen);
define <vscale x 8 x half> @intrinsic_vfnmsub_vv_nxv8f16_nxv8f16_nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, iXLen %3) nounwind { define <vscale x 8 x half> @intrinsic_vfnmsub_vv_nxv8f16_nxv8f16_nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfnmsub_vv_nxv8f16_nxv8f16_nxv8f16: ; CHECK-LABEL: intrinsic_vfnmsub_vv_nxv8f16_nxv8f16_nxv8f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, ma ; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, ma
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfnmsub.vv v8, v10, v12 ; CHECK-NEXT: vfnmsub.vv v8, v10, v12
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x half> @llvm.riscv.vfnmsub.nxv8f16.nxv8f16( %a = call <vscale x 8 x half> @llvm.riscv.vfnmsub.nxv8f16.nxv8f16(
<vscale x 8 x half> %0, <vscale x 8 x half> %0,
<vscale x 8 x half> %1, <vscale x 8 x half> %1,
<vscale x 8 x half> %2, <vscale x 8 x half> %2,
iXLen %3, iXLen 0) iXLen 0, iXLen %3, iXLen 0)
ret <vscale x 8 x half> %a ret <vscale x 8 x half> %a
} }
declare <vscale x 8 x half> @llvm.riscv.vfnmsub.mask.nxv8f16.nxv8f16( declare <vscale x 8 x half> @llvm.riscv.vfnmsub.mask.nxv8f16.nxv8f16(
<vscale x 8 x half>, <vscale x 8 x half>,
<vscale x 8 x half>, <vscale x 8 x half>,
<vscale x 8 x half>, <vscale x 8 x half>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
iXLen, iXLen); iXLen, iXLen, iXLen);
define <vscale x 8 x half> @intrinsic_vfnmsub_mask_vv_nxv8f16_nxv8f16_nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind { define <vscale x 8 x half> @intrinsic_vfnmsub_mask_vv_nxv8f16_nxv8f16_nxv8f16(<vscale x 8 x half> %0, <vscale x 8 x half> %1, <vscale x 8 x half> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfnmsub_mask_vv_nxv8f16_nxv8f16_nxv8f16: ; CHECK-LABEL: intrinsic_vfnmsub_mask_vv_nxv8f16_nxv8f16_nxv8f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, mu
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfnmsub.vv v8, v10, v12, v0.t ; CHECK-NEXT: vfnmsub.vv v8, v10, v12, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x half> @llvm.riscv.vfnmsub.mask.nxv8f16.nxv8f16( %a = call <vscale x 8 x half> @llvm.riscv.vfnmsub.mask.nxv8f16.nxv8f16(
<vscale x 8 x half> %0, <vscale x 8 x half> %0,
<vscale x 8 x half> %1, <vscale x 8 x half> %1,
<vscale x 8 x half> %2, <vscale x 8 x half> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
iXLen %4, iXLen 0); iXLen 0, iXLen %4, iXLen 0);
ret <vscale x 8 x half> %a ret <vscale x 8 x half> %a
} }
declare <vscale x 16 x half> @llvm.riscv.vfnmsub.nxv16f16.nxv16f16( declare <vscale x 16 x half> @llvm.riscv.vfnmsub.nxv16f16.nxv16f16(
<vscale x 16 x half>, <vscale x 16 x half>,
<vscale x 16 x half>, <vscale x 16 x half>,
<vscale x 16 x half>, <vscale x 16 x half>,
iXLen, iXLen, iXLen, iXLen);
iXLen);
define <vscale x 16 x half> @intrinsic_vfnmsub_vv_nxv16f16_nxv16f16_nxv16f16(<vscale x 16 x half> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %2, iXLen %3) nounwind { define <vscale x 16 x half> @intrinsic_vfnmsub_vv_nxv16f16_nxv16f16_nxv16f16(<vscale x 16 x half> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfnmsub_vv_nxv16f16_nxv16f16_nxv16f16: ; CHECK-LABEL: intrinsic_vfnmsub_vv_nxv16f16_nxv16f16_nxv16f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, ma ; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, ma
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfnmsub.vv v8, v12, v16 ; CHECK-NEXT: vfnmsub.vv v8, v12, v16
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x half> @llvm.riscv.vfnmsub.nxv16f16.nxv16f16( %a = call <vscale x 16 x half> @llvm.riscv.vfnmsub.nxv16f16.nxv16f16(
<vscale x 16 x half> %0, <vscale x 16 x half> %0,
<vscale x 16 x half> %1, <vscale x 16 x half> %1,
<vscale x 16 x half> %2, <vscale x 16 x half> %2,
iXLen %3, iXLen 0) iXLen 0, iXLen %3, iXLen 0)
ret <vscale x 16 x half> %a ret <vscale x 16 x half> %a
} }
declare <vscale x 16 x half> @llvm.riscv.vfnmsub.mask.nxv16f16.nxv16f16( declare <vscale x 16 x half> @llvm.riscv.vfnmsub.mask.nxv16f16.nxv16f16(
<vscale x 16 x half>, <vscale x 16 x half>,
<vscale x 16 x half>, <vscale x 16 x half>,
<vscale x 16 x half>, <vscale x 16 x half>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
iXLen, iXLen); iXLen, iXLen, iXLen);
define <vscale x 16 x half> @intrinsic_vfnmsub_mask_vv_nxv16f16_nxv16f16_nxv16f16(<vscale x 16 x half> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind { define <vscale x 16 x half> @intrinsic_vfnmsub_mask_vv_nxv16f16_nxv16f16_nxv16f16(<vscale x 16 x half> %0, <vscale x 16 x half> %1, <vscale x 16 x half> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfnmsub_mask_vv_nxv16f16_nxv16f16_nxv16f16: ; CHECK-LABEL: intrinsic_vfnmsub_mask_vv_nxv16f16_nxv16f16_nxv16f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfnmsub.vv v8, v12, v16, v0.t ; CHECK-NEXT: vfnmsub.vv v8, v12, v16, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x half> @llvm.riscv.vfnmsub.mask.nxv16f16.nxv16f16( %a = call <vscale x 16 x half> @llvm.riscv.vfnmsub.mask.nxv16f16.nxv16f16(
<vscale x 16 x half> %0, <vscale x 16 x half> %0,
<vscale x 16 x half> %1, <vscale x 16 x half> %1,
<vscale x 16 x half> %2, <vscale x 16 x half> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
iXLen %4, iXLen 0); iXLen 0, iXLen %4, iXLen 0);
ret <vscale x 16 x half> %a ret <vscale x 16 x half> %a
} }
declare <vscale x 1 x float> @llvm.riscv.vfnmsub.nxv1f32.nxv1f32( declare <vscale x 1 x float> @llvm.riscv.vfnmsub.nxv1f32.nxv1f32(
<vscale x 1 x float>, <vscale x 1 x float>,
<vscale x 1 x float>, <vscale x 1 x float>,
<vscale x 1 x float>, <vscale x 1 x float>,
iXLen, iXLen, iXLen, iXLen);
iXLen);
define <vscale x 1 x float> @intrinsic_vfnmsub_vv_nxv1f32_nxv1f32_nxv1f32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, iXLen %3) nounwind { define <vscale x 1 x float> @intrinsic_vfnmsub_vv_nxv1f32_nxv1f32_nxv1f32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfnmsub_vv_nxv1f32_nxv1f32_nxv1f32: ; CHECK-LABEL: intrinsic_vfnmsub_vv_nxv1f32_nxv1f32_nxv1f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, ma ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, ma
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfnmsub.vv v8, v9, v10 ; CHECK-NEXT: vfnmsub.vv v8, v9, v10
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x float> @llvm.riscv.vfnmsub.nxv1f32.nxv1f32( %a = call <vscale x 1 x float> @llvm.riscv.vfnmsub.nxv1f32.nxv1f32(
<vscale x 1 x float> %0, <vscale x 1 x float> %0,
<vscale x 1 x float> %1, <vscale x 1 x float> %1,
<vscale x 1 x float> %2, <vscale x 1 x float> %2,
iXLen %3, iXLen 0) iXLen 0, iXLen %3, iXLen 0)
ret <vscale x 1 x float> %a ret <vscale x 1 x float> %a
} }
declare <vscale x 1 x float> @llvm.riscv.vfnmsub.mask.nxv1f32.nxv1f32( declare <vscale x 1 x float> @llvm.riscv.vfnmsub.mask.nxv1f32.nxv1f32(
<vscale x 1 x float>, <vscale x 1 x float>,
<vscale x 1 x float>, <vscale x 1 x float>,
<vscale x 1 x float>, <vscale x 1 x float>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
iXLen, iXLen); iXLen, iXLen, iXLen);
define <vscale x 1 x float> @intrinsic_vfnmsub_mask_vv_nxv1f32_nxv1f32_nxv1f32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind { define <vscale x 1 x float> @intrinsic_vfnmsub_mask_vv_nxv1f32_nxv1f32_nxv1f32(<vscale x 1 x float> %0, <vscale x 1 x float> %1, <vscale x 1 x float> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfnmsub_mask_vv_nxv1f32_nxv1f32_nxv1f32: ; CHECK-LABEL: intrinsic_vfnmsub_mask_vv_nxv1f32_nxv1f32_nxv1f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfnmsub.vv v8, v9, v10, v0.t ; CHECK-NEXT: vfnmsub.vv v8, v9, v10, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x float> @llvm.riscv.vfnmsub.mask.nxv1f32.nxv1f32( %a = call <vscale x 1 x float> @llvm.riscv.vfnmsub.mask.nxv1f32.nxv1f32(
<vscale x 1 x float> %0, <vscale x 1 x float> %0,
<vscale x 1 x float> %1, <vscale x 1 x float> %1,
<vscale x 1 x float> %2, <vscale x 1 x float> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
iXLen %4, iXLen 0); iXLen 0, iXLen %4, iXLen 0);
ret <vscale x 1 x float> %a ret <vscale x 1 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vfnmsub.nxv2f32.nxv2f32( declare <vscale x 2 x float> @llvm.riscv.vfnmsub.nxv2f32.nxv2f32(
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 2 x float>, <vscale x 2 x float>,
iXLen, iXLen, iXLen, iXLen);
iXLen);
define <vscale x 2 x float> @intrinsic_vfnmsub_vv_nxv2f32_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, iXLen %3) nounwind { define <vscale x 2 x float> @intrinsic_vfnmsub_vv_nxv2f32_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfnmsub_vv_nxv2f32_nxv2f32_nxv2f32: ; CHECK-LABEL: intrinsic_vfnmsub_vv_nxv2f32_nxv2f32_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, ma ; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, ma
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfnmsub.vv v8, v9, v10 ; CHECK-NEXT: vfnmsub.vv v8, v9, v10
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfnmsub.nxv2f32.nxv2f32( %a = call <vscale x 2 x float> @llvm.riscv.vfnmsub.nxv2f32.nxv2f32(
<vscale x 2 x float> %0, <vscale x 2 x float> %0,
<vscale x 2 x float> %1, <vscale x 2 x float> %1,
<vscale x 2 x float> %2, <vscale x 2 x float> %2,
iXLen %3, iXLen 0) iXLen 0, iXLen %3, iXLen 0)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vfnmsub.mask.nxv2f32.nxv2f32( declare <vscale x 2 x float> @llvm.riscv.vfnmsub.mask.nxv2f32.nxv2f32(
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
iXLen, iXLen); iXLen, iXLen, iXLen);
define <vscale x 2 x float> @intrinsic_vfnmsub_mask_vv_nxv2f32_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind { define <vscale x 2 x float> @intrinsic_vfnmsub_mask_vv_nxv2f32_nxv2f32_nxv2f32(<vscale x 2 x float> %0, <vscale x 2 x float> %1, <vscale x 2 x float> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfnmsub_mask_vv_nxv2f32_nxv2f32_nxv2f32: ; CHECK-LABEL: intrinsic_vfnmsub_mask_vv_nxv2f32_nxv2f32_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfnmsub.vv v8, v9, v10, v0.t ; CHECK-NEXT: vfnmsub.vv v8, v9, v10, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfnmsub.mask.nxv2f32.nxv2f32( %a = call <vscale x 2 x float> @llvm.riscv.vfnmsub.mask.nxv2f32.nxv2f32(
<vscale x 2 x float> %0, <vscale x 2 x float> %0,
<vscale x 2 x float> %1, <vscale x 2 x float> %1,
<vscale x 2 x float> %2, <vscale x 2 x float> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
iXLen %4, iXLen 0); iXLen 0, iXLen %4, iXLen 0);
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 4 x float> @llvm.riscv.vfnmsub.nxv4f32.nxv4f32( declare <vscale x 4 x float> @llvm.riscv.vfnmsub.nxv4f32.nxv4f32(
<vscale x 4 x float>, <vscale x 4 x float>,
<vscale x 4 x float>, <vscale x 4 x float>,
<vscale x 4 x float>, <vscale x 4 x float>,
iXLen, iXLen, iXLen, iXLen);
iXLen);
define <vscale x 4 x float> @intrinsic_vfnmsub_vv_nxv4f32_nxv4f32_nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, <vscale x 4 x float> %2, iXLen %3) nounwind { define <vscale x 4 x float> @intrinsic_vfnmsub_vv_nxv4f32_nxv4f32_nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, <vscale x 4 x float> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfnmsub_vv_nxv4f32_nxv4f32_nxv4f32: ; CHECK-LABEL: intrinsic_vfnmsub_vv_nxv4f32_nxv4f32_nxv4f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, ma ; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, ma
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfnmsub.vv v8, v10, v12 ; CHECK-NEXT: vfnmsub.vv v8, v10, v12
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x float> @llvm.riscv.vfnmsub.nxv4f32.nxv4f32( %a = call <vscale x 4 x float> @llvm.riscv.vfnmsub.nxv4f32.nxv4f32(
<vscale x 4 x float> %0, <vscale x 4 x float> %0,
<vscale x 4 x float> %1, <vscale x 4 x float> %1,
<vscale x 4 x float> %2, <vscale x 4 x float> %2,
iXLen %3, iXLen 0) iXLen 0, iXLen %3, iXLen 0)
ret <vscale x 4 x float> %a ret <vscale x 4 x float> %a
} }
declare <vscale x 4 x float> @llvm.riscv.vfnmsub.mask.nxv4f32.nxv4f32( declare <vscale x 4 x float> @llvm.riscv.vfnmsub.mask.nxv4f32.nxv4f32(
<vscale x 4 x float>, <vscale x 4 x float>,
<vscale x 4 x float>, <vscale x 4 x float>,
<vscale x 4 x float>, <vscale x 4 x float>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
iXLen, iXLen); iXLen, iXLen, iXLen);
define <vscale x 4 x float> @intrinsic_vfnmsub_mask_vv_nxv4f32_nxv4f32_nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, <vscale x 4 x float> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind { define <vscale x 4 x float> @intrinsic_vfnmsub_mask_vv_nxv4f32_nxv4f32_nxv4f32(<vscale x 4 x float> %0, <vscale x 4 x float> %1, <vscale x 4 x float> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfnmsub_mask_vv_nxv4f32_nxv4f32_nxv4f32: ; CHECK-LABEL: intrinsic_vfnmsub_mask_vv_nxv4f32_nxv4f32_nxv4f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfnmsub.vv v8, v10, v12, v0.t ; CHECK-NEXT: vfnmsub.vv v8, v10, v12, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x float> @llvm.riscv.vfnmsub.mask.nxv4f32.nxv4f32( %a = call <vscale x 4 x float> @llvm.riscv.vfnmsub.mask.nxv4f32.nxv4f32(
<vscale x 4 x float> %0, <vscale x 4 x float> %0,
<vscale x 4 x float> %1, <vscale x 4 x float> %1,
<vscale x 4 x float> %2, <vscale x 4 x float> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
iXLen %4, iXLen 0); iXLen 0, iXLen %4, iXLen 0);
ret <vscale x 4 x float> %a ret <vscale x 4 x float> %a
} }
declare <vscale x 8 x float> @llvm.riscv.vfnmsub.nxv8f32.nxv8f32( declare <vscale x 8 x float> @llvm.riscv.vfnmsub.nxv8f32.nxv8f32(
<vscale x 8 x float>, <vscale x 8 x float>,
<vscale x 8 x float>, <vscale x 8 x float>,
<vscale x 8 x float>, <vscale x 8 x float>,
iXLen, iXLen, iXLen, iXLen);
iXLen);
define <vscale x 8 x float> @intrinsic_vfnmsub_vv_nxv8f32_nxv8f32_nxv8f32(<vscale x 8 x float> %0, <vscale x 8 x float> %1, <vscale x 8 x float> %2, iXLen %3) nounwind { define <vscale x 8 x float> @intrinsic_vfnmsub_vv_nxv8f32_nxv8f32_nxv8f32(<vscale x 8 x float> %0, <vscale x 8 x float> %1, <vscale x 8 x float> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfnmsub_vv_nxv8f32_nxv8f32_nxv8f32: ; CHECK-LABEL: intrinsic_vfnmsub_vv_nxv8f32_nxv8f32_nxv8f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, ma ; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, ma
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfnmsub.vv v8, v12, v16 ; CHECK-NEXT: vfnmsub.vv v8, v12, v16
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x float> @llvm.riscv.vfnmsub.nxv8f32.nxv8f32( %a = call <vscale x 8 x float> @llvm.riscv.vfnmsub.nxv8f32.nxv8f32(
<vscale x 8 x float> %0, <vscale x 8 x float> %0,
<vscale x 8 x float> %1, <vscale x 8 x float> %1,
<vscale x 8 x float> %2, <vscale x 8 x float> %2,
iXLen %3, iXLen 0) iXLen 0, iXLen %3, iXLen 0)
ret <vscale x 8 x float> %a ret <vscale x 8 x float> %a
} }
declare <vscale x 8 x float> @llvm.riscv.vfnmsub.mask.nxv8f32.nxv8f32( declare <vscale x 8 x float> @llvm.riscv.vfnmsub.mask.nxv8f32.nxv8f32(
<vscale x 8 x float>, <vscale x 8 x float>,
<vscale x 8 x float>, <vscale x 8 x float>,
<vscale x 8 x float>, <vscale x 8 x float>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
iXLen, iXLen); iXLen, iXLen, iXLen);
define <vscale x 8 x float> @intrinsic_vfnmsub_mask_vv_nxv8f32_nxv8f32_nxv8f32(<vscale x 8 x float> %0, <vscale x 8 x float> %1, <vscale x 8 x float> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind { define <vscale x 8 x float> @intrinsic_vfnmsub_mask_vv_nxv8f32_nxv8f32_nxv8f32(<vscale x 8 x float> %0, <vscale x 8 x float> %1, <vscale x 8 x float> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfnmsub_mask_vv_nxv8f32_nxv8f32_nxv8f32: ; CHECK-LABEL: intrinsic_vfnmsub_mask_vv_nxv8f32_nxv8f32_nxv8f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfnmsub.vv v8, v12, v16, v0.t ; CHECK-NEXT: vfnmsub.vv v8, v12, v16, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x float> @llvm.riscv.vfnmsub.mask.nxv8f32.nxv8f32( %a = call <vscale x 8 x float> @llvm.riscv.vfnmsub.mask.nxv8f32.nxv8f32(
<vscale x 8 x float> %0, <vscale x 8 x float> %0,
<vscale x 8 x float> %1, <vscale x 8 x float> %1,
<vscale x 8 x float> %2, <vscale x 8 x float> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
iXLen %4, iXLen 0); iXLen 0, iXLen %4, iXLen 0);
ret <vscale x 8 x float> %a ret <vscale x 8 x float> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vfnmsub.nxv1f64.nxv1f64( declare <vscale x 1 x double> @llvm.riscv.vfnmsub.nxv1f64.nxv1f64(
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 1 x double>, <vscale x 1 x double>,
iXLen, iXLen, iXLen, iXLen);
iXLen);
define <vscale x 1 x double> @intrinsic_vfnmsub_vv_nxv1f64_nxv1f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 1 x double> %1, <vscale x 1 x double> %2, iXLen %3) nounwind { define <vscale x 1 x double> @intrinsic_vfnmsub_vv_nxv1f64_nxv1f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 1 x double> %1, <vscale x 1 x double> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfnmsub_vv_nxv1f64_nxv1f64_nxv1f64: ; CHECK-LABEL: intrinsic_vfnmsub_vv_nxv1f64_nxv1f64_nxv1f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, ma ; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, ma
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfnmsub.vv v8, v9, v10 ; CHECK-NEXT: vfnmsub.vv v8, v9, v10
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfnmsub.nxv1f64.nxv1f64( %a = call <vscale x 1 x double> @llvm.riscv.vfnmsub.nxv1f64.nxv1f64(
<vscale x 1 x double> %0, <vscale x 1 x double> %0,
<vscale x 1 x double> %1, <vscale x 1 x double> %1,
<vscale x 1 x double> %2, <vscale x 1 x double> %2,
iXLen %3, iXLen 0) iXLen 0, iXLen %3, iXLen 0)
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vfnmsub.mask.nxv1f64.nxv1f64( declare <vscale x 1 x double> @llvm.riscv.vfnmsub.mask.nxv1f64.nxv1f64(
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
iXLen, iXLen); iXLen, iXLen, iXLen);
define <vscale x 1 x double> @intrinsic_vfnmsub_mask_vv_nxv1f64_nxv1f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 1 x double> %1, <vscale x 1 x double> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind { define <vscale x 1 x double> @intrinsic_vfnmsub_mask_vv_nxv1f64_nxv1f64_nxv1f64(<vscale x 1 x double> %0, <vscale x 1 x double> %1, <vscale x 1 x double> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfnmsub_mask_vv_nxv1f64_nxv1f64_nxv1f64: ; CHECK-LABEL: intrinsic_vfnmsub_mask_vv_nxv1f64_nxv1f64_nxv1f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, mu
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfnmsub.vv v8, v9, v10, v0.t ; CHECK-NEXT: vfnmsub.vv v8, v9, v10, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfnmsub.mask.nxv1f64.nxv1f64( %a = call <vscale x 1 x double> @llvm.riscv.vfnmsub.mask.nxv1f64.nxv1f64(
<vscale x 1 x double> %0, <vscale x 1 x double> %0,
<vscale x 1 x double> %1, <vscale x 1 x double> %1,
<vscale x 1 x double> %2, <vscale x 1 x double> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
iXLen %4, iXLen 0); iXLen 0, iXLen %4, iXLen 0);
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 2 x double> @llvm.riscv.vfnmsub.nxv2f64.nxv2f64( declare <vscale x 2 x double> @llvm.riscv.vfnmsub.nxv2f64.nxv2f64(
<vscale x 2 x double>, <vscale x 2 x double>,
<vscale x 2 x double>, <vscale x 2 x double>,
<vscale x 2 x double>, <vscale x 2 x double>,
iXLen, iXLen, iXLen, iXLen);
iXLen);
define <vscale x 2 x double> @intrinsic_vfnmsub_vv_nxv2f64_nxv2f64_nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1, <vscale x 2 x double> %2, iXLen %3) nounwind { define <vscale x 2 x double> @intrinsic_vfnmsub_vv_nxv2f64_nxv2f64_nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1, <vscale x 2 x double> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfnmsub_vv_nxv2f64_nxv2f64_nxv2f64: ; CHECK-LABEL: intrinsic_vfnmsub_vv_nxv2f64_nxv2f64_nxv2f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, ma ; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, ma
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfnmsub.vv v8, v10, v12 ; CHECK-NEXT: vfnmsub.vv v8, v10, v12
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x double> @llvm.riscv.vfnmsub.nxv2f64.nxv2f64( %a = call <vscale x 2 x double> @llvm.riscv.vfnmsub.nxv2f64.nxv2f64(
<vscale x 2 x double> %0, <vscale x 2 x double> %0,
<vscale x 2 x double> %1, <vscale x 2 x double> %1,
<vscale x 2 x double> %2, <vscale x 2 x double> %2,
iXLen %3, iXLen 0) iXLen 0, iXLen %3, iXLen 0)
ret <vscale x 2 x double> %a ret <vscale x 2 x double> %a
} }
declare <vscale x 2 x double> @llvm.riscv.vfnmsub.mask.nxv2f64.nxv2f64( declare <vscale x 2 x double> @llvm.riscv.vfnmsub.mask.nxv2f64.nxv2f64(
<vscale x 2 x double>, <vscale x 2 x double>,
<vscale x 2 x double>, <vscale x 2 x double>,
<vscale x 2 x double>, <vscale x 2 x double>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
iXLen, iXLen); iXLen, iXLen, iXLen);
define <vscale x 2 x double> @intrinsic_vfnmsub_mask_vv_nxv2f64_nxv2f64_nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1, <vscale x 2 x double> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind { define <vscale x 2 x double> @intrinsic_vfnmsub_mask_vv_nxv2f64_nxv2f64_nxv2f64(<vscale x 2 x double> %0, <vscale x 2 x double> %1, <vscale x 2 x double> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfnmsub_mask_vv_nxv2f64_nxv2f64_nxv2f64: ; CHECK-LABEL: intrinsic_vfnmsub_mask_vv_nxv2f64_nxv2f64_nxv2f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, mu
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfnmsub.vv v8, v10, v12, v0.t ; CHECK-NEXT: vfnmsub.vv v8, v10, v12, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x double> @llvm.riscv.vfnmsub.mask.nxv2f64.nxv2f64( %a = call <vscale x 2 x double> @llvm.riscv.vfnmsub.mask.nxv2f64.nxv2f64(
<vscale x 2 x double> %0, <vscale x 2 x double> %0,
<vscale x 2 x double> %1, <vscale x 2 x double> %1,
<vscale x 2 x double> %2, <vscale x 2 x double> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
iXLen %4, iXLen 0); iXLen 0, iXLen %4, iXLen 0);
ret <vscale x 2 x double> %a ret <vscale x 2 x double> %a
} }
declare <vscale x 4 x double> @llvm.riscv.vfnmsub.nxv4f64.nxv4f64( declare <vscale x 4 x double> @llvm.riscv.vfnmsub.nxv4f64.nxv4f64(
<vscale x 4 x double>, <vscale x 4 x double>,
<vscale x 4 x double>, <vscale x 4 x double>,
<vscale x 4 x double>, <vscale x 4 x double>,
iXLen, iXLen, iXLen, iXLen);
iXLen);
define <vscale x 4 x double> @intrinsic_vfnmsub_vv_nxv4f64_nxv4f64_nxv4f64(<vscale x 4 x double> %0, <vscale x 4 x double> %1, <vscale x 4 x double> %2, iXLen %3) nounwind { define <vscale x 4 x double> @intrinsic_vfnmsub_vv_nxv4f64_nxv4f64_nxv4f64(<vscale x 4 x double> %0, <vscale x 4 x double> %1, <vscale x 4 x double> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfnmsub_vv_nxv4f64_nxv4f64_nxv4f64: ; CHECK-LABEL: intrinsic_vfnmsub_vv_nxv4f64_nxv4f64_nxv4f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, ma ; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, ma
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfnmsub.vv v8, v12, v16 ; CHECK-NEXT: vfnmsub.vv v8, v12, v16
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x double> @llvm.riscv.vfnmsub.nxv4f64.nxv4f64( %a = call <vscale x 4 x double> @llvm.riscv.vfnmsub.nxv4f64.nxv4f64(
<vscale x 4 x double> %0, <vscale x 4 x double> %0,
<vscale x 4 x double> %1, <vscale x 4 x double> %1,
<vscale x 4 x double> %2, <vscale x 4 x double> %2,
iXLen %3, iXLen 0) iXLen 0, iXLen %3, iXLen 0)
ret <vscale x 4 x double> %a ret <vscale x 4 x double> %a
} }
declare <vscale x 4 x double> @llvm.riscv.vfnmsub.mask.nxv4f64.nxv4f64( declare <vscale x 4 x double> @llvm.riscv.vfnmsub.mask.nxv4f64.nxv4f64(
<vscale x 4 x double>, <vscale x 4 x double>,
<vscale x 4 x double>, <vscale x 4 x double>,
<vscale x 4 x double>, <vscale x 4 x double>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
iXLen, iXLen); iXLen, iXLen, iXLen);
define <vscale x 4 x double> @intrinsic_vfnmsub_mask_vv_nxv4f64_nxv4f64_nxv4f64(<vscale x 4 x double> %0, <vscale x 4 x double> %1, <vscale x 4 x double> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind { define <vscale x 4 x double> @intrinsic_vfnmsub_mask_vv_nxv4f64_nxv4f64_nxv4f64(<vscale x 4 x double> %0, <vscale x 4 x double> %1, <vscale x 4 x double> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfnmsub_mask_vv_nxv4f64_nxv4f64_nxv4f64: ; CHECK-LABEL: intrinsic_vfnmsub_mask_vv_nxv4f64_nxv4f64_nxv4f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, mu
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfnmsub.vv v8, v12, v16, v0.t ; CHECK-NEXT: vfnmsub.vv v8, v12, v16, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x double> @llvm.riscv.vfnmsub.mask.nxv4f64.nxv4f64( %a = call <vscale x 4 x double> @llvm.riscv.vfnmsub.mask.nxv4f64.nxv4f64(
<vscale x 4 x double> %0, <vscale x 4 x double> %0,
<vscale x 4 x double> %1, <vscale x 4 x double> %1,
<vscale x 4 x double> %2, <vscale x 4 x double> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
iXLen %4, iXLen 0); iXLen 0, iXLen %4, iXLen 0);
ret <vscale x 4 x double> %a ret <vscale x 4 x double> %a
} }
declare <vscale x 1 x half> @llvm.riscv.vfnmsub.nxv1f16.f16( declare <vscale x 1 x half> @llvm.riscv.vfnmsub.nxv1f16.f16(
<vscale x 1 x half>, <vscale x 1 x half>,
half, half,
<vscale x 1 x half>, <vscale x 1 x half>,
iXLen, iXLen, iXLen, iXLen);
iXLen);
define <vscale x 1 x half> @intrinsic_vfnmsub_vf_nxv1f16_f16_nxv1f16(<vscale x 1 x half> %0, half %1, <vscale x 1 x half> %2, iXLen %3) nounwind { define <vscale x 1 x half> @intrinsic_vfnmsub_vf_nxv1f16_f16_nxv1f16(<vscale x 1 x half> %0, half %1, <vscale x 1 x half> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfnmsub_vf_nxv1f16_f16_nxv1f16: ; CHECK-LABEL: intrinsic_vfnmsub_vf_nxv1f16_f16_nxv1f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, ma ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, ma
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfnmsub.vf v8, fa0, v9 ; CHECK-NEXT: vfnmsub.vf v8, fa0, v9
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x half> @llvm.riscv.vfnmsub.nxv1f16.f16( %a = call <vscale x 1 x half> @llvm.riscv.vfnmsub.nxv1f16.f16(
<vscale x 1 x half> %0, <vscale x 1 x half> %0,
half %1, half %1,
<vscale x 1 x half> %2, <vscale x 1 x half> %2,
iXLen %3, iXLen 0) iXLen 0, iXLen %3, iXLen 0)
ret <vscale x 1 x half> %a ret <vscale x 1 x half> %a
} }
declare <vscale x 1 x half> @llvm.riscv.vfnmsub.mask.nxv1f16.f16( declare <vscale x 1 x half> @llvm.riscv.vfnmsub.mask.nxv1f16.f16(
<vscale x 1 x half>, <vscale x 1 x half>,
half, half,
<vscale x 1 x half>, <vscale x 1 x half>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
iXLen, iXLen); iXLen, iXLen, iXLen);
define <vscale x 1 x half> @intrinsic_vfnmsub_mask_vf_nxv1f16_f16_nxv1f16(<vscale x 1 x half> %0, half %1, <vscale x 1 x half> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind { define <vscale x 1 x half> @intrinsic_vfnmsub_mask_vf_nxv1f16_f16_nxv1f16(<vscale x 1 x half> %0, half %1, <vscale x 1 x half> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfnmsub_mask_vf_nxv1f16_f16_nxv1f16: ; CHECK-LABEL: intrinsic_vfnmsub_mask_vf_nxv1f16_f16_nxv1f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf4, tu, mu
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfnmsub.vf v8, fa0, v9, v0.t ; CHECK-NEXT: vfnmsub.vf v8, fa0, v9, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x half> @llvm.riscv.vfnmsub.mask.nxv1f16.f16( %a = call <vscale x 1 x half> @llvm.riscv.vfnmsub.mask.nxv1f16.f16(
<vscale x 1 x half> %0, <vscale x 1 x half> %0,
half %1, half %1,
<vscale x 1 x half> %2, <vscale x 1 x half> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
iXLen %4, iXLen 0); iXLen 0, iXLen %4, iXLen 0);
ret <vscale x 1 x half> %a ret <vscale x 1 x half> %a
} }
declare <vscale x 2 x half> @llvm.riscv.vfnmsub.nxv2f16.f16( declare <vscale x 2 x half> @llvm.riscv.vfnmsub.nxv2f16.f16(
<vscale x 2 x half>, <vscale x 2 x half>,
half, half,
<vscale x 2 x half>, <vscale x 2 x half>,
iXLen, iXLen, iXLen, iXLen);
iXLen);
define <vscale x 2 x half> @intrinsic_vfnmsub_vf_nxv2f16_f16_nxv2f16(<vscale x 2 x half> %0, half %1, <vscale x 2 x half> %2, iXLen %3) nounwind { define <vscale x 2 x half> @intrinsic_vfnmsub_vf_nxv2f16_f16_nxv2f16(<vscale x 2 x half> %0, half %1, <vscale x 2 x half> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfnmsub_vf_nxv2f16_f16_nxv2f16: ; CHECK-LABEL: intrinsic_vfnmsub_vf_nxv2f16_f16_nxv2f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, ma ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, ma
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfnmsub.vf v8, fa0, v9 ; CHECK-NEXT: vfnmsub.vf v8, fa0, v9
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x half> @llvm.riscv.vfnmsub.nxv2f16.f16( %a = call <vscale x 2 x half> @llvm.riscv.vfnmsub.nxv2f16.f16(
<vscale x 2 x half> %0, <vscale x 2 x half> %0,
half %1, half %1,
<vscale x 2 x half> %2, <vscale x 2 x half> %2,
iXLen %3, iXLen 0) iXLen 0, iXLen %3, iXLen 0)
ret <vscale x 2 x half> %a ret <vscale x 2 x half> %a
} }
declare <vscale x 2 x half> @llvm.riscv.vfnmsub.mask.nxv2f16.f16( declare <vscale x 2 x half> @llvm.riscv.vfnmsub.mask.nxv2f16.f16(
<vscale x 2 x half>, <vscale x 2 x half>,
half, half,
<vscale x 2 x half>, <vscale x 2 x half>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
iXLen, iXLen); iXLen, iXLen, iXLen);
define <vscale x 2 x half> @intrinsic_vfnmsub_mask_vf_nxv2f16_f16_nxv2f16(<vscale x 2 x half> %0, half %1, <vscale x 2 x half> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind { define <vscale x 2 x half> @intrinsic_vfnmsub_mask_vf_nxv2f16_f16_nxv2f16(<vscale x 2 x half> %0, half %1, <vscale x 2 x half> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfnmsub_mask_vf_nxv2f16_f16_nxv2f16: ; CHECK-LABEL: intrinsic_vfnmsub_mask_vf_nxv2f16_f16_nxv2f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, mf2, tu, mu
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfnmsub.vf v8, fa0, v9, v0.t ; CHECK-NEXT: vfnmsub.vf v8, fa0, v9, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x half> @llvm.riscv.vfnmsub.mask.nxv2f16.f16( %a = call <vscale x 2 x half> @llvm.riscv.vfnmsub.mask.nxv2f16.f16(
<vscale x 2 x half> %0, <vscale x 2 x half> %0,
half %1, half %1,
<vscale x 2 x half> %2, <vscale x 2 x half> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
iXLen %4, iXLen 0); iXLen 0, iXLen %4, iXLen 0);
ret <vscale x 2 x half> %a ret <vscale x 2 x half> %a
} }
declare <vscale x 4 x half> @llvm.riscv.vfnmsub.nxv4f16.f16( declare <vscale x 4 x half> @llvm.riscv.vfnmsub.nxv4f16.f16(
<vscale x 4 x half>, <vscale x 4 x half>,
half, half,
<vscale x 4 x half>, <vscale x 4 x half>,
iXLen, iXLen, iXLen, iXLen);
iXLen);
define <vscale x 4 x half> @intrinsic_vfnmsub_vf_nxv4f16_f16_nxv4f16(<vscale x 4 x half> %0, half %1, <vscale x 4 x half> %2, iXLen %3) nounwind { define <vscale x 4 x half> @intrinsic_vfnmsub_vf_nxv4f16_f16_nxv4f16(<vscale x 4 x half> %0, half %1, <vscale x 4 x half> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfnmsub_vf_nxv4f16_f16_nxv4f16: ; CHECK-LABEL: intrinsic_vfnmsub_vf_nxv4f16_f16_nxv4f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, ma ; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, ma
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfnmsub.vf v8, fa0, v9 ; CHECK-NEXT: vfnmsub.vf v8, fa0, v9
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x half> @llvm.riscv.vfnmsub.nxv4f16.f16( %a = call <vscale x 4 x half> @llvm.riscv.vfnmsub.nxv4f16.f16(
<vscale x 4 x half> %0, <vscale x 4 x half> %0,
half %1, half %1,
<vscale x 4 x half> %2, <vscale x 4 x half> %2,
iXLen %3, iXLen 0) iXLen 0, iXLen %3, iXLen 0)
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 4 x half> @llvm.riscv.vfnmsub.mask.nxv4f16.f16( declare <vscale x 4 x half> @llvm.riscv.vfnmsub.mask.nxv4f16.f16(
<vscale x 4 x half>, <vscale x 4 x half>,
half, half,
<vscale x 4 x half>, <vscale x 4 x half>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
iXLen, iXLen); iXLen, iXLen, iXLen);
define <vscale x 4 x half> @intrinsic_vfnmsub_mask_vf_nxv4f16_f16_nxv4f16(<vscale x 4 x half> %0, half %1, <vscale x 4 x half> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind { define <vscale x 4 x half> @intrinsic_vfnmsub_mask_vf_nxv4f16_f16_nxv4f16(<vscale x 4 x half> %0, half %1, <vscale x 4 x half> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfnmsub_mask_vf_nxv4f16_f16_nxv4f16: ; CHECK-LABEL: intrinsic_vfnmsub_mask_vf_nxv4f16_f16_nxv4f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, mu
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfnmsub.vf v8, fa0, v9, v0.t ; CHECK-NEXT: vfnmsub.vf v8, fa0, v9, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x half> @llvm.riscv.vfnmsub.mask.nxv4f16.f16( %a = call <vscale x 4 x half> @llvm.riscv.vfnmsub.mask.nxv4f16.f16(
<vscale x 4 x half> %0, <vscale x 4 x half> %0,
half %1, half %1,
<vscale x 4 x half> %2, <vscale x 4 x half> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
iXLen %4, iXLen 0); iXLen 0, iXLen %4, iXLen 0);
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 8 x half> @llvm.riscv.vfnmsub.nxv8f16.f16( declare <vscale x 8 x half> @llvm.riscv.vfnmsub.nxv8f16.f16(
<vscale x 8 x half>, <vscale x 8 x half>,
half, half,
<vscale x 8 x half>, <vscale x 8 x half>,
iXLen, iXLen, iXLen, iXLen);
iXLen);
define <vscale x 8 x half> @intrinsic_vfnmsub_vf_nxv8f16_f16_nxv8f16(<vscale x 8 x half> %0, half %1, <vscale x 8 x half> %2, iXLen %3) nounwind { define <vscale x 8 x half> @intrinsic_vfnmsub_vf_nxv8f16_f16_nxv8f16(<vscale x 8 x half> %0, half %1, <vscale x 8 x half> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfnmsub_vf_nxv8f16_f16_nxv8f16: ; CHECK-LABEL: intrinsic_vfnmsub_vf_nxv8f16_f16_nxv8f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, ma ; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, ma
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfnmsub.vf v8, fa0, v10 ; CHECK-NEXT: vfnmsub.vf v8, fa0, v10
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x half> @llvm.riscv.vfnmsub.nxv8f16.f16( %a = call <vscale x 8 x half> @llvm.riscv.vfnmsub.nxv8f16.f16(
<vscale x 8 x half> %0, <vscale x 8 x half> %0,
half %1, half %1,
<vscale x 8 x half> %2, <vscale x 8 x half> %2,
iXLen %3, iXLen 0) iXLen 0, iXLen %3, iXLen 0)
ret <vscale x 8 x half> %a ret <vscale x 8 x half> %a
} }
declare <vscale x 8 x half> @llvm.riscv.vfnmsub.mask.nxv8f16.f16( declare <vscale x 8 x half> @llvm.riscv.vfnmsub.mask.nxv8f16.f16(
<vscale x 8 x half>, <vscale x 8 x half>,
half, half,
<vscale x 8 x half>, <vscale x 8 x half>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
iXLen, iXLen); iXLen, iXLen, iXLen);
define <vscale x 8 x half> @intrinsic_vfnmsub_mask_vf_nxv8f16_f16_nxv8f16(<vscale x 8 x half> %0, half %1, <vscale x 8 x half> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind { define <vscale x 8 x half> @intrinsic_vfnmsub_mask_vf_nxv8f16_f16_nxv8f16(<vscale x 8 x half> %0, half %1, <vscale x 8 x half> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfnmsub_mask_vf_nxv8f16_f16_nxv8f16: ; CHECK-LABEL: intrinsic_vfnmsub_mask_vf_nxv8f16_f16_nxv8f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m2, tu, mu
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfnmsub.vf v8, fa0, v10, v0.t ; CHECK-NEXT: vfnmsub.vf v8, fa0, v10, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x half> @llvm.riscv.vfnmsub.mask.nxv8f16.f16( %a = call <vscale x 8 x half> @llvm.riscv.vfnmsub.mask.nxv8f16.f16(
<vscale x 8 x half> %0, <vscale x 8 x half> %0,
half %1, half %1,
<vscale x 8 x half> %2, <vscale x 8 x half> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
iXLen %4, iXLen 0); iXLen 0, iXLen %4, iXLen 0);
ret <vscale x 8 x half> %a ret <vscale x 8 x half> %a
} }
declare <vscale x 16 x half> @llvm.riscv.vfnmsub.nxv16f16.f16( declare <vscale x 16 x half> @llvm.riscv.vfnmsub.nxv16f16.f16(
<vscale x 16 x half>, <vscale x 16 x half>,
half, half,
<vscale x 16 x half>, <vscale x 16 x half>,
iXLen, iXLen, iXLen, iXLen);
iXLen);
define <vscale x 16 x half> @intrinsic_vfnmsub_vf_nxv16f16_f16_nxv16f16(<vscale x 16 x half> %0, half %1, <vscale x 16 x half> %2, iXLen %3) nounwind { define <vscale x 16 x half> @intrinsic_vfnmsub_vf_nxv16f16_f16_nxv16f16(<vscale x 16 x half> %0, half %1, <vscale x 16 x half> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfnmsub_vf_nxv16f16_f16_nxv16f16: ; CHECK-LABEL: intrinsic_vfnmsub_vf_nxv16f16_f16_nxv16f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, ma ; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, ma
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfnmsub.vf v8, fa0, v12 ; CHECK-NEXT: vfnmsub.vf v8, fa0, v12
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x half> @llvm.riscv.vfnmsub.nxv16f16.f16( %a = call <vscale x 16 x half> @llvm.riscv.vfnmsub.nxv16f16.f16(
<vscale x 16 x half> %0, <vscale x 16 x half> %0,
half %1, half %1,
<vscale x 16 x half> %2, <vscale x 16 x half> %2,
iXLen %3, iXLen 0) iXLen 0, iXLen %3, iXLen 0)
ret <vscale x 16 x half> %a ret <vscale x 16 x half> %a
} }
declare <vscale x 16 x half> @llvm.riscv.vfnmsub.mask.nxv16f16.f16( declare <vscale x 16 x half> @llvm.riscv.vfnmsub.mask.nxv16f16.f16(
<vscale x 16 x half>, <vscale x 16 x half>,
half, half,
<vscale x 16 x half>, <vscale x 16 x half>,
<vscale x 16 x i1>, <vscale x 16 x i1>,
iXLen, iXLen); iXLen, iXLen, iXLen);
define <vscale x 16 x half> @intrinsic_vfnmsub_mask_vf_nxv16f16_f16_nxv16f16(<vscale x 16 x half> %0, half %1, <vscale x 16 x half> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind { define <vscale x 16 x half> @intrinsic_vfnmsub_mask_vf_nxv16f16_f16_nxv16f16(<vscale x 16 x half> %0, half %1, <vscale x 16 x half> %2, <vscale x 16 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfnmsub_mask_vf_nxv16f16_f16_nxv16f16: ; CHECK-LABEL: intrinsic_vfnmsub_mask_vf_nxv16f16_f16_nxv16f16:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e16, m4, tu, mu
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfnmsub.vf v8, fa0, v12, v0.t ; CHECK-NEXT: vfnmsub.vf v8, fa0, v12, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 16 x half> @llvm.riscv.vfnmsub.mask.nxv16f16.f16( %a = call <vscale x 16 x half> @llvm.riscv.vfnmsub.mask.nxv16f16.f16(
<vscale x 16 x half> %0, <vscale x 16 x half> %0,
half %1, half %1,
<vscale x 16 x half> %2, <vscale x 16 x half> %2,
<vscale x 16 x i1> %3, <vscale x 16 x i1> %3,
iXLen %4, iXLen 0); iXLen 0, iXLen %4, iXLen 0);
ret <vscale x 16 x half> %a ret <vscale x 16 x half> %a
} }
declare <vscale x 1 x float> @llvm.riscv.vfnmsub.nxv1f32.f32( declare <vscale x 1 x float> @llvm.riscv.vfnmsub.nxv1f32.f32(
<vscale x 1 x float>, <vscale x 1 x float>,
float, float,
<vscale x 1 x float>, <vscale x 1 x float>,
iXLen, iXLen, iXLen, iXLen);
iXLen);
define <vscale x 1 x float> @intrinsic_vfnmsub_vf_nxv1f32_f32_nxv1f32(<vscale x 1 x float> %0, float %1, <vscale x 1 x float> %2, iXLen %3) nounwind { define <vscale x 1 x float> @intrinsic_vfnmsub_vf_nxv1f32_f32_nxv1f32(<vscale x 1 x float> %0, float %1, <vscale x 1 x float> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfnmsub_vf_nxv1f32_f32_nxv1f32: ; CHECK-LABEL: intrinsic_vfnmsub_vf_nxv1f32_f32_nxv1f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, ma ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, ma
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfnmsub.vf v8, fa0, v9 ; CHECK-NEXT: vfnmsub.vf v8, fa0, v9
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x float> @llvm.riscv.vfnmsub.nxv1f32.f32( %a = call <vscale x 1 x float> @llvm.riscv.vfnmsub.nxv1f32.f32(
<vscale x 1 x float> %0, <vscale x 1 x float> %0,
float %1, float %1,
<vscale x 1 x float> %2, <vscale x 1 x float> %2,
iXLen %3, iXLen 0) iXLen 0, iXLen %3, iXLen 0)
ret <vscale x 1 x float> %a ret <vscale x 1 x float> %a
} }
declare <vscale x 1 x float> @llvm.riscv.vfnmsub.mask.nxv1f32.f32( declare <vscale x 1 x float> @llvm.riscv.vfnmsub.mask.nxv1f32.f32(
<vscale x 1 x float>, <vscale x 1 x float>,
float, float,
<vscale x 1 x float>, <vscale x 1 x float>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
iXLen, iXLen); iXLen, iXLen, iXLen);
define <vscale x 1 x float> @intrinsic_vfnmsub_mask_vf_nxv1f32_f32_nxv1f32(<vscale x 1 x float> %0, float %1, <vscale x 1 x float> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind { define <vscale x 1 x float> @intrinsic_vfnmsub_mask_vf_nxv1f32_f32_nxv1f32(<vscale x 1 x float> %0, float %1, <vscale x 1 x float> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfnmsub_mask_vf_nxv1f32_f32_nxv1f32: ; CHECK-LABEL: intrinsic_vfnmsub_mask_vf_nxv1f32_f32_nxv1f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, mf2, tu, mu
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfnmsub.vf v8, fa0, v9, v0.t ; CHECK-NEXT: vfnmsub.vf v8, fa0, v9, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x float> @llvm.riscv.vfnmsub.mask.nxv1f32.f32( %a = call <vscale x 1 x float> @llvm.riscv.vfnmsub.mask.nxv1f32.f32(
<vscale x 1 x float> %0, <vscale x 1 x float> %0,
float %1, float %1,
<vscale x 1 x float> %2, <vscale x 1 x float> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
iXLen %4, iXLen 0); iXLen 0, iXLen %4, iXLen 0);
ret <vscale x 1 x float> %a ret <vscale x 1 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vfnmsub.nxv2f32.f32( declare <vscale x 2 x float> @llvm.riscv.vfnmsub.nxv2f32.f32(
<vscale x 2 x float>, <vscale x 2 x float>,
float, float,
<vscale x 2 x float>, <vscale x 2 x float>,
iXLen, iXLen, iXLen, iXLen);
iXLen);
define <vscale x 2 x float> @intrinsic_vfnmsub_vf_nxv2f32_f32_nxv2f32(<vscale x 2 x float> %0, float %1, <vscale x 2 x float> %2, iXLen %3) nounwind { define <vscale x 2 x float> @intrinsic_vfnmsub_vf_nxv2f32_f32_nxv2f32(<vscale x 2 x float> %0, float %1, <vscale x 2 x float> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfnmsub_vf_nxv2f32_f32_nxv2f32: ; CHECK-LABEL: intrinsic_vfnmsub_vf_nxv2f32_f32_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, ma ; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, ma
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfnmsub.vf v8, fa0, v9 ; CHECK-NEXT: vfnmsub.vf v8, fa0, v9
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfnmsub.nxv2f32.f32( %a = call <vscale x 2 x float> @llvm.riscv.vfnmsub.nxv2f32.f32(
<vscale x 2 x float> %0, <vscale x 2 x float> %0,
float %1, float %1,
<vscale x 2 x float> %2, <vscale x 2 x float> %2,
iXLen %3, iXLen 0) iXLen 0, iXLen %3, iXLen 0)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 2 x float> @llvm.riscv.vfnmsub.mask.nxv2f32.f32( declare <vscale x 2 x float> @llvm.riscv.vfnmsub.mask.nxv2f32.f32(
<vscale x 2 x float>, <vscale x 2 x float>,
float, float,
<vscale x 2 x float>, <vscale x 2 x float>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
iXLen, iXLen); iXLen, iXLen, iXLen);
define <vscale x 2 x float> @intrinsic_vfnmsub_mask_vf_nxv2f32_f32_nxv2f32(<vscale x 2 x float> %0, float %1, <vscale x 2 x float> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind { define <vscale x 2 x float> @intrinsic_vfnmsub_mask_vf_nxv2f32_f32_nxv2f32(<vscale x 2 x float> %0, float %1, <vscale x 2 x float> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfnmsub_mask_vf_nxv2f32_f32_nxv2f32: ; CHECK-LABEL: intrinsic_vfnmsub_mask_vf_nxv2f32_f32_nxv2f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, mu
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfnmsub.vf v8, fa0, v9, v0.t ; CHECK-NEXT: vfnmsub.vf v8, fa0, v9, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x float> @llvm.riscv.vfnmsub.mask.nxv2f32.f32( %a = call <vscale x 2 x float> @llvm.riscv.vfnmsub.mask.nxv2f32.f32(
<vscale x 2 x float> %0, <vscale x 2 x float> %0,
float %1, float %1,
<vscale x 2 x float> %2, <vscale x 2 x float> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
iXLen %4, iXLen 0); iXLen 0, iXLen %4, iXLen 0);
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 4 x float> @llvm.riscv.vfnmsub.nxv4f32.f32( declare <vscale x 4 x float> @llvm.riscv.vfnmsub.nxv4f32.f32(
<vscale x 4 x float>, <vscale x 4 x float>,
float, float,
<vscale x 4 x float>, <vscale x 4 x float>,
iXLen, iXLen, iXLen, iXLen);
iXLen);
define <vscale x 4 x float> @intrinsic_vfnmsub_vf_nxv4f32_f32_nxv4f32(<vscale x 4 x float> %0, float %1, <vscale x 4 x float> %2, iXLen %3) nounwind { define <vscale x 4 x float> @intrinsic_vfnmsub_vf_nxv4f32_f32_nxv4f32(<vscale x 4 x float> %0, float %1, <vscale x 4 x float> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfnmsub_vf_nxv4f32_f32_nxv4f32: ; CHECK-LABEL: intrinsic_vfnmsub_vf_nxv4f32_f32_nxv4f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, ma ; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, ma
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfnmsub.vf v8, fa0, v10 ; CHECK-NEXT: vfnmsub.vf v8, fa0, v10
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x float> @llvm.riscv.vfnmsub.nxv4f32.f32( %a = call <vscale x 4 x float> @llvm.riscv.vfnmsub.nxv4f32.f32(
<vscale x 4 x float> %0, <vscale x 4 x float> %0,
float %1, float %1,
<vscale x 4 x float> %2, <vscale x 4 x float> %2,
iXLen %3, iXLen 0) iXLen 0, iXLen %3, iXLen 0)
ret <vscale x 4 x float> %a ret <vscale x 4 x float> %a
} }
declare <vscale x 4 x float> @llvm.riscv.vfnmsub.mask.nxv4f32.f32( declare <vscale x 4 x float> @llvm.riscv.vfnmsub.mask.nxv4f32.f32(
<vscale x 4 x float>, <vscale x 4 x float>,
float, float,
<vscale x 4 x float>, <vscale x 4 x float>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
iXLen, iXLen); iXLen, iXLen, iXLen);
define <vscale x 4 x float> @intrinsic_vfnmsub_mask_vf_nxv4f32_f32_nxv4f32(<vscale x 4 x float> %0, float %1, <vscale x 4 x float> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind { define <vscale x 4 x float> @intrinsic_vfnmsub_mask_vf_nxv4f32_f32_nxv4f32(<vscale x 4 x float> %0, float %1, <vscale x 4 x float> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfnmsub_mask_vf_nxv4f32_f32_nxv4f32: ; CHECK-LABEL: intrinsic_vfnmsub_mask_vf_nxv4f32_f32_nxv4f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m2, tu, mu
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfnmsub.vf v8, fa0, v10, v0.t ; CHECK-NEXT: vfnmsub.vf v8, fa0, v10, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x float> @llvm.riscv.vfnmsub.mask.nxv4f32.f32( %a = call <vscale x 4 x float> @llvm.riscv.vfnmsub.mask.nxv4f32.f32(
<vscale x 4 x float> %0, <vscale x 4 x float> %0,
float %1, float %1,
<vscale x 4 x float> %2, <vscale x 4 x float> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
iXLen %4, iXLen 0); iXLen 0, iXLen %4, iXLen 0);
ret <vscale x 4 x float> %a ret <vscale x 4 x float> %a
} }
declare <vscale x 8 x float> @llvm.riscv.vfnmsub.nxv8f32.f32( declare <vscale x 8 x float> @llvm.riscv.vfnmsub.nxv8f32.f32(
<vscale x 8 x float>, <vscale x 8 x float>,
float, float,
<vscale x 8 x float>, <vscale x 8 x float>,
iXLen, iXLen, iXLen, iXLen);
iXLen);
define <vscale x 8 x float> @intrinsic_vfnmsub_vf_nxv8f32_f32_nxv8f32(<vscale x 8 x float> %0, float %1, <vscale x 8 x float> %2, iXLen %3) nounwind { define <vscale x 8 x float> @intrinsic_vfnmsub_vf_nxv8f32_f32_nxv8f32(<vscale x 8 x float> %0, float %1, <vscale x 8 x float> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfnmsub_vf_nxv8f32_f32_nxv8f32: ; CHECK-LABEL: intrinsic_vfnmsub_vf_nxv8f32_f32_nxv8f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, ma ; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, ma
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfnmsub.vf v8, fa0, v12 ; CHECK-NEXT: vfnmsub.vf v8, fa0, v12
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x float> @llvm.riscv.vfnmsub.nxv8f32.f32( %a = call <vscale x 8 x float> @llvm.riscv.vfnmsub.nxv8f32.f32(
<vscale x 8 x float> %0, <vscale x 8 x float> %0,
float %1, float %1,
<vscale x 8 x float> %2, <vscale x 8 x float> %2,
iXLen %3, iXLen 0) iXLen 0, iXLen %3, iXLen 0)
ret <vscale x 8 x float> %a ret <vscale x 8 x float> %a
} }
declare <vscale x 8 x float> @llvm.riscv.vfnmsub.mask.nxv8f32.f32( declare <vscale x 8 x float> @llvm.riscv.vfnmsub.mask.nxv8f32.f32(
<vscale x 8 x float>, <vscale x 8 x float>,
float, float,
<vscale x 8 x float>, <vscale x 8 x float>,
<vscale x 8 x i1>, <vscale x 8 x i1>,
iXLen, iXLen); iXLen, iXLen, iXLen);
define <vscale x 8 x float> @intrinsic_vfnmsub_mask_vf_nxv8f32_f32_nxv8f32(<vscale x 8 x float> %0, float %1, <vscale x 8 x float> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind { define <vscale x 8 x float> @intrinsic_vfnmsub_mask_vf_nxv8f32_f32_nxv8f32(<vscale x 8 x float> %0, float %1, <vscale x 8 x float> %2, <vscale x 8 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfnmsub_mask_vf_nxv8f32_f32_nxv8f32: ; CHECK-LABEL: intrinsic_vfnmsub_mask_vf_nxv8f32_f32_nxv8f32:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e32, m4, tu, mu
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfnmsub.vf v8, fa0, v12, v0.t ; CHECK-NEXT: vfnmsub.vf v8, fa0, v12, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 8 x float> @llvm.riscv.vfnmsub.mask.nxv8f32.f32( %a = call <vscale x 8 x float> @llvm.riscv.vfnmsub.mask.nxv8f32.f32(
<vscale x 8 x float> %0, <vscale x 8 x float> %0,
float %1, float %1,
<vscale x 8 x float> %2, <vscale x 8 x float> %2,
<vscale x 8 x i1> %3, <vscale x 8 x i1> %3,
iXLen %4, iXLen 0); iXLen 0, iXLen %4, iXLen 0);
ret <vscale x 8 x float> %a ret <vscale x 8 x float> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vfnmsub.nxv1f64.f64( declare <vscale x 1 x double> @llvm.riscv.vfnmsub.nxv1f64.f64(
<vscale x 1 x double>, <vscale x 1 x double>,
double, double,
<vscale x 1 x double>, <vscale x 1 x double>,
iXLen, iXLen, iXLen, iXLen);
iXLen);
define <vscale x 1 x double> @intrinsic_vfnmsub_vf_nxv1f64_f64_nxv1f64(<vscale x 1 x double> %0, double %1, <vscale x 1 x double> %2, iXLen %3) nounwind { define <vscale x 1 x double> @intrinsic_vfnmsub_vf_nxv1f64_f64_nxv1f64(<vscale x 1 x double> %0, double %1, <vscale x 1 x double> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfnmsub_vf_nxv1f64_f64_nxv1f64: ; CHECK-LABEL: intrinsic_vfnmsub_vf_nxv1f64_f64_nxv1f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, ma ; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, ma
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfnmsub.vf v8, fa0, v9 ; CHECK-NEXT: vfnmsub.vf v8, fa0, v9
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfnmsub.nxv1f64.f64( %a = call <vscale x 1 x double> @llvm.riscv.vfnmsub.nxv1f64.f64(
<vscale x 1 x double> %0, <vscale x 1 x double> %0,
double %1, double %1,
<vscale x 1 x double> %2, <vscale x 1 x double> %2,
iXLen %3, iXLen 0) iXLen 0, iXLen %3, iXLen 0)
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 1 x double> @llvm.riscv.vfnmsub.mask.nxv1f64.f64( declare <vscale x 1 x double> @llvm.riscv.vfnmsub.mask.nxv1f64.f64(
<vscale x 1 x double>, <vscale x 1 x double>,
double, double,
<vscale x 1 x double>, <vscale x 1 x double>,
<vscale x 1 x i1>, <vscale x 1 x i1>,
iXLen, iXLen); iXLen, iXLen, iXLen);
define <vscale x 1 x double> @intrinsic_vfnmsub_mask_vf_nxv1f64_f64_nxv1f64(<vscale x 1 x double> %0, double %1, <vscale x 1 x double> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind { define <vscale x 1 x double> @intrinsic_vfnmsub_mask_vf_nxv1f64_f64_nxv1f64(<vscale x 1 x double> %0, double %1, <vscale x 1 x double> %2, <vscale x 1 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfnmsub_mask_vf_nxv1f64_f64_nxv1f64: ; CHECK-LABEL: intrinsic_vfnmsub_mask_vf_nxv1f64_f64_nxv1f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m1, tu, mu
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfnmsub.vf v8, fa0, v9, v0.t ; CHECK-NEXT: vfnmsub.vf v8, fa0, v9, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 1 x double> @llvm.riscv.vfnmsub.mask.nxv1f64.f64( %a = call <vscale x 1 x double> @llvm.riscv.vfnmsub.mask.nxv1f64.f64(
<vscale x 1 x double> %0, <vscale x 1 x double> %0,
double %1, double %1,
<vscale x 1 x double> %2, <vscale x 1 x double> %2,
<vscale x 1 x i1> %3, <vscale x 1 x i1> %3,
iXLen %4, iXLen 0); iXLen 0, iXLen %4, iXLen 0);
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 2 x double> @llvm.riscv.vfnmsub.nxv2f64.f64( declare <vscale x 2 x double> @llvm.riscv.vfnmsub.nxv2f64.f64(
<vscale x 2 x double>, <vscale x 2 x double>,
double, double,
<vscale x 2 x double>, <vscale x 2 x double>,
iXLen, iXLen, iXLen, iXLen);
iXLen);
define <vscale x 2 x double> @intrinsic_vfnmsub_vf_nxv2f64_f64_nxv2f64(<vscale x 2 x double> %0, double %1, <vscale x 2 x double> %2, iXLen %3) nounwind { define <vscale x 2 x double> @intrinsic_vfnmsub_vf_nxv2f64_f64_nxv2f64(<vscale x 2 x double> %0, double %1, <vscale x 2 x double> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfnmsub_vf_nxv2f64_f64_nxv2f64: ; CHECK-LABEL: intrinsic_vfnmsub_vf_nxv2f64_f64_nxv2f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, ma ; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, ma
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfnmsub.vf v8, fa0, v10 ; CHECK-NEXT: vfnmsub.vf v8, fa0, v10
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x double> @llvm.riscv.vfnmsub.nxv2f64.f64( %a = call <vscale x 2 x double> @llvm.riscv.vfnmsub.nxv2f64.f64(
<vscale x 2 x double> %0, <vscale x 2 x double> %0,
double %1, double %1,
<vscale x 2 x double> %2, <vscale x 2 x double> %2,
iXLen %3, iXLen 0) iXLen 0, iXLen %3, iXLen 0)
ret <vscale x 2 x double> %a ret <vscale x 2 x double> %a
} }
declare <vscale x 2 x double> @llvm.riscv.vfnmsub.mask.nxv2f64.f64( declare <vscale x 2 x double> @llvm.riscv.vfnmsub.mask.nxv2f64.f64(
<vscale x 2 x double>, <vscale x 2 x double>,
double, double,
<vscale x 2 x double>, <vscale x 2 x double>,
<vscale x 2 x i1>, <vscale x 2 x i1>,
iXLen, iXLen); iXLen, iXLen, iXLen);
define <vscale x 2 x double> @intrinsic_vfnmsub_mask_vf_nxv2f64_f64_nxv2f64(<vscale x 2 x double> %0, double %1, <vscale x 2 x double> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind { define <vscale x 2 x double> @intrinsic_vfnmsub_mask_vf_nxv2f64_f64_nxv2f64(<vscale x 2 x double> %0, double %1, <vscale x 2 x double> %2, <vscale x 2 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfnmsub_mask_vf_nxv2f64_f64_nxv2f64: ; CHECK-LABEL: intrinsic_vfnmsub_mask_vf_nxv2f64_f64_nxv2f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m2, tu, mu
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfnmsub.vf v8, fa0, v10, v0.t ; CHECK-NEXT: vfnmsub.vf v8, fa0, v10, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 2 x double> @llvm.riscv.vfnmsub.mask.nxv2f64.f64( %a = call <vscale x 2 x double> @llvm.riscv.vfnmsub.mask.nxv2f64.f64(
<vscale x 2 x double> %0, <vscale x 2 x double> %0,
double %1, double %1,
<vscale x 2 x double> %2, <vscale x 2 x double> %2,
<vscale x 2 x i1> %3, <vscale x 2 x i1> %3,
iXLen %4, iXLen 0); iXLen 0, iXLen %4, iXLen 0);
ret <vscale x 2 x double> %a ret <vscale x 2 x double> %a
} }
declare <vscale x 4 x double> @llvm.riscv.vfnmsub.nxv4f64.f64( declare <vscale x 4 x double> @llvm.riscv.vfnmsub.nxv4f64.f64(
<vscale x 4 x double>, <vscale x 4 x double>,
double, double,
<vscale x 4 x double>, <vscale x 4 x double>,
iXLen, iXLen, iXLen, iXLen);
iXLen);
define <vscale x 4 x double> @intrinsic_vfnmsub_vf_nxv4f64_f64_nxv4f64(<vscale x 4 x double> %0, double %1, <vscale x 4 x double> %2, iXLen %3) nounwind { define <vscale x 4 x double> @intrinsic_vfnmsub_vf_nxv4f64_f64_nxv4f64(<vscale x 4 x double> %0, double %1, <vscale x 4 x double> %2, iXLen %3) nounwind {
; CHECK-LABEL: intrinsic_vfnmsub_vf_nxv4f64_f64_nxv4f64: ; CHECK-LABEL: intrinsic_vfnmsub_vf_nxv4f64_f64_nxv4f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, ma ; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, ma
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfnmsub.vf v8, fa0, v12 ; CHECK-NEXT: vfnmsub.vf v8, fa0, v12
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x double> @llvm.riscv.vfnmsub.nxv4f64.f64( %a = call <vscale x 4 x double> @llvm.riscv.vfnmsub.nxv4f64.f64(
<vscale x 4 x double> %0, <vscale x 4 x double> %0,
double %1, double %1,
<vscale x 4 x double> %2, <vscale x 4 x double> %2,
iXLen %3, iXLen 0) iXLen 0, iXLen %3, iXLen 0)
ret <vscale x 4 x double> %a ret <vscale x 4 x double> %a
} }
declare <vscale x 4 x double> @llvm.riscv.vfnmsub.mask.nxv4f64.f64( declare <vscale x 4 x double> @llvm.riscv.vfnmsub.mask.nxv4f64.f64(
<vscale x 4 x double>, <vscale x 4 x double>,
double, double,
<vscale x 4 x double>, <vscale x 4 x double>,
<vscale x 4 x i1>, <vscale x 4 x i1>,
iXLen, iXLen); iXLen, iXLen, iXLen);
define <vscale x 4 x double> @intrinsic_vfnmsub_mask_vf_nxv4f64_f64_nxv4f64(<vscale x 4 x double> %0, double %1, <vscale x 4 x double> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind { define <vscale x 4 x double> @intrinsic_vfnmsub_mask_vf_nxv4f64_f64_nxv4f64(<vscale x 4 x double> %0, double %1, <vscale x 4 x double> %2, <vscale x 4 x i1> %3, iXLen %4) nounwind {
; CHECK-LABEL: intrinsic_vfnmsub_mask_vf_nxv4f64_f64_nxv4f64: ; CHECK-LABEL: intrinsic_vfnmsub_mask_vf_nxv4f64_f64_nxv4f64:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, mu ; CHECK-NEXT: vsetvli zero, a0, e64, m4, tu, mu
; CHECK-NEXT: fsrmi a0, 0
; CHECK-NEXT: vfnmsub.vf v8, fa0, v12, v0.t ; CHECK-NEXT: vfnmsub.vf v8, fa0, v12, v0.t
; CHECK-NEXT: fsrm a0
; CHECK-NEXT: ret ; CHECK-NEXT: ret
entry: entry:
%a = call <vscale x 4 x double> @llvm.riscv.vfnmsub.mask.nxv4f64.f64( %a = call <vscale x 4 x double> @llvm.riscv.vfnmsub.mask.nxv4f64.f64(
<vscale x 4 x double> %0, <vscale x 4 x double> %0,
double %1, double %1,
<vscale x 4 x double> %2, <vscale x 4 x double> %2,
<vscale x 4 x i1> %3, <vscale x 4 x i1> %3,
iXLen %4, iXLen 0); iXLen 0, iXLen %4, iXLen 0);
ret <vscale x 4 x double> %a ret <vscale x 4 x double> %a
} }

llvm/test/CodeGen/RISCV/rvv/vsetvli-insert-crossbb.ll

Show First 20 Lines • Show All 469 Lines • ▼ Show 20 Linesfor.body: ; preds = %for.body, %entry
%n.addr.016 = phi i64 [ %sub, %for.body ], [ %n, %entry ] %n.addr.016 = phi i64 [ %sub, %for.body ], [ %n, %entry ]
%x.addr.015 = phi float* [ %add.ptr, %for.body ], [ %x, %entry ] %x.addr.015 = phi float* [ %add.ptr, %for.body ], [ %x, %entry ]
%y.addr.014 = phi float* [ %add.ptr1, %for.body ], [ %y, %entry ] %y.addr.014 = phi float* [ %add.ptr1, %for.body ], [ %y, %entry ]
%2 = bitcast float* %x.addr.015 to <vscale x 16 x float>* %2 = bitcast float* %x.addr.015 to <vscale x 16 x float>*
%3 = tail call <vscale x 16 x float> @llvm.riscv.vle.nxv16f32.i64(<vscale x 16 x float> undef, <vscale x 16 x float>* %2, i64 %1) %3 = tail call <vscale x 16 x float> @llvm.riscv.vle.nxv16f32.i64(<vscale x 16 x float> undef, <vscale x 16 x float>* %2, i64 %1)
%add.ptr = getelementptr inbounds float, float* %x.addr.015, i64 %1 %add.ptr = getelementptr inbounds float, float* %x.addr.015, i64 %1
%4 = bitcast float* %y.addr.014 to <vscale x 16 x float>* %4 = bitcast float* %y.addr.014 to <vscale x 16 x float>*
%5 = tail call <vscale x 16 x float> @llvm.riscv.vle.nxv16f32.i64(<vscale x 16 x float> undef, <vscale x 16 x float>* %4, i64 %1) %5 = tail call <vscale x 16 x float> @llvm.riscv.vle.nxv16f32.i64(<vscale x 16 x float> undef, <vscale x 16 x float>* %4, i64 %1)
%6 = tail call <vscale x 16 x float> @llvm.riscv.vfmacc.nxv16f32.f32.i64(<vscale x 16 x float> %5, float %a, <vscale x 16 x float> %3, i64 %1, i64 0) %6 = tail call <vscale x 16 x float> @llvm.riscv.vfmacc.nxv16f32.f32.i64(<vscale x 16 x float> %5, float %a, <vscale x 16 x float> %3, i64 7, i64 %1, i64 0)
tail call void @llvm.riscv.vse.nxv16f32.i64(<vscale x 16 x float> %6, <vscale x 16 x float>* %4, i64 %1) tail call void @llvm.riscv.vse.nxv16f32.i64(<vscale x 16 x float> %6, <vscale x 16 x float>* %4, i64 %1)
%add.ptr1 = getelementptr inbounds float, float* %y.addr.014, i64 %1 %add.ptr1 = getelementptr inbounds float, float* %y.addr.014, i64 %1
%sub = sub i64 %n.addr.016, %1 %sub = sub i64 %n.addr.016, %1
%7 = tail call i64 @llvm.riscv.vsetvli.i64(i64 %sub, i64 2, i64 3) %7 = tail call i64 @llvm.riscv.vsetvli.i64(i64 %sub, i64 2, i64 3)
%cmp.not = icmp eq i64 %7, 0 %cmp.not = icmp eq i64 %7, 0
br i1 %cmp.not, label %for.end, label %for.body br i1 %cmp.not, label %for.end, label %for.body
for.end: ; preds = %for.body, %entry for.end: ; preds = %for.body, %entry
ret void ret void
} }
declare i64 @llvm.riscv.vsetvli.i64(i64, i64 immarg, i64 immarg) declare i64 @llvm.riscv.vsetvli.i64(i64, i64 immarg, i64 immarg)
declare <vscale x 16 x float> @llvm.riscv.vle.nxv16f32.i64(<vscale x 16 x float>, <vscale x 16 x float>* nocapture, i64) declare <vscale x 16 x float> @llvm.riscv.vle.nxv16f32.i64(<vscale x 16 x float>, <vscale x 16 x float>* nocapture, i64)
declare <vscale x 16 x float> @llvm.riscv.vfmacc.nxv16f32.f32.i64(<vscale x 16 x float>, float, <vscale x 16 x float>, i64, i64) declare <vscale x 16 x float> @llvm.riscv.vfmacc.nxv16f32.f32.i64(<vscale x 16 x float>, float, <vscale x 16 x float>, i64, i64, i64)
declare void @llvm.riscv.vse.nxv16f32.i64(<vscale x 16 x float>, <vscale x 16 x float>* nocapture, i64) declare void @llvm.riscv.vse.nxv16f32.i64(<vscale x 16 x float>, <vscale x 16 x float>* nocapture, i64)
; We need a vsetvli in the last block because the predecessors have different ; We need a vsetvli in the last block because the predecessors have different
; VTYPEs. The AVL is the same and the SEW/LMUL ratio implies the same VLMAX so ; VTYPEs. The AVL is the same and the SEW/LMUL ratio implies the same VLMAX so
; we don't need to read AVL and can keep VL unchanged. ; we don't need to read AVL and can keep VL unchanged.
define <vscale x 2 x i32> @test_vsetvli_x0_x0(<vscale x 2 x i32>* %x, <vscale x 2 x i16>* %y, <vscale x 2 x i32> %z, i64 %vl, i1 %cond) nounwind { define <vscale x 2 x i32> @test_vsetvli_x0_x0(<vscale x 2 x i32>* %x, <vscale x 2 x i16>* %y, <vscale x 2 x i32> %z, i64 %vl, i1 %cond) nounwind {
; CHECK-LABEL: test_vsetvli_x0_x0: ; CHECK-LABEL: test_vsetvli_x0_x0:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
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