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Differential D146749

[CodeGen] Fix nomerge attribute not working in tail calls.
ClosedPublic

Authored by zequanwu on Mar 23 2023, 11:50 AM.

Details

Reviewers
hans
craig.topper
stuij
RKSimon
jrtc27
rnk
Commits
rG3977b77a6bb7: [CodeGen] Fix nomerge attribute not working in tail calls.
Summary

In D79537, nomerge was made to only apply to non-tail calls. This fixes it by also applying it to tail calls.

For ARM, I only made the new MI to inherit the flag under TCRETURNdi and TCRETURNri, because that's the place tail calls got replaced. Not sure if there's any other place needed.

Fixes #61545.

Diff Detail

Event Timeline

zequanwu created this revision.Mar 23 2023, 11:50 AM
Herald added a project: Restricted Project. · View Herald TranscriptMar 23 2023, 11:50 AM
Herald added subscribers: luke, frasercrmck, luismarques and 25 others. · View Herald Transcript
zequanwu requested review of this revision.Mar 23 2023, 11:50 AM
Herald added a project: Restricted Project. · View Herald TranscriptMar 23 2023, 11:50 AM
Herald added subscribers: llvm-commits, • pcwang-thead, MaskRay. · View Herald Transcript
Harbormaster completed remote builds in B221390: Diff 507842.Mar 23 2023, 1:14 PM
hans added a comment.Mar 27 2023, 2:39 AM

Looks good as far as I can tell, but hopefully Craig who knows backends better can also take a look.

Maybe add to the description that this is a follow-up to D79537 which extends support to tail calls. (And do we need to do something for globalisel, or can that be left as a todo?)

zequanwu edited the summary of this revision. (Show Details)Mar 27 2023, 7:54 AM
zequanwu added a comment.Mar 27 2023, 7:59 AM

(And do we need to do something for globalisel, or can that be left as a todo?)

I don't know about globalisel. For the repro, this patch fixes that.

craig.topper added inline comments.Mar 27 2023, 9:49 AM
llvm/test/CodeGen/AArch64/nomerge.ll
23

This should be in the body of the @foo_tail function. Did you run utils/update_llc_test_checks.py?

llvm/test/CodeGen/ARM/nomerge.ll
69

These should be in the body of @foo_tail

zequanwu updated this revision to Diff 508725.Mar 27 2023, 10:16 AM
zequanwu marked 2 inline comments as done.

Update all tests by running llvm/utils/update_llc_test_checks.py.

zequanwu added inline comments.Mar 27 2023, 10:17 AM
llvm/test/CodeGen/AArch64/nomerge.ll
23

Updated. I didn't realize those CHECKs were generated by the script.

Harbormaster completed remote builds in B222067: Diff 508725.Mar 27 2023, 12:30 PM
zequanwu added a reviewer: RKSimon.Apr 3 2023, 8:50 AM
jrtc27 added inline comments.Apr 3 2023, 8:56 AM
llvm/lib/Target/PowerPC/PPCISelLowering.cpp
6301

Leave whitespace not in the code you're touching alone

llvm/test/CodeGen/AArch64/nomerge.ll
22

Where did this come from?

41

Precommit all these?

llvm/test/CodeGen/ARM/nomerge.ll
2

This conversion should likely be precommitted to highlight the actual diff

llvm/test/CodeGen/RISCV/nomerge.ll
2

Ugh, D79537 added this without getting a RISC-V contributor's review (Craig wasn't yet one)... like the others, convert this separately

8

These tests could benefit from nounwind to trim irrelevant CFI directives

zequanwu updated this revision to Diff 510539.Apr 3 2023, 9:45 AM
zequanwu marked 3 inline comments as done.
  • Reverted white spaces changes.
  • Add nounwind for tests to trim CFI directives.
llvm/test/CodeGen/AArch64/nomerge.ll
41

Can you elaborate on what does precommit mean? Do you mean commit on foo_tail functions without CHECKs before this patch?

jrtc27 added inline comments.Apr 3 2023, 9:47 AM
llvm/test/CodeGen/AArch64/nomerge.ll
41

Commit the tests with CHECK lines generated from the compiler without this codegen change applied

zequanwu mentioned this in D147454: [NFC] Update CodeGen/*/nomerge.ll tests with utils/update_llc_test_checks.py..Apr 3 2023, 10:02 AM
Harbormaster completed remote builds in B223384: Diff 510539.Apr 3 2023, 12:14 PM
zequanwu mentioned this in rG321d02cc6b6a: [NFC] Update CodeGen/*/nomerge.ll tests with utils/update_llc_test_checks.py..Apr 3 2023, 4:52 PM
zequanwu updated this revision to Diff 510870.Apr 4 2023, 11:43 AM
zequanwu marked 4 inline comments as done.

Rebase.

llvm/test/CodeGen/AArch64/nomerge.ll
41

Landed at https://reviews.llvm.org/rG321d02cc6b6a1116c227c172249b5cacf4d0deba. Rebased this patch.

zequanwu added a reviewer: jrtc27.Apr 4 2023, 11:44 AM
Harbormaster completed remote builds in B223629: Diff 510870.Apr 4 2023, 1:02 PM
zequanwu added a comment.Apr 11 2023, 9:24 AM

Ping.

jrtc27 added inline comments.Apr 11 2023, 9:25 AM
llvm/test/CodeGen/RISCV/nomerge.ll
42–67

?

zequanwu updated this revision to Diff 512492.Apr 11 2023, 9:28 AM
zequanwu marked an inline comment as done.

Address comment.

Harbormaster completed remote builds in B224805: Diff 512492.Apr 11 2023, 10:33 AM
zequanwu added a comment.Apr 27 2023, 9:07 AM

Ping.

zequanwu added a reviewer: rnk.May 9 2023, 1:49 PM
rnk accepted this revision.May 10 2023, 11:08 AM

This looks good to me.

I thought perhaps it would be shorter and simpler to have addNoMergeInfo take and return the SDValue which is being marked to avoid the need for new SDValue variables, but I don't think that's essential.

@jrtc27 , are your concerns addressed?

Regarding globalisel, @zequanwu , can you file an issue for implementing nomerge support in globalisel? It's probably easiest to construct an example with the AArch64 backend.

This revision is now accepted and ready to land.May 10 2023, 11:08 AM
jrtc27 added a comment.May 10 2023, 11:11 AM
In D146749#4332699, @rnk wrote:

This looks good to me.

I thought perhaps it would be shorter and simpler to have addNoMergeInfo take and return the SDValue which is being marked to avoid the need for new SDValue variables, but I don't think that's essential.

@jrtc27 , are your concerns addressed?

Regarding globalisel, @zequanwu , can you file an issue for implementing nomerge support in globalisel? It's probably easiest to construct an example with the AArch64 backend.

Yes, the tests are much cleaner now, both in content and in reviewability of the diff, thanks.

zequanwu added a comment.May 10 2023, 11:22 AM

Regarding globalisel, @zequanwu , can you file an issue for implementing nomerge support in globalisel? It's probably easiest to construct an example with the AArch64 backend.

Filed at https://github.com/llvm/llvm-project/issues/62641

This revision was landed with ongoing or failed builds.May 10 2023, 11:25 AM
Closed by commit rG3977b77a6bb7: [CodeGen] Fix nomerge attribute not working in tail calls. (authored by zequanwu). · Explain Why
This revision was automatically updated to reflect the committed changes.
zequanwu added a commit: rG3977b77a6bb7: [CodeGen] Fix nomerge attribute not working in tail calls..

Revision Contents

PathSize
llvm/
lib/
Target/
AArch64/
1 line
ARM/
3 lines
1 line
LoongArch/
4 lines
PowerPC/
4 lines
RISCV/
4 lines
SystemZ/
7 lines
X86/
1 line
test/
CodeGen/
AArch64/
33 lines
ARM/
53 lines
LoongArch/
56 lines
PowerPC/
67 lines
RISCV/
56 lines
SystemZ/
52 lines
X86/
53 lines

Diff 510539

llvm/lib/Target/AArch64/AArch64ISelLowering.cpp

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 7,552 Lines • ▼ Show 20 LinesAArch64TargetLowering::LowerCall(CallLoweringInfo &CLI,
// actual call instruction. // actual call instruction.
if (IsTailCall) { if (IsTailCall) {
MF.getFrameInfo().setHasTailCall(); MF.getFrameInfo().setHasTailCall();
SDValue Ret = DAG.getNode(AArch64ISD::TC_RETURN, DL, NodeTys, Ops); SDValue Ret = DAG.getNode(AArch64ISD::TC_RETURN, DL, NodeTys, Ops);
if (IsCFICall) if (IsCFICall)
Ret.getNode()->setCFIType(CLI.CFIType->getZExtValue()); Ret.getNode()->setCFIType(CLI.CFIType->getZExtValue());
DAG.addNoMergeSiteInfo(Ret.getNode(), CLI.NoMerge);
DAG.addCallSiteInfo(Ret.getNode(), std::move(CSInfo)); DAG.addCallSiteInfo(Ret.getNode(), std::move(CSInfo));
return Ret; return Ret;
} }
unsigned CallOpc = AArch64ISD::CALL; unsigned CallOpc = AArch64ISD::CALL;
// Calls with operand bundle "clang.arc.attachedcall" are special. They should // Calls with operand bundle "clang.arc.attachedcall" are special. They should
// be expanded to the call, directly followed by a special marker sequence and // be expanded to the call, directly followed by a special marker sequence and
// a call to an ObjC library function. Use CALL_RVMARKER to do that. // a call to an ObjC library function. Use CALL_RVMARKER to do that.
▲ Show 20 Lines • Show All 16,851 Lines • Show Last 20 Lines

llvm/lib/Target/ARM/ARMExpandPseudoInsts.cpp

Show First 20 Lines • Show All 2,165 Lines • ▼ Show 20 Lines case ARM::TCRETURNri: {
auto NewMI = std::prev(MBBI); auto NewMI = std::prev(MBBI);
for (unsigned i = 2, e = MBBI->getNumOperands(); i != e; ++i) for (unsigned i = 2, e = MBBI->getNumOperands(); i != e; ++i)
NewMI->addOperand(MBBI->getOperand(i)); NewMI->addOperand(MBBI->getOperand(i));
// Update call site info and delete the pseudo instruction TCRETURN. // Update call site info and delete the pseudo instruction TCRETURN.
if (MI.isCandidateForCallSiteEntry()) if (MI.isCandidateForCallSiteEntry())
MI.getMF()->moveCallSiteInfo(&MI, &*NewMI); MI.getMF()->moveCallSiteInfo(&MI, &*NewMI);
// Copy nomerge flag over to new instruction.
if (MI.getFlag(MachineInstr::NoMerge))
NewMI->setFlag(MachineInstr::NoMerge);
MBB.erase(MBBI); MBB.erase(MBBI);
MBBI = NewMI; MBBI = NewMI;
return true; return true;
} }
case ARM::tBXNS_RET: { case ARM::tBXNS_RET: {
// For v8.0-M.Main we need to authenticate LR before clearing FPRs, which // For v8.0-M.Main we need to authenticate LR before clearing FPRs, which
// uses R12 as a scratch register. // uses R12 as a scratch register.
▲ Show 20 Lines • Show All 993 Lines • Show Last 20 Lines

llvm/lib/Target/ARM/ARMISelLowering.cpp

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 2,839 Lines • ▼ Show 20 LinesARMTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
if (InFlag.getNode()) if (InFlag.getNode())
Ops.push_back(InFlag); Ops.push_back(InFlag);
SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
if (isTailCall) { if (isTailCall) {
MF.getFrameInfo().setHasTailCall(); MF.getFrameInfo().setHasTailCall();
SDValue Ret = DAG.getNode(ARMISD::TC_RETURN, dl, NodeTys, Ops); SDValue Ret = DAG.getNode(ARMISD::TC_RETURN, dl, NodeTys, Ops);
DAG.addNoMergeSiteInfo(Ret.getNode(), CLI.NoMerge);
DAG.addCallSiteInfo(Ret.getNode(), std::move(CSInfo)); DAG.addCallSiteInfo(Ret.getNode(), std::move(CSInfo));
return Ret; return Ret;
} }
// Returns a chain and a flag for retval copy to use. // Returns a chain and a flag for retval copy to use.
Chain = DAG.getNode(CallOpc, dl, NodeTys, Ops); Chain = DAG.getNode(CallOpc, dl, NodeTys, Ops);
DAG.addNoMergeSiteInfo(Chain.getNode(), CLI.NoMerge); DAG.addNoMergeSiteInfo(Chain.getNode(), CLI.NoMerge);
InFlag = Chain.getValue(1); InFlag = Chain.getValue(1);
▲ Show 20 Lines • Show All 19,184 Lines • Show Last 20 Lines

llvm/lib/Target/LoongArch/LoongArchISelLowering.cpp

Show First 20 Lines • Show All 2,609 Lines • ▼ Show 20 LinesLoongArchTargetLowering::LowerCall(CallLoweringInfo &CLI,
if (Glue.getNode()) if (Glue.getNode())
Ops.push_back(Glue); Ops.push_back(Glue);
// Emit the call. // Emit the call.
SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
if (IsTailCall) { if (IsTailCall) {
MF.getFrameInfo().setHasTailCall(); MF.getFrameInfo().setHasTailCall();
return DAG.getNode(LoongArchISD::TAIL, DL, NodeTys, Ops); SDValue Ret = DAG.getNode(LoongArchISD::TAIL, DL, NodeTys, Ops);
DAG.addNoMergeSiteInfo(Ret.getNode(), CLI.NoMerge);
return Ret;
} }
Chain = DAG.getNode(LoongArchISD::CALL, DL, NodeTys, Ops); Chain = DAG.getNode(LoongArchISD::CALL, DL, NodeTys, Ops);
DAG.addNoMergeSiteInfo(Chain.getNode(), CLI.NoMerge); DAG.addNoMergeSiteInfo(Chain.getNode(), CLI.NoMerge);
Glue = Chain.getValue(1); Glue = Chain.getValue(1);
// Mark the end of the call, which is glued to the call itself. // Mark the end of the call, which is glued to the call itself.
Chain = DAG.getCALLSEQ_END(Chain, NumBytes, 0, Glue, DL); Chain = DAG.getCALLSEQ_END(Chain, NumBytes, 0, Glue, DL);
▲ Show 20 Lines • Show All 570 Lines • Show Last 20 Lines

llvm/lib/Target/PowerPC/PPCISelLowering.cpp

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 5,616 Lines • ▼ Show 20 Lines assert(((Callee.getOpcode() == ISD::Register &&
(CFlags.IsIndirect && Subtarget.isUsingPCRelativeCalls())) && (CFlags.IsIndirect && Subtarget.isUsingPCRelativeCalls())) &&
"Expecting a global address, external symbol, absolute value, " "Expecting a global address, external symbol, absolute value, "
"register or an indirect tail call when PC Relative calls are " "register or an indirect tail call when PC Relative calls are "
"used."); "used.");
// PC Relative calls also use TC_RETURN as the way to mark tail calls. // PC Relative calls also use TC_RETURN as the way to mark tail calls.
assert(CallOpc == PPCISD::TC_RETURN && assert(CallOpc == PPCISD::TC_RETURN &&
"Unexpected call opcode for a tail call."); "Unexpected call opcode for a tail call.");
DAG.getMachineFunction().getFrameInfo().setHasTailCall(); DAG.getMachineFunction().getFrameInfo().setHasTailCall();
return DAG.getNode(CallOpc, dl, MVT::Other, Ops); SDValue Ret = DAG.getNode(CallOpc, dl, MVT::Other, Ops);
DAG.addNoMergeSiteInfo(Ret.getNode(), CFlags.NoMerge);
return Ret;
} }
std::array<EVT, 2> ReturnTypes = {{MVT::Other, MVT::Glue}}; std::array<EVT, 2> ReturnTypes = {{MVT::Other, MVT::Glue}};
Chain = DAG.getNode(CallOpc, dl, ReturnTypes, Ops); Chain = DAG.getNode(CallOpc, dl, ReturnTypes, Ops);
DAG.addNoMergeSiteInfo(Chain.getNode(), CFlags.NoMerge); DAG.addNoMergeSiteInfo(Chain.getNode(), CFlags.NoMerge);
Glue = Chain.getValue(1); Glue = Chain.getValue(1);
// When performing tail call optimization the callee pops its arguments off // When performing tail call optimization the callee pops its arguments off
▲ Show 20 Lines • Show All 657 Lines • ▼ Show 20 Lines if (Flags.isByVal()) {
AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const); AddPtr = DAG.getNode(ISD::ADD, dl, PtrVT, PtrOff, Const);
} }
Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, AddPtr, Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, AddPtr,
CallSeqStart, CallSeqStart,
Flags, DAG, dl); Flags, DAG, dl);
ArgOffset += PtrByteSize; ArgOffset += PtrByteSize;
continue; continue;
} }
// Copy the object to parameter save area if it can not be entirely passed // Copy the object to parameter save area if it can not be entirely passed
jrtc27Unsubmitted
Done
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Leave whitespace not in the code you're touching alone

jrtc27: Leave whitespace not in the code you're touching alone
// by registers. // by registers.
// FIXME: we only need to copy the parts which need to be passed in // FIXME: we only need to copy the parts which need to be passed in
// parameter save area. For the parts passed by registers, we don't need // parameter save area. For the parts passed by registers, we don't need
// to copy them to the stack although we need to allocate space for them // to copy them to the stack although we need to allocate space for them
// in parameter save area. // in parameter save area.
if ((NumGPRs - GPR_idx) * PtrByteSize < Size) if ((NumGPRs - GPR_idx) * PtrByteSize < Size)
Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, PtrOff, Chain = CallSeqStart = createMemcpyOutsideCallSeq(Arg, PtrOff,
CallSeqStart, CallSeqStart,
▲ Show 20 Lines • Show All 12,062 Lines • Show Last 20 Lines

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 13,671 Lines • ▼ Show 20 LinesSDValue RISCVTargetLowering::LowerCall(CallLoweringInfo &CLI,
if (Glue.getNode()) if (Glue.getNode())
Ops.push_back(Glue); Ops.push_back(Glue);
// Emit the call. // Emit the call.
SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
if (IsTailCall) { if (IsTailCall) {
MF.getFrameInfo().setHasTailCall(); MF.getFrameInfo().setHasTailCall();
return DAG.getNode(RISCVISD::TAIL, DL, NodeTys, Ops); SDValue Ret = DAG.getNode(RISCVISD::TAIL, DL, NodeTys, Ops);
DAG.addNoMergeSiteInfo(Ret.getNode(), CLI.NoMerge);
return Ret;
} }
Chain = DAG.getNode(RISCVISD::CALL, DL, NodeTys, Ops); Chain = DAG.getNode(RISCVISD::CALL, DL, NodeTys, Ops);
DAG.addNoMergeSiteInfo(Chain.getNode(), CLI.NoMerge); DAG.addNoMergeSiteInfo(Chain.getNode(), CLI.NoMerge);
Glue = Chain.getValue(1); Glue = Chain.getValue(1);
// Mark the end of the call, which is glued to the call itself. // Mark the end of the call, which is glued to the call itself.
Chain = DAG.getCALLSEQ_END(Chain, NumBytes, 0, Glue, DL); Chain = DAG.getCALLSEQ_END(Chain, NumBytes, 0, Glue, DL);
▲ Show 20 Lines • Show All 1,286 Lines • Show Last 20 Lines

llvm/lib/Target/SystemZ/SystemZISelLowering.cpp

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 1,842 Lines • ▼ Show 20 LinesSystemZTargetLowering::LowerCall(CallLoweringInfo &CLI,
Ops.push_back(DAG.getRegisterMask(Mask)); Ops.push_back(DAG.getRegisterMask(Mask));
// Glue the call to the argument copies, if any. // Glue the call to the argument copies, if any.
if (Glue.getNode()) if (Glue.getNode())
Ops.push_back(Glue); Ops.push_back(Glue);
// Emit the call. // Emit the call.
SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue); SDVTList NodeTys = DAG.getVTList(MVT::Other, MVT::Glue);
if (IsTailCall) if (IsTailCall) {
return DAG.getNode(SystemZISD::SIBCALL, DL, NodeTys, Ops); SDValue Ret = DAG.getNode(SystemZISD::SIBCALL, DL, NodeTys, Ops);
DAG.addNoMergeSiteInfo(Ret.getNode(), CLI.NoMerge);
return Ret;
}
Chain = DAG.getNode(SystemZISD::CALL, DL, NodeTys, Ops); Chain = DAG.getNode(SystemZISD::CALL, DL, NodeTys, Ops);
DAG.addNoMergeSiteInfo(Chain.getNode(), CLI.NoMerge); DAG.addNoMergeSiteInfo(Chain.getNode(), CLI.NoMerge);
Glue = Chain.getValue(1); Glue = Chain.getValue(1);
// Mark the end of the call, which is glued to the call itself. // Mark the end of the call, which is glued to the call itself.
Chain = DAG.getCALLSEQ_END(Chain, NumBytes, 0, Glue, DL); Chain = DAG.getCALLSEQ_END(Chain, NumBytes, 0, Glue, DL);
Glue = Chain.getValue(1); Glue = Chain.getValue(1);
▲ Show 20 Lines • Show All 7,234 Lines • Show Last 20 Lines

llvm/lib/Target/X86/X86ISelLowering.cpp

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 4,966 Lines • ▼ Show 20 Lines if (isTailCall) {
// should be computed from returns not tail calls. Consider a void // should be computed from returns not tail calls. Consider a void
// function making a tail call to a function returning int. // function making a tail call to a function returning int.
MF.getFrameInfo().setHasTailCall(); MF.getFrameInfo().setHasTailCall();
SDValue Ret = DAG.getNode(X86ISD::TC_RETURN, dl, NodeTys, Ops); SDValue Ret = DAG.getNode(X86ISD::TC_RETURN, dl, NodeTys, Ops);
if (IsCFICall) if (IsCFICall)
Ret.getNode()->setCFIType(CLI.CFIType->getZExtValue()); Ret.getNode()->setCFIType(CLI.CFIType->getZExtValue());
DAG.addNoMergeSiteInfo(Ret.getNode(), CLI.NoMerge);
DAG.addCallSiteInfo(Ret.getNode(), std::move(CSInfo)); DAG.addCallSiteInfo(Ret.getNode(), std::move(CSInfo));
return Ret; return Ret;
} }
if (HasNoCfCheck && IsCFProtectionSupported && IsIndirectCall) { if (HasNoCfCheck && IsCFProtectionSupported && IsIndirectCall) {
Chain = DAG.getNode(X86ISD::NT_CALL, dl, NodeTys, Ops); Chain = DAG.getNode(X86ISD::NT_CALL, dl, NodeTys, Ops);
} else if (CLI.CB && objcarc::hasAttachedCallOpBundle(CLI.CB)) { } else if (CLI.CB && objcarc::hasAttachedCallOpBundle(CLI.CB)) {
// Calls with a "clang.arc.attachedcall" bundle are special. They should be // Calls with a "clang.arc.attachedcall" bundle are special. They should be
▲ Show 20 Lines • Show All 32,759 Lines • Show Last 20 Lines

llvm/test/CodeGen/AArch64/nomerge.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=aarch64 -o - | FileCheck %s ; RUN: llc < %s -mtriple=aarch64 -o - | FileCheck %s
define void @foo(i32 %i) uwtable { define void @foo(i32 %i) nounwind {
; CHECK-LABEL: foo: ; CHECK-LABEL: foo:
; CHECK: // %bb.0: // %entry ; CHECK: // %bb.0: // %entry
; CHECK-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill ; CHECK-NEXT: str x30, [sp, #-16]! // 8-byte Folded Spill
; CHECK-NEXT: .cfi_def_cfa_offset 16
; CHECK-NEXT: .cfi_offset w30, -16
; CHECK-NEXT: .cfi_remember_state
; CHECK-NEXT: cmp w0, #7 ; CHECK-NEXT: cmp w0, #7
; CHECK-NEXT: b.eq .LBB0_3 ; CHECK-NEXT: b.eq .LBB0_3
; CHECK-NEXT: // %bb.1: // %entry ; CHECK-NEXT: // %bb.1: // %entry
; CHECK-NEXT: cmp w0, #5 ; CHECK-NEXT: cmp w0, #5
; CHECK-NEXT: b.ne .LBB0_4 ; CHECK-NEXT: b.ne .LBB0_4
; CHECK-NEXT: // %bb.2: // %if.then ; CHECK-NEXT: // %bb.2: // %if.then
; CHECK-NEXT: bl bar ; CHECK-NEXT: bl bar
; CHECK-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload ; CHECK-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload
; CHECK-NEXT: .cfi_def_cfa_offset 0
; CHECK-NEXT: .cfi_restore w30
; CHECK-NEXT: b bar ; CHECK-NEXT: b bar
; CHECK-NEXT: .LBB0_3: // %if.then2 ; CHECK-NEXT: .LBB0_3: // %if.then2
; CHECK-NEXT: .cfi_restore_state
; CHECK-NEXT: bl bar ; CHECK-NEXT: bl bar
; CHECK-NEXT: .LBB0_4: // %if.end3 ; CHECK-NEXT: .LBB0_4: // %if.end3
; CHECK-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload ; CHECK-NEXT: ldr x30, [sp], #16 // 8-byte Folded Reload
; CHECK-NEXT: .cfi_def_cfa_offset 0
; CHECK-NEXT: .cfi_restore w30
; CHECK-NEXT: b bar ; CHECK-NEXT: b bar
entry: entry:
jrtc27Unsubmitted
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Where did this come from?

jrtc27: Where did this come from?
switch i32 %i, label %if.end3 [ switch i32 %i, label %if.end3 [
craig.topperUnsubmitted
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This should be in the body of the @foo_tail function. Did you run utils/update_llc_test_checks.py?

craig.topper: This should be in the body of the @foo_tail function. Did you run utils/update_llc_test_checks.
zequanwuAuthorUnsubmitted
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Updated. I didn't realize those CHECKs were generated by the script.

zequanwu: Updated. I didn't realize those CHECKs were generated by the script.
i32 5, label %if.then i32 5, label %if.then
i32 7, label %if.then2 i32 7, label %if.then2
] ]
if.then: if.then:
tail call void @bar() #0 tail call void @bar() #0
br label %if.end3 br label %if.end3
if.then2: if.then2:
tail call void @bar() #0 tail call void @bar() #0
br label %if.end3 br label %if.end3
if.end3: if.end3:
tail call void @bar() #0 tail call void @bar() #0
ret void ret void
} }
define void @foo_tail(i1 %i) nounwind {
jrtc27Unsubmitted
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Precommit all these?

jrtc27: Precommit all these?
zequanwuAuthorUnsubmitted
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Can you elaborate on what does precommit mean? Do you mean commit on foo_tail functions without CHECKs before this patch?

zequanwu: Can you elaborate on what does precommit mean? Do you mean commit on foo_tail functions without…
jrtc27Unsubmitted
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Commit the tests with CHECK lines generated from the compiler without this codegen change applied

jrtc27: Commit the tests with CHECK lines generated from the compiler without this codegen change…
zequanwuAuthorUnsubmitted
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Landed at https://reviews.llvm.org/rG321d02cc6b6a1116c227c172249b5cacf4d0deba. Rebased this patch.

zequanwu: Landed at https://reviews.llvm.org/rG321d02cc6b6a1116c227c172249b5cacf4d0deba. Rebased this…
; CHECK-LABEL: foo_tail:
; CHECK: // %bb.0: // %entry
; CHECK-NEXT: tbz w0, #0, .LBB1_2
; CHECK-NEXT: // %bb.1: // %if.then
; CHECK-NEXT: b bar
; CHECK-NEXT: .LBB1_2: // %if.else
; CHECK-NEXT: b bar
entry:
br i1 %i, label %if.then, label %if.else
if.then:
tail call void @bar() #0
br label %if.end
if.else:
tail call void @bar() #0
br label %if.end
if.end:
ret void
}
declare void @bar() declare void @bar()
attributes #0 = { nomerge } attributes #0 = { nomerge }

llvm/test/CodeGen/ARM/nomerge.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
; RUN: llc < %s -mtriple=arm -o - | FileCheck %s ; RUN: llc < %s -mtriple=arm -o - | FileCheck %s
jrtc27Unsubmitted
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This conversion should likely be precommitted to highlight the actual diff

jrtc27: This conversion should likely be precommitted to highlight the actual diff
define void @foo(i32 %i) { define void @foo(i32 %i) {
; CHECK-LABEL: foo:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: push {r11, lr}
; CHECK-NEXT: cmp r0, #7
; CHECK-NEXT: beq .LBB0_3
; CHECK-NEXT: @ %bb.1: @ %entry
; CHECK-NEXT: cmp r0, #5
; CHECK-NEXT: bne .LBB0_4
; CHECK-NEXT: @ %bb.2: @ %if.then
; CHECK-NEXT: bl bar
; CHECK-NEXT: pop {r11, lr}
; CHECK-NEXT: b bar
; CHECK-NEXT: .LBB0_3: @ %if.then2
; CHECK-NEXT: bl bar
; CHECK-NEXT: .LBB0_4: @ %if.end3
; CHECK-NEXT: pop {r11, lr}
; CHECK-NEXT: b bar
entry: entry:
switch i32 %i, label %if.end3 [ switch i32 %i, label %if.end3 [
i32 5, label %if.then i32 5, label %if.then
i32 7, label %if.then2 i32 7, label %if.then2
] ]
if.then: if.then:
tail call void @bar() #0 tail call void @bar() #0
br label %if.end3 br label %if.end3
if.then2: if.then2:
tail call void @bar() #0 tail call void @bar() #0
br label %if.end3 br label %if.end3
if.end3: if.end3:
tail call void @bar() #0 tail call void @bar() #0
ret void ret void
} }
define void @foo_tail(i1 %i) {
; CHECK-LABEL: foo_tail:
; CHECK: @ %bb.0: @ %entry
; CHECK-NEXT: tst r0, #1
; CHECK-NEXT: beq .LBB1_2
; CHECK-NEXT: @ %bb.1: @ %if.then
; CHECK-NEXT: b bar
; CHECK-NEXT: .LBB1_2: @ %if.else
; CHECK-NEXT: b bar
entry:
br i1 %i, label %if.then, label %if.else
if.then:
tail call void @bar() #0
br label %if.end
if.else:
tail call void @bar() #0
br label %if.end
if.end:
ret void
}
declare void @bar() declare void @bar()
attributes #0 = { nomerge } attributes #0 = { nomerge }
craig.topperUnsubmitted
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These should be in the body of @foo_tail

craig.topper: These should be in the body of @foo_tail
; CHECK-LABEL: foo:
; CHECK: @ %bb.0: @ %entry
; CHECK: @ %bb.1: @ %entry
; CHECK: @ %bb.2: @ %if.then
; CHECK-NEXT: bl bar
; CHECK: b bar
; CHECK: .LBB0_3: @ %if.then2
; CHECK-NEXT: bl bar
; CHECK: .LBB0_4: @ %if.end3
; CHECK: b bar

llvm/test/CodeGen/LoongArch/nomerge.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
; RUN: llc --mtriple=loongarch64 < %s | FileCheck %s ; RUN: llc --mtriple=loongarch64 < %s | FileCheck %s
define void @foo(i32 %i) { define void @foo(i32 %i) nounwind {
; CHECK-LABEL: foo:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi.d $sp, $sp, -16
; CHECK-NEXT: st.d $ra, $sp, 8 # 8-byte Folded Spill
; CHECK-NEXT: bstrpick.d $a0, $a0, 31, 0
; CHECK-NEXT: ori $a1, $zero, 7
; CHECK-NEXT: beq $a0, $a1, .LBB0_3
; CHECK-NEXT: # %bb.1: # %entry
; CHECK-NEXT: ori $a1, $zero, 5
; CHECK-NEXT: bne $a0, $a1, .LBB0_4
; CHECK-NEXT: # %bb.2: # %if.then
; CHECK-NEXT: bl %plt(bar)
; CHECK-NEXT: b .LBB0_4
; CHECK-NEXT: .LBB0_3: # %if.then2
; CHECK-NEXT: bl %plt(bar)
; CHECK-NEXT: .LBB0_4: # %if.end3
; CHECK-NEXT: ld.d $ra, $sp, 8 # 8-byte Folded Reload
; CHECK-NEXT: addi.d $sp, $sp, 16
; CHECK-NEXT: b %plt(bar)
entry: entry:
switch i32 %i, label %if.end3 [ switch i32 %i, label %if.end3 [
i32 5, label %if.then i32 5, label %if.then
i32 7, label %if.then2 i32 7, label %if.then2
] ]
if.then: if.then:
tail call void @bar() #0 tail call void @bar() #0
br label %if.end3 br label %if.end3
if.then2: if.then2:
tail call void @bar() #0 tail call void @bar() #0
br label %if.end3 br label %if.end3
if.end3: if.end3:
tail call void @bar() #0 tail call void @bar() #0
ret void ret void
} }
define void @foo_tail(i1 %i) nounwind {
; CHECK-LABEL: foo_tail:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: andi $a0, $a0, 1
; CHECK-NEXT: beqz $a0, .LBB1_2
; CHECK-NEXT: # %bb.1: # %if.then
; CHECK-NEXT: b %plt(bar)
; CHECK-NEXT: .LBB1_2: # %if.else
; CHECK-NEXT: b %plt(bar)
entry:
br i1 %i, label %if.then, label %if.else
if.then:
tail call void @bar() #0
br label %if.end
if.else:
tail call void @bar() #0
br label %if.end
if.end:
ret void
}
declare void @bar() declare void @bar()
attributes #0 = { nomerge } attributes #0 = { nomerge }
; CHECK-LABEL: foo:
; CHECK: # %bb.0: # %entry
; CHECK: # %bb.1: # %entry
; CHECK: # %bb.2: # %if.then
; CHECK-NEXT: bl %plt(bar)
; CHECK: .LBB0_3: # %if.then2
; CHECK-NEXT: bl %plt(bar)
; CHECK: .LBB0_4: # %if.end3
; CHECK: b %plt(bar)

llvm/test/CodeGen/PowerPC/nomerge.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
; RUN: llc < %s -mtriple=powerpc -o - | FileCheck %s ; RUN: llc < %s -mtriple=powerpc -o - | FileCheck %s
define void @foo(i32 %i) { define void @foo(i32 %i) nounwind {
; CHECK-LABEL: foo:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: mflr 0
; CHECK-NEXT: stwu 1, -16(1)
; CHECK-NEXT: cmplwi 3, 7
; CHECK-NEXT: stw 0, 20(1)
; CHECK-NEXT: beq 0, .LBB0_3
; CHECK-NEXT: # %bb.1: # %entry
; CHECK-NEXT: cmplwi 3, 5
; CHECK-NEXT: bne 0, .LBB0_4
; CHECK-NEXT: # %bb.2: # %if.then
; CHECK-NEXT: bl bar
; CHECK-NEXT: b .LBB0_4
; CHECK-NEXT: .LBB0_3: # %if.then2
; CHECK-NEXT: bl bar
; CHECK-NEXT: .LBB0_4: # %if.end3
; CHECK-NEXT: bl bar
; CHECK-NEXT: lwz 0, 20(1)
; CHECK-NEXT: addi 1, 1, 16
; CHECK-NEXT: mtlr 0
; CHECK-NEXT: blr
entry: entry:
switch i32 %i, label %if.end3 [ switch i32 %i, label %if.end3 [
i32 5, label %if.then i32 5, label %if.then
i32 7, label %if.then2 i32 7, label %if.then2
] ]
if.then: if.then:
tail call void @bar() #0 tail call void @bar() #0
br label %if.end3 br label %if.end3
if.then2: if.then2:
tail call void @bar() #0 tail call void @bar() #0
br label %if.end3 br label %if.end3
if.end3: if.end3:
tail call void @bar() #0 tail call void @bar() #0
ret void ret void
} }
declare void @bar() define void @foo_tail(i1 %i) nounwind {
; CHECK-LABEL: foo_tail:
attributes #0 = { nomerge }
; CHECK-LABEL: foo:
; CHECK: # %bb.0: # %entry ; CHECK: # %bb.0: # %entry
; CHECK: # %bb.1: # %entry ; CHECK-NEXT: mflr 0
; CHECK: # %bb.2: # %if.then ; CHECK-NEXT: stwu 1, -16(1)
; CHECK-NEXT: bl bar ; CHECK-NEXT: andi. 3, 3, 1
; CHECK: .LBB0_3: # %if.then2 ; CHECK-NEXT: stw 0, 20(1)
; CHECK-NEXT: bc 4, 1, .LBB1_2
; CHECK-NEXT: # %bb.1: # %if.then
; CHECK-NEXT: bl bar ; CHECK-NEXT: bl bar
; CHECK: .LBB0_4: # %if.end3 ; CHECK-NEXT: b .LBB1_3
; CHECK-NEXT: .LBB1_2: # %if.else
; CHECK-NEXT: bl bar ; CHECK-NEXT: bl bar
; CHECK-NEXT: .LBB1_3: # %if.end
; CHECK-NEXT: lwz 0, 20(1)
; CHECK-NEXT: addi 1, 1, 16
; CHECK-NEXT: mtlr 0
; CHECK-NEXT: blr
entry:
br i1 %i, label %if.then, label %if.else
if.then:
tail call void @bar() #0
br label %if.end
if.else:
tail call void @bar() #0
br label %if.end
if.end:
ret void
}
declare void @bar()
attributes #0 = { nomerge }

llvm/test/CodeGen/RISCV/nomerge.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
; RUN: llc < %s -mtriple=riscv64 -o - | FileCheck %s ; RUN: llc < %s -mtriple=riscv64 -o - | FileCheck %s
jrtc27Unsubmitted
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Ugh, D79537 added this without getting a RISC-V contributor's review (Craig wasn't yet one)... like the others, convert this separately

jrtc27: Ugh, D79537 added this without getting a RISC-V contributor's review (Craig wasn't yet one)...
define void @foo(i32 %i) { define void @foo(i32 %i) nounwind {
; CHECK-LABEL: foo:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: addi sp, sp, -16
; CHECK-NEXT: sd ra, 8(sp) # 8-byte Folded Spill
jrtc27Unsubmitted
Done
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These tests could benefit from nounwind to trim irrelevant CFI directives

jrtc27: These tests could benefit from nounwind to trim irrelevant CFI directives
; CHECK-NEXT: sext.w a0, a0
; CHECK-NEXT: li a1, 7
; CHECK-NEXT: beq a0, a1, .LBB0_3
; CHECK-NEXT: # %bb.1: # %entry
; CHECK-NEXT: li a1, 5
; CHECK-NEXT: bne a0, a1, .LBB0_4
; CHECK-NEXT: # %bb.2: # %if.then
; CHECK-NEXT: call bar@plt
; CHECK-NEXT: j .LBB0_4
; CHECK-NEXT: .LBB0_3: # %if.then2
; CHECK-NEXT: call bar@plt
; CHECK-NEXT: .LBB0_4: # %if.end3
; CHECK-NEXT: ld ra, 8(sp) # 8-byte Folded Reload
; CHECK-NEXT: addi sp, sp, 16
; CHECK-NEXT: tail bar@plt
entry: entry:
switch i32 %i, label %if.end3 [ switch i32 %i, label %if.end3 [
i32 5, label %if.then i32 5, label %if.then
i32 7, label %if.then2 i32 7, label %if.then2
] ]
if.then: if.then:
tail call void @bar() #0 tail call void @bar() #0
br label %if.end3 br label %if.end3
if.then2: if.then2:
tail call void @bar() #0 tail call void @bar() #0
br label %if.end3 br label %if.end3
if.end3: if.end3:
tail call void @bar() #0 tail call void @bar() #0
ret void ret void
} }
define void @foo_tail(i1 %i) nounwind{
; CHECK-LABEL: foo_tail:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: andi a0, a0, 1
; CHECK-NEXT: beqz a0, .LBB1_2
; CHECK-NEXT: # %bb.1: # %if.then
; CHECK-NEXT: tail bar@plt
; CHECK-NEXT: .LBB1_2: # %if.else
; CHECK-NEXT: tail bar@plt
entry:
br i1 %i, label %if.then, label %if.else
if.then:
tail call void @bar() #0
br label %if.end
if.else:
tail call void @bar() #0
br label %if.end
if.end:
ret void
}
declare void @bar() declare void @bar()
jrtc27Unsubmitted
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?

jrtc27: ?
attributes #0 = { nomerge } attributes #0 = { nomerge }
; CHECK-LABEL: foo:
; CHECK: # %bb.0: # %entry
; CHECK: # %bb.1: # %entry
; CHECK: # %bb.2: # %if.then
; CHECK-NEXT: call bar
; CHECK: .LBB0_3: # %if.then2
; CHECK-NEXT: call bar
; CHECK: .LBB0_4: # %if.end3
; CHECK: tail bar

llvm/test/CodeGen/SystemZ/nomerge.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
; RUN: llc < %s -mtriple=s390x-linux-gnu -o - | FileCheck %s ; RUN: llc < %s -mtriple=s390x-linux-gnu -o - | FileCheck %s
define void @foo(i32 %i) { define void @foo(i32 %i) nounwind {
; CHECK-LABEL: foo:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: stmg %r14, %r15, 112(%r15)
; CHECK-NEXT: aghi %r15, -160
; CHECK-NEXT: cije %r2, 7, .LBB0_3
; CHECK-NEXT: # %bb.1: # %entry
; CHECK-NEXT: cijlh %r2, 5, .LBB0_4
; CHECK-NEXT: # %bb.2: # %if.then
; CHECK-NEXT: brasl %r14, bar@PLT
; CHECK-NEXT: lmg %r14, %r15, 272(%r15)
; CHECK-NEXT: jg bar@PLT
; CHECK-NEXT: .LBB0_3: # %if.then2
; CHECK-NEXT: brasl %r14, bar@PLT
; CHECK-NEXT: .LBB0_4: # %if.end3
; CHECK-NEXT: lmg %r14, %r15, 272(%r15)
; CHECK-NEXT: jg bar@PLT
entry: entry:
switch i32 %i, label %if.end3 [ switch i32 %i, label %if.end3 [
i32 5, label %if.then i32 5, label %if.then
i32 7, label %if.then2 i32 7, label %if.then2
] ]
if.then: if.then:
tail call void @bar() #0 tail call void @bar() #0
br label %if.end3 br label %if.end3
if.then2: if.then2:
tail call void @bar() #0 tail call void @bar() #0
br label %if.end3 br label %if.end3
if.end3: if.end3:
tail call void @bar() #0 tail call void @bar() #0
ret void ret void
} }
define void @foo_tail(i1 %i) nounwind {
; CHECK-LABEL: foo_tail:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: tmll %r2, 1
; CHECK-NEXT: jge bar@PLT
; CHECK-NEXT: .LBB1_1: # %if.then
; CHECK-NEXT: jg bar@PLT
entry:
br i1 %i, label %if.then, label %if.else
if.then:
tail call void @bar() #0
br label %if.end
if.else:
tail call void @bar() #0
br label %if.end
if.end:
ret void
}
declare void @bar() declare void @bar()
attributes #0 = { nomerge } attributes #0 = { nomerge }
; CHECK-LABEL: foo:
; CHECK: # %bb.0: # %entry
; CHECK: # %bb.1: # %entry
; CHECK: # %bb.2: # %if.then
; CHECK-NEXT: brasl %r14, bar@PLT
; CHECK: jg bar@PLT
; CHECK: .LBB0_3: # %if.then2
; CHECK: brasl %r14, bar@PLT
; CHECK: .LBB0_4: # %if.end3
; CHECK: jg bar@PLT

llvm/test/CodeGen/X86/nomerge.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
; RUN: llc < %s -mtriple=x86_64 -o - | FileCheck %s ; RUN: llc < %s -mtriple=x86_64 -o - | FileCheck %s
define void @foo(i32 %i) { define void @foo(i32 %i) nounwind {
; CHECK-LABEL: foo:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: pushq %rax
; CHECK-NEXT: cmpl $7, %edi
; CHECK-NEXT: je .LBB0_3
; CHECK-NEXT: # %bb.1: # %entry
; CHECK-NEXT: cmpl $5, %edi
; CHECK-NEXT: jne .LBB0_4
; CHECK-NEXT: # %bb.2: # %if.then
; CHECK-NEXT: callq bar
; CHECK-NEXT: popq %rax
; CHECK-NEXT: jmp bar # TAILCALL
; CHECK-NEXT: .LBB0_3: # %if.then2
; CHECK-NEXT: callq bar
; CHECK-NEXT: .LBB0_4: # %if.end3
; CHECK-NEXT: popq %rax
; CHECK-NEXT: jmp bar # TAILCALL
entry: entry:
switch i32 %i, label %if.end3 [ switch i32 %i, label %if.end3 [
i32 5, label %if.then i32 5, label %if.then
i32 7, label %if.then2 i32 7, label %if.then2
] ]
if.then: if.then:
tail call void @bar() #0 tail call void @bar() #0
br label %if.end3 br label %if.end3
if.then2: if.then2:
tail call void @bar() #0 tail call void @bar() #0
br label %if.end3 br label %if.end3
if.end3: if.end3:
tail call void @bar() #0 tail call void @bar() #0
ret void ret void
} }
define void @foo_tail(i1 %i) nounwind {
; CHECK-LABEL: foo_tail:
; CHECK: # %bb.0: # %entry
; CHECK-NEXT: testb $1, %dil
; CHECK-NEXT: je bar # TAILCALL
; CHECK-NEXT: # %bb.1: # %if.then
; CHECK-NEXT: jmp bar # TAILCALL
entry:
br i1 %i, label %if.then, label %if.else
if.then:
tail call void @bar() #0
br label %if.end
if.else:
tail call void @bar() #0
br label %if.end
if.end:
ret void
}
declare dso_local void @bar() declare dso_local void @bar()
attributes #0 = { nomerge } attributes #0 = { nomerge }
; CHECK-LABEL: foo:
; CHECK: # %bb.0: # %entry
; CHECK: # %bb.1: # %entry
; CHECK: # %bb.2: # %if.then
; CHECK-NEXT: callq bar
; CHECK: jmp bar # TAILCALL
; CHECK: .LBB0_3: # %if.then2
; CHECK: callq bar
; CHECK: .LBB0_4: # %if.end3
; CHECK: jmp bar # TAILCALL