[VP][RISCV] Add vp.bitreverse and RISC-V support.
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Authored by fakepaper56 on Dec 9 2022, 1:18 AM.

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craig.topper
reames
frasercrmck
rogfer01

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rG47b9da72e032: [VP][RISCV] Add vp.bitreverse and RISC-V support.

Summary

The patch also added function expandVPBITREVERSE to expand ISD::VP_BITREVERSE nodes.

Diff Detail

Repository: rG LLVM Github Monorepo

Event Timeline

fakepaper56 created this revision.Dec 9 2022, 1:18 AM

Herald added a project: Restricted Project. · View Herald TranscriptDec 9 2022, 1:18 AM

Herald added subscribers: sunshaoce, VincentWu, StephenFan and 28 others. · View Herald Transcript

fakepaper56 requested review of this revision.Dec 9 2022, 1:18 AM

Herald added a project: Restricted Project. · View Herald TranscriptDec 9 2022, 1:18 AM

Herald added subscribers: llvm-commits, pcwang-thead, eopXD, MaskRay. · View Herald Transcript

Harbormaster completed remote builds in B202172: Diff 481552.Dec 9 2022, 2:01 AM

craig.topper added inline comments.Dec 9 2022, 10:33 AM

llvm/docs/LangRef.rst
22089	It's only one vector
22136	It's wrong here too

Add VP intrinsic unit test and fix typos.

fakepaper56 marked 2 inline comments as done.Dec 9 2022, 5:15 PM

Harbormaster completed remote builds in B202342: Diff 481797.Dec 9 2022, 6:40 PM

LGTM

This revision is now accepted and ready to land.Dec 11 2022, 5:38 PM

This revision was landed with ongoing or failed builds.Dec 11 2022, 6:58 PM

Closed by commit rG47b9da72e032: [VP][RISCV] Add vp.bitreverse and RISC-V support. (authored by fakepaper56). · Explain Why

This revision was automatically updated to reflect the committed changes.

fakepaper56 added a commit: rG47b9da72e032: [VP][RISCV] Add vp.bitreverse and RISC-V support..

Revision Contents
Changeset List

Path

Size

llvm/

docs/

LangRef.rst

49 lines

include/

llvm/

CodeGen/

TargetLowering.h

5 lines

IR/

Intrinsics.td

4 lines

VPIntrinsics.def

4 lines

lib/

CodeGen/

SelectionDAG/

LegalizeVectorOps.cpp

6 lines

LegalizeVectorTypes.cpp

2 lines

TargetLowering.cpp

62 lines

Target/

RISCV/

RISCVISelLowering.cpp

2 lines

RISCVTargetTransformInfo.cpp

35 lines

test/

CodeGen/

RISCV/

rvv/

bitreverse-vp.ll

3798 lines

fixed-vectors-bitreverse-vp.ll

3197 lines

unittests/

IR/

VPIntrinsicTest.cpp

2 lines

Diff 481972

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llvm/docs/LangRef.rst

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llvm/include/llvm/CodeGen/TargetLowering.h

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llvm/include/llvm/IR/Intrinsics.td

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llvm/include/llvm/IR/VPIntrinsics.def

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llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp

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llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp

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llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp

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llvm/lib/Target/RISCV/RISCVISelLowering.cpp

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llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp

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llvm/test/CodeGen/RISCV/rvv/bitreverse-vp.ll

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llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitreverse-vp.ll

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llvm/unittests/IR/VPIntrinsicTest.cpp

[VP][RISCV] Add vp.bitreverse and RISC-V support.ClosedPublicActions

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Diff Detail

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Revision ContentsChangeset List

Diff 481972

llvm/docs/LangRef.rst

llvm/include/llvm/CodeGen/TargetLowering.h

llvm/include/llvm/IR/Intrinsics.td

llvm/include/llvm/IR/VPIntrinsics.def

llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp

llvm/lib/CodeGen/SelectionDAG/LegalizeVectorTypes.cpp

llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp

llvm/test/CodeGen/RISCV/rvv/bitreverse-vp.ll

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-bitreverse-vp.ll

llvm/unittests/IR/VPIntrinsicTest.cpp

[VP][RISCV] Add vp.bitreverse and RISC-V support.
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Revision Contents
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