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Differential D133238

[RISCV] Improve vector fceil/ffloor lowering by changing FRM.
ClosedPublic

Authored by craig.topper on Sep 2 2022, 3:24 PM.

Details

Reviewers
reames
arcbbb
Commits
rGf0332d12aeec: [RISCV] Improve vector fceil/ffloor lowering by changing FRM.
Summary

This adds new VFCVT pseudoinstructions that take a rounding mode operand. A custom inserter is used to insert additional instructions to change FRM around the
VFCVT.

Some of this is borrowed from D122860, but takes a somewhat different direction. We may migrate to that patch, but for now I was trying to keep this as independent from
RVV intrinsics as I could.

A followup patch will use this approach for FROUND too.

Still need to fix the cost model.

Diff Detail

Event Timeline

craig.topper created this revision.Sep 2 2022, 3:24 PM
Herald added a project: Restricted Project. · View Herald TranscriptSep 2 2022, 3:24 PM
Herald added subscribers: sunshaoce, VincentWu, luke957 and 30 others. · View Herald Transcript
craig.topper requested review of this revision.Sep 2 2022, 3:24 PM
Herald added a project: Restricted Project. · View Herald TranscriptSep 2 2022, 3:24 PM
Herald added subscribers: • pcwang-thead, eopXD, MaskRay. · View Herald Transcript
craig.topper edited the summary of this revision. (Show Details)Sep 2 2022, 3:25 PM
Harbormaster completed remote builds in B184900: Diff 457718.Sep 2 2022, 3:44 PM
frasercrmck added a comment.Sep 5 2022, 7:23 AM

Looks good to me.

llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
1034

Really minor but I find TAFRM quite hard to parse. I dunno if TA_FRM is preferable?

arcbbb accepted this revision.Sep 5 2022, 7:37 AM

LGTM.
It is nice to see vfcvt is used in fceil & ffloor.

This revision is now accepted and ready to land.Sep 5 2022, 7:37 AM
This revision was landed with ongoing or failed builds.Sep 5 2022, 7:04 PM
Closed by commit rGf0332d12aeec: [RISCV] Improve vector fceil/ffloor lowering by changing FRM. (authored by craig.topper). · Explain Why
This revision was automatically updated to reflect the committed changes.
craig.topper added a commit: rGf0332d12aeec: [RISCV] Improve vector fceil/ffloor lowering by changing FRM..
craig.topper mentioned this in D133335: [RISCV] Improve vector fround lowering by changing FRM..Sep 5 2022, 10:13 PM
craig.topper mentioned this in rG5d30565d807f: [RISCV] Improve vector fround lowering by changing FRM..Sep 6 2022, 9:33 AM

Revision Contents

PathSize
llvm/
lib/
Target/
RISCV/
1 line
103 lines
1 line
33 lines
22 lines
64 lines
test/
Analysis/
CostModel/
RISCV/
64 lines
CodeGen/
RISCV/
rvv/
288 lines
288 lines
144 lines

Diff 458078

llvm/lib/Target/RISCV/RISCVISelLowering.h

Show First 20 Lines • Show All 248 Lines • ▼ Show 20 Linesenum NodeType : unsigned {
// Vector unary ops with a mask as a second operand and VL as a third operand. // Vector unary ops with a mask as a second operand and VL as a third operand.
FNEG_VL, FNEG_VL,
FABS_VL, FABS_VL,
FSQRT_VL, FSQRT_VL,
FCOPYSIGN_VL, // Has a merge operand FCOPYSIGN_VL, // Has a merge operand
FP_TO_SINT_VL, FP_TO_SINT_VL,
FP_TO_UINT_VL, FP_TO_UINT_VL,
VFCVT_X_F_VL,
SINT_TO_FP_VL, SINT_TO_FP_VL,
UINT_TO_FP_VL, UINT_TO_FP_VL,
FP_ROUND_VL, FP_ROUND_VL,
FP_EXTEND_VL, FP_EXTEND_VL,
// Vector FMA ops with a mask as a fourth operand and VL as a fifth operand. // Vector FMA ops with a mask as a fourth operand and VL as a fifth operand.
VFMADD_VL, VFMADD_VL,
VFNMADD_VL, VFNMADD_VL,
▲ Show 20 Lines • Show All 499 Lines • Show Last 20 Lines

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 1,833 Lines • ▼ Show 20 Linesstatic SDValue lowerFP_TO_INT_SAT(SDValue Op, SelectionDAG &DAG,
SDValue ZeroInt = DAG.getConstant(0, DL, DstVT); SDValue ZeroInt = DAG.getConstant(0, DL, DstVT);
return DAG.getSelectCC(DL, Src, Src, ZeroInt, FpToInt, ISD::CondCode::SETUO); return DAG.getSelectCC(DL, Src, Src, ZeroInt, FpToInt, ISD::CondCode::SETUO);
} }
// Expand vector FTRUNC, FCEIL, and FFLOOR by converting to the integer domain // Expand vector FTRUNC, FCEIL, and FFLOOR by converting to the integer domain
// and back. Taking care to avoid converting values that are nan or already // and back. Taking care to avoid converting values that are nan or already
// correct. // correct.
// TODO: Floor and ceil could be shorter by changing rounding mode, but we don't
// have FRM dependencies modeled yet.
static SDValue lowerFTRUNC_FCEIL_FFLOOR(SDValue Op, SelectionDAG &DAG, static SDValue lowerFTRUNC_FCEIL_FFLOOR(SDValue Op, SelectionDAG &DAG,
const RISCVSubtarget &Subtarget) { const RISCVSubtarget &Subtarget) {
MVT VT = Op.getSimpleValueType(); MVT VT = Op.getSimpleValueType();
assert(VT.isVector() && "Unexpected type"); assert(VT.isVector() && "Unexpected type");
SDLoc DL(Op); SDLoc DL(Op);
SDValue Src = Op.getOperand(0); SDValue Src = Op.getOperand(0);
Show All 30 Linesstatic SDValue lowerFTRUNC_FCEIL_FFLOOR(SDValue Op, SelectionDAG &DAG,
// If abs(Src) was larger than MaxVal or nan, keep it. // If abs(Src) was larger than MaxVal or nan, keep it.
MVT SetccVT = MVT::getVectorVT(MVT::i1, ContainerVT.getVectorElementCount()); MVT SetccVT = MVT::getVectorVT(MVT::i1, ContainerVT.getVectorElementCount());
SDValue Mask = DAG.getNode(RISCVISD::SETCC_VL, DL, SetccVT, SDValue Mask = DAG.getNode(RISCVISD::SETCC_VL, DL, SetccVT,
{Abs, MaxValSplat, DAG.getCondCode(ISD::SETOLT), {Abs, MaxValSplat, DAG.getCondCode(ISD::SETOLT),
DAG.getUNDEF(SetccVT), TrueMask, VL}); DAG.getUNDEF(SetccVT), TrueMask, VL});
// Truncate to integer and convert back to FP. // Truncate to integer and convert back to FP.
MVT IntVT = ContainerVT.changeVectorElementTypeToInteger(); MVT IntVT = ContainerVT.changeVectorElementTypeToInteger();
SDValue Truncated = MVT XLenVT = Subtarget.getXLenVT();
DAG.getNode(RISCVISD::FP_TO_SINT_VL, DL, IntVT, Src, Mask, VL); SDValue Truncated;
Truncated = DAG.getNode(RISCVISD::SINT_TO_FP_VL, DL, ContainerVT, Truncated,
Mask, VL);
if (Op.getOpcode() == ISD::FCEIL) { switch (Op.getOpcode()) {
// If the truncated value is the greater than or equal to the original default:
// value, we've computed the ceil. Otherwise, we went the wrong way and llvm_unreachable("Unexpected opcode");
// need to increase by 1. case ISD::FCEIL:
// FIXME: This should use a masked operation. Handle here or in isel? Truncated =
SDValue SplatVal = DAG.getNode(RISCVISD::VFCVT_X_F_VL, DL, IntVT, Src, Mask,
DAG.getConstantFP(1.0, DL, ContainerVT.getVectorElementType()); DAG.getTargetConstant(RISCVFPRndMode::RUP, DL, XLenVT), VL);
SDValue Splat = DAG.getNode(RISCVISD::VFMV_V_F_VL, DL, ContainerVT, break;
DAG.getUNDEF(ContainerVT), SplatVal, VL); case ISD::FFLOOR:
SDValue NeedAdjust = DAG.getNode( Truncated =
RISCVISD::SETCC_VL, DL, SetccVT, DAG.getNode(RISCVISD::VFCVT_X_F_VL, DL, IntVT, Src, Mask,
{Truncated, Src, DAG.getCondCode(ISD::SETOLT), Mask, Mask, VL}); DAG.getTargetConstant(RISCVFPRndMode::RDN, DL, XLenVT), VL);
Truncated = DAG.getNode(RISCVISD::FADD_VL, DL, ContainerVT, Truncated, break;
Splat, Truncated, NeedAdjust, VL); case ISD::FTRUNC:
} else if (Op.getOpcode() == ISD::FFLOOR) { Truncated = DAG.getNode(RISCVISD::FP_TO_SINT_VL, DL, IntVT, Src, Mask, VL);
// If the truncated value is the less than or equal to the original value, break;
// we've computed the floor. Otherwise, we went the wrong way and need to
// decrease by 1.
// FIXME: This should use a masked operation. Handle here or in isel?
SDValue SplatVal =
DAG.getConstantFP(1.0, DL, ContainerVT.getVectorElementType());
SDValue Splat = DAG.getNode(RISCVISD::VFMV_V_F_VL, DL, ContainerVT,
DAG.getUNDEF(ContainerVT), SplatVal, VL);
SDValue NeedAdjust = DAG.getNode(
RISCVISD::SETCC_VL, DL, SetccVT,
{Src, Truncated, DAG.getCondCode(ISD::SETOLT), Mask, Mask, VL});
Truncated = DAG.getNode(RISCVISD::FSUB_VL, DL, ContainerVT, Truncated,
Splat, Truncated, NeedAdjust, VL);
} }
Truncated = DAG.getNode(RISCVISD::SINT_TO_FP_VL, DL, ContainerVT, Truncated,
Mask, VL);
// Restore the original sign so that -0.0 is preserved. // Restore the original sign so that -0.0 is preserved.
Truncated = DAG.getNode(RISCVISD::FCOPYSIGN_VL, DL, ContainerVT, Truncated, Truncated = DAG.getNode(RISCVISD::FCOPYSIGN_VL, DL, ContainerVT, Truncated,
Src, Src, Mask, VL); Src, Src, Mask, VL);
if (!VT.isFixedLengthVector()) if (!VT.isFixedLengthVector())
return Truncated; return Truncated;
return convertFromScalableVector(VT, Truncated, DAG, Subtarget); return convertFromScalableVector(VT, Truncated, DAG, Subtarget);
▲ Show 20 Lines • Show All 8,726 Lines • ▼ Show 20 Lines while (SelectMBBI != SelectEnd) {
} }
SelectMBBI = Next; SelectMBBI = Next;
} }
F->getProperties().reset(MachineFunctionProperties::Property::NoPHIs); F->getProperties().reset(MachineFunctionProperties::Property::NoPHIs);
return TailMBB; return TailMBB;
} }
static MachineBasicBlock *
emitVFCVT_RM_MASK(MachineInstr &MI, MachineBasicBlock *BB, unsigned Opcode) {
DebugLoc DL = MI.getDebugLoc();
const TargetInstrInfo &TII = *BB->getParent()->getSubtarget().getInstrInfo();
MachineRegisterInfo &MRI = BB->getParent()->getRegInfo();
Register SavedFRM = MRI.createVirtualRegister(&RISCV::GPRRegClass);
// Update FRM and save the old value.
BuildMI(*BB, MI, DL, TII.get(RISCV::SwapFRMImm), SavedFRM)
.addImm(MI.getOperand(4).getImm());
// Emit an VFCVT without the FRM operand.
assert(MI.getNumOperands() == 8);
auto MIB = BuildMI(*BB, MI, DL, TII.get(Opcode))
.add(MI.getOperand(0))
.add(MI.getOperand(1))
.add(MI.getOperand(2))
.add(MI.getOperand(3))
.add(MI.getOperand(5))
.add(MI.getOperand(6))
.add(MI.getOperand(7));
if (MI.getFlag(MachineInstr::MIFlag::NoFPExcept))
MIB->setFlag(MachineInstr::MIFlag::NoFPExcept);
// Restore FRM.
BuildMI(*BB, MI, DL, TII.get(RISCV::WriteFRM))
.addReg(SavedFRM, RegState::Kill);
// Erase the pseudoinstruction.
MI.eraseFromParent();
return BB;
}
MachineBasicBlock * MachineBasicBlock *
RISCVTargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI, RISCVTargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
MachineBasicBlock *BB) const { MachineBasicBlock *BB) const {
switch (MI.getOpcode()) { switch (MI.getOpcode()) {
default: default:
llvm_unreachable("Unexpected instr type to insert"); llvm_unreachable("Unexpected instr type to insert");
case RISCV::ReadCycleWide: case RISCV::ReadCycleWide:
assert(!Subtarget.is64Bit() && assert(!Subtarget.is64Bit() &&
Show All 15 LinesRISCVTargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
case RISCV::PseudoQuietFLE_S: case RISCV::PseudoQuietFLE_S:
return emitQuietFCMP(MI, BB, RISCV::FLE_S, RISCV::FEQ_S, Subtarget); return emitQuietFCMP(MI, BB, RISCV::FLE_S, RISCV::FEQ_S, Subtarget);
case RISCV::PseudoQuietFLT_S: case RISCV::PseudoQuietFLT_S:
return emitQuietFCMP(MI, BB, RISCV::FLT_S, RISCV::FEQ_S, Subtarget); return emitQuietFCMP(MI, BB, RISCV::FLT_S, RISCV::FEQ_S, Subtarget);
case RISCV::PseudoQuietFLE_D: case RISCV::PseudoQuietFLE_D:
return emitQuietFCMP(MI, BB, RISCV::FLE_D, RISCV::FEQ_D, Subtarget); return emitQuietFCMP(MI, BB, RISCV::FLE_D, RISCV::FEQ_D, Subtarget);
case RISCV::PseudoQuietFLT_D: case RISCV::PseudoQuietFLT_D:
return emitQuietFCMP(MI, BB, RISCV::FLT_D, RISCV::FEQ_D, Subtarget); return emitQuietFCMP(MI, BB, RISCV::FLT_D, RISCV::FEQ_D, Subtarget);
case RISCV::PseudoVFCVT_RM_X_F_V_M1_MASK:
return emitVFCVT_RM_MASK(MI, BB, RISCV::PseudoVFCVT_X_F_V_M1_MASK);
case RISCV::PseudoVFCVT_RM_X_F_V_M2_MASK:
return emitVFCVT_RM_MASK(MI, BB, RISCV::PseudoVFCVT_X_F_V_M2_MASK);
case RISCV::PseudoVFCVT_RM_X_F_V_M4_MASK:
return emitVFCVT_RM_MASK(MI, BB, RISCV::PseudoVFCVT_X_F_V_M4_MASK);
case RISCV::PseudoVFCVT_RM_X_F_V_M8_MASK:
return emitVFCVT_RM_MASK(MI, BB, RISCV::PseudoVFCVT_X_F_V_M8_MASK);
case RISCV::PseudoVFCVT_RM_X_F_V_MF2_MASK:
return emitVFCVT_RM_MASK(MI, BB, RISCV::PseudoVFCVT_X_F_V_MF2_MASK);
case RISCV::PseudoVFCVT_RM_X_F_V_MF4_MASK:
return emitVFCVT_RM_MASK(MI, BB, RISCV::PseudoVFCVT_X_F_V_MF4_MASK);
} }
} }
void RISCVTargetLowering::AdjustInstrPostInstrSelection(MachineInstr &MI, void RISCVTargetLowering::AdjustInstrPostInstrSelection(MachineInstr &MI,
SDNode *Node) const { SDNode *Node) const {
// Add FRM dependency to any instructions with dynamic rounding mode. // Add FRM dependency to any instructions with dynamic rounding mode.
unsigned Opc = MI.getOpcode(); unsigned Opc = MI.getOpcode();
auto Idx = RISCV::getNamedOperandIdx(Opc, RISCV::OpName::frm); auto Idx = RISCV::getNamedOperandIdx(Opc, RISCV::OpName::frm);
▲ Show 20 Lines • Show All 1,531 Lines • ▼ Show 20 Lines#define NODE_NAME_CASE(NODE) \
NODE_NAME_CASE(UMIN_VL) NODE_NAME_CASE(UMIN_VL)
NODE_NAME_CASE(UMAX_VL) NODE_NAME_CASE(UMAX_VL)
NODE_NAME_CASE(FMINNUM_VL) NODE_NAME_CASE(FMINNUM_VL)
NODE_NAME_CASE(FMAXNUM_VL) NODE_NAME_CASE(FMAXNUM_VL)
NODE_NAME_CASE(MULHS_VL) NODE_NAME_CASE(MULHS_VL)
NODE_NAME_CASE(MULHU_VL) NODE_NAME_CASE(MULHU_VL)
NODE_NAME_CASE(FP_TO_SINT_VL) NODE_NAME_CASE(FP_TO_SINT_VL)
NODE_NAME_CASE(FP_TO_UINT_VL) NODE_NAME_CASE(FP_TO_UINT_VL)
NODE_NAME_CASE(VFCVT_X_F_VL)
NODE_NAME_CASE(SINT_TO_FP_VL) NODE_NAME_CASE(SINT_TO_FP_VL)
NODE_NAME_CASE(UINT_TO_FP_VL) NODE_NAME_CASE(UINT_TO_FP_VL)
NODE_NAME_CASE(FP_EXTEND_VL) NODE_NAME_CASE(FP_EXTEND_VL)
NODE_NAME_CASE(FP_ROUND_VL) NODE_NAME_CASE(FP_ROUND_VL)
NODE_NAME_CASE(VWMUL_VL) NODE_NAME_CASE(VWMUL_VL)
NODE_NAME_CASE(VWMULU_VL) NODE_NAME_CASE(VWMULU_VL)
NODE_NAME_CASE(VWMULSU_VL) NODE_NAME_CASE(VWMULSU_VL)
NODE_NAME_CASE(VWADD_VL) NODE_NAME_CASE(VWADD_VL)
▲ Show 20 Lines • Show All 850 Lines • Show Last 20 Lines

llvm/lib/Target/RISCV/RISCVInstrInfo.td

Show First 20 Lines • Show All 1,549 Lines • ▼ Show 20 Linesclass SwapSysRegImm<SysReg SR, list<Register> Regs>
let hasSideEffects = 0; let hasSideEffects = 0;
let Uses = Regs; let Uses = Regs;
let Defs = Regs; let Defs = Regs;
} }
def ReadFRM : ReadSysReg<SysRegFRM, [FRM]>; def ReadFRM : ReadSysReg<SysRegFRM, [FRM]>;
def WriteFRM : WriteSysReg<SysRegFRM, [FRM]>; def WriteFRM : WriteSysReg<SysRegFRM, [FRM]>;
def WriteFRMImm : WriteSysRegImm<SysRegFRM, [FRM]>; def WriteFRMImm : WriteSysRegImm<SysRegFRM, [FRM]>;
def SwapFRMImm : SwapSysRegImm<SysRegFRM, [FRM]>;
let hasSideEffects = true in { let hasSideEffects = true in {
def ReadFFLAGS : ReadSysReg<SysRegFFLAGS, [FFLAGS]>; def ReadFFLAGS : ReadSysReg<SysRegFFLAGS, [FFLAGS]>;
def WriteFFLAGS : WriteSysReg<SysRegFFLAGS, [FFLAGS]>; def WriteFFLAGS : WriteSysReg<SysRegFFLAGS, [FFLAGS]>;
} }
/// Other pseudo-instructions /// Other pseudo-instructions
// Pessimistically assume the stack pointer will be clobbered // Pessimistically assume the stack pointer will be clobbered
▲ Show 20 Lines • Show All 153 Lines • Show Last 20 Lines

llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td

Show First 20 Lines • Show All 1,025 Lines • ▼ Show 20 Linesclass VPseudoUnaryMaskTA<VReg RetClass, VReg OpClass, string Constraint = ""> :
let Constraints = Join<[Constraint, "$rd = $merge"], ",">.ret; let Constraints = Join<[Constraint, "$rd = $merge"], ",">.ret;
let HasVLOp = 1; let HasVLOp = 1;
let HasSEWOp = 1; let HasSEWOp = 1;
let HasMergeOp = 1; let HasMergeOp = 1;
let HasVecPolicyOp = 1; let HasVecPolicyOp = 1;
let UsesMaskPolicy = 1; let UsesMaskPolicy = 1;
} }
class VPseudoUnaryMaskTA_FRM<VReg RetClass, VReg OpClass, string Constraint = ""> :
frasercrmckUnsubmitted
Not Done
ReplyInline Actions

Really minor but I find TAFRM quite hard to parse. I dunno if TA_FRM is preferable?

frasercrmck: Really minor but I find `TAFRM` quite hard to parse. I dunno if `TA_FRM` is preferable?
Pseudo<(outs GetVRegNoV0<RetClass>.R:$rd),
(ins GetVRegNoV0<RetClass>.R:$merge, OpClass:$rs2,
VMaskOp:$vm, ixlenimm:$frm, AVL:$vl, ixlenimm:$sew, ixlenimm:$policy), []> {
let mayLoad = 0;
let mayStore = 0;
let hasSideEffects = 0;
let Constraints = Join<[Constraint, "$rd = $merge"], ",">.ret;
let HasVLOp = 1;
let HasSEWOp = 1;
let HasMergeOp = 1;
let HasVecPolicyOp = 1;
let UsesMaskPolicy = 1;
let usesCustomInserter = 1;
}
// mask unary operation without maskedoff // mask unary operation without maskedoff
class VPseudoMaskUnarySOutMask: class VPseudoMaskUnarySOutMask:
Pseudo<(outs GPR:$rd), Pseudo<(outs GPR:$rd),
(ins VR:$rs1, VMaskOp:$vm, AVL:$vl, ixlenimm:$sew), []>, (ins VR:$rs1, VMaskOp:$vm, AVL:$vl, ixlenimm:$sew), []>,
RISCVVPseudo { RISCVVPseudo {
let mayLoad = 0; let mayLoad = 0;
let mayStore = 0; let mayStore = 0;
let hasSideEffects = 0; let hasSideEffects = 0;
▲ Show 20 Lines • Show All 1,722 Lines • ▼ Show 20 Lines let VLMul = MInfo.value in {
def "_" # MInfo.MX : VPseudoUnaryNoMask<RetClass, Op1Class, Constraint>; def "_" # MInfo.MX : VPseudoUnaryNoMask<RetClass, Op1Class, Constraint>;
def "_" # MInfo.MX # "_TU": VPseudoUnaryNoMaskTU<RetClass, Op1Class, Constraint>; def "_" # MInfo.MX # "_TU": VPseudoUnaryNoMaskTU<RetClass, Op1Class, Constraint>;
def "_" # MInfo.MX # "_MASK" : VPseudoUnaryMaskTA<RetClass, Op1Class, def "_" # MInfo.MX # "_MASK" : VPseudoUnaryMaskTA<RetClass, Op1Class,
Constraint>, Constraint>,
RISCVMaskedPseudo</*MaskOpIdx*/ 2>; RISCVMaskedPseudo</*MaskOpIdx*/ 2>;
} }
} }
multiclass VPseudoConversionRM<VReg RetClass,
VReg Op1Class,
LMULInfo MInfo,
string Constraint = ""> {
let VLMul = MInfo.value in {
def "_" # MInfo.MX # "_MASK" : VPseudoUnaryMaskTA_FRM<RetClass, Op1Class,
Constraint>;
}
}
multiclass VPseudoVCVTI_V { multiclass VPseudoVCVTI_V {
foreach m = MxListF in foreach m = MxListF in
defm _V : VPseudoConversion<m.vrclass, m.vrclass, m>, defm _V : VPseudoConversion<m.vrclass, m.vrclass, m>,
Sched<[WriteVFCvtFToIV, ReadVFCvtFToIV, ReadVMask]>; Sched<[WriteVFCvtFToIV, ReadVFCvtFToIV, ReadVMask]>;
} }
multiclass VPseudoVCVTI_RM_V {
foreach m = MxListF in
defm _V : VPseudoConversionRM<m.vrclass, m.vrclass, m>,
Sched<[WriteVFCvtFToIV, ReadVFCvtFToIV, ReadVMask]>;
}
multiclass VPseudoVCVTF_V { multiclass VPseudoVCVTF_V {
foreach m = MxListF in foreach m = MxListF in
defm _V : VPseudoConversion<m.vrclass, m.vrclass, m>, defm _V : VPseudoConversion<m.vrclass, m.vrclass, m>,
Sched<[WriteVFCvtIToFV, ReadVFCvtIToFV, ReadVMask]>; Sched<[WriteVFCvtIToFV, ReadVFCvtIToFV, ReadVMask]>;
} }
multiclass VPseudoConversionW_V { multiclass VPseudoConversionW_V {
defvar constraint = "@earlyclobber $rd"; defvar constraint = "@earlyclobber $rd";
▲ Show 20 Lines • Show All 2,058 Lines • ▼ Show 20 Lines
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
let mayRaiseFPException = true in { let mayRaiseFPException = true in {
let Uses = [FRM] in { let Uses = [FRM] in {
defm PseudoVFCVT_XU_F : VPseudoVCVTI_V; defm PseudoVFCVT_XU_F : VPseudoVCVTI_V;
defm PseudoVFCVT_X_F : VPseudoVCVTI_V; defm PseudoVFCVT_X_F : VPseudoVCVTI_V;
} }
defm PseudoVFCVT_RTZ_XU_F : VPseudoVCVTI_V; defm PseudoVFCVT_RTZ_XU_F : VPseudoVCVTI_V;
defm PseudoVFCVT_RTZ_X_F : VPseudoVCVTI_V; defm PseudoVFCVT_RTZ_X_F : VPseudoVCVTI_V;
defm PseudoVFCVT_RM_X_F : VPseudoVCVTI_RM_V;
let Uses = [FRM] in { let Uses = [FRM] in {
defm PseudoVFCVT_F_XU : VPseudoVCVTF_V; defm PseudoVFCVT_F_XU : VPseudoVCVTF_V;
defm PseudoVFCVT_F_X : VPseudoVCVTF_V; defm PseudoVFCVT_F_X : VPseudoVCVTF_V;
} }
} // mayRaiseFPException = true } // mayRaiseFPException = true
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// 14.18. Widening Floating-Point/Integer Type-Convert Instructions // 14.18. Widening Floating-Point/Integer Type-Convert Instructions
▲ Show 20 Lines • Show All 807 Lines • Show Last 20 Lines

llvm/lib/Target/RISCV/RISCVInstrInfoVVLPatterns.td

Show First 20 Lines • Show All 140 Lines • ▼ Show 20 Linesdef SDT_RISCVI2FPOp_VL : SDTypeProfile<1, 3, [
SDTCVecEltisVT<2, i1>, SDTCisSameNumEltsAs<1, 2>, SDTCisVT<3, XLenVT> SDTCVecEltisVT<2, i1>, SDTCisSameNumEltsAs<1, 2>, SDTCisVT<3, XLenVT>
]>; ]>;
def riscv_fp_to_sint_vl : SDNode<"RISCVISD::FP_TO_SINT_VL", SDT_RISCVFP2IOp_VL>; def riscv_fp_to_sint_vl : SDNode<"RISCVISD::FP_TO_SINT_VL", SDT_RISCVFP2IOp_VL>;
def riscv_fp_to_uint_vl : SDNode<"RISCVISD::FP_TO_UINT_VL", SDT_RISCVFP2IOp_VL>; def riscv_fp_to_uint_vl : SDNode<"RISCVISD::FP_TO_UINT_VL", SDT_RISCVFP2IOp_VL>;
def riscv_sint_to_fp_vl : SDNode<"RISCVISD::SINT_TO_FP_VL", SDT_RISCVI2FPOp_VL>; def riscv_sint_to_fp_vl : SDNode<"RISCVISD::SINT_TO_FP_VL", SDT_RISCVI2FPOp_VL>;
def riscv_uint_to_fp_vl : SDNode<"RISCVISD::UINT_TO_FP_VL", SDT_RISCVI2FPOp_VL>; def riscv_uint_to_fp_vl : SDNode<"RISCVISD::UINT_TO_FP_VL", SDT_RISCVI2FPOp_VL>;
def SDT_RISCVVecCvtX2FOp_VL : SDTypeProfile<1, 4, [
SDTCisInt<0>, SDTCisFP<1>, SDTCisSameNumEltsAs<0, 1>,
SDTCVecEltisVT<2, i1>, SDTCisSameNumEltsAs<1, 2>, SDTCisVT<3, XLenVT>,
SDTCisVT<4, XLenVT>
]>;
def riscv_vfcvt_x_f_vl : SDNode<"RISCVISD::VFCVT_X_F_VL", SDT_RISCVVecCvtX2FOp_VL>;
def riscv_setcc_vl : SDNode<"RISCVISD::SETCC_VL", def riscv_setcc_vl : SDNode<"RISCVISD::SETCC_VL",
SDTypeProfile<1, 6, [SDTCVecEltisVT<0, i1>, SDTypeProfile<1, 6, [SDTCVecEltisVT<0, i1>,
SDTCisVec<1>, SDTCisVec<1>,
SDTCisSameNumEltsAs<0, 1>, SDTCisSameNumEltsAs<0, 1>,
SDTCisSameAs<1, 2>, SDTCisSameAs<1, 2>,
SDTCisVT<3, OtherVT>, SDTCisVT<3, OtherVT>,
SDTCisSameAs<0, 4>, SDTCisSameAs<0, 4>,
SDTCisSameAs<0, 5>, SDTCisSameAs<0, 5>,
▲ Show 20 Lines • Show All 483 Lines • ▼ Show 20 Lines def : Pat<(ivti.Vector (vop (fvti.Vector fvti.RegClass:$rs1),
(fvti.Mask V0), (fvti.Mask V0),
VLOpFrag)), VLOpFrag)),
(!cast<Instruction>(instruction_name#"_"#ivti.LMul.MX#"_MASK") (!cast<Instruction>(instruction_name#"_"#ivti.LMul.MX#"_MASK")
(ivti.Vector (IMPLICIT_DEF)), fvti.RegClass:$rs1, (ivti.Vector (IMPLICIT_DEF)), fvti.RegClass:$rs1,
(fvti.Mask V0), GPR:$vl, ivti.Log2SEW, TAIL_AGNOSTIC)>; (fvti.Mask V0), GPR:$vl, ivti.Log2SEW, TAIL_AGNOSTIC)>;
} }
} }
multiclass VPatConvertFP2I_RM_VL_V<SDNode vop, string instruction_name> {
foreach fvti = AllFloatVectors in {
defvar ivti = GetIntVTypeInfo<fvti>.Vti;
def : Pat<(ivti.Vector (vop (fvti.Vector fvti.RegClass:$rs1),
(fvti.Mask V0), (XLenVT timm:$frm),
VLOpFrag)),
(!cast<Instruction>(instruction_name#"_"#ivti.LMul.MX#"_MASK")
(ivti.Vector (IMPLICIT_DEF)), fvti.RegClass:$rs1,
(fvti.Mask V0), timm:$frm, GPR:$vl, ivti.Log2SEW,
TAIL_AGNOSTIC)>;
}
}
multiclass VPatConvertI2FPVL_V<SDNode vop, string instruction_name> { multiclass VPatConvertI2FPVL_V<SDNode vop, string instruction_name> {
foreach fvti = AllFloatVectors in { foreach fvti = AllFloatVectors in {
defvar ivti = GetIntVTypeInfo<fvti>.Vti; defvar ivti = GetIntVTypeInfo<fvti>.Vti;
def : Pat<(fvti.Vector (vop (ivti.Vector ivti.RegClass:$rs1), def : Pat<(fvti.Vector (vop (ivti.Vector ivti.RegClass:$rs1),
(ivti.Mask V0), (ivti.Mask V0),
VLOpFrag)), VLOpFrag)),
(!cast<Instruction>(instruction_name#"_"#fvti.LMul.MX#"_MASK") (!cast<Instruction>(instruction_name#"_"#fvti.LMul.MX#"_MASK")
(fvti.Vector (IMPLICIT_DEF)), ivti.RegClass:$rs1, (fvti.Vector (IMPLICIT_DEF)), ivti.RegClass:$rs1,
▲ Show 20 Lines • Show All 810 Lines • ▼ Show 20 Linesforeach fvti = AllFloatVectors in {
def : Pat<(fvti.Vector (riscv_vfmv_v_f_vl def : Pat<(fvti.Vector (riscv_vfmv_v_f_vl
fvti.Vector:$passthru, (fvti.Scalar fvti.ScalarRegClass:$rs2), VLOpFrag)), fvti.Vector:$passthru, (fvti.Scalar fvti.ScalarRegClass:$rs2), VLOpFrag)),
(!cast<Instruction>("PseudoVFMV_V_" # fvti.ScalarSuffix # "_" # (!cast<Instruction>("PseudoVFMV_V_" # fvti.ScalarSuffix # "_" #
fvti.LMul.MX # "_TU") fvti.LMul.MX # "_TU")
$passthru, (fvti.Scalar fvti.ScalarRegClass:$rs2), $passthru, (fvti.Scalar fvti.ScalarRegClass:$rs2),
GPR:$vl, fvti.Log2SEW)>; GPR:$vl, fvti.Log2SEW)>;
// 14.17. Vector Single-Width Floating-Point/Integer Type-Convert Instructions // 14.17. Vector Single-Width Floating-Point/Integer Type-Convert Instructions
defm : VPatConvertFP2I_RM_VL_V<riscv_vfcvt_x_f_vl, "PseudoVFCVT_RM_X_F_V">;
defm : VPatConvertFP2IVL_V<riscv_fp_to_sint_vl, "PseudoVFCVT_RTZ_X_F_V">; defm : VPatConvertFP2IVL_V<riscv_fp_to_sint_vl, "PseudoVFCVT_RTZ_X_F_V">;
defm : VPatConvertFP2IVL_V<riscv_fp_to_uint_vl, "PseudoVFCVT_RTZ_XU_F_V">; defm : VPatConvertFP2IVL_V<riscv_fp_to_uint_vl, "PseudoVFCVT_RTZ_XU_F_V">;
defm : VPatConvertI2FPVL_V<riscv_sint_to_fp_vl, "PseudoVFCVT_F_X_V">; defm : VPatConvertI2FPVL_V<riscv_sint_to_fp_vl, "PseudoVFCVT_F_X_V">;
defm : VPatConvertI2FPVL_V<riscv_uint_to_fp_vl, "PseudoVFCVT_F_XU_V">; defm : VPatConvertI2FPVL_V<riscv_uint_to_fp_vl, "PseudoVFCVT_F_XU_V">;
// 14.18. Widening Floating-Point/Integer Type-Convert Instructions // 14.18. Widening Floating-Point/Integer Type-Convert Instructions
defm : VPatWConvertFP2IVL_V<riscv_fp_to_sint_vl, "PseudoVFWCVT_RTZ_X_F_V">; defm : VPatWConvertFP2IVL_V<riscv_fp_to_sint_vl, "PseudoVFWCVT_RTZ_X_F_V">;
defm : VPatWConvertFP2IVL_V<riscv_fp_to_uint_vl, "PseudoVFWCVT_RTZ_XU_F_V">; defm : VPatWConvertFP2IVL_V<riscv_fp_to_uint_vl, "PseudoVFWCVT_RTZ_XU_F_V">;
▲ Show 20 Lines • Show All 337 Lines • Show Last 20 Lines

llvm/lib/Target/RISCV/RISCVTargetTransformInfo.cpp

Show First 20 Lines • Show All 258 Lines • ▼ Show 20 LinesInstructionCost RISCVTTIImpl::getGatherScatterOpCost(
return NumLoads * MemOpCost; return NumLoads * MemOpCost;
} }
// Currently, these represent both throughput and codesize costs // Currently, these represent both throughput and codesize costs
// for the respective intrinsics. The costs in this table are simply // for the respective intrinsics. The costs in this table are simply
// instruction counts with the following adjustments made: // instruction counts with the following adjustments made:
// * One vsetvli is considered free. // * One vsetvli is considered free.
static const CostTblEntry VectorIntrinsicCostTable[]{ static const CostTblEntry VectorIntrinsicCostTable[]{
{Intrinsic::floor, MVT::v2f32, 15}, {Intrinsic::floor, MVT::v2f32, 9},
{Intrinsic::floor, MVT::v4f32, 15}, {Intrinsic::floor, MVT::v4f32, 9},
{Intrinsic::floor, MVT::v8f32, 15}, {Intrinsic::floor, MVT::v8f32, 9},
{Intrinsic::floor, MVT::v16f32, 15}, {Intrinsic::floor, MVT::v16f32, 9},
{Intrinsic::floor, MVT::nxv2f32, 15}, {Intrinsic::floor, MVT::nxv2f32, 9},
{Intrinsic::floor, MVT::nxv4f32, 15}, {Intrinsic::floor, MVT::nxv4f32, 9},
{Intrinsic::floor, MVT::nxv8f32, 15}, {Intrinsic::floor, MVT::nxv8f32, 9},
{Intrinsic::floor, MVT::nxv16f32, 15}, {Intrinsic::floor, MVT::nxv16f32, 9},
{Intrinsic::floor, MVT::v2f64, 15}, {Intrinsic::floor, MVT::v2f64, 9},
{Intrinsic::floor, MVT::v4f64, 15}, {Intrinsic::floor, MVT::v4f64, 9},
{Intrinsic::floor, MVT::v8f64, 15}, {Intrinsic::floor, MVT::v8f64, 9},
{Intrinsic::floor, MVT::v16f64, 15}, {Intrinsic::floor, MVT::v16f64, 9},
{Intrinsic::floor, MVT::nxv1f64, 15}, {Intrinsic::floor, MVT::nxv1f64, 9},
{Intrinsic::floor, MVT::nxv2f64, 15}, {Intrinsic::floor, MVT::nxv2f64, 9},
{Intrinsic::floor, MVT::nxv4f64, 15}, {Intrinsic::floor, MVT::nxv4f64, 9},
{Intrinsic::floor, MVT::nxv8f64, 15}, {Intrinsic::floor, MVT::nxv8f64, 9},
{Intrinsic::ceil, MVT::v2f32, 15}, {Intrinsic::ceil, MVT::v2f32, 9},
{Intrinsic::ceil, MVT::v4f32, 15}, {Intrinsic::ceil, MVT::v4f32, 9},
{Intrinsic::ceil, MVT::v8f32, 15}, {Intrinsic::ceil, MVT::v8f32, 9},
{Intrinsic::ceil, MVT::v16f32, 15}, {Intrinsic::ceil, MVT::v16f32, 9},
{Intrinsic::ceil, MVT::nxv2f32, 15}, {Intrinsic::ceil, MVT::nxv2f32, 9},
{Intrinsic::ceil, MVT::nxv4f32, 15}, {Intrinsic::ceil, MVT::nxv4f32, 9},
{Intrinsic::ceil, MVT::nxv8f32, 15}, {Intrinsic::ceil, MVT::nxv8f32, 9},
{Intrinsic::ceil, MVT::nxv16f32, 15}, {Intrinsic::ceil, MVT::nxv16f32, 9},
{Intrinsic::ceil, MVT::v2f64, 15}, {Intrinsic::ceil, MVT::v2f64, 9},
{Intrinsic::ceil, MVT::v4f64, 15}, {Intrinsic::ceil, MVT::v4f64, 9},
{Intrinsic::ceil, MVT::v8f64, 15}, {Intrinsic::ceil, MVT::v8f64, 9},
{Intrinsic::ceil, MVT::v16f64, 15}, {Intrinsic::ceil, MVT::v16f64, 9},
{Intrinsic::ceil, MVT::nxv1f64, 15}, {Intrinsic::ceil, MVT::nxv1f64, 9},
{Intrinsic::ceil, MVT::nxv2f64, 15}, {Intrinsic::ceil, MVT::nxv2f64, 9},
{Intrinsic::ceil, MVT::nxv4f64, 15}, {Intrinsic::ceil, MVT::nxv4f64, 9},
{Intrinsic::ceil, MVT::nxv8f64, 15}, {Intrinsic::ceil, MVT::nxv8f64, 9},
{Intrinsic::trunc, MVT::v2f32, 7}, {Intrinsic::trunc, MVT::v2f32, 7},
{Intrinsic::trunc, MVT::v4f32, 7}, {Intrinsic::trunc, MVT::v4f32, 7},
{Intrinsic::trunc, MVT::v8f32, 7}, {Intrinsic::trunc, MVT::v8f32, 7},
{Intrinsic::trunc, MVT::v16f32, 7}, {Intrinsic::trunc, MVT::v16f32, 7},
{Intrinsic::trunc, MVT::nxv2f32, 7}, {Intrinsic::trunc, MVT::nxv2f32, 7},
{Intrinsic::trunc, MVT::nxv4f32, 7}, {Intrinsic::trunc, MVT::nxv4f32, 7},
{Intrinsic::trunc, MVT::nxv8f32, 7}, {Intrinsic::trunc, MVT::nxv8f32, 7},
{Intrinsic::trunc, MVT::nxv16f32, 7}, {Intrinsic::trunc, MVT::nxv16f32, 7},
▲ Show 20 Lines • Show All 535 Lines • Show Last 20 Lines

llvm/test/Analysis/CostModel/RISCV/fround.ll

; NOTE: Assertions have been autogenerated by utils/update_analyze_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_analyze_test_checks.py
; RUN: opt < %s -passes="print<cost-model>" 2>&1 -disable-output -S -mtriple=riscv64 -mattr=+v,+f,+d -riscv-v-vector-bits-min=-1 | FileCheck %s ; RUN: opt < %s -passes="print<cost-model>" 2>&1 -disable-output -S -mtriple=riscv64 -mattr=+v,+f,+d -riscv-v-vector-bits-min=-1 | FileCheck %s
define void @floor() { define void @floor() {
; CHECK-LABEL: 'floor' ; CHECK-LABEL: 'floor'
; CHECK-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %1 = call float @llvm.floor.f32(float undef) ; CHECK-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %1 = call float @llvm.floor.f32(float undef)
; CHECK-NEXT: Cost Model: Found an estimated cost of 15 for instruction: %2 = call <2 x float> @llvm.floor.v2f32(<2 x float> undef) ; CHECK-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %2 = call <2 x float> @llvm.floor.v2f32(<2 x float> undef)
; CHECK-NEXT: Cost Model: Found an estimated cost of 15 for instruction: %3 = call <4 x float> @llvm.floor.v4f32(<4 x float> undef) ; CHECK-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %3 = call <4 x float> @llvm.floor.v4f32(<4 x float> undef)
; CHECK-NEXT: Cost Model: Found an estimated cost of 15 for instruction: %4 = call <8 x float> @llvm.floor.v8f32(<8 x float> undef) ; CHECK-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %4 = call <8 x float> @llvm.floor.v8f32(<8 x float> undef)
; CHECK-NEXT: Cost Model: Found an estimated cost of 15 for instruction: %5 = call <16 x float> @llvm.floor.v16f32(<16 x float> undef) ; CHECK-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %5 = call <16 x float> @llvm.floor.v16f32(<16 x float> undef)
; CHECK-NEXT: Cost Model: Found an estimated cost of 15 for instruction: %6 = call <vscale x 2 x float> @llvm.floor.nxv2f32(<vscale x 2 x float> undef) ; CHECK-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %6 = call <vscale x 2 x float> @llvm.floor.nxv2f32(<vscale x 2 x float> undef)
; CHECK-NEXT: Cost Model: Found an estimated cost of 15 for instruction: %7 = call <vscale x 4 x float> @llvm.floor.nxv4f32(<vscale x 4 x float> undef) ; CHECK-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %7 = call <vscale x 4 x float> @llvm.floor.nxv4f32(<vscale x 4 x float> undef)
; CHECK-NEXT: Cost Model: Found an estimated cost of 15 for instruction: %8 = call <vscale x 8 x float> @llvm.floor.nxv8f32(<vscale x 8 x float> undef) ; CHECK-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %8 = call <vscale x 8 x float> @llvm.floor.nxv8f32(<vscale x 8 x float> undef)
; CHECK-NEXT: Cost Model: Found an estimated cost of 15 for instruction: %9 = call <vscale x 16 x float> @llvm.floor.nxv16f32(<vscale x 16 x float> undef) ; CHECK-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %9 = call <vscale x 16 x float> @llvm.floor.nxv16f32(<vscale x 16 x float> undef)
; CHECK-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %10 = call double @llvm.floor.f64(double undef) ; CHECK-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %10 = call double @llvm.floor.f64(double undef)
; CHECK-NEXT: Cost Model: Found an estimated cost of 15 for instruction: %11 = call <2 x double> @llvm.floor.v2f64(<2 x double> undef) ; CHECK-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %11 = call <2 x double> @llvm.floor.v2f64(<2 x double> undef)
; CHECK-NEXT: Cost Model: Found an estimated cost of 15 for instruction: %12 = call <4 x double> @llvm.floor.v4f64(<4 x double> undef) ; CHECK-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %12 = call <4 x double> @llvm.floor.v4f64(<4 x double> undef)
; CHECK-NEXT: Cost Model: Found an estimated cost of 15 for instruction: %13 = call <8 x double> @llvm.floor.v8f64(<8 x double> undef) ; CHECK-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %13 = call <8 x double> @llvm.floor.v8f64(<8 x double> undef)
; CHECK-NEXT: Cost Model: Found an estimated cost of 15 for instruction: %14 = call <16 x double> @llvm.floor.v16f64(<16 x double> undef) ; CHECK-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %14 = call <16 x double> @llvm.floor.v16f64(<16 x double> undef)
; CHECK-NEXT: Cost Model: Found an estimated cost of 15 for instruction: %15 = call <vscale x 1 x double> @llvm.floor.nxv1f64(<vscale x 1 x double> undef) ; CHECK-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %15 = call <vscale x 1 x double> @llvm.floor.nxv1f64(<vscale x 1 x double> undef)
; CHECK-NEXT: Cost Model: Found an estimated cost of 15 for instruction: %16 = call <vscale x 2 x double> @llvm.floor.nxv2f64(<vscale x 2 x double> undef) ; CHECK-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %16 = call <vscale x 2 x double> @llvm.floor.nxv2f64(<vscale x 2 x double> undef)
; CHECK-NEXT: Cost Model: Found an estimated cost of 15 for instruction: %17 = call <vscale x 4 x double> @llvm.floor.nxv4f64(<vscale x 4 x double> undef) ; CHECK-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %17 = call <vscale x 4 x double> @llvm.floor.nxv4f64(<vscale x 4 x double> undef)
; CHECK-NEXT: Cost Model: Found an estimated cost of 15 for instruction: %18 = call <vscale x 8 x double> @llvm.floor.nxv8f64(<vscale x 8 x double> undef) ; CHECK-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %18 = call <vscale x 8 x double> @llvm.floor.nxv8f64(<vscale x 8 x double> undef)
; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void
; ;
call float @llvm.floor.f32(float undef) call float @llvm.floor.f32(float undef)
call <2 x float> @llvm.floor.v2f32(<2 x float> undef) call <2 x float> @llvm.floor.v2f32(<2 x float> undef)
call <4 x float> @llvm.floor.v4f32(<4 x float> undef) call <4 x float> @llvm.floor.v4f32(<4 x float> undef)
call <8 x float> @llvm.floor.v8f32(<8 x float> undef) call <8 x float> @llvm.floor.v8f32(<8 x float> undef)
call <16 x float> @llvm.floor.v16f32(<16 x float> undef) call <16 x float> @llvm.floor.v16f32(<16 x float> undef)
call <vscale x 2 x float> @llvm.floor.nvx2f32(<vscale x 2 x float> undef) call <vscale x 2 x float> @llvm.floor.nvx2f32(<vscale x 2 x float> undef)
Show All 10 Lines;
call <vscale x 4 x double> @llvm.floor.nvx5f64(<vscale x 4 x double> undef) call <vscale x 4 x double> @llvm.floor.nvx5f64(<vscale x 4 x double> undef)
call <vscale x 8 x double> @llvm.floor.nvx8f64(<vscale x 8 x double> undef) call <vscale x 8 x double> @llvm.floor.nvx8f64(<vscale x 8 x double> undef)
ret void ret void
} }
define void @ceil() { define void @ceil() {
; CHECK-LABEL: 'ceil' ; CHECK-LABEL: 'ceil'
; CHECK-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %1 = call float @llvm.ceil.f32(float undef) ; CHECK-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %1 = call float @llvm.ceil.f32(float undef)
; CHECK-NEXT: Cost Model: Found an estimated cost of 15 for instruction: %2 = call <2 x float> @llvm.ceil.v2f32(<2 x float> undef) ; CHECK-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %2 = call <2 x float> @llvm.ceil.v2f32(<2 x float> undef)
; CHECK-NEXT: Cost Model: Found an estimated cost of 15 for instruction: %3 = call <4 x float> @llvm.ceil.v4f32(<4 x float> undef) ; CHECK-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %3 = call <4 x float> @llvm.ceil.v4f32(<4 x float> undef)
; CHECK-NEXT: Cost Model: Found an estimated cost of 15 for instruction: %4 = call <8 x float> @llvm.ceil.v8f32(<8 x float> undef) ; CHECK-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %4 = call <8 x float> @llvm.ceil.v8f32(<8 x float> undef)
; CHECK-NEXT: Cost Model: Found an estimated cost of 15 for instruction: %5 = call <16 x float> @llvm.ceil.v16f32(<16 x float> undef) ; CHECK-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %5 = call <16 x float> @llvm.ceil.v16f32(<16 x float> undef)
; CHECK-NEXT: Cost Model: Found an estimated cost of 15 for instruction: %6 = call <vscale x 2 x float> @llvm.ceil.nxv2f32(<vscale x 2 x float> undef) ; CHECK-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %6 = call <vscale x 2 x float> @llvm.ceil.nxv2f32(<vscale x 2 x float> undef)
; CHECK-NEXT: Cost Model: Found an estimated cost of 15 for instruction: %7 = call <vscale x 4 x float> @llvm.ceil.nxv4f32(<vscale x 4 x float> undef) ; CHECK-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %7 = call <vscale x 4 x float> @llvm.ceil.nxv4f32(<vscale x 4 x float> undef)
; CHECK-NEXT: Cost Model: Found an estimated cost of 15 for instruction: %8 = call <vscale x 8 x float> @llvm.ceil.nxv8f32(<vscale x 8 x float> undef) ; CHECK-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %8 = call <vscale x 8 x float> @llvm.ceil.nxv8f32(<vscale x 8 x float> undef)
; CHECK-NEXT: Cost Model: Found an estimated cost of 15 for instruction: %9 = call <vscale x 16 x float> @llvm.ceil.nxv16f32(<vscale x 16 x float> undef) ; CHECK-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %9 = call <vscale x 16 x float> @llvm.ceil.nxv16f32(<vscale x 16 x float> undef)
; CHECK-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %10 = call double @llvm.ceil.f64(double undef) ; CHECK-NEXT: Cost Model: Found an estimated cost of 10 for instruction: %10 = call double @llvm.ceil.f64(double undef)
; CHECK-NEXT: Cost Model: Found an estimated cost of 15 for instruction: %11 = call <2 x double> @llvm.ceil.v2f64(<2 x double> undef) ; CHECK-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %11 = call <2 x double> @llvm.ceil.v2f64(<2 x double> undef)
; CHECK-NEXT: Cost Model: Found an estimated cost of 15 for instruction: %12 = call <4 x double> @llvm.ceil.v4f64(<4 x double> undef) ; CHECK-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %12 = call <4 x double> @llvm.ceil.v4f64(<4 x double> undef)
; CHECK-NEXT: Cost Model: Found an estimated cost of 15 for instruction: %13 = call <8 x double> @llvm.ceil.v8f64(<8 x double> undef) ; CHECK-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %13 = call <8 x double> @llvm.ceil.v8f64(<8 x double> undef)
; CHECK-NEXT: Cost Model: Found an estimated cost of 15 for instruction: %14 = call <16 x double> @llvm.ceil.v16f64(<16 x double> undef) ; CHECK-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %14 = call <16 x double> @llvm.ceil.v16f64(<16 x double> undef)
; CHECK-NEXT: Cost Model: Found an estimated cost of 15 for instruction: %15 = call <vscale x 1 x double> @llvm.ceil.nxv1f64(<vscale x 1 x double> undef) ; CHECK-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %15 = call <vscale x 1 x double> @llvm.ceil.nxv1f64(<vscale x 1 x double> undef)
; CHECK-NEXT: Cost Model: Found an estimated cost of 15 for instruction: %16 = call <vscale x 2 x double> @llvm.ceil.nxv2f64(<vscale x 2 x double> undef) ; CHECK-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %16 = call <vscale x 2 x double> @llvm.ceil.nxv2f64(<vscale x 2 x double> undef)
; CHECK-NEXT: Cost Model: Found an estimated cost of 15 for instruction: %17 = call <vscale x 4 x double> @llvm.ceil.nxv4f64(<vscale x 4 x double> undef) ; CHECK-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %17 = call <vscale x 4 x double> @llvm.ceil.nxv4f64(<vscale x 4 x double> undef)
; CHECK-NEXT: Cost Model: Found an estimated cost of 15 for instruction: %18 = call <vscale x 8 x double> @llvm.ceil.nxv8f64(<vscale x 8 x double> undef) ; CHECK-NEXT: Cost Model: Found an estimated cost of 9 for instruction: %18 = call <vscale x 8 x double> @llvm.ceil.nxv8f64(<vscale x 8 x double> undef)
; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void ; CHECK-NEXT: Cost Model: Found an estimated cost of 1 for instruction: ret void
; ;
call float @llvm.ceil.f32(float undef) call float @llvm.ceil.f32(float undef)
call <2 x float> @llvm.ceil.v2f32(<2 x float> undef) call <2 x float> @llvm.ceil.v2f32(<2 x float> undef)
call <4 x float> @llvm.ceil.v4f32(<4 x float> undef) call <4 x float> @llvm.ceil.v4f32(<4 x float> undef)
call <8 x float> @llvm.ceil.v8f32(<8 x float> undef) call <8 x float> @llvm.ceil.v8f32(<8 x float> undef)
call <16 x float> @llvm.ceil.v16f32(<16 x float> undef) call <16 x float> @llvm.ceil.v16f32(<16 x float> undef)
call <vscale x 2 x float> @llvm.ceil.nvx2f32(<vscale x 2 x float> undef) call <vscale x 2 x float> @llvm.ceil.nvx2f32(<vscale x 2 x float> undef)
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llvm/test/CodeGen/RISCV/rvv/fceil-sdnode.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+experimental-zvfh,+v -target-abi=ilp32d \ ; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+experimental-zvfh,+v -target-abi=ilp32d \
; RUN: -verify-machineinstrs < %s | FileCheck %s ; RUN: -verify-machineinstrs < %s | FileCheck %s
; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+experimental-zvfh,+v -target-abi=lp64d \ ; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+experimental-zvfh,+v -target-abi=lp64d \
; RUN: -verify-machineinstrs < %s | FileCheck %s ; RUN: -verify-machineinstrs < %s | FileCheck %s
define <vscale x 1 x half> @ceil_nxv1f16(<vscale x 1 x half> %x) { define <vscale x 1 x half> @ceil_nxv1f16(<vscale x 1 x half> %x) {
; CHECK-LABEL: ceil_nxv1f16: ; CHECK-LABEL: ceil_nxv1f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lui a0, %hi(.LCPI0_0) ; CHECK-NEXT: lui a0, %hi(.LCPI0_0)
; CHECK-NEXT: flh ft0, %lo(.LCPI0_0)(a0) ; CHECK-NEXT: flh ft0, %lo(.LCPI0_0)(a0)
; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, mu
; CHECK-NEXT: vfabs.v v9, v8 ; CHECK-NEXT: vfabs.v v9, v8
; CHECK-NEXT: vmflt.vf v9, v9, ft0 ; CHECK-NEXT: vmflt.vf v0, v9, ft0
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: fsrmi a0, 3
; CHECK-NEXT: vfcvt.rtz.x.f.v v10, v8, v0.t ; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t
; CHECK-NEXT: lui a0, %hi(.LCPI0_1) ; CHECK-NEXT: fsrm a0
; CHECK-NEXT: flh ft0, %lo(.LCPI0_1)(a0) ; CHECK-NEXT: vfcvt.f.x.v v9, v9, v0.t
; CHECK-NEXT: vfcvt.f.x.v v11, v10, v0.t ; CHECK-NEXT: vfsgnj.vv v8, v9, v8, v0.t
; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmflt.vv v10, v11, v8, v0.t
; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vfadd.vf v11, v11, ft0, v0.t
; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vfsgnj.vv v8, v11, v8, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = call <vscale x 1 x half> @llvm.ceil.nxv1f16(<vscale x 1 x half> %x) %a = call <vscale x 1 x half> @llvm.ceil.nxv1f16(<vscale x 1 x half> %x)
ret <vscale x 1 x half> %a ret <vscale x 1 x half> %a
} }
declare <vscale x 1 x half> @llvm.ceil.nxv1f16(<vscale x 1 x half>) declare <vscale x 1 x half> @llvm.ceil.nxv1f16(<vscale x 1 x half>)
define <vscale x 2 x half> @ceil_nxv2f16(<vscale x 2 x half> %x) { define <vscale x 2 x half> @ceil_nxv2f16(<vscale x 2 x half> %x) {
; CHECK-LABEL: ceil_nxv2f16: ; CHECK-LABEL: ceil_nxv2f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lui a0, %hi(.LCPI1_0) ; CHECK-NEXT: lui a0, %hi(.LCPI1_0)
; CHECK-NEXT: flh ft0, %lo(.LCPI1_0)(a0) ; CHECK-NEXT: flh ft0, %lo(.LCPI1_0)(a0)
; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, mu
; CHECK-NEXT: vfabs.v v9, v8 ; CHECK-NEXT: vfabs.v v9, v8
; CHECK-NEXT: vmflt.vf v9, v9, ft0 ; CHECK-NEXT: vmflt.vf v0, v9, ft0
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: fsrmi a0, 3
; CHECK-NEXT: vfcvt.rtz.x.f.v v10, v8, v0.t ; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t
; CHECK-NEXT: lui a0, %hi(.LCPI1_1) ; CHECK-NEXT: fsrm a0
; CHECK-NEXT: flh ft0, %lo(.LCPI1_1)(a0) ; CHECK-NEXT: vfcvt.f.x.v v9, v9, v0.t
; CHECK-NEXT: vfcvt.f.x.v v11, v10, v0.t ; CHECK-NEXT: vfsgnj.vv v8, v9, v8, v0.t
; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmflt.vv v10, v11, v8, v0.t
; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vfadd.vf v11, v11, ft0, v0.t
; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vfsgnj.vv v8, v11, v8, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = call <vscale x 2 x half> @llvm.ceil.nxv2f16(<vscale x 2 x half> %x) %a = call <vscale x 2 x half> @llvm.ceil.nxv2f16(<vscale x 2 x half> %x)
ret <vscale x 2 x half> %a ret <vscale x 2 x half> %a
} }
declare <vscale x 2 x half> @llvm.ceil.nxv2f16(<vscale x 2 x half>) declare <vscale x 2 x half> @llvm.ceil.nxv2f16(<vscale x 2 x half>)
define <vscale x 4 x half> @ceil_nxv4f16(<vscale x 4 x half> %x) { define <vscale x 4 x half> @ceil_nxv4f16(<vscale x 4 x half> %x) {
; CHECK-LABEL: ceil_nxv4f16: ; CHECK-LABEL: ceil_nxv4f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lui a0, %hi(.LCPI2_0) ; CHECK-NEXT: lui a0, %hi(.LCPI2_0)
; CHECK-NEXT: flh ft0, %lo(.LCPI2_0)(a0) ; CHECK-NEXT: flh ft0, %lo(.LCPI2_0)(a0)
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu
; CHECK-NEXT: vfabs.v v9, v8 ; CHECK-NEXT: vfabs.v v9, v8
; CHECK-NEXT: vmflt.vf v9, v9, ft0 ; CHECK-NEXT: vmflt.vf v0, v9, ft0
; CHECK-NEXT: vmv.v.v v0, v9 ; CHECK-NEXT: fsrmi a0, 3
; CHECK-NEXT: vfcvt.rtz.x.f.v v10, v8, v0.t ; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t
; CHECK-NEXT: lui a0, %hi(.LCPI2_1) ; CHECK-NEXT: fsrm a0
; CHECK-NEXT: flh ft0, %lo(.LCPI2_1)(a0) ; CHECK-NEXT: vfcvt.f.x.v v9, v9, v0.t
; CHECK-NEXT: vfcvt.f.x.v v11, v10, v0.t ; CHECK-NEXT: vfsgnj.vv v8, v9, v8, v0.t
; CHECK-NEXT: vmv.v.v v10, v9
; CHECK-NEXT: vmflt.vv v10, v11, v8, v0.t
; CHECK-NEXT: vmv.v.v v0, v10
; CHECK-NEXT: vfadd.vf v11, v11, ft0, v0.t
; CHECK-NEXT: vmv.v.v v0, v9
; CHECK-NEXT: vfsgnj.vv v8, v11, v8, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = call <vscale x 4 x half> @llvm.ceil.nxv4f16(<vscale x 4 x half> %x) %a = call <vscale x 4 x half> @llvm.ceil.nxv4f16(<vscale x 4 x half> %x)
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 4 x half> @llvm.ceil.nxv4f16(<vscale x 4 x half>) declare <vscale x 4 x half> @llvm.ceil.nxv4f16(<vscale x 4 x half>)
define <vscale x 8 x half> @ceil_nxv8f16(<vscale x 8 x half> %x) { define <vscale x 8 x half> @ceil_nxv8f16(<vscale x 8 x half> %x) {
; CHECK-LABEL: ceil_nxv8f16: ; CHECK-LABEL: ceil_nxv8f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lui a0, %hi(.LCPI3_0) ; CHECK-NEXT: lui a0, %hi(.LCPI3_0)
; CHECK-NEXT: flh ft0, %lo(.LCPI3_0)(a0) ; CHECK-NEXT: flh ft0, %lo(.LCPI3_0)(a0)
; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
; CHECK-NEXT: vfabs.v v12, v8 ; CHECK-NEXT: vfabs.v v10, v8
; CHECK-NEXT: vmflt.vf v10, v12, ft0 ; CHECK-NEXT: vmflt.vf v0, v10, ft0
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: fsrmi a0, 3
; CHECK-NEXT: vfcvt.rtz.x.f.v v12, v8, v0.t ; CHECK-NEXT: vfcvt.x.f.v v10, v8, v0.t
; CHECK-NEXT: lui a0, %hi(.LCPI3_1) ; CHECK-NEXT: fsrm a0
; CHECK-NEXT: flh ft0, %lo(.LCPI3_1)(a0) ; CHECK-NEXT: vfcvt.f.x.v v10, v10, v0.t
; CHECK-NEXT: vfcvt.f.x.v v12, v12, v0.t ; CHECK-NEXT: vfsgnj.vv v8, v10, v8, v0.t
; CHECK-NEXT: vmv1r.v v11, v10
; CHECK-NEXT: vmflt.vv v11, v12, v8, v0.t
; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: vfadd.vf v12, v12, ft0, v0.t
; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vfsgnj.vv v8, v12, v8, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = call <vscale x 8 x half> @llvm.ceil.nxv8f16(<vscale x 8 x half> %x) %a = call <vscale x 8 x half> @llvm.ceil.nxv8f16(<vscale x 8 x half> %x)
ret <vscale x 8 x half> %a ret <vscale x 8 x half> %a
} }
declare <vscale x 8 x half> @llvm.ceil.nxv8f16(<vscale x 8 x half>) declare <vscale x 8 x half> @llvm.ceil.nxv8f16(<vscale x 8 x half>)
define <vscale x 16 x half> @ceil_nxv16f16(<vscale x 16 x half> %x) { define <vscale x 16 x half> @ceil_nxv16f16(<vscale x 16 x half> %x) {
; CHECK-LABEL: ceil_nxv16f16: ; CHECK-LABEL: ceil_nxv16f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lui a0, %hi(.LCPI4_0) ; CHECK-NEXT: lui a0, %hi(.LCPI4_0)
; CHECK-NEXT: flh ft0, %lo(.LCPI4_0)(a0) ; CHECK-NEXT: flh ft0, %lo(.LCPI4_0)(a0)
; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, mu
; CHECK-NEXT: vfabs.v v16, v8 ; CHECK-NEXT: vfabs.v v12, v8
; CHECK-NEXT: vmflt.vf v12, v16, ft0 ; CHECK-NEXT: vmflt.vf v0, v12, ft0
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: fsrmi a0, 3
; CHECK-NEXT: vfcvt.rtz.x.f.v v16, v8, v0.t ; CHECK-NEXT: vfcvt.x.f.v v12, v8, v0.t
; CHECK-NEXT: lui a0, %hi(.LCPI4_1) ; CHECK-NEXT: fsrm a0
; CHECK-NEXT: flh ft0, %lo(.LCPI4_1)(a0) ; CHECK-NEXT: vfcvt.f.x.v v12, v12, v0.t
; CHECK-NEXT: vfcvt.f.x.v v16, v16, v0.t ; CHECK-NEXT: vfsgnj.vv v8, v12, v8, v0.t
; CHECK-NEXT: vmv1r.v v13, v12
; CHECK-NEXT: vmflt.vv v13, v16, v8, v0.t
; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: vfadd.vf v16, v16, ft0, v0.t
; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vfsgnj.vv v8, v16, v8, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = call <vscale x 16 x half> @llvm.ceil.nxv16f16(<vscale x 16 x half> %x) %a = call <vscale x 16 x half> @llvm.ceil.nxv16f16(<vscale x 16 x half> %x)
ret <vscale x 16 x half> %a ret <vscale x 16 x half> %a
} }
declare <vscale x 16 x half> @llvm.ceil.nxv16f16(<vscale x 16 x half>) declare <vscale x 16 x half> @llvm.ceil.nxv16f16(<vscale x 16 x half>)
define <vscale x 32 x half> @ceil_nxv32f16(<vscale x 32 x half> %x) { define <vscale x 32 x half> @ceil_nxv32f16(<vscale x 32 x half> %x) {
; CHECK-LABEL: ceil_nxv32f16: ; CHECK-LABEL: ceil_nxv32f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lui a0, %hi(.LCPI5_0) ; CHECK-NEXT: lui a0, %hi(.LCPI5_0)
; CHECK-NEXT: flh ft0, %lo(.LCPI5_0)(a0) ; CHECK-NEXT: flh ft0, %lo(.LCPI5_0)(a0)
; CHECK-NEXT: vsetvli a0, zero, e16, m8, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e16, m8, ta, mu
; CHECK-NEXT: vfabs.v v24, v8 ; CHECK-NEXT: vfabs.v v16, v8
; CHECK-NEXT: vmflt.vf v16, v24, ft0 ; CHECK-NEXT: vmflt.vf v0, v16, ft0
; CHECK-NEXT: vmv1r.v v0, v16 ; CHECK-NEXT: fsrmi a0, 3
; CHECK-NEXT: vfcvt.rtz.x.f.v v24, v8, v0.t ; CHECK-NEXT: vfcvt.x.f.v v16, v8, v0.t
; CHECK-NEXT: lui a0, %hi(.LCPI5_1) ; CHECK-NEXT: fsrm a0
; CHECK-NEXT: flh ft0, %lo(.LCPI5_1)(a0) ; CHECK-NEXT: vfcvt.f.x.v v16, v16, v0.t
; CHECK-NEXT: vfcvt.f.x.v v24, v24, v0.t ; CHECK-NEXT: vfsgnj.vv v8, v16, v8, v0.t
; CHECK-NEXT: vmv1r.v v17, v16
; CHECK-NEXT: vmflt.vv v17, v24, v8, v0.t
; CHECK-NEXT: vmv1r.v v0, v17
; CHECK-NEXT: vfadd.vf v24, v24, ft0, v0.t
; CHECK-NEXT: vmv1r.v v0, v16
; CHECK-NEXT: vfsgnj.vv v8, v24, v8, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = call <vscale x 32 x half> @llvm.ceil.nxv32f16(<vscale x 32 x half> %x) %a = call <vscale x 32 x half> @llvm.ceil.nxv32f16(<vscale x 32 x half> %x)
ret <vscale x 32 x half> %a ret <vscale x 32 x half> %a
} }
declare <vscale x 32 x half> @llvm.ceil.nxv32f16(<vscale x 32 x half>) declare <vscale x 32 x half> @llvm.ceil.nxv32f16(<vscale x 32 x half>)
define <vscale x 1 x float> @ceil_nxv1f32(<vscale x 1 x float> %x) { define <vscale x 1 x float> @ceil_nxv1f32(<vscale x 1 x float> %x) {
; CHECK-LABEL: ceil_nxv1f32: ; CHECK-LABEL: ceil_nxv1f32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lui a0, %hi(.LCPI6_0) ; CHECK-NEXT: lui a0, %hi(.LCPI6_0)
; CHECK-NEXT: flw ft0, %lo(.LCPI6_0)(a0) ; CHECK-NEXT: flw ft0, %lo(.LCPI6_0)(a0)
; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu
; CHECK-NEXT: vfabs.v v9, v8 ; CHECK-NEXT: vfabs.v v9, v8
; CHECK-NEXT: vmflt.vf v9, v9, ft0 ; CHECK-NEXT: vmflt.vf v0, v9, ft0
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: fsrmi a0, 3
; CHECK-NEXT: vfcvt.rtz.x.f.v v10, v8, v0.t ; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t
; CHECK-NEXT: lui a0, %hi(.LCPI6_1) ; CHECK-NEXT: fsrm a0
; CHECK-NEXT: flw ft0, %lo(.LCPI6_1)(a0) ; CHECK-NEXT: vfcvt.f.x.v v9, v9, v0.t
; CHECK-NEXT: vfcvt.f.x.v v11, v10, v0.t ; CHECK-NEXT: vfsgnj.vv v8, v9, v8, v0.t
; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmflt.vv v10, v11, v8, v0.t
; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vfadd.vf v11, v11, ft0, v0.t
; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vfsgnj.vv v8, v11, v8, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = call <vscale x 1 x float> @llvm.ceil.nxv1f32(<vscale x 1 x float> %x) %a = call <vscale x 1 x float> @llvm.ceil.nxv1f32(<vscale x 1 x float> %x)
ret <vscale x 1 x float> %a ret <vscale x 1 x float> %a
} }
declare <vscale x 1 x float> @llvm.ceil.nxv1f32(<vscale x 1 x float>) declare <vscale x 1 x float> @llvm.ceil.nxv1f32(<vscale x 1 x float>)
define <vscale x 2 x float> @ceil_nxv2f32(<vscale x 2 x float> %x) { define <vscale x 2 x float> @ceil_nxv2f32(<vscale x 2 x float> %x) {
; CHECK-LABEL: ceil_nxv2f32: ; CHECK-LABEL: ceil_nxv2f32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lui a0, %hi(.LCPI7_0) ; CHECK-NEXT: lui a0, %hi(.LCPI7_0)
; CHECK-NEXT: flw ft0, %lo(.LCPI7_0)(a0) ; CHECK-NEXT: flw ft0, %lo(.LCPI7_0)(a0)
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
; CHECK-NEXT: vfabs.v v9, v8 ; CHECK-NEXT: vfabs.v v9, v8
; CHECK-NEXT: vmflt.vf v9, v9, ft0 ; CHECK-NEXT: vmflt.vf v0, v9, ft0
; CHECK-NEXT: vmv.v.v v0, v9 ; CHECK-NEXT: fsrmi a0, 3
; CHECK-NEXT: vfcvt.rtz.x.f.v v10, v8, v0.t ; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t
; CHECK-NEXT: lui a0, %hi(.LCPI7_1) ; CHECK-NEXT: fsrm a0
; CHECK-NEXT: flw ft0, %lo(.LCPI7_1)(a0) ; CHECK-NEXT: vfcvt.f.x.v v9, v9, v0.t
; CHECK-NEXT: vfcvt.f.x.v v11, v10, v0.t ; CHECK-NEXT: vfsgnj.vv v8, v9, v8, v0.t
; CHECK-NEXT: vmv.v.v v10, v9
; CHECK-NEXT: vmflt.vv v10, v11, v8, v0.t
; CHECK-NEXT: vmv.v.v v0, v10
; CHECK-NEXT: vfadd.vf v11, v11, ft0, v0.t
; CHECK-NEXT: vmv.v.v v0, v9
; CHECK-NEXT: vfsgnj.vv v8, v11, v8, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = call <vscale x 2 x float> @llvm.ceil.nxv2f32(<vscale x 2 x float> %x) %a = call <vscale x 2 x float> @llvm.ceil.nxv2f32(<vscale x 2 x float> %x)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 2 x float> @llvm.ceil.nxv2f32(<vscale x 2 x float>) declare <vscale x 2 x float> @llvm.ceil.nxv2f32(<vscale x 2 x float>)
define <vscale x 4 x float> @ceil_nxv4f32(<vscale x 4 x float> %x) { define <vscale x 4 x float> @ceil_nxv4f32(<vscale x 4 x float> %x) {
; CHECK-LABEL: ceil_nxv4f32: ; CHECK-LABEL: ceil_nxv4f32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lui a0, %hi(.LCPI8_0) ; CHECK-NEXT: lui a0, %hi(.LCPI8_0)
; CHECK-NEXT: flw ft0, %lo(.LCPI8_0)(a0) ; CHECK-NEXT: flw ft0, %lo(.LCPI8_0)(a0)
; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu
; CHECK-NEXT: vfabs.v v12, v8 ; CHECK-NEXT: vfabs.v v10, v8
; CHECK-NEXT: vmflt.vf v10, v12, ft0 ; CHECK-NEXT: vmflt.vf v0, v10, ft0
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: fsrmi a0, 3
; CHECK-NEXT: vfcvt.rtz.x.f.v v12, v8, v0.t ; CHECK-NEXT: vfcvt.x.f.v v10, v8, v0.t
; CHECK-NEXT: lui a0, %hi(.LCPI8_1) ; CHECK-NEXT: fsrm a0
; CHECK-NEXT: flw ft0, %lo(.LCPI8_1)(a0) ; CHECK-NEXT: vfcvt.f.x.v v10, v10, v0.t
; CHECK-NEXT: vfcvt.f.x.v v12, v12, v0.t ; CHECK-NEXT: vfsgnj.vv v8, v10, v8, v0.t
; CHECK-NEXT: vmv1r.v v11, v10
; CHECK-NEXT: vmflt.vv v11, v12, v8, v0.t
; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: vfadd.vf v12, v12, ft0, v0.t
; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vfsgnj.vv v8, v12, v8, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = call <vscale x 4 x float> @llvm.ceil.nxv4f32(<vscale x 4 x float> %x) %a = call <vscale x 4 x float> @llvm.ceil.nxv4f32(<vscale x 4 x float> %x)
ret <vscale x 4 x float> %a ret <vscale x 4 x float> %a
} }
declare <vscale x 4 x float> @llvm.ceil.nxv4f32(<vscale x 4 x float>) declare <vscale x 4 x float> @llvm.ceil.nxv4f32(<vscale x 4 x float>)
define <vscale x 8 x float> @ceil_nxv8f32(<vscale x 8 x float> %x) { define <vscale x 8 x float> @ceil_nxv8f32(<vscale x 8 x float> %x) {
; CHECK-LABEL: ceil_nxv8f32: ; CHECK-LABEL: ceil_nxv8f32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lui a0, %hi(.LCPI9_0) ; CHECK-NEXT: lui a0, %hi(.LCPI9_0)
; CHECK-NEXT: flw ft0, %lo(.LCPI9_0)(a0) ; CHECK-NEXT: flw ft0, %lo(.LCPI9_0)(a0)
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
; CHECK-NEXT: vfabs.v v16, v8 ; CHECK-NEXT: vfabs.v v12, v8
; CHECK-NEXT: vmflt.vf v12, v16, ft0 ; CHECK-NEXT: vmflt.vf v0, v12, ft0
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: fsrmi a0, 3
; CHECK-NEXT: vfcvt.rtz.x.f.v v16, v8, v0.t ; CHECK-NEXT: vfcvt.x.f.v v12, v8, v0.t
; CHECK-NEXT: lui a0, %hi(.LCPI9_1) ; CHECK-NEXT: fsrm a0
; CHECK-NEXT: flw ft0, %lo(.LCPI9_1)(a0) ; CHECK-NEXT: vfcvt.f.x.v v12, v12, v0.t
; CHECK-NEXT: vfcvt.f.x.v v16, v16, v0.t ; CHECK-NEXT: vfsgnj.vv v8, v12, v8, v0.t
; CHECK-NEXT: vmv1r.v v13, v12
; CHECK-NEXT: vmflt.vv v13, v16, v8, v0.t
; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: vfadd.vf v16, v16, ft0, v0.t
; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vfsgnj.vv v8, v16, v8, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = call <vscale x 8 x float> @llvm.ceil.nxv8f32(<vscale x 8 x float> %x) %a = call <vscale x 8 x float> @llvm.ceil.nxv8f32(<vscale x 8 x float> %x)
ret <vscale x 8 x float> %a ret <vscale x 8 x float> %a
} }
declare <vscale x 8 x float> @llvm.ceil.nxv8f32(<vscale x 8 x float>) declare <vscale x 8 x float> @llvm.ceil.nxv8f32(<vscale x 8 x float>)
define <vscale x 16 x float> @ceil_nxv16f32(<vscale x 16 x float> %x) { define <vscale x 16 x float> @ceil_nxv16f32(<vscale x 16 x float> %x) {
; CHECK-LABEL: ceil_nxv16f32: ; CHECK-LABEL: ceil_nxv16f32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lui a0, %hi(.LCPI10_0) ; CHECK-NEXT: lui a0, %hi(.LCPI10_0)
; CHECK-NEXT: flw ft0, %lo(.LCPI10_0)(a0) ; CHECK-NEXT: flw ft0, %lo(.LCPI10_0)(a0)
; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, mu
; CHECK-NEXT: vfabs.v v24, v8 ; CHECK-NEXT: vfabs.v v16, v8
; CHECK-NEXT: vmflt.vf v16, v24, ft0 ; CHECK-NEXT: vmflt.vf v0, v16, ft0
; CHECK-NEXT: vmv1r.v v0, v16 ; CHECK-NEXT: fsrmi a0, 3
; CHECK-NEXT: vfcvt.rtz.x.f.v v24, v8, v0.t ; CHECK-NEXT: vfcvt.x.f.v v16, v8, v0.t
; CHECK-NEXT: lui a0, %hi(.LCPI10_1) ; CHECK-NEXT: fsrm a0
; CHECK-NEXT: flw ft0, %lo(.LCPI10_1)(a0) ; CHECK-NEXT: vfcvt.f.x.v v16, v16, v0.t
; CHECK-NEXT: vfcvt.f.x.v v24, v24, v0.t ; CHECK-NEXT: vfsgnj.vv v8, v16, v8, v0.t
; CHECK-NEXT: vmv1r.v v17, v16
; CHECK-NEXT: vmflt.vv v17, v24, v8, v0.t
; CHECK-NEXT: vmv1r.v v0, v17
; CHECK-NEXT: vfadd.vf v24, v24, ft0, v0.t
; CHECK-NEXT: vmv1r.v v0, v16
; CHECK-NEXT: vfsgnj.vv v8, v24, v8, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = call <vscale x 16 x float> @llvm.ceil.nxv16f32(<vscale x 16 x float> %x) %a = call <vscale x 16 x float> @llvm.ceil.nxv16f32(<vscale x 16 x float> %x)
ret <vscale x 16 x float> %a ret <vscale x 16 x float> %a
} }
declare <vscale x 16 x float> @llvm.ceil.nxv16f32(<vscale x 16 x float>) declare <vscale x 16 x float> @llvm.ceil.nxv16f32(<vscale x 16 x float>)
define <vscale x 1 x double> @ceil_nxv1f64(<vscale x 1 x double> %x) { define <vscale x 1 x double> @ceil_nxv1f64(<vscale x 1 x double> %x) {
; CHECK-LABEL: ceil_nxv1f64: ; CHECK-LABEL: ceil_nxv1f64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lui a0, %hi(.LCPI11_0) ; CHECK-NEXT: lui a0, %hi(.LCPI11_0)
; CHECK-NEXT: fld ft0, %lo(.LCPI11_0)(a0) ; CHECK-NEXT: fld ft0, %lo(.LCPI11_0)(a0)
; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu
; CHECK-NEXT: vfabs.v v9, v8 ; CHECK-NEXT: vfabs.v v9, v8
; CHECK-NEXT: vmflt.vf v9, v9, ft0 ; CHECK-NEXT: vmflt.vf v0, v9, ft0
; CHECK-NEXT: vmv.v.v v0, v9 ; CHECK-NEXT: fsrmi a0, 3
; CHECK-NEXT: vfcvt.rtz.x.f.v v10, v8, v0.t ; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t
; CHECK-NEXT: lui a0, %hi(.LCPI11_1) ; CHECK-NEXT: fsrm a0
; CHECK-NEXT: fld ft0, %lo(.LCPI11_1)(a0) ; CHECK-NEXT: vfcvt.f.x.v v9, v9, v0.t
; CHECK-NEXT: vfcvt.f.x.v v11, v10, v0.t ; CHECK-NEXT: vfsgnj.vv v8, v9, v8, v0.t
; CHECK-NEXT: vmv.v.v v10, v9
; CHECK-NEXT: vmflt.vv v10, v11, v8, v0.t
; CHECK-NEXT: vmv.v.v v0, v10
; CHECK-NEXT: vfadd.vf v11, v11, ft0, v0.t
; CHECK-NEXT: vmv.v.v v0, v9
; CHECK-NEXT: vfsgnj.vv v8, v11, v8, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = call <vscale x 1 x double> @llvm.ceil.nxv1f64(<vscale x 1 x double> %x) %a = call <vscale x 1 x double> @llvm.ceil.nxv1f64(<vscale x 1 x double> %x)
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 1 x double> @llvm.ceil.nxv1f64(<vscale x 1 x double>) declare <vscale x 1 x double> @llvm.ceil.nxv1f64(<vscale x 1 x double>)
define <vscale x 2 x double> @ceil_nxv2f64(<vscale x 2 x double> %x) { define <vscale x 2 x double> @ceil_nxv2f64(<vscale x 2 x double> %x) {
; CHECK-LABEL: ceil_nxv2f64: ; CHECK-LABEL: ceil_nxv2f64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lui a0, %hi(.LCPI12_0) ; CHECK-NEXT: lui a0, %hi(.LCPI12_0)
; CHECK-NEXT: fld ft0, %lo(.LCPI12_0)(a0) ; CHECK-NEXT: fld ft0, %lo(.LCPI12_0)(a0)
; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, mu
; CHECK-NEXT: vfabs.v v12, v8 ; CHECK-NEXT: vfabs.v v10, v8
; CHECK-NEXT: vmflt.vf v10, v12, ft0 ; CHECK-NEXT: vmflt.vf v0, v10, ft0
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: fsrmi a0, 3
; CHECK-NEXT: vfcvt.rtz.x.f.v v12, v8, v0.t ; CHECK-NEXT: vfcvt.x.f.v v10, v8, v0.t
; CHECK-NEXT: lui a0, %hi(.LCPI12_1) ; CHECK-NEXT: fsrm a0
; CHECK-NEXT: fld ft0, %lo(.LCPI12_1)(a0) ; CHECK-NEXT: vfcvt.f.x.v v10, v10, v0.t
; CHECK-NEXT: vfcvt.f.x.v v12, v12, v0.t ; CHECK-NEXT: vfsgnj.vv v8, v10, v8, v0.t
; CHECK-NEXT: vmv1r.v v11, v10
; CHECK-NEXT: vmflt.vv v11, v12, v8, v0.t
; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: vfadd.vf v12, v12, ft0, v0.t
; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vfsgnj.vv v8, v12, v8, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = call <vscale x 2 x double> @llvm.ceil.nxv2f64(<vscale x 2 x double> %x) %a = call <vscale x 2 x double> @llvm.ceil.nxv2f64(<vscale x 2 x double> %x)
ret <vscale x 2 x double> %a ret <vscale x 2 x double> %a
} }
declare <vscale x 2 x double> @llvm.ceil.nxv2f64(<vscale x 2 x double>) declare <vscale x 2 x double> @llvm.ceil.nxv2f64(<vscale x 2 x double>)
define <vscale x 4 x double> @ceil_nxv4f64(<vscale x 4 x double> %x) { define <vscale x 4 x double> @ceil_nxv4f64(<vscale x 4 x double> %x) {
; CHECK-LABEL: ceil_nxv4f64: ; CHECK-LABEL: ceil_nxv4f64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lui a0, %hi(.LCPI13_0) ; CHECK-NEXT: lui a0, %hi(.LCPI13_0)
; CHECK-NEXT: fld ft0, %lo(.LCPI13_0)(a0) ; CHECK-NEXT: fld ft0, %lo(.LCPI13_0)(a0)
; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, mu
; CHECK-NEXT: vfabs.v v16, v8 ; CHECK-NEXT: vfabs.v v12, v8
; CHECK-NEXT: vmflt.vf v12, v16, ft0 ; CHECK-NEXT: vmflt.vf v0, v12, ft0
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: fsrmi a0, 3
; CHECK-NEXT: vfcvt.rtz.x.f.v v16, v8, v0.t ; CHECK-NEXT: vfcvt.x.f.v v12, v8, v0.t
; CHECK-NEXT: lui a0, %hi(.LCPI13_1) ; CHECK-NEXT: fsrm a0
; CHECK-NEXT: fld ft0, %lo(.LCPI13_1)(a0) ; CHECK-NEXT: vfcvt.f.x.v v12, v12, v0.t
; CHECK-NEXT: vfcvt.f.x.v v16, v16, v0.t ; CHECK-NEXT: vfsgnj.vv v8, v12, v8, v0.t
; CHECK-NEXT: vmv1r.v v13, v12
; CHECK-NEXT: vmflt.vv v13, v16, v8, v0.t
; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: vfadd.vf v16, v16, ft0, v0.t
; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vfsgnj.vv v8, v16, v8, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = call <vscale x 4 x double> @llvm.ceil.nxv4f64(<vscale x 4 x double> %x) %a = call <vscale x 4 x double> @llvm.ceil.nxv4f64(<vscale x 4 x double> %x)
ret <vscale x 4 x double> %a ret <vscale x 4 x double> %a
} }
declare <vscale x 4 x double> @llvm.ceil.nxv4f64(<vscale x 4 x double>) declare <vscale x 4 x double> @llvm.ceil.nxv4f64(<vscale x 4 x double>)
define <vscale x 8 x double> @ceil_nxv8f64(<vscale x 8 x double> %x) { define <vscale x 8 x double> @ceil_nxv8f64(<vscale x 8 x double> %x) {
; CHECK-LABEL: ceil_nxv8f64: ; CHECK-LABEL: ceil_nxv8f64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lui a0, %hi(.LCPI14_0) ; CHECK-NEXT: lui a0, %hi(.LCPI14_0)
; CHECK-NEXT: fld ft0, %lo(.LCPI14_0)(a0) ; CHECK-NEXT: fld ft0, %lo(.LCPI14_0)(a0)
; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
; CHECK-NEXT: vfabs.v v24, v8 ; CHECK-NEXT: vfabs.v v16, v8
; CHECK-NEXT: vmflt.vf v16, v24, ft0 ; CHECK-NEXT: vmflt.vf v0, v16, ft0
; CHECK-NEXT: vmv1r.v v0, v16 ; CHECK-NEXT: fsrmi a0, 3
; CHECK-NEXT: vfcvt.rtz.x.f.v v24, v8, v0.t ; CHECK-NEXT: vfcvt.x.f.v v16, v8, v0.t
; CHECK-NEXT: lui a0, %hi(.LCPI14_1) ; CHECK-NEXT: fsrm a0
; CHECK-NEXT: fld ft0, %lo(.LCPI14_1)(a0) ; CHECK-NEXT: vfcvt.f.x.v v16, v16, v0.t
; CHECK-NEXT: vfcvt.f.x.v v24, v24, v0.t ; CHECK-NEXT: vfsgnj.vv v8, v16, v8, v0.t
; CHECK-NEXT: vmv1r.v v17, v16
; CHECK-NEXT: vmflt.vv v17, v24, v8, v0.t
; CHECK-NEXT: vmv1r.v v0, v17
; CHECK-NEXT: vfadd.vf v24, v24, ft0, v0.t
; CHECK-NEXT: vmv1r.v v0, v16
; CHECK-NEXT: vfsgnj.vv v8, v24, v8, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = call <vscale x 8 x double> @llvm.ceil.nxv8f64(<vscale x 8 x double> %x) %a = call <vscale x 8 x double> @llvm.ceil.nxv8f64(<vscale x 8 x double> %x)
ret <vscale x 8 x double> %a ret <vscale x 8 x double> %a
} }
declare <vscale x 8 x double> @llvm.ceil.nxv8f64(<vscale x 8 x double>) declare <vscale x 8 x double> @llvm.ceil.nxv8f64(<vscale x 8 x double>)

llvm/test/CodeGen/RISCV/rvv/ffloor-sdnode.ll

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+experimental-zvfh,+v -target-abi=ilp32d \ ; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+experimental-zvfh,+v -target-abi=ilp32d \
; RUN: -verify-machineinstrs < %s | FileCheck %s ; RUN: -verify-machineinstrs < %s | FileCheck %s
; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+experimental-zvfh,+v -target-abi=lp64d \ ; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+experimental-zvfh,+v -target-abi=lp64d \
; RUN: -verify-machineinstrs < %s | FileCheck %s ; RUN: -verify-machineinstrs < %s | FileCheck %s
define <vscale x 1 x half> @floor_nxv1f16(<vscale x 1 x half> %x) { define <vscale x 1 x half> @floor_nxv1f16(<vscale x 1 x half> %x) {
; CHECK-LABEL: floor_nxv1f16: ; CHECK-LABEL: floor_nxv1f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lui a0, %hi(.LCPI0_0) ; CHECK-NEXT: lui a0, %hi(.LCPI0_0)
; CHECK-NEXT: flh ft0, %lo(.LCPI0_0)(a0) ; CHECK-NEXT: flh ft0, %lo(.LCPI0_0)(a0)
; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e16, mf4, ta, mu
; CHECK-NEXT: vfabs.v v9, v8 ; CHECK-NEXT: vfabs.v v9, v8
; CHECK-NEXT: vmflt.vf v9, v9, ft0 ; CHECK-NEXT: vmflt.vf v0, v9, ft0
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: fsrmi a0, 2
; CHECK-NEXT: vfcvt.rtz.x.f.v v10, v8, v0.t ; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t
; CHECK-NEXT: lui a0, %hi(.LCPI0_1) ; CHECK-NEXT: fsrm a0
; CHECK-NEXT: flh ft0, %lo(.LCPI0_1)(a0) ; CHECK-NEXT: vfcvt.f.x.v v9, v9, v0.t
; CHECK-NEXT: vfcvt.f.x.v v11, v10, v0.t ; CHECK-NEXT: vfsgnj.vv v8, v9, v8, v0.t
; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmflt.vv v10, v8, v11, v0.t
; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vfsub.vf v11, v11, ft0, v0.t
; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vfsgnj.vv v8, v11, v8, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = call <vscale x 1 x half> @llvm.floor.nxv1f16(<vscale x 1 x half> %x) %a = call <vscale x 1 x half> @llvm.floor.nxv1f16(<vscale x 1 x half> %x)
ret <vscale x 1 x half> %a ret <vscale x 1 x half> %a
} }
declare <vscale x 1 x half> @llvm.floor.nxv1f16(<vscale x 1 x half>) declare <vscale x 1 x half> @llvm.floor.nxv1f16(<vscale x 1 x half>)
define <vscale x 2 x half> @floor_nxv2f16(<vscale x 2 x half> %x) { define <vscale x 2 x half> @floor_nxv2f16(<vscale x 2 x half> %x) {
; CHECK-LABEL: floor_nxv2f16: ; CHECK-LABEL: floor_nxv2f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lui a0, %hi(.LCPI1_0) ; CHECK-NEXT: lui a0, %hi(.LCPI1_0)
; CHECK-NEXT: flh ft0, %lo(.LCPI1_0)(a0) ; CHECK-NEXT: flh ft0, %lo(.LCPI1_0)(a0)
; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e16, mf2, ta, mu
; CHECK-NEXT: vfabs.v v9, v8 ; CHECK-NEXT: vfabs.v v9, v8
; CHECK-NEXT: vmflt.vf v9, v9, ft0 ; CHECK-NEXT: vmflt.vf v0, v9, ft0
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: fsrmi a0, 2
; CHECK-NEXT: vfcvt.rtz.x.f.v v10, v8, v0.t ; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t
; CHECK-NEXT: lui a0, %hi(.LCPI1_1) ; CHECK-NEXT: fsrm a0
; CHECK-NEXT: flh ft0, %lo(.LCPI1_1)(a0) ; CHECK-NEXT: vfcvt.f.x.v v9, v9, v0.t
; CHECK-NEXT: vfcvt.f.x.v v11, v10, v0.t ; CHECK-NEXT: vfsgnj.vv v8, v9, v8, v0.t
; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmflt.vv v10, v8, v11, v0.t
; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vfsub.vf v11, v11, ft0, v0.t
; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vfsgnj.vv v8, v11, v8, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = call <vscale x 2 x half> @llvm.floor.nxv2f16(<vscale x 2 x half> %x) %a = call <vscale x 2 x half> @llvm.floor.nxv2f16(<vscale x 2 x half> %x)
ret <vscale x 2 x half> %a ret <vscale x 2 x half> %a
} }
declare <vscale x 2 x half> @llvm.floor.nxv2f16(<vscale x 2 x half>) declare <vscale x 2 x half> @llvm.floor.nxv2f16(<vscale x 2 x half>)
define <vscale x 4 x half> @floor_nxv4f16(<vscale x 4 x half> %x) { define <vscale x 4 x half> @floor_nxv4f16(<vscale x 4 x half> %x) {
; CHECK-LABEL: floor_nxv4f16: ; CHECK-LABEL: floor_nxv4f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lui a0, %hi(.LCPI2_0) ; CHECK-NEXT: lui a0, %hi(.LCPI2_0)
; CHECK-NEXT: flh ft0, %lo(.LCPI2_0)(a0) ; CHECK-NEXT: flh ft0, %lo(.LCPI2_0)(a0)
; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e16, m1, ta, mu
; CHECK-NEXT: vfabs.v v9, v8 ; CHECK-NEXT: vfabs.v v9, v8
; CHECK-NEXT: vmflt.vf v9, v9, ft0 ; CHECK-NEXT: vmflt.vf v0, v9, ft0
; CHECK-NEXT: vmv.v.v v0, v9 ; CHECK-NEXT: fsrmi a0, 2
; CHECK-NEXT: vfcvt.rtz.x.f.v v10, v8, v0.t ; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t
; CHECK-NEXT: lui a0, %hi(.LCPI2_1) ; CHECK-NEXT: fsrm a0
; CHECK-NEXT: flh ft0, %lo(.LCPI2_1)(a0) ; CHECK-NEXT: vfcvt.f.x.v v9, v9, v0.t
; CHECK-NEXT: vfcvt.f.x.v v11, v10, v0.t ; CHECK-NEXT: vfsgnj.vv v8, v9, v8, v0.t
; CHECK-NEXT: vmv.v.v v10, v9
; CHECK-NEXT: vmflt.vv v10, v8, v11, v0.t
; CHECK-NEXT: vmv.v.v v0, v10
; CHECK-NEXT: vfsub.vf v11, v11, ft0, v0.t
; CHECK-NEXT: vmv.v.v v0, v9
; CHECK-NEXT: vfsgnj.vv v8, v11, v8, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = call <vscale x 4 x half> @llvm.floor.nxv4f16(<vscale x 4 x half> %x) %a = call <vscale x 4 x half> @llvm.floor.nxv4f16(<vscale x 4 x half> %x)
ret <vscale x 4 x half> %a ret <vscale x 4 x half> %a
} }
declare <vscale x 4 x half> @llvm.floor.nxv4f16(<vscale x 4 x half>) declare <vscale x 4 x half> @llvm.floor.nxv4f16(<vscale x 4 x half>)
define <vscale x 8 x half> @floor_nxv8f16(<vscale x 8 x half> %x) { define <vscale x 8 x half> @floor_nxv8f16(<vscale x 8 x half> %x) {
; CHECK-LABEL: floor_nxv8f16: ; CHECK-LABEL: floor_nxv8f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lui a0, %hi(.LCPI3_0) ; CHECK-NEXT: lui a0, %hi(.LCPI3_0)
; CHECK-NEXT: flh ft0, %lo(.LCPI3_0)(a0) ; CHECK-NEXT: flh ft0, %lo(.LCPI3_0)(a0)
; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e16, m2, ta, mu
; CHECK-NEXT: vfabs.v v12, v8 ; CHECK-NEXT: vfabs.v v10, v8
; CHECK-NEXT: vmflt.vf v10, v12, ft0 ; CHECK-NEXT: vmflt.vf v0, v10, ft0
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: fsrmi a0, 2
; CHECK-NEXT: vfcvt.rtz.x.f.v v12, v8, v0.t ; CHECK-NEXT: vfcvt.x.f.v v10, v8, v0.t
; CHECK-NEXT: lui a0, %hi(.LCPI3_1) ; CHECK-NEXT: fsrm a0
; CHECK-NEXT: flh ft0, %lo(.LCPI3_1)(a0) ; CHECK-NEXT: vfcvt.f.x.v v10, v10, v0.t
; CHECK-NEXT: vfcvt.f.x.v v12, v12, v0.t ; CHECK-NEXT: vfsgnj.vv v8, v10, v8, v0.t
; CHECK-NEXT: vmv1r.v v11, v10
; CHECK-NEXT: vmflt.vv v11, v8, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: vfsub.vf v12, v12, ft0, v0.t
; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vfsgnj.vv v8, v12, v8, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = call <vscale x 8 x half> @llvm.floor.nxv8f16(<vscale x 8 x half> %x) %a = call <vscale x 8 x half> @llvm.floor.nxv8f16(<vscale x 8 x half> %x)
ret <vscale x 8 x half> %a ret <vscale x 8 x half> %a
} }
declare <vscale x 8 x half> @llvm.floor.nxv8f16(<vscale x 8 x half>) declare <vscale x 8 x half> @llvm.floor.nxv8f16(<vscale x 8 x half>)
define <vscale x 16 x half> @floor_nxv16f16(<vscale x 16 x half> %x) { define <vscale x 16 x half> @floor_nxv16f16(<vscale x 16 x half> %x) {
; CHECK-LABEL: floor_nxv16f16: ; CHECK-LABEL: floor_nxv16f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lui a0, %hi(.LCPI4_0) ; CHECK-NEXT: lui a0, %hi(.LCPI4_0)
; CHECK-NEXT: flh ft0, %lo(.LCPI4_0)(a0) ; CHECK-NEXT: flh ft0, %lo(.LCPI4_0)(a0)
; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e16, m4, ta, mu
; CHECK-NEXT: vfabs.v v16, v8 ; CHECK-NEXT: vfabs.v v12, v8
; CHECK-NEXT: vmflt.vf v12, v16, ft0 ; CHECK-NEXT: vmflt.vf v0, v12, ft0
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: fsrmi a0, 2
; CHECK-NEXT: vfcvt.rtz.x.f.v v16, v8, v0.t ; CHECK-NEXT: vfcvt.x.f.v v12, v8, v0.t
; CHECK-NEXT: lui a0, %hi(.LCPI4_1) ; CHECK-NEXT: fsrm a0
; CHECK-NEXT: flh ft0, %lo(.LCPI4_1)(a0) ; CHECK-NEXT: vfcvt.f.x.v v12, v12, v0.t
; CHECK-NEXT: vfcvt.f.x.v v16, v16, v0.t ; CHECK-NEXT: vfsgnj.vv v8, v12, v8, v0.t
; CHECK-NEXT: vmv1r.v v13, v12
; CHECK-NEXT: vmflt.vv v13, v8, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: vfsub.vf v16, v16, ft0, v0.t
; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vfsgnj.vv v8, v16, v8, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = call <vscale x 16 x half> @llvm.floor.nxv16f16(<vscale x 16 x half> %x) %a = call <vscale x 16 x half> @llvm.floor.nxv16f16(<vscale x 16 x half> %x)
ret <vscale x 16 x half> %a ret <vscale x 16 x half> %a
} }
declare <vscale x 16 x half> @llvm.floor.nxv16f16(<vscale x 16 x half>) declare <vscale x 16 x half> @llvm.floor.nxv16f16(<vscale x 16 x half>)
define <vscale x 32 x half> @floor_nxv32f16(<vscale x 32 x half> %x) { define <vscale x 32 x half> @floor_nxv32f16(<vscale x 32 x half> %x) {
; CHECK-LABEL: floor_nxv32f16: ; CHECK-LABEL: floor_nxv32f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lui a0, %hi(.LCPI5_0) ; CHECK-NEXT: lui a0, %hi(.LCPI5_0)
; CHECK-NEXT: flh ft0, %lo(.LCPI5_0)(a0) ; CHECK-NEXT: flh ft0, %lo(.LCPI5_0)(a0)
; CHECK-NEXT: vsetvli a0, zero, e16, m8, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e16, m8, ta, mu
; CHECK-NEXT: vfabs.v v24, v8 ; CHECK-NEXT: vfabs.v v16, v8
; CHECK-NEXT: vmflt.vf v16, v24, ft0 ; CHECK-NEXT: vmflt.vf v0, v16, ft0
; CHECK-NEXT: vmv1r.v v0, v16 ; CHECK-NEXT: fsrmi a0, 2
; CHECK-NEXT: vfcvt.rtz.x.f.v v24, v8, v0.t ; CHECK-NEXT: vfcvt.x.f.v v16, v8, v0.t
; CHECK-NEXT: lui a0, %hi(.LCPI5_1) ; CHECK-NEXT: fsrm a0
; CHECK-NEXT: flh ft0, %lo(.LCPI5_1)(a0) ; CHECK-NEXT: vfcvt.f.x.v v16, v16, v0.t
; CHECK-NEXT: vfcvt.f.x.v v24, v24, v0.t ; CHECK-NEXT: vfsgnj.vv v8, v16, v8, v0.t
; CHECK-NEXT: vmv1r.v v17, v16
; CHECK-NEXT: vmflt.vv v17, v8, v24, v0.t
; CHECK-NEXT: vmv1r.v v0, v17
; CHECK-NEXT: vfsub.vf v24, v24, ft0, v0.t
; CHECK-NEXT: vmv1r.v v0, v16
; CHECK-NEXT: vfsgnj.vv v8, v24, v8, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = call <vscale x 32 x half> @llvm.floor.nxv32f16(<vscale x 32 x half> %x) %a = call <vscale x 32 x half> @llvm.floor.nxv32f16(<vscale x 32 x half> %x)
ret <vscale x 32 x half> %a ret <vscale x 32 x half> %a
} }
declare <vscale x 32 x half> @llvm.floor.nxv32f16(<vscale x 32 x half>) declare <vscale x 32 x half> @llvm.floor.nxv32f16(<vscale x 32 x half>)
define <vscale x 1 x float> @floor_nxv1f32(<vscale x 1 x float> %x) { define <vscale x 1 x float> @floor_nxv1f32(<vscale x 1 x float> %x) {
; CHECK-LABEL: floor_nxv1f32: ; CHECK-LABEL: floor_nxv1f32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lui a0, %hi(.LCPI6_0) ; CHECK-NEXT: lui a0, %hi(.LCPI6_0)
; CHECK-NEXT: flw ft0, %lo(.LCPI6_0)(a0) ; CHECK-NEXT: flw ft0, %lo(.LCPI6_0)(a0)
; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e32, mf2, ta, mu
; CHECK-NEXT: vfabs.v v9, v8 ; CHECK-NEXT: vfabs.v v9, v8
; CHECK-NEXT: vmflt.vf v9, v9, ft0 ; CHECK-NEXT: vmflt.vf v0, v9, ft0
; CHECK-NEXT: vmv1r.v v0, v9 ; CHECK-NEXT: fsrmi a0, 2
; CHECK-NEXT: vfcvt.rtz.x.f.v v10, v8, v0.t ; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t
; CHECK-NEXT: lui a0, %hi(.LCPI6_1) ; CHECK-NEXT: fsrm a0
; CHECK-NEXT: flw ft0, %lo(.LCPI6_1)(a0) ; CHECK-NEXT: vfcvt.f.x.v v9, v9, v0.t
; CHECK-NEXT: vfcvt.f.x.v v11, v10, v0.t ; CHECK-NEXT: vfsgnj.vv v8, v9, v8, v0.t
; CHECK-NEXT: vmv1r.v v10, v9
; CHECK-NEXT: vmflt.vv v10, v8, v11, v0.t
; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vfsub.vf v11, v11, ft0, v0.t
; CHECK-NEXT: vmv1r.v v0, v9
; CHECK-NEXT: vfsgnj.vv v8, v11, v8, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = call <vscale x 1 x float> @llvm.floor.nxv1f32(<vscale x 1 x float> %x) %a = call <vscale x 1 x float> @llvm.floor.nxv1f32(<vscale x 1 x float> %x)
ret <vscale x 1 x float> %a ret <vscale x 1 x float> %a
} }
declare <vscale x 1 x float> @llvm.floor.nxv1f32(<vscale x 1 x float>) declare <vscale x 1 x float> @llvm.floor.nxv1f32(<vscale x 1 x float>)
define <vscale x 2 x float> @floor_nxv2f32(<vscale x 2 x float> %x) { define <vscale x 2 x float> @floor_nxv2f32(<vscale x 2 x float> %x) {
; CHECK-LABEL: floor_nxv2f32: ; CHECK-LABEL: floor_nxv2f32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lui a0, %hi(.LCPI7_0) ; CHECK-NEXT: lui a0, %hi(.LCPI7_0)
; CHECK-NEXT: flw ft0, %lo(.LCPI7_0)(a0) ; CHECK-NEXT: flw ft0, %lo(.LCPI7_0)(a0)
; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, mu
; CHECK-NEXT: vfabs.v v9, v8 ; CHECK-NEXT: vfabs.v v9, v8
; CHECK-NEXT: vmflt.vf v9, v9, ft0 ; CHECK-NEXT: vmflt.vf v0, v9, ft0
; CHECK-NEXT: vmv.v.v v0, v9 ; CHECK-NEXT: fsrmi a0, 2
; CHECK-NEXT: vfcvt.rtz.x.f.v v10, v8, v0.t ; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t
; CHECK-NEXT: lui a0, %hi(.LCPI7_1) ; CHECK-NEXT: fsrm a0
; CHECK-NEXT: flw ft0, %lo(.LCPI7_1)(a0) ; CHECK-NEXT: vfcvt.f.x.v v9, v9, v0.t
; CHECK-NEXT: vfcvt.f.x.v v11, v10, v0.t ; CHECK-NEXT: vfsgnj.vv v8, v9, v8, v0.t
; CHECK-NEXT: vmv.v.v v10, v9
; CHECK-NEXT: vmflt.vv v10, v8, v11, v0.t
; CHECK-NEXT: vmv.v.v v0, v10
; CHECK-NEXT: vfsub.vf v11, v11, ft0, v0.t
; CHECK-NEXT: vmv.v.v v0, v9
; CHECK-NEXT: vfsgnj.vv v8, v11, v8, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = call <vscale x 2 x float> @llvm.floor.nxv2f32(<vscale x 2 x float> %x) %a = call <vscale x 2 x float> @llvm.floor.nxv2f32(<vscale x 2 x float> %x)
ret <vscale x 2 x float> %a ret <vscale x 2 x float> %a
} }
declare <vscale x 2 x float> @llvm.floor.nxv2f32(<vscale x 2 x float>) declare <vscale x 2 x float> @llvm.floor.nxv2f32(<vscale x 2 x float>)
define <vscale x 4 x float> @floor_nxv4f32(<vscale x 4 x float> %x) { define <vscale x 4 x float> @floor_nxv4f32(<vscale x 4 x float> %x) {
; CHECK-LABEL: floor_nxv4f32: ; CHECK-LABEL: floor_nxv4f32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lui a0, %hi(.LCPI8_0) ; CHECK-NEXT: lui a0, %hi(.LCPI8_0)
; CHECK-NEXT: flw ft0, %lo(.LCPI8_0)(a0) ; CHECK-NEXT: flw ft0, %lo(.LCPI8_0)(a0)
; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, mu
; CHECK-NEXT: vfabs.v v12, v8 ; CHECK-NEXT: vfabs.v v10, v8
; CHECK-NEXT: vmflt.vf v10, v12, ft0 ; CHECK-NEXT: vmflt.vf v0, v10, ft0
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: fsrmi a0, 2
; CHECK-NEXT: vfcvt.rtz.x.f.v v12, v8, v0.t ; CHECK-NEXT: vfcvt.x.f.v v10, v8, v0.t
; CHECK-NEXT: lui a0, %hi(.LCPI8_1) ; CHECK-NEXT: fsrm a0
; CHECK-NEXT: flw ft0, %lo(.LCPI8_1)(a0) ; CHECK-NEXT: vfcvt.f.x.v v10, v10, v0.t
; CHECK-NEXT: vfcvt.f.x.v v12, v12, v0.t ; CHECK-NEXT: vfsgnj.vv v8, v10, v8, v0.t
; CHECK-NEXT: vmv1r.v v11, v10
; CHECK-NEXT: vmflt.vv v11, v8, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: vfsub.vf v12, v12, ft0, v0.t
; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vfsgnj.vv v8, v12, v8, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = call <vscale x 4 x float> @llvm.floor.nxv4f32(<vscale x 4 x float> %x) %a = call <vscale x 4 x float> @llvm.floor.nxv4f32(<vscale x 4 x float> %x)
ret <vscale x 4 x float> %a ret <vscale x 4 x float> %a
} }
declare <vscale x 4 x float> @llvm.floor.nxv4f32(<vscale x 4 x float>) declare <vscale x 4 x float> @llvm.floor.nxv4f32(<vscale x 4 x float>)
define <vscale x 8 x float> @floor_nxv8f32(<vscale x 8 x float> %x) { define <vscale x 8 x float> @floor_nxv8f32(<vscale x 8 x float> %x) {
; CHECK-LABEL: floor_nxv8f32: ; CHECK-LABEL: floor_nxv8f32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lui a0, %hi(.LCPI9_0) ; CHECK-NEXT: lui a0, %hi(.LCPI9_0)
; CHECK-NEXT: flw ft0, %lo(.LCPI9_0)(a0) ; CHECK-NEXT: flw ft0, %lo(.LCPI9_0)(a0)
; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, mu
; CHECK-NEXT: vfabs.v v16, v8 ; CHECK-NEXT: vfabs.v v12, v8
; CHECK-NEXT: vmflt.vf v12, v16, ft0 ; CHECK-NEXT: vmflt.vf v0, v12, ft0
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: fsrmi a0, 2
; CHECK-NEXT: vfcvt.rtz.x.f.v v16, v8, v0.t ; CHECK-NEXT: vfcvt.x.f.v v12, v8, v0.t
; CHECK-NEXT: lui a0, %hi(.LCPI9_1) ; CHECK-NEXT: fsrm a0
; CHECK-NEXT: flw ft0, %lo(.LCPI9_1)(a0) ; CHECK-NEXT: vfcvt.f.x.v v12, v12, v0.t
; CHECK-NEXT: vfcvt.f.x.v v16, v16, v0.t ; CHECK-NEXT: vfsgnj.vv v8, v12, v8, v0.t
; CHECK-NEXT: vmv1r.v v13, v12
; CHECK-NEXT: vmflt.vv v13, v8, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: vfsub.vf v16, v16, ft0, v0.t
; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vfsgnj.vv v8, v16, v8, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = call <vscale x 8 x float> @llvm.floor.nxv8f32(<vscale x 8 x float> %x) %a = call <vscale x 8 x float> @llvm.floor.nxv8f32(<vscale x 8 x float> %x)
ret <vscale x 8 x float> %a ret <vscale x 8 x float> %a
} }
declare <vscale x 8 x float> @llvm.floor.nxv8f32(<vscale x 8 x float>) declare <vscale x 8 x float> @llvm.floor.nxv8f32(<vscale x 8 x float>)
define <vscale x 16 x float> @floor_nxv16f32(<vscale x 16 x float> %x) { define <vscale x 16 x float> @floor_nxv16f32(<vscale x 16 x float> %x) {
; CHECK-LABEL: floor_nxv16f32: ; CHECK-LABEL: floor_nxv16f32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lui a0, %hi(.LCPI10_0) ; CHECK-NEXT: lui a0, %hi(.LCPI10_0)
; CHECK-NEXT: flw ft0, %lo(.LCPI10_0)(a0) ; CHECK-NEXT: flw ft0, %lo(.LCPI10_0)(a0)
; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, mu
; CHECK-NEXT: vfabs.v v24, v8 ; CHECK-NEXT: vfabs.v v16, v8
; CHECK-NEXT: vmflt.vf v16, v24, ft0 ; CHECK-NEXT: vmflt.vf v0, v16, ft0
; CHECK-NEXT: vmv1r.v v0, v16 ; CHECK-NEXT: fsrmi a0, 2
; CHECK-NEXT: vfcvt.rtz.x.f.v v24, v8, v0.t ; CHECK-NEXT: vfcvt.x.f.v v16, v8, v0.t
; CHECK-NEXT: lui a0, %hi(.LCPI10_1) ; CHECK-NEXT: fsrm a0
; CHECK-NEXT: flw ft0, %lo(.LCPI10_1)(a0) ; CHECK-NEXT: vfcvt.f.x.v v16, v16, v0.t
; CHECK-NEXT: vfcvt.f.x.v v24, v24, v0.t ; CHECK-NEXT: vfsgnj.vv v8, v16, v8, v0.t
; CHECK-NEXT: vmv1r.v v17, v16
; CHECK-NEXT: vmflt.vv v17, v8, v24, v0.t
; CHECK-NEXT: vmv1r.v v0, v17
; CHECK-NEXT: vfsub.vf v24, v24, ft0, v0.t
; CHECK-NEXT: vmv1r.v v0, v16
; CHECK-NEXT: vfsgnj.vv v8, v24, v8, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = call <vscale x 16 x float> @llvm.floor.nxv16f32(<vscale x 16 x float> %x) %a = call <vscale x 16 x float> @llvm.floor.nxv16f32(<vscale x 16 x float> %x)
ret <vscale x 16 x float> %a ret <vscale x 16 x float> %a
} }
declare <vscale x 16 x float> @llvm.floor.nxv16f32(<vscale x 16 x float>) declare <vscale x 16 x float> @llvm.floor.nxv16f32(<vscale x 16 x float>)
define <vscale x 1 x double> @floor_nxv1f64(<vscale x 1 x double> %x) { define <vscale x 1 x double> @floor_nxv1f64(<vscale x 1 x double> %x) {
; CHECK-LABEL: floor_nxv1f64: ; CHECK-LABEL: floor_nxv1f64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lui a0, %hi(.LCPI11_0) ; CHECK-NEXT: lui a0, %hi(.LCPI11_0)
; CHECK-NEXT: fld ft0, %lo(.LCPI11_0)(a0) ; CHECK-NEXT: fld ft0, %lo(.LCPI11_0)(a0)
; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e64, m1, ta, mu
; CHECK-NEXT: vfabs.v v9, v8 ; CHECK-NEXT: vfabs.v v9, v8
; CHECK-NEXT: vmflt.vf v9, v9, ft0 ; CHECK-NEXT: vmflt.vf v0, v9, ft0
; CHECK-NEXT: vmv.v.v v0, v9 ; CHECK-NEXT: fsrmi a0, 2
; CHECK-NEXT: vfcvt.rtz.x.f.v v10, v8, v0.t ; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t
; CHECK-NEXT: lui a0, %hi(.LCPI11_1) ; CHECK-NEXT: fsrm a0
; CHECK-NEXT: fld ft0, %lo(.LCPI11_1)(a0) ; CHECK-NEXT: vfcvt.f.x.v v9, v9, v0.t
; CHECK-NEXT: vfcvt.f.x.v v11, v10, v0.t ; CHECK-NEXT: vfsgnj.vv v8, v9, v8, v0.t
; CHECK-NEXT: vmv.v.v v10, v9
; CHECK-NEXT: vmflt.vv v10, v8, v11, v0.t
; CHECK-NEXT: vmv.v.v v0, v10
; CHECK-NEXT: vfsub.vf v11, v11, ft0, v0.t
; CHECK-NEXT: vmv.v.v v0, v9
; CHECK-NEXT: vfsgnj.vv v8, v11, v8, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = call <vscale x 1 x double> @llvm.floor.nxv1f64(<vscale x 1 x double> %x) %a = call <vscale x 1 x double> @llvm.floor.nxv1f64(<vscale x 1 x double> %x)
ret <vscale x 1 x double> %a ret <vscale x 1 x double> %a
} }
declare <vscale x 1 x double> @llvm.floor.nxv1f64(<vscale x 1 x double>) declare <vscale x 1 x double> @llvm.floor.nxv1f64(<vscale x 1 x double>)
define <vscale x 2 x double> @floor_nxv2f64(<vscale x 2 x double> %x) { define <vscale x 2 x double> @floor_nxv2f64(<vscale x 2 x double> %x) {
; CHECK-LABEL: floor_nxv2f64: ; CHECK-LABEL: floor_nxv2f64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lui a0, %hi(.LCPI12_0) ; CHECK-NEXT: lui a0, %hi(.LCPI12_0)
; CHECK-NEXT: fld ft0, %lo(.LCPI12_0)(a0) ; CHECK-NEXT: fld ft0, %lo(.LCPI12_0)(a0)
; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, mu
; CHECK-NEXT: vfabs.v v12, v8 ; CHECK-NEXT: vfabs.v v10, v8
; CHECK-NEXT: vmflt.vf v10, v12, ft0 ; CHECK-NEXT: vmflt.vf v0, v10, ft0
; CHECK-NEXT: vmv1r.v v0, v10 ; CHECK-NEXT: fsrmi a0, 2
; CHECK-NEXT: vfcvt.rtz.x.f.v v12, v8, v0.t ; CHECK-NEXT: vfcvt.x.f.v v10, v8, v0.t
; CHECK-NEXT: lui a0, %hi(.LCPI12_1) ; CHECK-NEXT: fsrm a0
; CHECK-NEXT: fld ft0, %lo(.LCPI12_1)(a0) ; CHECK-NEXT: vfcvt.f.x.v v10, v10, v0.t
; CHECK-NEXT: vfcvt.f.x.v v12, v12, v0.t ; CHECK-NEXT: vfsgnj.vv v8, v10, v8, v0.t
; CHECK-NEXT: vmv1r.v v11, v10
; CHECK-NEXT: vmflt.vv v11, v8, v12, v0.t
; CHECK-NEXT: vmv1r.v v0, v11
; CHECK-NEXT: vfsub.vf v12, v12, ft0, v0.t
; CHECK-NEXT: vmv1r.v v0, v10
; CHECK-NEXT: vfsgnj.vv v8, v12, v8, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = call <vscale x 2 x double> @llvm.floor.nxv2f64(<vscale x 2 x double> %x) %a = call <vscale x 2 x double> @llvm.floor.nxv2f64(<vscale x 2 x double> %x)
ret <vscale x 2 x double> %a ret <vscale x 2 x double> %a
} }
declare <vscale x 2 x double> @llvm.floor.nxv2f64(<vscale x 2 x double>) declare <vscale x 2 x double> @llvm.floor.nxv2f64(<vscale x 2 x double>)
define <vscale x 4 x double> @floor_nxv4f64(<vscale x 4 x double> %x) { define <vscale x 4 x double> @floor_nxv4f64(<vscale x 4 x double> %x) {
; CHECK-LABEL: floor_nxv4f64: ; CHECK-LABEL: floor_nxv4f64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lui a0, %hi(.LCPI13_0) ; CHECK-NEXT: lui a0, %hi(.LCPI13_0)
; CHECK-NEXT: fld ft0, %lo(.LCPI13_0)(a0) ; CHECK-NEXT: fld ft0, %lo(.LCPI13_0)(a0)
; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, mu
; CHECK-NEXT: vfabs.v v16, v8 ; CHECK-NEXT: vfabs.v v12, v8
; CHECK-NEXT: vmflt.vf v12, v16, ft0 ; CHECK-NEXT: vmflt.vf v0, v12, ft0
; CHECK-NEXT: vmv1r.v v0, v12 ; CHECK-NEXT: fsrmi a0, 2
; CHECK-NEXT: vfcvt.rtz.x.f.v v16, v8, v0.t ; CHECK-NEXT: vfcvt.x.f.v v12, v8, v0.t
; CHECK-NEXT: lui a0, %hi(.LCPI13_1) ; CHECK-NEXT: fsrm a0
; CHECK-NEXT: fld ft0, %lo(.LCPI13_1)(a0) ; CHECK-NEXT: vfcvt.f.x.v v12, v12, v0.t
; CHECK-NEXT: vfcvt.f.x.v v16, v16, v0.t ; CHECK-NEXT: vfsgnj.vv v8, v12, v8, v0.t
; CHECK-NEXT: vmv1r.v v13, v12
; CHECK-NEXT: vmflt.vv v13, v8, v16, v0.t
; CHECK-NEXT: vmv1r.v v0, v13
; CHECK-NEXT: vfsub.vf v16, v16, ft0, v0.t
; CHECK-NEXT: vmv1r.v v0, v12
; CHECK-NEXT: vfsgnj.vv v8, v16, v8, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = call <vscale x 4 x double> @llvm.floor.nxv4f64(<vscale x 4 x double> %x) %a = call <vscale x 4 x double> @llvm.floor.nxv4f64(<vscale x 4 x double> %x)
ret <vscale x 4 x double> %a ret <vscale x 4 x double> %a
} }
declare <vscale x 4 x double> @llvm.floor.nxv4f64(<vscale x 4 x double>) declare <vscale x 4 x double> @llvm.floor.nxv4f64(<vscale x 4 x double>)
define <vscale x 8 x double> @floor_nxv8f64(<vscale x 8 x double> %x) { define <vscale x 8 x double> @floor_nxv8f64(<vscale x 8 x double> %x) {
; CHECK-LABEL: floor_nxv8f64: ; CHECK-LABEL: floor_nxv8f64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: lui a0, %hi(.LCPI14_0) ; CHECK-NEXT: lui a0, %hi(.LCPI14_0)
; CHECK-NEXT: fld ft0, %lo(.LCPI14_0)(a0) ; CHECK-NEXT: fld ft0, %lo(.LCPI14_0)(a0)
; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu ; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, mu
; CHECK-NEXT: vfabs.v v24, v8 ; CHECK-NEXT: vfabs.v v16, v8
; CHECK-NEXT: vmflt.vf v16, v24, ft0 ; CHECK-NEXT: vmflt.vf v0, v16, ft0
; CHECK-NEXT: vmv1r.v v0, v16 ; CHECK-NEXT: fsrmi a0, 2
; CHECK-NEXT: vfcvt.rtz.x.f.v v24, v8, v0.t ; CHECK-NEXT: vfcvt.x.f.v v16, v8, v0.t
; CHECK-NEXT: lui a0, %hi(.LCPI14_1) ; CHECK-NEXT: fsrm a0
; CHECK-NEXT: fld ft0, %lo(.LCPI14_1)(a0) ; CHECK-NEXT: vfcvt.f.x.v v16, v16, v0.t
; CHECK-NEXT: vfcvt.f.x.v v24, v24, v0.t ; CHECK-NEXT: vfsgnj.vv v8, v16, v8, v0.t
; CHECK-NEXT: vmv1r.v v17, v16
; CHECK-NEXT: vmflt.vv v17, v8, v24, v0.t
; CHECK-NEXT: vmv1r.v v0, v17
; CHECK-NEXT: vfsub.vf v24, v24, ft0, v0.t
; CHECK-NEXT: vmv1r.v v0, v16
; CHECK-NEXT: vfsgnj.vv v8, v24, v8, v0.t
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = call <vscale x 8 x double> @llvm.floor.nxv8f64(<vscale x 8 x double> %x) %a = call <vscale x 8 x double> @llvm.floor.nxv8f64(<vscale x 8 x double> %x)
ret <vscale x 8 x double> %a ret <vscale x 8 x double> %a
} }
declare <vscale x 8 x double> @llvm.floor.nxv8f64(<vscale x 8 x double>) declare <vscale x 8 x double> @llvm.floor.nxv8f64(<vscale x 8 x double>)

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-fp.ll

Show First 20 Lines • Show All 2,024 Lines • ▼ Show 20 Lines; CHECK-NEXT: ret
ret void ret void
} }
declare <2 x double> @llvm.trunc.v2f64(<2 x double>) declare <2 x double> @llvm.trunc.v2f64(<2 x double>)
define void @ceil_v8f16(<8 x half>* %x) { define void @ceil_v8f16(<8 x half>* %x) {
; CHECK-LABEL: ceil_v8f16: ; CHECK-LABEL: ceil_v8f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu ; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu
; CHECK-NEXT: vle16.v v10, (a0) ; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: lui a1, %hi(.LCPI94_0) ; CHECK-NEXT: lui a1, %hi(.LCPI94_0)
; CHECK-NEXT: flh ft0, %lo(.LCPI94_0)(a1) ; CHECK-NEXT: flh ft0, %lo(.LCPI94_0)(a1)
; CHECK-NEXT: vfabs.v v8, v10 ; CHECK-NEXT: vfabs.v v9, v8
; CHECK-NEXT: vmflt.vf v8, v8, ft0 ; CHECK-NEXT: vmflt.vf v0, v9, ft0
; CHECK-NEXT: vmv.v.v v0, v8 ; CHECK-NEXT: fsrmi a1, 3
; CHECK-NEXT: vfcvt.rtz.x.f.v v9, v10, v0.t ; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t
; CHECK-NEXT: lui a1, %hi(.LCPI94_1) ; CHECK-NEXT: fsrm a1
; CHECK-NEXT: flh ft0, %lo(.LCPI94_1)(a1) ; CHECK-NEXT: vfcvt.f.x.v v9, v9, v0.t
; CHECK-NEXT: vfcvt.f.x.v v11, v9, v0.t ; CHECK-NEXT: vfsgnj.vv v8, v9, v8, v0.t
; CHECK-NEXT: vmv.v.v v9, v8 ; CHECK-NEXT: vse16.v v8, (a0)
; CHECK-NEXT: vmflt.vv v9, v11, v10, v0.t
; CHECK-NEXT: vmv.v.v v0, v9
; CHECK-NEXT: vfadd.vf v11, v11, ft0, v0.t
; CHECK-NEXT: vmv.v.v v0, v8
; CHECK-NEXT: vfsgnj.vv v10, v11, v10, v0.t
; CHECK-NEXT: vse16.v v10, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = load <8 x half>, <8 x half>* %x %a = load <8 x half>, <8 x half>* %x
%b = call <8 x half> @llvm.ceil.v8f16(<8 x half> %a) %b = call <8 x half> @llvm.ceil.v8f16(<8 x half> %a)
store <8 x half> %b, <8 x half>* %x store <8 x half> %b, <8 x half>* %x
ret void ret void
} }
declare <8 x half> @llvm.ceil.v8f16(<8 x half>) declare <8 x half> @llvm.ceil.v8f16(<8 x half>)
define void @ceil_v4f32(<4 x float>* %x) { define void @ceil_v4f32(<4 x float>* %x) {
; CHECK-LABEL: ceil_v4f32: ; CHECK-LABEL: ceil_v4f32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; CHECK-NEXT: vle32.v v10, (a0) ; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: lui a1, %hi(.LCPI95_0) ; CHECK-NEXT: lui a1, %hi(.LCPI95_0)
; CHECK-NEXT: flw ft0, %lo(.LCPI95_0)(a1) ; CHECK-NEXT: flw ft0, %lo(.LCPI95_0)(a1)
; CHECK-NEXT: vfabs.v v8, v10 ; CHECK-NEXT: vfabs.v v9, v8
; CHECK-NEXT: vmflt.vf v8, v8, ft0 ; CHECK-NEXT: vmflt.vf v0, v9, ft0
; CHECK-NEXT: vmv.v.v v0, v8 ; CHECK-NEXT: fsrmi a1, 3
; CHECK-NEXT: vfcvt.rtz.x.f.v v9, v10, v0.t ; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t
; CHECK-NEXT: lui a1, %hi(.LCPI95_1) ; CHECK-NEXT: fsrm a1
; CHECK-NEXT: flw ft0, %lo(.LCPI95_1)(a1) ; CHECK-NEXT: vfcvt.f.x.v v9, v9, v0.t
; CHECK-NEXT: vfcvt.f.x.v v11, v9, v0.t ; CHECK-NEXT: vfsgnj.vv v8, v9, v8, v0.t
; CHECK-NEXT: vmv.v.v v9, v8 ; CHECK-NEXT: vse32.v v8, (a0)
; CHECK-NEXT: vmflt.vv v9, v11, v10, v0.t
; CHECK-NEXT: vmv.v.v v0, v9
; CHECK-NEXT: vfadd.vf v11, v11, ft0, v0.t
; CHECK-NEXT: vmv.v.v v0, v8
; CHECK-NEXT: vfsgnj.vv v10, v11, v10, v0.t
; CHECK-NEXT: vse32.v v10, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = load <4 x float>, <4 x float>* %x %a = load <4 x float>, <4 x float>* %x
%b = call <4 x float> @llvm.ceil.v4f32(<4 x float> %a) %b = call <4 x float> @llvm.ceil.v4f32(<4 x float> %a)
store <4 x float> %b, <4 x float>* %x store <4 x float> %b, <4 x float>* %x
ret void ret void
} }
declare <4 x float> @llvm.ceil.v4f32(<4 x float>) declare <4 x float> @llvm.ceil.v4f32(<4 x float>)
define void @ceil_v2f64(<2 x double>* %x) { define void @ceil_v2f64(<2 x double>* %x) {
; CHECK-LABEL: ceil_v2f64: ; CHECK-LABEL: ceil_v2f64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu ; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; CHECK-NEXT: vle64.v v10, (a0) ; CHECK-NEXT: vle64.v v8, (a0)
; CHECK-NEXT: lui a1, %hi(.LCPI96_0) ; CHECK-NEXT: lui a1, %hi(.LCPI96_0)
; CHECK-NEXT: fld ft0, %lo(.LCPI96_0)(a1) ; CHECK-NEXT: fld ft0, %lo(.LCPI96_0)(a1)
; CHECK-NEXT: vfabs.v v8, v10 ; CHECK-NEXT: vfabs.v v9, v8
; CHECK-NEXT: vmflt.vf v8, v8, ft0 ; CHECK-NEXT: vmflt.vf v0, v9, ft0
; CHECK-NEXT: vmv.v.v v0, v8 ; CHECK-NEXT: fsrmi a1, 3
; CHECK-NEXT: vfcvt.rtz.x.f.v v9, v10, v0.t ; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t
; CHECK-NEXT: lui a1, %hi(.LCPI96_1) ; CHECK-NEXT: fsrm a1
; CHECK-NEXT: fld ft0, %lo(.LCPI96_1)(a1) ; CHECK-NEXT: vfcvt.f.x.v v9, v9, v0.t
; CHECK-NEXT: vfcvt.f.x.v v11, v9, v0.t ; CHECK-NEXT: vfsgnj.vv v8, v9, v8, v0.t
; CHECK-NEXT: vmv.v.v v9, v8 ; CHECK-NEXT: vse64.v v8, (a0)
; CHECK-NEXT: vmflt.vv v9, v11, v10, v0.t
; CHECK-NEXT: vmv.v.v v0, v9
; CHECK-NEXT: vfadd.vf v11, v11, ft0, v0.t
; CHECK-NEXT: vmv.v.v v0, v8
; CHECK-NEXT: vfsgnj.vv v10, v11, v10, v0.t
; CHECK-NEXT: vse64.v v10, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = load <2 x double>, <2 x double>* %x %a = load <2 x double>, <2 x double>* %x
%b = call <2 x double> @llvm.ceil.v2f64(<2 x double> %a) %b = call <2 x double> @llvm.ceil.v2f64(<2 x double> %a)
store <2 x double> %b, <2 x double>* %x store <2 x double> %b, <2 x double>* %x
ret void ret void
} }
declare <2 x double> @llvm.ceil.v2f64(<2 x double>) declare <2 x double> @llvm.ceil.v2f64(<2 x double>)
define void @floor_v8f16(<8 x half>* %x) { define void @floor_v8f16(<8 x half>* %x) {
; CHECK-LABEL: floor_v8f16: ; CHECK-LABEL: floor_v8f16:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu ; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, mu
; CHECK-NEXT: vle16.v v10, (a0) ; CHECK-NEXT: vle16.v v8, (a0)
; CHECK-NEXT: lui a1, %hi(.LCPI97_0) ; CHECK-NEXT: lui a1, %hi(.LCPI97_0)
; CHECK-NEXT: flh ft0, %lo(.LCPI97_0)(a1) ; CHECK-NEXT: flh ft0, %lo(.LCPI97_0)(a1)
; CHECK-NEXT: vfabs.v v8, v10 ; CHECK-NEXT: vfabs.v v9, v8
; CHECK-NEXT: vmflt.vf v8, v8, ft0 ; CHECK-NEXT: vmflt.vf v0, v9, ft0
; CHECK-NEXT: vmv.v.v v0, v8 ; CHECK-NEXT: fsrmi a1, 2
; CHECK-NEXT: vfcvt.rtz.x.f.v v9, v10, v0.t ; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t
; CHECK-NEXT: lui a1, %hi(.LCPI97_1) ; CHECK-NEXT: fsrm a1
; CHECK-NEXT: flh ft0, %lo(.LCPI97_1)(a1) ; CHECK-NEXT: vfcvt.f.x.v v9, v9, v0.t
; CHECK-NEXT: vfcvt.f.x.v v11, v9, v0.t ; CHECK-NEXT: vfsgnj.vv v8, v9, v8, v0.t
; CHECK-NEXT: vmv.v.v v9, v8 ; CHECK-NEXT: vse16.v v8, (a0)
; CHECK-NEXT: vmflt.vv v9, v10, v11, v0.t
; CHECK-NEXT: vmv.v.v v0, v9
; CHECK-NEXT: vfsub.vf v11, v11, ft0, v0.t
; CHECK-NEXT: vmv.v.v v0, v8
; CHECK-NEXT: vfsgnj.vv v10, v11, v10, v0.t
; CHECK-NEXT: vse16.v v10, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = load <8 x half>, <8 x half>* %x %a = load <8 x half>, <8 x half>* %x
%b = call <8 x half> @llvm.floor.v8f16(<8 x half> %a) %b = call <8 x half> @llvm.floor.v8f16(<8 x half> %a)
store <8 x half> %b, <8 x half>* %x store <8 x half> %b, <8 x half>* %x
ret void ret void
} }
declare <8 x half> @llvm.floor.v8f16(<8 x half>) declare <8 x half> @llvm.floor.v8f16(<8 x half>)
define void @floor_v4f32(<4 x float>* %x) { define void @floor_v4f32(<4 x float>* %x) {
; CHECK-LABEL: floor_v4f32: ; CHECK-LABEL: floor_v4f32:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu ; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, mu
; CHECK-NEXT: vle32.v v10, (a0) ; CHECK-NEXT: vle32.v v8, (a0)
; CHECK-NEXT: lui a1, %hi(.LCPI98_0) ; CHECK-NEXT: lui a1, %hi(.LCPI98_0)
; CHECK-NEXT: flw ft0, %lo(.LCPI98_0)(a1) ; CHECK-NEXT: flw ft0, %lo(.LCPI98_0)(a1)
; CHECK-NEXT: vfabs.v v8, v10 ; CHECK-NEXT: vfabs.v v9, v8
; CHECK-NEXT: vmflt.vf v8, v8, ft0 ; CHECK-NEXT: vmflt.vf v0, v9, ft0
; CHECK-NEXT: vmv.v.v v0, v8 ; CHECK-NEXT: fsrmi a1, 2
; CHECK-NEXT: vfcvt.rtz.x.f.v v9, v10, v0.t ; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t
; CHECK-NEXT: lui a1, %hi(.LCPI98_1) ; CHECK-NEXT: fsrm a1
; CHECK-NEXT: flw ft0, %lo(.LCPI98_1)(a1) ; CHECK-NEXT: vfcvt.f.x.v v9, v9, v0.t
; CHECK-NEXT: vfcvt.f.x.v v11, v9, v0.t ; CHECK-NEXT: vfsgnj.vv v8, v9, v8, v0.t
; CHECK-NEXT: vmv.v.v v9, v8 ; CHECK-NEXT: vse32.v v8, (a0)
; CHECK-NEXT: vmflt.vv v9, v10, v11, v0.t
; CHECK-NEXT: vmv.v.v v0, v9
; CHECK-NEXT: vfsub.vf v11, v11, ft0, v0.t
; CHECK-NEXT: vmv.v.v v0, v8
; CHECK-NEXT: vfsgnj.vv v10, v11, v10, v0.t
; CHECK-NEXT: vse32.v v10, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = load <4 x float>, <4 x float>* %x %a = load <4 x float>, <4 x float>* %x
%b = call <4 x float> @llvm.floor.v4f32(<4 x float> %a) %b = call <4 x float> @llvm.floor.v4f32(<4 x float> %a)
store <4 x float> %b, <4 x float>* %x store <4 x float> %b, <4 x float>* %x
ret void ret void
} }
declare <4 x float> @llvm.floor.v4f32(<4 x float>) declare <4 x float> @llvm.floor.v4f32(<4 x float>)
define void @floor_v2f64(<2 x double>* %x) { define void @floor_v2f64(<2 x double>* %x) {
; CHECK-LABEL: floor_v2f64: ; CHECK-LABEL: floor_v2f64:
; CHECK: # %bb.0: ; CHECK: # %bb.0:
; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu ; CHECK-NEXT: vsetivli zero, 2, e64, m1, ta, mu
; CHECK-NEXT: vle64.v v10, (a0) ; CHECK-NEXT: vle64.v v8, (a0)
; CHECK-NEXT: lui a1, %hi(.LCPI99_0) ; CHECK-NEXT: lui a1, %hi(.LCPI99_0)
; CHECK-NEXT: fld ft0, %lo(.LCPI99_0)(a1) ; CHECK-NEXT: fld ft0, %lo(.LCPI99_0)(a1)
; CHECK-NEXT: vfabs.v v8, v10 ; CHECK-NEXT: vfabs.v v9, v8
; CHECK-NEXT: vmflt.vf v8, v8, ft0 ; CHECK-NEXT: vmflt.vf v0, v9, ft0
; CHECK-NEXT: vmv.v.v v0, v8 ; CHECK-NEXT: fsrmi a1, 2
; CHECK-NEXT: vfcvt.rtz.x.f.v v9, v10, v0.t ; CHECK-NEXT: vfcvt.x.f.v v9, v8, v0.t
; CHECK-NEXT: lui a1, %hi(.LCPI99_1) ; CHECK-NEXT: fsrm a1
; CHECK-NEXT: fld ft0, %lo(.LCPI99_1)(a1) ; CHECK-NEXT: vfcvt.f.x.v v9, v9, v0.t
; CHECK-NEXT: vfcvt.f.x.v v11, v9, v0.t ; CHECK-NEXT: vfsgnj.vv v8, v9, v8, v0.t
; CHECK-NEXT: vmv.v.v v9, v8 ; CHECK-NEXT: vse64.v v8, (a0)
; CHECK-NEXT: vmflt.vv v9, v10, v11, v0.t
; CHECK-NEXT: vmv.v.v v0, v9
; CHECK-NEXT: vfsub.vf v11, v11, ft0, v0.t
; CHECK-NEXT: vmv.v.v v0, v8
; CHECK-NEXT: vfsgnj.vv v10, v11, v10, v0.t
; CHECK-NEXT: vse64.v v10, (a0)
; CHECK-NEXT: ret ; CHECK-NEXT: ret
%a = load <2 x double>, <2 x double>* %x %a = load <2 x double>, <2 x double>* %x
%b = call <2 x double> @llvm.floor.v2f64(<2 x double> %a) %b = call <2 x double> @llvm.floor.v2f64(<2 x double> %a)
store <2 x double> %b, <2 x double>* %x store <2 x double> %b, <2 x double>* %x
ret void ret void
} }
declare <2 x double> @llvm.floor.v2f64(<2 x double>) declare <2 x double> @llvm.floor.v2f64(<2 x double>)
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