[RegisterInfoEmitter] Generate isConstantPhysReg(). NFCI

[arichardson]

Summary

This commit moves the information on whether a register is constant into
the Tablegen files to allow generating the implementaiton of
isConstantPhysReg(). I've marked isConstantPhysReg() as final in this
generated file to ensure that changes are made to tablegen instead of
overriding this function, but if that turns out to be too restrictive,
we can remove the qualifier.

This should be pretty much NFC, but I did notice that e.g. the AMDGPU
generated file also includes the LO16/HI16 registers now.

The new isConstant flag will also be used by D131958 to ensure that
constant registers are marked as call-preserved.

[arichardson]

fix indentation

[arichardson]

Include the tablegen changes here

[arichardson]

The generated functions look as follows and mostly match the existing ones (a few extra subregs for AMDGPU and added PPC registers).

cmake-build-debug/lib/Target/AArch64/AArch64GenRegisterInfo.inc:isConstantPhysReg(MCRegister PhysReg) const {
cmake-build-debug/lib/Target/AArch64/AArch64GenRegisterInfo.inc-  return
cmake-build-debug/lib/Target/AArch64/AArch64GenRegisterInfo.inc-      PhysReg == AArch64::WZR ||
cmake-build-debug/lib/Target/AArch64/AArch64GenRegisterInfo.inc-      PhysReg == AArch64::XZR ||
cmake-build-debug/lib/Target/AArch64/AArch64GenRegisterInfo.inc-      false;
cmake-build-debug/lib/Target/AArch64/AArch64GenRegisterInfo.inc-}
--
cmake-build-debug/lib/Target/AMDGPU/AMDGPUGenRegisterInfo.inc:isConstantPhysReg(MCRegister PhysReg) const {
cmake-build-debug/lib/Target/AMDGPU/AMDGPUGenRegisterInfo.inc-  return
cmake-build-debug/lib/Target/AMDGPU/AMDGPUGenRegisterInfo.inc-      PhysReg == AMDGPU::SGPR_NULL ||
cmake-build-debug/lib/Target/AMDGPU/AMDGPUGenRegisterInfo.inc-      PhysReg == AMDGPU::SGPR_NULL_HI ||
cmake-build-debug/lib/Target/AMDGPU/AMDGPUGenRegisterInfo.inc-      PhysReg == AMDGPU::SRC_POPS_EXITING_WAVE_ID ||
cmake-build-debug/lib/Target/AMDGPU/AMDGPUGenRegisterInfo.inc-      PhysReg == AMDGPU::SRC_PRIVATE_BASE ||
cmake-build-debug/lib/Target/AMDGPU/AMDGPUGenRegisterInfo.inc-      PhysReg == AMDGPU::SRC_PRIVATE_LIMIT ||
cmake-build-debug/lib/Target/AMDGPU/AMDGPUGenRegisterInfo.inc-      PhysReg == AMDGPU::SRC_SHARED_BASE ||
cmake-build-debug/lib/Target/AMDGPU/AMDGPUGenRegisterInfo.inc-      PhysReg == AMDGPU::SRC_SHARED_LIMIT ||
cmake-build-debug/lib/Target/AMDGPU/AMDGPUGenRegisterInfo.inc-      PhysReg == AMDGPU::SGPR_NULL64 ||
cmake-build-debug/lib/Target/AMDGPU/AMDGPUGenRegisterInfo.inc-      PhysReg == AMDGPU::SGPR_NULL_HI16 ||
cmake-build-debug/lib/Target/AMDGPU/AMDGPUGenRegisterInfo.inc-      PhysReg == AMDGPU::SGPR_NULL_HI_HI16 ||
cmake-build-debug/lib/Target/AMDGPU/AMDGPUGenRegisterInfo.inc-      PhysReg == AMDGPU::SGPR_NULL_HI_LO16 ||
cmake-build-debug/lib/Target/AMDGPU/AMDGPUGenRegisterInfo.inc-      PhysReg == AMDGPU::SGPR_NULL_LO16 ||
cmake-build-debug/lib/Target/AMDGPU/AMDGPUGenRegisterInfo.inc-      PhysReg == AMDGPU::SRC_POPS_EXITING_WAVE_ID_HI16 ||
cmake-build-debug/lib/Target/AMDGPU/AMDGPUGenRegisterInfo.inc-      PhysReg == AMDGPU::SRC_POPS_EXITING_WAVE_ID_LO16 ||
cmake-build-debug/lib/Target/AMDGPU/AMDGPUGenRegisterInfo.inc-      PhysReg == AMDGPU::SRC_PRIVATE_BASE_HI16 ||
cmake-build-debug/lib/Target/AMDGPU/AMDGPUGenRegisterInfo.inc-      PhysReg == AMDGPU::SRC_PRIVATE_BASE_LO16 ||
cmake-build-debug/lib/Target/AMDGPU/AMDGPUGenRegisterInfo.inc-      PhysReg == AMDGPU::SRC_PRIVATE_LIMIT_HI16 ||
cmake-build-debug/lib/Target/AMDGPU/AMDGPUGenRegisterInfo.inc-      PhysReg == AMDGPU::SRC_PRIVATE_LIMIT_LO16 ||
cmake-build-debug/lib/Target/AMDGPU/AMDGPUGenRegisterInfo.inc-      PhysReg == AMDGPU::SRC_SHARED_BASE_HI16 ||
cmake-build-debug/lib/Target/AMDGPU/AMDGPUGenRegisterInfo.inc-      PhysReg == AMDGPU::SRC_SHARED_BASE_LO16 ||
cmake-build-debug/lib/Target/AMDGPU/AMDGPUGenRegisterInfo.inc-      PhysReg == AMDGPU::SRC_SHARED_LIMIT_HI16 ||
cmake-build-debug/lib/Target/AMDGPU/AMDGPUGenRegisterInfo.inc-      PhysReg == AMDGPU::SRC_SHARED_LIMIT_LO16 ||
cmake-build-debug/lib/Target/AMDGPU/AMDGPUGenRegisterInfo.inc-      false;
cmake-build-debug/lib/Target/AMDGPU/AMDGPUGenRegisterInfo.inc-}
--
cmake-build-debug/lib/Target/AMDGPU/R600GenRegisterInfo.inc:isConstantPhysReg(MCRegister PhysReg) const {
cmake-build-debug/lib/Target/AMDGPU/R600GenRegisterInfo.inc-  return
cmake-build-debug/lib/Target/AMDGPU/R600GenRegisterInfo.inc-      false;
cmake-build-debug/lib/Target/AMDGPU/R600GenRegisterInfo.inc-}
--
cmake-build-debug/lib/Target/ARM/ARMGenRegisterInfo.inc:isConstantPhysReg(MCRegister PhysReg) const {
cmake-build-debug/lib/Target/ARM/ARMGenRegisterInfo.inc-  return
cmake-build-debug/lib/Target/ARM/ARMGenRegisterInfo.inc-      false;
cmake-build-debug/lib/Target/ARM/ARMGenRegisterInfo.inc-}
--
cmake-build-debug/lib/Target/AVR/AVRGenRegisterInfo.inc:isConstantPhysReg(MCRegister PhysReg) const {
cmake-build-debug/lib/Target/AVR/AVRGenRegisterInfo.inc-  return
cmake-build-debug/lib/Target/AVR/AVRGenRegisterInfo.inc-      false;
cmake-build-debug/lib/Target/AVR/AVRGenRegisterInfo.inc-}
--
cmake-build-debug/lib/Target/BPF/BPFGenRegisterInfo.inc:isConstantPhysReg(MCRegister PhysReg) const {
cmake-build-debug/lib/Target/BPF/BPFGenRegisterInfo.inc-  return
cmake-build-debug/lib/Target/BPF/BPFGenRegisterInfo.inc-      false;
cmake-build-debug/lib/Target/BPF/BPFGenRegisterInfo.inc-}
--
cmake-build-debug/lib/Target/Hexagon/HexagonGenRegisterInfo.inc:isConstantPhysReg(MCRegister PhysReg) const {
cmake-build-debug/lib/Target/Hexagon/HexagonGenRegisterInfo.inc-  return
cmake-build-debug/lib/Target/Hexagon/HexagonGenRegisterInfo.inc-      false;
cmake-build-debug/lib/Target/Hexagon/HexagonGenRegisterInfo.inc-}
--
cmake-build-debug/lib/Target/Lanai/LanaiGenRegisterInfo.inc:isConstantPhysReg(MCRegister PhysReg) const {
cmake-build-debug/lib/Target/Lanai/LanaiGenRegisterInfo.inc-  return
cmake-build-debug/lib/Target/Lanai/LanaiGenRegisterInfo.inc-      false;
cmake-build-debug/lib/Target/Lanai/LanaiGenRegisterInfo.inc-}
--
cmake-build-debug/lib/Target/Mips/MipsGenRegisterInfo.inc:isConstantPhysReg(MCRegister PhysReg) const {
cmake-build-debug/lib/Target/Mips/MipsGenRegisterInfo.inc-  return
cmake-build-debug/lib/Target/Mips/MipsGenRegisterInfo.inc-      PhysReg == Mips::ZERO ||
cmake-build-debug/lib/Target/Mips/MipsGenRegisterInfo.inc-      PhysReg == Mips::ZERO_64 ||
cmake-build-debug/lib/Target/Mips/MipsGenRegisterInfo.inc-      false;
cmake-build-debug/lib/Target/Mips/MipsGenRegisterInfo.inc-}
--
cmake-build-debug/lib/Target/MSP430/MSP430GenRegisterInfo.inc:isConstantPhysReg(MCRegister PhysReg) const {
cmake-build-debug/lib/Target/MSP430/MSP430GenRegisterInfo.inc-  return
cmake-build-debug/lib/Target/MSP430/MSP430GenRegisterInfo.inc-      false;
cmake-build-debug/lib/Target/MSP430/MSP430GenRegisterInfo.inc-}
--
cmake-build-debug/lib/Target/NVPTX/NVPTXGenRegisterInfo.inc:isConstantPhysReg(MCRegister PhysReg) const {
cmake-build-debug/lib/Target/NVPTX/NVPTXGenRegisterInfo.inc-  return
cmake-build-debug/lib/Target/NVPTX/NVPTXGenRegisterInfo.inc-      false;
cmake-build-debug/lib/Target/NVPTX/NVPTXGenRegisterInfo.inc-}
--
cmake-build-debug/lib/Target/PowerPC/PPCGenRegisterInfo.inc:isConstantPhysReg(MCRegister PhysReg) const {
cmake-build-debug/lib/Target/PowerPC/PPCGenRegisterInfo.inc-  return
cmake-build-debug/lib/Target/PowerPC/PPCGenRegisterInfo.inc-      PhysReg == PPC::ZERO ||
cmake-build-debug/lib/Target/PowerPC/PPCGenRegisterInfo.inc-      PhysReg == PPC::ZERO8 ||
cmake-build-debug/lib/Target/PowerPC/PPCGenRegisterInfo.inc-      false;
cmake-build-debug/lib/Target/PowerPC/PPCGenRegisterInfo.inc-}
--
cmake-build-debug/lib/Target/RISCV/RISCVGenRegisterInfo.inc:isConstantPhysReg(MCRegister PhysReg) const {
cmake-build-debug/lib/Target/RISCV/RISCVGenRegisterInfo.inc-  return
cmake-build-debug/lib/Target/RISCV/RISCVGenRegisterInfo.inc-      PhysReg == RISCV::VLENB ||
cmake-build-debug/lib/Target/RISCV/RISCVGenRegisterInfo.inc-      PhysReg == RISCV::X0 ||
cmake-build-debug/lib/Target/RISCV/RISCVGenRegisterInfo.inc-      false;
cmake-build-debug/lib/Target/RISCV/RISCVGenRegisterInfo.inc-}
--
cmake-build-debug/lib/Target/Sparc/SparcGenRegisterInfo.inc:isConstantPhysReg(MCRegister PhysReg) const {
cmake-build-debug/lib/Target/Sparc/SparcGenRegisterInfo.inc-  return
cmake-build-debug/lib/Target/Sparc/SparcGenRegisterInfo.inc-      false;
cmake-build-debug/lib/Target/Sparc/SparcGenRegisterInfo.inc-}
--
cmake-build-debug/lib/Target/SystemZ/SystemZGenRegisterInfo.inc:isConstantPhysReg(MCRegister PhysReg) const {
cmake-build-debug/lib/Target/SystemZ/SystemZGenRegisterInfo.inc-  return
cmake-build-debug/lib/Target/SystemZ/SystemZGenRegisterInfo.inc-      false;
cmake-build-debug/lib/Target/SystemZ/SystemZGenRegisterInfo.inc-}
--
cmake-build-debug/lib/Target/VE/VEGenRegisterInfo.inc:isConstantPhysReg(MCRegister PhysReg) const {
cmake-build-debug/lib/Target/VE/VEGenRegisterInfo.inc-  return
cmake-build-debug/lib/Target/VE/VEGenRegisterInfo.inc-      PhysReg == VE::VM0 ||
cmake-build-debug/lib/Target/VE/VEGenRegisterInfo.inc-      PhysReg == VE::VMP0 ||
cmake-build-debug/lib/Target/VE/VEGenRegisterInfo.inc-      false;
cmake-build-debug/lib/Target/VE/VEGenRegisterInfo.inc-}
--
cmake-build-debug/lib/Target/WebAssembly/WebAssemblyGenRegisterInfo.inc:isConstantPhysReg(MCRegister PhysReg) const {
cmake-build-debug/lib/Target/WebAssembly/WebAssemblyGenRegisterInfo.inc-  return
cmake-build-debug/lib/Target/WebAssembly/WebAssemblyGenRegisterInfo.inc-      false;
cmake-build-debug/lib/Target/WebAssembly/WebAssemblyGenRegisterInfo.inc-}
--
cmake-build-debug/lib/Target/X86/X86GenRegisterInfo.inc:isConstantPhysReg(MCRegister PhysReg) const {
cmake-build-debug/lib/Target/X86/X86GenRegisterInfo.inc-  return
cmake-build-debug/lib/Target/X86/X86GenRegisterInfo.inc-      false;
cmake-build-debug/lib/Target/X86/X86GenRegisterInfo.inc-}
--
cmake-build-debug/lib/Target/XCore/XCoreGenRegisterInfo.inc:isConstantPhysReg(MCRegister PhysReg) const {
cmake-build-debug/lib/Target/XCore/XCoreGenRegisterInfo.inc-  return
cmake-build-debug/lib/Target/XCore/XCoreGenRegisterInfo.inc-      false;
cmake-build-debug/lib/Target/XCore/XCoreGenRegisterInfo.inc-}

[jrtc27]

llvm/lib/Target/AMDGPU/SIRegisterInfo.td

146

Not used any more

224–225

This wasn't constant before

241

This wasn't constant before

llvm/lib/Target/Mips/MipsRegisterInfo.td

88

let ... in gets used for SubRegIndices later

[arichardson]

improve tablegen style

[arichardson]

SRC_POPS_EXITING_WAVE_ID should not be constant

[arichardson]

llvm/lib/Target/AMDGPU/SIRegisterInfo.td

224–225

That's true, but since it's a subreg if SGPR_NULL64 I assumed it must be.

241

fixed.

[asb]

This LGTM from a RISC-V perspective and makes a lot of sense to generate from from TableGen rather than hand-coding.

I think it would be worth getting an LGTM from the AMDGPU side before landing.

[nemanjai]

LGTM for PPC.

[Carrot]

%g0 on SPARC is also a constant register.
https://docs.oracle.com/cd/E26502_01/html/E28387/gentextid-2715.html

[foad]

LGTM for AMDGPU.

llvm/lib/Target/AMDGPU/SIRegisterInfo.td

231

Please don't remove the blank line :)

[arichardson]

In D131962#3735681, @Carrot wrote:

%g0 on SPARC is also a constant register.
https://docs.oracle.com/cd/E26502_01/html/E28387/gentextid-2715.html

Done in https://reviews.llvm.org/D132561

llvm/include/llvm/Target/Target.td

class Register<string n, list<string> altNames = []> {
   // x86 register AX is covered by its sub-registers AL and AH, but EAX is not
   // covered by its sub-register AX.
   bit CoveredBySubRegs = false;
 
   // HWEncoding - The target specific hardware encoding for this register.
   bits<16> HWEncoding = 0;
 
   bit isArtificial = false;
+
+  // isConstant - This register always holds a constant value (e.g. the zero
+  // register in architectures such as MIPS)
+  bit isConstant = false;
 }
 
 // RegisterWithSubRegs - This can be used to define instances of Register which
 // need to specify sub-registers.
 // List "subregs" specifies which registers are sub-registers to this one. This
 // is used to populate the SubRegs and AliasSet fields of TargetRegisterDesc.
 // This allows the code generator to be careful not to put two values with
 // overlapping live ranges into registers which alias.

llvm/lib/Target/AArch64/AArch64RegisterInfo.h

const uint32_t *getThisReturnPreservedMask(const MachineFunction &MF,
                                              CallingConv::ID) const;
 
   /// Stack probing calls preserve different CSRs to the normal CC.
   const uint32_t *getWindowsStackProbePreservedMask() const;
 
   BitVector getReservedRegs(const MachineFunction &MF) const override;
   bool isAsmClobberable(const MachineFunction &MF,
                        MCRegister PhysReg) const override;
-  bool isConstantPhysReg(MCRegister PhysReg) const override;
   const TargetRegisterClass *
   getPointerRegClass(const MachineFunction &MF,
                      unsigned Kind = 0) const override;
   const TargetRegisterClass *
   getCrossCopyRegClass(const TargetRegisterClass *RC) const override;
 
   bool requiresRegisterScavenging(const MachineFunction &MF) const override;
   bool useFPForScavengingIndex(const MachineFunction &MF) const override;

llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp

F.getContext().diagnose(DiagnosticInfoUnsupported{F, ("AArch64 doesn't support"
     " function calls if any of the argument registers is reserved.")});
 }
 
 bool AArch64RegisterInfo::isAsmClobberable(const MachineFunction &MF,
                                           MCRegister PhysReg) const {
   return !isReservedReg(MF, PhysReg);
 }
 
-bool AArch64RegisterInfo::isConstantPhysReg(MCRegister PhysReg) const {
-  return PhysReg == AArch64::WZR || PhysReg == AArch64::XZR;
-}
-
 const TargetRegisterClass *
 AArch64RegisterInfo::getPointerRegClass(const MachineFunction &MF,
                                       unsigned Kind) const {
   return &AArch64::GPR64spRegClass;
 }
 
 const TargetRegisterClass *
 AArch64RegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const {

llvm/lib/Target/AArch64/AArch64RegisterInfo.td

 def W24   : AArch64Reg<24, "w24">, DwarfRegNum<[24]>;
 def W25   : AArch64Reg<25, "w25">, DwarfRegNum<[25]>;
 def W26   : AArch64Reg<26, "w26">, DwarfRegNum<[26]>;
 def W27   : AArch64Reg<27, "w27">, DwarfRegNum<[27]>;
 def W28   : AArch64Reg<28, "w28">, DwarfRegNum<[28]>;
 def W29   : AArch64Reg<29, "w29">, DwarfRegNum<[29]>;
 def W30   : AArch64Reg<30, "w30">, DwarfRegNum<[30]>;
 def WSP   : AArch64Reg<31, "wsp">, DwarfRegNum<[31]>;
+let isConstant = true in
 def WZR   : AArch64Reg<31, "wzr">, DwarfRegAlias<WSP>;
 
 let SubRegIndices = [sub_32] in {
 def X0    : AArch64Reg<0,   "x0",  [W0]>, DwarfRegAlias<W0>;
 def X1    : AArch64Reg<1,   "x1",  [W1]>, DwarfRegAlias<W1>;
 def X2    : AArch64Reg<2,   "x2",  [W2]>, DwarfRegAlias<W2>;
 def X3    : AArch64Reg<3,   "x3",  [W3]>, DwarfRegAlias<W3>;
 def X4    : AArch64Reg<4,   "x4",  [W4]>, DwarfRegAlias<W4>;

 def X24   : AArch64Reg<24, "x24", [W24]>, DwarfRegAlias<W24>;
 def X25   : AArch64Reg<25, "x25", [W25]>, DwarfRegAlias<W25>;
 def X26   : AArch64Reg<26, "x26", [W26]>, DwarfRegAlias<W26>;
 def X27   : AArch64Reg<27, "x27", [W27]>, DwarfRegAlias<W27>;
 def X28   : AArch64Reg<28, "x28", [W28]>, DwarfRegAlias<W28>;
 def FP    : AArch64Reg<29, "x29", [W29]>, DwarfRegAlias<W29>;
 def LR    : AArch64Reg<30, "x30", [W30]>, DwarfRegAlias<W30>;
 def SP    : AArch64Reg<31, "sp",  [WSP]>, DwarfRegAlias<WSP>;
+let isConstant = true in
 def XZR   : AArch64Reg<31, "xzr", [WZR]>, DwarfRegAlias<WSP>;
 }
 
 // Condition code register.
 def NZCV  : AArch64Reg<0, "nzcv">;
 
 // First fault status register
 def FFR : AArch64Reg<0, "ffr">, DwarfRegNum<[47]>;

llvm/lib/Target/AMDGPU/SIRegisterInfo.h

public:
   const TargetRegisterClass *getRegClassForReg(const MachineRegisterInfo &MRI,
                                                Register Reg) const;
   bool isVGPR(const MachineRegisterInfo &MRI, Register Reg) const;
   bool isAGPR(const MachineRegisterInfo &MRI, Register Reg) const;
   bool isVectorRegister(const MachineRegisterInfo &MRI, Register Reg) const {
     return isVGPR(MRI, Reg) || isAGPR(MRI, Reg);
   }
 
-  bool isConstantPhysReg(MCRegister PhysReg) const override;
-
   bool isDivergentRegClass(const TargetRegisterClass *RC) const override {
     return !isSGPRClass(RC);
   }
 
   ArrayRef<int16_t> getRegSplitParts(const TargetRegisterClass *RC,
                                      unsigned EltSize) const;
 
   bool shouldCoalesce(MachineInstr *MI,

llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp

SIRegisterInfo::getProperlyAlignedRC(const TargetRegisterClass *RC) const {
   if (isAGPRClass(RC))
     return getAlignedAGPRClassForBitWidth(Size);
   if (isVectorSuperClass(RC))
     return getAlignedVectorSuperClassForBitWidth(Size);
 
   return RC;
 }
 
-bool SIRegisterInfo::isConstantPhysReg(MCRegister PhysReg) const {
-  switch (PhysReg) {
-  case AMDGPU::SGPR_NULL:
-  case AMDGPU::SGPR_NULL64:
-  case AMDGPU::SRC_SHARED_BASE:
-  case AMDGPU::SRC_PRIVATE_BASE:
-  case AMDGPU::SRC_SHARED_LIMIT:
-  case AMDGPU::SRC_PRIVATE_LIMIT:
-    return true;
-  default:
-    return false;
-  }
-}
-
 ArrayRef<MCPhysReg>
 SIRegisterInfo::getAllSGPR128(const MachineFunction &MF) const {
   return makeArrayRef(AMDGPU::SGPR_128RegClass.begin(),
                       ST.getMaxNumSGPRs(MF) / 4);
 }
 
 ArrayRef<MCPhysReg>
 SIRegisterInfo::getAllSGPR64(const MachineFunction &MF) const {
   return makeArrayRef(AMDGPU::SGPR_64RegClass.begin(),
                       ST.getMaxNumSGPRs(MF) / 2);
 }
 
 ArrayRef<MCPhysReg>
 SIRegisterInfo::getAllSGPR32(const MachineFunction &MF) const {
   return makeArrayRef(AMDGPU::SGPR_32RegClass.begin(), ST.getMaxNumSGPRs(MF));
 }

llvm/lib/Target/AMDGPU/SIRegisterInfo.td

class SIRegisterClass <string n, list<ValueType> rTypes, int Align, dag rList>
 
   // These need to be kept in sync with the enum SIRCFlags.
   let TSFlags{0} = HasVGPR;
   let TSFlags{1} = HasAGPR;
   let TSFlags{2} = HasSGPR;
 }
 
 multiclass SIRegLoHi16 <string n, bits<16> regIdx, bit ArtificialHigh = 1,
                         bit HWEncodingHigh = 0> {
   // There is no special encoding for 16 bit subregs, these are not real
   // registers but rather operands for instructions preserving other 16 bits
   // of the result or reading just 16 bits of a 32 bit VGPR.
   // It is encoded as a corresponding 32 bit register.
   // Non-VGPR register classes use it as we need to have matching subregisters
   // to move instructions and data between ALUs.
   def _LO16 : SIReg<n#".l", regIdx> {
     let HWEncoding{8} = HWEncodingHigh;

 // Encoding changes between subtarget generations.
 // See also Utils/AMDGPUBaseInfo.cpp MAP_REG2REG.
 defm M0_gfxpre11 : SIRegLoHi16 <"m0", 124>;
 defm M0_gfx11plus : SIRegLoHi16 <"m0", 125>;
 defm M0 : SIRegLoHi16 <"m0", 0>;
 
 defm SGPR_NULL_gfxpre11 : SIRegLoHi16 <"null", 125>;
 defm SGPR_NULL_gfx11plus : SIRegLoHi16 <"null", 124>;
+let isConstant = true in {
 defm SGPR_NULL : SIRegLoHi16 <"null", 0>;
 defm SGPR_NULL_HI : SIRegLoHi16 <"", 0>;
+} // isConstant = true
 
 def SGPR_NULL64 :
     RegisterWithSubRegs<"null", [SGPR_NULL, SGPR_NULL_HI]> {
   let Namespace = "AMDGPU";
   let SubRegIndices = [sub0, sub1];
   let HWEncoding = SGPR_NULL.HWEncoding;
+  let isConstant = true;
 }
 
+let isConstant = true in {
 defm SRC_SHARED_BASE : SIRegLoHi16<"src_shared_base", 235>;
 defm SRC_SHARED_LIMIT : SIRegLoHi16<"src_shared_limit", 236>;
 defm SRC_PRIVATE_BASE : SIRegLoHi16<"src_private_base", 237>;
 defm SRC_PRIVATE_LIMIT : SIRegLoHi16<"src_private_limit", 238>;
+} // isConstant = true
 defm SRC_POPS_EXITING_WAVE_ID : SIRegLoHi16<"src_pops_exiting_wave_id", 239>;
 
 // Not addressable
 def MODE : SIReg <"mode", 0>;
 
 def LDS_DIRECT : SIReg <"src_lds_direct", 254> {
   // There is no physical register corresponding to this. This is an
   // encoding value in a source field, which will ultimately trigger a
   // read from m0.

llvm/lib/Target/LoongArch/LoongArchRegisterInfo.h

struct LoongArchRegisterInfo : public LoongArchGenRegisterInfo {
   LoongArchRegisterInfo(unsigned HwMode);
 
   const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF) const override;
   const uint32_t *getCallPreservedMask(const MachineFunction &MF,
                                        CallingConv::ID) const override;
   const uint32_t *getNoPreservedMask() const override;
 
   BitVector getReservedRegs(const MachineFunction &MF) const override;
-  bool isConstantPhysReg(MCRegister PhysReg) const override;
 
   const TargetRegisterClass *
   getPointerRegClass(const MachineFunction &MF,
                      unsigned Kind = 0) const override {
     return &LoongArch::GPRRegClass;
   }
 
   void eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj,
                            unsigned FIOperandNum,
                            RegScavenger *RS = nullptr) const override;
 
   Register getFrameRegister(const MachineFunction &MF) const override;
 };
 } // end namespace llvm
 
 #endif // LLVM_LIB_TARGET_LOONGARCH_LOONGARCHREGISTERINFO_H

llvm/lib/Target/LoongArch/LoongArchRegisterInfo.cpp

LoongArchRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
   // variable-sized objects at runtime.
   if (TFI->hasBP(MF))
     markSuperRegs(Reserved, LoongArchABI::getBPReg()); // bp
 
   assert(checkAllSuperRegsMarked(Reserved));
   return Reserved;
 }
 
-bool LoongArchRegisterInfo::isConstantPhysReg(MCRegister PhysReg) const {
-  return PhysReg == LoongArch::R0;
-}
-
 Register
 LoongArchRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
   const TargetFrameLowering *TFI = getFrameLowering(MF);
   return TFI->hasFP(MF) ? LoongArch::R22 : LoongArch::R3;
 }
 
 void LoongArchRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
                                                 int SPAdj,

llvm/lib/Target/LoongArch/LoongArchRegisterInfo.td

 
 let FallbackRegAltNameIndex = NoRegAltName in
 def RegAliasName : RegAltNameIndex;
 } // Namespace = "LoongArch"
 
 // Integer registers
 
 let RegAltNameIndices = [RegAliasName] in {
+  let isConstant = true in
   def R0  : LoongArchReg<0,  "r0", ["zero"]>, DwarfRegNum<[0]>;
   def R1  : LoongArchReg<1,  "r1", ["ra"]>, DwarfRegNum<[1]>;
   def R2  : LoongArchReg<2,  "r2", ["tp"]>, DwarfRegNum<[2]>;
   def R3  : LoongArchReg<3,  "r3", ["sp"]>, DwarfRegNum<[3]>;
   def R4  : LoongArchReg<4,  "r4", ["a0"]>, DwarfRegNum<[4]>;
   def R5  : LoongArchReg<5,  "r5", ["a1"]>, DwarfRegNum<[5]>;
   def R6  : LoongArchReg<6,  "r6", ["a2"]>, DwarfRegNum<[6]>;
   def R7  : LoongArchReg<7,  "r7", ["a3"]>, DwarfRegNum<[7]>;

llvm/lib/Target/Mips/MipsRegisterInfo.h

void eliminateFrameIndex(MachineBasicBlock::iterator II,
                            RegScavenger *RS = nullptr) const override;
 
   // Stack realignment queries.
   bool canRealignStack(const MachineFunction &MF) const override;
 
   /// Debug information queries.
   Register getFrameRegister(const MachineFunction &MF) const override;
 
-  bool isConstantPhysReg(MCRegister PhysReg) const override;
-
   /// Return GPR register class.
   virtual const TargetRegisterClass *intRegClass(unsigned Size) const = 0;
 
 private:
   virtual void eliminateFI(MachineBasicBlock::iterator II, unsigned OpNo,
                            int FrameIndex, uint64_t StackSize,
                            int64_t SPOffset) const = 0;
 };
 
 } // end namespace llvm
 
 #endif // LLVM_LIB_TARGET_MIPS_MIPSREGISTERINFO_H

llvm/lib/Target/Mips/MipsRegisterInfo.cpp

bool MipsRegisterInfo::canRealignStack(const MachineFunction &MF) const {
   // don't have variable sized objects.
   if (Subtarget.getFrameLowering()->hasReservedCallFrame(MF))
     return true;
 
   // We have to reserve the base pointer register in the presence of variable
   // sized objects.
   return MF.getRegInfo().canReserveReg(BP);
 }
-
-bool MipsRegisterInfo::isConstantPhysReg(MCRegister PhysReg) const {
-  return PhysReg == Mips::ZERO_64 || PhysReg == Mips::ZERO;
-}

llvm/lib/Target/Mips/MipsRegisterInfo.td

 class HWR<bits<16> Enc, string n> : MipsReg<Enc, n>;
 
 //===----------------------------------------------------------------------===//
 //  Registers
 //===----------------------------------------------------------------------===//
 
 let Namespace = "Mips" in {
   // General Purpose Registers
+  let isConstant = true in
   def ZERO : MipsGPRReg< 0, "zero">, DwarfRegNum<[0]>;
   def AT   : MipsGPRReg< 1, "1">,    DwarfRegNum<[1]>;
   def V0   : MipsGPRReg< 2, "2">,    DwarfRegNum<[2]>;
   def V1   : MipsGPRReg< 3, "3">,    DwarfRegNum<[3]>;
   def A0   : MipsGPRReg< 4, "4">,    DwarfRegNum<[4]>;
   def A1   : MipsGPRReg< 5, "5">,    DwarfRegNum<[5]>;
   def A2   : MipsGPRReg< 6, "6">,    DwarfRegNum<[6]>;
   def A3   : MipsGPRReg< 7, "7">,    DwarfRegNum<[7]>;
   def T0   : MipsGPRReg< 8, "8">,    DwarfRegNum<[8]>;
let Namespace = "Mips" in {
   def K0   : MipsGPRReg< 26, "26">,  DwarfRegNum<[26]>;
   def K1   : MipsGPRReg< 27, "27">,  DwarfRegNum<[27]>;
   def GP   : MipsGPRReg< 28, "gp">,  DwarfRegNum<[28]>;
   def SP   : MipsGPRReg< 29, "sp">,  DwarfRegNum<[29]>;
   def FP   : MipsGPRReg< 30, "fp">,  DwarfRegNum<[30]>;
   def RA   : MipsGPRReg< 31, "ra">,  DwarfRegNum<[31]>;
 
   // General Purpose 64-bit Registers
+  let isConstant = true in
   def ZERO_64 : Mips64GPRReg< 0, "zero", [ZERO]>, DwarfRegNum<[0]>;
   def AT_64   : Mips64GPRReg< 1, "1",    [AT]>, DwarfRegNum<[1]>;
   def V0_64   : Mips64GPRReg< 2, "2",    [V0]>, DwarfRegNum<[2]>;
   def V1_64   : Mips64GPRReg< 3, "3",    [V1]>, DwarfRegNum<[3]>;
   def A0_64   : Mips64GPRReg< 4, "4",    [A0]>, DwarfRegNum<[4]>;
   def A1_64   : Mips64GPRReg< 5, "5",    [A1]>, DwarfRegNum<[5]>;
   def A2_64   : Mips64GPRReg< 6, "6",    [A2]>, DwarfRegNum<[6]>;
   def A3_64   : Mips64GPRReg< 7, "7",    [A3]>, DwarfRegNum<[7]>;

llvm/lib/Target/PowerPC/PPCRegisterInfo.td

 }
 
 // 16 paired even-odd consecutive GP8s.
 foreach Index = { 0, 2, 4, 6, 8, 10, 12, 14, 16, 18, 20, 22, 24, 26, 28, 30 } in {
   def G8p#!srl(Index, 1) : GP8Pair<"r"#Index, Index>;
 }
 
 // The representation of r0 when treated as the constant 0.
+let isConstant = true in {
 def ZERO  : GPR<0, "0">,    DwarfRegAlias<R0>;
 def ZERO8 : GP8<ZERO, "0">, DwarfRegAlias<X0>;
+} // isConstant = true
 
 // Representations of the frame pointer used by ISD::FRAMEADDR.
 def FP   : GPR<0 /* arbitrary */, "**FRAME POINTER**">;
 def FP8  : GP8<FP, "**FRAME POINTER**">;
 
 // Representations of the base pointer used by setjmp.
 def BP   : GPR<0 /* arbitrary */, "**BASE POINTER**">;
 def BP8  : GP8<BP, "**BASE POINTER**">;

llvm/lib/Target/RISCV/RISCVRegisterInfo.h

const uint32_t *getCallPreservedMask(const MachineFunction &MF,
                                        CallingConv::ID) const override;
 
   const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF) const override;
 
   BitVector getReservedRegs(const MachineFunction &MF) const override;
   bool isAsmClobberable(const MachineFunction &MF,
                         MCRegister PhysReg) const override;
 
-  bool isConstantPhysReg(MCRegister PhysReg) const override;
-
   const uint32_t *getNoPreservedMask() const override;
 
   bool hasReservedSpillSlot(const MachineFunction &MF, Register Reg,
                             int &FrameIdx) const override;
 
   void eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj,
                            unsigned FIOperandNum,
                            RegScavenger *RS = nullptr) const override;

llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp

BitVector RISCVRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
   return Reserved;
 }
 
 bool RISCVRegisterInfo::isAsmClobberable(const MachineFunction &MF,
                                          MCRegister PhysReg) const {
   return !MF.getSubtarget<RISCVSubtarget>().isRegisterReservedByUser(PhysReg);
 }
 
-bool RISCVRegisterInfo::isConstantPhysReg(MCRegister PhysReg) const {
-  return PhysReg == RISCV::X0 || PhysReg == RISCV::VLENB;
-}
-
 const uint32_t *RISCVRegisterInfo::getNoPreservedMask() const {
   return CSR_NoRegs_RegMask;
 }
 
 // Frame indexes representing locations of CSRs which are given a fixed location
 // by save/restore libcalls.
 static const std::pair<unsigned, int> FixedCSRFIMap[] = {
   {/*ra*/  RISCV::X1,   -1},

llvm/lib/Target/RISCV/RISCVRegisterInfo.td

 // Integer registers
 // CostPerUse is set higher for registers that may not be compressible as they
 // are not part of GPRC, the most restrictive register class used by the
 // compressed instruction set. This will influence the greedy register
 // allocator to reduce the use of registers that can't be encoded in 16 bit
 // instructions.
 
 let RegAltNameIndices = [ABIRegAltName] in {
+  let isConstant = true in
   def X0  : RISCVReg<0, "x0", ["zero"]>, DwarfRegNum<[0]>;
   let CostPerUse = [0, 1] in {
   def X1  : RISCVReg<1, "x1", ["ra"]>, DwarfRegNum<[1]>;
   def X2  : RISCVReg<2, "x2", ["sp"]>, DwarfRegNum<[2]>;
   def X3  : RISCVReg<3, "x3", ["gp"]>, DwarfRegNum<[3]>;
   def X4  : RISCVReg<4, "x4", ["tp"]>, DwarfRegNum<[4]>;
   def X5  : RISCVReg<5, "x5", ["t0"]>, DwarfRegNum<[5]>;
   def X6  : RISCVReg<6, "x6", ["t1"]>, DwarfRegNum<[6]>;
def V#Index#M8 : RISCVRegWithSubRegs<Index, "v"#Index,
       let SubRegIndices = [sub_vrm4_0, sub_vrm4_1];
     }
   }
 
   def VTYPE  : RISCVReg<0, "vtype", ["vtype"]>;
   def VL     : RISCVReg<0, "vl", ["vl"]>;
   def VXSAT  : RISCVReg<0, "vxsat", ["vxsat"]>;
   def VXRM   : RISCVReg<0, "vxrm", ["vxrm"]>;
+  let isConstant = true in
   def VLENB  : RISCVReg<0, "vlenb", ["vlenb"]>,
                DwarfRegNum<[!add(4096, SysRegVLENB.Encoding)]>;
 }
 
 def VCSR : RegisterClass<"RISCV", [XLenVT], 32,
                           (add VTYPE, VL, VLENB)> {
   let RegInfos = XLenRI;
 }

llvm/lib/Target/VE/VERegisterInfo.h

public:
 
   /// Code Generation virtual methods...
   const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF) const override;
   const uint32_t *getCallPreservedMask(const MachineFunction &MF,
                                        CallingConv::ID CC) const override;
   const uint32_t *getNoPreservedMask() const override;
 
   BitVector getReservedRegs(const MachineFunction &MF) const override;
-  bool isConstantPhysReg(MCRegister PhysReg) const override;
 
   const TargetRegisterClass *getPointerRegClass(const MachineFunction &MF,
                                                 unsigned Kind) const override;
 
   void eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj,
                            unsigned FIOperandNum,
                            RegScavenger *RS = nullptr) const override;
 
   Register getFrameRegister(const MachineFunction &MF) const override;
 };
 
 } // namespace llvm
 
 #endif

llvm/lib/Target/VE/VERegisterInfo.cpp

BitVector VERegisterInfo::getReservedRegs(const MachineFunction &MF) const {
 
   // Reserve constant registers.
   Reserved.set(VE::VM0);
   Reserved.set(VE::VMP0);
 
   return Reserved;
 }
 
-bool VERegisterInfo::isConstantPhysReg(MCRegister PhysReg) const {
-  switch (PhysReg) {
-  case VE::VM0:
-  case VE::VMP0:
-    return true;
-  default:
-    return false;
-  }
-}
-
 const TargetRegisterClass *
 VERegisterInfo::getPointerRegClass(const MachineFunction &MF,
                                    unsigned Kind) const {
   return &VE::I64RegClass;
 }
 
 static unsigned offsetToDisp(MachineInstr &MI) {
   // Default offset in instruction's operands (reg+reg+imm).

llvm/lib/Target/VE/VERegisterInfo.td

 // Vector registers - 64 bits wide 256 elements
 foreach I = 0-63 in
   def V#I : VEVecReg<I, "v"#I, [], ["v"#I]>, DwarfRegNum<[!add(64,I)]>;
 
 // Vector Index Register
 def VIX : VEVecReg<255, "vix", [], ["vix"]>;
 
 // Vector mask registers - 256 bits wide
-foreach I = 0-15 in
+let isConstant = true in
+def VM0 : VEMaskReg<0, "vm0", [], ["vm0"]>, DwarfRegNum<[128]>;
+foreach I = 1-15 in
   def VM#I : VEMaskReg<I, "vm"#I, [], ["vm"#I]>, DwarfRegNum<[!add(128,I)]>;
 
 // Aliases of VMs to use as a pair of two VM for packed instructions
+let isConstant = true in
 def VMP0 : VEMaskReg<0, "vm0", [], ["vm0"]>;
 
 let SubRegIndices = [sub_vm_even, sub_vm_odd], CoveredBySubRegs = 1 in
 foreach I = 1-7 in
   def VMP#I : VEMaskReg<!shl(I,1), "vmp"#I,
                         [!cast<VEMaskReg>("VM"#!shl(I,1)),
                          !cast<VEMaskReg>("VM"#!add(!shl(I,1),1))],
                         ["vm"#!shl(I,1)]>;

llvm/utils/TableGen/CodeGenRegisters.h

namespace llvm {
   /// CodeGenRegister - Represents a register definition.
   struct CodeGenRegister {
     Record *TheDef;
     unsigned EnumValue;
     std::vector<int64_t> CostPerUse;
     bool CoveredBySubRegs;
     bool HasDisjunctSubRegs;
     bool Artificial;
+    bool Constant;
 
     // Map SubRegIndex -> Register.
     typedef std::map<CodeGenSubRegIndex *, CodeGenRegister *,
                      deref<std::less<>>>
         SubRegMap;
 
     CodeGenRegister(Record *R, unsigned Enum);
 

llvm/utils/TableGen/CodeGenRegisters.cpp

 //===----------------------------------------------------------------------===//
 //                              CodeGenRegister
 //===----------------------------------------------------------------------===//
 
 CodeGenRegister::CodeGenRegister(Record *R, unsigned Enum)
     : TheDef(R), EnumValue(Enum),
       CostPerUse(R->getValueAsListOfInts("CostPerUse")),
       CoveredBySubRegs(R->getValueAsBit("CoveredBySubRegs")),
-      HasDisjunctSubRegs(false), SubRegsComplete(false),
-      SuperRegsComplete(false), TopoSig(~0u) {
+      HasDisjunctSubRegs(false), Constant(R->getValueAsBit("isConstant")),
+      SubRegsComplete(false), SuperRegsComplete(false), TopoSig(~0u) {
   Artificial = R->getValueAsBit("isArtificial");
 }
 
 void CodeGenRegister::buildObjectGraph(CodeGenRegBank &RegBank) {
   std::vector<Record*> SRIs = TheDef->getValueAsListOfDefs("SubRegIndices");
   std::vector<Record*> SRs = TheDef->getValueAsListOfDefs("SubRegs");
 
   if (SRIs.size() != SRs.size())

llvm/utils/TableGen/RegisterInfoEmitter.cpp

OS << "  const RegClassWeight &getRegClassWeight("
      << "  ArrayRef<const char *> getRegMaskNames() const override;\n"
      << "  ArrayRef<const uint32_t *> getRegMasks() const override;\n"
      << "  bool isGeneralPurposeRegister(const MachineFunction &, "
      << "MCRegister) const override;\n"
      << "  bool isFixedRegister(const MachineFunction &, "
      << "MCRegister) const override;\n"
      << "  bool isArgumentRegister(const MachineFunction &, "
      << "MCRegister) const override;\n"
+     << "  bool isConstantPhysReg(MCRegister PhysReg) const override final;\n"
      << "  /// Devirtualized TargetFrameLowering.\n"
      << "  static const " << TargetName << "FrameLowering *getFrameLowering(\n"
      << "      const MachineFunction &MF);\n"
      << "};\n\n";
 
   const auto &RegisterClasses = RegBank.getRegClasses();
 
   if (!RegisterClasses.empty()) {
if (Category.getName() == "ArgumentRegisters") {
       for (const CodeGenRegisterClass *RC : Category.getClasses())
         OS << "      " << RC->getQualifiedName()
            << "RegClass.contains(PhysReg) ||\n";
       break;
     }
   OS << "      false;\n";
   OS << "}\n\n";
 
+  OS << "bool " << ClassName << "::\n"
+     << "isConstantPhysReg(MCRegister PhysReg) const {\n"
+     << "  return\n";
+  for (const auto &Reg : Regs)
+    if (Reg.Constant)
+      OS << "      PhysReg == " << getQualifiedName(Reg.TheDef) << " ||\n";
+  OS << "      false;\n";
+  OS << "}\n\n";
+
   OS << "ArrayRef<const char *> " << ClassName
      << "::getRegMaskNames() const {\n";
   if (!CSRSets.empty()) {
     OS << "  static const char *Names[] = {\n";
     for (Record *CSRSet : CSRSets)
       OS << "    " << '"' << CSRSet->getName() << '"' << ",\n";
     OS << "  };\n";
     OS << "  return makeArrayRef(Names);\n";