[RegisterInfoEmitter] Generate isConstantPhysReg(). NFCI

[arichardson]

Summary

This commit moves the information on whether a register is constant into
the Tablegen files to allow generating the implementaiton of
isConstantPhysReg(). I've marked isConstantPhysReg() as final in this
generated file to ensure that changes are made to tablegen instead of
overriding this function, but if that turns out to be too restrictive,
we can remove the qualifier.

This should be pretty much NFC, but I did notice that e.g. the AMDGPU
generated file also includes the LO16/HI16 registers now.

The new isConstant flag will also be used by D131958 to ensure that
constant registers are marked as call-preserved.

[arichardson]

fix indentation

[arichardson]

Include the tablegen changes here

[arichardson]

The generated functions look as follows and mostly match the existing ones (a few extra subregs for AMDGPU and added PPC registers).

cmake-build-debug/lib/Target/AArch64/AArch64GenRegisterInfo.inc:isConstantPhysReg(MCRegister PhysReg) const {
cmake-build-debug/lib/Target/AArch64/AArch64GenRegisterInfo.inc-  return
cmake-build-debug/lib/Target/AArch64/AArch64GenRegisterInfo.inc-      PhysReg == AArch64::WZR ||
cmake-build-debug/lib/Target/AArch64/AArch64GenRegisterInfo.inc-      PhysReg == AArch64::XZR ||
cmake-build-debug/lib/Target/AArch64/AArch64GenRegisterInfo.inc-      false;
cmake-build-debug/lib/Target/AArch64/AArch64GenRegisterInfo.inc-}
--
cmake-build-debug/lib/Target/AMDGPU/AMDGPUGenRegisterInfo.inc:isConstantPhysReg(MCRegister PhysReg) const {
cmake-build-debug/lib/Target/AMDGPU/AMDGPUGenRegisterInfo.inc-  return
cmake-build-debug/lib/Target/AMDGPU/AMDGPUGenRegisterInfo.inc-      PhysReg == AMDGPU::SGPR_NULL ||
cmake-build-debug/lib/Target/AMDGPU/AMDGPUGenRegisterInfo.inc-      PhysReg == AMDGPU::SGPR_NULL_HI ||
cmake-build-debug/lib/Target/AMDGPU/AMDGPUGenRegisterInfo.inc-      PhysReg == AMDGPU::SRC_POPS_EXITING_WAVE_ID ||
cmake-build-debug/lib/Target/AMDGPU/AMDGPUGenRegisterInfo.inc-      PhysReg == AMDGPU::SRC_PRIVATE_BASE ||
cmake-build-debug/lib/Target/AMDGPU/AMDGPUGenRegisterInfo.inc-      PhysReg == AMDGPU::SRC_PRIVATE_LIMIT ||
cmake-build-debug/lib/Target/AMDGPU/AMDGPUGenRegisterInfo.inc-      PhysReg == AMDGPU::SRC_SHARED_BASE ||
cmake-build-debug/lib/Target/AMDGPU/AMDGPUGenRegisterInfo.inc-      PhysReg == AMDGPU::SRC_SHARED_LIMIT ||
cmake-build-debug/lib/Target/AMDGPU/AMDGPUGenRegisterInfo.inc-      PhysReg == AMDGPU::SGPR_NULL64 ||
cmake-build-debug/lib/Target/AMDGPU/AMDGPUGenRegisterInfo.inc-      PhysReg == AMDGPU::SGPR_NULL_HI16 ||
cmake-build-debug/lib/Target/AMDGPU/AMDGPUGenRegisterInfo.inc-      PhysReg == AMDGPU::SGPR_NULL_HI_HI16 ||
cmake-build-debug/lib/Target/AMDGPU/AMDGPUGenRegisterInfo.inc-      PhysReg == AMDGPU::SGPR_NULL_HI_LO16 ||
cmake-build-debug/lib/Target/AMDGPU/AMDGPUGenRegisterInfo.inc-      PhysReg == AMDGPU::SGPR_NULL_LO16 ||
cmake-build-debug/lib/Target/AMDGPU/AMDGPUGenRegisterInfo.inc-      PhysReg == AMDGPU::SRC_POPS_EXITING_WAVE_ID_HI16 ||
cmake-build-debug/lib/Target/AMDGPU/AMDGPUGenRegisterInfo.inc-      PhysReg == AMDGPU::SRC_POPS_EXITING_WAVE_ID_LO16 ||
cmake-build-debug/lib/Target/AMDGPU/AMDGPUGenRegisterInfo.inc-      PhysReg == AMDGPU::SRC_PRIVATE_BASE_HI16 ||
cmake-build-debug/lib/Target/AMDGPU/AMDGPUGenRegisterInfo.inc-      PhysReg == AMDGPU::SRC_PRIVATE_BASE_LO16 ||
cmake-build-debug/lib/Target/AMDGPU/AMDGPUGenRegisterInfo.inc-      PhysReg == AMDGPU::SRC_PRIVATE_LIMIT_HI16 ||
cmake-build-debug/lib/Target/AMDGPU/AMDGPUGenRegisterInfo.inc-      PhysReg == AMDGPU::SRC_PRIVATE_LIMIT_LO16 ||
cmake-build-debug/lib/Target/AMDGPU/AMDGPUGenRegisterInfo.inc-      PhysReg == AMDGPU::SRC_SHARED_BASE_HI16 ||
cmake-build-debug/lib/Target/AMDGPU/AMDGPUGenRegisterInfo.inc-      PhysReg == AMDGPU::SRC_SHARED_BASE_LO16 ||
cmake-build-debug/lib/Target/AMDGPU/AMDGPUGenRegisterInfo.inc-      PhysReg == AMDGPU::SRC_SHARED_LIMIT_HI16 ||
cmake-build-debug/lib/Target/AMDGPU/AMDGPUGenRegisterInfo.inc-      PhysReg == AMDGPU::SRC_SHARED_LIMIT_LO16 ||
cmake-build-debug/lib/Target/AMDGPU/AMDGPUGenRegisterInfo.inc-      false;
cmake-build-debug/lib/Target/AMDGPU/AMDGPUGenRegisterInfo.inc-}
--
cmake-build-debug/lib/Target/AMDGPU/R600GenRegisterInfo.inc:isConstantPhysReg(MCRegister PhysReg) const {
cmake-build-debug/lib/Target/AMDGPU/R600GenRegisterInfo.inc-  return
cmake-build-debug/lib/Target/AMDGPU/R600GenRegisterInfo.inc-      false;
cmake-build-debug/lib/Target/AMDGPU/R600GenRegisterInfo.inc-}
--
cmake-build-debug/lib/Target/ARM/ARMGenRegisterInfo.inc:isConstantPhysReg(MCRegister PhysReg) const {
cmake-build-debug/lib/Target/ARM/ARMGenRegisterInfo.inc-  return
cmake-build-debug/lib/Target/ARM/ARMGenRegisterInfo.inc-      false;
cmake-build-debug/lib/Target/ARM/ARMGenRegisterInfo.inc-}
--
cmake-build-debug/lib/Target/AVR/AVRGenRegisterInfo.inc:isConstantPhysReg(MCRegister PhysReg) const {
cmake-build-debug/lib/Target/AVR/AVRGenRegisterInfo.inc-  return
cmake-build-debug/lib/Target/AVR/AVRGenRegisterInfo.inc-      false;
cmake-build-debug/lib/Target/AVR/AVRGenRegisterInfo.inc-}
--
cmake-build-debug/lib/Target/BPF/BPFGenRegisterInfo.inc:isConstantPhysReg(MCRegister PhysReg) const {
cmake-build-debug/lib/Target/BPF/BPFGenRegisterInfo.inc-  return
cmake-build-debug/lib/Target/BPF/BPFGenRegisterInfo.inc-      false;
cmake-build-debug/lib/Target/BPF/BPFGenRegisterInfo.inc-}
--
cmake-build-debug/lib/Target/Hexagon/HexagonGenRegisterInfo.inc:isConstantPhysReg(MCRegister PhysReg) const {
cmake-build-debug/lib/Target/Hexagon/HexagonGenRegisterInfo.inc-  return
cmake-build-debug/lib/Target/Hexagon/HexagonGenRegisterInfo.inc-      false;
cmake-build-debug/lib/Target/Hexagon/HexagonGenRegisterInfo.inc-}
--
cmake-build-debug/lib/Target/Lanai/LanaiGenRegisterInfo.inc:isConstantPhysReg(MCRegister PhysReg) const {
cmake-build-debug/lib/Target/Lanai/LanaiGenRegisterInfo.inc-  return
cmake-build-debug/lib/Target/Lanai/LanaiGenRegisterInfo.inc-      false;
cmake-build-debug/lib/Target/Lanai/LanaiGenRegisterInfo.inc-}
--
cmake-build-debug/lib/Target/Mips/MipsGenRegisterInfo.inc:isConstantPhysReg(MCRegister PhysReg) const {
cmake-build-debug/lib/Target/Mips/MipsGenRegisterInfo.inc-  return
cmake-build-debug/lib/Target/Mips/MipsGenRegisterInfo.inc-      PhysReg == Mips::ZERO ||
cmake-build-debug/lib/Target/Mips/MipsGenRegisterInfo.inc-      PhysReg == Mips::ZERO_64 ||
cmake-build-debug/lib/Target/Mips/MipsGenRegisterInfo.inc-      false;
cmake-build-debug/lib/Target/Mips/MipsGenRegisterInfo.inc-}
--
cmake-build-debug/lib/Target/MSP430/MSP430GenRegisterInfo.inc:isConstantPhysReg(MCRegister PhysReg) const {
cmake-build-debug/lib/Target/MSP430/MSP430GenRegisterInfo.inc-  return
cmake-build-debug/lib/Target/MSP430/MSP430GenRegisterInfo.inc-      false;
cmake-build-debug/lib/Target/MSP430/MSP430GenRegisterInfo.inc-}
--
cmake-build-debug/lib/Target/NVPTX/NVPTXGenRegisterInfo.inc:isConstantPhysReg(MCRegister PhysReg) const {
cmake-build-debug/lib/Target/NVPTX/NVPTXGenRegisterInfo.inc-  return
cmake-build-debug/lib/Target/NVPTX/NVPTXGenRegisterInfo.inc-      false;
cmake-build-debug/lib/Target/NVPTX/NVPTXGenRegisterInfo.inc-}
--
cmake-build-debug/lib/Target/PowerPC/PPCGenRegisterInfo.inc:isConstantPhysReg(MCRegister PhysReg) const {
cmake-build-debug/lib/Target/PowerPC/PPCGenRegisterInfo.inc-  return
cmake-build-debug/lib/Target/PowerPC/PPCGenRegisterInfo.inc-      PhysReg == PPC::ZERO ||
cmake-build-debug/lib/Target/PowerPC/PPCGenRegisterInfo.inc-      PhysReg == PPC::ZERO8 ||
cmake-build-debug/lib/Target/PowerPC/PPCGenRegisterInfo.inc-      false;
cmake-build-debug/lib/Target/PowerPC/PPCGenRegisterInfo.inc-}
--
cmake-build-debug/lib/Target/RISCV/RISCVGenRegisterInfo.inc:isConstantPhysReg(MCRegister PhysReg) const {
cmake-build-debug/lib/Target/RISCV/RISCVGenRegisterInfo.inc-  return
cmake-build-debug/lib/Target/RISCV/RISCVGenRegisterInfo.inc-      PhysReg == RISCV::VLENB ||
cmake-build-debug/lib/Target/RISCV/RISCVGenRegisterInfo.inc-      PhysReg == RISCV::X0 ||
cmake-build-debug/lib/Target/RISCV/RISCVGenRegisterInfo.inc-      false;
cmake-build-debug/lib/Target/RISCV/RISCVGenRegisterInfo.inc-}
--
cmake-build-debug/lib/Target/Sparc/SparcGenRegisterInfo.inc:isConstantPhysReg(MCRegister PhysReg) const {
cmake-build-debug/lib/Target/Sparc/SparcGenRegisterInfo.inc-  return
cmake-build-debug/lib/Target/Sparc/SparcGenRegisterInfo.inc-      false;
cmake-build-debug/lib/Target/Sparc/SparcGenRegisterInfo.inc-}
--
cmake-build-debug/lib/Target/SystemZ/SystemZGenRegisterInfo.inc:isConstantPhysReg(MCRegister PhysReg) const {
cmake-build-debug/lib/Target/SystemZ/SystemZGenRegisterInfo.inc-  return
cmake-build-debug/lib/Target/SystemZ/SystemZGenRegisterInfo.inc-      false;
cmake-build-debug/lib/Target/SystemZ/SystemZGenRegisterInfo.inc-}
--
cmake-build-debug/lib/Target/VE/VEGenRegisterInfo.inc:isConstantPhysReg(MCRegister PhysReg) const {
cmake-build-debug/lib/Target/VE/VEGenRegisterInfo.inc-  return
cmake-build-debug/lib/Target/VE/VEGenRegisterInfo.inc-      PhysReg == VE::VM0 ||
cmake-build-debug/lib/Target/VE/VEGenRegisterInfo.inc-      PhysReg == VE::VMP0 ||
cmake-build-debug/lib/Target/VE/VEGenRegisterInfo.inc-      false;
cmake-build-debug/lib/Target/VE/VEGenRegisterInfo.inc-}
--
cmake-build-debug/lib/Target/WebAssembly/WebAssemblyGenRegisterInfo.inc:isConstantPhysReg(MCRegister PhysReg) const {
cmake-build-debug/lib/Target/WebAssembly/WebAssemblyGenRegisterInfo.inc-  return
cmake-build-debug/lib/Target/WebAssembly/WebAssemblyGenRegisterInfo.inc-      false;
cmake-build-debug/lib/Target/WebAssembly/WebAssemblyGenRegisterInfo.inc-}
--
cmake-build-debug/lib/Target/X86/X86GenRegisterInfo.inc:isConstantPhysReg(MCRegister PhysReg) const {
cmake-build-debug/lib/Target/X86/X86GenRegisterInfo.inc-  return
cmake-build-debug/lib/Target/X86/X86GenRegisterInfo.inc-      false;
cmake-build-debug/lib/Target/X86/X86GenRegisterInfo.inc-}
--
cmake-build-debug/lib/Target/XCore/XCoreGenRegisterInfo.inc:isConstantPhysReg(MCRegister PhysReg) const {
cmake-build-debug/lib/Target/XCore/XCoreGenRegisterInfo.inc-  return
cmake-build-debug/lib/Target/XCore/XCoreGenRegisterInfo.inc-      false;
cmake-build-debug/lib/Target/XCore/XCoreGenRegisterInfo.inc-}

[jrtc27]

llvm/lib/Target/AMDGPU/SIRegisterInfo.td

146 ↗

(On Diff #452992)

Not used any more

227 ↗

(On Diff #452992)

This wasn't constant before

242 ↗

(On Diff #452992)

This wasn't constant before

llvm/lib/Target/Mips/MipsRegisterInfo.td

87 ↗

(On Diff #452992)

let ... in gets used for SubRegIndices later

[arichardson]

improve tablegen style

[arichardson]

SRC_POPS_EXITING_WAVE_ID should not be constant

[arichardson]

llvm/lib/Target/AMDGPU/SIRegisterInfo.td

227 ↗

(On Diff #452992)

That's true, but since it's a subreg if SGPR_NULL64 I assumed it must be.

242 ↗

(On Diff #452992)

fixed.

[asb]

This LGTM from a RISC-V perspective and makes a lot of sense to generate from from TableGen rather than hand-coding.

I think it would be worth getting an LGTM from the AMDGPU side before landing.

[nemanjai]

LGTM for PPC.

[Carrot]

%g0 on SPARC is also a constant register.
https://docs.oracle.com/cd/E26502_01/html/E28387/gentextid-2715.html

[foad]

LGTM for AMDGPU.

llvm/lib/Target/AMDGPU/SIRegisterInfo.td

231 ↗

(On Diff #452996)

Please don't remove the blank line :)

[arichardson]

In D131962#3735681, @Carrot wrote:

%g0 on SPARC is also a constant register.
https://docs.oracle.com/cd/E26502_01/html/E28387/gentextid-2715.html

Done in https://reviews.llvm.org/D132561

llvm/lib/Target/AArch64/AArch64RegisterInfo.h

const uint32_t *getThisReturnPreservedMask(const MachineFunction &MF,
                                              CallingConv::ID) const;
 
   /// Stack probing calls preserve different CSRs to the normal CC.
   const uint32_t *getWindowsStackProbePreservedMask() const;
 
   BitVector getReservedRegs(const MachineFunction &MF) const override;
   bool isAsmClobberable(const MachineFunction &MF,
                        MCRegister PhysReg) const override;
-  bool isConstantPhysReg(MCRegister PhysReg) const override;
   const TargetRegisterClass *
   getPointerRegClass(const MachineFunction &MF,
                      unsigned Kind = 0) const override;
   const TargetRegisterClass *
   getCrossCopyRegClass(const TargetRegisterClass *RC) const override;
 
   bool requiresRegisterScavenging(const MachineFunction &MF) const override;
   bool useFPForScavengingIndex(const MachineFunction &MF) const override;

llvm/lib/Target/AArch64/AArch64RegisterInfo.cpp

F.getContext().diagnose(DiagnosticInfoUnsupported{F, ("AArch64 doesn't support"
     " function calls if any of the argument registers is reserved.")});
 }
 
 bool AArch64RegisterInfo::isAsmClobberable(const MachineFunction &MF,
                                           MCRegister PhysReg) const {
   return !isReservedReg(MF, PhysReg);
 }
 
-bool AArch64RegisterInfo::isConstantPhysReg(MCRegister PhysReg) const {
-  return PhysReg == AArch64::WZR || PhysReg == AArch64::XZR;
-}
-
 const TargetRegisterClass *
 AArch64RegisterInfo::getPointerRegClass(const MachineFunction &MF,
                                       unsigned Kind) const {
   return &AArch64::GPR64spRegClass;
 }
 
 const TargetRegisterClass *
 AArch64RegisterInfo::getCrossCopyRegClass(const TargetRegisterClass *RC) const {

llvm/lib/Target/AMDGPU/SIRegisterInfo.h

public:
   const TargetRegisterClass *getRegClassForReg(const MachineRegisterInfo &MRI,
                                                Register Reg) const;
   bool isVGPR(const MachineRegisterInfo &MRI, Register Reg) const;
   bool isAGPR(const MachineRegisterInfo &MRI, Register Reg) const;
   bool isVectorRegister(const MachineRegisterInfo &MRI, Register Reg) const {
     return isVGPR(MRI, Reg) || isAGPR(MRI, Reg);
   }
 
-  bool isConstantPhysReg(MCRegister PhysReg) const override;
-
   bool isDivergentRegClass(const TargetRegisterClass *RC) const override {
     return !isSGPRClass(RC);
   }
 
   ArrayRef<int16_t> getRegSplitParts(const TargetRegisterClass *RC,
                                      unsigned EltSize) const;
 
   bool shouldCoalesce(MachineInstr *MI,

llvm/lib/Target/AMDGPU/SIRegisterInfo.cpp

SIRegisterInfo::getProperlyAlignedRC(const TargetRegisterClass *RC) const {
   if (isAGPRClass(RC))
     return getAlignedAGPRClassForBitWidth(Size);
   if (isVectorSuperClass(RC))
     return getAlignedVectorSuperClassForBitWidth(Size);
 
   return RC;
 }
 
-bool SIRegisterInfo::isConstantPhysReg(MCRegister PhysReg) const {
-  switch (PhysReg) {
-  case AMDGPU::SGPR_NULL:
-  case AMDGPU::SGPR_NULL64:
-  case AMDGPU::SGPR_NULL_HI:
-  case AMDGPU::SRC_SHARED_BASE:
-  case AMDGPU::SRC_PRIVATE_BASE:
-  case AMDGPU::SRC_SHARED_LIMIT:
-  case AMDGPU::SRC_PRIVATE_LIMIT:
-    return true;
-  default:
-    return false;
-  }
-}
-
 ArrayRef<MCPhysReg>
 SIRegisterInfo::getAllSGPR128(const MachineFunction &MF) const {
   return makeArrayRef(AMDGPU::SGPR_128RegClass.begin(),
                       ST.getMaxNumSGPRs(MF) / 4);
 }
 
 ArrayRef<MCPhysReg>
 SIRegisterInfo::getAllSGPR64(const MachineFunction &MF) const {
   return makeArrayRef(AMDGPU::SGPR_64RegClass.begin(),
                       ST.getMaxNumSGPRs(MF) / 2);
 }
 
 ArrayRef<MCPhysReg>
 SIRegisterInfo::getAllSGPR32(const MachineFunction &MF) const {
   return makeArrayRef(AMDGPU::SGPR_32RegClass.begin(), ST.getMaxNumSGPRs(MF));
 }

llvm/lib/Target/LoongArch/LoongArchRegisterInfo.h

struct LoongArchRegisterInfo : public LoongArchGenRegisterInfo {
   LoongArchRegisterInfo(unsigned HwMode);
 
   const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF) const override;
   const uint32_t *getCallPreservedMask(const MachineFunction &MF,
                                        CallingConv::ID) const override;
   const uint32_t *getNoPreservedMask() const override;
 
   BitVector getReservedRegs(const MachineFunction &MF) const override;
-  bool isConstantPhysReg(MCRegister PhysReg) const override;
 
   const TargetRegisterClass *
   getPointerRegClass(const MachineFunction &MF,
                      unsigned Kind = 0) const override {
     return &LoongArch::GPRRegClass;
   }
 
   void eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj,
                            unsigned FIOperandNum,
                            RegScavenger *RS = nullptr) const override;
 
   Register getFrameRegister(const MachineFunction &MF) const override;
 };
 } // end namespace llvm
 
 #endif // LLVM_LIB_TARGET_LOONGARCH_LOONGARCHREGISTERINFO_H

llvm/lib/Target/LoongArch/LoongArchRegisterInfo.cpp

LoongArchRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
   // variable-sized objects at runtime.
   if (TFI->hasBP(MF))
     markSuperRegs(Reserved, LoongArchABI::getBPReg()); // bp
 
   assert(checkAllSuperRegsMarked(Reserved));
   return Reserved;
 }
 
-bool LoongArchRegisterInfo::isConstantPhysReg(MCRegister PhysReg) const {
-  return PhysReg == LoongArch::R0;
-}
-
 Register
 LoongArchRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
   const TargetFrameLowering *TFI = getFrameLowering(MF);
   return TFI->hasFP(MF) ? LoongArch::R22 : LoongArch::R3;
 }
 
 void LoongArchRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
                                                 int SPAdj,

llvm/lib/Target/Mips/MipsRegisterInfo.h

void eliminateFrameIndex(MachineBasicBlock::iterator II,
                            RegScavenger *RS = nullptr) const override;
 
   // Stack realignment queries.
   bool canRealignStack(const MachineFunction &MF) const override;
 
   /// Debug information queries.
   Register getFrameRegister(const MachineFunction &MF) const override;
 
-  bool isConstantPhysReg(MCRegister PhysReg) const override;
-
   /// Return GPR register class.
   virtual const TargetRegisterClass *intRegClass(unsigned Size) const = 0;
 
 private:
   virtual void eliminateFI(MachineBasicBlock::iterator II, unsigned OpNo,
                            int FrameIndex, uint64_t StackSize,
                            int64_t SPOffset) const = 0;
 };
 
 } // end namespace llvm
 
 #endif // LLVM_LIB_TARGET_MIPS_MIPSREGISTERINFO_H

llvm/lib/Target/Mips/MipsRegisterInfo.cpp

bool MipsRegisterInfo::canRealignStack(const MachineFunction &MF) const {
   // don't have variable sized objects.
   if (Subtarget.getFrameLowering()->hasReservedCallFrame(MF))
     return true;
 
   // We have to reserve the base pointer register in the presence of variable
   // sized objects.
   return MF.getRegInfo().canReserveReg(BP);
 }
-
-bool MipsRegisterInfo::isConstantPhysReg(MCRegister PhysReg) const {
-  return PhysReg == Mips::ZERO_64 || PhysReg == Mips::ZERO;
-}

llvm/lib/Target/RISCV/RISCVRegisterInfo.h

const uint32_t *getCallPreservedMask(const MachineFunction &MF,
                                        CallingConv::ID) const override;
 
   const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF) const override;
 
   BitVector getReservedRegs(const MachineFunction &MF) const override;
   bool isAsmClobberable(const MachineFunction &MF,
                         MCRegister PhysReg) const override;
 
-  bool isConstantPhysReg(MCRegister PhysReg) const override;
-
   const uint32_t *getNoPreservedMask() const override;
 
   bool hasReservedSpillSlot(const MachineFunction &MF, Register Reg,
                             int &FrameIdx) const override;
 
   void eliminateFrameIndex(MachineBasicBlock::iterator MI, int SPAdj,
                            unsigned FIOperandNum,
                            RegScavenger *RS = nullptr) const override;

llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp

BitVector RISCVRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
   return Reserved;
 }
 
 bool RISCVRegisterInfo::isAsmClobberable(const MachineFunction &MF,
                                          MCRegister PhysReg) const {
   return !MF.getSubtarget<RISCVSubtarget>().isRegisterReservedByUser(PhysReg);
 }
 
-bool RISCVRegisterInfo::isConstantPhysReg(MCRegister PhysReg) const {
-  return PhysReg == RISCV::X0 || PhysReg == RISCV::VLENB;
-}
-
 const uint32_t *RISCVRegisterInfo::getNoPreservedMask() const {
   return CSR_NoRegs_RegMask;
 }
 
 // Frame indexes representing locations of CSRs which are given a fixed location
 // by save/restore libcalls.
 static const std::pair<unsigned, int> FixedCSRFIMap[] = {
   {/*ra*/  RISCV::X1,   -1},

llvm/lib/Target/VE/VERegisterInfo.h

public:
 
   /// Code Generation virtual methods...
   const MCPhysReg *getCalleeSavedRegs(const MachineFunction *MF) const override;
   const uint32_t *getCallPreservedMask(const MachineFunction &MF,
                                        CallingConv::ID CC) const override;
   const uint32_t *getNoPreservedMask() const override;
 
   BitVector getReservedRegs(const MachineFunction &MF) const override;
-  bool isConstantPhysReg(MCRegister PhysReg) const override;
 
   const TargetRegisterClass *getPointerRegClass(const MachineFunction &MF,
                                                 unsigned Kind) const override;
 
   void eliminateFrameIndex(MachineBasicBlock::iterator II, int SPAdj,
                            unsigned FIOperandNum,
                            RegScavenger *RS = nullptr) const override;
 
   Register getFrameRegister(const MachineFunction &MF) const override;
 };
 
 } // namespace llvm
 
 #endif

llvm/lib/Target/VE/VERegisterInfo.cpp

BitVector VERegisterInfo::getReservedRegs(const MachineFunction &MF) const {
 
   // Reserve constant registers.
   Reserved.set(VE::VM0);
   Reserved.set(VE::VMP0);
 
   return Reserved;
 }
 
-bool VERegisterInfo::isConstantPhysReg(MCRegister PhysReg) const {
-  switch (PhysReg) {
-  case VE::VM0:
-  case VE::VMP0:
-    return true;
-  default:
-    return false;
-  }
-}
-
 const TargetRegisterClass *
 VERegisterInfo::getPointerRegClass(const MachineFunction &MF,
                                    unsigned Kind) const {
   return &VE::I64RegClass;
 }
 
 static unsigned offsetToDisp(MachineInstr &MI) {
   // Default offset in instruction's operands (reg+reg+imm).

llvm/utils/TableGen/RegisterInfoEmitter.cpp

OS << "  const RegClassWeight &getRegClassWeight("
      << "  ArrayRef<const char *> getRegMaskNames() const override;\n"
      << "  ArrayRef<const uint32_t *> getRegMasks() const override;\n"
      << "  bool isGeneralPurposeRegister(const MachineFunction &, "
      << "MCRegister) const override;\n"
      << "  bool isFixedRegister(const MachineFunction &, "
      << "MCRegister) const override;\n"
      << "  bool isArgumentRegister(const MachineFunction &, "
      << "MCRegister) const override;\n"
+     << "  bool isConstantPhysReg(MCRegister PhysReg) const override final;\n"
      << "  /// Devirtualized TargetFrameLowering.\n"
      << "  static const " << TargetName << "FrameLowering *getFrameLowering(\n"
      << "      const MachineFunction &MF);\n"
      << "};\n\n";
 
   const auto &RegisterClasses = RegBank.getRegClasses();
 
   if (!RegisterClasses.empty()) {
if (Category.getName() == "ArgumentRegisters") {
       for (const CodeGenRegisterClass *RC : Category.getClasses())
         OS << "      " << RC->getQualifiedName()
            << "RegClass.contains(PhysReg) ||\n";
       break;
     }
   OS << "      false;\n";
   OS << "}\n\n";
 
+  OS << "bool " << ClassName << "::\n"
+     << "isConstantPhysReg(MCRegister PhysReg) const {\n"
+     << "  return\n";
+  for (const auto &Reg : Regs)
+    if (Reg.Constant)
+      OS << "      PhysReg == " << getQualifiedName(Reg.TheDef) << " ||\n";
+  OS << "      false;\n";
+  OS << "}\n\n";
+
   OS << "ArrayRef<const char *> " << ClassName
      << "::getRegMaskNames() const {\n";
   if (!CSRSets.empty()) {
     OS << "  static const char *Names[] = {\n";
     for (Record *CSRSet : CSRSets)
       OS << "    " << '"' << CSRSet->getName() << '"' << ",\n";
     OS << "  };\n";
     OS << "  return makeArrayRef(Names);\n";