[WIP] [RISCV] Emit cfi directives for function epilogue

[xgupta]

Summary

This patch attempt to fix https://bugs.llvm.org/show_bug.cgi?id=51864. Which is related to debugging of a binary. This patch is actually reverted https://reviews.llvm.org/D69723 with a minor change.

[xgupta]

minor fix

[xgupta]

update one testcase

[xgupta]

IIUC the issue with previous version that .cfi_def_cfa_offset 0 should be .cfi_def_cfa_offset 16? If that is still the case I will try to fix this.
I have one question: - By applying this patch 304 test cases are failing. I only corrected one test case. Is there any script to update other test cases or do they need to be manually updated?

[jrtc27]

As I told you in various bug reports, the issue is that LLVM's CFI epilogue directives are utterly broken when shrink-wrapping is used. Please go re-read https://reviews.llvm.org/D69723 for the rationale behind reverting the original commit.

[xgupta]

Thanks for letting me know on various reports :). But I completely don't know what is shrink wrapping. I will read it more. My only understanding it as LLVM x86 is emitting these CFI directives so there should be no problem in RISCV. If shrink wrapping is the problem then we should revert that patch: https://reviews.llvm.org/D62190. If .cfi_restore ra is the problem then does that need to be fixed?
I only want watchpoints to work correctly in that binary. If it is not possible here, I think LLVM developers recommending me to "go" and add support for hardware watchpoint in RISCV gdb port. Is that correct?

[xgupta]

update few more testcase

[xgupta]

.

[xgupta]

Hi @HsiangKai, I want to know how you have written 12877+ lines of test cases such as in https://github.com/llvm/llvm-project/blob/main/llvm/test/CodeGen/RISCV/rvv/vluxseg-rv32.ll . I need to update them in this patch to pass check-llvm. It is some script? can you please tell me how to use that.

[jrtc27]

In D111519#3087088, @xgupta wrote:

Hi @HsiangKai, I want to know how you have written 12877+ lines of test cases such as in https://github.com/llvm/llvm-project/blob/main/llvm/test/CodeGen/RISCV/rvv/vluxseg-rv32.ll . I need to update them in this patch to pass check-llvm. It is some script? can you please tell me how to use that.

Read the very first line:

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py

Almost every test in llvm/test/CodeGen/RISCV uses that, you should rarely have to update them manually (I hope you didn't do so for all these tests here... if you did, please re-run the script on all of them, because the script can include things a human might not, e.g. you can see comments on many of the lines that technically aren't needed, but using the script ensures that when someone re-runs it they don't see spurious diffs).

[jrtc27]

That is:

utils/update_llc_test_checks.py --llc-binary build/bin/llc -u `find llvm/test/CodeGen/RISCV \( -name '*.ll' -o -name '*.mir' \)`
utils/update_mir_test_checks.py --llc-binary build/bin/llc -u `find llvm/test/CodeGen/RISCV \( -name '*.ll' -o -name '*.mir' \)`

[xgupta]

update all test cases

[xgupta]

In D111519#3087096, @jrtc27 wrote:

That is:

utils/update_llc_test_checks.py --llc-binary build/bin/llc -u `find llvm/test/CodeGen/RISCV \( -name '*.ll' -o -name '*.mir' \)`
utils/update_mir_test_checks.py --llc-binary build/bin/llc -u `find llvm/test/CodeGen/RISCV \( -name '*.ll' -o -name '*.mir' \)`

Thanks, I think it is not mention in the docs, I will write something about it in TestingGuide.rst .

[luke957]

So sorry for my bad herald script.

[xgupta]

Hi @luismarques, Do you have any comments here? Or what happens(break) when this CFI directive is emitted and shrink wrapping is used, an example? Stack unwinding problem, still it is here, what it needed to be fixed, maybe some hint.

I think this problem needs to be solved soon, and I am not an expert here to fix it by myself.

[xgupta]

Hello @luismarques,

can you please tell me how you have generated this assembly mentioned in the commit summary(.c file)?

define void @branch_and_tail_call(i1 %a) {
; RV32-LABEL: branch_and_tail_call:
; RV32:       # %bb.0:
; RV32-NEXT:    addi sp, sp, -16
; RV32-NEXT:    .cfi_def_cfa_offset 16
; RV32-NEXT:    sw ra, 12(sp)
; RV32-NEXT:    .cfi_offset ra, -4
; RV32-NEXT:    andi a0, a0, 1
; RV32-NEXT:    beqz a0, .LBB2_2
; RV32-NEXT:  # %bb.1: # %blue_pill
; RV32-NEXT:    lw ra, 12(sp)
; RV32-NEXT:    .cfi_restore ra
; RV32-NEXT:    addi sp, sp, 16
; RV32-NEXT:    .cfi_def_cfa_offset 0
; RV32-NEXT:    tail foo
; RV32-NEXT:  .LBB2_2: # %red_pill
; RV32-NEXT:    call bar
; RV32-NEXT:    lw ra, 12(sp)
; RV32-NEXT:    .cfi_restore ra
; RV32-NEXT:    addi sp, sp, 16
; RV32-NEXT:    .cfi_def_cfa_offset 0
; RV32-NEXT:    ret
}

For instance, without this patch the following program will not correctly unwind, and will get stuck (compile with clang, link with a gnu toolchain, test with qemu):

void three() {
    throw 7;
}

void two(void) {
    try {
        three();
    } catch(int &c) {
        throw 42;
    }
}

int main() {
    try {
        two();
    }
    catch(...) {
    }
    return 0;
}

When you say it get stuck, can you please tell me what steps you have run?

PS I want to revert this patch to fix https://bugs.llvm.org/show_bug.cgi?id=51864 in https://reviews.llvm.org/D111519.

[xgupta]

Oops, commented on wrong review.

[jrtc27]

In D111519#3115513, @xgupta wrote:

Hello @luismarques,

can you please tell me how you have generated this assembly mentioned in the commit summary(.c file)?

define void @branch_and_tail_call(i1 %a) {
; RV32-LABEL: branch_and_tail_call:
; RV32:       # %bb.0:
; RV32-NEXT:    addi sp, sp, -16
; RV32-NEXT:    .cfi_def_cfa_offset 16
; RV32-NEXT:    sw ra, 12(sp)
; RV32-NEXT:    .cfi_offset ra, -4
; RV32-NEXT:    andi a0, a0, 1
; RV32-NEXT:    beqz a0, .LBB2_2
; RV32-NEXT:  # %bb.1: # %blue_pill
; RV32-NEXT:    lw ra, 12(sp)
; RV32-NEXT:    .cfi_restore ra
; RV32-NEXT:    addi sp, sp, 16
; RV32-NEXT:    .cfi_def_cfa_offset 0
; RV32-NEXT:    tail foo
; RV32-NEXT:  .LBB2_2: # %red_pill
; RV32-NEXT:    call bar
; RV32-NEXT:    lw ra, 12(sp)
; RV32-NEXT:    .cfi_restore ra
; RV32-NEXT:    addi sp, sp, 16
; RV32-NEXT:    .cfi_def_cfa_offset 0
; RV32-NEXT:    ret
}

This is clearly the branch_and_tail_call test case in frame-info.ll that had the ; FIXME: fix use of .cfi_restore with wrong CFAs.

For instance, without this patch the following program will not correctly unwind, and will get stuck (compile with clang, link with a gnu toolchain, test with qemu):

void three() {
    throw 7;
}

void two(void) {
    try {
        three();
    } catch(int &c) {
        throw 42;
    }
}

int main() {
    try {
        two();
    }
    catch(...) {
    }
    return 0;
}

When you say it get stuck, can you please tell me what steps you have run?

I'm going to assume as he said: "compile with clang, link with a gnu toolchain, test with qemu". Presumably the bogus DWARF leads it to get stuck in an unwind loop, with an early prologue meaning the call site is incorrectly (by correctly decoding the DWARF) determined to be a leaf, but RA is the call site itself, not the caller, so every iteration does nothing.

PS I want to revert this patch to fix https://bugs.llvm.org/show_bug.cgi?id=51864 in https://reviews.llvm.org/D111519.

I'm getting tired of saying this, but the underlying target-independent deficiency in LLVM needs fixing before you can think about reverting this.

[xgupta]

In D111519#3115534, @jrtc27 wrote:

In D111519#3115513, @xgupta wrote:

Hello @luismarques,

can you please tell me how you have generated this assembly mentioned in the commit summary(.c file)?

define void @branch_and_tail_call(i1 %a) {
; RV32-LABEL: branch_and_tail_call:
; RV32:       # %bb.0:
; RV32-NEXT:    addi sp, sp, -16
; RV32-NEXT:    .cfi_def_cfa_offset 16
; RV32-NEXT:    sw ra, 12(sp)
; RV32-NEXT:    .cfi_offset ra, -4
; RV32-NEXT:    andi a0, a0, 1
; RV32-NEXT:    beqz a0, .LBB2_2
; RV32-NEXT:  # %bb.1: # %blue_pill
; RV32-NEXT:    lw ra, 12(sp)
; RV32-NEXT:    .cfi_restore ra
; RV32-NEXT:    addi sp, sp, 16
; RV32-NEXT:    .cfi_def_cfa_offset 0
; RV32-NEXT:    tail foo
; RV32-NEXT:  .LBB2_2: # %red_pill
; RV32-NEXT:    call bar
; RV32-NEXT:    lw ra, 12(sp)
; RV32-NEXT:    .cfi_restore ra
; RV32-NEXT:    addi sp, sp, 16
; RV32-NEXT:    .cfi_def_cfa_offset 0
; RV32-NEXT:    ret
}

This is clearly the branch_and_tail_call test case in frame-info.ll that had the ; FIXME: fix use of .cfi_restore with wrong CFAs.

I am still looking for .cpp file so that I can test/diff it (clang riscv assembly) with gcc riscv generated assembly. Side question if someone knows why clang riscv emits .cfi_restore in epilogue (for frame-info.ll after applying this patch) while clang x86 does not. What is the use of .cf_restore in riscv that is not needed in x86? I have read .cfi_restore directive in https://sourceware.org/binutils/docs/as/CFI-directives.html but definition didn't give the answer.

[xgupta]

I have taken this example from https://reviews.llvm.org/D69723 to understand the problem with stack unwinding.

cat test.cpp

void three() {
    throw 7;
}

void two(void) {
    try {
        three();
    } catch(int &c) {
        throw 42;
    }
}

int main() {
    try {
        two();
    }
    catch(...) {
    }
    return 0;
}

If I see the output of the generated assembly in both GCC RISCV and Clang RISCV cases, differences can be seen in three directive lines sequence in epilogue.
clang RISCV epilogue:

.cfi_def_cfa sp, 48
 ld      ra, 40(sp)            
.cfi_restore ra
.cfi_restore s0

vs

GCC RISCV epilogue where 1= ra and 8= s0:

.cfi_restore 1
ld      s0,0(sp)
.cfi_restore 8
.cfi_def_cfa 2, 16

So I will assume these three lines need to be corrected to match GCC and fix the issue.

[jrtc27]

No. That is -O0 code and won't exhibit the issue, because the issue happens due to optimisation. Nor is main the function I believe to be the problem, since once you've unwound to main (which depends on the callee to have correct CFI, not the caller) there's no more unwinding to do, either implicitly (since the exception has been caught) or explicitly (since main itself performs no further actions that will request unwinding).

See https://godbolt.org/z/5xvTY9EKf. Observe that two has had its epilogue scheduled before its landing pad (corresponding to the call site that is the call to three):

.Ltmp10:
.Ltmp4:
        .loc    1 15 1                          # example.cpp:15:1
        ld      s0, 0(sp)                       # 8-byte Folded Reload
        # after this patch: .cfi_def_cfa sp, 16
        ld      ra, 8(sp)                       # 8-byte Folded Reload
        # after this patch: .cfi_restore ra
        # after this patch: .cfi_restore s0
        addi    sp, sp, 16
        # after this patch: .cfi_def_cfa_offset 0
        ret
.LBB1_2:
.Ltmp5:
.Ltmp11:
        .loc    1 15 1 is_stmt 0                # example.cpp:15:1
        sext.w  a1, a1
        addi    a2, zero, 1
        mv      s0, a0
        .loc    1 12 5 is_stmt 1                # example.cpp:12:5
        bne     a1, a2, .LBB1_6
        mv      a0, s0
        call    __cxa_begin_catch
...

This means that, if you have CFI in the epilogue as with this patch (annotated above with what I believe would be emitted), it is bogusly applied to the call to __cxa_throw (for throwing the 42 in the catch).

Now let's consider how that unwinds (during the search phase). The runtime and unwinder will unwind fine all the way back to the call to __cxa_throw (specifically the byte after; all the range checks are start < x <= end not the normal start <= x < end since jalr writes the next instruction to the link register) during the search phase. Once there, the runtime will ask the unwinder to unwind another frame, as there is no exception handler there for an int. But the unwinder, trusting the CFI which says ra has already been restored (and s0), will leave ra (and s0) untouched, so after one iteration of unwinding ra still points at the byte after two's call to __cxa_throw. So it sees if there's an exception handler there for an int, and the answer is still no. So it unwinds again, trusting the CFI, and again leaves ra untouched, which again still points at the byte after the call to __cxa_throw. And so on and so on, forever trying to unwind out of two to find an exception handler but stuck in it with no escape. It's possible I've got the details slightly wrong, but they aren't really the point, the general idea of how this breaks is, and why it is crucial that all C++ call sites have CFI that will unwind accurately if followed.

GCC's code for the same sequence is:

.LVL2:
.LEHE0:
        .loc 1 15 1
        ld      ra,8(sp)
        .cfi_remember_state
        .cfi_restore 1
        ld      s0,0(sp)
        .cfi_restore 8
        addi    sp,sp,16
        .cfi_def_cfa_offset 0
        jr      ra
.L7:
        .cfi_restore_state
        .loc 1 12 7
        li      a5,1
        bne     a1,a5,.L11
.LBB2:
        .loc 1 12 18 discriminator 1
        call    __cxa_begin_catch
...

This is almost the same CFI as what this patch produces (GCC interleaves the .cfi_restores with the corresponding loads but that doesn't really matter, so long as the stack slot and stack pointer aren't clobbered it's valid to defer a .cfi_restore) with the key difference that, because the epilogue has been scheduled before the landing pad, a .cfi_remember_state is emitted before any other CFI directives in the epilogue and a .cfi_restore_state is emitted as the first thing in the landing pad, restoring the state to the remembered state, namely that before the epilogue, and thus ensuring that the unwinder sees CFI that says ra is still stored on the stack (along with s0). That is the crucial part missing in LLVM, and the reason that we cannot emit CFI in epilogues.

(In case you're looking at main's assembly and notice that it too has its epilogue scheduled before its landing pad, yes that results in incorrect CFI for the landing pad, but no it doesn't matter in this case unless you're debugging, since all it does is call __cxa_begin_catch and __cxa_end_catch that do reference counting of the exception object behind the scenes, they don't need to unwind)

[xgupta]

.

[Miss_Grape]

In D111519#3130496, @jrtc27 wrote:

No. That is -O0 code and won't exhibit the issue, because the issue happens due to optimisation. Nor is main the function I believe to be the problem, since once you've unwound to main (which depends on the callee to have correct CFI, not the caller) there's no more unwinding to do, either implicitly (since the exception has been caught) or explicitly (since main itself performs no further actions that will request unwinding).

See https://godbolt.org/z/5xvTY9EKf. Observe that two has had its epilogue scheduled before its landing pad (corresponding to the call site that is the call to three):

.Ltmp10:
.Ltmp4:
        .loc    1 15 1                          # example.cpp:15:1
        ld      s0, 0(sp)                       # 8-byte Folded Reload
        # after this patch: .cfi_def_cfa sp, 16
        ld      ra, 8(sp)                       # 8-byte Folded Reload
        # after this patch: .cfi_restore ra
        # after this patch: .cfi_restore s0
        addi    sp, sp, 16
        # after this patch: .cfi_def_cfa_offset 0
        ret
.LBB1_2:
.Ltmp5:
.Ltmp11:
        .loc    1 15 1 is_stmt 0                # example.cpp:15:1
        sext.w  a1, a1
        addi    a2, zero, 1
        mv      s0, a0
        .loc    1 12 5 is_stmt 1                # example.cpp:12:5
        bne     a1, a2, .LBB1_6
        mv      a0, s0
        call    __cxa_begin_catch
...

This means that, if you have CFI in the epilogue as with this patch (annotated above with what I believe would be emitted), it is bogusly applied to the call to __cxa_throw (for throwing the 42 in the catch).

Now let's consider how that unwinds (during the search phase). The runtime and unwinder will unwind fine all the way back to the call to __cxa_throw (specifically the byte after; all the range checks are start < x <= end not the normal start <= x < end since jalr writes the next instruction to the link register) during the search phase. Once there, the runtime will ask the unwinder to unwind another frame, as there is no exception handler there for an int. But the unwinder, trusting the CFI which says ra has already been restored (and s0), will leave ra (and s0) untouched, so after one iteration of unwinding ra still points at the byte after two's call to __cxa_throw. So it sees if there's an exception handler there for an int, and the answer is still no. So it unwinds again, trusting the CFI, and again leaves ra untouched, which again still points at the byte after the call to __cxa_throw. And so on and so on, forever trying to unwind out of two to find an exception handler but stuck in it with no escape. It's possible I've got the details slightly wrong, but they aren't really the point, the general idea of how this breaks is, and why it is crucial that all C++ call sites have CFI that will unwind accurately if followed.

GCC's code for the same sequence is:

.LVL2:
.LEHE0:
        .loc 1 15 1
        ld      ra,8(sp)
        .cfi_remember_state
        .cfi_restore 1
        ld      s0,0(sp)
        .cfi_restore 8
        addi    sp,sp,16
        .cfi_def_cfa_offset 0
        jr      ra
.L7:
        .cfi_restore_state
        .loc 1 12 7
        li      a5,1
        bne     a1,a5,.L11
.LBB2:
        .loc 1 12 18 discriminator 1
        call    __cxa_begin_catch
...

This is almost the same CFI as what this patch produces (GCC interleaves the .cfi_restores with the corresponding loads but that doesn't really matter, so long as the stack slot and stack pointer aren't clobbered it's valid to defer a .cfi_restore) with the key difference that, because the epilogue has been scheduled before the landing pad, a .cfi_remember_state is emitted before any other CFI directives in the epilogue and a .cfi_restore_state is emitted as the first thing in the landing pad, restoring the state to the remembered state, namely that before the epilogue, and thus ensuring that the unwinder sees CFI that says ra is still stored on the stack (along with s0). That is the crucial part missing in LLVM, and the reason that we cannot emit CFI in epilogues.

(In case you're looking at main's assembly and notice that it too has its epilogue scheduled before its landing pad, yes that results in incorrect CFI for the landing pad, but no it doesn't matter in this case unless you're debugging, since all it does is call __cxa_begin_catch and __cxa_end_catch that do reference counting of the exception object behind the scenes, they don't need to unwind)

my command: riscv64-unknown-elf-g++ xxx.cpp -g -S xxx.s, but my assemble don't have .cfi_remember_state and .cfi_restore_state directives.

ToolChain down load from here:

I was wondering how your CFI directive above came about? Is there something wrong with my command?

[jrtc27]

I used the GCC 10.2.0 on godbolt.org. Basic block scheduling in newer GCCs may result in the directives being not needed for its code generation, I don't know; the necessary CFI is a function of what code is being generated, so if that changes then so does the CFI.

llvm/lib/Target/RISCV/RISCVFrameLowering.cpp

void RISCVFrameLowering::emitPrologue(MachineFunction &MF,
   }
 }
 
 void RISCVFrameLowering::emitEpilogue(MachineFunction &MF,
                                       MachineBasicBlock &MBB) const {
   const RISCVRegisterInfo *RI = STI.getRegisterInfo();
   MachineFrameInfo &MFI = MF.getFrameInfo();
   auto *RVFI = MF.getInfo<RISCVMachineFunctionInfo>();
+  const RISCVInstrInfo *TII = STI.getInstrInfo();
   Register FPReg = getFPReg(STI);
   Register SPReg = getSPReg(STI);
 
   // All calls are tail calls in GHC calling conv, and functions have no
   // prologue/epilogue.
   if (MF.getFunction().getCallingConv() == CallingConv::GHC)
     return;
 
void RISCVFrameLowering::emitEpilogue(MachineFunction &MF,
   uint64_t FirstSPAdjustAmount = getFirstSPAdjustAmount(MF);
   if (FirstSPAdjustAmount) {
     uint64_t SecondSPAdjustAmount = MFI.getStackSize() - FirstSPAdjustAmount;
     assert(SecondSPAdjustAmount > 0 &&
            "SecondSPAdjustAmount should be greater than zero");
 
     adjustReg(MBB, LastFrameDestroy, DL, SPReg, SPReg, SecondSPAdjustAmount,
               MachineInstr::FrameDestroy);
+
+    // Emit ".cfi_def_cfa_offset FirstSPAdjustAmount" if using an sp-based CFA
+    if (!hasFP(MF)) {
+      unsigned CFIIndex = MF.addFrameInst(
+          MCCFIInstruction::cfiDefCfaOffset(nullptr, -FirstSPAdjustAmount));
+      BuildMI(MBB, LastFrameDestroy, DL,
+              TII->get(TargetOpcode::CFI_INSTRUCTION))
+          .addCFIIndex(CFIIndex);
+    }
+  }
+
+  if (hasFP(MF)) {
+    // To find the instruction restoring FP from stack.
+    for (auto &I = LastFrameDestroy; I != MBBI; ++I) {
+      if (I->mayLoad() && I->getOperand(0).isReg()) {
+        Register DestReg = I->getOperand(0).getReg();
+        if (DestReg == FPReg) {
+          // If there is frame pointer, after restoring $fp registers, we
+          // need adjust CFA back to the correct sp-based offset.
+          // Emit ".cfi_def_cfa $sp, CFAOffset"
+          uint64_t CFAOffset =
+              FirstSPAdjustAmount
+                  ? FirstSPAdjustAmount + RVFI->getVarArgsSaveSize()
+                  : FPOffset;
+          unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::cfiDefCfa(
+              nullptr, RI->getDwarfRegNum(SPReg, true), CFAOffset));
+          BuildMI(MBB, std::next(I), DL,
+                  TII->get(TargetOpcode::CFI_INSTRUCTION))
+              .addCFIIndex(CFIIndex);
+          break;
+        }
+      }
+    }
+  }
+
+  // Add CFI directives for callee-saved registers.
+  // Iterate over list of callee-saved registers and emit .cfi_restore
+  // directives.
+  for (const auto &Entry : CSI) {
+    Register Reg = Entry.getReg();
+    unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createRestore(
+        nullptr, RI->getDwarfRegNum(Reg, true)));
+    BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
+        .addCFIIndex(CFIIndex);
   }
 
   if (FirstSPAdjustAmount)
     StackSize = FirstSPAdjustAmount;
 
   // Deallocate stack
   adjustReg(MBB, MBBI, DL, SPReg, SPReg, StackSize, MachineInstr::FrameDestroy);
 
   // Emit epilogue for shadow call stack.
   emitSCSEpilogue(MF, MBB, MBBI, DL);
+
+  // After restoring $sp, we need to adjust CFA to $(sp + 0)
+  // Emit ".cfi_def_cfa_offset 0"
+  unsigned CFIIndex =
+      MF.addFrameInst(MCCFIInstruction::cfiDefCfaOffset(nullptr, 0));
+  BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
+      .addCFIIndex(CFIIndex);
 }
 
 StackOffset
 RISCVFrameLowering::getFrameIndexReference(const MachineFunction &MF, int FI,
                                            Register &FrameReg) const {
   const MachineFrameInfo &MFI = MF.getFrameInfo();
   const TargetRegisterInfo *RI = MF.getSubtarget().getRegisterInfo();
   const auto *RVFI = MF.getInfo<RISCVMachineFunctionInfo>();

llvm/test/CodeGen/RISCV/addimm-mulimm.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ;; Test that (mul (add x, c1), c2) can be transformed to
 ;; (add (mul x, c2), c1*c2) if profitable.
 
 ; RUN: llc -mtriple=riscv32 -mattr=+m,+experimental-zba -verify-machineinstrs < %s \
 ; RUN:   | FileCheck -check-prefix=RV32IMB %s
 ; RUN: llc -mtriple=riscv64 -mattr=+m,+experimental-zba -verify-machineinstrs < %s \
 ; RUN:   | FileCheck -check-prefix=RV64IMB %s
 
 define i32 @add_mul_combine_accept_a1(i32 %x) {
 ; RV32IMB-LABEL: add_mul_combine_accept_a1:
 ; RV32IMB:       # %bb.0:
 ; RV32IMB-NEXT:    addi a1, zero, 29
 ; RV32IMB-NEXT:    mul a0, a0, a1
 ; RV32IMB-NEXT:    addi a0, a0, 1073
+; RV32IMB-NEXT:    .cfi_def_cfa_offset 0
 ; RV32IMB-NEXT:    ret
 ;
 ; RV64IMB-LABEL: add_mul_combine_accept_a1:
 ; RV64IMB:       # %bb.0:
 ; RV64IMB-NEXT:    addi a1, zero, 29
 ; RV64IMB-NEXT:    mulw a0, a0, a1
 ; RV64IMB-NEXT:    addiw a0, a0, 1073
+; RV64IMB-NEXT:    .cfi_def_cfa_offset 0
 ; RV64IMB-NEXT:    ret
   %tmp0 = add i32 %x, 37
   %tmp1 = mul i32 %tmp0, 29
   ret i32 %tmp1
 }
 
 define signext i32 @add_mul_combine_accept_a2(i32 signext %x) {
 ; RV32IMB-LABEL: add_mul_combine_accept_a2:
 ; RV32IMB:       # %bb.0:
 ; RV32IMB-NEXT:    addi a1, zero, 29
 ; RV32IMB-NEXT:    mul a0, a0, a1
 ; RV32IMB-NEXT:    addi a0, a0, 1073
+; RV32IMB-NEXT:    .cfi_def_cfa_offset 0
 ; RV32IMB-NEXT:    ret
 ;
 ; RV64IMB-LABEL: add_mul_combine_accept_a2:
 ; RV64IMB:       # %bb.0:
 ; RV64IMB-NEXT:    addi a1, zero, 29
 ; RV64IMB-NEXT:    mulw a0, a0, a1
 ; RV64IMB-NEXT:    addiw a0, a0, 1073
+; RV64IMB-NEXT:    .cfi_def_cfa_offset 0
 ; RV64IMB-NEXT:    ret
   %tmp0 = add i32 %x, 37
   %tmp1 = mul i32 %tmp0, 29
   ret i32 %tmp1
 }
 
 define i64 @add_mul_combine_accept_a3(i64 %x) {
 ; RV32IMB-LABEL: add_mul_combine_accept_a3:
 ; RV32IMB:       # %bb.0:
 ; RV32IMB-NEXT:    addi a2, zero, 29
 ; RV32IMB-NEXT:    mul a1, a1, a2
 ; RV32IMB-NEXT:    mulhu a3, a0, a2
 ; RV32IMB-NEXT:    add a1, a3, a1
 ; RV32IMB-NEXT:    mul a2, a0, a2
 ; RV32IMB-NEXT:    addi a0, a2, 1073
 ; RV32IMB-NEXT:    sltu a2, a0, a2
 ; RV32IMB-NEXT:    add a1, a1, a2
+; RV32IMB-NEXT:    .cfi_def_cfa_offset 0
 ; RV32IMB-NEXT:    ret
 ;
 ; RV64IMB-LABEL: add_mul_combine_accept_a3:
 ; RV64IMB:       # %bb.0:
 ; RV64IMB-NEXT:    addi a1, zero, 29
 ; RV64IMB-NEXT:    mul a0, a0, a1
 ; RV64IMB-NEXT:    addi a0, a0, 1073
+; RV64IMB-NEXT:    .cfi_def_cfa_offset 0
 ; RV64IMB-NEXT:    ret
   %tmp0 = add i64 %x, 37
   %tmp1 = mul i64 %tmp0, 29
   ret i64 %tmp1
 }
 
 define i32 @add_mul_combine_accept_b1(i32 %x) {
 ; RV32IMB-LABEL: add_mul_combine_accept_b1:
 ; RV32IMB:       # %bb.0:
 ; RV32IMB-NEXT:    addi a1, zero, 23
 ; RV32IMB-NEXT:    mul a0, a0, a1
 ; RV32IMB-NEXT:    lui a1, 50
 ; RV32IMB-NEXT:    addi a1, a1, 1119
 ; RV32IMB-NEXT:    add a0, a0, a1
+; RV32IMB-NEXT:    .cfi_def_cfa_offset 0
 ; RV32IMB-NEXT:    ret
 ;
 ; RV64IMB-LABEL: add_mul_combine_accept_b1:
 ; RV64IMB:       # %bb.0:
 ; RV64IMB-NEXT:    addi a1, zero, 23
 ; RV64IMB-NEXT:    mulw a0, a0, a1
 ; RV64IMB-NEXT:    lui a1, 50
 ; RV64IMB-NEXT:    addiw a1, a1, 1119
 ; RV64IMB-NEXT:    addw a0, a0, a1
+; RV64IMB-NEXT:    .cfi_def_cfa_offset 0
 ; RV64IMB-NEXT:    ret
   %tmp0 = add i32 %x, 8953
   %tmp1 = mul i32 %tmp0, 23
   ret i32 %tmp1
 }
 
 define signext i32 @add_mul_combine_accept_b2(i32 signext %x) {
 ; RV32IMB-LABEL: add_mul_combine_accept_b2:
 ; RV32IMB:       # %bb.0:
 ; RV32IMB-NEXT:    addi a1, zero, 23
 ; RV32IMB-NEXT:    mul a0, a0, a1
 ; RV32IMB-NEXT:    lui a1, 50
 ; RV32IMB-NEXT:    addi a1, a1, 1119
 ; RV32IMB-NEXT:    add a0, a0, a1
+; RV32IMB-NEXT:    .cfi_def_cfa_offset 0
 ; RV32IMB-NEXT:    ret
 ;
 ; RV64IMB-LABEL: add_mul_combine_accept_b2:
 ; RV64IMB:       # %bb.0:
 ; RV64IMB-NEXT:    addi a1, zero, 23
 ; RV64IMB-NEXT:    mulw a0, a0, a1
 ; RV64IMB-NEXT:    lui a1, 50
 ; RV64IMB-NEXT:    addiw a1, a1, 1119
 ; RV64IMB-NEXT:    addw a0, a0, a1
+; RV64IMB-NEXT:    .cfi_def_cfa_offset 0
 ; RV64IMB-NEXT:    ret
   %tmp0 = add i32 %x, 8953
   %tmp1 = mul i32 %tmp0, 23
   ret i32 %tmp1
 }
 
 define i64 @add_mul_combine_accept_b3(i64 %x) {
 ; RV32IMB-LABEL: add_mul_combine_accept_b3:
 ; RV32IMB:       # %bb.0:
 ; RV32IMB-NEXT:    addi a2, zero, 23
 ; RV32IMB-NEXT:    mul a1, a1, a2
 ; RV32IMB-NEXT:    mulhu a3, a0, a2
 ; RV32IMB-NEXT:    add a1, a3, a1
 ; RV32IMB-NEXT:    mul a2, a0, a2
 ; RV32IMB-NEXT:    lui a0, 50
 ; RV32IMB-NEXT:    addi a0, a0, 1119
 ; RV32IMB-NEXT:    add a0, a2, a0
 ; RV32IMB-NEXT:    sltu a2, a0, a2
 ; RV32IMB-NEXT:    add a1, a1, a2
+; RV32IMB-NEXT:    .cfi_def_cfa_offset 0
 ; RV32IMB-NEXT:    ret
 ;
 ; RV64IMB-LABEL: add_mul_combine_accept_b3:
 ; RV64IMB:       # %bb.0:
 ; RV64IMB-NEXT:    addi a1, zero, 23
 ; RV64IMB-NEXT:    mul a0, a0, a1
 ; RV64IMB-NEXT:    lui a1, 50
 ; RV64IMB-NEXT:    addiw a1, a1, 1119
 ; RV64IMB-NEXT:    add a0, a0, a1
+; RV64IMB-NEXT:    .cfi_def_cfa_offset 0
 ; RV64IMB-NEXT:    ret
   %tmp0 = add i64 %x, 8953
   %tmp1 = mul i64 %tmp0, 23
   ret i64 %tmp1
 }
 
 define i32 @add_mul_combine_reject_a1(i32 %x) {
 ; RV32IMB-LABEL: add_mul_combine_reject_a1:
 ; RV32IMB:       # %bb.0:
 ; RV32IMB-NEXT:    addi a0, a0, 1971
 ; RV32IMB-NEXT:    addi a1, zero, 29
 ; RV32IMB-NEXT:    mul a0, a0, a1
+; RV32IMB-NEXT:    .cfi_def_cfa_offset 0
 ; RV32IMB-NEXT:    ret
 ;
 ; RV64IMB-LABEL: add_mul_combine_reject_a1:
 ; RV64IMB:       # %bb.0:
 ; RV64IMB-NEXT:    addiw a0, a0, 1971
 ; RV64IMB-NEXT:    addi a1, zero, 29
 ; RV64IMB-NEXT:    mulw a0, a0, a1
+; RV64IMB-NEXT:    .cfi_def_cfa_offset 0
 ; RV64IMB-NEXT:    ret
   %tmp0 = add i32 %x, 1971
   %tmp1 = mul i32 %tmp0, 29
   ret i32 %tmp1
 }
 
 define signext i32 @add_mul_combine_reject_a2(i32 signext %x) {
 ; RV32IMB-LABEL: add_mul_combine_reject_a2:
 ; RV32IMB:       # %bb.0:
 ; RV32IMB-NEXT:    addi a0, a0, 1971
 ; RV32IMB-NEXT:    addi a1, zero, 29
 ; RV32IMB-NEXT:    mul a0, a0, a1
+; RV32IMB-NEXT:    .cfi_def_cfa_offset 0
 ; RV32IMB-NEXT:    ret
 ;
 ; RV64IMB-LABEL: add_mul_combine_reject_a2:
 ; RV64IMB:       # %bb.0:
 ; RV64IMB-NEXT:    addiw a0, a0, 1971
 ; RV64IMB-NEXT:    addi a1, zero, 29
 ; RV64IMB-NEXT:    mulw a0, a0, a1
+; RV64IMB-NEXT:    .cfi_def_cfa_offset 0
 ; RV64IMB-NEXT:    ret
   %tmp0 = add i32 %x, 1971
   %tmp1 = mul i32 %tmp0, 29
   ret i32 %tmp1
 }
 
 define i64 @add_mul_combine_reject_a3(i64 %x) {
 ; RV32IMB-LABEL: add_mul_combine_reject_a3:
 ; RV32IMB:       # %bb.0:
 ; RV32IMB-NEXT:    addi a2, zero, 29
 ; RV32IMB-NEXT:    mul a1, a1, a2
 ; RV32IMB-NEXT:    mulhu a3, a0, a2
 ; RV32IMB-NEXT:    add a1, a3, a1
 ; RV32IMB-NEXT:    mul a2, a0, a2
 ; RV32IMB-NEXT:    lui a0, 14
 ; RV32IMB-NEXT:    addi a0, a0, -185
 ; RV32IMB-NEXT:    add a0, a2, a0
 ; RV32IMB-NEXT:    sltu a2, a0, a2
 ; RV32IMB-NEXT:    add a1, a1, a2
+; RV32IMB-NEXT:    .cfi_def_cfa_offset 0
 ; RV32IMB-NEXT:    ret
 ;
 ; RV64IMB-LABEL: add_mul_combine_reject_a3:
 ; RV64IMB:       # %bb.0:
 ; RV64IMB-NEXT:    addi a0, a0, 1971
 ; RV64IMB-NEXT:    addi a1, zero, 29
 ; RV64IMB-NEXT:    mul a0, a0, a1
+; RV64IMB-NEXT:    .cfi_def_cfa_offset 0
 ; RV64IMB-NEXT:    ret
   %tmp0 = add i64 %x, 1971
   %tmp1 = mul i64 %tmp0, 29
   ret i64 %tmp1
 }
 
 define i32 @add_mul_combine_reject_c1(i32 %x) {
 ; RV32IMB-LABEL: add_mul_combine_reject_c1:
 ; RV32IMB:       # %bb.0:
 ; RV32IMB-NEXT:    addi a0, a0, 1000
 ; RV32IMB-NEXT:    sh3add a1, a0, a0
 ; RV32IMB-NEXT:    sh3add a0, a1, a0
+; RV32IMB-NEXT:    .cfi_def_cfa_offset 0
 ; RV32IMB-NEXT:    ret
 ;
 ; RV64IMB-LABEL: add_mul_combine_reject_c1:
 ; RV64IMB:       # %bb.0:
 ; RV64IMB-NEXT:    addi a0, a0, 1000
 ; RV64IMB-NEXT:    sh3add a1, a0, a0
 ; RV64IMB-NEXT:    sh3add a0, a1, a0
 ; RV64IMB-NEXT:    sext.w a0, a0
+; RV64IMB-NEXT:    .cfi_def_cfa_offset 0
 ; RV64IMB-NEXT:    ret
   %tmp0 = add i32 %x, 1000
   %tmp1 = mul i32 %tmp0, 73
   ret i32 %tmp1
 }
 
 define signext i32 @add_mul_combine_reject_c2(i32 signext %x) {
 ; RV32IMB-LABEL: add_mul_combine_reject_c2:
 ; RV32IMB:       # %bb.0:
 ; RV32IMB-NEXT:    addi a0, a0, 1000
 ; RV32IMB-NEXT:    sh3add a1, a0, a0
 ; RV32IMB-NEXT:    sh3add a0, a1, a0
+; RV32IMB-NEXT:    .cfi_def_cfa_offset 0
 ; RV32IMB-NEXT:    ret
 ;
 ; RV64IMB-LABEL: add_mul_combine_reject_c2:
 ; RV64IMB:       # %bb.0:
 ; RV64IMB-NEXT:    addi a0, a0, 1000
 ; RV64IMB-NEXT:    sh3add a1, a0, a0
 ; RV64IMB-NEXT:    sh3add a0, a1, a0
 ; RV64IMB-NEXT:    sext.w a0, a0
+; RV64IMB-NEXT:    .cfi_def_cfa_offset 0
 ; RV64IMB-NEXT:    ret
   %tmp0 = add i32 %x, 1000
   %tmp1 = mul i32 %tmp0, 73
   ret i32 %tmp1
 }
 
 define i64 @add_mul_combine_reject_c3(i64 %x) {
 ; RV32IMB-LABEL: add_mul_combine_reject_c3:
 ; RV32IMB:       # %bb.0:
 ; RV32IMB-NEXT:    addi a2, zero, 73
 ; RV32IMB-NEXT:    mul a1, a1, a2
 ; RV32IMB-NEXT:    mulhu a3, a0, a2
 ; RV32IMB-NEXT:    add a1, a3, a1
 ; RV32IMB-NEXT:    mul a2, a0, a2
 ; RV32IMB-NEXT:    lui a0, 18
 ; RV32IMB-NEXT:    addi a0, a0, -728
 ; RV32IMB-NEXT:    add a0, a2, a0
 ; RV32IMB-NEXT:    sltu a2, a0, a2
 ; RV32IMB-NEXT:    add a1, a1, a2
+; RV32IMB-NEXT:    .cfi_def_cfa_offset 0
 ; RV32IMB-NEXT:    ret
 ;
 ; RV64IMB-LABEL: add_mul_combine_reject_c3:
 ; RV64IMB:       # %bb.0:
 ; RV64IMB-NEXT:    addi a0, a0, 1000
 ; RV64IMB-NEXT:    sh3add a1, a0, a0
 ; RV64IMB-NEXT:    sh3add a0, a1, a0
+; RV64IMB-NEXT:    .cfi_def_cfa_offset 0
 ; RV64IMB-NEXT:    ret
   %tmp0 = add i64 %x, 1000
   %tmp1 = mul i64 %tmp0, 73
   ret i64 %tmp1
 }
 
 define i32 @add_mul_combine_reject_d1(i32 %x) {
 ; RV32IMB-LABEL: add_mul_combine_reject_d1:
 ; RV32IMB:       # %bb.0:
 ; RV32IMB-NEXT:    addi a0, a0, 1000
 ; RV32IMB-NEXT:    sh1add a0, a0, a0
 ; RV32IMB-NEXT:    slli a0, a0, 6
+; RV32IMB-NEXT:    .cfi_def_cfa_offset 0
 ; RV32IMB-NEXT:    ret
 ;
 ; RV64IMB-LABEL: add_mul_combine_reject_d1:
 ; RV64IMB:       # %bb.0:
 ; RV64IMB-NEXT:    addi a0, a0, 1000
 ; RV64IMB-NEXT:    sh1add a0, a0, a0
 ; RV64IMB-NEXT:    slliw a0, a0, 6
+; RV64IMB-NEXT:    .cfi_def_cfa_offset 0
 ; RV64IMB-NEXT:    ret
   %tmp0 = add i32 %x, 1000
   %tmp1 = mul i32 %tmp0, 192
   ret i32 %tmp1
 }
 
 define signext i32 @add_mul_combine_reject_d2(i32 signext %x) {
 ; RV32IMB-LABEL: add_mul_combine_reject_d2:
 ; RV32IMB:       # %bb.0:
 ; RV32IMB-NEXT:    addi a0, a0, 1000
 ; RV32IMB-NEXT:    sh1add a0, a0, a0
 ; RV32IMB-NEXT:    slli a0, a0, 6
+; RV32IMB-NEXT:    .cfi_def_cfa_offset 0
 ; RV32IMB-NEXT:    ret
 ;
 ; RV64IMB-LABEL: add_mul_combine_reject_d2:
 ; RV64IMB:       # %bb.0:
 ; RV64IMB-NEXT:    addi a0, a0, 1000
 ; RV64IMB-NEXT:    sh1add a0, a0, a0
 ; RV64IMB-NEXT:    slliw a0, a0, 6
+; RV64IMB-NEXT:    .cfi_def_cfa_offset 0
 ; RV64IMB-NEXT:    ret
   %tmp0 = add i32 %x, 1000
   %tmp1 = mul i32 %tmp0, 192
   ret i32 %tmp1
 }
 
 define i64 @add_mul_combine_reject_d3(i64 %x) {
 ; RV32IMB-LABEL: add_mul_combine_reject_d3:
 ; RV32IMB:       # %bb.0:
 ; RV32IMB-NEXT:    addi a2, zero, 192
 ; RV32IMB-NEXT:    mulhu a2, a0, a2
 ; RV32IMB-NEXT:    sh1add a1, a1, a1
 ; RV32IMB-NEXT:    slli a1, a1, 6
 ; RV32IMB-NEXT:    add a1, a2, a1
 ; RV32IMB-NEXT:    sh1add a0, a0, a0
 ; RV32IMB-NEXT:    slli a2, a0, 6
 ; RV32IMB-NEXT:    lui a0, 47
 ; RV32IMB-NEXT:    addi a0, a0, -512
 ; RV32IMB-NEXT:    add a0, a2, a0
 ; RV32IMB-NEXT:    sltu a2, a0, a2
 ; RV32IMB-NEXT:    add a1, a1, a2
+; RV32IMB-NEXT:    .cfi_def_cfa_offset 0
 ; RV32IMB-NEXT:    ret
 ;
 ; RV64IMB-LABEL: add_mul_combine_reject_d3:
 ; RV64IMB:       # %bb.0:
 ; RV64IMB-NEXT:    addi a0, a0, 1000
 ; RV64IMB-NEXT:    sh1add a0, a0, a0
 ; RV64IMB-NEXT:    slli a0, a0, 6
+; RV64IMB-NEXT:    .cfi_def_cfa_offset 0
 ; RV64IMB-NEXT:    ret
   %tmp0 = add i64 %x, 1000
   %tmp1 = mul i64 %tmp0, 192
   ret i64 %tmp1
 }
 
 define i32 @add_mul_combine_reject_e1(i32 %x) {
 ; RV32IMB-LABEL: add_mul_combine_reject_e1:
 ; RV32IMB:       # %bb.0:
 ; RV32IMB-NEXT:    addi a0, a0, 1971
 ; RV32IMB-NEXT:    addi a1, zero, 29
 ; RV32IMB-NEXT:    mul a0, a0, a1
+; RV32IMB-NEXT:    .cfi_def_cfa_offset 0
 ; RV32IMB-NEXT:    ret
 ;
 ; RV64IMB-LABEL: add_mul_combine_reject_e1:
 ; RV64IMB:       # %bb.0:
 ; RV64IMB-NEXT:    addiw a0, a0, 1971
 ; RV64IMB-NEXT:    addi a1, zero, 29
 ; RV64IMB-NEXT:    mulw a0, a0, a1
+; RV64IMB-NEXT:    .cfi_def_cfa_offset 0
 ; RV64IMB-NEXT:    ret
   %tmp0 = mul i32 %x, 29
   %tmp1 = add i32 %tmp0, 57159
   ret i32 %tmp1
 }
 
 define signext i32 @add_mul_combine_reject_e2(i32 signext %x) {
 ; RV32IMB-LABEL: add_mul_combine_reject_e2:
 ; RV32IMB:       # %bb.0:
 ; RV32IMB-NEXT:    addi a0, a0, 1971
 ; RV32IMB-NEXT:    addi a1, zero, 29
 ; RV32IMB-NEXT:    mul a0, a0, a1
+; RV32IMB-NEXT:    .cfi_def_cfa_offset 0
 ; RV32IMB-NEXT:    ret
 ;
 ; RV64IMB-LABEL: add_mul_combine_reject_e2:
 ; RV64IMB:       # %bb.0:
 ; RV64IMB-NEXT:    addiw a0, a0, 1971
 ; RV64IMB-NEXT:    addi a1, zero, 29
 ; RV64IMB-NEXT:    mulw a0, a0, a1
+; RV64IMB-NEXT:    .cfi_def_cfa_offset 0
 ; RV64IMB-NEXT:    ret
   %tmp0 = mul i32 %x, 29
   %tmp1 = add i32 %tmp0, 57159
   ret i32 %tmp1
 }
 
 define i64 @add_mul_combine_reject_e3(i64 %x) {
 ; RV32IMB-LABEL: add_mul_combine_reject_e3:
 ; RV32IMB:       # %bb.0:
 ; RV32IMB-NEXT:    addi a2, zero, 29
 ; RV32IMB-NEXT:    mul a1, a1, a2
 ; RV32IMB-NEXT:    mulhu a3, a0, a2
 ; RV32IMB-NEXT:    add a1, a3, a1
 ; RV32IMB-NEXT:    mul a2, a0, a2
 ; RV32IMB-NEXT:    lui a0, 14
 ; RV32IMB-NEXT:    addi a0, a0, -185
 ; RV32IMB-NEXT:    add a0, a2, a0
 ; RV32IMB-NEXT:    sltu a2, a0, a2
 ; RV32IMB-NEXT:    add a1, a1, a2
+; RV32IMB-NEXT:    .cfi_def_cfa_offset 0
 ; RV32IMB-NEXT:    ret
 ;
 ; RV64IMB-LABEL: add_mul_combine_reject_e3:
 ; RV64IMB:       # %bb.0:
 ; RV64IMB-NEXT:    addi a0, a0, 1971
 ; RV64IMB-NEXT:    addi a1, zero, 29
 ; RV64IMB-NEXT:    mul a0, a0, a1
+; RV64IMB-NEXT:    .cfi_def_cfa_offset 0
 ; RV64IMB-NEXT:    ret
   %tmp0 = mul i64 %x, 29
   %tmp1 = add i64 %tmp0, 57159
   ret i64 %tmp1
 }
 
 define i32 @add_mul_combine_reject_f1(i32 %x) {
 ; RV32IMB-LABEL: add_mul_combine_reject_f1:
 ; RV32IMB:       # %bb.0:
 ; RV32IMB-NEXT:    addi a0, a0, 1972
 ; RV32IMB-NEXT:    addi a1, zero, 29
 ; RV32IMB-NEXT:    mul a0, a0, a1
 ; RV32IMB-NEXT:    addi a0, a0, 11
+; RV32IMB-NEXT:    .cfi_def_cfa_offset 0
 ; RV32IMB-NEXT:    ret
 ;
 ; RV64IMB-LABEL: add_mul_combine_reject_f1:
 ; RV64IMB:       # %bb.0:
 ; RV64IMB-NEXT:    addiw a0, a0, 1972
 ; RV64IMB-NEXT:    addi a1, zero, 29
 ; RV64IMB-NEXT:    mulw a0, a0, a1
 ; RV64IMB-NEXT:    addiw a0, a0, 11
+; RV64IMB-NEXT:    .cfi_def_cfa_offset 0
 ; RV64IMB-NEXT:    ret
   %tmp0 = mul i32 %x, 29
   %tmp1 = add i32 %tmp0, 57199
   ret i32 %tmp1
 }
 
 define signext i32 @add_mul_combine_reject_f2(i32 signext %x) {
 ; RV32IMB-LABEL: add_mul_combine_reject_f2:
 ; RV32IMB:       # %bb.0:
 ; RV32IMB-NEXT:    addi a0, a0, 1972
 ; RV32IMB-NEXT:    addi a1, zero, 29
 ; RV32IMB-NEXT:    mul a0, a0, a1
 ; RV32IMB-NEXT:    addi a0, a0, 11
+; RV32IMB-NEXT:    .cfi_def_cfa_offset 0
 ; RV32IMB-NEXT:    ret
 ;
 ; RV64IMB-LABEL: add_mul_combine_reject_f2:
 ; RV64IMB:       # %bb.0:
 ; RV64IMB-NEXT:    addiw a0, a0, 1972
 ; RV64IMB-NEXT:    addi a1, zero, 29
 ; RV64IMB-NEXT:    mulw a0, a0, a1
 ; RV64IMB-NEXT:    addiw a0, a0, 11
+; RV64IMB-NEXT:    .cfi_def_cfa_offset 0
 ; RV64IMB-NEXT:    ret
   %tmp0 = mul i32 %x, 29
   %tmp1 = add i32 %tmp0, 57199
   ret i32 %tmp1
 }
 
 define i64 @add_mul_combine_reject_f3(i64 %x) {
 ; RV32IMB-LABEL: add_mul_combine_reject_f3:
 ; RV32IMB:       # %bb.0:
 ; RV32IMB-NEXT:    addi a2, zero, 29
 ; RV32IMB-NEXT:    mul a1, a1, a2
 ; RV32IMB-NEXT:    mulhu a3, a0, a2
 ; RV32IMB-NEXT:    add a1, a3, a1
 ; RV32IMB-NEXT:    mul a2, a0, a2
 ; RV32IMB-NEXT:    lui a0, 14
 ; RV32IMB-NEXT:    addi a0, a0, -145
 ; RV32IMB-NEXT:    add a0, a2, a0
 ; RV32IMB-NEXT:    sltu a2, a0, a2
 ; RV32IMB-NEXT:    add a1, a1, a2
+; RV32IMB-NEXT:    .cfi_def_cfa_offset 0
 ; RV32IMB-NEXT:    ret
 ;
 ; RV64IMB-LABEL: add_mul_combine_reject_f3:
 ; RV64IMB:       # %bb.0:
 ; RV64IMB-NEXT:    addi a0, a0, 1972
 ; RV64IMB-NEXT:    addi a1, zero, 29
 ; RV64IMB-NEXT:    mul a0, a0, a1
 ; RV64IMB-NEXT:    addi a0, a0, 11
+; RV64IMB-NEXT:    .cfi_def_cfa_offset 0
 ; RV64IMB-NEXT:    ret
   %tmp0 = mul i64 %x, 29
   %tmp1 = add i64 %tmp0, 57199
   ret i64 %tmp1
 }
 
 define i32 @add_mul_combine_reject_g1(i32 %x) {
 ; RV32IMB-LABEL: add_mul_combine_reject_g1:
 ; RV32IMB:       # %bb.0:
 ; RV32IMB-NEXT:    addi a0, a0, 100
 ; RV32IMB-NEXT:    sh3add a1, a0, a0
 ; RV32IMB-NEXT:    sh3add a0, a1, a0
 ; RV32IMB-NEXT:    addi a0, a0, 10
+; RV32IMB-NEXT:    .cfi_def_cfa_offset 0
 ; RV32IMB-NEXT:    ret
 ;
 ; RV64IMB-LABEL: add_mul_combine_reject_g1:
 ; RV64IMB:       # %bb.0:
 ; RV64IMB-NEXT:    addi a0, a0, 100
 ; RV64IMB-NEXT:    sh3add a1, a0, a0
 ; RV64IMB-NEXT:    sh3add a0, a1, a0
 ; RV64IMB-NEXT:    addiw a0, a0, 10
+; RV64IMB-NEXT:    .cfi_def_cfa_offset 0
 ; RV64IMB-NEXT:    ret
   %tmp0 = mul i32 %x, 73
   %tmp1 = add i32 %tmp0, 7310
   ret i32 %tmp1
 }
 
 define signext i32 @add_mul_combine_reject_g2(i32 signext %x) {
 ; RV32IMB-LABEL: add_mul_combine_reject_g2:
 ; RV32IMB:       # %bb.0:
 ; RV32IMB-NEXT:    addi a0, a0, 100
 ; RV32IMB-NEXT:    sh3add a1, a0, a0
 ; RV32IMB-NEXT:    sh3add a0, a1, a0
 ; RV32IMB-NEXT:    addi a0, a0, 10
+; RV32IMB-NEXT:    .cfi_def_cfa_offset 0
 ; RV32IMB-NEXT:    ret
 ;
 ; RV64IMB-LABEL: add_mul_combine_reject_g2:
 ; RV64IMB:       # %bb.0:
 ; RV64IMB-NEXT:    addi a0, a0, 100
 ; RV64IMB-NEXT:    sh3add a1, a0, a0
 ; RV64IMB-NEXT:    sh3add a0, a1, a0
 ; RV64IMB-NEXT:    addiw a0, a0, 10
+; RV64IMB-NEXT:    .cfi_def_cfa_offset 0
 ; RV64IMB-NEXT:    ret
   %tmp0 = mul i32 %x, 73
   %tmp1 = add i32 %tmp0, 7310
   ret i32 %tmp1
 }
 
 define i64 @add_mul_combine_reject_g3(i64 %x) {
 ; RV32IMB-LABEL: add_mul_combine_reject_g3:
 ; RV32IMB:       # %bb.0:
 ; RV32IMB-NEXT:    addi a2, zero, 73
 ; RV32IMB-NEXT:    mul a1, a1, a2
 ; RV32IMB-NEXT:    mulhu a3, a0, a2
 ; RV32IMB-NEXT:    add a1, a3, a1
 ; RV32IMB-NEXT:    mul a2, a0, a2
 ; RV32IMB-NEXT:    lui a0, 2
 ; RV32IMB-NEXT:    addi a0, a0, -882
 ; RV32IMB-NEXT:    add a0, a2, a0
 ; RV32IMB-NEXT:    sltu a2, a0, a2
 ; RV32IMB-NEXT:    add a1, a1, a2
+; RV32IMB-NEXT:    .cfi_def_cfa_offset 0
 ; RV32IMB-NEXT:    ret
 ;
 ; RV64IMB-LABEL: add_mul_combine_reject_g3:
 ; RV64IMB:       # %bb.0:
 ; RV64IMB-NEXT:    addi a0, a0, 100
 ; RV64IMB-NEXT:    sh3add a1, a0, a0
 ; RV64IMB-NEXT:    sh3add a0, a1, a0
 ; RV64IMB-NEXT:    addi a0, a0, 10
+; RV64IMB-NEXT:    .cfi_def_cfa_offset 0
 ; RV64IMB-NEXT:    ret
   %tmp0 = mul i64 %x, 73
   %tmp1 = add i64 %tmp0, 7310
   ret i64 %tmp1
 }
 
 ; This test previously infinite looped in DAG combine.
 define i64 @add_mul_combine_infinite_loop(i64 %x) {
 ; RV32IMB-LABEL: add_mul_combine_infinite_loop:
 ; RV32IMB:       # %bb.0:
 ; RV32IMB-NEXT:    addi a2, zero, 24
 ; RV32IMB-NEXT:    mulhu a2, a0, a2
 ; RV32IMB-NEXT:    sh1add a1, a1, a1
 ; RV32IMB-NEXT:    sh3add a1, a1, a2
 ; RV32IMB-NEXT:    sh1add a0, a0, a0
 ; RV32IMB-NEXT:    slli a2, a0, 3
 ; RV32IMB-NEXT:    addi a0, a2, 1024
 ; RV32IMB-NEXT:    addi a0, a0, 1024
 ; RV32IMB-NEXT:    sltu a2, a0, a2
 ; RV32IMB-NEXT:    add a1, a1, a2
+; RV32IMB-NEXT:    .cfi_def_cfa_offset 0
 ; RV32IMB-NEXT:    ret
 ;
 ; RV64IMB-LABEL: add_mul_combine_infinite_loop:
 ; RV64IMB:       # %bb.0:
 ; RV64IMB-NEXT:    sh1add a0, a0, a0
 ; RV64IMB-NEXT:    lui a1, 1
 ; RV64IMB-NEXT:    addiw a1, a1, -2048
 ; RV64IMB-NEXT:    sh3add a0, a0, a1
+; RV64IMB-NEXT:    .cfi_def_cfa_offset 0
 ; RV64IMB-NEXT:    ret
   %tmp0 = mul i64 %x, 24
   %tmp1 = add i64 %tmp0, 2048
   ret i64 %tmp1
 }
 
 define i32 @mul3000_add8990_a(i32 %x) {
 ; RV32IMB-LABEL: mul3000_add8990_a:
 ; RV32IMB:       # %bb.0:
 ; RV32IMB-NEXT:    lui a1, 1
 ; RV32IMB-NEXT:    addi a1, a1, -1096
 ; RV32IMB-NEXT:    mul a0, a0, a1
 ; RV32IMB-NEXT:    lui a1, 2
 ; RV32IMB-NEXT:    addi a1, a1, 798
 ; RV32IMB-NEXT:    add a0, a0, a1
+; RV32IMB-NEXT:    .cfi_def_cfa_offset 0
 ; RV32IMB-NEXT:    ret
 ;
 ; RV64IMB-LABEL: mul3000_add8990_a:
 ; RV64IMB:       # %bb.0:
 ; RV64IMB-NEXT:    lui a1, 1
 ; RV64IMB-NEXT:    addiw a1, a1, -1096
 ; RV64IMB-NEXT:    mulw a0, a0, a1
 ; RV64IMB-NEXT:    lui a1, 2
 ; RV64IMB-NEXT:    addiw a1, a1, 798
 ; RV64IMB-NEXT:    addw a0, a0, a1
+; RV64IMB-NEXT:    .cfi_def_cfa_offset 0
 ; RV64IMB-NEXT:    ret
   %tmp0 = mul i32 %x, 3000
   %tmp1 = add i32 %tmp0, 8990
   ret i32 %tmp1
 }
 
 define signext i32 @mul3000_add8990_b(i32 signext %x) {
 ; RV32IMB-LABEL: mul3000_add8990_b:
 ; RV32IMB:       # %bb.0:
 ; RV32IMB-NEXT:    lui a1, 1
 ; RV32IMB-NEXT:    addi a1, a1, -1096
 ; RV32IMB-NEXT:    mul a0, a0, a1
 ; RV32IMB-NEXT:    lui a1, 2
 ; RV32IMB-NEXT:    addi a1, a1, 798
 ; RV32IMB-NEXT:    add a0, a0, a1
+; RV32IMB-NEXT:    .cfi_def_cfa_offset 0
 ; RV32IMB-NEXT:    ret
 ;
 ; RV64IMB-LABEL: mul3000_add8990_b:
 ; RV64IMB:       # %bb.0:
 ; RV64IMB-NEXT:    lui a1, 1
 ; RV64IMB-NEXT:    addiw a1, a1, -1096
 ; RV64IMB-NEXT:    mulw a0, a0, a1
 ; RV64IMB-NEXT:    lui a1, 2
 ; RV64IMB-NEXT:    addiw a1, a1, 798
 ; RV64IMB-NEXT:    addw a0, a0, a1
+; RV64IMB-NEXT:    .cfi_def_cfa_offset 0
 ; RV64IMB-NEXT:    ret
   %tmp0 = mul i32 %x, 3000
   %tmp1 = add i32 %tmp0, 8990
   ret i32 %tmp1
 }
 
 define i64 @mul3000_add8990_c(i64 %x) {
 ; RV32IMB-LABEL: mul3000_add8990_c:
 ; RV32IMB:       # %bb.0:
 ; RV32IMB-NEXT:    lui a2, 1
 ; RV32IMB-NEXT:    addi a2, a2, -1096
 ; RV32IMB-NEXT:    mul a1, a1, a2
 ; RV32IMB-NEXT:    mulhu a3, a0, a2
 ; RV32IMB-NEXT:    add a1, a3, a1
 ; RV32IMB-NEXT:    mul a2, a0, a2
 ; RV32IMB-NEXT:    lui a0, 2
 ; RV32IMB-NEXT:    addi a0, a0, 798
 ; RV32IMB-NEXT:    add a0, a2, a0
 ; RV32IMB-NEXT:    sltu a2, a0, a2
 ; RV32IMB-NEXT:    add a1, a1, a2
+; RV32IMB-NEXT:    .cfi_def_cfa_offset 0
 ; RV32IMB-NEXT:    ret
 ;
 ; RV64IMB-LABEL: mul3000_add8990_c:
 ; RV64IMB:       # %bb.0:
 ; RV64IMB-NEXT:    lui a1, 1
 ; RV64IMB-NEXT:    addiw a1, a1, -1096
 ; RV64IMB-NEXT:    mul a0, a0, a1
 ; RV64IMB-NEXT:    lui a1, 2
 ; RV64IMB-NEXT:    addiw a1, a1, 798
 ; RV64IMB-NEXT:    add a0, a0, a1
+; RV64IMB-NEXT:    .cfi_def_cfa_offset 0
 ; RV64IMB-NEXT:    ret
   %tmp0 = mul i64 %x, 3000
   %tmp1 = add i64 %tmp0, 8990
   ret i64 %tmp1
 }
 
 define i32 @mul3000_sub8990_a(i32 %x) {
 ; RV32IMB-LABEL: mul3000_sub8990_a:
 ; RV32IMB:       # %bb.0:
 ; RV32IMB-NEXT:    lui a1, 1
 ; RV32IMB-NEXT:    addi a1, a1, -1096
 ; RV32IMB-NEXT:    mul a0, a0, a1
 ; RV32IMB-NEXT:    lui a1, 1048574
 ; RV32IMB-NEXT:    addi a1, a1, -798
 ; RV32IMB-NEXT:    add a0, a0, a1
+; RV32IMB-NEXT:    .cfi_def_cfa_offset 0
 ; RV32IMB-NEXT:    ret
 ;
 ; RV64IMB-LABEL: mul3000_sub8990_a:
 ; RV64IMB:       # %bb.0:
 ; RV64IMB-NEXT:    lui a1, 1
 ; RV64IMB-NEXT:    addiw a1, a1, -1096
 ; RV64IMB-NEXT:    mulw a0, a0, a1
 ; RV64IMB-NEXT:    lui a1, 1048574
 ; RV64IMB-NEXT:    addiw a1, a1, -798
 ; RV64IMB-NEXT:    addw a0, a0, a1
+; RV64IMB-NEXT:    .cfi_def_cfa_offset 0
 ; RV64IMB-NEXT:    ret
   %tmp0 = mul i32 %x, 3000
   %tmp1 = add i32 %tmp0, -8990
   ret i32 %tmp1
 }
 
 define signext i32 @mul3000_sub8990_b(i32 signext %x) {
 ; RV32IMB-LABEL: mul3000_sub8990_b:
 ; RV32IMB:       # %bb.0:
 ; RV32IMB-NEXT:    lui a1, 1
 ; RV32IMB-NEXT:    addi a1, a1, -1096
 ; RV32IMB-NEXT:    mul a0, a0, a1
 ; RV32IMB-NEXT:    lui a1, 1048574
 ; RV32IMB-NEXT:    addi a1, a1, -798
 ; RV32IMB-NEXT:    add a0, a0, a1
+; RV32IMB-NEXT:    .cfi_def_cfa_offset 0
 ; RV32IMB-NEXT:    ret
 ;
 ; RV64IMB-LABEL: mul3000_sub8990_b:
 ; RV64IMB:       # %bb.0:
 ; RV64IMB-NEXT:    lui a1, 1
 ; RV64IMB-NEXT:    addiw a1, a1, -1096
 ; RV64IMB-NEXT:    mulw a0, a0, a1
 ; RV64IMB-NEXT:    lui a1, 1048574
 ; RV64IMB-NEXT:    addiw a1, a1, -798
 ; RV64IMB-NEXT:    addw a0, a0, a1
+; RV64IMB-NEXT:    .cfi_def_cfa_offset 0
 ; RV64IMB-NEXT:    ret
   %tmp0 = mul i32 %x, 3000
   %tmp1 = add i32 %tmp0, -8990
   ret i32 %tmp1
 }
 
 define i64 @mul3000_sub8990_c(i64 %x) {
 ; RV32IMB-LABEL: mul3000_sub8990_c:
 ; RV32IMB:       # %bb.0:
 ; RV32IMB-NEXT:    lui a2, 1
 ; RV32IMB-NEXT:    addi a2, a2, -1096
 ; RV32IMB-NEXT:    mul a1, a1, a2
 ; RV32IMB-NEXT:    mulhu a3, a0, a2
 ; RV32IMB-NEXT:    add a1, a3, a1
 ; RV32IMB-NEXT:    mul a2, a0, a2
 ; RV32IMB-NEXT:    lui a0, 1048574
 ; RV32IMB-NEXT:    addi a0, a0, -798
 ; RV32IMB-NEXT:    add a0, a2, a0
 ; RV32IMB-NEXT:    sltu a2, a0, a2
 ; RV32IMB-NEXT:    add a1, a1, a2
 ; RV32IMB-NEXT:    addi a1, a1, -1
+; RV32IMB-NEXT:    .cfi_def_cfa_offset 0
 ; RV32IMB-NEXT:    ret
 ;
 ; RV64IMB-LABEL: mul3000_sub8990_c:
 ; RV64IMB:       # %bb.0:
 ; RV64IMB-NEXT:    lui a1, 1
 ; RV64IMB-NEXT:    addiw a1, a1, -1096
 ; RV64IMB-NEXT:    mul a0, a0, a1
 ; RV64IMB-NEXT:    lui a1, 1048574
 ; RV64IMB-NEXT:    addiw a1, a1, -798
 ; RV64IMB-NEXT:    add a0, a0, a1
+; RV64IMB-NEXT:    .cfi_def_cfa_offset 0
 ; RV64IMB-NEXT:    ret
   %tmp0 = mul i64 %x, 3000
   %tmp1 = add i64 %tmp0, -8990
   ret i64 %tmp1
 }
 
 define i32 @mulneg3000_add8990_a(i32 %x) {
 ; RV32IMB-LABEL: mulneg3000_add8990_a:
 ; RV32IMB:       # %bb.0:
 ; RV32IMB-NEXT:    lui a1, 1048575
 ; RV32IMB-NEXT:    addi a1, a1, 1096
 ; RV32IMB-NEXT:    mul a0, a0, a1
 ; RV32IMB-NEXT:    lui a1, 2
 ; RV32IMB-NEXT:    addi a1, a1, 798
 ; RV32IMB-NEXT:    add a0, a0, a1
+; RV32IMB-NEXT:    .cfi_def_cfa_offset 0
 ; RV32IMB-NEXT:    ret
 ;
 ; RV64IMB-LABEL: mulneg3000_add8990_a:
 ; RV64IMB:       # %bb.0:
 ; RV64IMB-NEXT:    lui a1, 1048575
 ; RV64IMB-NEXT:    addiw a1, a1, 1096
 ; RV64IMB-NEXT:    mulw a0, a0, a1
 ; RV64IMB-NEXT:    lui a1, 2
 ; RV64IMB-NEXT:    addiw a1, a1, 798
 ; RV64IMB-NEXT:    addw a0, a0, a1
+; RV64IMB-NEXT:    .cfi_def_cfa_offset 0
 ; RV64IMB-NEXT:    ret
   %tmp0 = mul i32 %x, -3000
   %tmp1 = add i32 %tmp0, 8990
   ret i32 %tmp1
 }
 
 define signext i32 @mulneg3000_add8990_b(i32 signext %x) {
 ; RV32IMB-LABEL: mulneg3000_add8990_b:
 ; RV32IMB:       # %bb.0:
 ; RV32IMB-NEXT:    lui a1, 1048575
 ; RV32IMB-NEXT:    addi a1, a1, 1096
 ; RV32IMB-NEXT:    mul a0, a0, a1
 ; RV32IMB-NEXT:    lui a1, 2
 ; RV32IMB-NEXT:    addi a1, a1, 798
 ; RV32IMB-NEXT:    add a0, a0, a1
+; RV32IMB-NEXT:    .cfi_def_cfa_offset 0
 ; RV32IMB-NEXT:    ret
 ;
 ; RV64IMB-LABEL: mulneg3000_add8990_b:
 ; RV64IMB:       # %bb.0:
 ; RV64IMB-NEXT:    lui a1, 1048575
 ; RV64IMB-NEXT:    addiw a1, a1, 1096
 ; RV64IMB-NEXT:    mulw a0, a0, a1
 ; RV64IMB-NEXT:    lui a1, 2
 ; RV64IMB-NEXT:    addiw a1, a1, 798
 ; RV64IMB-NEXT:    addw a0, a0, a1
+; RV64IMB-NEXT:    .cfi_def_cfa_offset 0
 ; RV64IMB-NEXT:    ret
   %tmp0 = mul i32 %x, -3000
   %tmp1 = add i32 %tmp0, 8990
   ret i32 %tmp1
 }
 
 define i64 @mulneg3000_add8990_c(i64 %x) {
 ; RV32IMB-LABEL: mulneg3000_add8990_c:
 ; RV32IMB:       # %bb.0:
 ; RV32IMB-NEXT:    lui a2, 1048575
 ; RV32IMB-NEXT:    addi a2, a2, 1096
 ; RV32IMB-NEXT:    mul a1, a1, a2
 ; RV32IMB-NEXT:    mulhu a3, a0, a2
 ; RV32IMB-NEXT:    sub a3, a3, a0
 ; RV32IMB-NEXT:    add a1, a3, a1
 ; RV32IMB-NEXT:    mul a2, a0, a2
 ; RV32IMB-NEXT:    lui a0, 2
 ; RV32IMB-NEXT:    addi a0, a0, 798
 ; RV32IMB-NEXT:    add a0, a2, a0
 ; RV32IMB-NEXT:    sltu a2, a0, a2
 ; RV32IMB-NEXT:    add a1, a1, a2
+; RV32IMB-NEXT:    .cfi_def_cfa_offset 0
 ; RV32IMB-NEXT:    ret
 ;
 ; RV64IMB-LABEL: mulneg3000_add8990_c:
 ; RV64IMB:       # %bb.0:
 ; RV64IMB-NEXT:    lui a1, 1048575
 ; RV64IMB-NEXT:    addiw a1, a1, 1096
 ; RV64IMB-NEXT:    mul a0, a0, a1
 ; RV64IMB-NEXT:    lui a1, 2
 ; RV64IMB-NEXT:    addiw a1, a1, 798
 ; RV64IMB-NEXT:    add a0, a0, a1
+; RV64IMB-NEXT:    .cfi_def_cfa_offset 0
 ; RV64IMB-NEXT:    ret
   %tmp0 = mul i64 %x, -3000
   %tmp1 = add i64 %tmp0, 8990
   ret i64 %tmp1
 }
 
 define i32 @mulneg3000_sub8990_a(i32 %x) {
 ; RV32IMB-LABEL: mulneg3000_sub8990_a:
 ; RV32IMB:       # %bb.0:
 ; RV32IMB-NEXT:    lui a1, 1048575
 ; RV32IMB-NEXT:    addi a1, a1, 1096
 ; RV32IMB-NEXT:    mul a0, a0, a1
 ; RV32IMB-NEXT:    lui a1, 1048574
 ; RV32IMB-NEXT:    addi a1, a1, -798
 ; RV32IMB-NEXT:    add a0, a0, a1
+; RV32IMB-NEXT:    .cfi_def_cfa_offset 0
 ; RV32IMB-NEXT:    ret
 ;
 ; RV64IMB-LABEL: mulneg3000_sub8990_a:
 ; RV64IMB:       # %bb.0:
 ; RV64IMB-NEXT:    lui a1, 1048575
 ; RV64IMB-NEXT:    addiw a1, a1, 1096
 ; RV64IMB-NEXT:    mulw a0, a0, a1
 ; RV64IMB-NEXT:    lui a1, 1048574
 ; RV64IMB-NEXT:    addiw a1, a1, -798
 ; RV64IMB-NEXT:    addw a0, a0, a1
+; RV64IMB-NEXT:    .cfi_def_cfa_offset 0
 ; RV64IMB-NEXT:    ret
   %tmp0 = mul i32 %x, -3000
   %tmp1 = add i32 %tmp0, -8990
   ret i32 %tmp1
 }
 
 define signext i32 @mulneg3000_sub8990_b(i32 signext %x) {
 ; RV32IMB-LABEL: mulneg3000_sub8990_b:
 ; RV32IMB:       # %bb.0:
 ; RV32IMB-NEXT:    lui a1, 1048575
 ; RV32IMB-NEXT:    addi a1, a1, 1096
 ; RV32IMB-NEXT:    mul a0, a0, a1
 ; RV32IMB-NEXT:    lui a1, 1048574
 ; RV32IMB-NEXT:    addi a1, a1, -798
 ; RV32IMB-NEXT:    add a0, a0, a1
+; RV32IMB-NEXT:    .cfi_def_cfa_offset 0
 ; RV32IMB-NEXT:    ret
 ;
 ; RV64IMB-LABEL: mulneg3000_sub8990_b:
 ; RV64IMB:       # %bb.0:
 ; RV64IMB-NEXT:    lui a1, 1048575
 ; RV64IMB-NEXT:    addiw a1, a1, 1096
 ; RV64IMB-NEXT:    mulw a0, a0, a1
 ; RV64IMB-NEXT:    lui a1, 1048574
 ; RV64IMB-NEXT:    addiw a1, a1, -798
 ; RV64IMB-NEXT:    addw a0, a0, a1
+; RV64IMB-NEXT:    .cfi_def_cfa_offset 0
 ; RV64IMB-NEXT:    ret
   %tmp0 = mul i32 %x, -3000
   %tmp1 = add i32 %tmp0, -8990
   ret i32 %tmp1
 }
 
 define i64 @mulneg3000_sub8990_c(i64 %x) {
 ; RV32IMB-LABEL: mulneg3000_sub8990_c:
 ; RV32IMB:       # %bb.0:
 ; RV32IMB-NEXT:    lui a2, 1048575
 ; RV32IMB-NEXT:    addi a2, a2, 1096
 ; RV32IMB-NEXT:    mul a1, a1, a2
 ; RV32IMB-NEXT:    mulhu a3, a0, a2
 ; RV32IMB-NEXT:    sub a3, a3, a0
 ; RV32IMB-NEXT:    add a1, a3, a1
 ; RV32IMB-NEXT:    mul a2, a0, a2
 ; RV32IMB-NEXT:    lui a0, 1048574
 ; RV32IMB-NEXT:    addi a0, a0, -798
 ; RV32IMB-NEXT:    add a0, a2, a0
 ; RV32IMB-NEXT:    sltu a2, a0, a2
 ; RV32IMB-NEXT:    add a1, a1, a2
 ; RV32IMB-NEXT:    addi a1, a1, -1
+; RV32IMB-NEXT:    .cfi_def_cfa_offset 0
 ; RV32IMB-NEXT:    ret
 ;
 ; RV64IMB-LABEL: mulneg3000_sub8990_c:
 ; RV64IMB:       # %bb.0:
 ; RV64IMB-NEXT:    lui a1, 1048575
 ; RV64IMB-NEXT:    addiw a1, a1, 1096
 ; RV64IMB-NEXT:    mul a0, a0, a1
 ; RV64IMB-NEXT:    lui a1, 1048574
 ; RV64IMB-NEXT:    addiw a1, a1, -798
 ; RV64IMB-NEXT:    add a0, a0, a1
+; RV64IMB-NEXT:    .cfi_def_cfa_offset 0
 ; RV64IMB-NEXT:    ret
   %tmp0 = mul i64 %x, -3000
   %tmp1 = add i64 %tmp0, -8990
   ret i64 %tmp1
 }

llvm/test/CodeGen/RISCV/addrspacecast.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
 ; RUN:   | FileCheck %s --check-prefix=RV32I
 ; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
 ; RUN:   | FileCheck %s --check-prefix=RV64I
 
 define void @cast0(i32 addrspace(1)* %ptr) {
 ; RV32I-LABEL: cast0:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    sw zero, 0(a0)
+; RV32I-NEXT:    .cfi_def_cfa_offset 0
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: cast0:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    sw zero, 0(a0)
+; RV64I-NEXT:    .cfi_def_cfa_offset 0
 ; RV64I-NEXT:    ret
   %ptr0 = addrspacecast i32 addrspace(1)* %ptr to i32 addrspace(0)*
   store i32 0, i32* %ptr0
   ret void
 }
 
 define void @cast1(i32* %ptr) {
 ; RV32I-LABEL: cast1:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    .cfi_def_cfa_offset 16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    .cfi_offset ra, -4
 ; RV32I-NEXT:    call foo@plt
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT:    .cfi_restore ra
 ; RV32I-NEXT:    addi sp, sp, 16
+; RV32I-NEXT:    .cfi_def_cfa_offset 0
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: cast1:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    addi sp, sp, -16
 ; RV64I-NEXT:    .cfi_def_cfa_offset 16
 ; RV64I-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64I-NEXT:    .cfi_offset ra, -8
 ; RV64I-NEXT:    call foo@plt
 ; RV64I-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
+; RV64I-NEXT:    .cfi_restore ra
 ; RV64I-NEXT:    addi sp, sp, 16
+; RV64I-NEXT:    .cfi_def_cfa_offset 0
 ; RV64I-NEXT:    ret
   %castptr = addrspacecast i32* %ptr to i32 addrspace(10)*
   call void @foo(i32 addrspace(10)* %castptr)
   ret void
 }
 
 declare void @foo(i32 addrspace(10)*)

llvm/test/CodeGen/RISCV/aext-to-sext.ll

 ; RV64I-NEXT:    sext.w a0, a0
 ; RV64I-NEXT:    seqz a3, a0
 ; RV64I-NEXT:    addw a0, a1, a2
 ; RV64I-NEXT:    slli a1, a3, 3
 ; RV64I-NEXT:  .LBB1_1: # %bb
 ; RV64I-NEXT:    # =>This Inner Loop Header: Depth=1
 ; RV64I-NEXT:    beq a0, a1, .LBB1_1
 ; RV64I-NEXT:  # %bb.2: # %bar
+; RV64I-NEXT:    .cfi_def_cfa_offset 0
 ; RV64I-NEXT:    ret
   br label %bb
 
 bb:
   %a = icmp eq i32 %x, 0
   %b = add i32 %y, %z
   %c = select i1 %a, i32 8, i32 0
   %d = icmp eq i32 %b, %c
   br i1 %d, label %bb, label %bar
 
 bar:
   ret i32 %b
 }

llvm/test/CodeGen/RISCV/alu32.ll

 
 ; This makes sure SimplifyDemandedBits doesn't prevent us from matching SRLIW
 ; on RV64.
 define i32 @srli_demandedbits(i32 %0) {
 ; RV32I-LABEL: srli_demandedbits:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    srli a0, a0, 3
 ; RV32I-NEXT:    ori a0, a0, 1
+; RV32I-NEXT:    .cfi_def_cfa_offset 0
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: srli_demandedbits:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    srliw a0, a0, 3
 ; RV64I-NEXT:    ori a0, a0, 1
+; RV64I-NEXT:    .cfi_def_cfa_offset 0
 ; RV64I-NEXT:    ret
   %2 = lshr i32 %0, 3
   %3 = or i32 %2, 1
   ret i32 %3
 }
 
 define i32 @srai(i32 %a) nounwind {
 ; RV32I-LABEL: srai:

llvm/test/CodeGen/RISCV/bswap-ctlz-cttz-ctpop.ll

 ; RV32I-NEXT:    xor a0, a0, a1
 ; RV32I-NEXT:    srli a1, a0, 4
 ; RV32I-NEXT:    xor a0, a0, a1
 ; RV32I-NEXT:    srli a1, a0, 2
 ; RV32I-NEXT:    xor a0, a0, a1
 ; RV32I-NEXT:    srli a1, a0, 1
 ; RV32I-NEXT:    xor a0, a0, a1
 ; RV32I-NEXT:    andi a0, a0, 1
+; RV32I-NEXT:    .cfi_def_cfa_offset 0
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: test_parity_i32:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    slli a1, a0, 32
 ; RV64I-NEXT:    srli a1, a1, 32
 ; RV64I-NEXT:    srliw a0, a0, 16
 ; RV64I-NEXT:    xor a0, a1, a0
 ; RV64I-NEXT:    srli a1, a0, 8
 ; RV64I-NEXT:    xor a0, a0, a1
 ; RV64I-NEXT:    srli a1, a0, 4
 ; RV64I-NEXT:    xor a0, a0, a1
 ; RV64I-NEXT:    srli a1, a0, 2
 ; RV64I-NEXT:    xor a0, a0, a1
 ; RV64I-NEXT:    srli a1, a0, 1
 ; RV64I-NEXT:    xor a0, a0, a1
 ; RV64I-NEXT:    andi a0, a0, 1
+; RV64I-NEXT:    .cfi_def_cfa_offset 0
 ; RV64I-NEXT:    ret
   %1 = call i32 @llvm.ctpop.i32(i32 %a)
   %2 = and i32 %1, 1
   ret i32 %2
 }
 
 define i64 @test_parity_i64(i64 %a) {
 ; RV32I-LABEL: test_parity_i64:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    xor a0, a0, a1
 ; RV32I-NEXT:    srli a1, a0, 16
 ; RV32I-NEXT:    xor a0, a0, a1
 ; RV32I-NEXT:    srli a1, a0, 8
 ; RV32I-NEXT:    xor a0, a0, a1
 ; RV32I-NEXT:    srli a1, a0, 4
 ; RV32I-NEXT:    xor a0, a0, a1
 ; RV32I-NEXT:    srli a1, a0, 2
 ; RV32I-NEXT:    xor a0, a0, a1
 ; RV32I-NEXT:    srli a1, a0, 1
 ; RV32I-NEXT:    xor a0, a0, a1
 ; RV32I-NEXT:    andi a0, a0, 1
 ; RV32I-NEXT:    mv a1, zero
+; RV32I-NEXT:    .cfi_def_cfa_offset 0
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: test_parity_i64:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    srli a1, a0, 32
 ; RV64I-NEXT:    xor a0, a0, a1
 ; RV64I-NEXT:    srli a1, a0, 16
 ; RV64I-NEXT:    xor a0, a0, a1
 ; RV64I-NEXT:    srli a1, a0, 8
 ; RV64I-NEXT:    xor a0, a0, a1
 ; RV64I-NEXT:    srli a1, a0, 4
 ; RV64I-NEXT:    xor a0, a0, a1
 ; RV64I-NEXT:    srli a1, a0, 2
 ; RV64I-NEXT:    xor a0, a0, a1
 ; RV64I-NEXT:    srli a1, a0, 1
 ; RV64I-NEXT:    xor a0, a0, a1
 ; RV64I-NEXT:    andi a0, a0, 1
+; RV64I-NEXT:    .cfi_def_cfa_offset 0
 ; RV64I-NEXT:    ret
   %1 = call i64 @llvm.ctpop.i64(i64 %a)
   %2 = and i64 %1, 1
   ret i64 %2
 }

llvm/test/CodeGen/RISCV/calling-conv-vector-float.ll

 ; RV64-NEXT:    fmv.w.x ft0, a2
 ; RV64-NEXT:    fmv.w.x ft1, a0
 ; RV64-NEXT:    fmv.w.x ft2, a3
 ; RV64-NEXT:    fmv.w.x ft3, a1
 ; RV64-NEXT:    fadd.s ft2, ft3, ft2
 ; RV64-NEXT:    fadd.s ft0, ft1, ft0
 ; RV64-NEXT:    fmv.x.w a0, ft0
 ; RV64-NEXT:    fmv.x.w a1, ft2
+; RV64-NEXT:    .cfi_def_cfa_offset 0
 ; RV64-NEXT:    ret
 ;
 ; RV64LP64F-LABEL: callee_v2f32:
 ; RV64LP64F:       # %bb.0:
 ; RV64LP64F-NEXT:    fadd.s fa0, fa0, fa2
 ; RV64LP64F-NEXT:    fadd.s fa1, fa1, fa3
+; RV64LP64F-NEXT:         .cfi_def_cfa_offset 0
 ; RV64LP64F-NEXT:    ret
   %z = fadd <2 x float> %x, %y
   ret <2 x float> %z
 }
 
 define <4 x float> @callee_v4f32(<4 x float> %x, <4 x float> %y) {
 ; RV64-LABEL: callee_v4f32:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    fmv.w.x ft0, a4
 ; RV64-NEXT:    fmv.w.x ft1, a7
 ; RV64-NEXT:    fmv.w.x ft2, a3
 ; RV64-NEXT:    fmv.w.x ft3, a6
 ; RV64-NEXT:    fmv.w.x ft4, a2
 ; RV64-NEXT:    fmv.w.x ft5, a5
 ; RV64-NEXT:    fmv.w.x ft6, a1
 ; RV64-NEXT:    flw ft7, 0(sp)
 ; RV64-NEXT:    fadd.s ft5, ft6, ft5
 ; RV64-NEXT:    fadd.s ft3, ft4, ft3
 ; RV64-NEXT:    fadd.s ft1, ft2, ft1
 ; RV64-NEXT:    fadd.s ft0, ft0, ft7
 ; RV64-NEXT:    fsw ft0, 12(a0)
 ; RV64-NEXT:    fsw ft1, 8(a0)
 ; RV64-NEXT:    fsw ft3, 4(a0)
 ; RV64-NEXT:    fsw ft5, 0(a0)
+; RV64-NEXT:    .cfi_def_cfa_offset 0
 ; RV64-NEXT:    ret
 ;
 ; RV64LP64F-LABEL: callee_v4f32:
 ; RV64LP64F:       # %bb.0:
 ; RV64LP64F-NEXT:    fadd.s ft0, fa0, fa4
 ; RV64LP64F-NEXT:    fadd.s ft1, fa1, fa5
 ; RV64LP64F-NEXT:    fadd.s ft2, fa2, fa6
 ; RV64LP64F-NEXT:    fadd.s ft3, fa3, fa7
 ; RV64LP64F-NEXT:    fsw ft3, 12(a0)
 ; RV64LP64F-NEXT:    fsw ft2, 8(a0)
 ; RV64LP64F-NEXT:    fsw ft1, 4(a0)
 ; RV64LP64F-NEXT:    fsw ft0, 0(a0)
+; RV64LP64F-NEXT:    .cfi_def_cfa_offset 0
 ; RV64LP64F-NEXT:    ret
   %z = fadd <4 x float> %x, %y
   ret <4 x float> %z
 }

llvm/test/CodeGen/RISCV/double-convert.ll

 ; RV32IFD-NEXT:    fld ft0, 8(sp)
 ; RV32IFD-NEXT:    fcvt.wu.d a1, ft0, rtz
 ; RV32IFD-NEXT:    addi a0, zero, 1
 ; RV32IFD-NEXT:    beqz a1, .LBB5_2
 ; RV32IFD-NEXT:  # %bb.1:
 ; RV32IFD-NEXT:    mv a0, a1
 ; RV32IFD-NEXT:  .LBB5_2:
 ; RV32IFD-NEXT:    addi sp, sp, 16
+; RV32IFD-NEXT:    .cfi_def_cfa_offset 0
 ; RV32IFD-NEXT:    ret
 ;
 ; RV64IFD-LABEL: fcvt_wu_d_multiple_use:
 ; RV64IFD:       # %bb.0:
 ; RV64IFD-NEXT:    fmv.d.x ft0, a0
 ; RV64IFD-NEXT:    fcvt.wu.d a1, ft0, rtz
 ; RV64IFD-NEXT:    addi a0, zero, 1
 ; RV64IFD-NEXT:    beqz a1, .LBB5_2
 ; RV64IFD-NEXT:  # %bb.1:
 ; RV64IFD-NEXT:    mv a0, a1
 ; RV64IFD-NEXT:  .LBB5_2:
+; RV64IFD-NEXT:  .cfi_def_cfa_offset 0
 ; RV64IFD-NEXT:    ret
   %a = fptoui double %x to i32
   %b = icmp eq i32 %a, 0
   %c = select i1 %b, i32 1, i32 %a
   ret i32 %c
 }
 
 define i32 @fcvt_wu_d_sat(double %a) nounwind {

 
 ; Make sure we select W version of addi on RV64.
 define signext i32 @fcvt_d_w_demanded_bits(i32 signext %0, double* %1) {
 ; RV32IFD-LABEL: fcvt_d_w_demanded_bits:
 ; RV32IFD:       # %bb.0:
 ; RV32IFD-NEXT:    addi a0, a0, 1
 ; RV32IFD-NEXT:    fcvt.d.w ft0, a0
 ; RV32IFD-NEXT:    fsd ft0, 0(a1)
+; RV32IFD-NEXT:    .cfi_def_cfa_offset 0
 ; RV32IFD-NEXT:    ret
 ;
 ; RV64IFD-LABEL: fcvt_d_w_demanded_bits:
 ; RV64IFD:       # %bb.0:
 ; RV64IFD-NEXT:    addiw a0, a0, 1
 ; RV64IFD-NEXT:    fcvt.d.w ft0, a0
 ; RV64IFD-NEXT:    fsd ft0, 0(a1)
+; RV64IFD-NEXT:    .cfi_def_cfa_offset 0
 ; RV64IFD-NEXT:    ret
   %3 = add i32 %0, 1
   %4 = sitofp i32 %3 to double
   store double %4, double* %1, align 8
   ret i32 %3
 }
 
 ; Make sure we select W version of addi on RV64.
 define signext i32 @fcvt_d_wu_demanded_bits(i32 signext %0, double* %1) {
 ; RV32IFD-LABEL: fcvt_d_wu_demanded_bits:
 ; RV32IFD:       # %bb.0:
 ; RV32IFD-NEXT:    addi a0, a0, 1
 ; RV32IFD-NEXT:    fcvt.d.wu ft0, a0
 ; RV32IFD-NEXT:    fsd ft0, 0(a1)
+; RV32IFD-NEXT:    .cfi_def_cfa_offset 0
 ; RV32IFD-NEXT:    ret
 ;
 ; RV64IFD-LABEL: fcvt_d_wu_demanded_bits:
 ; RV64IFD:       # %bb.0:
 ; RV64IFD-NEXT:    addiw a0, a0, 1
 ; RV64IFD-NEXT:    fcvt.d.wu ft0, a0
 ; RV64IFD-NEXT:    fsd ft0, 0(a1)
+; RV64IFD-NEXT:    .cfi_def_cfa_offset 0
 ; RV64IFD-NEXT:    ret
   %3 = add i32 %0, 1
   %4 = uitofp i32 %3 to double
   store double %4, double* %1, align 8
   ret i32 %3
 }

llvm/test/CodeGen/RISCV/exception-pointer-register.ll

 ; RV32I-NEXT:  .Ltmp2:
 ; RV32I-NEXT:    mv a0, s0
 ; RV32I-NEXT:    call foo@plt
 ; RV32I-NEXT:  .Ltmp3:
 ; RV32I-NEXT:  .LBB0_3: # %end2
 ; RV32I-NEXT:    lw s1, 4(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32I-NEXT:    .cfi_restore ra
+; RV32I-NEXT:    .cfi_restore s0
+; RV32I-NEXT:    .cfi_restore s1
 ; RV32I-NEXT:    addi sp, sp, 16
+; RV32I-NEXT:    .cfi_def_cfa_offset 0
 ; RV32I-NEXT:    ret
 ; RV32I-NEXT:  .LBB0_4: # %lpad
 ; RV32I-NEXT:  .Ltmp4:
 ; RV32I-NEXT:    mv s1, a0
 ; RV32I-NEXT:    mv a0, s0
 ; RV32I-NEXT:    call callee
 ; RV32I-NEXT:    mv a0, s1
 ; RV32I-NEXT:    call _Unwind_Resume@plt

 ; RV64I-NEXT:  .Ltmp2:
 ; RV64I-NEXT:    mv a0, s0
 ; RV64I-NEXT:    call foo@plt
 ; RV64I-NEXT:  .Ltmp3:
 ; RV64I-NEXT:  .LBB0_3: # %end2
 ; RV64I-NEXT:    ld s1, 8(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld s0, 16(sp) # 8-byte Folded Reload
 ; RV64I-NEXT:    ld ra, 24(sp) # 8-byte Folded Reload
+; RV64I-NEXT:    .cfi_restore ra
+; RV64I-NEXT:    .cfi_restore s0
+; RV64I-NEXT:    .cfi_restore s1
 ; RV64I-NEXT:    addi sp, sp, 32
+; RV64I-NEXT:    .cfi_def_cfa_offset 0
 ; RV64I-NEXT:    ret
 ; RV64I-NEXT:  .LBB0_4: # %lpad
 ; RV64I-NEXT:  .Ltmp4:
 ; RV64I-NEXT:    mv s1, a0
 ; RV64I-NEXT:    mv a0, s0
 ; RV64I-NEXT:    call callee
 ; RV64I-NEXT:    mv a0, s1
 ; RV64I-NEXT:    call _Unwind_Resume@plt

 
 end2:
   ret void
 }
 
 define internal void @callee(i1* %p) {
 ; RV32I-LABEL: callee:
 ; RV32I:       # %bb.0:
+; RV32I-NEXT:    .cfi_def_cfa_offset 0
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: callee:
 ; RV64I:       # %bb.0:
+; RV64I-NEXT:    .cfi_def_cfa_offset 0
 ; RV64I-NEXT:    ret
   ret void
 }

llvm/test/CodeGen/RISCV/float-convert.ll

 ; RV32IF:       # %bb.0:
 ; RV32IF-NEXT:    fmv.w.x ft0, a0
 ; RV32IF-NEXT:    fcvt.wu.s a1, ft0, rtz
 ; RV32IF-NEXT:    addi a0, zero, 1
 ; RV32IF-NEXT:    beqz a1, .LBB3_2
 ; RV32IF-NEXT:  # %bb.1:
 ; RV32IF-NEXT:    mv a0, a1
 ; RV32IF-NEXT:  .LBB3_2:
+; RV32IF-NEXT:    .cfi_def_cfa_offset 0
 ; RV32IF-NEXT:    ret
 ;
 ; RV64IF-LABEL: fcvt_wu_s_multiple_use:
 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    fmv.w.x ft0, a0
 ; RV64IF-NEXT:    fcvt.wu.s a1, ft0, rtz
 ; RV64IF-NEXT:    addi a0, zero, 1
 ; RV64IF-NEXT:    beqz a1, .LBB3_2
 ; RV64IF-NEXT:  # %bb.1:
 ; RV64IF-NEXT:    mv a0, a1
 ; RV64IF-NEXT:  .LBB3_2:
+; RV64IF-NEXT:    .cfi_def_cfa_offset 0
 ; RV64IF-NEXT:    ret
   %a = fptoui float %x to i32
   %b = icmp eq i32 %a, 0
   %c = select i1 %b, i32 1, i32 %a
   ret i32 %c
 }
 
 define i32 @fcvt_wu_s_sat(float %a) nounwind {

 
 ; Make sure we select W version of addi on RV64.
 define signext i32 @fcvt_s_w_demanded_bits(i32 signext %0, float* %1) {
 ; RV32IF-LABEL: fcvt_s_w_demanded_bits:
 ; RV32IF:       # %bb.0:
 ; RV32IF-NEXT:    addi a0, a0, 1
 ; RV32IF-NEXT:    fcvt.s.w ft0, a0
 ; RV32IF-NEXT:    fsw ft0, 0(a1)
+; RV32IF-NEXT:    .cfi_def_cfa_offset 0
 ; RV32IF-NEXT:    ret
 ;
 ; RV64IF-LABEL: fcvt_s_w_demanded_bits:
 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    addiw a0, a0, 1
 ; RV64IF-NEXT:    fcvt.s.w ft0, a0
 ; RV64IF-NEXT:    fsw ft0, 0(a1)
+; RV64IF-NEXT:    .cfi_def_cfa_offset 0
 ; RV64IF-NEXT:    ret
   %3 = add i32 %0, 1
   %4 = sitofp i32 %3 to float
   store float %4, float* %1, align 4
   ret i32 %3
 }
 
 ; Make sure we select W version of addi on RV64.
 define signext i32 @fcvt_s_wu_demanded_bits(i32 signext %0, float* %1) {
 ; RV32IF-LABEL: fcvt_s_wu_demanded_bits:
 ; RV32IF:       # %bb.0:
 ; RV32IF-NEXT:    addi a0, a0, 1
 ; RV32IF-NEXT:    fcvt.s.wu ft0, a0
 ; RV32IF-NEXT:    fsw ft0, 0(a1)
+; RV32IF-NEXT:    .cfi_def_cfa_offset 0
 ; RV32IF-NEXT:    ret
 ;
 ; RV64IF-LABEL: fcvt_s_wu_demanded_bits:
 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    addiw a0, a0, 1
 ; RV64IF-NEXT:    fcvt.s.wu ft0, a0
 ; RV64IF-NEXT:    fsw ft0, 0(a1)
+; RV64IF-NEXT:    .cfi_def_cfa_offset 0
 ; RV64IF-NEXT:    ret
   %3 = add i32 %0, 1
   %4 = uitofp i32 %3 to float
   store float %4, float* %1, align 4
   ret i32 %3
 }

llvm/test/CodeGen/RISCV/fpenv.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -mattr=+f -verify-machineinstrs < %s | FileCheck -check-prefix=RV32IF %s
 ; RUN: llc -mtriple=riscv64 -mattr=+f -verify-machineinstrs < %s | FileCheck -check-prefix=RV64IF %s
 
 define i32 @func_01() {
 ; RV32IF-LABEL: func_01:
 ; RV32IF:       # %bb.0:
 ; RV32IF-NEXT:    frrm a0
 ; RV32IF-NEXT:    slli a0, a0, 2
 ; RV32IF-NEXT:    lui a1, 66
 ; RV32IF-NEXT:    addi a1, a1, 769
 ; RV32IF-NEXT:    srl a0, a1, a0
 ; RV32IF-NEXT:    andi a0, a0, 7
+; RV32IF-NEXT:    .cfi_def_cfa_offset 0
 ; RV32IF-NEXT:    ret
 ;
 ; RV64IF-LABEL: func_01:
 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    frrm a0
 ; RV64IF-NEXT:    slli a0, a0, 2
 ; RV64IF-NEXT:    lui a1, 66
 ; RV64IF-NEXT:    addiw a1, a1, 769
 ; RV64IF-NEXT:    srl a0, a1, a0
 ; RV64IF-NEXT:    andi a0, a0, 7
+; RV64IF-NEXT:    .cfi_def_cfa_offset 0
 ; RV64IF-NEXT:    ret
   %rm = call i32 @llvm.flt.rounds()
   ret i32 %rm
 }
 
 define void @func_02(i32 %rm) {
 ; RV32IF-LABEL: func_02:
 ; RV32IF:       # %bb.0:
 ; RV32IF-NEXT:    slli a0, a0, 2
 ; RV32IF-NEXT:    lui a1, 66
 ; RV32IF-NEXT:    addi a1, a1, 769
 ; RV32IF-NEXT:    srl a0, a1, a0
 ; RV32IF-NEXT:    andi a0, a0, 7
 ; RV32IF-NEXT:    fsrm a0
+; RV32IF-NEXT:    .cfi_def_cfa_offset 0
 ; RV32IF-NEXT:    ret
 ;
 ; RV64IF-LABEL: func_02:
 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    slli a0, a0, 32
 ; RV64IF-NEXT:    srli a0, a0, 30
 ; RV64IF-NEXT:    lui a1, 66
 ; RV64IF-NEXT:    addiw a1, a1, 769
 ; RV64IF-NEXT:    srl a0, a1, a0
 ; RV64IF-NEXT:    andi a0, a0, 7
 ; RV64IF-NEXT:    fsrm a0
+; RV64IF-NEXT:    .cfi_def_cfa_offset 0
 ; RV64IF-NEXT:    ret
   call void @llvm.set.rounding(i32 %rm)
   ret void
 }
 
 define void @func_03() {
 ; RV32IF-LABEL: func_03:
 ; RV32IF:       # %bb.0:
 ; RV32IF-NEXT:    fsrmi 1
+; RV32IF-NEXT:    .cfi_def_cfa_offset 0
 ; RV32IF-NEXT:    ret
 ;
 ; RV64IF-LABEL: func_03:
 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    fsrmi 1
+; RV64IF-NEXT:    .cfi_def_cfa_offset 0
 ; RV64IF-NEXT:    ret
   call void @llvm.set.rounding(i32 0)
   ret void
 }
 
 define void @func_04() {
 ; RV32IF-LABEL: func_04:
 ; RV32IF:       # %bb.0:
 ; RV32IF-NEXT:    fsrmi 0
+; RV32IF-NEXT:    .cfi_def_cfa_offset 0
 ; RV32IF-NEXT:    ret
 ;
 ; RV64IF-LABEL: func_04:
 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    fsrmi 0
+; RV64IF-NEXT:    .cfi_def_cfa_offset 0
 ; RV64IF-NEXT:    ret
   call void @llvm.set.rounding(i32 1)
   ret void
 }
 
 define void @func_05() {
 ; RV32IF-LABEL: func_05:
 ; RV32IF:       # %bb.0:
 ; RV32IF-NEXT:    fsrmi 3
+; RV32IF-NEXT:    .cfi_def_cfa_offset 0
 ; RV32IF-NEXT:    ret
 ;
 ; RV64IF-LABEL: func_05:
 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    fsrmi 3
+; RV64IF-NEXT:    .cfi_def_cfa_offset 0
 ; RV64IF-NEXT:    ret
   call void @llvm.set.rounding(i32 2)
   ret void
 }
 
 define void @func_06() {
 ; RV32IF-LABEL: func_06:
 ; RV32IF:       # %bb.0:
 ; RV32IF-NEXT:    fsrmi 2
+; RV32IF-NEXT:    .cfi_def_cfa_offset 0
 ; RV32IF-NEXT:    ret
 ;
 ; RV64IF-LABEL: func_06:
 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    fsrmi 2
+; RV64IF-NEXT:    .cfi_def_cfa_offset 0
 ; RV64IF-NEXT:    ret
   call void @llvm.set.rounding(i32 3)
   ret void
 }
 
 define void @func_07() {
 ; RV32IF-LABEL: func_07:
 ; RV32IF:       # %bb.0:
 ; RV32IF-NEXT:    fsrmi 4
+; RV32IF-NEXT:    .cfi_def_cfa_offset 0
 ; RV32IF-NEXT:    ret
 ;
 ; RV64IF-LABEL: func_07:
 ; RV64IF:       # %bb.0:
 ; RV64IF-NEXT:    fsrmi 4
+; RV64IF-NEXT:    .cfi_def_cfa_offset 0
 ; RV64IF-NEXT:    ret
   call void @llvm.set.rounding(i32 4)
   ret void
 }
 
 declare void @llvm.set.rounding(i32)
 declare i32 @llvm.flt.rounds()

llvm/test/CodeGen/RISCV/frame-info.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 < %s \
 ; RUN:   | FileCheck -check-prefix=RV32 %s
 ; RUN: llc -mtriple=riscv64 < %s \
 ; RUN:   | FileCheck -check-prefix=RV64 %s
 ; RUN: llc -mtriple=riscv32 -frame-pointer=all -verify-machineinstrs < %s \
 ; RUN:   | FileCheck -check-prefix=RV32-WITHFP %s
 ; RUN: llc -mtriple=riscv64 -frame-pointer=all -verify-machineinstrs < %s \
 ; RUN:   | FileCheck -check-prefix=RV64-WITHFP %s
 
 define void @trivial() {
 ; RV32-LABEL: trivial:
 ; RV32:       # %bb.0:
+; RV32-NEXT:    .cfi_def_cfa_offset 0
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: trivial:
 ; RV64:       # %bb.0:
+; RV64-NEXT:    .cfi_def_cfa_offset 0
 ; RV64-NEXT:    ret
 ;
 ; RV32-WITHFP-LABEL: trivial:
 ; RV32-WITHFP:       # %bb.0:
 ; RV32-WITHFP-NEXT:    addi sp, sp, -16
 ; RV32-WITHFP-NEXT:    .cfi_def_cfa_offset 16
 ; RV32-WITHFP-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32-WITHFP-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
 ; RV32-WITHFP-NEXT:    .cfi_offset ra, -4
 ; RV32-WITHFP-NEXT:    .cfi_offset s0, -8
 ; RV32-WITHFP-NEXT:    addi s0, sp, 16
 ; RV32-WITHFP-NEXT:    .cfi_def_cfa s0, 0
 ; RV32-WITHFP-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
+; RV32-WITHFP-NEXT:    .cfi_def_cfa sp, 16
 ; RV32-WITHFP-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32-WITHFP-NEXT:    .cfi_restore ra
+; RV32-WITHFP-NEXT:    .cfi_restore s0
 ; RV32-WITHFP-NEXT:    addi sp, sp, 16
+; RV32-WITHFP-NEXT:    .cfi_def_cfa_offset 0
 ; RV32-WITHFP-NEXT:    ret
-;
-; RV64-WITHFP-LABEL: trivial:
-; RV64-WITHFP:       # %bb.0:
 ; RV64-WITHFP-NEXT:    addi sp, sp, -16
 ; RV64-WITHFP-NEXT:    .cfi_def_cfa_offset 16
 ; RV64-WITHFP-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64-WITHFP-NEXT:    sd s0, 0(sp) # 8-byte Folded Spill
 ; RV64-WITHFP-NEXT:    .cfi_offset ra, -8
 ; RV64-WITHFP-NEXT:    .cfi_offset s0, -16
 ; RV64-WITHFP-NEXT:    addi s0, sp, 16
 ; RV64-WITHFP-NEXT:    .cfi_def_cfa s0, 0

 ; RV32-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
 ; RV32-NEXT:    .cfi_offset ra, -4
 ; RV32-NEXT:    .cfi_offset s0, -8
 ; RV32-NEXT:    addi s0, sp, 16
 ; RV32-NEXT:    .cfi_def_cfa s0, 0
 ; RV32-NEXT:    addi a0, a0, 15
 ; RV32-NEXT:    andi a0, a0, -16
 ; RV32-NEXT:    sub a0, sp, a0
-; RV32-NEXT:    mv sp, a0
+; RV32-NEXT:    mv sp, a0   
 ; RV32-NEXT:    call callee_with_args@plt
 ; RV32-NEXT:    addi sp, s0, -16
 ; RV32-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
+; RV32-NEXT:    .cfi_def_cfa sp, 16
 ; RV32-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32-NEXT:    .cfi_restore ra
+; RV32-NEXT:    .cfi_restore s0
 ; RV32-NEXT:    addi sp, sp, 16
+; RV32-NEXT:    .cfi_def_cfa_offset 0
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: stack_alloc:
 ; RV64:       # %bb.0: # %entry
 ; RV64-NEXT:    addi sp, sp, -16
 ; RV64-NEXT:    .cfi_def_cfa_offset 16
 ; RV64-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64-NEXT:    sd s0, 0(sp) # 8-byte Folded Spill
 ; RV64-NEXT:    .cfi_offset ra, -8
 ; RV64-NEXT:    .cfi_offset s0, -16
 ; RV64-NEXT:    addi s0, sp, 16
 ; RV64-NEXT:    .cfi_def_cfa s0, 0
 ; RV64-NEXT:    slli a0, a0, 32
 ; RV64-NEXT:    srli a0, a0, 32
 ; RV64-NEXT:    addi a0, a0, 15
 ; RV64-NEXT:    andi a0, a0, -16
 ; RV64-NEXT:    sub a0, sp, a0
 ; RV64-NEXT:    mv sp, a0
 ; RV64-NEXT:    call callee_with_args@plt
 ; RV64-NEXT:    addi sp, s0, -16
 ; RV64-NEXT:    ld s0, 0(sp) # 8-byte Folded Reload
+; RV64-NEXT:    .cfi_def_cfa sp, 16
 ; RV64-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
+; RV64-NEXT:    .cfi_restore ra
+; RV64-NEXT:    .cfi_restore s0
 ; RV64-NEXT:    addi sp, sp, 16
+; RV64-NEXT:    .cfi_def_cfa_offset 0
 ; RV64-NEXT:    ret
 ;
 ; RV32-WITHFP-LABEL: stack_alloc:
 ; RV32-WITHFP:       # %bb.0: # %entry
 ; RV32-WITHFP-NEXT:    addi sp, sp, -16
 ; RV32-WITHFP-NEXT:    .cfi_def_cfa_offset 16
 ; RV32-WITHFP-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32-WITHFP-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
 ; RV32-WITHFP-NEXT:    .cfi_offset ra, -4
 ; RV32-WITHFP-NEXT:    .cfi_offset s0, -8
 ; RV32-WITHFP-NEXT:    addi s0, sp, 16
 ; RV32-WITHFP-NEXT:    .cfi_def_cfa s0, 0
 ; RV32-WITHFP-NEXT:    addi a0, a0, 15
 ; RV32-WITHFP-NEXT:    andi a0, a0, -16
 ; RV32-WITHFP-NEXT:    sub a0, sp, a0
 ; RV32-WITHFP-NEXT:    mv sp, a0
 ; RV32-WITHFP-NEXT:    call callee_with_args@plt
 ; RV32-WITHFP-NEXT:    addi sp, s0, -16
 ; RV32-WITHFP-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
+; RV32-WITHFP-NEXT:    .cfi_def_cfa sp, 16
 ; RV32-WITHFP-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32-WITHFP-NEXT:    .cfi_restore ra
+; RV32-WITHFP-NEXT:    .cfi_restore s0
 ; RV32-WITHFP-NEXT:    addi sp, sp, 16
+; RV32-WITHFP-NEXT:    .cfi_def_cfa_offset 0
 ; RV32-WITHFP-NEXT:    ret
 ;
 ; RV64-WITHFP-LABEL: stack_alloc:
 ; RV64-WITHFP:       # %bb.0: # %entry
 ; RV64-WITHFP-NEXT:    addi sp, sp, -16
 ; RV64-WITHFP-NEXT:    .cfi_def_cfa_offset 16
 ; RV64-WITHFP-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64-WITHFP-NEXT:    sd s0, 0(sp) # 8-byte Folded Spill

 ; RV32-NEXT:    tail callee1@plt
 ; RV32-NEXT:  .LBB2_2: # %red_pill
 ; RV32-NEXT:    addi sp, sp, -16
 ; RV32-NEXT:    .cfi_def_cfa_offset 16
 ; RV32-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32-NEXT:    .cfi_offset ra, -4
 ; RV32-NEXT:    call callee2@plt
 ; RV32-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32-NEXT:    .cfi_restore ra
 ; RV32-NEXT:    addi sp, sp, 16
+; RV32-NEXT:    .cfi_def_cfa_offset 0
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: branch_and_tail_call:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    andi a0, a0, 1
 ; RV64-NEXT:    beqz a0, .LBB2_2
 ; RV64-NEXT:  # %bb.1: # %blue_pill
 ; RV64-NEXT:    tail callee1@plt
 ; RV64-NEXT:  .LBB2_2: # %red_pill
 ; RV64-NEXT:    addi sp, sp, -16
 ; RV64-NEXT:    .cfi_def_cfa_offset 16
 ; RV64-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64-NEXT:    .cfi_offset ra, -8
 ; RV64-NEXT:    call callee2@plt
 ; RV64-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
+; RV64-NEXT:    .cfi_restore ra
 ; RV64-NEXT:    addi sp, sp, 16
+; RV64-NEXT:    .cfi_def_cfa_offset 0
 ; RV64-NEXT:    ret
 ;
 ; RV32-WITHFP-LABEL: branch_and_tail_call:
 ; RV32-WITHFP:       # %bb.0:
 ; RV32-WITHFP-NEXT:    andi a0, a0, 1
 ; RV32-WITHFP-NEXT:    beqz a0, .LBB2_2
 ; RV32-WITHFP-NEXT:  # %bb.1: # %blue_pill
 ; RV32-WITHFP-NEXT:    tail callee1@plt
 ; RV32-WITHFP-NEXT:  .LBB2_2: # %red_pill
 ; RV32-WITHFP-NEXT:    addi sp, sp, -16
 ; RV32-WITHFP-NEXT:    .cfi_def_cfa_offset 16
 ; RV32-WITHFP-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32-WITHFP-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
 ; RV32-WITHFP-NEXT:    .cfi_offset ra, -4
 ; RV32-WITHFP-NEXT:    .cfi_offset s0, -8
 ; RV32-WITHFP-NEXT:    addi s0, sp, 16
 ; RV32-WITHFP-NEXT:    .cfi_def_cfa s0, 0
 ; RV32-WITHFP-NEXT:    call callee2@plt
 ; RV32-WITHFP-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
+; RV32-WITHFP-NEXT:    .cfi_def_cfa sp, 16
 ; RV32-WITHFP-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32-WITHFP-NEXT:    .cfi_restore ra
+; RV32-WITHFP-NEXT:    .cfi_restore s0
 ; RV32-WITHFP-NEXT:    addi sp, sp, 16
+; RV32-WITHFP-NEXT:    .cfi_def_cfa_offset 0
 ; RV32-WITHFP-NEXT:    ret
 ;
 ; RV64-WITHFP-LABEL: branch_and_tail_call:
 ; RV64-WITHFP:       # %bb.0:
 ; RV64-WITHFP-NEXT:    andi a0, a0, 1
 ; RV64-WITHFP-NEXT:    beqz a0, .LBB2_2
 ; RV64-WITHFP-NEXT:  # %bb.1: # %blue_pill
 ; RV64-WITHFP-NEXT:    tail callee1@plt

llvm/test/CodeGen/RISCV/half-convert.ll

 ; RV32IZFH-LABEL: fcvt_ui_h_multiple_use:
 ; RV32IZFH:       # %bb.0:
 ; RV32IZFH-NEXT:    fcvt.wu.h a1, fa0, rtz
 ; RV32IZFH-NEXT:    addi a0, zero, 1
 ; RV32IZFH-NEXT:    beqz a1, .LBB3_2
 ; RV32IZFH-NEXT:  # %bb.1:
 ; RV32IZFH-NEXT:    mv a0, a1
 ; RV32IZFH-NEXT:  .LBB3_2:
+; RV32IZFH-NEXT:    .cfi_def_cfa_offset 0
 ; RV32IZFH-NEXT:    ret
 ;
 ; RV32IDZFH-LABEL: fcvt_ui_h_multiple_use:
 ; RV32IDZFH:       # %bb.0:
 ; RV32IDZFH-NEXT:    fcvt.wu.h a1, fa0, rtz
 ; RV32IDZFH-NEXT:    addi a0, zero, 1
 ; RV32IDZFH-NEXT:    beqz a1, .LBB3_2
 ; RV32IDZFH-NEXT:  # %bb.1:
 ; RV32IDZFH-NEXT:    mv a0, a1
 ; RV32IDZFH-NEXT:  .LBB3_2:
+; RV32IDZFH-NEXT:    .cfi_def_cfa_offset 0
 ; RV32IDZFH-NEXT:    ret
 ;
 ; RV64IZFH-LABEL: fcvt_ui_h_multiple_use:
 ; RV64IZFH:       # %bb.0:
 ; RV64IZFH-NEXT:    fcvt.wu.h a1, fa0, rtz
 ; RV64IZFH-NEXT:    addi a0, zero, 1
 ; RV64IZFH-NEXT:    beqz a1, .LBB3_2
 ; RV64IZFH-NEXT:  # %bb.1:
 ; RV64IZFH-NEXT:    mv a0, a1
 ; RV64IZFH-NEXT:  .LBB3_2:
+; RV64IZFH-NEXT:  .cfi_def_cfa_offset 0
 ; RV64IZFH-NEXT:    ret
 ;
 ; RV64IDZFH-LABEL: fcvt_ui_h_multiple_use:
 ; RV64IDZFH:       # %bb.0:
 ; RV64IDZFH-NEXT:    fcvt.wu.h a1, fa0, rtz
 ; RV64IDZFH-NEXT:    addi a0, zero, 1
 ; RV64IDZFH-NEXT:    beqz a1, .LBB3_2
 ; RV64IDZFH-NEXT:  # %bb.1:
 ; RV64IDZFH-NEXT:    mv a0, a1
 ; RV64IDZFH-NEXT:  .LBB3_2:
+; RV64IDZFH-NEXT:    .cfi_def_cfa_offset 0
 ; RV64IDZFH-NEXT:    ret
   %a = fptoui half %x to i32
   %b = icmp eq i32 %a, 0
   %c = select i1 %b, i32 1, i32 %a
   ret i32 %c
 }
 
 define i16 @fcvt_ui_h_sat(half %a) nounwind {

 
 ; Make sure we select W version of addi on RV64.
 define signext i32 @fcvt_h_w_demanded_bits(i32 signext %0, half* %1) {
 ; RV32IZFH-LABEL: fcvt_h_w_demanded_bits:
 ; RV32IZFH:       # %bb.0:
 ; RV32IZFH-NEXT:    addi a0, a0, 1
 ; RV32IZFH-NEXT:    fcvt.h.w ft0, a0
 ; RV32IZFH-NEXT:    fsh ft0, 0(a1)
+; RV32IZFH-NEXT:    .cfi_def_cfa_offset 0
 ; RV32IZFH-NEXT:    ret
 ;
 ; RV32IDZFH-LABEL: fcvt_h_w_demanded_bits:
 ; RV32IDZFH:       # %bb.0:
 ; RV32IDZFH-NEXT:    addi a0, a0, 1
 ; RV32IDZFH-NEXT:    fcvt.h.w ft0, a0
 ; RV32IDZFH-NEXT:    fsh ft0, 0(a1)
+; RV32IDZFH-NEXT:    .cfi_def_cfa_offset 0
 ; RV32IDZFH-NEXT:    ret
 ;
 ; RV64IZFH-LABEL: fcvt_h_w_demanded_bits:
 ; RV64IZFH:       # %bb.0:
 ; RV64IZFH-NEXT:    addiw a0, a0, 1
 ; RV64IZFH-NEXT:    fcvt.h.w ft0, a0
 ; RV64IZFH-NEXT:    fsh ft0, 0(a1)
+; RV64IZFH-NEXT:  .cfi_def_cfa_offset 0
 ; RV64IZFH-NEXT:    ret
 ;
 ; RV64IDZFH-LABEL: fcvt_h_w_demanded_bits:
 ; RV64IDZFH:       # %bb.0:
 ; RV64IDZFH-NEXT:    addiw a0, a0, 1
 ; RV64IDZFH-NEXT:    fcvt.h.w ft0, a0
 ; RV64IDZFH-NEXT:    fsh ft0, 0(a1)
+; RV64IDZFH-NEXT:    .cfi_def_cfa_offset 0
 ; RV64IDZFH-NEXT:    ret
   %3 = add i32 %0, 1
   %4 = sitofp i32 %3 to half
   store half %4, half* %1, align 2
   ret i32 %3
 }
 
 ; Make sure we select W version of addi on RV64.
 define signext i32 @fcvt_h_wu_demanded_bits(i32 signext %0, half* %1) {
 ; RV32IZFH-LABEL: fcvt_h_wu_demanded_bits:
 ; RV32IZFH:       # %bb.0:
 ; RV32IZFH-NEXT:    addi a0, a0, 1
 ; RV32IZFH-NEXT:    fcvt.h.wu ft0, a0
 ; RV32IZFH-NEXT:    fsh ft0, 0(a1)
+; RV32IZFH-NEXT:    .cfi_def_cfa_offset 0
 ; RV32IZFH-NEXT:    ret
 ;
 ; RV32IDZFH-LABEL: fcvt_h_wu_demanded_bits:
 ; RV32IDZFH:       # %bb.0:
 ; RV32IDZFH-NEXT:    addi a0, a0, 1
 ; RV32IDZFH-NEXT:    fcvt.h.wu ft0, a0
 ; RV32IDZFH-NEXT:    fsh ft0, 0(a1)
+; RV32IDZFH-NEXT:    .cfi_def_cfa_offset 0
 ; RV32IDZFH-NEXT:    ret
 ;
 ; RV64IZFH-LABEL: fcvt_h_wu_demanded_bits:
 ; RV64IZFH:       # %bb.0:
 ; RV64IZFH-NEXT:    addiw a0, a0, 1
 ; RV64IZFH-NEXT:    fcvt.h.wu ft0, a0
 ; RV64IZFH-NEXT:    fsh ft0, 0(a1)
+; RV64IZFH-NEXT:  .cfi_def_cfa_offset 0
 ; RV64IZFH-NEXT:    ret
 ;
 ; RV64IDZFH-LABEL: fcvt_h_wu_demanded_bits:
 ; RV64IDZFH:       # %bb.0:
 ; RV64IDZFH-NEXT:    addiw a0, a0, 1
 ; RV64IDZFH-NEXT:    fcvt.h.wu ft0, a0
 ; RV64IDZFH-NEXT:    fsh ft0, 0(a1)
+; RV64IDZFH-NEXT:    .cfi_def_cfa_offset 0
 ; RV64IDZFH-NEXT:    ret
   %3 = add i32 %0, 1
   %4 = uitofp i32 %3 to half
   store half %4, half* %1, align 2
   ret i32 %3
 }

llvm/test/CodeGen/RISCV/inline-asm-S-constraint.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 < %s | FileCheck %s --check-prefix=RV32
 ; RUN: llc -mtriple=riscv64 < %s | FileCheck %s --check-prefix=RV64
 
 @var = external dso_local global i32, align 4
 
 define dso_local i8* @constraint_S() {
 ; RV32-LABEL: constraint_S:
 ; RV32:       # %bb.0:
 ; RV32-NEXT:    #APP
 ; RV32-NEXT:    lui a0, %hi(var)
 ; RV32-NEXT:    addi a0, a0, %lo(var)
 ; RV32-NEXT:    #NO_APP
+; RV32-NEXT:    .cfi_def_cfa_offset 0
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: constraint_S:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    #APP
 ; RV64-NEXT:    lui a0, %hi(var)
 ; RV64-NEXT:    addi a0, a0, %lo(var)
 ; RV64-NEXT:    #NO_APP
+; RV64-NEXT:    .cfi_def_cfa_offset 0
 ; RV64-NEXT:    ret
   %ret = tail call i8* asm "lui $0, %hi($1)\0Aaddi $0, $0, %lo($1)", "=r,S"(i32* nonnull @var)
   ret i8* %ret
 }
 
 ; Function Attrs: nofree nosync nounwind readnone
 define dso_local i8* @constraint_S_label() {
 ; RV32-LABEL: constraint_S_label:
 ; RV32:       # %bb.0: # %entry
 ; RV32-NEXT:  .Ltmp0: # Block address taken
 ; RV32-NEXT:  # %bb.1: # %L1
 ; RV32-NEXT:    #APP
 ; RV32-NEXT:    lui a0, %hi(.Ltmp0)
 ; RV32-NEXT:    addi a0, a0, %lo(.Ltmp0)
 ; RV32-NEXT:    #NO_APP
+; RV32-NEXT:    .cfi_def_cfa_offset 0
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: constraint_S_label:
 ; RV64:       # %bb.0: # %entry
 ; RV64-NEXT:  .Ltmp0: # Block address taken
 ; RV64-NEXT:  # %bb.1: # %L1
 ; RV64-NEXT:    #APP
 ; RV64-NEXT:    lui a0, %hi(.Ltmp0)
 ; RV64-NEXT:    addi a0, a0, %lo(.Ltmp0)
 ; RV64-NEXT:    #NO_APP
+; RV64-NEXT:    .cfi_def_cfa_offset 0
 ; RV64-NEXT:    ret
 entry:
   br label %L1
 
 L1:
   %ret = tail call i8* asm "lui $0, %hi($1)\0Aaddi $0, $0, %lo($1)", "=r,S"(i8* blockaddress(@constraint_S_label, %L1))
   ret i8* %ret
 }

llvm/test/CodeGen/RISCV/large-stack.ll

 ; RV32I-FPELIM:       # %bb.0:
 ; RV32I-FPELIM-NEXT:    lui a0, 74565
 ; RV32I-FPELIM-NEXT:    addi a0, a0, 1664
 ; RV32I-FPELIM-NEXT:    sub sp, sp, a0
 ; RV32I-FPELIM-NEXT:    .cfi_def_cfa_offset 305419904
 ; RV32I-FPELIM-NEXT:    lui a0, 74565
 ; RV32I-FPELIM-NEXT:    addi a0, a0, 1664
 ; RV32I-FPELIM-NEXT:    add sp, sp, a0
+; RV32I-FPELIM-NEXT:    .cfi_def_cfa_offset 0
 ; RV32I-FPELIM-NEXT:    ret
 ;
 ; RV32I-WITHFP-LABEL: test:
 ; RV32I-WITHFP:       # %bb.0:
 ; RV32I-WITHFP-NEXT:    addi sp, sp, -2032
 ; RV32I-WITHFP-NEXT:    .cfi_def_cfa_offset 2032
 ; RV32I-WITHFP-NEXT:    sw ra, 2028(sp) # 4-byte Folded Spill
 ; RV32I-WITHFP-NEXT:    sw s0, 2024(sp) # 4-byte Folded Spill
 ; RV32I-WITHFP-NEXT:    .cfi_offset ra, -4
 ; RV32I-WITHFP-NEXT:    .cfi_offset s0, -8
 ; RV32I-WITHFP-NEXT:    addi s0, sp, 2032
 ; RV32I-WITHFP-NEXT:    .cfi_def_cfa s0, 0
 ; RV32I-WITHFP-NEXT:    lui a0, 74565
 ; RV32I-WITHFP-NEXT:    addi a0, a0, -352
 ; RV32I-WITHFP-NEXT:    sub sp, sp, a0
 ; RV32I-WITHFP-NEXT:    lui a0, 74565
 ; RV32I-WITHFP-NEXT:    addi a0, a0, -352
 ; RV32I-WITHFP-NEXT:    add sp, sp, a0
 ; RV32I-WITHFP-NEXT:    lw s0, 2024(sp) # 4-byte Folded Reload
+; RV32I-WITHFP-NEXT:    .cfi_def_cfa sp, 2032
 ; RV32I-WITHFP-NEXT:    lw ra, 2028(sp) # 4-byte Folded Reload
+; RV32I-WITHFP-NEXT:    .cfi_restore ra
+; RV32I-WITHFP-NEXT:    .cfi_restore s0
 ; RV32I-WITHFP-NEXT:    addi sp, sp, 2032
+; RV32I-WITHFP-NEXT:    .cfi_def_cfa_offset 0
 ; RV32I-WITHFP-NEXT:    ret
   %tmp = alloca [ 305419896 x i8 ] , align 4
   ret void
 }
 
 ; This test case artificially produces register pressure which should force
 ; use of the emergency spill slot.
 

 ; RV32I-FPELIM-NEXT:    sw a0, 0(a1)
 ; RV32I-FPELIM-NEXT:    #APP
 ; RV32I-FPELIM-NEXT:    nop
 ; RV32I-FPELIM-EMPTY:
 ; RV32I-FPELIM-NEXT:    #NO_APP
 ; RV32I-FPELIM-NEXT:    lui a0, 97
 ; RV32I-FPELIM-NEXT:    addi a0, a0, 672
 ; RV32I-FPELIM-NEXT:    add sp, sp, a0
+; RV32I-FPELIM-NEXT:    .cfi_def_cfa_offset -2032
 ; RV32I-FPELIM-NEXT:    lw s1, 2024(sp) # 4-byte Folded Reload
 ; RV32I-FPELIM-NEXT:    lw s0, 2028(sp) # 4-byte Folded Reload
+; RV32I-FPELIM-NEXT:    .cfi_restore s0
+; RV32I-FPELIM-NEXT:    .cfi_restore s1
 ; RV32I-FPELIM-NEXT:    addi sp, sp, 2032
+; RV32I-FPELIM-NEXT:    .cfi_def_cfa_offset 0
 ; RV32I-FPELIM-NEXT:    ret
 ;
 ; RV32I-WITHFP-LABEL: test_emergency_spill_slot:
 ; RV32I-WITHFP:       # %bb.0:
 ; RV32I-WITHFP-NEXT:    addi sp, sp, -2032
 ; RV32I-WITHFP-NEXT:    .cfi_def_cfa_offset 2032
 ; RV32I-WITHFP-NEXT:    sw ra, 2028(sp) # 4-byte Folded Spill
 ; RV32I-WITHFP-NEXT:    sw s0, 2024(sp) # 4-byte Folded Spill

 ; RV32I-WITHFP-EMPTY:
 ; RV32I-WITHFP-NEXT:    #NO_APP
 ; RV32I-WITHFP-NEXT:    lui a0, 97
 ; RV32I-WITHFP-NEXT:    addi a0, a0, 688
 ; RV32I-WITHFP-NEXT:    add sp, sp, a0
 ; RV32I-WITHFP-NEXT:    lw s2, 2016(sp) # 4-byte Folded Reload
 ; RV32I-WITHFP-NEXT:    lw s1, 2020(sp) # 4-byte Folded Reload
 ; RV32I-WITHFP-NEXT:    lw s0, 2024(sp) # 4-byte Folded Reload
+; RV32I-WITHFP-NEXT:    .cfi_def_cfa sp, 2032
 ; RV32I-WITHFP-NEXT:    lw ra, 2028(sp) # 4-byte Folded Reload
+; RV32I-WITHFP-NEXT:    .cfi_restore ra
+; RV32I-WITHFP-NEXT:    .cfi_restore s0
+; RV32I-WITHFP-NEXT:    .cfi_restore s1
+; RV32I-WITHFP-NEXT:    .cfi_restore s2
 ; RV32I-WITHFP-NEXT:    addi sp, sp, 2032
+; RV32I-WITHFP-NEXT:    .cfi_def_cfa_offset 0
 ; RV32I-WITHFP-NEXT:    ret
   %data = alloca [ 100000 x i32 ] , align 4
   %ptr = getelementptr inbounds [100000 x i32], [100000 x i32]* %data, i32 0, i32 80000
   %1 = tail call { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } asm sideeffect "nop", "=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r,=r"()
   %asmresult0 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %1, 0
   %asmresult1 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %1, 1
   %asmresult2 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %1, 2
   %asmresult3 = extractvalue { i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32, i32 } %1, 3

llvm/test/CodeGen/RISCV/neg-abs.ll

 declare i64 @llvm.abs.i64(i64, i1 immarg)
 
 define i32 @neg_abs32(i32 %x) {
 ; RV32I-LABEL: neg_abs32:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    srai a1, a0, 31
 ; RV32I-NEXT:    xor a0, a0, a1
 ; RV32I-NEXT:    sub a0, a1, a0
+; RV32I-NEXT:    .cfi_def_cfa_offset 0
 ; RV32I-NEXT:    ret
 ;
 ; RV32IBT-LABEL: neg_abs32:
 ; RV32IBT:       # %bb.0:
 ; RV32IBT-NEXT:    srai a1, a0, 31
 ; RV32IBT-NEXT:    xor a0, a0, a1
 ; RV32IBT-NEXT:    sub a0, a1, a0
+; RV32IBT-NEXT:    .cfi_def_cfa_offset 0
 ; RV32IBT-NEXT:    ret
 ;
 ; RV64I-LABEL: neg_abs32:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    sraiw a1, a0, 31
 ; RV64I-NEXT:    xor a0, a0, a1
 ; RV64I-NEXT:    subw a0, a1, a0
+; RV64I-NEXT:    .cfi_def_cfa_offset 0
 ; RV64I-NEXT:    ret
 ;
 ; RV64IBT-LABEL: neg_abs32:
 ; RV64IBT:       # %bb.0:
 ; RV64IBT-NEXT:    sraiw a1, a0, 31
 ; RV64IBT-NEXT:    xor a0, a0, a1
 ; RV64IBT-NEXT:    subw a0, a1, a0
+; RV64IBT-NEXT:    .cfi_def_cfa_offset 0
 ; RV64IBT-NEXT:    ret
   %abs = tail call i32 @llvm.abs.i32(i32 %x, i1 true)
   %neg = sub nsw i32 0, %abs
   ret i32 %neg
 }
 
 define i32 @select_neg_abs32(i32 %x) {
 ; RV32I-LABEL: select_neg_abs32:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    srai a1, a0, 31
 ; RV32I-NEXT:    xor a0, a0, a1
 ; RV32I-NEXT:    sub a0, a1, a0
+; RV32I-NEXT:    .cfi_def_cfa_offset 0
 ; RV32I-NEXT:    ret
 ;
 ; RV32IBT-LABEL: select_neg_abs32:
 ; RV32IBT:       # %bb.0:
 ; RV32IBT-NEXT:    srai a1, a0, 31
 ; RV32IBT-NEXT:    xor a0, a0, a1
 ; RV32IBT-NEXT:    sub a0, a1, a0
+; RV32IBT-NEXT:    .cfi_def_cfa_offset 0
 ; RV32IBT-NEXT:    ret
 ;
 ; RV64I-LABEL: select_neg_abs32:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    sraiw a1, a0, 31
 ; RV64I-NEXT:    xor a0, a0, a1
 ; RV64I-NEXT:    subw a0, a1, a0
+; RV64I-NEXT:    .cfi_def_cfa_offset 0
 ; RV64I-NEXT:    ret
 ;
 ; RV64IBT-LABEL: select_neg_abs32:
 ; RV64IBT:       # %bb.0:
 ; RV64IBT-NEXT:    sraiw a1, a0, 31
 ; RV64IBT-NEXT:    xor a0, a0, a1
 ; RV64IBT-NEXT:    subw a0, a1, a0
+; RV64IBT-NEXT:    .cfi_def_cfa_offset 0
 ; RV64IBT-NEXT:    ret
   %1 = icmp slt i32 %x, 0
   %2 = sub nsw i32 0, %x
   %3 = select i1 %1, i32 %x, i32 %2
   ret i32 %3
 }
 
 define i64 @neg_abs64(i64 %x) {
 ; RV32I-LABEL: neg_abs64:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    srai a2, a1, 31
 ; RV32I-NEXT:    xor a0, a0, a2
 ; RV32I-NEXT:    sltu a3, a2, a0
 ; RV32I-NEXT:    xor a1, a1, a2
 ; RV32I-NEXT:    sub a1, a2, a1
 ; RV32I-NEXT:    sub a1, a1, a3
 ; RV32I-NEXT:    sub a0, a2, a0
+; RV32I-NEXT:    .cfi_def_cfa_offset 0
 ; RV32I-NEXT:    ret
 ;
 ; RV32IBT-LABEL: neg_abs64:
 ; RV32IBT:       # %bb.0:
 ; RV32IBT-NEXT:    srai a2, a1, 31
 ; RV32IBT-NEXT:    xor a0, a0, a2
 ; RV32IBT-NEXT:    sltu a3, a2, a0
 ; RV32IBT-NEXT:    xor a1, a1, a2
 ; RV32IBT-NEXT:    sub a1, a2, a1
 ; RV32IBT-NEXT:    sub a1, a1, a3
 ; RV32IBT-NEXT:    sub a0, a2, a0
+; RV32IBT-NEXT:    .cfi_def_cfa_offset 0
 ; RV32IBT-NEXT:    ret
 ;
 ; RV64I-LABEL: neg_abs64:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    srai a1, a0, 63
 ; RV64I-NEXT:    xor a0, a0, a1
 ; RV64I-NEXT:    sub a0, a1, a0
+; RV64I-NEXT:    .cfi_def_cfa_offset 0
 ; RV64I-NEXT:    ret
 ;
 ; RV64IBT-LABEL: neg_abs64:
 ; RV64IBT:       # %bb.0:
 ; RV64IBT-NEXT:    srai a1, a0, 63
 ; RV64IBT-NEXT:    xor a0, a0, a1
 ; RV64IBT-NEXT:    sub a0, a1, a0
+; RV64IBT-NEXT:    .cfi_def_cfa_offset 0
 ; RV64IBT-NEXT:    ret
   %abs = tail call i64 @llvm.abs.i64(i64 %x, i1 true)
   %neg = sub nsw i64 0, %abs
   ret i64 %neg
 }
 
 define i64 @select_neg_abs64(i64 %x) {
 ; RV32I-LABEL: select_neg_abs64:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    srai a2, a1, 31
 ; RV32I-NEXT:    xor a0, a0, a2
 ; RV32I-NEXT:    sltu a3, a2, a0
 ; RV32I-NEXT:    xor a1, a1, a2
 ; RV32I-NEXT:    sub a1, a2, a1
 ; RV32I-NEXT:    sub a1, a1, a3
 ; RV32I-NEXT:    sub a0, a2, a0
+; RV32I-NEXT:    .cfi_def_cfa_offset 0
 ; RV32I-NEXT:    ret
 ;
 ; RV32IBT-LABEL: select_neg_abs64:
 ; RV32IBT:       # %bb.0:
 ; RV32IBT-NEXT:    srai a2, a1, 31
 ; RV32IBT-NEXT:    xor a0, a0, a2
 ; RV32IBT-NEXT:    sltu a3, a2, a0
 ; RV32IBT-NEXT:    xor a1, a1, a2
 ; RV32IBT-NEXT:    sub a1, a2, a1
 ; RV32IBT-NEXT:    sub a1, a1, a3
 ; RV32IBT-NEXT:    sub a0, a2, a0
+; RV32IBT-NEXT:    .cfi_def_cfa_offset 0
 ; RV32IBT-NEXT:    ret
 ;
 ; RV64I-LABEL: select_neg_abs64:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    srai a1, a0, 63
 ; RV64I-NEXT:    xor a0, a0, a1
 ; RV64I-NEXT:    sub a0, a1, a0
+; RV64I-NEXT:    .cfi_def_cfa_offset 0
 ; RV64I-NEXT:    ret
 ;
 ; RV64IBT-LABEL: select_neg_abs64:
 ; RV64IBT:       # %bb.0:
 ; RV64IBT-NEXT:    srai a1, a0, 63
 ; RV64IBT-NEXT:    xor a0, a0, a1
 ; RV64IBT-NEXT:    sub a0, a1, a0
+; RV64IBT-NEXT:    .cfi_def_cfa_offset 0
 ; RV64IBT-NEXT:    ret
   %1 = icmp slt i64 %x, 0
   %2 = sub nsw i64 0, %x
   %3 = select i1 %1, i64 %x, i64 %2
   ret i64 %3
 }
 

llvm/test/CodeGen/RISCV/patchable-function-entry.ll

 ; CHECK-NOT:   .section __patchable_function_entries
   ret void
 }
 
 define void @f1() "patchable-function-entry"="1" {
 ; CHECK-LABEL: f1:
 ; CHECK-NEXT: .Lfunc_begin1:
 ; NORVC:         addi zero, zero, 0
+; NORVC-NEXT:      cfi_def_cfa_offset 0
 ; NORVC-NEXT:    jalr zero, 0(ra)
 ; RVC:           c.nop
+; RVC-NEXT:      cfi_def_cfa_offset 0
 ; RVC-NEXT:      c.jr ra
 ; CHECK:       .section __patchable_function_entries,"awo",@progbits,f1{{$}}
 ; 32:          .p2align 2
 ; 32-NEXT:     .word .Lfunc_begin1
 ; 64:          .p2align 3
 ; 64-NEXT:     .quad .Lfunc_begin1
   ret void
 }
 
 $f5 = comdat any
 define void @f5() "patchable-function-entry"="5" comdat {
 ; CHECK-LABEL: f5:
 ; CHECK-NEXT:  .Lfunc_begin2:
 ; NORVC-COUNT-5: addi zero, zero, 0
+; NORVC-NEXT:      cfi_def_cfa_offset 0
 ; NORVC-NEXT:    jalr zero, 0(ra)
 ; RVC-COUNT-5:   c.nop
+; RVC-NEXT:      cfi_def_cfa_offset 0
 ; RVC-NEXT:      c.jr ra
 ; CHECK:       .section __patchable_function_entries,"aGwo",@progbits,f5,comdat,f5{{$}}
 ; RV32:        .p2align 2
 ; RV32-NEXT:   .word .Lfunc_begin2
 ; RV64:        .p2align 3
 ; RV64-NEXT:   .quad .Lfunc_begin2
   ret void
 }

llvm/test/CodeGen/RISCV/rv32zba.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -mattr=+m -verify-machineinstrs < %s \
 ; RUN:   | FileCheck %s -check-prefix=RV32I
 ; RUN: llc -mtriple=riscv32 -mattr=+m,+experimental-zba -verify-machineinstrs < %s \
 ; RUN:   | FileCheck %s -check-prefix=RV32ZBA
 
 define signext i16 @sh1add(i64 %0, i16* %1) {
 ; RV32I-LABEL: sh1add:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    slli a0, a0, 1
 ; RV32I-NEXT:    add a0, a2, a0
 ; RV32I-NEXT:    lh a0, 0(a0)
+; RV32I-NEXT:    .cfi_def_cfa_offset 0
 ; RV32I-NEXT:    ret
 ;
 ; RV32ZBA-LABEL: sh1add:
 ; RV32ZBA:       # %bb.0:
 ; RV32ZBA-NEXT:    sh1add a0, a0, a2
 ; RV32ZBA-NEXT:    lh a0, 0(a0)
+; RV32ZBA-NEXT:    .cfi_def_cfa_offset 0
 ; RV32ZBA-NEXT:    ret
   %3 = getelementptr inbounds i16, i16* %1, i64 %0
   %4 = load i16, i16* %3
   ret i16 %4
 }
 
 define i32 @sh2add(i64 %0, i32* %1) {
 ; RV32I-LABEL: sh2add:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    slli a0, a0, 2
 ; RV32I-NEXT:    add a0, a2, a0
 ; RV32I-NEXT:    lw a0, 0(a0)
+; RV32I-NEXT:    .cfi_def_cfa_offset 0
 ; RV32I-NEXT:    ret
 ;
 ; RV32ZBA-LABEL: sh2add:
 ; RV32ZBA:       # %bb.0:
 ; RV32ZBA-NEXT:    sh2add a0, a0, a2
 ; RV32ZBA-NEXT:    lw a0, 0(a0)
+; RV32ZBA-NEXT:    .cfi_def_cfa_offset 0
 ; RV32ZBA-NEXT:    ret
   %3 = getelementptr inbounds i32, i32* %1, i64 %0
   %4 = load i32, i32* %3
   ret i32 %4
 }
 
 define i64 @sh3add(i64 %0, i64* %1) {
 ; RV32I-LABEL: sh3add:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    slli a0, a0, 3
 ; RV32I-NEXT:    add a1, a2, a0
 ; RV32I-NEXT:    lw a0, 0(a1)
 ; RV32I-NEXT:    lw a1, 4(a1)
+; RV32I-NEXT:    .cfi_def_cfa_offset 0
 ; RV32I-NEXT:    ret
 ;
 ; RV32ZBA-LABEL: sh3add:
 ; RV32ZBA:       # %bb.0:
 ; RV32ZBA-NEXT:    sh3add a1, a0, a2
 ; RV32ZBA-NEXT:    lw a0, 0(a1)
 ; RV32ZBA-NEXT:    lw a1, 4(a1)
+; RV32ZBA-NEXT:    .cfi_def_cfa_offset 0
 ; RV32ZBA-NEXT:    ret
   %3 = getelementptr inbounds i64, i64* %1, i64 %0
   %4 = load i64, i64* %3
   ret i64 %4
 }
 
 define i32 @addmul6(i32 %a, i32 %b) {
 ; RV32I-LABEL: addmul6:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi a2, zero, 6
 ; RV32I-NEXT:    mul a0, a0, a2
 ; RV32I-NEXT:    add a0, a0, a1
+; RV32I-NEXT:    .cfi_def_cfa_offset 0
 ; RV32I-NEXT:    ret
 ;
 ; RV32ZBA-LABEL: addmul6:
 ; RV32ZBA:       # %bb.0:
 ; RV32ZBA-NEXT:    sh1add a0, a0, a0
 ; RV32ZBA-NEXT:    sh1add a0, a0, a1
+; RV32ZBA-NEXT:    .cfi_def_cfa_offset 0
 ; RV32ZBA-NEXT:    ret
   %c = mul i32 %a, 6
   %d = add i32 %c, %b
   ret i32 %d
 }
 
 define i32 @addmul10(i32 %a, i32 %b) {
 ; RV32I-LABEL: addmul10:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi a2, zero, 10
 ; RV32I-NEXT:    mul a0, a0, a2
 ; RV32I-NEXT:    add a0, a0, a1
+; RV32I-NEXT:    .cfi_def_cfa_offset 0
 ; RV32I-NEXT:    ret
 ;
 ; RV32ZBA-LABEL: addmul10:
 ; RV32ZBA:       # %bb.0:
 ; RV32ZBA-NEXT:    sh2add a0, a0, a0
 ; RV32ZBA-NEXT:    sh1add a0, a0, a1
+; RV32ZBA-NEXT:    .cfi_def_cfa_offset 0
 ; RV32ZBA-NEXT:    ret
   %c = mul i32 %a, 10
   %d = add i32 %c, %b
   ret i32 %d
 }
 
 define i32 @addmul12(i32 %a, i32 %b) {
 ; RV32I-LABEL: addmul12:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi a2, zero, 12
 ; RV32I-NEXT:    mul a0, a0, a2
 ; RV32I-NEXT:    add a0, a0, a1
+; RV32I-NEXT:    .cfi_def_cfa_offset 0
 ; RV32I-NEXT:    ret
 ;
 ; RV32ZBA-LABEL: addmul12:
 ; RV32ZBA:       # %bb.0:
 ; RV32ZBA-NEXT:    sh1add a0, a0, a0
 ; RV32ZBA-NEXT:    sh2add a0, a0, a1
+; RV32ZBA-NEXT:    .cfi_def_cfa_offset 0
 ; RV32ZBA-NEXT:    ret
   %c = mul i32 %a, 12
   %d = add i32 %c, %b
   ret i32 %d
 }
 
 define i32 @addmul18(i32 %a, i32 %b) {
 ; RV32I-LABEL: addmul18:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi a2, zero, 18
 ; RV32I-NEXT:    mul a0, a0, a2
 ; RV32I-NEXT:    add a0, a0, a1
+; RV32I-NEXT:    .cfi_def_cfa_offset 0
 ; RV32I-NEXT:    ret
 ;
 ; RV32ZBA-LABEL: addmul18:
 ; RV32ZBA:       # %bb.0:
 ; RV32ZBA-NEXT:    sh3add a0, a0, a0
 ; RV32ZBA-NEXT:    sh1add a0, a0, a1
+; RV32ZBA-NEXT:    .cfi_def_cfa_offset 0
 ; RV32ZBA-NEXT:    ret
   %c = mul i32 %a, 18
   %d = add i32 %c, %b
   ret i32 %d
 }
 
 define i32 @addmul20(i32 %a, i32 %b) {
 ; RV32I-LABEL: addmul20:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi a2, zero, 20
 ; RV32I-NEXT:    mul a0, a0, a2
 ; RV32I-NEXT:    add a0, a0, a1
+; RV32I-NEXT:    .cfi_def_cfa_offset 0
 ; RV32I-NEXT:    ret
 ;
 ; RV32ZBA-LABEL: addmul20:
 ; RV32ZBA:       # %bb.0:
 ; RV32ZBA-NEXT:    sh2add a0, a0, a0
 ; RV32ZBA-NEXT:    sh2add a0, a0, a1
+; RV32ZBA-NEXT:    .cfi_def_cfa_offset 0
 ; RV32ZBA-NEXT:    ret
   %c = mul i32 %a, 20
   %d = add i32 %c, %b
   ret i32 %d
 }
 
 define i32 @addmul24(i32 %a, i32 %b) {
 ; RV32I-LABEL: addmul24:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi a2, zero, 24
 ; RV32I-NEXT:    mul a0, a0, a2
 ; RV32I-NEXT:    add a0, a0, a1
+; RV32I-NEXT:    .cfi_def_cfa_offset 0
 ; RV32I-NEXT:    ret
 ;
 ; RV32ZBA-LABEL: addmul24:
 ; RV32ZBA:       # %bb.0:
 ; RV32ZBA-NEXT:    sh1add a0, a0, a0
 ; RV32ZBA-NEXT:    sh3add a0, a0, a1
+; RV32ZBA-NEXT:    .cfi_def_cfa_offset 0
 ; RV32ZBA-NEXT:    ret
   %c = mul i32 %a, 24
   %d = add i32 %c, %b
   ret i32 %d
 }
 
 define i32 @addmul36(i32 %a, i32 %b) {
 ; RV32I-LABEL: addmul36:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi a2, zero, 36
 ; RV32I-NEXT:    mul a0, a0, a2
 ; RV32I-NEXT:    add a0, a0, a1
+; RV32I-NEXT:    .cfi_def_cfa_offset 0
 ; RV32I-NEXT:    ret
 ;
 ; RV32ZBA-LABEL: addmul36:
 ; RV32ZBA:       # %bb.0:
 ; RV32ZBA-NEXT:    sh3add a0, a0, a0
 ; RV32ZBA-NEXT:    sh2add a0, a0, a1
+; RV32ZBA-NEXT:    .cfi_def_cfa_offset 0
 ; RV32ZBA-NEXT:    ret
   %c = mul i32 %a, 36
   %d = add i32 %c, %b
   ret i32 %d
 }
 
 define i32 @addmul40(i32 %a, i32 %b) {
 ; RV32I-LABEL: addmul40:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi a2, zero, 40
 ; RV32I-NEXT:    mul a0, a0, a2
 ; RV32I-NEXT:    add a0, a0, a1
+; RV32I-NEXT:    .cfi_def_cfa_offset 0
 ; RV32I-NEXT:    ret
 ;
 ; RV32ZBA-LABEL: addmul40:
 ; RV32ZBA:       # %bb.0:
 ; RV32ZBA-NEXT:    sh2add a0, a0, a0
 ; RV32ZBA-NEXT:    sh3add a0, a0, a1
+; RV32ZBA-NEXT:    .cfi_def_cfa_offset 0
 ; RV32ZBA-NEXT:    ret
   %c = mul i32 %a, 40
   %d = add i32 %c, %b
   ret i32 %d
 }
 
 define i32 @addmul72(i32 %a, i32 %b) {
 ; RV32I-LABEL: addmul72:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi a2, zero, 72
 ; RV32I-NEXT:    mul a0, a0, a2
 ; RV32I-NEXT:    add a0, a0, a1
+; RV32I-NEXT:    .cfi_def_cfa_offset 0
 ; RV32I-NEXT:    ret
 ;
 ; RV32ZBA-LABEL: addmul72:
 ; RV32ZBA:       # %bb.0:
 ; RV32ZBA-NEXT:    sh3add a0, a0, a0
 ; RV32ZBA-NEXT:    sh3add a0, a0, a1
+; RV32ZBA-NEXT:    .cfi_def_cfa_offset 0
 ; RV32ZBA-NEXT:    ret
   %c = mul i32 %a, 72
   %d = add i32 %c, %b
   ret i32 %d
 }
 
 define i32 @mul96(i32 %a) {
 ; RV32I-LABEL: mul96:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi a1, zero, 96
 ; RV32I-NEXT:    mul a0, a0, a1
+; RV32I-NEXT:    .cfi_def_cfa_offset 0
 ; RV32I-NEXT:    ret
 ;
 ; RV32ZBA-LABEL: mul96:
 ; RV32ZBA:       # %bb.0:
 ; RV32ZBA-NEXT:    sh1add a0, a0, a0
 ; RV32ZBA-NEXT:    slli a0, a0, 5
+; RV32ZBA-NEXT:    .cfi_def_cfa_offset 0
 ; RV32ZBA-NEXT:    ret
   %c = mul i32 %a, 96
   ret i32 %c
 }
 
 define i32 @mul160(i32 %a) {
 ; RV32I-LABEL: mul160:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi a1, zero, 160
 ; RV32I-NEXT:    mul a0, a0, a1
+; RV32I-NEXT:    .cfi_def_cfa_offset 0
 ; RV32I-NEXT:    ret
 ;
 ; RV32ZBA-LABEL: mul160:
 ; RV32ZBA:       # %bb.0:
 ; RV32ZBA-NEXT:    sh2add a0, a0, a0
 ; RV32ZBA-NEXT:    slli a0, a0, 5
+; RV32ZBA-NEXT:    .cfi_def_cfa_offset 0
 ; RV32ZBA-NEXT:    ret
   %c = mul i32 %a, 160
   ret i32 %c
 }
 
 define i32 @mul288(i32 %a) {
 ; RV32I-LABEL: mul288:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi a1, zero, 288
 ; RV32I-NEXT:    mul a0, a0, a1
+; RV32I-NEXT:    .cfi_def_cfa_offset 0
 ; RV32I-NEXT:    ret
 ;
 ; RV32ZBA-LABEL: mul288:
 ; RV32ZBA:       # %bb.0:
 ; RV32ZBA-NEXT:    sh3add a0, a0, a0
 ; RV32ZBA-NEXT:    slli a0, a0, 5
+; RV32ZBA-NEXT:    .cfi_def_cfa_offset 0
 ; RV32ZBA-NEXT:    ret
   %c = mul i32 %a, 288
   ret i32 %c
 }
 
 define i32 @mul258(i32 %a) {
 ; RV32I-LABEL: mul258:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi a1, zero, 258
 ; RV32I-NEXT:    mul a0, a0, a1
+; RV32I-NEXT:    .cfi_def_cfa_offset 0
 ; RV32I-NEXT:    ret
 ;
 ; RV32ZBA-LABEL: mul258:
 ; RV32ZBA:       # %bb.0:
 ; RV32ZBA-NEXT:    addi a1, zero, 258
 ; RV32ZBA-NEXT:    mul a0, a0, a1
+; RV32ZBA-NEXT:    .cfi_def_cfa_offset 0
 ; RV32ZBA-NEXT:    ret
   %c = mul i32 %a, 258
   ret i32 %c
 }
 
 define i32 @mul260(i32 %a) {
 ; RV32I-LABEL: mul260:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi a1, zero, 260
 ; RV32I-NEXT:    mul a0, a0, a1
+; RV32I-NEXT:    .cfi_def_cfa_offset 0
 ; RV32I-NEXT:    ret
 ;
 ; RV32ZBA-LABEL: mul260:
 ; RV32ZBA:       # %bb.0:
 ; RV32ZBA-NEXT:    addi a1, zero, 260
 ; RV32ZBA-NEXT:    mul a0, a0, a1
+; RV32ZBA-NEXT:    .cfi_def_cfa_offset 0
 ; RV32ZBA-NEXT:    ret
   %c = mul i32 %a, 260
   ret i32 %c
 }
 
 define i32 @mul264(i32 %a) {
 ; RV32I-LABEL: mul264:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi a1, zero, 264
 ; RV32I-NEXT:    mul a0, a0, a1
+; RV32I-NEXT:    .cfi_def_cfa_offset 0
 ; RV32I-NEXT:    ret
 ;
 ; RV32ZBA-LABEL: mul264:
 ; RV32ZBA:       # %bb.0:
 ; RV32ZBA-NEXT:    addi a1, zero, 264
 ; RV32ZBA-NEXT:    mul a0, a0, a1
+; RV32ZBA-NEXT:    .cfi_def_cfa_offset 0
 ; RV32ZBA-NEXT:    ret
   %c = mul i32 %a, 264
   ret i32 %c
 }
 
 define i32 @mul11(i32 %a) {
 ; RV32I-LABEL: mul11:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi a1, zero, 11
 ; RV32I-NEXT:    mul a0, a0, a1
+; RV32I-NEXT:    .cfi_def_cfa_offset 0
 ; RV32I-NEXT:    ret
 ;
 ; RV32ZBA-LABEL: mul11:
 ; RV32ZBA:       # %bb.0:
 ; RV32ZBA-NEXT:    sh2add a1, a0, a0
 ; RV32ZBA-NEXT:    sh1add a0, a1, a0
+; RV32ZBA-NEXT:    .cfi_def_cfa_offset 0
 ; RV32ZBA-NEXT:    ret
   %c = mul i32 %a, 11
   ret i32 %c
 }
 
 define i32 @mul19(i32 %a) {
 ; RV32I-LABEL: mul19:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi a1, zero, 19
 ; RV32I-NEXT:    mul a0, a0, a1
+; RV32I-NEXT:    .cfi_def_cfa_offset 0
 ; RV32I-NEXT:    ret
 ;
 ; RV32ZBA-LABEL: mul19:
 ; RV32ZBA:       # %bb.0:
 ; RV32ZBA-NEXT:    sh3add a1, a0, a0
 ; RV32ZBA-NEXT:    sh1add a0, a1, a0
+; RV32ZBA-NEXT:    .cfi_def_cfa_offset 0
 ; RV32ZBA-NEXT:    ret
   %c = mul i32 %a, 19
   ret i32 %c
 }
 
 define i32 @mul13(i32 %a) {
 ; RV32I-LABEL: mul13:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi a1, zero, 13
 ; RV32I-NEXT:    mul a0, a0, a1
+; RV32I-NEXT:    .cfi_def_cfa_offset 0
 ; RV32I-NEXT:    ret
 ;
 ; RV32ZBA-LABEL: mul13:
 ; RV32ZBA:       # %bb.0:
 ; RV32ZBA-NEXT:    sh1add a1, a0, a0
 ; RV32ZBA-NEXT:    sh2add a0, a1, a0
+; RV32ZBA-NEXT:    .cfi_def_cfa_offset 0
 ; RV32ZBA-NEXT:    ret
   %c = mul i32 %a, 13
   ret i32 %c
 }
 
 define i32 @mul21(i32 %a) {
 ; RV32I-LABEL: mul21:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi a1, zero, 21
 ; RV32I-NEXT:    mul a0, a0, a1
+; RV32I-NEXT:    .cfi_def_cfa_offset 0
 ; RV32I-NEXT:    ret
 ;
 ; RV32ZBA-LABEL: mul21:
 ; RV32ZBA:       # %bb.0:
 ; RV32ZBA-NEXT:    sh2add a1, a0, a0
 ; RV32ZBA-NEXT:    sh2add a0, a1, a0
+; RV32ZBA-NEXT:    .cfi_def_cfa_offset 0
 ; RV32ZBA-NEXT:    ret
   %c = mul i32 %a, 21
   ret i32 %c
 }
 
 define i32 @mul37(i32 %a) {
 ; RV32I-LABEL: mul37:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi a1, zero, 37
 ; RV32I-NEXT:    mul a0, a0, a1
+; RV32I-NEXT:    .cfi_def_cfa_offset 0
 ; RV32I-NEXT:    ret
 ;
 ; RV32ZBA-LABEL: mul37:
 ; RV32ZBA:       # %bb.0:
 ; RV32ZBA-NEXT:    sh3add a1, a0, a0
 ; RV32ZBA-NEXT:    sh2add a0, a1, a0
+; RV32ZBA-NEXT:    .cfi_def_cfa_offset 0
 ; RV32ZBA-NEXT:    ret
   %c = mul i32 %a, 37
   ret i32 %c
 }
 
 define i32 @mul25(i32 %a) {
 ; RV32I-LABEL: mul25:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi a1, zero, 25
 ; RV32I-NEXT:    mul a0, a0, a1
+; RV32I-NEXT:    .cfi_def_cfa_offset 0
 ; RV32I-NEXT:    ret
 ;
 ; RV32ZBA-LABEL: mul25:
 ; RV32ZBA:       # %bb.0:
 ; RV32ZBA-NEXT:    sh1add a1, a0, a0
 ; RV32ZBA-NEXT:    sh3add a0, a1, a0
+; RV32ZBA-NEXT:    .cfi_def_cfa_offset 0
 ; RV32ZBA-NEXT:    ret
   %c = mul i32 %a, 25
   ret i32 %c
 }
 
 define i32 @mul41(i32 %a) {
 ; RV32I-LABEL: mul41:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi a1, zero, 41
 ; RV32I-NEXT:    mul a0, a0, a1
+; RV32I-NEXT:    .cfi_def_cfa_offset 0
 ; RV32I-NEXT:    ret
 ;
 ; RV32ZBA-LABEL: mul41:
 ; RV32ZBA:       # %bb.0:
 ; RV32ZBA-NEXT:    sh2add a1, a0, a0
 ; RV32ZBA-NEXT:    sh3add a0, a1, a0
+; RV32ZBA-NEXT:    .cfi_def_cfa_offset 0
 ; RV32ZBA-NEXT:    ret
   %c = mul i32 %a, 41
   ret i32 %c
 }
 
 define i32 @mul73(i32 %a) {
 ; RV32I-LABEL: mul73:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi a1, zero, 73
 ; RV32I-NEXT:    mul a0, a0, a1
+; RV32I-NEXT:    .cfi_def_cfa_offset 0
 ; RV32I-NEXT:    ret
 ;
 ; RV32ZBA-LABEL: mul73:
 ; RV32ZBA:       # %bb.0:
 ; RV32ZBA-NEXT:    sh3add a1, a0, a0
 ; RV32ZBA-NEXT:    sh3add a0, a1, a0
+; RV32ZBA-NEXT:    .cfi_def_cfa_offset 0
 ; RV32ZBA-NEXT:    ret
   %c = mul i32 %a, 73
   ret i32 %c
 }
 
 define i32 @mul27(i32 %a) {
 ; RV32I-LABEL: mul27:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi a1, zero, 27
 ; RV32I-NEXT:    mul a0, a0, a1
+; RV32I-NEXT:    .cfi_def_cfa_offset 0
 ; RV32I-NEXT:    ret
 ;
 ; RV32ZBA-LABEL: mul27:
 ; RV32ZBA:       # %bb.0:
 ; RV32ZBA-NEXT:    sh3add a0, a0, a0
 ; RV32ZBA-NEXT:    sh1add a0, a0, a0
+; RV32ZBA-NEXT:    .cfi_def_cfa_offset 0
 ; RV32ZBA-NEXT:    ret
   %c = mul i32 %a, 27
   ret i32 %c
 }
 
 define i32 @mul45(i32 %a) {
 ; RV32I-LABEL: mul45:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi a1, zero, 45
 ; RV32I-NEXT:    mul a0, a0, a1
+; RV32I-NEXT:    .cfi_def_cfa_offset 0
 ; RV32I-NEXT:    ret
 ;
 ; RV32ZBA-LABEL: mul45:
 ; RV32ZBA:       # %bb.0:
 ; RV32ZBA-NEXT:    sh3add a0, a0, a0
 ; RV32ZBA-NEXT:    sh2add a0, a0, a0
+; RV32ZBA-NEXT:    .cfi_def_cfa_offset 0
 ; RV32ZBA-NEXT:    ret
   %c = mul i32 %a, 45
   ret i32 %c
 }
 
 define i32 @mul81(i32 %a) {
 ; RV32I-LABEL: mul81:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi a1, zero, 81
 ; RV32I-NEXT:    mul a0, a0, a1
+; RV32I-NEXT:    .cfi_def_cfa_offset 0
 ; RV32I-NEXT:    ret
 ;
 ; RV32ZBA-LABEL: mul81:
 ; RV32ZBA:       # %bb.0:
 ; RV32ZBA-NEXT:    sh3add a0, a0, a0
 ; RV32ZBA-NEXT:    sh3add a0, a0, a0
+; RV32ZBA-NEXT:    .cfi_def_cfa_offset 0
 ; RV32ZBA-NEXT:    ret
   %c = mul i32 %a, 81
   ret i32 %c
 }
 
 define i32 @mul4098(i32 %a) {
 ; RV32I-LABEL: mul4098:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    lui a1, 1
 ; RV32I-NEXT:    addi a1, a1, 2
 ; RV32I-NEXT:    mul a0, a0, a1
+; RV32I-NEXT:    .cfi_def_cfa_offset 0
 ; RV32I-NEXT:    ret
 ;
 ; RV32ZBA-LABEL: mul4098:
 ; RV32ZBA:       # %bb.0:
 ; RV32ZBA-NEXT:    slli a1, a0, 12
 ; RV32ZBA-NEXT:    sh1add a0, a0, a1
+; RV32ZBA-NEXT:    .cfi_def_cfa_offset 0
 ; RV32ZBA-NEXT:    ret
   %c = mul i32 %a, 4098
   ret i32 %c
 }
 
 define i32 @mul4100(i32 %a) {
 ; RV32I-LABEL: mul4100:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    lui a1, 1
 ; RV32I-NEXT:    addi a1, a1, 4
 ; RV32I-NEXT:    mul a0, a0, a1
+; RV32I-NEXT:    .cfi_def_cfa_offset 0
 ; RV32I-NEXT:    ret
 ;
 ; RV32ZBA-LABEL: mul4100:
 ; RV32ZBA:       # %bb.0:
 ; RV32ZBA-NEXT:    slli a1, a0, 12
 ; RV32ZBA-NEXT:    sh2add a0, a0, a1
+; RV32ZBA-NEXT:    .cfi_def_cfa_offset 0
 ; RV32ZBA-NEXT:    ret
   %c = mul i32 %a, 4100
   ret i32 %c
 }
 
 define i32 @mul4104(i32 %a) {
 ; RV32I-LABEL: mul4104:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    lui a1, 1
 ; RV32I-NEXT:    addi a1, a1, 8
 ; RV32I-NEXT:    mul a0, a0, a1
+; RV32I-NEXT:    .cfi_def_cfa_offset 0
 ; RV32I-NEXT:    ret
 ;
 ; RV32ZBA-LABEL: mul4104:
 ; RV32ZBA:       # %bb.0:
 ; RV32ZBA-NEXT:    slli a1, a0, 12
 ; RV32ZBA-NEXT:    sh3add a0, a0, a1
+; RV32ZBA-NEXT:    .cfi_def_cfa_offset 0
 ; RV32ZBA-NEXT:    ret
   %c = mul i32 %a, 4104
   ret i32 %c
 }
 
 define i32 @add4104(i32 %a) {
 ; RV32I-LABEL: add4104:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    lui a1, 1
 ; RV32I-NEXT:    addi a1, a1, 8
 ; RV32I-NEXT:    add a0, a0, a1
+; RV32I-NEXT:    .cfi_def_cfa_offset 0
 ; RV32I-NEXT:    ret
 ;
 ; RV32ZBA-LABEL: add4104:
 ; RV32ZBA:       # %bb.0:
 ; RV32ZBA-NEXT:    addi a1, zero, 1026
 ; RV32ZBA-NEXT:    sh2add a0, a1, a0
+; RV32ZBA-NEXT:    .cfi_def_cfa_offset 0
 ; RV32ZBA-NEXT:    ret
   %c = add i32 %a, 4104
   ret i32 %c
 }
 
 define i32 @add8208(i32 %a) {
 ; RV32I-LABEL: add8208:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    lui a1, 2
 ; RV32I-NEXT:    addi a1, a1, 16
 ; RV32I-NEXT:    add a0, a0, a1
+; RV32I-NEXT:    .cfi_def_cfa_offset 0
 ; RV32I-NEXT:    ret
 ;
 ; RV32ZBA-LABEL: add8208:
 ; RV32ZBA:       # %bb.0:
 ; RV32ZBA-NEXT:    addi a1, zero, 1026
 ; RV32ZBA-NEXT:    sh3add a0, a1, a0
+; RV32ZBA-NEXT:    .cfi_def_cfa_offset 0
 ; RV32ZBA-NEXT:    ret
   %c = add i32 %a, 8208
   ret i32 %c
 }
 
 define i32 @addshl_5_6(i32 %a, i32 %b) {
 ; RV32I-LABEL: addshl_5_6:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    slli a0, a0, 5
 ; RV32I-NEXT:    slli a1, a1, 6
 ; RV32I-NEXT:    add a0, a0, a1
+; RV32I-NEXT:    .cfi_def_cfa_offset 0
 ; RV32I-NEXT:    ret
 ;
 ; RV32ZBA-LABEL: addshl_5_6:
 ; RV32ZBA:       # %bb.0:
 ; RV32ZBA-NEXT:    sh1add a0, a1, a0
 ; RV32ZBA-NEXT:    slli a0, a0, 5
+; RV32ZBA-NEXT:    .cfi_def_cfa_offset 0
 ; RV32ZBA-NEXT:    ret
   %c = shl i32 %a, 5
   %d = shl i32 %b, 6
   %e = add i32 %c, %d
   ret i32 %e
 }
 
 define i32 @addshl_5_7(i32 %a, i32 %b) {
 ; RV32I-LABEL: addshl_5_7:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    slli a0, a0, 5
 ; RV32I-NEXT:    slli a1, a1, 7
 ; RV32I-NEXT:    add a0, a0, a1
+; RV32I-NEXT:    .cfi_def_cfa_offset 0
 ; RV32I-NEXT:    ret
 ;
 ; RV32ZBA-LABEL: addshl_5_7:
 ; RV32ZBA:       # %bb.0:
 ; RV32ZBA-NEXT:    sh2add a0, a1, a0
 ; RV32ZBA-NEXT:    slli a0, a0, 5
+; RV32ZBA-NEXT:    .cfi_def_cfa_offset 0
 ; RV32ZBA-NEXT:    ret
   %c = shl i32 %a, 5
   %d = shl i32 %b, 7
   %e = add i32 %c, %d
   ret i32 %e
 }
 
 define i32 @addshl_5_8(i32 %a, i32 %b) {
 ; RV32I-LABEL: addshl_5_8:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    slli a0, a0, 5
 ; RV32I-NEXT:    slli a1, a1, 8
 ; RV32I-NEXT:    add a0, a0, a1
+; RV32I-NEXT:    .cfi_def_cfa_offset 0
 ; RV32I-NEXT:    ret
 ;
 ; RV32ZBA-LABEL: addshl_5_8:
 ; RV32ZBA:       # %bb.0:
 ; RV32ZBA-NEXT:    sh3add a0, a1, a0
 ; RV32ZBA-NEXT:    slli a0, a0, 5
+; RV32ZBA-NEXT:    .cfi_def_cfa_offset 0
 ; RV32ZBA-NEXT:    ret
   %c = shl i32 %a, 5
   %d = shl i32 %b, 8
   %e = add i32 %c, %d
   ret i32 %e
 }