[RISCV] Add CFI directives for RISCV epilog

[kito-cheng]

Do you mind add a test case to demonstrate that we've emit .cfi_def_cfa after this patch?

[Miss_Grape]

In D119315#3306940, @kito-cheng wrote:

Do you mind add a test case to demonstrate that we've emit .cfi_def_cfa after this patch?

The CFI directives is emitted to ensure that it can correctly print the stack debug in the case of debugging. We need to update the CFA in the function Epilogue, otherwise we cannot find the calling relationship of the caller function
The following shows the difference between the debug_frame sections of clang and riscv-unknown-elf-gcc

[kito-cheng]

I mean add a testcase like: https://github.com/llvm/llvm-project/blob/main/llvm/test/CodeGen/RISCV/frame-info.ll

[jrtc27]

This lack of CFI is deliberate. See https://reviews.llvm.org/D69723 and discussions in https://reviews.llvm.org/D111519. The underlying problem has not been fixed, so we cannot do this.

[frasercrmck]

Perhaps something we can do to avoid this in the future is add a comment to emitEpilogue explaining why we deliberately don't emit CFI directives, pointing to these discussions and a bug number (creating one if no such bug exists)?

[Miss_Grape]

llvm/lib/Target/RISCV/RISCVFrameLowering.cpp

 //===----------------------------------------------------------------------===//
 
 #include "RISCVFrameLowering.h"
 #include "RISCVMachineFunctionInfo.h"
 #include "RISCVSubtarget.h"
 #include "llvm/CodeGen/MachineFrameInfo.h"
 #include "llvm/CodeGen/MachineFunction.h"
 #include "llvm/CodeGen/MachineInstrBuilder.h"
+#include "llvm/CodeGen/MachineModuleInfo.h"
 #include "llvm/CodeGen/MachineRegisterInfo.h"
 #include "llvm/CodeGen/RegisterScavenging.h"
 #include "llvm/IR/DiagnosticInfo.h"
 #include "llvm/MC/MCDwarf.h"
 
 using namespace llvm;
 
 // For now we use x18, a.k.a s2, as pointer to shadow call stack.
void RISCVFrameLowering::emitPrologue(MachineFunction &MF,
   }
 }
 
 void RISCVFrameLowering::emitEpilogue(MachineFunction &MF,
                                       MachineBasicBlock &MBB) const {
   const RISCVRegisterInfo *RI = STI.getRegisterInfo();
   MachineFrameInfo &MFI = MF.getFrameInfo();
   auto *RVFI = MF.getInfo<RISCVMachineFunctionInfo>();
+  const RISCVInstrInfo *TII = STI.getInstrInfo();
   Register FPReg = getFPReg(STI);
   Register SPReg = getSPReg(STI);
 
   // All calls are tail calls in GHC calling conv, and functions have no
   // prologue/epilogue.
   if (MF.getFunction().getCallingConv() == CallingConv::GHC)
     return;
 
if (FirstSPAdjustAmount) {
     uint64_t SecondSPAdjustAmount = MFI.getStackSize() - FirstSPAdjustAmount;
     assert(SecondSPAdjustAmount > 0 &&
            "SecondSPAdjustAmount should be greater than zero");
 
     adjustReg(MBB, LastFrameDestroy, DL, SPReg, SPReg, SecondSPAdjustAmount,
               MachineInstr::FrameDestroy);
   }
 
+  if (hasFP(MF) && StackSize != 0) {
+    // To find the instruction restoring FP from stack.
+    for (auto &I = LastFrameDestroy; I != MBBI; ++I) {
+      if (I->mayLoad() && I->getOperand(0).isReg()) {
+        Register DestReg = I->getOperand(0).getReg();
+        if (DestReg == FPReg) {
+          // We need adjust CFA back to the correct sp-based offset.
+          // Emit ".cfi_def_cfa $sp, CFAOffset"
+          uint64_t CFAOffset =
+              FirstSPAdjustAmount
+                  ? -FirstSPAdjustAmount + RVFI->getVarArgsSaveSize()
+                  : FPOffset;
+          unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::cfiDefCfa(
+              nullptr, RI->getDwarfRegNum(SPReg, true), CFAOffset));
+          BuildMI(MBB, std::next(I), DL,
+                  TII->get(TargetOpcode::CFI_INSTRUCTION))
+              .addCFIIndex(CFIIndex);
+          break;
+        }
+      }
+    }
+  }
+
+  // Emit ".cfi_def_cfa $sp, FPOffset"
+  if (!hasFP(MF) && FPOffset != 0) {
+    unsigned regSP = RI->getDwarfRegNum(SPReg, true);
+    unsigned CFIIndex =
+        MF.addFrameInst(MCCFIInstruction::cfiDefCfa(nullptr, regSP, FPOffset));
+    BuildMI(MBB, LastFrameDestroy, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
+        .addCFIIndex(CFIIndex);
+  }
+
   if (FirstSPAdjustAmount)
     StackSize = FirstSPAdjustAmount;
 
   // Deallocate stack
   adjustReg(MBB, MBBI, DL, SPReg, SPReg, StackSize, MachineInstr::FrameDestroy);
 
+  // Update the CFA information to ensure that the stack debugging information
+  // can finds the calling information of the Caller function
+  if (StackSize != 0) {
+    unsigned regSP = RI->getDwarfRegNum(SPReg, true);
+    // Emit ".cfi_def_cfa $sp, 0".
+    unsigned CFIIndex =
+        MF.addFrameInst(MCCFIInstruction::cfiDefCfa(nullptr, regSP, 0));
+    BuildMI(MBB, MBBI, DL, TII->get(TargetOpcode::CFI_INSTRUCTION))
+        .addCFIIndex(CFIIndex);
+  }
+
   // Emit epilogue for shadow call stack.
   emitSCSEpilogue(MF, MBB, MBBI, DL);
 }
 
 StackOffset
 RISCVFrameLowering::getFrameIndexReference(const MachineFunction &MF, int FI,
                                            Register &FrameReg) const {
   const MachineFrameInfo &MFI = MF.getFrameInfo();

llvm/test/DebugInfo/RISCV/relax-debug-frame.ll

 ; RUN: llc -filetype=obj -mtriple=riscv32 -mattr=+relax %s -o %t.o
 ; RUN: llvm-readobj -r %t.o | FileCheck -check-prefix=RELAX %s
 ; RUN: llvm-dwarfdump --debug-frame %t.o 2>&1 \
 ; RUN:     | FileCheck -check-prefix=RELAX-DWARFDUMP %s
 ;
 ; RELAX:      Section ({{.*}}) .rela.eh_frame {
 ; RELAX-NEXT:   0x1C R_RISCV_32_PCREL - 0x0
 ; RELAX-NEXT:   0x20 R_RISCV_ADD32 - 0x0
 ; RELAX-NEXT:   0x20 R_RISCV_SUB32 - 0x0
 ; RELAX-NOT:  }
-; RELAX:        0x39 R_RISCV_SET6 - 0x0
-; RELAX-NEXT:   0x39 R_RISCV_SUB6 - 0x0
+; RELAX:        0x25 R_RISCV_SET6 - 0x0
+; RELAX-NEXT:   0x25 R_RISCV_SUB6 - 0x0
 ;
 ; RELAX-DWARFDUMP-NOT: error: failed to compute relocation
 ; RELAX-DWARFDUMP: CIE
 ; RELAX-DWARFDUMP: DW_CFA_advance_loc
 ; RELAX-DWARFDUMP: DW_CFA_def_cfa_offset
 ; RELAX-DWARFDUMP: DW_CFA_offset
 source_filename = "frame.c"