Page MenuHomePhabricator

[RISCV] Add undisturbed version of unmasked intrinsics.
Needs ReviewPublic

Authored by HsiangKai on Sep 30 2021, 6:43 AM.

Details

Summary

In https://github.com/riscv-non-isa/rvv-intrinsic-doc/pull/116, we
propose a new set of intrinsics for unmasked tail undisturbed
instructions. This patch is the implementation of the proposal.

This is a preparation work for these new C intrinsics. This patch only
adds LLVM IR intrinsics. There is no compile time or binary size
problem.

Diff Detail

Event Timeline

HsiangKai created this revision.Sep 30 2021, 6:43 AM
HsiangKai requested review of this revision.Sep 30 2021, 6:43 AM
Herald added a project: Restricted Project. · View Herald TranscriptSep 30 2021, 6:43 AM
HsiangKai retitled this revision from [PoC][RISCV] Add undisturbed version of unmasked intrinsics. Draft version. Proof of concept of https://github.com/riscv-non-isa/rvv-intrinsic-doc/pull/116. to [PoC][RISCV] Add undisturbed version of unmasked intrinsics..Sep 30 2021, 6:44 AM
HsiangKai edited the summary of this revision. (Show Details)

Full implementation of LLVM IR intrinsics for unmasked tail undisturbed intrinsics.

HsiangKai retitled this revision from [PoC][RISCV] Add undisturbed version of unmasked intrinsics. to [RISCV] Add undisturbed version of unmasked intrinsics..Oct 18 2021, 11:44 PM
HsiangKai edited the summary of this revision. (Show Details)

Fix build errors.

HsiangKai updated this revision to Diff 380639.Oct 19 2021, 4:20 AM

Add test cases.

Handle vmv.v.x, vfmv.v.f, and vector loads.

khchen added a subscriber: khchen.Mon, Nov 8, 7:45 AM
khchen added inline comments.
llvm/include/llvm/IR/IntrinsicsRISCV.td
203

// Input: (undisturbed, pointer, vl) maybe better.

llvm/lib/Target/RISCV/RISCVInstrInfoVPseudos.td
478

How about

class RISCVVSX<bit M, bit O, bits<3> S, bits<3> L, bits<3> IL> :
  RISCVVLX_VSX<M, /*TU*/ 0, O, S, L, IL>;