[RISCV] Add the zvl extension according to the v1.0 spec

[eopXD]

Summary

zvl is the new standard vector extension that specifies the minimum vector length of the vector extension.
The zvl extension is related to the zve extension and other updates that are added in v1.0.

According to https://github.com/riscv-non-isa/riscv-c-api-doc/pull/21,
Clang defines macro __riscv_v_min_vlen for zvl and it can be used for applications that uses the vector extension.
LLVM checks whether the option riscv-v-vector-bits-min (if specified) matches the zvl* extension specified.

[eopXD]

Update code, bug fixes to this patch.

[eopXD]

llvm/lib/Target/RISCV/RISCV.td

188

Don't need the AssemblerPredicate here because this sub-extension is used to restrict vlen, which is treated as a constant in the assembly.

llvm/lib/Target/RISCV/RISCVSubtarget.h

154

I don't think this function will be called. However other sub-extensions will have this function so I still created it.

[kito-cheng]

llvm/lib/Support/RISCVISAInfo.cpp

72

Although the table in vector spec only list zvl32b~zvl1024b, but there is note say Longer vector length extensions should follow the same pattern.[1], so I would suggest let enumerate to 65536, the unbound of VLEN[2],

[1] https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#181-zvl-minimum-vector-length-standard-extensions
[2] https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#2-implementation-defined-constant-parameters

llvm/lib/Target/RISCV/RISCVSubtarget.cpp

181

I guess this should be more than an assertion? but I am not sure does it make sense to emit error or warning here? or just silently return ZvlLen if RVVVectorBitsMin is less than ZvlLen.

[kito-cheng]

llvm/lib/Support/RISCVISAInfo.cpp

72

Oh, typo, unbound should be upper bound :p

[eopXD]

Address comments.

• enumerate zvl up to 65536
• fix grammitcal error in assertion error message

llvm/lib/Target/RISCV/RISCVSubtarget.cpp

181

I think the compiler should not return ZvlLen silently if the specified RVVVectorBitsMin is less. As zvl hard restricts the minimum vlen, the user should be aware (notified) of that. I think the assertion error here can guide the user to either increase their RVVVectorBitsMin in the argument or compile under another architecture specification.

[craig.topper]

llvm/lib/Target/RISCV/RISCVSubtarget.cpp

144–152

The max should be greater than ZvlLen right?

174

Some of the callers of this will break if it returns a value less than 64. We need to limit ELEN to 32 if VLEN is 32. And we can't use LMUL=1/8 with i8 vectors, or LMUL=1/4 with i16 vector, or LMUL=1/2 with i32 vector.

181

assertions are compiled out of release builds. The code after the assertions was trying to do something sane for release builds.

[craig.topper]

I think we need to visit some larger aspects of our vector implementation. Here are some thoughts.

-Most uses of Subtarget.hasStdExtV() don't really mean what the spec calls the standard V extension. They just means that we have vector instructions. Could be V, could be one of the Zve32* or Zve64* extensions.
-V extension passed to -march should imply at least Zvl128b.
-V extension passed to -march should enable F and D.
-Does Zvl32b passed to march enable vector instructions? Or do we still need Zve32* or Zve64* or V?
-If Zvl32b is in effect the i64 and f64 RVV intrinsics need to be disabled.

[kito-cheng]

Those rule are unclear to me too, I created an issue on vector spec, I guess we need writing few special rule for those extensions...

https://github.com/riscv/riscv-v-spec/issues/723

In D108694#2966553, @craig.topper wrote:

I think we need to visit some larger aspects of our vector implementation. Here are some thoughts.

-Most uses of Subtarget.hasStdExtV() don't really mean what the spec calls the standard V extension. They just means that we have vector instructions. Could be V, could be one of the Zve32* or Zve64* extensions.
-V extension passed to -march should imply at least Zvl128b.
-V extension passed to -march should enable F and D.
-Does Zvl32b passed to march enable vector instructions? Or do we still need Zve32* or Zve64* or V?
-If Zvl32b is in effect the i64 and f64 RVV intrinsics need to be disabled.

[HsiangKai]

llvm/lib/Target/RISCV/RISCVSubtarget.cpp

174

We have an implicit assumption that VLEN >= 64 from our VLA types. I suggest use 64 as the lower bound and add a FIXME here for VLEN is 32.

181

Should it be RVVVectorBitsMin < ZvlLen?

I suggest to return 0 and print a warning message for users.

[HsiangKai]

llvm/lib/Target/RISCV/RISCVSubtarget.cpp

144–152

Should it be less than or equal to ZvlLen? I would suggest to return 0 when RVVVectorBitsMax > ZvlLen.
The value also needs to >= 64.

[craig.topper]

llvm/lib/Target/RISCV/RISCVSubtarget.cpp

181

This isn't a good place to print warnings. It would just be a random message printed to stderr without going through any of clang's diagnostic infrastructure.

[HsiangKai]

In D108694#2966553, @craig.topper wrote:

I think we need to visit some larger aspects of our vector implementation. Here are some thoughts.

-Most uses of Subtarget.hasStdExtV() don't really mean what the spec calls the standard V extension. They just means that we have vector instructions. Could be V, could be one of the Zve32* or Zve64* extensions.
-V extension passed to -march should imply at least Zvl128b.
-V extension passed to -march should enable F and D.
-Does Zvl32b passed to march enable vector instructions? Or do we still need Zve32* or Zve64* or V?
-If Zvl32b is in effect the i64 and f64 RVV intrinsics need to be disabled.

We need to apply the constraints of Zve* to intrinsics/pseudo instructions. I am not sure what is the behavior if users specify V and Zve* at the same time? I think Zve* is more complicated. We could prepare another patch for it.

Could we support Zvl32b? We already have an implicit constraint of vlen >= 64 from our VLA types, right?

[eopXD]

llvm/lib/Target/RISCV/RISCVSubtarget.cpp

181

I think moving the check to initializeSubtargetDependencies and use report_fatal_error will be a more appropriate approach?

[craig.topper]

llvm/lib/Target/RISCV/RISCVSubtarget.cpp

181

I think that causes clang to generate a crash report and telling the user to file a bug.

Forgot to mention, all this code is also being modified by D107290

[eopXD]

llvm/lib/Target/RISCV/RISCVSubtarget.cpp

181

I see, then my proposal is invalid.

I am not yet that familiar with the code base. I see RISCVFrameLowering.cpp using LLVMContext::diagnose, but RISCVSubtarget here doesn't seem to have access to LLVMContext.

May you recommend a pointer to some diagnose function I can use to tell the user this is an invalid setting between RVVVectorBitsMin(from riscv-v-vector-bits-min) and ZvlLen (from -march=zvl*b)?

[frasercrmck]

I also don't think we're ready/able to support Zvl32b for the reasons stated above. I think the smoothest path forward would be, as @HsiangKai suggests, to only support VLEN>=64 and revisit 32. Supporting 32 is (I think) a much larger thing owing to our codegen assumptions on VLEN and ELEN. And, as @craig.topper said, there are a few little things that would probably be best prepared before this patch, replacing some of the calls to hasStdExtV at least (hasVVectors, for codegen purposes?). It sounds like we're unsure on some of the finer details about how the extensions interact.

[craig.topper]

In D108694#2971960, @frasercrmck wrote:

I also don't think we're ready/able to support Zvl32b for the reasons stated above. I think the smoothest path forward would be, as @HsiangKai suggests, to only support VLEN>=64 and revisit 32. Supporting 32 is (I think) a much larger thing owing to our codegen assumptions on VLEN and ELEN. And, as @craig.topper said, there are a few little things that would probably be best prepared before this patch, replacing some of the calls to hasStdExtV at least (hasVVectors, for codegen purposes?). It sounds like we're unsure on some of the finer details about how the extensions interact.

I think our mapping from lmul/sew to <vscale x Y x iZ> types also break with VLEN=32. I haven't been able to figure out a single mapping that works for VLEN=32 and VLEN=64 and supports i64 vectors. To support VLEN=32 we need to reduce RVVBitsPerBlock to 32, but then you can't fit an i64 element into it.

[eopXD]

Address comments and add macro in clang.

[eopXD]

Rebase.

[eopXD]

Rebase.

[eopXD]

Fix clang-format.

[eopXD]

Update code.

[eopXD]

Add implication: v imply d and f

[eopXD]

Address comments:

• remove duplicate checkDependency()
• stay consistent in my patch of using auto for StringRef

[eopXD]

Update.

[eopXD]

Change:

• Address commments on restrictions in RISCVSubtarget.cpp
• Fix clang-format fail
• Fix test case fail

[eopXD]

llvm/lib/Target/RISCV/RISCVSubtarget.cpp

181

I see code under RISCVSubtarget::initializeSubtargetDependencies also using report_fatal_error:

[eopXD]

Update code.

[eopXD]

Update code.

llvm/lib/Target/RISCV/RISCVSubtarget.cpp

144–152

@HsiangKai I think you mis-typed the equation? It should be RVVVectorBitsMax < ZvlLen ;)

[eopXD]

Fix test case.

[eopXD]

Rebase to newest main.

[eopXD]

Rebase.

[eopXD]

Rebase.

[eopXD]

Rebase now since the preceeding patches are accepted.
This patch is ready for review.

[craig.topper]

llvm/lib/Support/RISCVISAInfo.cpp

751

I think I'd like to see this as a static data structure rather than building a StringMap on the fly.

Maybe like

static const char *zvl64bimplied[] = { "zvl32b" };
static const char *zvl128bimplied[] = { "zvl64b" };
...

struct ImpliedEntry = {
  StringLiteral Name;
  ArrayRef<const char*> ImpliedExtensions;
};

static constexpr ImpliedEntry ImpliedTable[] = {
  { "zvl64b", zvl64bimplied },
  { "zvl128b", zvl128implied },
  ...
};

You can then use std::lower_bound to search the ImpliedTable to find the correct row of ImpliedTable. I haven't tested this. Maybe I'll put up a patch on the existing V implications as a proof of concept.

800

I think we should check the return value from consume_back and getAsInteger to make sure we really parsed what we think we parsed. That will prevent surprises if a new extension comes along that also starts with "zvl"

llvm/lib/Target/RISCV/RISCVSubtarget.cpp

174

This needs the same FIXME as above.

[craig.topper]

llvm/lib/Support/RISCVISAInfo.cpp

800

This would match for "zvlsseg" right now wouldn't it?

[eopXD]

llvm/lib/Support/RISCVISAInfo.cpp

800

This would match for "zvlsseg" right now wouldn't it?

Yes, you have a point.

IsZvlExt should be ExtName.consume_front("zvl") && ExtName.consume_back("b").

[eopXD]

Rebase and address comment.

llvm/lib/Target/RISCV/RISCVSubtarget.cpp

181

I am marking this thread as done since there are no further comments.

This patch currently uses report_fatal_error for it. Although as Craig mentioned it may not be ideal.

[frasercrmck]

clang/test/Preprocessor/riscv-target-features.c

242

Are we able to test non-default values of __riscv_v_min_vlen here?

llvm/lib/Target/RISCV/RISCVSubtarget.cpp

145

Is this intuitive behaviour? If the user supplies RVVVectorBitsMax and it's less than ZvlLen, should it silently return? Or do we instead see RVVVectorBitsMax as a user-guided limit on top of the architecture? Which means it can be less but not more? I'm not sure.

[eopXD]

Rebase and address comments.

clang/test/Preprocessor/riscv-target-features.c

242

Yes we shall, thank you for the reminder.

llvm/lib/Target/RISCV/RISCVSubtarget.cpp

145

Added report_fatal_error here.

[eopXD]

Rebase to latest main.

[craig.topper]

llvm/lib/Support/RISCVISAInfo.cpp

736–747

Need curly braces around the strings too.

801

getAsInteger returns an indication of success or failure. We should check that too. That will protect us in case someone creates an extension like "zvlfoob" in the future.

[eopXD]

Address comments from Craig.

[eopXD]

Ping, thank you.

[achieveartificialintelligence]

llvm/lib/Support/RISCVISAInfo.cpp

737–747

Can we compress the code?

llvm/lib/Target/RISCV/RISCV.td

153–186

Same as here.

[eopXD]

Rebase.

[eopXD]

llvm/lib/Support/RISCVISAInfo.cpp

737–747

Hi,

Thank you for leaving a comment. Do you mean to embed the list of implied extensions into the declaration of ImpliedExts? Like:

static constexpr ImpliedExtsEntry ImpliedExts[] = {
    {{"v"}, {{"zvlsseg", "zvl128b"}}},
   ...

In my opinion I think compressing here may not help because the indirection is intended to have the implications be in more sorted order that is more human readable since ImpliedExts are required to be in lexicographical order.

I am just stating my opinion on my current implementation since I think this is a coding style problem. What do you think?

[eopXD]

ping again, thank you.

[achieveartificialintelligence]

llvm/lib/Target/RISCV/RISCV.td

155–187

I think we can write in this way:

foreach i = { 5-15 } in {
  defvar I = !shl(2, i);
  def FeatureStdExtZvl#I#b
      : SubtargetFeature<"experimental-zvl"#I#"b", "ZvlLen", "ExtZvl::Zvl"#I#"b",
                        "'Zvl' (Minimum Vector Length) "#I,
                        [!cast<SubtargetFeature>("FeatureStdExtZvl"#!srl(I, 1)#"b")]>;
}

[craig.topper]

llvm/lib/Support/RISCVISAInfo.cpp

769

Use StringRef instead of auto here.

770

You can keep this auto though. iterators are ugly.

llvm/lib/Target/RISCV/RISCV.td

188

Is this used?

llvm/lib/Target/RISCV/RISCVSubtarget.cpp

148

Why do we need an explicit Twine construction here?

167

Same here.

[eopXD]

Address comments.
Thanks for reviewing!

llvm/lib/Target/RISCV/RISCV.td

155–187

Thank you for the tip! I previously don't know TableGen can compute values like bit-shift left and do value type casting.

Adapted your code snippet. I modified a bit because Zvl32b don't imply anything.

188

No it is not, deleted.

[craig.topper]

LGTM

[eopXD]

Rebase to latest main.
Resolve test case conflicts due to Zvamo removal.

[eopXD]

Rebase to latest main.
Resolve test case conflicts due to Zfh, Zfhmin version update.

clang/lib/Basic/Targets/RISCV.cpp

 void RISCVTargetInfo::getTargetDefines(const LangOptions &Opts,
                                        MacroBuilder &Builder) const {
   Builder.defineMacro("__ELF__");
   Builder.defineMacro("__riscv");
   bool Is64Bit = getTriple().getArch() == llvm::Triple::riscv64;
   Builder.defineMacro("__riscv_xlen", Is64Bit ? "64" : "32");
   StringRef CodeModel = getTargetOpts().CodeModel;
   unsigned FLen = ISAInfo->getFLen();
+  unsigned MinVLen = ISAInfo->getMinVLen();
   if (CodeModel == "default")
     CodeModel = "small";
 
   if (CodeModel == "small")
     Builder.defineMacro("__riscv_cmodel_medlow");
   else if (CodeModel == "medium")
     Builder.defineMacro("__riscv_cmodel_medany");
 
void RISCVTargetInfo::getTargetDefines(const LangOptions &Opts,
   }
 
   if (FLen) {
     Builder.defineMacro("__riscv_flen", Twine(FLen));
     Builder.defineMacro("__riscv_fdiv");
     Builder.defineMacro("__riscv_fsqrt");
   }
 
+  if (MinVLen)
+    Builder.defineMacro("__riscv_v_min_vlen", Twine(MinVLen));
+
   if (ISAInfo->hasExtension("c"))
     Builder.defineMacro("__riscv_compressed");
 
   if (ISAInfo->hasExtension("v"))
     Builder.defineMacro("__riscv_vector");
 }
 
 const Builtin::Info RISCVTargetInfo::BuiltinInfo[] = {

clang/test/Driver/riscv-arch.c

 // RUN: %clang -target riscv32-unknown-elf -march=rv32izvlsseg0p1 -menable-experimental-extensions -### %s -c 2>&1 | \
 // RUN:   FileCheck -check-prefix=RV32-EXPERIMENTAL-ZVLSSEG-BADVERS %s
 // RV32-EXPERIMENTAL-ZVLSSEG-BADVERS: error: invalid arch name 'rv32izvlsseg0p1'
 // RV32-EXPERIMENTAL-ZVLSSEG-BADVERS: unsupported version number 0.1 for experimental extension 'zvlsseg'
 
 // RUN: %clang -target riscv32-unknown-elf -march=rv32izvlsseg0p10 -menable-experimental-extensions -### %s -c 2>&1 | \
 // RUN:   FileCheck -check-prefix=RV32-EXPERIMENTAL-ZVLSSEG-GOODVERS %s
 // RV32-EXPERIMENTAL-ZVLSSEG-GOODVERS: "-target-feature" "+experimental-zvlsseg"
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32izvl32b0p10 -### %s -c 2>&1 | \
+// RUN:   FileCheck -check-prefix=RV32-EXPERIMENTAL-ZVL-NOFLAG %s
+// RV32-EXPERIMENTAL-ZVL-NOFLAG: error: invalid arch name 'rv32izvl32b0p10'
+// RV32-EXPERIMENTAL-ZVL-NOFLAG: requires '-menable-experimental-extensions'
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32izvl32b0p1 -menable-experimental-extensions -### %s -c 2>&1 | \
+// RUN:   FileCheck -check-prefix=RV32-EXPERIMENTAL-ZVL-BADVERS %s
+// RV32-EXPERIMENTAL-ZVL-BADVERS: error: invalid arch name 'rv32izvl32b0p1'
+// RV32-EXPERIMENTAL-ZVL-BADVERS: unsupported version number 0.1 for experimental extension
+
+// RUN: %clang -target riscv32-unknown-elf -march=rv32izvl32b0p10 -menable-experimental-extensions -### %s -c 2>&1 | \
+// RUN:   FileCheck -check-prefix=RV32-EXPERIMENTAL-ZVL-GOODVERS %s
+// RV32-EXPERIMENTAL-ZVL-GOODVERS: "-target-feature" "+experimental-zvl32b"

clang/test/Preprocessor/riscv-target-features.c

 
 // RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions \
 // RUN: -march=rv32izfh0p1 -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-ZFH-EXT %s
 // RUN: %clang -target riscv64-unknown-linux-gnu -menable-experimental-extensions \
 // RUN: -march=rv64izfh0p1 -x c -E -dM %s \
 // RUN: -o - | FileCheck --check-prefix=CHECK-ZFH-EXT %s
 // CHECK-ZFH-EXT: __riscv_zfh 1000
+
+// RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions \
+// RUN: -march=rv64iv0p10 -x c -E -dM %s -o - \
+// RUN: | FileCheck --check-prefix=CHECK-V-MINVLEN %s
+// CHECK-V-MINVLEN: __riscv_v_min_vlen 128
+
+// RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions \
+// RUN: -march=rv64iv0p10_zvl256b0p10 -x c -E -dM %s -o - \
+// RUN: | FileCheck --check-prefix=CHECK-ZVL256b %s
+// CHECK-ZVL256b: __riscv_v_min_vlen 256
+
+// RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions \
+// RUN: -march=rv64iv0p10_zvl512b0p10 -x c -E -dM %s -o - \
+// RUN: | FileCheck --check-prefix=CHECK-ZVL512b %s
+// CHECK-ZVL512b: __riscv_v_min_vlen 512
+
+// RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions \
+// RUN: -march=rv64iv0p10_zvl1024b0p10 -x c -E -dM %s -o - \
+// RUN: | FileCheck --check-prefix=CHECK-ZVL1024b %s
+// CHECK-ZVL1024b: __riscv_v_min_vlen 1024
+
+// RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions \
+// RUN: -march=rv64iv0p10_zvl2048b0p10 -x c -E -dM %s -o - \
+// RUN: | FileCheck --check-prefix=CHECK-ZVL2048b %s
+// CHECK-ZVL2048b: __riscv_v_min_vlen 2048
+
+// RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions \
+// RUN: -march=rv64iv0p10_zvl4096b0p10 -x c -E -dM %s -o - \
+// RUN: | FileCheck --check-prefix=CHECK-ZVL4096b %s
+// CHECK-ZVL4096b: __riscv_v_min_vlen 4096
+
+// RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions \
+// RUN: -march=rv64iv0p10_zvl8192b0p10 -x c -E -dM %s -o - \
+// RUN: | FileCheck --check-prefix=CHECK-ZVL8192b %s
+// CHECK-ZVL8192b: __riscv_v_min_vlen 8192
+
+// RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions \
+// RUN: -march=rv64iv0p10_zvl16384b0p10 -x c -E -dM %s -o - \
+// RUN: | FileCheck --check-prefix=CHECK-ZVL16384b %s
+// CHECK-ZVL16384b: __riscv_v_min_vlen 16384
+
+// RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions \
+// RUN: -march=rv64iv0p10_zvl32768b0p10 -x c -E -dM %s -o - \
+// RUN: | FileCheck --check-prefix=CHECK-ZVL32768b %s
+// CHECK-ZVL32768b: __riscv_v_min_vlen 32768
+
+// RUN: %clang -target riscv32-unknown-linux-gnu -menable-experimental-extensions \
+// RUN: -march=rv64iv0p10_zvl65536b0p10 -x c -E -dM %s -o - \
+// RUN: | FileCheck --check-prefix=CHECK-ZVL65536b %s
+// CHECK-ZVL65536b: __riscv_v_min_vlen 65536

llvm/include/llvm/Support/RISCVISAInfo.h

public:
   /// Convert RISCV ISA info to a feature vector.
   void toFeatures(std::vector<StringRef> &Features,
                   std::function<StringRef(const Twine &)> StrAlloc) const;
 
   const OrderedExtensionMap &getExtensions() const { return Exts; };
 
   unsigned getXLen() const { return XLen; };
   unsigned getFLen() const { return FLen; };
+  unsigned getMinVLen() const { return MinVLen; }
 
   bool hasExtension(StringRef Ext) const;
   std::string toString() const;
 
   static bool isSupportedExtensionFeature(StringRef Ext);
   static bool isSupportedExtension(StringRef Ext);
   static bool isSupportedExtension(StringRef Ext, unsigned MajorVersion,
                                    unsigned MinorVersion);
 
 private:
-  RISCVISAInfo(unsigned XLen) : XLen(XLen), FLen(0) {}
+  RISCVISAInfo(unsigned XLen) : XLen(XLen), FLen(0), MinVLen(0) {}
 
   unsigned XLen;
   unsigned FLen;
+  unsigned MinVLen;
 
   OrderedExtensionMap Exts;
 
   void addExtension(StringRef ExtName, unsigned MajorVersion,
                     unsigned MinorVersion);
 
   Error checkDependency();
 
   void updateImplication();
   void updateFLen();
+  void updateMinVLen();
 };
 
 } // namespace llvm
 
 #endif

llvm/lib/Support/RISCVISAInfo.cpp

 //===-- RISCVISAInfo.cpp - RISCV Arch String Parser --------------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 
 #include "llvm/Support/RISCVISAInfo.h"
 #include "llvm/ADT/None.h"
 #include "llvm/ADT/STLExtras.h"
+#include "llvm/ADT/SetVector.h"
 #include "llvm/ADT/StringExtras.h"
 #include "llvm/ADT/StringRef.h"
 #include "llvm/Support/Errc.h"
 #include "llvm/Support/Error.h"
 #include "llvm/Support/raw_ostream.h"
 
 #include <array>
 #include <string>
static const RISCVSupportedExtension SupportedExperimentalExtensions[] = {
     {"zbe", RISCVExtensionVersion{0, 93}},
     {"zbf", RISCVExtensionVersion{0, 93}},
     {"zbm", RISCVExtensionVersion{0, 93}},
     {"zbp", RISCVExtensionVersion{0, 93}},
     {"zbr", RISCVExtensionVersion{0, 93}},
     {"zbt", RISCVExtensionVersion{0, 93}},
 
     {"zvlsseg", RISCVExtensionVersion{0, 10}},
+    {"zvl32b", RISCVExtensionVersion{0, 10}},
+    {"zvl64b", RISCVExtensionVersion{0, 10}},
+    {"zvl128b", RISCVExtensionVersion{0, 10}},
+    {"zvl256b", RISCVExtensionVersion{0, 10}},
+    {"zvl512b", RISCVExtensionVersion{0, 10}},
+    {"zvl1024b", RISCVExtensionVersion{0, 10}},
+    {"zvl2048b", RISCVExtensionVersion{0, 10}},
+    {"zvl4096b", RISCVExtensionVersion{0, 10}},
+    {"zvl8192b", RISCVExtensionVersion{0, 10}},
+    {"zvl16384b", RISCVExtensionVersion{0, 10}},
+    {"zvl32768b", RISCVExtensionVersion{0, 10}},
+    {"zvl65536b", RISCVExtensionVersion{0, 10}},
 
     {"zfhmin", RISCVExtensionVersion{0, 1}},
     {"zfh", RISCVExtensionVersion{0, 1}},
 };
 
 static bool stripExperimentalPrefix(StringRef &Ext) {
   return Ext.consume_front("experimental-");
 }
if (Add)
       ISAInfo->addExtension(ExtName, ExtensionInfoIterator->Version.Major,
                             ExtensionInfoIterator->Version.Minor);
     else
       ISAInfo->Exts.erase(ExtName.str());
   }
 
   ISAInfo->updateImplication();
   ISAInfo->updateFLen();
+  ISAInfo->updateMinVLen();
 
   if (Error Result = ISAInfo->checkDependency())
     return std::move(Result);
 
   return std::move(ISAInfo);
 }
 
 llvm::Expected<std::unique_ptr<RISCVISAInfo>>
if (!isSupportedExtension(Ext)) {
       StringRef Desc = getExtensionTypeDesc(getExtensionType(Ext));
       return createStringError(errc::invalid_argument, "unsupported %s '%s'",
                                Desc.str().c_str(), Ext.str().c_str());
     }
   }
 
   ISAInfo->updateImplication();
   ISAInfo->updateFLen();
+  ISAInfo->updateMinVLen();
 
   if (Error Result = ISAInfo->checkDependency())
     return std::move(Result);
 
   return std::move(ISAInfo);
 }
 
 Error RISCVISAInfo::checkDependency() {
Error RISCVISAInfo::checkDependency() {
 
   // Additional dependency checks.
   // TODO: The 'q' extension requires rv64.
   // TODO: It is illegal to specify 'e' extensions with 'f' and 'd'.
 
   return Error::success();
 }
 
-static const char *ImpliedExtsV[] = {"zvlsseg"};
+static const char *ImpliedExtsV[] = {"zvlsseg", "zvl128b"};
 static const char *ImpliedExtsZfh[] = {"zfhmin"};
+static const char *ImpliedExtsZvl65536b[] = {"zvl32768b"};
+static const char *ImpliedExtsZvl32768b[] = {"zvl16384b"};
+static const char *ImpliedExtsZvl16384b[] = {"zvl8192b"};
+static const char *ImpliedExtsZvl8192b[] = {"zvl4096b"};
+static const char *ImpliedExtsZvl4096b[] = {"zvl2048b"};
+static const char *ImpliedExtsZvl2048b[] = {"zvl1024b"};
+static const char *ImpliedExtsZvl1024b[] = {"zvl512b"};
+static const char *ImpliedExtsZvl512b[] = {"zvl256b"};
+static const char *ImpliedExtsZvl256b[] = {"zvl128b"};
+static const char *ImpliedExtsZvl128b[] = {"zvl64b"};
+static const char *ImpliedExtsZvl64b[] = {"zvl32b"};
 
 struct ImpliedExtsEntry {
   StringLiteral Name;
   ArrayRef<const char *> Exts;
 
   bool operator<(const ImpliedExtsEntry &Other) const {
     return Name < Other.Name;
   }
 
   bool operator<(StringRef Other) const { return Name < Other; }
 };
 
 static constexpr ImpliedExtsEntry ImpliedExts[] = {
     {{"v"}, {ImpliedExtsV}},
     {{"zfh"}, {ImpliedExtsZfh}},
+    {{"zvl1024b"}, {ImpliedExtsZvl1024b}},
+    {{"zvl128b"}, {ImpliedExtsZvl128b}},
+    {{"zvl16384b"}, {ImpliedExtsZvl16384b}},
+    {{"zvl2048b"}, {ImpliedExtsZvl2048b}},
+    {{"zvl256b"}, {ImpliedExtsZvl256b}},
+    {{"zvl32768b"}, {ImpliedExtsZvl32768b}},
+    {{"zvl4096b"}, {ImpliedExtsZvl4096b}},
+    {{"zvl512b"}, {ImpliedExtsZvl512b}},
+    {{"zvl64b"}, {ImpliedExtsZvl64b}},
+    {{"zvl65536b"}, {ImpliedExtsZvl65536b}},
+    {{"zvl8192b"}, {ImpliedExtsZvl8192b}},
 };
 
 void RISCVISAInfo::updateImplication() {
   bool HasE = Exts.count("e") == 1;
   bool HasI = Exts.count("i") == 1;
 
   // If not in e extension and i extension does not exist, i extension is
   // implied
   if (!HasE && !HasI) {
     auto Version = findDefaultVersion("i");
     addExtension("i", Version->Major, Version->Minor);
   }
 
   assert(llvm::is_sorted(ImpliedExts) && "Table not sorted by Name");
-  for (auto &Ext : Exts) {
-    auto I = llvm::lower_bound(ImpliedExts, Ext.first);
-    if (I != std::end(ImpliedExts) && I->Name == Ext.first) {
-      for (auto &ImpliedExt : I->Exts) {
+
+  // This loop may execute over 1 iteration since implication can be layered
+  // Exits loop if no more implication is applied
+  SmallSetVector<StringRef, 16> WorkList;
+  for (auto &Ext : Exts)
+    WorkList.insert(Ext.first);
+
+  while (!WorkList.empty()) {
+    StringRef ExtName = WorkList.pop_back_val();
+    auto I = llvm::lower_bound(ImpliedExts, ExtName);
+    if (I != std::end(ImpliedExts) && I->Name == ExtName) {
+      for (const char *ImpliedExt : I->Exts) {
+        if (WorkList.count(ImpliedExt))
+          continue;
+        if (Exts.count(ImpliedExt))
+          continue;
         auto Version = findDefaultVersion(ImpliedExt);
         addExtension(ImpliedExt, Version->Major, Version->Minor);
+        WorkList.insert(ImpliedExt);
       }
     }
   }
 }
 
 void RISCVISAInfo::updateFLen() {
   FLen = 0;
   // TODO: Handle q extension.
   if (Exts.count("d"))
     FLen = 64;
   else if (Exts.count("f"))
     FLen = 32;
 }
 
+void RISCVISAInfo::updateMinVLen() {
+  for (auto Ext : Exts) {
+    StringRef ExtName = Ext.first;
+    bool IsZvlExt = ExtName.consume_front("zvl") && ExtName.consume_back("b");
+    if (IsZvlExt) {
+      unsigned ZvlLen;
+      if (!ExtName.getAsInteger(10, ZvlLen))
+        MinVLen = std::max(MinVLen, ZvlLen);
+    }
+  }
+}
+
 std::string RISCVISAInfo::toString() const {
   std::string Buffer;
   raw_string_ostream Arch(Buffer);
 
   Arch << "rv" << XLen;
 
   ListSeparator LS("_");
   for (auto &Ext : Exts) {
     StringRef ExtName = Ext.first;
     auto ExtInfo = Ext.second;
     Arch << LS << ExtName;
     Arch << ExtInfo.MajorVersion << "p" << ExtInfo.MinorVersion;
   }
 
   return Arch.str();
 }

llvm/lib/Target/RISCV/RISCV.td

 
 def FeatureNoRVCHints
     : SubtargetFeature<"no-rvc-hints", "EnableRVCHintInstrs", "false",
                        "Disable RVC Hint Instructions.">;
 def HasRVCHints : Predicate<"Subtarget->enableRVCHintInstrs()">,
                   AssemblerPredicate<(all_of(not FeatureNoRVCHints)),
                                       "RVC Hint Instructions">;
 
+def FeatureStdExtZvl32b : SubtargetFeature<"experimental-zvl32b", "ZvlLen", "ExtZvl::Zvl32b",
+                       "'Zvl' (Minimum Vector Length) 32">;
+
+foreach i = { 6-15 } in {
+    defvar I = !shl(1, i);
+    def FeatureStdExtZvl#I#b :
+        SubtargetFeature<"experimental-zvl"#I#"b", "ZvlLen", "ExtZvl::Zvl"#I#"b",
+                        "'Zvl' (Minimum Vector Length) "#I,
+                        [!cast<SubtargetFeature>("FeatureStdExtZvl"#!srl(I, 1)#"b")]>;
+}
+
 def FeatureStdExtV
     : SubtargetFeature<"experimental-v", "HasStdExtV", "true",
-                       "'V' (Vector Instructions)">;
+                       "'V' (Vector Instructions)",
+                       [FeatureStdExtZvl128b]>;
 def HasStdExtV : Predicate<"Subtarget->hasStdExtV()">,
                            AssemblerPredicate<(all_of FeatureStdExtV),
                            "'V' (Vector Instructions)">;
 
 def HasVInstructions    : Predicate<"Subtarget->hasVInstructions()">;
 def HasVInstructionsAnyF : Predicate<"Subtarget->hasVInstructionsAnyF()">;
 
 def FeatureStdExtZvlsseg
     : SubtargetFeature<"experimental-zvlsseg", "HasStdExtZvlsseg", "true",
                        "'Zvlsseg' (Vector segment load/store instructions)",
                        [FeatureStdExtV]>;
 def HasStdExtZvlsseg : Predicate<"Subtarget->hasStdExtZvlsseg()">,
                                  AssemblerPredicate<(all_of FeatureStdExtZvlsseg),
                                  "'Zvlsseg' (Vector segment load/store instructions)">;
 
 def Feature64Bit
     : SubtargetFeature<"64bit", "HasRV64", "true", "Implements RV64">;
 def IsRV64 : Predicate<"Subtarget->is64Bit()">,
                        AssemblerPredicate<(all_of Feature64Bit),
                        "RV64I Base Instruction Set">;
 def IsRV32 : Predicate<"!Subtarget->is64Bit()">,
                        AssemblerPredicate<(all_of (not Feature64Bit)),
                        "RV32I Base Instruction Set">;
 
 defvar RV32 = DefaultMode;
 def RV64           : HwMode<"+64bit">;
 
 def FeatureRV32E
     : SubtargetFeature<"e", "IsRV32E", "true",

llvm/lib/Target/RISCV/RISCVSubtarget.h

 #define GET_SUBTARGETINFO_HEADER
 #include "RISCVGenSubtargetInfo.inc"
 
 namespace llvm {
 class StringRef;
 
 class RISCVSubtarget : public RISCVGenSubtargetInfo {
 public:
+  enum ExtZvl : unsigned {
+    NotSet = 0,
+    Zvl32b = 32,
+    Zvl64b = 64,
+    Zvl128b = 128,
+    Zvl256b = 256,
+    Zvl512b = 512,
+    Zvl1024b = 1024,
+    Zvl2048b = 2048,
+    Zvl4096b = 4096,
+    Zvl8192b = 8192,
+    Zvl16384b = 16384,
+    Zvl32768b = 32768,
+    Zvl65536b = 65536
+  };
+
   enum RISCVProcFamilyEnum : uint8_t {
     Others,
     SiFive7,
   };
 
 private:
   virtual void anchor();
 
private:
   bool HasStdExtZfhmin = false;
   bool HasStdExtZfh = false;
   bool HasRV64 = false;
   bool IsRV32E = false;
   bool EnableLinkerRelax = false;
   bool EnableRVCHintInstrs = true;
   bool EnableSaveRestore = false;
   unsigned XLen = 32;
+  ExtZvl ZvlLen = ExtZvl::NotSet;
   MVT XLenVT = MVT::i32;
   uint8_t MaxInterleaveFactor = 2;
   RISCVABI::ABI TargetABI = RISCVABI::ABI_Unknown;
   BitVector UserReservedRegister;
   RISCVFrameLowering FrameLowering;
   RISCVInstrInfo InstrInfo;
   RISCVRegisterInfo RegInfo;
   RISCVTargetLowering TLInfo;
public:
   bool hasStdExtZbf() const { return HasStdExtZbf; }
   bool hasStdExtZbm() const { return HasStdExtZbm; }
   bool hasStdExtZbp() const { return HasStdExtZbp; }
   bool hasStdExtZbr() const { return HasStdExtZbr; }
   bool hasStdExtZbs() const { return HasStdExtZbs; }
   bool hasStdExtZbt() const { return HasStdExtZbt; }
   bool hasStdExtV() const { return HasStdExtV; }
   bool hasStdExtZvlsseg() const { return HasStdExtZvlsseg; }
+  bool hasStdExtZvl() const { return ZvlLen != ExtZvl::NotSet; }
   bool hasStdExtZfhmin() const { return HasStdExtZfhmin; }
   bool hasStdExtZfh() const { return HasStdExtZfh; }
   bool is64Bit() const { return HasRV64; }
   bool isRV32E() const { return IsRV32E; }
   bool enableLinkerRelax() const { return EnableLinkerRelax; }
   bool enableRVCHintInstrs() const { return EnableRVCHintInstrs; }
   bool enableSaveRestore() const { return EnableSaveRestore; }
   MVT getXLenVT() const { return XLenVT; }

llvm/lib/Target/RISCV/RISCVSubtarget.cpp

 #include "RISCVSubtarget.h"
 #include "RISCV.h"
 #include "RISCVCallLowering.h"
 #include "RISCVFrameLowering.h"
 #include "RISCVLegalizerInfo.h"
 #include "RISCVRegisterBankInfo.h"
 #include "RISCVTargetMachine.h"
 #include "llvm/MC/TargetRegistry.h"
+#include "llvm/Support/ErrorHandling.h"
 
 using namespace llvm;
 
 #define DEBUG_TYPE "riscv-subtarget"
 
 #define GET_SUBTARGETINFO_TARGET_DESC
 #define GET_SUBTARGETINFO_CTOR
 #include "RISCVGenSubtargetInfo.inc"
return RISCVMaxBuildIntsCost == 0
              : std::max<unsigned>(2, RISCVMaxBuildIntsCost);
 }
 
 unsigned RISCVSubtarget::getMaxRVVVectorSizeInBits() const {
   assert(hasVInstructions() &&
          "Tried to get vector length without Zve or V extension support!");
   if (RVVVectorBitsMax == 0)
     return 0;
-  assert(RVVVectorBitsMax >= 128 && RVVVectorBitsMax <= 65536 &&
+
+  // ZvlLen specifies the minimum required vlen. The upper bound provided by
+  // riscv-v-vector-bits-max should be no less than it.
+  if (RVVVectorBitsMax < ZvlLen)
+    report_fatal_error("riscv-v-vector-bits-max specified is lower "
+                       "than the Zvl*b limitation");
+
+  // FIXME: Change to >= 32 when VLEN = 32 is supported
+  assert(RVVVectorBitsMax >= 64 && RVVVectorBitsMax <= 65536 &&
          isPowerOf2_32(RVVVectorBitsMax) &&
          "V extension requires vector length to be in the range of 128 to "
          "65536 and a power of 2!");
   assert(RVVVectorBitsMax >= RVVVectorBitsMin &&
          "Minimum V extension vector length should not be larger than its "
          "maximum!");
   unsigned Max = std::max(RVVVectorBitsMin, RVVVectorBitsMax);
   return PowerOf2Floor((Max < 128 || Max > 65536) ? 0 : Max);
 }
 
 unsigned RISCVSubtarget::getMinRVVVectorSizeInBits() const {
+  // ZvlLen specifies the minimum required vlen. The lower bound provided by
+  // riscv-v-vector-bits-min should be no less than it.
+  if (RVVVectorBitsMin != 0 && RVVVectorBitsMin < ZvlLen)
+    report_fatal_error("riscv-v-vector-bits-min specified is lower "
+                       "than the Zvl*b limitation");
+
   assert(hasVInstructions() &&
          "Tried to get vector length without Zve or V extension support!");
+  // FIXME: Change to >= 32 when VLEN = 32 is supported
   assert((RVVVectorBitsMin == 0 ||
-          (RVVVectorBitsMin >= 128 && RVVVectorBitsMax <= 65536 &&
+          (RVVVectorBitsMin >= 64 && RVVVectorBitsMax <= 65536 &&
            isPowerOf2_32(RVVVectorBitsMin))) &&
          "V extension requires vector length to be in the range of 128 to "
          "65536 and a power of 2!");
   assert((RVVVectorBitsMax >= RVVVectorBitsMin || RVVVectorBitsMax == 0) &&
          "Minimum V extension vector length should not be larger than its "
          "maximum!");
   unsigned Min = RVVVectorBitsMin;
   if (RVVVectorBitsMax != 0)
     Min = std::min(RVVVectorBitsMin, RVVVectorBitsMax);
   return PowerOf2Floor((Min < 128 || Min > 65536) ? 0 : Min);
 }
 
 unsigned RISCVSubtarget::getMaxLMULForFixedLengthVectors() const {
   assert(hasVInstructions() &&
          "Tried to get vector length without Zve or V extension support!");

llvm/test/CodeGen/RISCV/attributes.ll

 ; RUN: llc -mtriple=riscv64 -mattr=+zbs %s -o - | FileCheck --check-prefix=RV64ZBS %s
 ; RUN: llc -mtriple=riscv64 -mattr=+experimental-zbt %s -o - | FileCheck --check-prefix=RV64ZBT %s
 
 ; RV32M: .attribute 5, "rv32i2p0_m2p0"
 ; RV32A: .attribute 5, "rv32i2p0_a2p0"
 ; RV32F: .attribute 5, "rv32i2p0_f2p0"
 ; RV32D: .attribute 5, "rv32i2p0_f2p0_d2p0"
 ; RV32C: .attribute 5, "rv32i2p0_c2p0"
-; RV32V: .attribute 5, "rv32i2p0_v0p10_zvlsseg0p10"
+; RV32V: .attribute 5, "rv32i2p0_v0p10_zvamo0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
 ; RV32ZFHMIN: .attribute 5, "rv32i2p0_f2p0_zfhmin0p1"
 ; RV32ZFH: .attribute 5, "rv32i2p0_f2p0_zfh0p1_zfhmin0p1"
 ; RV32ZBA: .attribute 5, "rv32i2p0_zba1p0"
 ; RV32ZBB: .attribute 5, "rv32i2p0_zbb1p0"
 ; RV32ZBC: .attribute 5, "rv32i2p0_zbc1p0"
 ; RV32ZBE: .attribute 5, "rv32i2p0_zbe0p93"
 ; RV32ZBF: .attribute 5, "rv32i2p0_zbf0p93"
 ; RV32ZBM: .attribute 5, "rv32i2p0_zbm0p93"
 ; RV32ZBP: .attribute 5, "rv32i2p0_zbp0p93"
 ; RV32ZBR: .attribute 5, "rv32i2p0_zbr0p93"
 ; RV32ZBS: .attribute 5, "rv32i2p0_zbs1p0"
 ; RV32ZBT: .attribute 5, "rv32i2p0_zbt0p93"
-; RV32COMBINED: .attribute 5, "rv32i2p0_f2p0_v0p10_zfh0p1_zfhmin0p1_zbb1p0_zvlsseg0p10"
+; RV32COMBINED: .attribute 5, "rv32i2p0_f2p0_v0p10_zfh0p1_zfhmin0p1_zbb1p0_zvamo0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
 
 ; RV64M: .attribute 5, "rv64i2p0_m2p0"
 ; RV64A: .attribute 5, "rv64i2p0_a2p0"
 ; RV64F: .attribute 5, "rv64i2p0_f2p0"
 ; RV64D: .attribute 5, "rv64i2p0_f2p0_d2p0"
 ; RV64C: .attribute 5, "rv64i2p0_c2p0"
 ; RV64ZFHMIN: .attribute 5, "rv64i2p0_f2p0_zfhmin0p1"
 ; RV64ZFH: .attribute 5, "rv64i2p0_f2p0_zfh0p1_zfhmin0p1"
 ; RV64ZBA: .attribute 5, "rv64i2p0_zba1p0"
 ; RV64ZBB: .attribute 5, "rv64i2p0_zbb1p0"
 ; RV64ZBC: .attribute 5, "rv64i2p0_zbc1p0"
 ; RV64ZBE: .attribute 5, "rv64i2p0_zbe0p93"
 ; RV64ZBF: .attribute 5, "rv64i2p0_zbf0p93"
 ; RV64ZBM: .attribute 5, "rv64i2p0_zbm0p93"
 ; RV64ZBP: .attribute 5, "rv64i2p0_zbp0p93"
 ; RV64ZBR: .attribute 5, "rv64i2p0_zbr0p93"
 ; RV64ZBS: .attribute 5, "rv64i2p0_zbs1p0"
 ; RV64ZBT: .attribute 5, "rv64i2p0_zbt0p93"
-; RV64V: .attribute 5, "rv64i2p0_v0p10_zvlsseg0p10"
-; RV64COMBINED: .attribute 5, "rv64i2p0_f2p0_v0p10_zfh0p1_zfhmin0p1_zbb1p0_zvlsseg0p10"
+; RV64V: .attribute 5, "rv64i2p0_v0p10_zvamo0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
+; RV64COMBINED: .attribute 5, "rv64i2p0_f2p0_v0p10_zfh0p1_zfhmin0p1_zbb1p0_zvamo0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
 
 
 define i32 @addi(i32 %a) {
   %1 = add i32 %a, 1
   ret i32 %1
 }

llvm/test/MC/RISCV/attribute-arch.s

 # CHECK: attribute      5, "rv32i2p0_m2p0_a2p0_f2p0_d2p0_c2p0"
 
 .attribute arch, "rv32ima2p0_fdc"
 # CHECK: attribute      5, "rv32i2p0_m2p0_a2p0_f2p0_d2p0_c2p0"
 
 ## Experimental extensions require version string to be explicitly specified
 
 .attribute arch, "rv32iv0p10"
-# CHECK: attribute      5, "rv32i2p0_v0p10_zvlsseg0p10"
+# CHECK: attribute      5, "rv32i2p0_v0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
 
 .attribute arch, "rv32izba1p0"
 # CHECK: attribute      5, "rv32i2p0_zba1p0"
 
 .attribute arch, "rv32izbb1p0"
 # CHECK: attribute      5, "rv32i2p0_zbb1p0"
 
 .attribute arch, "rv32izbc1p0"

 # CHECK: attribute      5, "rv32i2p0_zbt0p93"
 
 .attribute arch, "rv32ifzfhmin0p1"
 # CHECK: attribute      5, "rv32i2p0_f2p0_zfhmin0p1"
 
 .attribute arch, "rv32ifzfh0p1"
 # CHECK: attribute      5, "rv32i2p0_f2p0_zfh0p1_zfhmin0p1"
 
-.attribute arch, "rv32iv0p10zvlsseg0p10"
-# CHECK: attribute      5, "rv32i2p0_v0p10_zvlsseg0p10"
+.attribute arch, "rv32iv0p10_zvlsseg0p10"
+# CHECK: attribute      5, "rv32i2p0_v0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv0p10zvl32b0p10"
+# CHECK: attribute      5, "rv32i2p0_v0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv0p10zvl64b0p10"
+# CHECK: attribute      5, "rv32i2p0_v0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv0p10zvl128b0p10"
+# CHECK: attribute      5, "rv32i2p0_v0p10_zvl128b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv0p10zvl256b0p10"
+# CHECK: attribute      5, "rv32i2p0_v0p10_zvl128b0p10_zvl256b0p10_zvl32b0p10_zvl64b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv0p10zvl512b0p10"
+# CHECK: attribute      5, "rv32i2p0_v0p10_zvl128b0p10_zvl256b0p10_zvl32b0p10_zvl512b0p10_zvl64b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv0p10zvl1024b0p10"
+# CHECK: attribute      5, "rv32i2p0_v0p10_zvl1024b0p10_zvl128b0p10_zvl256b0p10_zvl32b0p10_zvl512b0p10_zvl64b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv0p10zvl2048b0p10"
+# CHECK: attribute      5, "rv32i2p0_v0p10_zvl1024b0p10_zvl128b0p10_zvl2048b0p10_zvl256b0p10_zvl32b0p10_zvl512b0p10_zvl64b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv0p10zvl4096b0p10"
+# CHECK: attribute      5, "rv32i2p0_v0p10_zvl1024b0p10_zvl128b0p10_zvl2048b0p10_zvl256b0p10_zvl32b0p10_zvl4096b0p10_zvl512b0p10_zvl64b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv0p10zvl8192b0p10"
+# CHECK: attribute      5, "rv32i2p0_v0p10_zvl1024b0p10_zvl128b0p10_zvl2048b0p10_zvl256b0p10_zvl32b0p10_zvl4096b0p10_zvl512b0p10_zvl64b0p10_zvl8192b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv0p10zvl16384b0p10"
+# CHECK: attribute      5, "rv32i2p0_v0p10_zvl1024b0p10_zvl128b0p10_zvl16384b0p10_zvl2048b0p10_zvl256b0p10_zvl32b0p10_zvl4096b0p10_zvl512b0p10_zvl64b0p10_zvl8192b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv0p10zvl32768b0p10"
+# CHECK: attribute      5, "rv32i2p0_v0p10_zvl1024b0p10_zvl128b0p10_zvl16384b0p10_zvl2048b0p10_zvl256b0p10_zvl32768b0p10_zvl32b0p10_zvl4096b0p10_zvl512b0p10_zvl64b0p10_zvl8192b0p10_zvlsseg0p10"
+
+.attribute arch, "rv32iv0p10zvl65536b0p10"
+# CHECK: attribute      5, "rv32i2p0_v0p10_zvl1024b0p10_zvl128b0p10_zvl16384b0p10_zvl2048b0p10_zvl256b0p10_zvl32768b0p10_zvl32b0p10_zvl4096b0p10_zvl512b0p10_zvl64b0p10_zvl65536b0p10_zvl8192b0p10_zvlsseg0p10"