[PoC][RISCV] Define a symbol flags and a dynamic tag to avoid lazy binding for vector calls.

[HsiangKai]

Summary

This is the primitive work for https://github.com/riscv/riscv-elf-psabi-doc/pull/190.

Functions with vector arguments will use vector registers to pass
arguments, In the dynamic linker resolver, we plan not to save/restore
the vector argument registers for lazy binding efficiency. To avoid
ruining the vector arguments by the dynamic linker resolver, functions
with vector arguments will not go through the resolver.

To achieve the goal, we will annotate the function symbols with
STO_RISCV_VARIANT_CC flag and add DT_RISCV_VARIANT_CC tag in the dynamic
section. For assembler, we add a new directive, .variant_cc, to annotate
the symbol has special calling convention and does not go through the
resolver.

[HsiangKai]

Related discussions in RISC-V psABI is here. https://github.com/riscv/riscv-elf-psabi-doc/issues/66

[craig.topper]

llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp

156

Put with the other emitDirective* methods?

llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.h

42

Maybe put this with the other emitDirective* declarations?

llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp

205

Use a reference liek the two functions right above this for consistency.

llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp

358 ↗

(On Diff #348885)

This is incorrect if the element size of the vector is larger than i64. Not sure how much that matters in practice since it would be pretty unusual to have such a vector argument/return.

I was really hoping to find a way to get this from Machine IR directly. MachineRegisterInfo does have a list of livein physical registers, but I can't find anywhere that knows what physical registers are used for returns

[jhenderson]

Could you please split this patch into a patch that adds the new enum values, which would include the llvm-readobj and yaml2obj/obj2yaml changes, and then another patch (or patches) with the rest in? The latter builds on the former, but the former doesn't need the latter to work.

llvm/tools/llvm-readobj/ELFDumper.cpp

1605

Nit: clang-format

[jrtc27]

llvm/tools/llvm-readobj/ELFDumper.cpp

3776

So if STO_RISCV_VARIANT_CC isn't set but another bit is we now don't print anything? This looks like a bug in the AArch64 code you've copied?

[HsiangKai]

Address comments.

[HsiangKai]

clang-format.

[HsiangKai]

Record IsVectorCall in RISCVMachineFunctionInfo.

[HsiangKai]

Move RISCVTargetStreamer::emitDirectiveVariantCC near to emitDirectiveXXX.

[jrtc27]

llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp

203

RMFI?

[MaskRay]

llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp

2210

unneeded blank line

2216

unneeded blank line

2221

Delete // Eat the symbol which does not convey more information than the code

2223

comments are usually full sentences ending with .

2225

addErrorSuffix is generally not useful because the error contains the source line.

llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.h

106

If Symbol is non-null, prefer a reference.

llvm/include/llvm/BinaryFormat/DynamicTags.def

 #define PPC_DYNAMIC_TAG_DEFINED
 #endif
 
 #ifndef PPC64_DYNAMIC_TAG
 #define PPC64_DYNAMIC_TAG(name, value) DYNAMIC_TAG(name, value)
 #define PPC64_DYNAMIC_TAG_DEFINED
 #endif
 
+#ifndef RISCV_DYNAMIC_TAG
+#define RISCV_DYNAMIC_TAG(name, value) DYNAMIC_TAG(name, value)
+#define RISCV_DYNAMIC_TAG_DEFINED
+#endif
+
 #ifndef DYNAMIC_TAG_MARKER
 #define DYNAMIC_TAG_MARKER(name, value) DYNAMIC_TAG(name, value)
 #define DYNAMIC_TAG_MARKER_DEFINED
 #endif
 
 DYNAMIC_TAG(NULL, 0)        // Marks end of dynamic array.
 DYNAMIC_TAG(NEEDED, 1)      // String table offset of needed library.
 DYNAMIC_TAG(PLTRELSZ, 2)    // Size of relocation entries in PLT.

 // PPC specific dynamic table entries.
 PPC_DYNAMIC_TAG(PPC_GOT, 0x70000000) // Uses Secure PLT ABI.
 PPC_DYNAMIC_TAG(PPC_OPT, 0x70000001) // Has TLS optimization.
 
 // PPC64 specific dynamic table entries.
 PPC64_DYNAMIC_TAG(PPC64_GLINK, 0x70000000) // Address of 32 bytes before the
                                            // first glink lazy resolver stub.
 
+// RISC-V specific dynamic table entries.
+RISCV_DYNAMIC_TAG(RISCV_VARIANT_CC, 0x70000001)
+
 // Sun machine-independent extensions.
 DYNAMIC_TAG(AUXILIARY, 0x7FFFFFFD) // Shared object to load before self
 DYNAMIC_TAG(USED, 0x7FFFFFFE)      // Same as DT_NEEDED
 DYNAMIC_TAG(FILTER, 0x7FFFFFFF)    // Shared object to get values from
 
 
 #ifdef DYNAMIC_TAG_MARKER_DEFINED
 #undef DYNAMIC_TAG_MARKER

 #ifdef PPC_DYNAMIC_TAG_DEFINED
 #undef PPC_DYNAMIC_TAG
 #undef PPC_DYNAMIC_TAG_DEFINED
 #endif
 #ifdef PPC64_DYNAMIC_TAG_DEFINED
 #undef PPC64_DYNAMIC_TAG
 #undef PPC64_DYNAMIC_TAG_DEFINED
 #endif
+#ifdef RISCV_DYNAMIC_TAG_DEFINED
+#undef RISCV_DYNAMIC_TAG
+#undef RISCV_DYNAMIC_TAG_DEFINED
+#endif

llvm/include/llvm/BinaryFormat/ELF.h

 #include "ELFRelocs/Hexagon.def"
 };
 
 // ELF Relocation type for Lanai.
 enum {
 #include "ELFRelocs/Lanai.def"
 };
 
+// Special values for the st_other field in the symbol table entry for RISC-V.
+enum {
+  // Symbol may follow different calling convention than standard calling
+  // conventions.
+  STO_RISCV_VARIANT_CC = 0x80
+};
+
 // RISCV Specific e_flags
 enum : unsigned {
   EF_RISCV_RVC = 0x0001,
   EF_RISCV_FLOAT_ABI = 0x0006,
   EF_RISCV_FLOAT_ABI_SOFT = 0x0000,
   EF_RISCV_FLOAT_ABI_SINGLE = 0x0002,
   EF_RISCV_FLOAT_ABI_DOUBLE = 0x0004,
   EF_RISCV_FLOAT_ABI_QUAD = 0x0006,

llvm/lib/Object/ELF.cpp

#undef MIPS_DYNAMIC_TAG
 
   case ELF::EM_PPC64:
     switch (Type) {
 #define PPC64_DYNAMIC_TAG(name, value) DYNAMIC_STRINGIFY_ENUM(name, value)
 #include "llvm/BinaryFormat/DynamicTags.def"
 #undef PPC64_DYNAMIC_TAG
     }
     break;
+
+  case ELF::EM_RISCV:
+    switch (Type) {
+#define RISCV_DYNAMIC_TAG(name, value) DYNAMIC_STRINGIFY_ENUM(name, value)
+#include "llvm/BinaryFormat/DynamicTags.def"
+#undef RISCV_DYNAMIC_TAG
+    }
+    break;
   }
 #undef DYNAMIC_TAG
   switch (Type) {
 // Now handle all dynamic tags except the architecture specific ones
 #define AARCH64_DYNAMIC_TAG(name, value)
 #define MIPS_DYNAMIC_TAG(name, value)
 #define HEXAGON_DYNAMIC_TAG(name, value)
 #define PPC64_DYNAMIC_TAG(name, value)
+#define RISCV_DYNAMIC_TAG(name, value)
 // Also ignore marker tags such as DT_HIOS (maps to DT_VERNEEDNUM), etc.
 #define DYNAMIC_TAG_MARKER(name, value)
 #define DYNAMIC_TAG(name, value) case value: return #name;
 #include "llvm/BinaryFormat/DynamicTags.def"
 #undef DYNAMIC_TAG
 #undef AARCH64_DYNAMIC_TAG
 #undef MIPS_DYNAMIC_TAG
 #undef HEXAGON_DYNAMIC_TAG
 #undef PPC64_DYNAMIC_TAG
+#undef RISCV_DYNAMIC_TAG
 #undef DYNAMIC_TAG_MARKER
 #undef DYNAMIC_STRINGIFY_ENUM
   default:
     return "<unknown:>0x" + utohexstr(Type, true);
   }
 }
 
 template <class ELFT>

llvm/lib/ObjectYAML/ELFYAML.cpp

void ScalarEnumerationTraits<ELFYAML::ELF_DYNTAG>::enumeration(
   assert(Object && "The IO context is not initialized");
 
 // Disable architecture specific tags by default. We might enable them below.
 #define AARCH64_DYNAMIC_TAG(name, value)
 #define MIPS_DYNAMIC_TAG(name, value)
 #define HEXAGON_DYNAMIC_TAG(name, value)
 #define PPC_DYNAMIC_TAG(name, value)
 #define PPC64_DYNAMIC_TAG(name, value)
+#define RISCV_DYNAMIC_TAG(name, value)
 // Ignore marker tags such as DT_HIOS (maps to DT_VERNEEDNUM), etc.
 #define DYNAMIC_TAG_MARKER(name, value)
 
 #define STRINGIFY(X) (#X)
 #define DYNAMIC_TAG(X, Y) IO.enumCase(Value, STRINGIFY(DT_##X), ELF::DT_##X);
   switch (Object->getMachine()) {
   case ELF::EM_AARCH64:
 #undef AARCH64_DYNAMIC_TAG
#define PPC_DYNAMIC_TAG(name, value)
     break;
   case ELF::EM_PPC64:
 #undef PPC64_DYNAMIC_TAG
 #define PPC64_DYNAMIC_TAG(name, value) DYNAMIC_TAG(name, value)
 #include "llvm/BinaryFormat/DynamicTags.def"
 #undef PPC64_DYNAMIC_TAG
 #define PPC64_DYNAMIC_TAG(name, value)
     break;
+  case ELF::EM_RISCV:
+#undef RISCV_DYNAMIC_TAG
+#define RISCV_DYNAMIC_TAG(name, value) DYNAMIC_TAG(name, value)
+#include "llvm/BinaryFormat/DynamicTags.def"
+#undef RISCV_DYNAMIC_TAG
+#define RISCV_DYNAMIC_TAG(name, value)
+    break;
   default:
 #include "llvm/BinaryFormat/DynamicTags.def"
     break;
   }
 #undef AARCH64_DYNAMIC_TAG
 #undef MIPS_DYNAMIC_TAG
 #undef HEXAGON_DYNAMIC_TAG
 #undef PPC_DYNAMIC_TAG
 #undef PPC64_DYNAMIC_TAG
+#undef RISCV_DYNAMIC_TAG
 #undef DYNAMIC_TAG_MARKER
 #undef STRINGIFY
 #undef DYNAMIC_TAG
 
   IO.enumFallback<Hex64>(Value);
 }
 
 void ScalarEnumerationTraits<ELFYAML::MIPS_AFL_REG>::enumeration(
if (EMachine == ELF::EM_MIPS) {
       Map["STO_MIPS_MICROMIPS"] = ELF::STO_MIPS_MICROMIPS;
       Map["STO_MIPS_PIC"] = ELF::STO_MIPS_PIC;
       Map["STO_MIPS_PLT"] = ELF::STO_MIPS_PLT;
       Map["STO_MIPS_OPTIONAL"] = ELF::STO_MIPS_OPTIONAL;
     }
 
     if (EMachine == ELF::EM_AARCH64)
       Map["STO_AARCH64_VARIANT_PCS"] = ELF::STO_AARCH64_VARIANT_PCS;
+
+    if (EMachine == ELF::EM_RISCV)
+      Map["STO_RISCV_VARIANT_CC"] = ELF::STO_RISCV_VARIANT_CC;
+
     return Map;
   }
 
   IO &YamlIO;
   Optional<std::vector<StOtherPiece>> Other;
   std::string UnknownFlagsHolder;
 };
 

llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp

#include "RISCVGenAsmMatcher.inc"
   OperandMatchResultTy parseJALOffset(OperandVector &Operands);
   OperandMatchResultTy parseVTypeI(OperandVector &Operands);
   OperandMatchResultTy parseMaskReg(OperandVector &Operands);
 
   bool parseOperand(OperandVector &Operands, StringRef Mnemonic);
 
   bool parseDirectiveOption();
   bool parseDirectiveAttribute();
+  bool parseDirectiveVariantCC();
 
   void setFeatureBits(uint64_t Feature, StringRef FeatureString) {
     if (!(getSTI().getFeatureBits()[Feature])) {
       MCSubtargetInfo &STI = copySTI();
       setAvailableFeatures(
           ComputeAvailableFeatures(STI.ToggleFeature(FeatureString)));
     }
   }
bool RISCVAsmParser::ParseDirective(AsmToken DirectiveID) {
   // error. Otherwise it returns true to give the generic parser a
   // chance at recognizing it.
   StringRef IDVal = DirectiveID.getString();
 
   if (IDVal == ".option")
     return parseDirectiveOption();
   else if (IDVal == ".attribute")
     return parseDirectiveAttribute();
+  else if (IDVal == ".variant_cc")
+    return parseDirectiveVariantCC();
 
   return true;
 }
 
 bool RISCVAsmParser::parseDirectiveOption() {
   MCAsmParser &Parser = getParser();
   // Get the option token.
   AsmToken Tok = Parser.getTok();
if (Tag != RISCVAttrs::ARCH) {
 
       getTargetStreamer().emitTextAttribute(Tag, formalArchStr);
     }
   }
 
   return false;
 }
 
+/// parseDirectiveVariantCC
+///  ::= .variant_cc symbol
+bool RISCVAsmParser::parseDirectiveVariantCC() {
+  MCAsmParser &Parser = getParser();
+
+  const AsmToken &Tok = Parser.getTok();
+  if (Tok.isNot(AsmToken::Identifier))
+    return TokError("expected symbol name");
+
+  StringRef SymbolName = Tok.getIdentifier();
+
+  MCSymbol *Sym = getContext().lookupSymbol(SymbolName);
+  if (!Sym)
+    return TokError("unknown symbol in '.variant_cc' directive");
+
+  Parser.Lex(); // Eat the symbol
+
+  // Shouldn't be any more tokens
+  if (parseToken(AsmToken::EndOfStatement))
+    return addErrorSuffix(" in '.variant_cc' directive");
+
+  getTargetStreamer().emitDirectiveVariantCC(Sym);
+
+  return false;
+}
+
 void RISCVAsmParser::emitToStreamer(MCStreamer &S, const MCInst &Inst) {
   MCInst CInst;
   bool Res = compressInst(CInst, Inst, getSTI(), S.getContext());
   if (Res)
     ++RISCVNumInstrsCompressed;
   S.emitInstruction((Res ? CInst : Inst), getSTI());
 }
 

llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.h

public:
   void emitDirectiveOptionPush() override;
   void emitDirectiveOptionPop() override;
   void emitDirectiveOptionPIC() override;
   void emitDirectiveOptionNoPIC() override;
   void emitDirectiveOptionRVC() override;
   void emitDirectiveOptionNoRVC() override;
   void emitDirectiveOptionRelax() override;
   void emitDirectiveOptionNoRelax() override;
+  void emitDirectiveVariantCC(MCSymbol *Symbol) override;
 };
 }
 #endif

llvm/lib/Target/RISCV/MCTargetDesc/RISCVELFStreamer.cpp

case AttributeType::NumericAndText:
       Result += getULEB128Size(item.Tag);
       Result += getULEB128Size(item.IntValue);
       Result += item.StringValue.size() + 1; // string + '\0';
       break;
     }
   }
   return Result;
 }
+
+void RISCVTargetELFStreamer::emitDirectiveVariantCC(MCSymbol *Symbol) {
+  cast<MCSymbolELF>(Symbol)->setOther(ELF::STO_RISCV_VARIANT_CC);
+}

llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.h

public:
   virtual void emitDirectiveOptionPush();
   virtual void emitDirectiveOptionPop();
   virtual void emitDirectiveOptionPIC();
   virtual void emitDirectiveOptionNoPIC();
   virtual void emitDirectiveOptionRVC();
   virtual void emitDirectiveOptionNoRVC();
   virtual void emitDirectiveOptionRelax();
   virtual void emitDirectiveOptionNoRelax();
+  /// Callback used to implement the .variant_cc directive.
+  virtual void emitDirectiveVariantCC(MCSymbol *Symbol);
   virtual void emitAttribute(unsigned Attribute, unsigned Value);
   virtual void finishAttributeSection();
   virtual void emitTextAttribute(unsigned Attribute, StringRef String);
   virtual void emitIntTextAttribute(unsigned Attribute, unsigned IntValue,
                                     StringRef StringValue);
 
   void emitTargetAttributes(const MCSubtargetInfo &STI);
 };
 
 // This part is for ascii assembly output
 class RISCVTargetAsmStreamer : public RISCVTargetStreamer {
   formatted_raw_ostream &OS;
 
   void finishAttributeSection() override;
   void emitAttribute(unsigned Attribute, unsigned Value) override;
   void emitTextAttribute(unsigned Attribute, StringRef String) override;
   void emitIntTextAttribute(unsigned Attribute, unsigned IntValue,
                             StringRef StringValue) override;
 
 public:
   RISCVTargetAsmStreamer(MCStreamer &S, formatted_raw_ostream &OS);
 
   void emitDirectiveOptionPush() override;
   void emitDirectiveOptionPop() override;
   void emitDirectiveOptionPIC() override;
   void emitDirectiveOptionNoPIC() override;
   void emitDirectiveOptionRVC() override;
   void emitDirectiveOptionNoRVC() override;
   void emitDirectiveOptionRelax() override;
   void emitDirectiveOptionNoRelax() override;
+  void emitDirectiveVariantCC(MCSymbol *Symbol) override;
 };
 
 }
 #endif

llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp

 void RISCVTargetStreamer::emitDirectiveOptionPush() {}
 void RISCVTargetStreamer::emitDirectiveOptionPop() {}
 void RISCVTargetStreamer::emitDirectiveOptionPIC() {}
 void RISCVTargetStreamer::emitDirectiveOptionNoPIC() {}
 void RISCVTargetStreamer::emitDirectiveOptionRVC() {}
 void RISCVTargetStreamer::emitDirectiveOptionNoRVC() {}
 void RISCVTargetStreamer::emitDirectiveOptionRelax() {}
 void RISCVTargetStreamer::emitDirectiveOptionNoRelax() {}
+void RISCVTargetStreamer::emitDirectiveVariantCC(MCSymbol *Symbol) {}
 void RISCVTargetStreamer::emitAttribute(unsigned Attribute, unsigned Value) {}
 void RISCVTargetStreamer::finishAttributeSection() {}
 void RISCVTargetStreamer::emitTextAttribute(unsigned Attribute,
                                             StringRef String) {}
 void RISCVTargetStreamer::emitIntTextAttribute(unsigned Attribute,
                                                unsigned IntValue,
                                                StringRef StringValue) {}
 

 void RISCVTargetAsmStreamer::emitDirectiveOptionRelax() {
   OS << "\t.option\trelax\n";
 }
 
 void RISCVTargetAsmStreamer::emitDirectiveOptionNoRelax() {
   OS << "\t.option\tnorelax\n";
 }
 
+void RISCVTargetAsmStreamer::emitDirectiveVariantCC(MCSymbol *Symbol) {
+  OS << "\t.variant_cc\t" << Symbol->getName() << "\n";
+}
+
 void RISCVTargetAsmStreamer::emitAttribute(unsigned Attribute, unsigned Value) {
   OS << "\t.attribute\t" << Attribute << ", " << Twine(Value) << "\n";
 }
 
 void RISCVTargetAsmStreamer::emitTextAttribute(unsigned Attribute,
                                                StringRef String) {
   OS << "\t.attribute\t" << Attribute << ", \"" << String << "\"\n";
 }
 
 void RISCVTargetAsmStreamer::emitIntTextAttribute(unsigned Attribute,
                                                   unsigned IntValue,
                                                   StringRef StringValue) {}
 
 void RISCVTargetAsmStreamer::finishAttributeSection() {}

llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp

 // of machine-dependent LLVM code to the RISCV assembly language.
 //
 //===----------------------------------------------------------------------===//
 
 #include "MCTargetDesc/RISCVInstPrinter.h"
 #include "MCTargetDesc/RISCVMCExpr.h"
 #include "MCTargetDesc/RISCVTargetStreamer.h"
 #include "RISCV.h"
+#include "RISCVMachineFunctionInfo.h"
 #include "RISCVTargetMachine.h"
 #include "TargetInfo/RISCVTargetInfo.h"
 #include "llvm/ADT/Statistic.h"
 #include "llvm/CodeGen/AsmPrinter.h"
 #include "llvm/CodeGen/MachineConstantPool.h"
 #include "llvm/CodeGen/MachineFunctionPass.h"
 #include "llvm/CodeGen/MachineInstr.h"
 #include "llvm/CodeGen/MachineModuleInfo.h"
public:
   // Wrapper needed for tblgenned pseudo lowering.
   bool lowerOperand(const MachineOperand &MO, MCOperand &MCOp) const {
     return LowerRISCVMachineOperandToMCOperand(MO, MCOp, *this);
   }
 
   void emitStartOfAsmFile(Module &M) override;
   void emitEndOfAsmFile(Module &M) override;
 
+  void emitFunctionEntryLabel() override;
+
 private:
   void emitAttributes();
 };
 }
 
 #define GEN_COMPRESS_INSTR
 #include "RISCVGenCompressInstEmitter.inc"
 void RISCVAsmPrinter::EmitToStreamer(MCStreamer &S, const MCInst &Inst) {

 }
 
 void RISCVAsmPrinter::emitAttributes() {
   RISCVTargetStreamer &RTS =
       static_cast<RISCVTargetStreamer &>(*OutStreamer->getTargetStreamer());
   RTS.emitTargetAttributes(*STI);
 }
 
+void RISCVAsmPrinter::emitFunctionEntryLabel() {
+  const RISCVMachineFunctionInfo *RVFI =
+      MF->getInfo<RISCVMachineFunctionInfo>();
+  if (RVFI->isVectorCall()) {
+    RISCVTargetStreamer &RTS =
+        static_cast<RISCVTargetStreamer &>(*OutStreamer->getTargetStreamer());
+    RTS.emitDirectiveVariantCC(CurrentFnSym);
+  }
+
+  return AsmPrinter::emitFunctionEntryLabel();
+}
+
 // Force static initialization.
 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializeRISCVAsmPrinter() {
   RegisterAsmPrinter<RISCVAsmPrinter> X(getTheRISCV32Target());
   RegisterAsmPrinter<RISCVAsmPrinter> Y(getTheRISCV64Target());
 }

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

SDValue RISCVTargetLowering::LowerFormalArguments(
 
   if (CallConv == CallingConv::Fast)
     CCInfo.AnalyzeFormalArguments(Ins, CC_RISCV_FastCC);
   else if (CallConv == CallingConv::GHC)
     CCInfo.AnalyzeFormalArguments(Ins, CC_RISCV_GHC);
   else
     analyzeInputArgs(MF, CCInfo, Ins, /*IsRet=*/false);
 
+  bool IsVectorCall = false;
   for (unsigned i = 0, e = ArgLocs.size(); i != e; ++i) {
     CCValAssign &VA = ArgLocs[i];
     SDValue ArgValue;
     // Passing f64 on RV32D with a soft float ABI must be handled as a special
     // case.
     if (VA.getLocVT() == MVT::i32 && VA.getValVT() == MVT::f64)
       ArgValue = unpackF64OnRV32DSoftABI(DAG, Chain, VA, DL);
     else if (VA.isRegLoc())
       ArgValue = unpackFromRegLoc(DAG, Chain, VA, DL, *this);
     else
       ArgValue = unpackFromMemLoc(DAG, Chain, VA, DL);
 
+    // Check the argument is using vector registers or not.
+    if (!IsVectorCall && VA.getLocVT().isScalableVector())
+      IsVectorCall = true;
+
     if (VA.getLocInfo() == CCValAssign::Indirect) {
       // If the original argument was split and passed by reference (e.g. i128
       // on RV32), we need to load all parts of it here (using the same
       // address). Vectors may be partly split to registers and partly to the
       // stack, in which case the base address is partly offset and subsequent
       // stores are relative to that.
       InVals.push_back(DAG.getLoad(VA.getValVT(), DL, Chain, ArgValue,
                                    MachinePointerInfo()));
if (VA.getLocInfo() == CCValAssign::Indirect) {
                                      MachinePointerInfo()));
         ++i;
       }
       continue;
     }
     InVals.push_back(ArgValue);
   }
 
+  if (IsVectorCall) {
+    RISCVMachineFunctionInfo *RVFI = MF.getInfo<RISCVMachineFunctionInfo>();
+    RVFI->setIsVectorCall();
+  }
+
   if (IsVarArg) {
     ArrayRef<MCPhysReg> ArgRegs = makeArrayRef(ArgGPRs);
     unsigned Idx = CCInfo.getFirstUnallocated(ArgRegs);
     const TargetRegisterClass *RC = &RISCV::GPRRegClass;
     MachineFrameInfo &MFI = MF.getFrameInfo();
     MachineRegisterInfo &RegInfo = MF.getRegInfo();
     RISCVMachineFunctionInfo *RVFI = MF.getInfo<RISCVMachineFunctionInfo>();
 

 }
 
 SDValue
 RISCVTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
                                  bool IsVarArg,
                                  const SmallVectorImpl<ISD::OutputArg> &Outs,
                                  const SmallVectorImpl<SDValue> &OutVals,
                                  const SDLoc &DL, SelectionDAG &DAG) const {
-  const MachineFunction &MF = DAG.getMachineFunction();
+  MachineFunction &MF = DAG.getMachineFunction();
   const RISCVSubtarget &STI = MF.getSubtarget<RISCVSubtarget>();
 
   // Stores the assignment of the return value to a location.
   SmallVector<CCValAssign, 16> RVLocs;
 
   // Info about the registers and stack slot.
   CCState CCInfo(CallConv, IsVarArg, DAG.getMachineFunction(), RVLocs,
                  *DAG.getContext());
 
   analyzeOutputArgs(DAG.getMachineFunction(), CCInfo, Outs, /*IsRet=*/true,
                     nullptr);
 
   if (CallConv == CallingConv::GHC && !RVLocs.empty())
     report_fatal_error("GHC functions return void only");
 
   SDValue Glue;
   SmallVector<SDValue, 4> RetOps(1, Chain);
+  bool IsVectorCall = false;
 
   // Copy the result values into the output registers.
   for (unsigned i = 0, e = RVLocs.size(); i < e; ++i) {
     SDValue Val = OutVals[i];
     CCValAssign &VA = RVLocs[i];
     assert(VA.isRegLoc() && "Can only return in registers!");
 
     if (VA.getLocVT() == MVT::i32 && VA.getValVT() == MVT::f64) {
if (VA.getLocVT() == MVT::i32 && VA.getValVT() == MVT::f64) {
 
       Chain = DAG.getCopyToReg(Chain, DL, RegLo, Lo, Glue);
       Glue = Chain.getValue(1);
       RetOps.push_back(DAG.getRegister(RegLo, MVT::i32));
       Chain = DAG.getCopyToReg(Chain, DL, RegHi, Hi, Glue);
       Glue = Chain.getValue(1);
       RetOps.push_back(DAG.getRegister(RegHi, MVT::i32));
     } else {
+      // Check the return value is using vector registers or not.
+      if (!IsVectorCall && VA.getLocVT().isScalableVector())
+        IsVectorCall = true;
+
       // Handle a 'normal' return.
       Val = convertValVTToLocVT(DAG, Val, VA, DL, Subtarget);
       Chain = DAG.getCopyToReg(Chain, DL, VA.getLocReg(), Val, Glue);
 
       if (STI.isRegisterReservedByUser(VA.getLocReg()))
         MF.getFunction().getContext().diagnose(DiagnosticInfoUnsupported{
             MF.getFunction(),
             "Return value register required, but has been reserved."});
 
       // Guarantee that all emitted copies are stuck together.
       Glue = Chain.getValue(1);
       RetOps.push_back(DAG.getRegister(VA.getLocReg(), VA.getLocVT()));
     }
   }
 
+  if (IsVectorCall) {
+    RISCVMachineFunctionInfo *RVFI = MF.getInfo<RISCVMachineFunctionInfo>();
+    RVFI->setIsVectorCall();
+  }
+
   RetOps[0] = Chain; // Update chain.
 
   // Add the glue node if we have it.
   if (Glue.getNode()) {
     RetOps.push_back(Glue);
   }
 
   // Interrupt service routines use different return instructions.

llvm/lib/Target/RISCV/RISCVMachineFunctionInfo.h

private:
   /// Size of any opaque stack adjustment due to save/restore libcalls.
   unsigned LibCallStackSize = 0;
   /// Size of RVV stack.
   uint64_t RVVStackSize = 0;
   /// Padding required to keep RVV stack aligned within the main stack.
   uint64_t RVVPadding = 0;
   /// Size of stack frame to save callee saved registers
   unsigned CalleeSavedStackSize = 0;
+  /// Is there any vector argument or return?
+  bool IsVectorCall = false;
 
 public:
   RISCVMachineFunctionInfo(const MachineFunction &MF) {}
 
   int getVarArgsFrameIndex() const { return VarArgsFrameIndex; }
   void setVarArgsFrameIndex(int Index) { VarArgsFrameIndex = Index; }
 
   unsigned getVarArgsSaveSize() const { return VarArgsSaveSize; }
public:
   uint64_t getRVVStackSize() const { return RVVStackSize; }
   void setRVVStackSize(uint64_t Size) { RVVStackSize = Size; }
 
   uint64_t getRVVPadding() const { return RVVPadding; }
   void setRVVPadding(uint64_t Padding) { RVVPadding = Padding; }
 
   unsigned getCalleeSavedStackSize() const { return CalleeSavedStackSize; }
   void setCalleeSavedStackSize(unsigned Size) { CalleeSavedStackSize = Size; }
+
+  bool isVectorCall() const { return IsVectorCall; }
+  void setIsVectorCall() { IsVectorCall = true; }
 };
 
 } // end namespace llvm
 
 #endif // LLVM_LIB_TARGET_RISCV_RISCVMACHINEFUNCTIONINFO_H

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-variant-cc.ll

+; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -riscv-v-vector-bits-min=128 -o - %s \
+; RUN:  | FileCheck %s --check-prefix=CHECK-ASM
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -riscv-v-vector-bits-min=128 -filetype=obj -o - %s \
+; RUN:   | llvm-readobj --symbols - | FileCheck %s --check-prefix=CHECK-OBJ
+
+define i32 @base_cc() {
+; CHECK-ASM-LABEL: base_cc:
+; CHECK-ASM-NOT: .variant_cc
+; CHECK-OBJ-LABEL: Name: base_cc
+; CHECK-OBJ: Other: 0
+  ret i32 42
+}
+
+define <4 x i32> @fixed_vector_vector_cc_1() {
+; CHECK-ASM: .variant_cc fixed_vector_vector_cc_1
+; CHECK-ASM-NEXT: fixed_vector_vector_cc_1:
+; CHECK-OBJ-LABEL: Name: fixed_vector_vector_cc_1
+; CHECK-OBJ: Other [ (0x80)
+  ret <4 x i32> undef
+}
+
+define <4 x i1> @fixed_vector_vector_cc_2() {
+; CHECK-ASM: .variant_cc fixed_vector_vector_cc_2
+; CHECK-ASM-NEXT: fixed_vector_vector_cc_2:
+; CHECK-OBJ-LABEL: Name: fixed_vector_vector_cc_2
+; CHECK-OBJ: Other [ (0x80)
+  ret <4 x i1> undef
+}
+
+define void @fixed_vector_vector_cc_3(<4 x i32> %arg) {
+; CHECK-ASM: .variant_cc fixed_vector_vector_cc_3
+; CHECK-ASM-NEXT: fixed_vector_vector_cc_3:
+; CHECK-OBJ-LABEL: Name: fixed_vector_vector_cc_3
+; CHECK-OBJ: Other [ (0x80)
+  ret void
+}
+
+define void @fixed_vector_vector_cc_4(<4 x i1> %arg) {
+; CHECK-ASM: .variant_cc fixed_vector_vector_cc_4
+; CHECK-ASM-NEXT: fixed_vector_vector_cc_4:
+; CHECK-OBJ-LABEL: Name: fixed_vector_vector_cc_4
+; CHECK-OBJ: Other [ (0x80)
+  ret void
+}

llvm/test/CodeGen/RISCV/rvv/variant-cc.ll

+; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -o - %s | FileCheck %s --check-prefix=CHECK-ASM
+; RUN: llc -mtriple=riscv64 -mattr=+experimental-v -filetype=obj -o - %s \
+; RUN:   | llvm-readobj --symbols - | FileCheck %s --check-prefix=CHECK-OBJ
+
+define i32 @base_cc() {
+; CHECK-ASM-LABEL: base_cc:
+; CHECK-ASM-NOT: .variant_cc
+; CHECK-OBJ-LABEL: Name: base_cc
+; CHECK-OBJ: Other: 0
+  ret i32 42
+}
+
+define <4 x i32> @fixed_vector_cc_1(<4 x i32> %arg) {
+; CHECK-ASM-LABEL: fixed_vector_cc_1:
+; CHECK-ASM-NOT: .variant_cc
+; CHECK-OBJ-LABEL: Name: fixed_vector_cc_1
+; CHECK-OBJ: Other: 0
+  ret <4 x i32> %arg
+}
+
+define <vscale x 4 x i32> @rvv_vector_cc_1() {
+; CHECK-ASM: .variant_cc rvv_vector_cc_1
+; CHECK-ASM-NEXT: rvv_vector_cc_1:
+; CHECK-OBJ-LABEL: Name: rvv_vector_cc_1
+; CHECK-OBJ: Other [ (0x80)
+  ret <vscale x 4 x i32> undef
+}
+
+define <vscale x 4 x i1> @rvv_vector_cc_2() {
+; CHECK-ASM: .variant_cc rvv_vector_cc_2
+; CHECK-ASM-NEXT: rvv_vector_cc_2:
+; CHECK-OBJ-LABEL: Name: rvv_vector_cc_2
+; CHECK-OBJ: Other [ (0x80)
+  ret <vscale x 4 x i1> undef
+}
+
+define void @rvv_vector_cc_3(<vscale x 4 x i32> %arg) {
+; CHECK-ASM: .variant_cc rvv_vector_cc_3
+; CHECK-ASM-NEXT: rvv_vector_cc_3:
+; CHECK-OBJ-LABEL: Name: rvv_vector_cc_3
+; CHECK-OBJ: Other [ (0x80)
+  ret void
+}
+
+define void @rvv_vector_cc_4(<vscale x 4 x i1> %arg) {
+; CHECK-ASM: .variant_cc rvv_vector_cc_4
+; CHECK-ASM-NEXT: rvv_vector_cc_4:
+; CHECK-OBJ-LABEL: Name: rvv_vector_cc_4
+; CHECK-OBJ: Other [ (0x80)
+  ret void
+}

llvm/test/MC/RISCV/directive-variant_cc-err.s

+// RUN: not llvm-mc -triple riscv64 -filetype asm -o - %s 2>&1 | FileCheck %s
+
+.variant_cc
+// CHECK: error: expected symbol name
+// CHECK-NEXT:   .variant_cc
+// CHECK-NEXT:              ^
+
+.variant_cc foo
+// CHECK: error: unknown symbol in '.variant_cc' directive
+// CHECK-NEXT:   .variant_cc foo
+// CHECK-NEXT:               ^
+
+.global foo
+.variant_cc foo bar
+// CHECK: error: unexpected token in '.variant_cc' directive
+// CHECK-NEXT:   .variant_cc foo bar
+// CHECK-NEXT:                   ^

llvm/test/MC/RISCV/directive-variant_cc.s

+// RUN: llvm-mc -triple riscv64 -filetype asm -o - %s | FileCheck %s
+// RUN: llvm-mc -triple riscv64 -filetype obj -o - %s \
+// RUN:   | llvm-readobj --symbols - | FileCheck %s --check-prefix=CHECK-ST_OTHER
+
+.text
+.global foo
+.variant_cc foo
+// CHECK: .variant_cc foo
+
+// CHECK-ST_OTHER: Name: foo
+// CHECK-ST_OTHER: Other [ (0x80)

llvm/test/tools/llvm-readobj/ELF/dynamic-tags-machine-specific.test

Entries:
         Value: 0
 ProgramHeaders:
   - Type:     PT_LOAD
     FirstSec: .dynamic
     LastSec:  .dynamic
   - Type:     PT_DYNAMIC
     FirstSec: .dynamic
     LastSec:  .dynamic
+
+## Case 6: Test that RISC-V machine-specific tags can be dumped.
+# RUN: yaml2obj --docnum=6 %s -o %t.riscv
+# RUN: llvm-readobj --dynamic-table %t.riscv | FileCheck %s --check-prefix=LLVM-RISCV
+# RUN: llvm-readelf --dynamic-table %t.riscv | FileCheck %s --check-prefix=GNU-RISCV
+
+# LLVM-RISCV:     DynamicSection [ (2 entries)
+# LLVM-RISCV-NEXT:  Tag                Type                Name/Value
+# LLVM-RISCV-NEXT:  0x0000000070000001 RISCV_VARIANT_CC    1
+# LLVM-RISCV-NEXT:  0x0000000000000000 NULL                0x0
+# LLVM-RISCV-NEXT:]
+
+# GNU-RISCV:      Dynamic section at offset {{.*}} contains 2 entries:
+# GNU-RISCV-NEXT:  Tag                Type                  Name/Value
+# GNU-RISCV-NEXT:  0x0000000070000001 (RISCV_VARIANT_CC)    1
+# GNU-RISCV-NEXT:  0x0000000000000000 (NULL)                0x0
+
+--- !ELF
+FileHeader:
+  Class:   ELFCLASS64
+  Data:    ELFDATA2LSB
+  Type:    ET_EXEC
+  Machine: EM_RISCV
+Sections:
+  - Name: .dynamic
+    Type: SHT_DYNAMIC
+    Entries:
+      - Tag:   DT_RISCV_VARIANT_CC
+        Value: 1
+      - Tag:   DT_NULL
+        Value: 0
+ProgramHeaders:
+  - Type:     PT_LOAD
+    FirstSec: .dynamic
+    LastSec:  .dynamic
+  - Type:     PT_DYNAMIC
+    FirstSec: .dynamic
+    LastSec:  .dynamic

llvm/test/tools/llvm-readobj/ELF/riscv-symbols-stother.test

+## Check that we are able to dump RISC-V STO_* flags correctly when dumping symbols.
+
+# RUN: yaml2obj %s -o %t.o
+# RUN: llvm-readobj --symbols %t.o | FileCheck %s --check-prefix=LLVM
+# RUN: llvm-readelf --symbols %t.o | FileCheck %s --check-prefix=GNU
+
+# LLVM:      Name: foo1
+# LLVM:      Other [ (0x80)
+# LLVM-NEXT:   STO_RISCV_VARIANT_CC (0x80)
+# LLVM-NEXT: ]
+
+# GNU:      Symbol table '.symtab' contains 2 entries:
+# GNU:      1: 0000000000000000 0 NOTYPE LOCAL DEFAULT   [VARIANT_CC]      UND foo1
+
+--- !ELF
+FileHeader:
+  Class:   ELFCLASS64
+  Data:    ELFDATA2LSB
+  Type:    ET_REL
+  Machine: EM_RISCV
+Symbols:
+  - Name: foo1
+    Other: [ STO_RISCV_VARIANT_CC ]

llvm/test/tools/obj2yaml/ELF/riscv-sym-other.yaml

+## Check RISC-V st_other extension support.
+
+# RUN: yaml2obj %s -o %t
+# RUN: obj2yaml %t | FileCheck %s
+
+# CHECK: Symbols:
+# CHECK:  - Name:  foo1
+# CHECK:    Other: [ STO_RISCV_VARIANT_CC ]
+
+--- !ELF
+FileHeader:
+  Class:   ELFCLASS64
+  Data:    ELFDATA2LSB
+  Type:    ET_REL
+  Machine: EM_RISCV
+Symbols:
+  - Name:  foo1
+    Other: [ STO_RISCV_VARIANT_CC ]

llvm/tools/llvm-readobj/ELFDumper.cpp

 };
 
 static const EnumEntry<unsigned> ElfMips16SymOtherFlags[] = {
   LLVM_READOBJ_ENUM_ENT(ELF, STO_MIPS_OPTIONAL),
   LLVM_READOBJ_ENUM_ENT(ELF, STO_MIPS_PLT),
   LLVM_READOBJ_ENUM_ENT(ELF, STO_MIPS_MIPS16)
 };
 
+static const EnumEntry<unsigned> ElfRISCVSymOtherFlags[] = {
+    LLVM_READOBJ_ENUM_ENT(ELF, STO_RISCV_VARIANT_CC)};
+
 static const char *getElfMipsOptionsOdkType(unsigned Odk) {
   switch (Odk) {
   LLVM_READOBJ_ENUM_CASE(ELF, ODK_NULL);
   LLVM_READOBJ_ENUM_CASE(ELF, ODK_REGINFO);
   LLVM_READOBJ_ENUM_CASE(ELF, ODK_EXCEPTIONS);
   LLVM_READOBJ_ENUM_CASE(ELF, ODK_PAD);
   LLVM_READOBJ_ENUM_CASE(ELF, ODK_HWPATCH);
   LLVM_READOBJ_ENUM_CASE(ELF, ODK_FILL);
case EM_MIPS:
     case DT_MIPS_RLD_MAP_REL:
       return FormatHexValue(Value);
     case DT_MIPS_FLAGS:
       return FormatFlags(Value, makeArrayRef(ElfDynamicDTMipsFlags));
     default:
       break;
     }
     break;
+  case EM_RISCV:
+    switch (Type) {
+    case DT_RISCV_VARIANT_CC:
+      return std::to_string(Value);
+    default:
+      break;
+    }
+    break;
   default:
     break;
   }
 
   switch (Type) {
   case DT_PLTREL:
     if (Value == DT_REL)
       return "REL";
if (this->Obj.getHeader().e_machine == ELF::EM_AARCH64) {
       uint8_t Other = Symbol.st_other & ~0x3;
       if (Other & STO_AARCH64_VARIANT_PCS) {
         Other &= ~STO_AARCH64_VARIANT_PCS;
         Fields[5].Str += " [VARIANT_PCS";
         if (Other != 0)
           Fields[5].Str.append(" | " + to_hexString(Other, false));
         Fields[5].Str.append("]");
       }
+    } else if (this->Obj.getHeader().e_machine == ELF::EM_RISCV) {
+      uint8_t Other = Symbol.st_other & ~0x3;
+      Fields[5].Str += " [";
+      if (Other & STO_RISCV_VARIANT_CC) {
+        Other &= ~STO_RISCV_VARIANT_CC;
+        Fields[5].Str += "VARIANT_CC";
+        if (Other != 0)
+          Fields[5].Str += " | ";
+      }
+      // If there is any unrecognized bit, print the value directly.
+      if (Other)
+        Fields[5].Str += to_hexString(Other, false);
+      Fields[5].Str += "]";
     } else {
       Fields[5].Str +=
           " [<other: " + to_string(format_hex(Symbol.st_other, 2)) + ">]";
     }
   }
 
   Fields[6].Column += NonVisibilityBitsUsed ? 13 : 0;
   Fields[6].Str = getSymbolSectionNdx(Symbol, SymIndex, ShndxTable);
if (this->Obj.getHeader().e_machine == EM_MIPS) {
       else
         SymOtherFlags.insert(SymOtherFlags.end(),
                              std::begin(ElfMipsSymOtherFlags),
                              std::end(ElfMipsSymOtherFlags));
     } else if (this->Obj.getHeader().e_machine == EM_AARCH64) {
       SymOtherFlags.insert(SymOtherFlags.end(),
                            std::begin(ElfAArch64SymOtherFlags),
                            std::end(ElfAArch64SymOtherFlags));
+    } else if (this->Obj.getHeader().e_machine == EM_RISCV) {
+      SymOtherFlags.insert(SymOtherFlags.end(),
+                           std::begin(ElfRISCVSymOtherFlags),
+                           std::end(ElfRISCVSymOtherFlags));
     }
     W.printFlags("Other", Symbol.st_other, makeArrayRef(SymOtherFlags), 0x3u);
   }
   printSymbolSection(Symbol, SymIndex, ShndxTable);
 }
 
 template <class ELFT>
 void LLVMELFDumper<ELFT>::printSymbols(bool PrintSymbols,