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[PoC][RISCV] Define a symbol flags and a dynamic tag to avoid lazy binding for vector calls.
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Authored by HsiangKai on May 31 2021, 11:08 PM.

Details

Summary

This is the primitive work for https://github.com/riscv/riscv-elf-psabi-doc/pull/190.

Functions with vector arguments will use vector registers to pass
arguments, In the dynamic linker resolver, we plan not to save/restore
the vector argument registers for lazy binding efficiency. To avoid
ruining the vector arguments by the dynamic linker resolver, functions
with vector arguments will not go through the resolver.

To achieve the goal, we will annotate the function symbols with
STO_RISCV_VARIANT_CC flag and add DT_RISCV_VARIANT_CC tag in the dynamic
section. For assembler, we add a new directive, .variant_cc, to annotate
the symbol has special calling convention and does not go through the
resolver.

Diff Detail

Unit TestsFailed

TimeTest
90 msx64 windows > Flang.Driver::debug-parsing-log.f90
Script: -- : 'RUN: at line 1'; c:\ws\w5\llvm-project\premerge-checks\build\bin\flang-new.exe -fc1 -fdebug-dump-parsing-log C:\ws\w5\llvm-project\premerge-checks\flang\test\Driver\debug-parsing-log.f90 2>&1 | c:\ws\w5\llvm-project\premerge-checks\build\bin\filecheck.exe C:\ws\w5\llvm-project\premerge-checks\flang\test\Driver\debug-parsing-log.f90
60 msx64 windows > Flang.Driver::debug-provenance.f90
Script: -- : 'RUN: at line 6'; c:\ws\w5\llvm-project\premerge-checks\build\bin\flang-new.exe -fc1 -fdebug-dump-provenance C:\ws\w5\llvm-project\premerge-checks\flang\test\Driver\debug-provenance.f90 2>&1 | c:\ws\w5\llvm-project\premerge-checks\build\bin\filecheck.exe C:\ws\w5\llvm-project\premerge-checks\flang\test\Driver\debug-provenance.f90
20 msx64 windows > Flang.Evaluate::folding01.f90
Script: -- : 'RUN: at line 1'; C:\ws\w5\llvm-project\premerge-checks\flang\test\Evaluate/test_folding.sh C:\ws\w5\llvm-project\premerge-checks\flang\test\Evaluate\folding01.f90 C:\ws\w5\llvm-project\premerge-checks\build\tools\flang\test\Evaluate\Output\folding01.f90.tmp c:\ws\w5\llvm-project\premerge-checks\build\bin\flang-new.exe -fc1
0 msx64 windows > Flang.Evaluate::folding02.f90
Script: -- : 'RUN: at line 1'; C:\ws\w5\llvm-project\premerge-checks\flang\test\Evaluate/test_folding.sh C:\ws\w5\llvm-project\premerge-checks\flang\test\Evaluate\folding02.f90 C:\ws\w5\llvm-project\premerge-checks\build\tools\flang\test\Evaluate\Output\folding02.f90.tmp c:\ws\w5\llvm-project\premerge-checks\build\bin\flang-new.exe -fc1
0 msx64 windows > Flang.Evaluate::folding03.f90
Script: -- : 'RUN: at line 1'; C:\ws\w5\llvm-project\premerge-checks\flang\test\Evaluate/test_folding.sh C:\ws\w5\llvm-project\premerge-checks\flang\test\Evaluate\folding03.f90 C:\ws\w5\llvm-project\premerge-checks\build\tools\flang\test\Evaluate\Output\folding03.f90.tmp c:\ws\w5\llvm-project\premerge-checks\build\bin\flang-new.exe -fc1
View Full Test Results (481 Failed)

Event Timeline

HsiangKai created this revision.May 31 2021, 11:08 PM
HsiangKai requested review of this revision.May 31 2021, 11:08 PM
Herald added a project: Restricted Project. · View Herald TranscriptMay 31 2021, 11:08 PM
craig.topper added inline comments.Jun 1 2021, 12:43 PM
llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.cpp
156

Put with the other emitDirective* methods?

llvm/lib/Target/RISCV/MCTargetDesc/RISCVTargetStreamer.h
42

Maybe put this with the other emitDirective* declarations?

llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
205

Use a reference liek the two functions right above this for consistency.

llvm/lib/Target/RISCV/RISCVRegisterInfo.cpp
358 ↗(On Diff #348885)

This is incorrect if the element size of the vector is larger than i64. Not sure how much that matters in practice since it would be pretty unusual to have such a vector argument/return.

I was really hoping to find a way to get this from Machine IR directly. MachineRegisterInfo does have a list of livein physical registers, but I can't find anywhere that knows what physical registers are used for returns

Could you please split this patch into a patch that adds the new enum values, which would include the llvm-readobj and yaml2obj/obj2yaml changes, and then another patch (or patches) with the rest in? The latter builds on the former, but the former doesn't need the latter to work.

llvm/tools/llvm-readobj/ELFDumper.cpp
1605

Nit: clang-format

jrtc27 added inline comments.Jun 7 2021, 5:02 AM
llvm/tools/llvm-readobj/ELFDumper.cpp
3776

So if STO_RISCV_VARIANT_CC isn't set but another bit is we now don't print anything? This looks like a bug in the AArch64 code you've copied?

HsiangKai updated this revision to Diff 356430.Sun, Jul 4, 10:41 PM

Address comments.

HsiangKai updated this revision to Diff 356431.Sun, Jul 4, 10:44 PM
HsiangKai marked 3 inline comments as done.

clang-format.

HsiangKai marked 2 inline comments as done.Sun, Jul 4, 10:46 PM
HsiangKai updated this revision to Diff 356433.Sun, Jul 4, 11:14 PM

Record IsVectorCall in RISCVMachineFunctionInfo.

HsiangKai marked an inline comment as done.Sun, Jul 4, 11:15 PM
HsiangKai updated this revision to Diff 356435.Sun, Jul 4, 11:27 PM

Move RISCVTargetStreamer::emitDirectiveVariantCC near to emitDirectiveXXX.