[RISCV] Enable SPLAT_VECTOR for fixed vXi64 types on RV32.

[craig.topper]

Summary

This replaces D98479.

This allows type legalization to form SPLAT_VECTOR_PARTS so we don't
lose the splattedness when the scalar type is split.

I'm handling SPLAT_VECTOR_PARTS for fixed vectors separately so
we can continue using non-VL nodes for scalable vectors.

I limited to RV32+vXi64 because DAGCombiner::visitBUILD_VECTOR likes
to form SPLAT_VECTOR before seeing if it can replace the BUILD_VECTOR
with other operations. Especially interesting is a splat BUILD_VECTOR of
the extract_vector_elt which can become a splat shuffle, but won't if
we form SPLAT_VECTOR first. We either need to reorder visitBUILD_VECTOR
or add visitSPLAT_VECTOR.

[craig.topper]

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-splat.ll

50–51

This is a regression.

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-vrgather.ll

56 ↗

(On Diff #338660)

grr the script deleted the checks.

[craig.topper]

Fix missing check lines.
clang-format

[craig.topper]

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-vrgather.ll

56 ↗

(On Diff #338661)

This is caused by SPLAT_VECTOR being formed before splat VECTOR_SHUFFLE as noted in the description.

[frasercrmck]

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

2788

I'm wondering if you could fold this optimization into splatPartsI64WithVL

[craig.topper]

Sink constant handling into splatPartsI64WithVL

[frasercrmck]

This is starting to look good. I think it'd be good to have all vectors treated similarly but it isn't time for that yet. Maybe something like visitSplatLike in the DAGCombiner could serve as a generic splat optimization path and avoid us diverging too much like we currently have with BUILD_VECTOR/SPLAT_VECTOR.

Is your plan to address the regressions in this patch or later on? Do you have a feeling of how much work it'd be?

[craig.topper]

Push SPLAT_VECTOR formation to late in visitBUILD_VECTOR which recovers some of the regressions and doesn't effect any other target lit tests.

[craig.topper]

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-splat.ll

50–51

Andrew Waterman's advice at least for us was to use stores and a strided load with x0 stride to splat SEW=64 on RV32. This is analogous to the sequence for loading a double precision value from integer data on RV32. Should we use that instead of being clever with shifts/ors?

[craig.topper]

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-splat.ll

50–51

I've implemented the strided store in splatSplitI64WithVL here https://reviews.llvm.org/D101002

[craig.topper]

Rebase

[frasercrmck]

LGTM. There are a couple of areas that need formatting according to clang-tidy.

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

 //===- DAGCombiner.cpp - Implement a DAG node combiner --------------------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
if (SDValue Splat = cast<BuildVectorSDNode>(N)->getSplatValue()) {
           SDValue Concat = DAG.getNode(ISD::CONCAT_VECTORS, SDLoc(N),
                                        NewVT, Ops);
           return DAG.getBitcast(VT, Concat);
         }
       }
     }
   }
 
-  // A splat of a single element is a SPLAT_VECTOR if supported on the target.
-  if (TLI.getOperationAction(ISD::SPLAT_VECTOR, VT) != TargetLowering::Expand)
-    if (SDValue V = cast<BuildVectorSDNode>(N)->getSplatValue()) {
-      assert(!V.isUndef() && "Splat of undef should have been handled earlier");
-      return DAG.getNode(ISD::SPLAT_VECTOR, SDLoc(N), VT, V);
-    }
-
   // Check if we can express BUILD VECTOR via subvector extract.
   if (!LegalTypes && (N->getNumOperands() > 1)) {
     SDValue Op0 = N->getOperand(0);
     auto checkElem = [&](SDValue Op) -> uint64_t {
       if ((Op.getOpcode() == ISD::EXTRACT_VECTOR_ELT) &&
           (Op0.getOperand(0) == Op.getOperand(0)))
         if (auto CNode = dyn_cast<ConstantSDNode>(Op.getOperand(1)))
           return CNode->getZExtValue();
if (SDValue V = reduceBuildVecExtToExtBuildVec(N))
     return V;
 
   if (SDValue V = reduceBuildVecTruncToBitCast(N))
     return V;
 
   if (SDValue V = reduceBuildVecToShuffle(N))
     return V;
 
+  // A splat of a single element is a SPLAT_VECTOR if supported on the target.
+  // Do this late as some of the above may replace the splat.
+  if (TLI.getOperationAction(ISD::SPLAT_VECTOR, VT) != TargetLowering::Expand)
+    if (SDValue V = cast<BuildVectorSDNode>(N)->getSplatValue()) {
+      assert(!V.isUndef() && "Splat of undef should have been handled earlier");
+      return DAG.getNode(ISD::SPLAT_VECTOR, SDLoc(N), VT, V);
+    }
+
   return SDValue();
 }
 
 static SDValue combineConcatVectorOfScalars(SDNode *N, SelectionDAG &DAG) {
   const TargetLowering &TLI = DAG.getTargetLoweringInfo();
   EVT OpVT = N->getOperand(0).getValueType();
 
   // If the operands are legal vectors, leave them alone.

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

 //===-- RISCVISelLowering.cpp - RISCV DAG Lowering Implementation  --------===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
if (Subtarget.useRVVForFixedLengthVectors()) {
         // Operations below are different for between masks and other vectors.
         if (VT.getVectorElementType() == MVT::i1) {
           setOperationAction(ISD::AND, VT, Custom);
           setOperationAction(ISD::OR, VT, Custom);
           setOperationAction(ISD::XOR, VT, Custom);
           continue;
         }
 
+        // Use SPLAT_VECTOR to prevent type legalization from destroying the
+        // splats when type legalizing i64 scalar on RV32.
+        // FIXME: Use SPLAT_VECTOR for all types? DAGCombine probably needs
+        // improvements first.
+        if (!Subtarget.is64Bit() && VT.getVectorElementType() == MVT::i64) {
+          setOperationAction(ISD::SPLAT_VECTOR, VT, Custom);
+          setOperationAction(ISD::SPLAT_VECTOR_PARTS, VT, Custom);
+        }
+
         setOperationAction(ISD::VECTOR_SHUFFLE, VT, Custom);
         setOperationAction(ISD::INSERT_VECTOR_ELT, VT, Custom);
 
         setOperationAction(ISD::MLOAD, VT, Custom);
         setOperationAction(ISD::MSTORE, VT, Custom);
         setOperationAction(ISD::MGATHER, VT, Custom);
         setOperationAction(ISD::MSCATTER, VT, Custom);
         setOperationAction(ISD::ADD, VT, Custom);

 bool RISCVTargetLowering::isShuffleMaskLegal(ArrayRef<int> M, EVT VT) const {
   // Only splats are currently supported.
   if (ShuffleVectorSDNode::isSplatMask(M.data(), VT))
     return true;
 
   return false;
 }
 
+static SDValue lowerSPLAT_VECTOR(SDValue Op, SelectionDAG &DAG,
+                                 const RISCVSubtarget &Subtarget) {
+  MVT VT = Op.getSimpleValueType();
+  assert(VT.isFixedLengthVector() && "Unexpected vector!");
+
+  MVT ContainerVT = getContainerForFixedLengthVector(DAG, VT, Subtarget);
+
+  SDLoc DL(Op);
+  SDValue Mask, VL;
+  std::tie(Mask, VL) = getDefaultVLOps(VT, ContainerVT, DL, DAG, Subtarget);
+
+  unsigned Opc =
+      VT.isFloatingPoint() ? RISCVISD::VFMV_V_F_VL : RISCVISD::VMV_V_X_VL;
+  SDValue Splat = DAG.getNode(Opc, DL, ContainerVT, Op.getOperand(0), VL);
+  return convertFromScalableVector(VT, Splat, DAG, Subtarget);
+}
+
 static SDValue lowerBUILD_VECTOR(SDValue Op, SelectionDAG &DAG,
                                  const RISCVSubtarget &Subtarget) {
   MVT VT = Op.getSimpleValueType();
   assert(VT.isFixedLengthVector() && "Unexpected vector!");
 
   MVT ContainerVT = getContainerForFixedLengthVector(DAG, VT, Subtarget);
 
   SDLoc DL(Op);
if (!DAG.shouldOptForSize() &&
     }
 
     return Vec;
   }
 
   return SDValue();
 }
 
-// Called by type legalization to handle splat of i64 on RV32.
-// FIXME: We can optimize this when the type has sign or zero bits in one
-// of the halves.
-static SDValue splatSplitI64WithVL(const SDLoc &DL, MVT VT, SDValue Scalar,
-                                   SDValue VL, SelectionDAG &DAG,
-                                   const RISCVSubtarget &Subtarget) {
-  SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, Scalar,
-                           DAG.getConstant(0, DL, MVT::i32));
-  SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, Scalar,
-                           DAG.getConstant(1, DL, MVT::i32));
+static SDValue splatPartsI64WithVL(const SDLoc &DL, MVT VT, SDValue Lo,
+                                   SDValue Hi,
+                                   SDValue VL, SelectionDAG &DAG) {
+  if (isa<ConstantSDNode>(Lo) && isa<ConstantSDNode>(Hi)) {
+    int32_t LoC = cast<ConstantSDNode>(Lo)->getSExtValue();
+    int32_t HiC = cast<ConstantSDNode>(Hi)->getSExtValue();
+    // If Hi constant is all the same sign bit as Lo, lower this as a custom
+    // node in order to try and match RVV vector/scalar instructions.
+    if ((LoC >> 31) == HiC)
+      return DAG.getNode(RISCVISD::VMV_V_X_VL, DL, VT, Lo, VL);
+  }
 
   // Fall back to a stack store and stride x0 vector load.
   MachineFunction &MF = DAG.getMachineFunction();
   RISCVMachineFunctionInfo *FuncInfo = MF.getInfo<RISCVMachineFunctionInfo>();
 
   // We use the same frame index we use for moving two i32s into 64-bit FPR.
   // This is an analogous operation.
   int FI = FuncInfo->getMoveF64FrameIndex(MF);
   MachinePointerInfo MPI = MachinePointerInfo::getFixedStack(MF, FI);
   const TargetLowering &TLI = DAG.getTargetLoweringInfo();
   SDValue StackSlot =
       DAG.getFrameIndex(FI, TLI.getPointerTy(DAG.getDataLayout()));
 
   SDValue Chain = DAG.getEntryNode();
   Lo = DAG.getStore(Chain, DL, Lo, StackSlot, MPI, Align(8));
 
   SDValue OffsetSlot =
       DAG.getMemBasePlusOffset(StackSlot, TypeSize::Fixed(4), DL);
   Hi = DAG.getStore(Chain, DL, Hi, OffsetSlot, MPI.getWithOffset(4), Align(8));
 
   Chain = DAG.getNode(ISD::TokenFactor, DL, MVT::Other, Lo, Hi);
 
-  MVT XLenVT = Subtarget.getXLenVT();
   SDVTList VTs = DAG.getVTList({VT, MVT::Other});
-  SDValue IntID = DAG.getTargetConstant(Intrinsic::riscv_vlse, DL, XLenVT);
-  SDValue Ops[] = {Chain, IntID, StackSlot, DAG.getRegister(RISCV::X0, XLenVT),
+  SDValue IntID = DAG.getTargetConstant(Intrinsic::riscv_vlse, DL, MVT::i64);
+  SDValue Ops[] = {Chain, IntID, StackSlot, DAG.getRegister(RISCV::X0, MVT::i64),
                    VL};
 
   return DAG.getMemIntrinsicNode(ISD::INTRINSIC_W_CHAIN, DL, VTs, Ops, MVT::i64,
                                  MPI, Align(8), MachineMemOperand::MOLoad);
 }
 
+// Called by type legalization to handle splat of i64 on RV32.
+// FIXME: We can optimize this when the type has sign or zero bits in one
+// of the halves.
+static SDValue splatSplitI64WithVL(const SDLoc &DL, MVT VT, SDValue Scalar,
+                                   SDValue VL, SelectionDAG &DAG) {
+  assert(Scalar.getValueType() == MVT::i64 && "Unexpected VT!");
+  SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, Scalar,
+                           DAG.getConstant(0, DL, MVT::i32));
+  SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, Scalar,
+                           DAG.getConstant(1, DL, MVT::i32));
+  return splatPartsI64WithVL(DL, VT, Lo, Hi, VL, DAG);
+}
+
 // This function lowers a splat of a scalar operand Splat with the vector
 // length VL. It ensures the final sequence is type legal, which is useful when
 // lowering a splat after type legalization.
 static SDValue lowerScalarSplat(SDValue Scalar, SDValue VL, MVT VT, SDLoc DL,
                                 SelectionDAG &DAG,
                                 const RISCVSubtarget &Subtarget) {
   if (VT.isFloatingPoint())
     return DAG.getNode(RISCVISD::VFMV_V_F_VL, DL, VT, Scalar, VL);
unsigned ExtOpc =
         isa<ConstantSDNode>(Scalar) ? ISD::SIGN_EXTEND : ISD::ANY_EXTEND;
     Scalar = DAG.getNode(ExtOpc, DL, XLenVT, Scalar);
     return DAG.getNode(RISCVISD::VMV_V_X_VL, DL, VT, Scalar, VL);
   }
 
   assert(XLenVT == MVT::i32 && Scalar.getValueType() == MVT::i64 &&
          "Unexpected scalar for splat lowering!");
 
-  // If this is a sign-extended 32-bit constant, we can truncate it and rely
-  // on the instruction to sign-extend since SEW>XLEN.
-  if (auto *CVal = dyn_cast<ConstantSDNode>(Scalar)) {
-    if (isInt<32>(CVal->getSExtValue()))
-      return DAG.getNode(RISCVISD::VMV_V_X_VL, DL, VT,
-                         DAG.getConstant(CVal->getSExtValue(), DL, MVT::i32),
-                         VL);
-  }
-
   // Otherwise use the more complicated splatting algorithm.
-  return splatSplitI64WithVL(DL, VT, Scalar, VL, DAG, Subtarget);
+  return splatSplitI64WithVL(DL, VT, Scalar, VL, DAG);
 }
 
 static SDValue lowerVECTOR_SHUFFLE(SDValue Op, SelectionDAG &DAG,
                                    const RISCVSubtarget &Subtarget) {
   SDValue V1 = Op.getOperand(0);
   SDValue V2 = Op.getOperand(1);
   SDLoc DL(Op);
   MVT XLenVT = Subtarget.getXLenVT();
SDValue RISCVTargetLowering::LowerOperation(SDValue Op,
   case ISD::EXTRACT_SUBVECTOR:
     return lowerEXTRACT_SUBVECTOR(Op, DAG);
   case ISD::STEP_VECTOR:
     return lowerSTEP_VECTOR(Op, DAG);
   case ISD::VECTOR_REVERSE:
     return lowerVECTOR_REVERSE(Op, DAG);
   case ISD::BUILD_VECTOR:
     return lowerBUILD_VECTOR(Op, DAG, Subtarget);
+  case ISD::SPLAT_VECTOR:
+    return lowerSPLAT_VECTOR(Op, DAG, Subtarget);
   case ISD::VECTOR_SHUFFLE:
     return lowerVECTOR_SHUFFLE(Op, DAG, Subtarget);
   case ISD::CONCAT_VECTORS: {
     // Split CONCAT_VECTORS into a series of INSERT_SUBVECTOR nodes. This is
     // better than going through the stack, as the default expansion does.
     SDLoc DL(Op);
     MVT VT = Op.getSimpleValueType();
     unsigned NumOpElts =

 
 // Custom-lower a SPLAT_VECTOR_PARTS where XLEN<SEW, as the SEW element type is
 // illegal (currently only vXi64 RV32).
 // FIXME: We could also catch non-constant sign-extended i32 values and lower
 // them to SPLAT_VECTOR_I64
 SDValue RISCVTargetLowering::lowerSPLAT_VECTOR_PARTS(SDValue Op,
                                                      SelectionDAG &DAG) const {
   SDLoc DL(Op);
-  EVT VecVT = Op.getValueType();
+  MVT VecVT = Op.getSimpleValueType();
   assert(!Subtarget.is64Bit() && VecVT.getVectorElementType() == MVT::i64 &&
          "Unexpected SPLAT_VECTOR_PARTS lowering");
 
   assert(Op.getNumOperands() == 2 && "Unexpected number of operands!");
   SDValue Lo = Op.getOperand(0);
   SDValue Hi = Op.getOperand(1);
 
+  if (VecVT.isFixedLengthVector()) {
+    MVT ContainerVT = getContainerForFixedLengthVector(VecVT);
+    SDLoc DL(Op);
+    SDValue Mask, VL;
+    std::tie(Mask, VL) =
+        getDefaultVLOps(VecVT, ContainerVT, DL, DAG, Subtarget);
+
+    SDValue Res = splatPartsI64WithVL(DL, ContainerVT, Lo, Hi, VL, DAG);
+    return convertFromScalableVector(VecVT, Res, DAG, Subtarget);
+  }
+
   if (isa<ConstantSDNode>(Lo) && isa<ConstantSDNode>(Hi)) {
     int32_t LoC = cast<ConstantSDNode>(Lo)->getSExtValue();
     int32_t HiC = cast<ConstantSDNode>(Hi)->getSExtValue();
     // If Hi constant is all the same sign bit as Lo, lower this as a custom
     // node in order to try and match RVV vector/scalar instructions.
     if ((LoC >> 31) == HiC)
       return DAG.getNode(RISCVISD::SPLAT_VECTOR_I64, DL, VecVT, Lo);
   }
static SDValue lowerVectorIntrinsicSplats(SDValue Op, SelectionDAG &DAG,
   }
 
   // We need to convert the scalar to a splat vector.
   // FIXME: Can we implicitly truncate the scalar if it is known to
   // be sign extended?
   // VL should be the last operand.
   SDValue VL = Op.getOperand(Op.getNumOperands() - 1);
   assert(VL.getValueType() == XLenVT);
-  ScalarOp = splatSplitI64WithVL(DL, VT, ScalarOp, VL, DAG, Subtarget);
+  ScalarOp = splatSplitI64WithVL(DL, VT, ScalarOp, VL, DAG);
   return DAG.getNode(Op->getOpcode(), DL, Op->getVTList(), Operands);
 }
 
 SDValue RISCVTargetLowering::LowerINTRINSIC_WO_CHAIN(SDValue Op,
                                                      SelectionDAG &DAG) const {
   unsigned IntNo = Op.getConstantOperandVal(0);
   SDLoc DL(Op);
   MVT XLenVT = Subtarget.getXLenVT();
case Intrinsic::riscv_vmv_s_x: {
     // This is an i64 value that lives in two scalar registers. We have to
     // insert this in a convoluted way. First we build vXi64 splat containing
     // the/ two values that we assemble using some bit math. Next we'll use
     // vid.v and vmseq to build a mask with bit 0 set. Then we'll use that mask
     // to merge element 0 from our splat into the source vector.
     // FIXME: This is probably not the best way to do this, but it is
     // consistent with INSERT_VECTOR_ELT lowering so it is a good starting
     // point.
-    //   vmv.v.x vX, hi
-    //   vsll.vx vX, vX, /*32*/
-    //   vmv.v.x vY, lo
-    //   vsll.vx vY, vY, /*32*/
-    //   vsrl.vx vY, vY, /*32*/
-    //   vor.vv vX, vX, vY
+    //   sw lo, (a0)
+    //   sw hi, 4(a0)
+    //   vlse vX, (a0)
     //
     //   vid.v      vVid
     //   vmseq.vx   mMask, vVid, 0
     //   vmerge.vvm vDest, vSrc, vVal, mMask
     MVT VT = Op.getSimpleValueType();
     SDValue Vec = Op.getOperand(1);
     SDValue VL = Op.getOperand(3);
 
     SDValue SplattedVal =
-        splatSplitI64WithVL(DL, VT, Scalar, VL, DAG, Subtarget);
+        splatSplitI64WithVL(DL, VT, Scalar, VL, DAG);
     SDValue SplattedIdx = DAG.getNode(RISCVISD::VMV_V_X_VL, DL, VT,
                                       DAG.getConstant(0, DL, MVT::i32), VL);
 
     MVT MaskVT = MVT::getVectorVT(MVT::i1, VT.getVectorElementCount());
     SDValue Mask = DAG.getNode(RISCVISD::VMSET_VL, DL, MaskVT, VL);
     SDValue VID = DAG.getNode(RISCVISD::VID_VL, DL, VT, Mask, VL);
     SDValue SelectCond =
         DAG.getNode(RISCVISD::SETCC_VL, DL, MaskVT, VID, SplattedIdx,

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-shuffles.ll

 ; RV32-NEXT:    vslideup.vi v27, v25, 6
 ; RV32-NEXT:    addi a0, zero, 113
 ; RV32-NEXT:    vsetivli a1, 1, e8,m1,ta,mu
 ; RV32-NEXT:    vmv.s.x v0, a0
 ; RV32-NEXT:    lui a0, %hi(.LCPI12_0)
 ; RV32-NEXT:    addi a0, a0, %lo(.LCPI12_0)
 ; RV32-NEXT:    vsetivli a1, 8, e16,m1,ta,mu
 ; RV32-NEXT:    vle16.v v25, (a0)
-; RV32-NEXT:    vsetivli a0, 16, e32,m4,ta,mu
-; RV32-NEXT:    vmv.v.i v12, -1
 ; RV32-NEXT:    vsetivli a0, 8, e64,m4,ta,mu
+; RV32-NEXT:    vmv.v.i v12, -1
 ; RV32-NEXT:    vrgatherei16.vv v28, v12, v25
 ; RV32-NEXT:    vsetivli a0, 8, e64,m4,tu,mu
 ; RV32-NEXT:    vrgatherei16.vv v28, v8, v27, v0.t
 ; RV32-NEXT:    vmv4r.v v8, v28
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: vrgather_shuffle_xv_v8i64:
 ; RV64:       # %bb.0:

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int-splat.ll

; CHECK-NEXT:    ret
   %a = insertelement <4 x i32> undef, i32 %y, i32 0
   %b = shufflevector <4 x i32> %a, <4 x i32> undef, <4 x i32> zeroinitializer
   store <4 x i32> %b, <4 x i32>* %x
   ret void
 }
 
 define void @splat_v2i64(<2 x i64>* %x, i64 %y) {
 ; LMULMAX8-RV32-LABEL: splat_v2i64:
 ; LMULMAX8-RV32:       # %bb.0:
-; LMULMAX8-RV32-NEXT:    addi a3, zero, 5
-; LMULMAX8-RV32-NEXT:    vsetivli a4, 1, e8,m1,ta,mu
-; LMULMAX8-RV32-NEXT:    vmv.s.x v0, a3
-; LMULMAX8-RV32-NEXT:    vsetivli a3, 4, e32,m1,ta,mu
-; LMULMAX8-RV32-NEXT:    vmv.v.x v25, a2
-; LMULMAX8-RV32-NEXT:    vmerge.vxm v25, v25, a1, v0
-; LMULMAX8-RV32-NEXT:    vse32.v v25, (a0)
+; LMULMAX8-RV32-NEXT:    addi sp, sp, -16
+; LMULMAX8-RV32-NEXT:    .cfi_def_cfa_offset 16
+; LMULMAX8-RV32-NEXT:    sw a2, 12(sp)
+; LMULMAX8-RV32-NEXT:    sw a1, 8(sp)
+; LMULMAX8-RV32-NEXT:    vsetivli a1, 2, e64,m1,ta,mu
+; LMULMAX8-RV32-NEXT:    addi a1, sp, 8
+; LMULMAX8-RV32-NEXT:    vlse64.v v25, (a1), zero
+; LMULMAX8-RV32-NEXT:    vse64.v v25, (a0)
+; LMULMAX8-RV32-NEXT:    addi sp, sp, 16
 ; LMULMAX8-RV32-NEXT:    ret
 ;
 ; LMULMAX2-RV32-LABEL: splat_v2i64:
 ; LMULMAX2-RV32:       # %bb.0:
-; LMULMAX2-RV32-NEXT:    addi a3, zero, 5
-; LMULMAX2-RV32-NEXT:    vsetivli a4, 1, e8,m1,ta,mu
-; LMULMAX2-RV32-NEXT:    vmv.s.x v0, a3
-; LMULMAX2-RV32-NEXT:    vsetivli a3, 4, e32,m1,ta,mu
-; LMULMAX2-RV32-NEXT:    vmv.v.x v25, a2
-; LMULMAX2-RV32-NEXT:    vmerge.vxm v25, v25, a1, v0
-; LMULMAX2-RV32-NEXT:    vse32.v v25, (a0)
+; LMULMAX2-RV32-NEXT:    addi sp, sp, -16
+; LMULMAX2-RV32-NEXT:    .cfi_def_cfa_offset 16
+; LMULMAX2-RV32-NEXT:    sw a2, 12(sp)
+; LMULMAX2-RV32-NEXT:    sw a1, 8(sp)
+; LMULMAX2-RV32-NEXT:    vsetivli a1, 2, e64,m1,ta,mu
+; LMULMAX2-RV32-NEXT:    addi a1, sp, 8
+; LMULMAX2-RV32-NEXT:    vlse64.v v25, (a1), zero
+; LMULMAX2-RV32-NEXT:    vse64.v v25, (a0)
+; LMULMAX2-RV32-NEXT:    addi sp, sp, 16
 ; LMULMAX2-RV32-NEXT:    ret
 ;
 ; LMULMAX1-RV32-LABEL: splat_v2i64:
 ; LMULMAX1-RV32:       # %bb.0:
-; LMULMAX1-RV32-NEXT:    addi a3, zero, 5
-; LMULMAX1-RV32-NEXT:    vsetivli a4, 1, e8,m1,ta,mu
-; LMULMAX1-RV32-NEXT:    vmv.s.x v0, a3
-; LMULMAX1-RV32-NEXT:    vsetivli a3, 4, e32,m1,ta,mu
-; LMULMAX1-RV32-NEXT:    vmv.v.x v25, a2
-; LMULMAX1-RV32-NEXT:    vmerge.vxm v25, v25, a1, v0
-; LMULMAX1-RV32-NEXT:    vse32.v v25, (a0)
+; LMULMAX1-RV32-NEXT:    addi sp, sp, -16
+; LMULMAX1-RV32-NEXT:    .cfi_def_cfa_offset 16
+; LMULMAX1-RV32-NEXT:    sw a2, 12(sp)
+; LMULMAX1-RV32-NEXT:    sw a1, 8(sp)
+; LMULMAX1-RV32-NEXT:    vsetivli a1, 2, e64,m1,ta,mu
+; LMULMAX1-RV32-NEXT:    addi a1, sp, 8
+; LMULMAX1-RV32-NEXT:    vlse64.v v25, (a1), zero
+; LMULMAX1-RV32-NEXT:    vse64.v v25, (a0)
+; LMULMAX1-RV32-NEXT:    addi sp, sp, 16
 ; LMULMAX1-RV32-NEXT:    ret
 ;
 ; LMULMAX8-RV64-LABEL: splat_v2i64:
 ; LMULMAX8-RV64:       # %bb.0:
 ; LMULMAX8-RV64-NEXT:    vsetivli a2, 2, e64,m1,ta,mu
 ; LMULMAX8-RV64-NEXT:    vmv.v.x v25, a1
 ; LMULMAX8-RV64-NEXT:    vse64.v v25, (a0)
 ; LMULMAX8-RV64-NEXT:    ret
; LMULMAX1-NEXT:    ret
   %b = shufflevector <8 x i32> %a, <8 x i32> undef, <8 x i32> zeroinitializer
   store <8 x i32> %b, <8 x i32>* %x
   ret void
 }
 
 define void @splat_v4i64(<4 x i64>* %x, i64 %y) {
 ; LMULMAX8-RV32-LABEL: splat_v4i64:
 ; LMULMAX8-RV32:       # %bb.0:
-; LMULMAX8-RV32-NEXT:    addi a3, zero, 85
-; LMULMAX8-RV32-NEXT:    vsetivli a4, 1, e8,m1,ta,mu
-; LMULMAX8-RV32-NEXT:    vmv.s.x v0, a3
-; LMULMAX8-RV32-NEXT:    vsetivli a3, 8, e32,m2,ta,mu
-; LMULMAX8-RV32-NEXT:    vmv.v.x v26, a2
-; LMULMAX8-RV32-NEXT:    vmerge.vxm v26, v26, a1, v0
-; LMULMAX8-RV32-NEXT:    vse32.v v26, (a0)
+; LMULMAX8-RV32-NEXT:    addi sp, sp, -16
+; LMULMAX8-RV32-NEXT:    .cfi_def_cfa_offset 16
+; LMULMAX8-RV32-NEXT:    sw a2, 12(sp)
+; LMULMAX8-RV32-NEXT:    sw a1, 8(sp)
+; LMULMAX8-RV32-NEXT:    vsetivli a1, 4, e64,m2,ta,mu
+; LMULMAX8-RV32-NEXT:    addi a1, sp, 8
+; LMULMAX8-RV32-NEXT:    vlse64.v v26, (a1), zero
+; LMULMAX8-RV32-NEXT:    vse64.v v26, (a0)
+; LMULMAX8-RV32-NEXT:    addi sp, sp, 16
 ; LMULMAX8-RV32-NEXT:    ret
 ;
 ; LMULMAX2-RV32-LABEL: splat_v4i64:
 ; LMULMAX2-RV32:       # %bb.0:
-; LMULMAX2-RV32-NEXT:    addi a3, zero, 85
-; LMULMAX2-RV32-NEXT:    vsetivli a4, 1, e8,m1,ta,mu
-; LMULMAX2-RV32-NEXT:    vmv.s.x v0, a3
-; LMULMAX2-RV32-NEXT:    vsetivli a3, 8, e32,m2,ta,mu
-; LMULMAX2-RV32-NEXT:    vmv.v.x v26, a2
-; LMULMAX2-RV32-NEXT:    vmerge.vxm v26, v26, a1, v0
-; LMULMAX2-RV32-NEXT:    vse32.v v26, (a0)
+; LMULMAX2-RV32-NEXT:    addi sp, sp, -16
+; LMULMAX2-RV32-NEXT:    .cfi_def_cfa_offset 16
+; LMULMAX2-RV32-NEXT:    sw a2, 12(sp)
+; LMULMAX2-RV32-NEXT:    sw a1, 8(sp)
+; LMULMAX2-RV32-NEXT:    vsetivli a1, 4, e64,m2,ta,mu
+; LMULMAX2-RV32-NEXT:    addi a1, sp, 8
+; LMULMAX2-RV32-NEXT:    vlse64.v v26, (a1), zero
+; LMULMAX2-RV32-NEXT:    vse64.v v26, (a0)
+; LMULMAX2-RV32-NEXT:    addi sp, sp, 16
 ; LMULMAX2-RV32-NEXT:    ret
 ;
 ; LMULMAX1-RV32-LABEL: splat_v4i64:
 ; LMULMAX1-RV32:       # %bb.0:
 ; LMULMAX1-RV32-NEXT:    addi a3, zero, 5
 ; LMULMAX1-RV32-NEXT:    vsetivli a4, 1, e8,m1,ta,mu
 ; LMULMAX1-RV32-NEXT:    vmv.s.x v0, a3
 ; LMULMAX1-RV32-NEXT:    vsetivli a3, 4, e32,m1,ta,mu

 ; CHECK-NEXT:    ret
   %a = insertelement <4 x i32> undef, i32 0, i32 0
   %b = shufflevector <4 x i32> %a, <4 x i32> undef, <4 x i32> zeroinitializer
   store <4 x i32> %b, <4 x i32>* %x
   ret void
 }
 
 define void @splat_zero_v2i64(<2 x i64>* %x) {
-; LMULMAX8-RV32-LABEL: splat_zero_v2i64:
-; LMULMAX8-RV32:       # %bb.0:
-; LMULMAX8-RV32-NEXT:    vsetivli a1, 4, e32,m1,ta,mu
-; LMULMAX8-RV32-NEXT:    vmv.v.i v25, 0
-; LMULMAX8-RV32-NEXT:    vse32.v v25, (a0)
-; LMULMAX8-RV32-NEXT:    ret
-;
-; LMULMAX2-RV32-LABEL: splat_zero_v2i64:
-; LMULMAX2-RV32:       # %bb.0:
-; LMULMAX2-RV32-NEXT:    vsetivli a1, 4, e32,m1,ta,mu
-; LMULMAX2-RV32-NEXT:    vmv.v.i v25, 0
-; LMULMAX2-RV32-NEXT:    vse32.v v25, (a0)
-; LMULMAX2-RV32-NEXT:    ret
-;
-; LMULMAX1-RV32-LABEL: splat_zero_v2i64:
-; LMULMAX1-RV32:       # %bb.0:
-; LMULMAX1-RV32-NEXT:    vsetivli a1, 4, e32,m1,ta,mu
-; LMULMAX1-RV32-NEXT:    vmv.v.i v25, 0
-; LMULMAX1-RV32-NEXT:    vse32.v v25, (a0)
-; LMULMAX1-RV32-NEXT:    ret
-;
-; LMULMAX8-RV64-LABEL: splat_zero_v2i64:
-; LMULMAX8-RV64:       # %bb.0:
-; LMULMAX8-RV64-NEXT:    vsetivli a1, 2, e64,m1,ta,mu
-; LMULMAX8-RV64-NEXT:    vmv.v.i v25, 0
-; LMULMAX8-RV64-NEXT:    vse64.v v25, (a0)
-; LMULMAX8-RV64-NEXT:    ret
-;
-; LMULMAX2-RV64-LABEL: splat_zero_v2i64:
-; LMULMAX2-RV64:       # %bb.0:
-; LMULMAX2-RV64-NEXT:    vsetivli a1, 2, e64,m1,ta,mu
-; LMULMAX2-RV64-NEXT:    vmv.v.i v25, 0
-; LMULMAX2-RV64-NEXT:    vse64.v v25, (a0)
-; LMULMAX2-RV64-NEXT:    ret
-;
-; LMULMAX1-RV64-LABEL: splat_zero_v2i64:
-; LMULMAX1-RV64:       # %bb.0:
-; LMULMAX1-RV64-NEXT:    vsetivli a1, 2, e64,m1,ta,mu
-; LMULMAX1-RV64-NEXT:    vmv.v.i v25, 0
-; LMULMAX1-RV64-NEXT:    vse64.v v25, (a0)
-; LMULMAX1-RV64-NEXT:    ret
+; CHECK-LABEL: splat_zero_v2i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetivli a1, 2, e64,m1,ta,mu
+; CHECK-NEXT:    vmv.v.i v25, 0
+; CHECK-NEXT:    vse64.v v25, (a0)
+; CHECK-NEXT:    ret
   %a = insertelement <2 x i64> undef, i64 0, i32 0
   %b = shufflevector <2 x i64> %a, <2 x i64> undef, <2 x i32> zeroinitializer
   store <2 x i64> %b, <2 x i64>* %x
   ret void
 }
 
 define void @splat_zero_v32i8(<32 x i8>* %x) {
 ; LMULMAX8-LABEL: splat_zero_v32i8:

 ; LMULMAX1-NEXT:    ret
   %a = insertelement <8 x i32> undef, i32 0, i32 0
   %b = shufflevector <8 x i32> %a, <8 x i32> undef, <8 x i32> zeroinitializer
   store <8 x i32> %b, <8 x i32>* %x
   ret void
 }
 
 define void @splat_zero_v4i64(<4 x i64>* %x) {
-; LMULMAX8-RV32-LABEL: splat_zero_v4i64:
-; LMULMAX8-RV32:       # %bb.0:
-; LMULMAX8-RV32-NEXT:    vsetivli a1, 8, e32,m2,ta,mu
-; LMULMAX8-RV32-NEXT:    vmv.v.i v26, 0
-; LMULMAX8-RV32-NEXT:    vse32.v v26, (a0)
-; LMULMAX8-RV32-NEXT:    ret
+; LMULMAX8-LABEL: splat_zero_v4i64:
+; LMULMAX8:       # %bb.0:
+; LMULMAX8-NEXT:    vsetivli a1, 4, e64,m2,ta,mu
+; LMULMAX8-NEXT:    vmv.v.i v26, 0
+; LMULMAX8-NEXT:    vse64.v v26, (a0)
+; LMULMAX8-NEXT:    ret
 ;
-; LMULMAX2-RV32-LABEL: splat_zero_v4i64:
-; LMULMAX2-RV32:       # %bb.0:
-; LMULMAX2-RV32-NEXT:    vsetivli a1, 8, e32,m2,ta,mu
-; LMULMAX2-RV32-NEXT:    vmv.v.i v26, 0
-; LMULMAX2-RV32-NEXT:    vse32.v v26, (a0)
-; LMULMAX2-RV32-NEXT:    ret
+; LMULMAX2-LABEL: splat_zero_v4i64:
+; LMULMAX2:       # %bb.0:
+; LMULMAX2-NEXT:    vsetivli a1, 4, e64,m2,ta,mu
+; LMULMAX2-NEXT:    vmv.v.i v26, 0
+; LMULMAX2-NEXT:    vse64.v v26, (a0)
+; LMULMAX2-NEXT:    ret
 ;
 ; LMULMAX1-RV32-LABEL: splat_zero_v4i64:
 ; LMULMAX1-RV32:       # %bb.0:
 ; LMULMAX1-RV32-NEXT:    vsetivli a1, 4, e32,m1,ta,mu
 ; LMULMAX1-RV32-NEXT:    vmv.v.i v25, 0
 ; LMULMAX1-RV32-NEXT:    addi a1, a0, 16
 ; LMULMAX1-RV32-NEXT:    vse32.v v25, (a1)
 ; LMULMAX1-RV32-NEXT:    vse32.v v25, (a0)
 ; LMULMAX1-RV32-NEXT:    ret
 ;
-; LMULMAX8-RV64-LABEL: splat_zero_v4i64:
-; LMULMAX8-RV64:       # %bb.0:
-; LMULMAX8-RV64-NEXT:    vsetivli a1, 4, e64,m2,ta,mu
-; LMULMAX8-RV64-NEXT:    vmv.v.i v26, 0
-; LMULMAX8-RV64-NEXT:    vse64.v v26, (a0)
-; LMULMAX8-RV64-NEXT:    ret
-;
-; LMULMAX2-RV64-LABEL: splat_zero_v4i64:
-; LMULMAX2-RV64:       # %bb.0:
-; LMULMAX2-RV64-NEXT:    vsetivli a1, 4, e64,m2,ta,mu
-; LMULMAX2-RV64-NEXT:    vmv.v.i v26, 0
-; LMULMAX2-RV64-NEXT:    vse64.v v26, (a0)
-; LMULMAX2-RV64-NEXT:    ret
-;
 ; LMULMAX1-RV64-LABEL: splat_zero_v4i64:
 ; LMULMAX1-RV64:       # %bb.0:
 ; LMULMAX1-RV64-NEXT:    vsetivli a1, 2, e64,m1,ta,mu
 ; LMULMAX1-RV64-NEXT:    vmv.v.i v25, 0
 ; LMULMAX1-RV64-NEXT:    addi a1, a0, 16
 ; LMULMAX1-RV64-NEXT:    vse64.v v25, (a1)
 ; LMULMAX1-RV64-NEXT:    vse64.v v25, (a0)
 ; LMULMAX1-RV64-NEXT:    ret

 ; CHECK-NEXT:    ret
   %a = insertelement <4 x i32> undef, i32 -1, i32 0
   %b = shufflevector <4 x i32> %a, <4 x i32> undef, <4 x i32> zeroinitializer
   store <4 x i32> %b, <4 x i32>* %x
   ret void
 }
 
 define void @splat_allones_v2i64(<2 x i64>* %x) {
-; LMULMAX8-RV32-LABEL: splat_allones_v2i64:
-; LMULMAX8-RV32:       # %bb.0:
-; LMULMAX8-RV32-NEXT:    vsetivli a1, 4, e32,m1,ta,mu
-; LMULMAX8-RV32-NEXT:    vmv.v.i v25, -1
-; LMULMAX8-RV32-NEXT:    vse32.v v25, (a0)
-; LMULMAX8-RV32-NEXT:    ret
-;
-; LMULMAX2-RV32-LABEL: splat_allones_v2i64:
-; LMULMAX2-RV32:       # %bb.0:
-; LMULMAX2-RV32-NEXT:    vsetivli a1, 4, e32,m1,ta,mu
-; LMULMAX2-RV32-NEXT:    vmv.v.i v25, -1
-; LMULMAX2-RV32-NEXT:    vse32.v v25, (a0)
-; LMULMAX2-RV32-NEXT:    ret
-;
-; LMULMAX1-RV32-LABEL: splat_allones_v2i64:
-; LMULMAX1-RV32:       # %bb.0:
-; LMULMAX1-RV32-NEXT:    vsetivli a1, 4, e32,m1,ta,mu
-; LMULMAX1-RV32-NEXT:    vmv.v.i v25, -1
-; LMULMAX1-RV32-NEXT:    vse32.v v25, (a0)
-; LMULMAX1-RV32-NEXT:    ret
-;
-; LMULMAX8-RV64-LABEL: splat_allones_v2i64:
-; LMULMAX8-RV64:       # %bb.0:
-; LMULMAX8-RV64-NEXT:    vsetivli a1, 2, e64,m1,ta,mu
-; LMULMAX8-RV64-NEXT:    vmv.v.i v25, -1
-; LMULMAX8-RV64-NEXT:    vse64.v v25, (a0)
-; LMULMAX8-RV64-NEXT:    ret
-;
-; LMULMAX2-RV64-LABEL: splat_allones_v2i64:
-; LMULMAX2-RV64:       # %bb.0:
-; LMULMAX2-RV64-NEXT:    vsetivli a1, 2, e64,m1,ta,mu
-; LMULMAX2-RV64-NEXT:    vmv.v.i v25, -1
-; LMULMAX2-RV64-NEXT:    vse64.v v25, (a0)
-; LMULMAX2-RV64-NEXT:    ret
-;
-; LMULMAX1-RV64-LABEL: splat_allones_v2i64:
-; LMULMAX1-RV64:       # %bb.0:
-; LMULMAX1-RV64-NEXT:    vsetivli a1, 2, e64,m1,ta,mu
-; LMULMAX1-RV64-NEXT:    vmv.v.i v25, -1
-; LMULMAX1-RV64-NEXT:    vse64.v v25, (a0)
-; LMULMAX1-RV64-NEXT:    ret
+; CHECK-LABEL: splat_allones_v2i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetivli a1, 2, e64,m1,ta,mu
+; CHECK-NEXT:    vmv.v.i v25, -1
+; CHECK-NEXT:    vse64.v v25, (a0)
+; CHECK-NEXT:    ret
   %a = insertelement <2 x i64> undef, i64 -1, i32 0
   %b = shufflevector <2 x i64> %a, <2 x i64> undef, <2 x i32> zeroinitializer
   store <2 x i64> %b, <2 x i64>* %x
   ret void
 }
 
 define void @splat_allones_v32i8(<32 x i8>* %x) {
 ; LMULMAX8-LABEL: splat_allones_v32i8:

 ; LMULMAX1-NEXT:    ret
   %a = insertelement <8 x i32> undef, i32 -1, i32 0
   %b = shufflevector <8 x i32> %a, <8 x i32> undef, <8 x i32> zeroinitializer
   store <8 x i32> %b, <8 x i32>* %x
   ret void
 }
 
 define void @splat_allones_v4i64(<4 x i64>* %x) {
-; LMULMAX8-RV32-LABEL: splat_allones_v4i64:
-; LMULMAX8-RV32:       # %bb.0:
-; LMULMAX8-RV32-NEXT:    vsetivli a1, 8, e32,m2,ta,mu
-; LMULMAX8-RV32-NEXT:    vmv.v.i v26, -1
-; LMULMAX8-RV32-NEXT:    vse32.v v26, (a0)
-; LMULMAX8-RV32-NEXT:    ret
+; LMULMAX8-LABEL: splat_allones_v4i64:
+; LMULMAX8:       # %bb.0:
+; LMULMAX8-NEXT:    vsetivli a1, 4, e64,m2,ta,mu
+; LMULMAX8-NEXT:    vmv.v.i v26, -1
+; LMULMAX8-NEXT:    vse64.v v26, (a0)
+; LMULMAX8-NEXT:    ret
 ;
-; LMULMAX2-RV32-LABEL: splat_allones_v4i64:
-; LMULMAX2-RV32:       # %bb.0:
-; LMULMAX2-RV32-NEXT:    vsetivli a1, 8, e32,m2,ta,mu
-; LMULMAX2-RV32-NEXT:    vmv.v.i v26, -1
-; LMULMAX2-RV32-NEXT:    vse32.v v26, (a0)
-; LMULMAX2-RV32-NEXT:    ret
+; LMULMAX2-LABEL: splat_allones_v4i64:
+; LMULMAX2:       # %bb.0:
+; LMULMAX2-NEXT:    vsetivli a1, 4, e64,m2,ta,mu
+; LMULMAX2-NEXT:    vmv.v.i v26, -1
+; LMULMAX2-NEXT:    vse64.v v26, (a0)
+; LMULMAX2-NEXT:    ret
 ;
 ; LMULMAX1-RV32-LABEL: splat_allones_v4i64:
 ; LMULMAX1-RV32:       # %bb.0:
 ; LMULMAX1-RV32-NEXT:    vsetivli a1, 4, e32,m1,ta,mu
 ; LMULMAX1-RV32-NEXT:    vmv.v.i v25, -1
 ; LMULMAX1-RV32-NEXT:    addi a1, a0, 16
 ; LMULMAX1-RV32-NEXT:    vse32.v v25, (a1)
 ; LMULMAX1-RV32-NEXT:    vse32.v v25, (a0)
 ; LMULMAX1-RV32-NEXT:    ret
 ;
-; LMULMAX8-RV64-LABEL: splat_allones_v4i64:
-; LMULMAX8-RV64:       # %bb.0:
-; LMULMAX8-RV64-NEXT:    vsetivli a1, 4, e64,m2,ta,mu
-; LMULMAX8-RV64-NEXT:    vmv.v.i v26, -1
-; LMULMAX8-RV64-NEXT:    vse64.v v26, (a0)
-; LMULMAX8-RV64-NEXT:    ret
-;
-; LMULMAX2-RV64-LABEL: splat_allones_v4i64:
-; LMULMAX2-RV64:       # %bb.0:
-; LMULMAX2-RV64-NEXT:    vsetivli a1, 4, e64,m2,ta,mu
-; LMULMAX2-RV64-NEXT:    vmv.v.i v26, -1
-; LMULMAX2-RV64-NEXT:    vse64.v v26, (a0)
-; LMULMAX2-RV64-NEXT:    ret
-;
 ; LMULMAX1-RV64-LABEL: splat_allones_v4i64:
 ; LMULMAX1-RV64:       # %bb.0:
 ; LMULMAX1-RV64-NEXT:    vsetivli a1, 2, e64,m1,ta,mu
 ; LMULMAX1-RV64-NEXT:    vmv.v.i v25, -1
 ; LMULMAX1-RV64-NEXT:    addi a1, a0, 16
 ; LMULMAX1-RV64-NEXT:    vse64.v v25, (a1)
 ; LMULMAX1-RV64-NEXT:    vse64.v v25, (a0)
 ; LMULMAX1-RV64-NEXT:    ret
   %a = insertelement <4 x i64> undef, i64 -1, i32 0
   %b = shufflevector <4 x i64> %a, <4 x i64> undef, <4 x i32> zeroinitializer
   store <4 x i64> %b, <4 x i64>* %x
   ret void
 }
 
 ; This requires a bitcast on RV32 due to type legalization rewriting the
 ; build_vector to v8i32.
 ; FIXME: We should prevent this and use the implicit sign extension of vmv.v.x
 ; with SEW=64 on RV32.
 define void @splat_allones_with_use_v4i64(<4 x i64>* %x) {
-; LMULMAX8-RV32-LABEL: splat_allones_with_use_v4i64:
-; LMULMAX8-RV32:       # %bb.0:
-; LMULMAX8-RV32-NEXT:    vsetivli a1, 4, e64,m2,ta,mu
-; LMULMAX8-RV32-NEXT:    vle64.v v26, (a0)
-; LMULMAX8-RV32-NEXT:    vsetivli a1, 8, e32,m2,ta,mu
-; LMULMAX8-RV32-NEXT:    vmv.v.i v28, -1
-; LMULMAX8-RV32-NEXT:    vsetivli a1, 4, e64,m2,ta,mu
-; LMULMAX8-RV32-NEXT:    vadd.vv v26, v26, v28
-; LMULMAX8-RV32-NEXT:    vse64.v v26, (a0)
-; LMULMAX8-RV32-NEXT:    ret
+; LMULMAX8-LABEL: splat_allones_with_use_v4i64:
+; LMULMAX8:       # %bb.0:
+; LMULMAX8-NEXT:    vsetivli a1, 4, e64,m2,ta,mu
+; LMULMAX8-NEXT:    vle64.v v26, (a0)
+; LMULMAX8-NEXT:    vadd.vi v26, v26, -1
+; LMULMAX8-NEXT:    vse64.v v26, (a0)
+; LMULMAX8-NEXT:    ret
 ;
-; LMULMAX2-RV32-LABEL: splat_allones_with_use_v4i64:
-; LMULMAX2-RV32:       # %bb.0:
-; LMULMAX2-RV32-NEXT:    vsetivli a1, 4, e64,m2,ta,mu
-; LMULMAX2-RV32-NEXT:    vle64.v v26, (a0)
-; LMULMAX2-RV32-NEXT:    vsetivli a1, 8, e32,m2,ta,mu
-; LMULMAX2-RV32-NEXT:    vmv.v.i v28, -1
-; LMULMAX2-RV32-NEXT:    vsetivli a1, 4, e64,m2,ta,mu
-; LMULMAX2-RV32-NEXT:    vadd.vv v26, v26, v28
-; LMULMAX2-RV32-NEXT:    vse64.v v26, (a0)
-; LMULMAX2-RV32-NEXT:    ret
+; LMULMAX2-LABEL: splat_allones_with_use_v4i64:
+; LMULMAX2:       # %bb.0:
+; LMULMAX2-NEXT:    vsetivli a1, 4, e64,m2,ta,mu
+; LMULMAX2-NEXT:    vle64.v v26, (a0)
+; LMULMAX2-NEXT:    vadd.vi v26, v26, -1
+; LMULMAX2-NEXT:    vse64.v v26, (a0)
+; LMULMAX2-NEXT:    ret
 ;
 ; LMULMAX1-RV32-LABEL: splat_allones_with_use_v4i64:
 ; LMULMAX1-RV32:       # %bb.0:
 ; LMULMAX1-RV32-NEXT:    vsetivli a1, 2, e64,m1,ta,mu
 ; LMULMAX1-RV32-NEXT:    vle64.v v25, (a0)
 ; LMULMAX1-RV32-NEXT:    addi a1, a0, 16
 ; LMULMAX1-RV32-NEXT:    vle64.v v26, (a1)
 ; LMULMAX1-RV32-NEXT:    vsetivli a2, 4, e32,m1,ta,mu
 ; LMULMAX1-RV32-NEXT:    vmv.v.i v27, -1
 ; LMULMAX1-RV32-NEXT:    vsetivli a2, 2, e64,m1,ta,mu
 ; LMULMAX1-RV32-NEXT:    vadd.vv v26, v26, v27
 ; LMULMAX1-RV32-NEXT:    vadd.vv v25, v25, v27
 ; LMULMAX1-RV32-NEXT:    vse64.v v25, (a0)
 ; LMULMAX1-RV32-NEXT:    vse64.v v26, (a1)
 ; LMULMAX1-RV32-NEXT:    ret
 ;
-; LMULMAX8-RV64-LABEL: splat_allones_with_use_v4i64:
-; LMULMAX8-RV64:       # %bb.0:
-; LMULMAX8-RV64-NEXT:    vsetivli a1, 4, e64,m2,ta,mu
-; LMULMAX8-RV64-NEXT:    vle64.v v26, (a0)
-; LMULMAX8-RV64-NEXT:    vadd.vi v26, v26, -1
-; LMULMAX8-RV64-NEXT:    vse64.v v26, (a0)
-; LMULMAX8-RV64-NEXT:    ret
-;
-; LMULMAX2-RV64-LABEL: splat_allones_with_use_v4i64:
-; LMULMAX2-RV64:       # %bb.0:
-; LMULMAX2-RV64-NEXT:    vsetivli a1, 4, e64,m2,ta,mu
-; LMULMAX2-RV64-NEXT:    vle64.v v26, (a0)
-; LMULMAX2-RV64-NEXT:    vadd.vi v26, v26, -1
-; LMULMAX2-RV64-NEXT:    vse64.v v26, (a0)
-; LMULMAX2-RV64-NEXT:    ret
-;
 ; LMULMAX1-RV64-LABEL: splat_allones_with_use_v4i64:
 ; LMULMAX1-RV64:       # %bb.0:
 ; LMULMAX1-RV64-NEXT:    vsetivli a1, 2, e64,m1,ta,mu
 ; LMULMAX1-RV64-NEXT:    addi a1, a0, 16
 ; LMULMAX1-RV64-NEXT:    vle64.v v25, (a1)
 ; LMULMAX1-RV64-NEXT:    vle64.v v26, (a0)
 ; LMULMAX1-RV64-NEXT:    vadd.vi v25, v25, -1
 ; LMULMAX1-RV64-NEXT:    vadd.vi v26, v26, -1
 ; LMULMAX1-RV64-NEXT:    vse64.v v26, (a0)
 ; LMULMAX1-RV64-NEXT:    vse64.v v25, (a1)
 ; LMULMAX1-RV64-NEXT:    ret
   %a = load <4 x i64>, <4 x i64>* %x
   %b = add <4 x i64> %a, <i64 -1, i64 -1, i64 -1, i64 -1>
   store <4 x i64> %b, <4 x i64>* %x
   ret void
 }
 
 ; This test used to crash at LMUL=8 when inserting a v16i64 subvector into
 ; nxv8i64 at index 0: the v16i64 type was used to get the LMUL, the size of
 ; which exceeded maximum-expected size of 512. The scalable container type of
 ; nxv8i64 should have been used instead.
 define void @vadd_vx_v16i64(<16 x i64>* %a, i64 %b, <16 x i64>* %c) {
 ; LMULMAX8-RV32-LABEL: vadd_vx_v16i64:
 ; LMULMAX8-RV32:       # %bb.0:
+; LMULMAX8-RV32-NEXT:    addi sp, sp, -16
+; LMULMAX8-RV32-NEXT:    .cfi_def_cfa_offset 16
 ; LMULMAX8-RV32-NEXT:    vsetivli a4, 16, e64,m8,ta,mu
 ; LMULMAX8-RV32-NEXT:    vle64.v v8, (a0)
-; LMULMAX8-RV32-NEXT:    lui a0, 349525
-; LMULMAX8-RV32-NEXT:    addi a0, a0, 1365
-; LMULMAX8-RV32-NEXT:    vsetivli a4, 1, e32,m1,ta,mu
-; LMULMAX8-RV32-NEXT:    vmv.s.x v0, a0
-; LMULMAX8-RV32-NEXT:    addi a0, zero, 32
-; LMULMAX8-RV32-NEXT:    vsetvli a0, a0, e32,m8,ta,mu
-; LMULMAX8-RV32-NEXT:    vmv.v.x v16, a2
-; LMULMAX8-RV32-NEXT:    vmerge.vxm v16, v16, a1, v0
-; LMULMAX8-RV32-NEXT:    vsetivli a0, 16, e64,m8,ta,mu
+; LMULMAX8-RV32-NEXT:    sw a2, 12(sp)
+; LMULMAX8-RV32-NEXT:    sw a1, 8(sp)
+; LMULMAX8-RV32-NEXT:    addi a0, sp, 8
+; LMULMAX8-RV32-NEXT:    vlse64.v v16, (a0), zero
 ; LMULMAX8-RV32-NEXT:    vadd.vv v8, v8, v16
 ; LMULMAX8-RV32-NEXT:    vse64.v v8, (a3)
+; LMULMAX8-RV32-NEXT:    addi sp, sp, 16
 ; LMULMAX8-RV32-NEXT:    ret
 ;
 ; LMULMAX2-RV32-LABEL: vadd_vx_v16i64:
 ; LMULMAX2-RV32:       # %bb.0:
 ; LMULMAX2-RV32-NEXT:    addi a4, a0, 64
 ; LMULMAX2-RV32-NEXT:    vsetivli a5, 4, e64,m2,ta,mu
 ; LMULMAX2-RV32-NEXT:    vle64.v v26, (a4)
 ; LMULMAX2-RV32-NEXT:    addi a4, a0, 96

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-int.ll

; CHECK-NEXT:    ret
   %b = insertelement <4 x i32> undef, i32 -1, i32 0
   %c = shufflevector <4 x i32> %b, <4 x i32> undef, <4 x i32> zeroinitializer
   %d = add <4 x i32> %a, %c
   store <4 x i32> %d, <4 x i32>* %x
   ret void
 }
 
 define void @add_vi_v2i64(<2 x i64>* %x) {
-; RV32-LABEL: add_vi_v2i64:
-; RV32:       # %bb.0:
-; RV32-NEXT:    vsetivli a1, 2, e64,m1,ta,mu
-; RV32-NEXT:    vle64.v v25, (a0)
-; RV32-NEXT:    vsetivli a1, 4, e32,m1,ta,mu
-; RV32-NEXT:    vmv.v.i v26, -1
-; RV32-NEXT:    vsetivli a1, 2, e64,m1,ta,mu
-; RV32-NEXT:    vadd.vv v25, v25, v26
-; RV32-NEXT:    vse64.v v25, (a0)
-; RV32-NEXT:    ret
-;
-; RV64-LABEL: add_vi_v2i64:
-; RV64:       # %bb.0:
-; RV64-NEXT:    vsetivli a1, 2, e64,m1,ta,mu
-; RV64-NEXT:    vle64.v v25, (a0)
-; RV64-NEXT:    vadd.vi v25, v25, -1
-; RV64-NEXT:    vse64.v v25, (a0)
-; RV64-NEXT:    ret
+; CHECK-LABEL: add_vi_v2i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetivli a1, 2, e64,m1,ta,mu
+; CHECK-NEXT:    vle64.v v25, (a0)
+; CHECK-NEXT:    vadd.vi v25, v25, -1
+; CHECK-NEXT:    vse64.v v25, (a0)
+; CHECK-NEXT:    ret
   %a = load <2 x i64>, <2 x i64>* %x
   %b = insertelement <2 x i64> undef, i64 -1, i32 0
   %c = shufflevector <2 x i64> %b, <2 x i64> undef, <2 x i32> zeroinitializer
   %d = add <2 x i64> %a, %c
   store <2 x i64> %d, <2 x i64>* %x
   ret void
 }
 
; CHECK-NEXT:    ret
   %b = insertelement <4 x i32> undef, i32 -1, i32 0
   %c = shufflevector <4 x i32> %b, <4 x i32> undef, <4 x i32> zeroinitializer
   %d = sub <4 x i32> %a, %c
   store <4 x i32> %d, <4 x i32>* %x
   ret void
 }
 
 define void @sub_vi_v2i64(<2 x i64>* %x) {
-; RV32-LABEL: sub_vi_v2i64:
-; RV32:       # %bb.0:
-; RV32-NEXT:    vsetivli a1, 2, e64,m1,ta,mu
-; RV32-NEXT:    vle64.v v25, (a0)
-; RV32-NEXT:    vsetivli a1, 4, e32,m1,ta,mu
-; RV32-NEXT:    vmv.v.i v26, -1
-; RV32-NEXT:    vsetivli a1, 2, e64,m1,ta,mu
-; RV32-NEXT:    vsub.vv v25, v25, v26
-; RV32-NEXT:    vse64.v v25, (a0)
-; RV32-NEXT:    ret
-;
-; RV64-LABEL: sub_vi_v2i64:
-; RV64:       # %bb.0:
-; RV64-NEXT:    vsetivli a1, 2, e64,m1,ta,mu
-; RV64-NEXT:    vle64.v v25, (a0)
-; RV64-NEXT:    addi a1, zero, -1
-; RV64-NEXT:    vsub.vx v25, v25, a1
-; RV64-NEXT:    vse64.v v25, (a0)
-; RV64-NEXT:    ret
+; CHECK-LABEL: sub_vi_v2i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetivli a1, 2, e64,m1,ta,mu
+; CHECK-NEXT:    vle64.v v25, (a0)
+; CHECK-NEXT:    addi a1, zero, -1
+; CHECK-NEXT:    vsub.vx v25, v25, a1
+; CHECK-NEXT:    vse64.v v25, (a0)
+; CHECK-NEXT:    ret
   %a = load <2 x i64>, <2 x i64>* %x
   %b = insertelement <2 x i64> undef, i64 -1, i32 0
   %c = shufflevector <2 x i64> %b, <2 x i64> undef, <2 x i32> zeroinitializer
   %d = sub <2 x i64> %a, %c
   store <2 x i64> %d, <2 x i64>* %x
   ret void
 }
 
; CHECK-NEXT:    ret
   %b = insertelement <4 x i32> undef, i32 -1, i32 0
   %c = shufflevector <4 x i32> %b, <4 x i32> undef, <4 x i32> zeroinitializer
   %d = xor <4 x i32> %a, %c
   store <4 x i32> %d, <4 x i32>* %x
   ret void
 }
 
 define void @xor_vi_v2i64(<2 x i64>* %x) {
-; RV32-LABEL: xor_vi_v2i64:
-; RV32:       # %bb.0:
-; RV32-NEXT:    vsetivli a1, 2, e64,m1,ta,mu
-; RV32-NEXT:    vle64.v v25, (a0)
-; RV32-NEXT:    vsetivli a1, 4, e32,m1,ta,mu
-; RV32-NEXT:    vmv.v.i v26, -1
-; RV32-NEXT:    vsetivli a1, 2, e64,m1,ta,mu
-; RV32-NEXT:    vxor.vv v25, v25, v26
-; RV32-NEXT:    vse64.v v25, (a0)
-; RV32-NEXT:    ret
-;
-; RV64-LABEL: xor_vi_v2i64:
-; RV64:       # %bb.0:
-; RV64-NEXT:    vsetivli a1, 2, e64,m1,ta,mu
-; RV64-NEXT:    vle64.v v25, (a0)
-; RV64-NEXT:    vxor.vi v25, v25, -1
-; RV64-NEXT:    vse64.v v25, (a0)
-; RV64-NEXT:    ret
+; CHECK-LABEL: xor_vi_v2i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetivli a1, 2, e64,m1,ta,mu
+; CHECK-NEXT:    vle64.v v25, (a0)
+; CHECK-NEXT:    vxor.vi v25, v25, -1
+; CHECK-NEXT:    vse64.v v25, (a0)
+; CHECK-NEXT:    ret
   %a = load <2 x i64>, <2 x i64>* %x
   %b = insertelement <2 x i64> undef, i64 -1, i32 0
   %c = shufflevector <2 x i64> %b, <2 x i64> undef, <2 x i32> zeroinitializer
   %d = xor <2 x i64> %a, %c
   store <2 x i64> %d, <2 x i64>* %x
   ret void
 }
 
; RV64-NEXT:    ret
   %b = udiv <4 x i32> %a, <i32 5, i32 5, i32 5, i32 5>
   store <4 x i32> %b, <4 x i32>* %x
   ret void
 }
 
 define void @mulhu_vx_v2i64(<2 x i64>* %x) {
 ; RV32-LABEL: mulhu_vx_v2i64:
 ; RV32:       # %bb.0:
+; RV32-NEXT:    addi sp, sp, -16
+; RV32-NEXT:    .cfi_def_cfa_offset 16
 ; RV32-NEXT:    vsetivli a1, 2, e64,m1,ta,mu
 ; RV32-NEXT:    vle64.v v25, (a0)
-; RV32-NEXT:    addi a1, zero, 5
-; RV32-NEXT:    vsetivli a2, 1, e8,m1,ta,mu
-; RV32-NEXT:    vmv.s.x v0, a1
 ; RV32-NEXT:    lui a1, 699051
 ; RV32-NEXT:    addi a2, a1, -1366
-; RV32-NEXT:    vsetivli a3, 4, e32,m1,ta,mu
-; RV32-NEXT:    vmv.v.x v26, a2
+; RV32-NEXT:    sw a2, 12(sp)
 ; RV32-NEXT:    addi a1, a1, -1365
-; RV32-NEXT:    vmerge.vxm v26, v26, a1, v0
-; RV32-NEXT:    vsetivli a1, 2, e64,m1,ta,mu
+; RV32-NEXT:    sw a1, 8(sp)
+; RV32-NEXT:    addi a1, sp, 8
+; RV32-NEXT:    vlse64.v v26, (a1), zero
 ; RV32-NEXT:    vmulhu.vv v25, v25, v26
 ; RV32-NEXT:    vsrl.vi v25, v25, 1
 ; RV32-NEXT:    vse64.v v25, (a0)
+; RV32-NEXT:    addi sp, sp, 16
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: mulhu_vx_v2i64:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vsetivli a1, 2, e64,m1,ta,mu
 ; RV64-NEXT:    vle64.v v25, (a0)
 ; RV64-NEXT:    lui a1, 1026731
 ; RV64-NEXT:    addiw a1, a1, -1365
; RV64-NEXT:    ret
   %b = sdiv <4 x i32> %a, <i32 -5, i32 -5, i32 -5, i32 -5>
   store <4 x i32> %b, <4 x i32>* %x
   ret void
 }
 
 define void @mulhs_vx_v2i64(<2 x i64>* %x) {
 ; RV32-LABEL: mulhs_vx_v2i64:
 ; RV32:       # %bb.0:
+; RV32-NEXT:    addi sp, sp, -16
+; RV32-NEXT:    .cfi_def_cfa_offset 16
 ; RV32-NEXT:    vsetivli a1, 2, e64,m1,ta,mu
 ; RV32-NEXT:    vle64.v v25, (a0)
-; RV32-NEXT:    addi a1, zero, 5
-; RV32-NEXT:    vsetivli a2, 1, e8,m1,ta,mu
-; RV32-NEXT:    vmv.s.x v0, a1
 ; RV32-NEXT:    lui a1, 349525
 ; RV32-NEXT:    addi a2, a1, 1365
-; RV32-NEXT:    vsetivli a3, 4, e32,m1,ta,mu
-; RV32-NEXT:    vmv.v.x v26, a2
+; RV32-NEXT:    sw a2, 12(sp)
 ; RV32-NEXT:    addi a1, a1, 1366
-; RV32-NEXT:    vmerge.vxm v26, v26, a1, v0
-; RV32-NEXT:    vsetivli a1, 2, e64,m1,ta,mu
+; RV32-NEXT:    sw a1, 8(sp)
+; RV32-NEXT:    addi a1, sp, 8
+; RV32-NEXT:    vlse64.v v26, (a1), zero
 ; RV32-NEXT:    vmulh.vv v25, v25, v26
 ; RV32-NEXT:    addi a1, zero, 63
 ; RV32-NEXT:    vsrl.vx v26, v25, a1
 ; RV32-NEXT:    vadd.vv v25, v25, v26
 ; RV32-NEXT:    vse64.v v25, (a0)
+; RV32-NEXT:    addi sp, sp, 16
 ; RV32-NEXT:    ret
 ;
 ; RV64-LABEL: mulhs_vx_v2i64:
 ; RV64:       # %bb.0:
 ; RV64-NEXT:    vsetivli a1, 2, e64,m1,ta,mu
 ; RV64-NEXT:    vle64.v v25, (a0)
 ; RV64-NEXT:    lui a1, 21845
 ; RV64-NEXT:    addiw a1, a1, 1365

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-load-int.ll

; CHECK-NEXT:    ret
   %mask = icmp eq <1 x i32> %m, zeroinitializer
   %load = call <1 x i32> @llvm.masked.load.v1i32(<1 x i32>* %a, i32 8, <1 x i1> %mask, <1 x i32> undef)
   store <1 x i32> %load, <1 x i32>* %res_ptr
   ret void
 }
 declare <1 x i32> @llvm.masked.load.v1i32(<1 x i32>*, i32, <1 x i1>, <1 x i32>)
 
 define void @masked_load_v1i64(<1 x i64>* %a, <1 x i64>* %m_ptr, <1 x i64>* %res_ptr) nounwind {
-; RV32-LABEL: masked_load_v1i64:
-; RV32:       # %bb.0:
-; RV32-NEXT:    vsetivli a3, 1, e64,m1,ta,mu
-; RV32-NEXT:    vle64.v v25, (a1)
-; RV32-NEXT:    vsetivli a1, 2, e32,m1,ta,mu
-; RV32-NEXT:    vmv.v.i v26, 0
-; RV32-NEXT:    vsetivli a1, 1, e64,m1,ta,mu
-; RV32-NEXT:    vmseq.vv v0, v25, v26
-; RV32-NEXT:    vle64.v v25, (a0), v0.t
-; RV32-NEXT:    vse64.v v25, (a2)
-; RV32-NEXT:    ret
-;
-; RV64-LABEL: masked_load_v1i64:
-; RV64:       # %bb.0:
-; RV64-NEXT:    vsetivli a3, 1, e64,m1,ta,mu
-; RV64-NEXT:    vle64.v v25, (a1)
-; RV64-NEXT:    vmseq.vi v0, v25, 0
-; RV64-NEXT:    vle64.v v25, (a0), v0.t
-; RV64-NEXT:    vse64.v v25, (a2)
-; RV64-NEXT:    ret
+; CHECK-LABEL: masked_load_v1i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetivli a3, 1, e64,m1,ta,mu
+; CHECK-NEXT:    vle64.v v25, (a1)
+; CHECK-NEXT:    vmseq.vi v0, v25, 0
+; CHECK-NEXT:    vle64.v v25, (a0), v0.t
+; CHECK-NEXT:    vse64.v v25, (a2)
+; CHECK-NEXT:    ret
   %m = load <1 x i64>, <1 x i64>* %m_ptr
   %mask = icmp eq <1 x i64> %m, zeroinitializer
   %load = call <1 x i64> @llvm.masked.load.v1i64(<1 x i64>* %a, i32 8, <1 x i1> %mask, <1 x i64> undef)
   store <1 x i64> %load, <1 x i64>* %res_ptr
   ret void
 }
 declare <1 x i64> @llvm.masked.load.v1i64(<1 x i64>*, i32, <1 x i1>, <1 x i64>)
 
; CHECK-NEXT:    ret
   %mask = icmp eq <2 x i32> %m, zeroinitializer
   %load = call <2 x i32> @llvm.masked.load.v2i32(<2 x i32>* %a, i32 8, <2 x i1> %mask, <2 x i32> undef)
   store <2 x i32> %load, <2 x i32>* %res_ptr
   ret void
 }
 declare <2 x i32> @llvm.masked.load.v2i32(<2 x i32>*, i32, <2 x i1>, <2 x i32>)
 
 define void @masked_load_v2i64(<2 x i64>* %a, <2 x i64>* %m_ptr, <2 x i64>* %res_ptr) nounwind {
-; RV32-LABEL: masked_load_v2i64:
-; RV32:       # %bb.0:
-; RV32-NEXT:    vsetivli a3, 2, e64,m1,ta,mu
-; RV32-NEXT:    vle64.v v25, (a1)
-; RV32-NEXT:    vsetivli a1, 4, e32,m1,ta,mu
-; RV32-NEXT:    vmv.v.i v26, 0
-; RV32-NEXT:    vsetivli a1, 2, e64,m1,ta,mu
-; RV32-NEXT:    vmseq.vv v0, v25, v26
-; RV32-NEXT:    vle64.v v25, (a0), v0.t
-; RV32-NEXT:    vse64.v v25, (a2)
-; RV32-NEXT:    ret
-;
-; RV64-LABEL: masked_load_v2i64:
-; RV64:       # %bb.0:
-; RV64-NEXT:    vsetivli a3, 2, e64,m1,ta,mu
-; RV64-NEXT:    vle64.v v25, (a1)
-; RV64-NEXT:    vmseq.vi v0, v25, 0
-; RV64-NEXT:    vle64.v v25, (a0), v0.t
-; RV64-NEXT:    vse64.v v25, (a2)
-; RV64-NEXT:    ret
+; CHECK-LABEL: masked_load_v2i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetivli a3, 2, e64,m1,ta,mu
+; CHECK-NEXT:    vle64.v v25, (a1)
+; CHECK-NEXT:    vmseq.vi v0, v25, 0
+; CHECK-NEXT:    vle64.v v25, (a0), v0.t
+; CHECK-NEXT:    vse64.v v25, (a2)
+; CHECK-NEXT:    ret
   %m = load <2 x i64>, <2 x i64>* %m_ptr
   %mask = icmp eq <2 x i64> %m, zeroinitializer
   %load = call <2 x i64> @llvm.masked.load.v2i64(<2 x i64>* %a, i32 8, <2 x i1> %mask, <2 x i64> undef)
   store <2 x i64> %load, <2 x i64>* %res_ptr
   ret void
 }
 declare <2 x i64> @llvm.masked.load.v2i64(<2 x i64>*, i32, <2 x i1>, <2 x i64>)
 
; CHECK-NEXT:    ret
   %mask = icmp eq <4 x i32> %m, zeroinitializer
   %load = call <4 x i32> @llvm.masked.load.v4i32(<4 x i32>* %a, i32 8, <4 x i1> %mask, <4 x i32> undef)
   store <4 x i32> %load, <4 x i32>* %res_ptr
   ret void
 }
 declare <4 x i32> @llvm.masked.load.v4i32(<4 x i32>*, i32, <4 x i1>, <4 x i32>)
 
 define void @masked_load_v4i64(<4 x i64>* %a, <4 x i64>* %m_ptr, <4 x i64>* %res_ptr) nounwind {
-; RV32-LABEL: masked_load_v4i64:
-; RV32:       # %bb.0:
-; RV32-NEXT:    vsetivli a3, 4, e64,m2,ta,mu
-; RV32-NEXT:    vle64.v v26, (a1)
-; RV32-NEXT:    vsetivli a1, 8, e32,m2,ta,mu
-; RV32-NEXT:    vmv.v.i v28, 0
-; RV32-NEXT:    vsetivli a1, 4, e64,m2,ta,mu
-; RV32-NEXT:    vmseq.vv v0, v26, v28
-; RV32-NEXT:    vle64.v v26, (a0), v0.t
-; RV32-NEXT:    vse64.v v26, (a2)
-; RV32-NEXT:    ret
-;
-; RV64-LABEL: masked_load_v4i64:
-; RV64:       # %bb.0:
-; RV64-NEXT:    vsetivli a3, 4, e64,m2,ta,mu
-; RV64-NEXT:    vle64.v v26, (a1)
-; RV64-NEXT:    vmseq.vi v0, v26, 0
-; RV64-NEXT:    vle64.v v26, (a0), v0.t
-; RV64-NEXT:    vse64.v v26, (a2)
-; RV64-NEXT:    ret
+; CHECK-LABEL: masked_load_v4i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetivli a3, 4, e64,m2,ta,mu
+; CHECK-NEXT:    vle64.v v26, (a1)
+; CHECK-NEXT:    vmseq.vi v0, v26, 0
+; CHECK-NEXT:    vle64.v v26, (a0), v0.t
+; CHECK-NEXT:    vse64.v v26, (a2)
+; CHECK-NEXT:    ret
   %m = load <4 x i64>, <4 x i64>* %m_ptr
   %mask = icmp eq <4 x i64> %m, zeroinitializer
   %load = call <4 x i64> @llvm.masked.load.v4i64(<4 x i64>* %a, i32 8, <4 x i1> %mask, <4 x i64> undef)
   store <4 x i64> %load, <4 x i64>* %res_ptr
   ret void
 }
 declare <4 x i64> @llvm.masked.load.v4i64(<4 x i64>*, i32, <4 x i1>, <4 x i64>)
 
; CHECK-NEXT:    ret
   %mask = icmp eq <8 x i32> %m, zeroinitializer
   %load = call <8 x i32> @llvm.masked.load.v8i32(<8 x i32>* %a, i32 8, <8 x i1> %mask, <8 x i32> undef)
   store <8 x i32> %load, <8 x i32>* %res_ptr
   ret void
 }
 declare <8 x i32> @llvm.masked.load.v8i32(<8 x i32>*, i32, <8 x i1>, <8 x i32>)
 
 define void @masked_load_v8i64(<8 x i64>* %a, <8 x i64>* %m_ptr, <8 x i64>* %res_ptr) nounwind {
-; RV32-LABEL: masked_load_v8i64:
-; RV32:       # %bb.0:
-; RV32-NEXT:    vsetivli a3, 8, e64,m4,ta,mu
-; RV32-NEXT:    vle64.v v28, (a1)
-; RV32-NEXT:    vsetivli a1, 16, e32,m4,ta,mu
-; RV32-NEXT:    vmv.v.i v8, 0
-; RV32-NEXT:    vsetivli a1, 8, e64,m4,ta,mu
-; RV32-NEXT:    vmseq.vv v0, v28, v8
-; RV32-NEXT:    vle64.v v28, (a0), v0.t
-; RV32-NEXT:    vse64.v v28, (a2)
-; RV32-NEXT:    ret
-;
-; RV64-LABEL: masked_load_v8i64:
-; RV64:       # %bb.0:
-; RV64-NEXT:    vsetivli a3, 8, e64,m4,ta,mu
-; RV64-NEXT:    vle64.v v28, (a1)
-; RV64-NEXT:    vmseq.vi v0, v28, 0
-; RV64-NEXT:    vle64.v v28, (a0), v0.t
-; RV64-NEXT:    vse64.v v28, (a2)
-; RV64-NEXT:    ret
+; CHECK-LABEL: masked_load_v8i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetivli a3, 8, e64,m4,ta,mu
+; CHECK-NEXT:    vle64.v v28, (a1)
+; CHECK-NEXT:    vmseq.vi v0, v28, 0
+; CHECK-NEXT:    vle64.v v28, (a0), v0.t
+; CHECK-NEXT:    vse64.v v28, (a2)
+; CHECK-NEXT:    ret
   %m = load <8 x i64>, <8 x i64>* %m_ptr
   %mask = icmp eq <8 x i64> %m, zeroinitializer
   %load = call <8 x i64> @llvm.masked.load.v8i64(<8 x i64>* %a, i32 8, <8 x i1> %mask, <8 x i64> undef)
   store <8 x i64> %load, <8 x i64>* %res_ptr
   ret void
 }
 declare <8 x i64> @llvm.masked.load.v8i64(<8 x i64>*, i32, <8 x i1>, <8 x i64>)
 
; CHECK-NEXT:    ret
   %mask = icmp eq <16 x i32> %m, zeroinitializer
   %load = call <16 x i32> @llvm.masked.load.v16i32(<16 x i32>* %a, i32 8, <16 x i1> %mask, <16 x i32> undef)
   store <16 x i32> %load, <16 x i32>* %res_ptr
   ret void
 }
 declare <16 x i32> @llvm.masked.load.v16i32(<16 x i32>*, i32, <16 x i1>, <16 x i32>)
 
 define void @masked_load_v16i64(<16 x i64>* %a, <16 x i64>* %m_ptr, <16 x i64>* %res_ptr) nounwind {
-; RV32-LABEL: masked_load_v16i64:
-; RV32:       # %bb.0:
-; RV32-NEXT:    vsetivli a3, 16, e64,m8,ta,mu
-; RV32-NEXT:    vle64.v v8, (a1)
-; RV32-NEXT:    addi a1, zero, 32
-; RV32-NEXT:    vsetvli a1, a1, e32,m8,ta,mu
-; RV32-NEXT:    vmv.v.i v16, 0
-; RV32-NEXT:    vsetivli a1, 16, e64,m8,ta,mu
-; RV32-NEXT:    vmseq.vv v0, v8, v16
-; RV32-NEXT:    vle64.v v8, (a0), v0.t
-; RV32-NEXT:    vse64.v v8, (a2)
-; RV32-NEXT:    ret
-;
-; RV64-LABEL: masked_load_v16i64:
-; RV64:       # %bb.0:
-; RV64-NEXT:    vsetivli a3, 16, e64,m8,ta,mu
-; RV64-NEXT:    vle64.v v8, (a1)
-; RV64-NEXT:    vmseq.vi v0, v8, 0
-; RV64-NEXT:    vle64.v v8, (a0), v0.t
-; RV64-NEXT:    vse64.v v8, (a2)
-; RV64-NEXT:    ret
+; CHECK-LABEL: masked_load_v16i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetivli a3, 16, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a1)
+; CHECK-NEXT:    vmseq.vi v0, v8, 0
+; CHECK-NEXT:    vle64.v v8, (a0), v0.t
+; CHECK-NEXT:    vse64.v v8, (a2)
+; CHECK-NEXT:    ret
   %m = load <16 x i64>, <16 x i64>* %m_ptr
   %mask = icmp eq <16 x i64> %m, zeroinitializer
   %load = call <16 x i64> @llvm.masked.load.v16i64(<16 x i64>* %a, i32 8, <16 x i1> %mask, <16 x i64> undef)
   store <16 x i64> %load, <16 x i64>* %res_ptr
   ret void
 }
 declare <16 x i64> @llvm.masked.load.v16i64(<16 x i64>*, i32, <16 x i1>, <16 x i64>)
 

llvm/test/CodeGen/RISCV/rvv/fixed-vectors-masked-store-int.ll

; CHECK-NEXT:    ret
   %mask = icmp eq <1 x i32> %m, zeroinitializer
   %val = load <1 x i32>, <1 x i32>* %val_ptr
   call void @llvm.masked.store.v1i32.p0v1i32(<1 x i32> %val, <1 x i32>* %a, i32 8, <1 x i1> %mask)
   ret void
 }
 declare void @llvm.masked.store.v1i32.p0v1i32(<1 x i32>, <1 x i32>*, i32, <1 x i1>)
 
 define void @masked_store_v1i64(<1 x i64>* %val_ptr, <1 x i64>* %a, <1 x i64>* %m_ptr) nounwind {
-; RV32-LABEL: masked_store_v1i64:
-; RV32:       # %bb.0:
-; RV32-NEXT:    vsetivli a3, 1, e64,m1,ta,mu
-; RV32-NEXT:    vle64.v v25, (a2)
-; RV32-NEXT:    vsetivli a2, 2, e32,m1,ta,mu
-; RV32-NEXT:    vmv.v.i v26, 0
-; RV32-NEXT:    vsetivli a2, 1, e64,m1,ta,mu
-; RV32-NEXT:    vle64.v v27, (a0)
-; RV32-NEXT:    vmseq.vv v0, v25, v26
-; RV32-NEXT:    vse64.v v27, (a1), v0.t
-; RV32-NEXT:    ret
-;
-; RV64-LABEL: masked_store_v1i64:
-; RV64:       # %bb.0:
-; RV64-NEXT:    vsetivli a3, 1, e64,m1,ta,mu
-; RV64-NEXT:    vle64.v v25, (a2)
-; RV64-NEXT:    vle64.v v26, (a0)
-; RV64-NEXT:    vmseq.vi v0, v25, 0
-; RV64-NEXT:    vse64.v v26, (a1), v0.t
-; RV64-NEXT:    ret
+; CHECK-LABEL: masked_store_v1i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetivli a3, 1, e64,m1,ta,mu
+; CHECK-NEXT:    vle64.v v25, (a2)
+; CHECK-NEXT:    vle64.v v26, (a0)
+; CHECK-NEXT:    vmseq.vi v0, v25, 0
+; CHECK-NEXT:    vse64.v v26, (a1), v0.t
+; CHECK-NEXT:    ret
   %m = load <1 x i64>, <1 x i64>* %m_ptr
   %mask = icmp eq <1 x i64> %m, zeroinitializer
   %val = load <1 x i64>, <1 x i64>* %val_ptr
   call void @llvm.masked.store.v1i64.p0v1i64(<1 x i64> %val, <1 x i64>* %a, i32 8, <1 x i1> %mask)
   ret void
 }
 declare void @llvm.masked.store.v1i64.p0v1i64(<1 x i64>, <1 x i64>*, i32, <1 x i1>)
 
; CHECK-NEXT:    ret
   %mask = icmp eq <2 x i32> %m, zeroinitializer
   %val = load <2 x i32>, <2 x i32>* %val_ptr
   call void @llvm.masked.store.v2i32.p0v2i32(<2 x i32> %val, <2 x i32>* %a, i32 8, <2 x i1> %mask)
   ret void
 }
 declare void @llvm.masked.store.v2i32.p0v2i32(<2 x i32>, <2 x i32>*, i32, <2 x i1>)
 
 define void @masked_store_v2i64(<2 x i64>* %val_ptr, <2 x i64>* %a, <2 x i64>* %m_ptr) nounwind {
-; RV32-LABEL: masked_store_v2i64:
-; RV32:       # %bb.0:
-; RV32-NEXT:    vsetivli a3, 2, e64,m1,ta,mu
-; RV32-NEXT:    vle64.v v25, (a2)
-; RV32-NEXT:    vsetivli a2, 4, e32,m1,ta,mu
-; RV32-NEXT:    vmv.v.i v26, 0
-; RV32-NEXT:    vsetivli a2, 2, e64,m1,ta,mu
-; RV32-NEXT:    vle64.v v27, (a0)
-; RV32-NEXT:    vmseq.vv v0, v25, v26
-; RV32-NEXT:    vse64.v v27, (a1), v0.t
-; RV32-NEXT:    ret
-;
-; RV64-LABEL: masked_store_v2i64:
-; RV64:       # %bb.0:
-; RV64-NEXT:    vsetivli a3, 2, e64,m1,ta,mu
-; RV64-NEXT:    vle64.v v25, (a2)
-; RV64-NEXT:    vle64.v v26, (a0)
-; RV64-NEXT:    vmseq.vi v0, v25, 0
-; RV64-NEXT:    vse64.v v26, (a1), v0.t
-; RV64-NEXT:    ret
+; CHECK-LABEL: masked_store_v2i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetivli a3, 2, e64,m1,ta,mu
+; CHECK-NEXT:    vle64.v v25, (a2)
+; CHECK-NEXT:    vle64.v v26, (a0)
+; CHECK-NEXT:    vmseq.vi v0, v25, 0
+; CHECK-NEXT:    vse64.v v26, (a1), v0.t
+; CHECK-NEXT:    ret
   %m = load <2 x i64>, <2 x i64>* %m_ptr
   %mask = icmp eq <2 x i64> %m, zeroinitializer
   %val = load <2 x i64>, <2 x i64>* %val_ptr
   call void @llvm.masked.store.v2i64.p0v2i64(<2 x i64> %val, <2 x i64>* %a, i32 8, <2 x i1> %mask)
   ret void
 }
 declare void @llvm.masked.store.v2i64.p0v2i64(<2 x i64>, <2 x i64>*, i32, <2 x i1>)
 
; CHECK-NEXT:    ret
   %mask = icmp eq <4 x i32> %m, zeroinitializer
   %val = load <4 x i32>, <4 x i32>* %val_ptr
   call void @llvm.masked.store.v4i32.p0v4i32(<4 x i32> %val, <4 x i32>* %a, i32 8, <4 x i1> %mask)
   ret void
 }
 declare void @llvm.masked.store.v4i32.p0v4i32(<4 x i32>, <4 x i32>*, i32, <4 x i1>)
 
 define void @masked_store_v4i64(<4 x i64>* %val_ptr, <4 x i64>* %a, <4 x i64>* %m_ptr) nounwind {
-; RV32-LABEL: masked_store_v4i64:
-; RV32:       # %bb.0:
-; RV32-NEXT:    vsetivli a3, 4, e64,m2,ta,mu
-; RV32-NEXT:    vle64.v v26, (a2)
-; RV32-NEXT:    vsetivli a2, 8, e32,m2,ta,mu
-; RV32-NEXT:    vmv.v.i v28, 0
-; RV32-NEXT:    vsetivli a2, 4, e64,m2,ta,mu
-; RV32-NEXT:    vle64.v v30, (a0)
-; RV32-NEXT:    vmseq.vv v0, v26, v28
-; RV32-NEXT:    vse64.v v30, (a1), v0.t
-; RV32-NEXT:    ret
-;
-; RV64-LABEL: masked_store_v4i64:
-; RV64:       # %bb.0:
-; RV64-NEXT:    vsetivli a3, 4, e64,m2,ta,mu
-; RV64-NEXT:    vle64.v v26, (a2)
-; RV64-NEXT:    vle64.v v28, (a0)
-; RV64-NEXT:    vmseq.vi v0, v26, 0
-; RV64-NEXT:    vse64.v v28, (a1), v0.t
-; RV64-NEXT:    ret
+; CHECK-LABEL: masked_store_v4i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetivli a3, 4, e64,m2,ta,mu
+; CHECK-NEXT:    vle64.v v26, (a2)
+; CHECK-NEXT:    vle64.v v28, (a0)
+; CHECK-NEXT:    vmseq.vi v0, v26, 0
+; CHECK-NEXT:    vse64.v v28, (a1), v0.t
+; CHECK-NEXT:    ret
   %m = load <4 x i64>, <4 x i64>* %m_ptr
   %mask = icmp eq <4 x i64> %m, zeroinitializer
   %val = load <4 x i64>, <4 x i64>* %val_ptr
   call void @llvm.masked.store.v4i64.p0v4i64(<4 x i64> %val, <4 x i64>* %a, i32 8, <4 x i1> %mask)
   ret void
 }
 declare void @llvm.masked.store.v4i64.p0v4i64(<4 x i64>, <4 x i64>*, i32, <4 x i1>)
 
; CHECK-NEXT:    ret
   %mask = icmp eq <8 x i32> %m, zeroinitializer
   %val = load <8 x i32>, <8 x i32>* %val_ptr
   call void @llvm.masked.store.v8i32.p0v8i32(<8 x i32> %val, <8 x i32>* %a, i32 8, <8 x i1> %mask)
   ret void
 }
 declare void @llvm.masked.store.v8i32.p0v8i32(<8 x i32>, <8 x i32>*, i32, <8 x i1>)
 
 define void @masked_store_v8i64(<8 x i64>* %val_ptr, <8 x i64>* %a, <8 x i64>* %m_ptr) nounwind {
-; RV32-LABEL: masked_store_v8i64:
-; RV32:       # %bb.0:
-; RV32-NEXT:    vsetivli a3, 8, e64,m4,ta,mu
-; RV32-NEXT:    vle64.v v28, (a2)
-; RV32-NEXT:    vsetivli a2, 16, e32,m4,ta,mu
-; RV32-NEXT:    vmv.v.i v8, 0
-; RV32-NEXT:    vsetivli a2, 8, e64,m4,ta,mu
-; RV32-NEXT:    vle64.v v12, (a0)
-; RV32-NEXT:    vmseq.vv v0, v28, v8
-; RV32-NEXT:    vse64.v v12, (a1), v0.t
-; RV32-NEXT:    ret
-;
-; RV64-LABEL: masked_store_v8i64:
-; RV64:       # %bb.0:
-; RV64-NEXT:    vsetivli a3, 8, e64,m4,ta,mu
-; RV64-NEXT:    vle64.v v28, (a2)
-; RV64-NEXT:    vle64.v v8, (a0)
-; RV64-NEXT:    vmseq.vi v0, v28, 0
-; RV64-NEXT:    vse64.v v8, (a1), v0.t
-; RV64-NEXT:    ret
+; CHECK-LABEL: masked_store_v8i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetivli a3, 8, e64,m4,ta,mu
+; CHECK-NEXT:    vle64.v v28, (a2)
+; CHECK-NEXT:    vle64.v v8, (a0)
+; CHECK-NEXT:    vmseq.vi v0, v28, 0
+; CHECK-NEXT:    vse64.v v8, (a1), v0.t
+; CHECK-NEXT:    ret
   %m = load <8 x i64>, <8 x i64>* %m_ptr
   %mask = icmp eq <8 x i64> %m, zeroinitializer
   %val = load <8 x i64>, <8 x i64>* %val_ptr
   call void @llvm.masked.store.v8i64.p0v8i64(<8 x i64> %val, <8 x i64>* %a, i32 8, <8 x i1> %mask)
   ret void
 }
 declare void @llvm.masked.store.v8i64.p0v8i64(<8 x i64>, <8 x i64>*, i32, <8 x i1>)
 
; CHECK-NEXT:    ret
   %mask = icmp eq <16 x i32> %m, zeroinitializer
   %val = load <16 x i32>, <16 x i32>* %val_ptr
   call void @llvm.masked.store.v16i32.p0v16i32(<16 x i32> %val, <16 x i32>* %a, i32 8, <16 x i1> %mask)
   ret void
 }
 declare void @llvm.masked.store.v16i32.p0v16i32(<16 x i32>, <16 x i32>*, i32, <16 x i1>)
 
 define void @masked_store_v16i64(<16 x i64>* %val_ptr, <16 x i64>* %a, <16 x i64>* %m_ptr) nounwind {
-; RV32-LABEL: masked_store_v16i64:
-; RV32:       # %bb.0:
-; RV32-NEXT:    vsetivli a3, 16, e64,m8,ta,mu
-; RV32-NEXT:    vle64.v v8, (a2)
-; RV32-NEXT:    addi a2, zero, 32
-; RV32-NEXT:    vsetvli a2, a2, e32,m8,ta,mu
-; RV32-NEXT:    vmv.v.i v16, 0
-; RV32-NEXT:    vsetivli a2, 16, e64,m8,ta,mu
-; RV32-NEXT:    vle64.v v24, (a0)
-; RV32-NEXT:    vmseq.vv v0, v8, v16
-; RV32-NEXT:    vse64.v v24, (a1), v0.t
-; RV32-NEXT:    ret
-;
-; RV64-LABEL: masked_store_v16i64:
-; RV64:       # %bb.0:
-; RV64-NEXT:    vsetivli a3, 16, e64,m8,ta,mu
-; RV64-NEXT:    vle64.v v8, (a2)
-; RV64-NEXT:    vle64.v v16, (a0)
-; RV64-NEXT:    vmseq.vi v0, v8, 0
-; RV64-NEXT:    vse64.v v16, (a1), v0.t
-; RV64-NEXT:    ret
+; CHECK-LABEL: masked_store_v16i64:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    vsetivli a3, 16, e64,m8,ta,mu
+; CHECK-NEXT:    vle64.v v8, (a2)
+; CHECK-NEXT:    vle64.v v16, (a0)
+; CHECK-NEXT:    vmseq.vi v0, v8, 0
+; CHECK-NEXT:    vse64.v v16, (a1), v0.t
+; CHECK-NEXT:    ret
   %m = load <16 x i64>, <16 x i64>* %m_ptr
   %mask = icmp eq <16 x i64> %m, zeroinitializer
   %val = load <16 x i64>, <16 x i64>* %val_ptr
   call void @llvm.masked.store.v16i64.p0v16i64(<16 x i64> %val, <16 x i64>* %a, i32 8, <16 x i1> %mask)
   ret void
 }
 declare void @llvm.masked.store.v16i64.p0v16i64(<16 x i64>, <16 x i64>*, i32, <16 x i1>)