[AsmPrinter] Add per BB instruction mix remark.

[fhahn]

Summary

This patch adds a remarks that provides counts for each opcode per basic block.

An snippet of the generated information can be seen below.

The current implementation uses the target specific opcode for the counts. For example, on AArch64 this means we currently get 2 entries for add instructions if the block contains 32 and 64 bit adds. Similarly, immediate version are treated differently.

Unfortunately there seems to be no convenient way to get only the mnemonic part of the instruction as a string AFAIK. This could be improved in the future.

--- !Analysis
Pass:            asm-printer
Name:            InstructionMix
DebugLoc:        { File: arm64-instruction-mix-remarks.ll, Line: 30, Column: 30 }
Function:        foo
Args:
  - String:          'BasicBlock: '
  - BasicBlock:      else
  - String:          "\n"
  - String:          INST_MADDWrrr
  - String:          ': '
  - INST_MADDWrrr:   '2'
  - String:          "\n"
  - String:          INST_MOVZWi
  - String:          ': '
  - INST_MOVZWi:     '1'

[fhahn]

Sort entries by count and name.

[fhahn]

If there's a convenient way to get only the mnemonic part of the opcode name, that would be really helpful to know :)

[anemet]

LGTM, you may want to wait a little for other potential comments. Especially some ideas on getting the actual mnemonic.

[paquette]

llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp

1208

Will this work with inline assembly? Looks like inline assembly is handled earlier in the switch.

(Probably fine to support it later anyway.)

1258

MBB.empty()?

1268

Is there any reason that you're prefixing these with INST_? Are you planning on adding other ways to categorise these?

[paquette]

For the mnemonics, it looks like the logic to get at them is currently table-generated into build/lib/Target/MyTarget/MyTargetGenAsmWriter.inc.

I suppose you could factor out the logic for mnemonic printing in utils/TableGen/AsmWriterEmitter.cpp into something that can also be used here? Not sure if there is any better way than that...

[thegameg]

This looks great! Thanks!

If this evolves into something bigger (e.g. per-loop instruction mix remarks, instruction mix in assembly comments, etc.) it may be useful to have it around as an analysis.

llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp

1125

Looks like we can have loop info around here too, maybe a nice future extension would be to emit a remark with the instruction mix per loop too.

[anemet]

How about adding a total count as well? That should help quickly eye ball the ratios.

[thegameg]

In D89892#2349184, @anemet wrote:

How about adding a total count as well? That should help quickly eye ball the ratios.

Wouldn't that overlap with the InstructionCount remark?

[fhahn]

Thanks for all the comments. Updated to use MBB.empty().

In D89892#2349185, @thegameg wrote:

In D89892#2349184, @anemet wrote:

How about adding a total count as well? That should help quickly eye ball the ratios.

Wouldn't that overlap with the InstructionCount remark?

I think so. Or do you mean per instruction counts for the whole function? That could also be done by post-processing I think.

[fhahn]

llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp

1125

Sounds like a useful extension in the future indeed!

1208

Hmm, I am not sure we can really do much about inline assembly in general. Isn't that just a opaque string passed through?

1268

The prefix is intended to make it easier for tool to post-process the information to disambiguate the counts from other info (like the BB). But at the moment it is not really necessary and mostly for convenience. For now I am not planning on adding other ways to categorize the instruction counts. That seems tricky to do here in a target-independent way unfortunately.

[fhahn]

In D89892#2345866, @paquette wrote:

For the mnemonics, it looks like the logic to get at them is currently table-generated into build/lib/Target/MyTarget/MyTargetGenAsmWriter.inc.

I suppose you could factor out the logic for mnemonic printing in utils/TableGen/AsmWriterEmitter.cpp into something that can also be used here? Not sure if there is any better way than that...

I tried to do that as follow up in D90039 & D90040. Seems to work reasonably well, although it seems like it misses the conditional codes for branches.

[paquette]

LGTM!

The follow-up changes look really nice too.

llvm/lib/CodeGen/AsmPrinter/AsmPrinter.cpp

if (isVerbose()) {
     MDT = getAnalysisIfAvailable<MachineDominatorTree>();
     if (!MDT) {
       OwnedMDT = std::make_unique<MachineDominatorTree>();
       OwnedMDT->getBase().recalculate(*MF);
       MDT = OwnedMDT.get();
     }
 
     // Get MachineLoopInfo or compute it on the fly if it's unavailable
     MLI = getAnalysisIfAvailable<MachineLoopInfo>();
     if (!MLI) {
       OwnedMLI = std::make_unique<MachineLoopInfo>();
       OwnedMLI->getBase().analyze(MDT->getBase());
       MLI = OwnedMLI.get();
     }
   }
 
   // Print out code for the function.
   bool HasAnyRealCode = false;
   int NumInstsInFunction = 0;
 
+  bool CanDoExtraAnalysis = ORE->allowExtraAnalysis(DEBUG_TYPE);
+  const TargetInstrInfo *TII = MF->getSubtarget().getInstrInfo();
   for (auto &MBB : *MF) {
     // Print a label for the basic block.
     emitBasicBlockStart(MBB);
+    DenseMap<unsigned, unsigned> OpcodeCounts;
     for (auto &MI : MBB) {
       // Print the assembly for the instruction.
       if (!MI.isPosition() && !MI.isImplicitDef() && !MI.isKill() &&
           !MI.isDebugInstr()) {
         HasAnyRealCode = true;
         ++NumInstsInFunction;
       }
 
for (auto &MI : MBB) {
       case TargetOpcode::IMPLICIT_DEF:
         if (isVerbose()) emitImplicitDef(&MI);
         break;
       case TargetOpcode::KILL:
         if (isVerbose()) emitKill(&MI, *this);
         break;
       default:
         emitInstruction(&MI);
+        if (CanDoExtraAnalysis) {
+          auto I = OpcodeCounts.insert({MI.getOpcode(), 0u});
+          I.first->second++;
+        }
         break;
       }
 
       // If there is a post-instruction symbol, emit a label for it here.
       if (MCSymbol *S = MI.getPostInstrSymbol())
         OutStreamer->emitLabel(S);
 
       if (ShouldPrintDebugScopes) {
if (MBB.isEndSection()) {
               OutContext);
           OutStreamer->emitELFSize(CurrentSectionBeginSym, SizeExp);
         }
         MBBSectionRanges[MBB.getSectionIDNum()] =
             MBBSectionRange{CurrentSectionBeginSym, MBB.getEndSymbol()};
       }
     }
     emitBasicBlockEnd(MBB);
+
+    if (CanDoExtraAnalysis) {
+      // Skip empty blocks.
+      if (MBB.begin() == MBB.end())
+        continue;
+
+      MachineOptimizationRemarkAnalysis R(DEBUG_TYPE, "InstructionMix",
+                                          MBB.begin()->getDebugLoc(), &MBB);
+
+      // Generate instruction mix remark. First, convert opcodes to string
+      // names, then sort them in descending order by count and name.
+      SmallVector<std::pair<std::string, unsigned>, 128> OpcodeCountsVec;
+      for (auto &KV : OpcodeCounts) {
+        auto Name = (Twine("INST_") + TII->getName(KV.first)).str();
+        OpcodeCountsVec.emplace_back(Name, KV.second);
+      }
+      sort(OpcodeCountsVec, [](const std::pair<std::string, unsigned> &A,
+                               const std::pair<std::string, unsigned> &B) {
+        if (A.second > B.second)
+          return true;
+        if (A.second == B.second)
+          return A.first < B.first;
+        return false;
+      });
+      R << "BasicBlock: " << ore::NV("BasicBlock", MBB.getName()) << "\n";
+      for (auto &KV : OpcodeCountsVec)
+        R << KV.first << ": " << ore::NV(KV.first, KV.second) << "\n";
+      ORE->emit(R);
+    }
   }
 
   EmittedInsts += NumInstsInFunction;
   MachineOptimizationRemarkAnalysis R(DEBUG_TYPE, "InstructionCount",
                                       MF->getFunction().getSubprogram(),
                                       &MF->front());
   R << ore::NV("NumInstructions", NumInstsInFunction)
     << " instructions in function";

llvm/test/CodeGen/AArch64/arm64-instruction-mix-remarks.ll

+; RUN: llc -mtriple=arm64-apple-ios7.0 -pass-remarks-output=%t -pass-remarks=asm-printer -o - %s | FileCheck %s
+; RUN: FileCheck --input-file=%t --check-prefix=YAML %s
+
+; CHECK-LABEL: %entry
+; CHECK-NEXT:   ldr w8, [x0]
+; CHECK-NEXT:   add w8, w8, w1
+; CHECK-NEXT:   cmp w8, #100
+; CHECK-NEXT:   b.ne    LBB0_2
+
+; YAML:      Name:            InstructionMix
+; YAML-NEXT: DebugLoc:        { File: arm64-instruction-mix-remarks.ll, Line: 10, Column: 10 }
+; YAML-NEXT: Function:        foo
+; YAML-NEXT: Args:
+; YAML:      - BasicBlock:      entry
+; YAML:      - INST_ADDWrs:     '1'
+; YAML:      - INST_Bcc:        '1'
+; YAML:      - INST_LDRWui:     '1'
+; YAML:      - INST_SUBSWri:    '1'
+
+
+; CHECK-LABEL: %then
+; CHECK-NEXT:    mov w0, w8
+; CHECK-NEXT:    ret
+
+; YAML:      Name:            InstructionMix
+; YAML-NEXT: DebugLoc:        { File: arm64-instruction-mix-remarks.ll, Line: 20, Column: 20 }
+; YAML-NEXT: Function:        foo
+; YAML-NEXT: Args:
+; YAML:        - BasicBlock:      then
+; YAML:        - INST_ORRWrs:     '1'
+; YAML:        - INST_RET:        '1'
+
+; CHECK-LABEL: %else
+; CHECK-NEXT:    mul w8, w8, w1
+; CHECK-NEXT:    mov w9, #10
+; CHECK-NEXT:    mul w8, w8, w1
+; CHECK-NEXT:    str w9, [x0]
+; CHECK-NEXT:    mov w0, w8
+; CHECK-NEXT:    ret
+
+; YAML:      Name:            InstructionMix
+; YAML-NEXT: DebugLoc:        { File: arm64-instruction-mix-remarks.ll, Line: 30, Column: 30 }
+; YAML-NEXT: Function:        foo
+; YAML-NEXT: Args:
+; YAML:       - BasicBlock:      else
+; YAML:       - INST_MADDWrrr:   '2'
+; YAML:       - INST_ORRWrs:     '1'
+; YAML:       - INST_RET:        '1'
+; YAML:       - INST_STRWui:     '1'
+define i32 @foo(i32* %ptr, i32 %x) !dbg !3 {
+entry:
+  %l = load i32, i32* %ptr, !dbg !4
+  %add = add i32 %l, %x, !dbg !4
+  %c = icmp eq i32 %add, 100, !dbg !4
+  br i1 %c, label %then, label %else, !dbg !4
+
+then:
+  ret i32 %add, !dbg !5
+
+else:
+  store i32 10, i32* %ptr, !dbg !6
+  %res = mul i32 %add, %x, !dbg !6
+  %res.2 = mul i32 %res, %x, !dbg !6
+  ret i32 %res.2, !dbg !6
+}
+!llvm.dbg.cu = !{!0}
+!llvm.module.flags = !{!2}
+
+!0 = distinct !DICompileUnit(language: DW_LANG_C, file: !1)
+!1 = !DIFile(filename: "arm64-instruction-mix-remarks.ll", directory: "")
+!2 = !{i32 2, !"Debug Info Version", i32 3}
+!3 = distinct !DISubprogram(name: "foo", scope: !1, file: !1, line: 5, scopeLine: 5, unit: !0)
+!4 = distinct !DILocation(line: 10, column: 10, scope: !3)
+!5 = distinct !DILocation(line: 20, column: 20, scope: !3)
+!6 = distinct !DILocation(line: 30, column: 30, scope: !3)