[TargetLowering] Combine known bits for icmp in SimplifySetCC (PR41182)

[RKSimon]

Summary

Fold integer comparisons where the known bits of the operands allows the result to be constant folded.

[darcangelo.matthew]

Removed the Signed argument from getMinValue

[lebedev.ri]

You need to upload the diff between the master branch and your branch, not the last commit in your branch.

[darcangelo.matthew]

Removed mistaken Signed argument

[nikic]

What is the motivation for this patch? The added tests should already get folded before reaching the backend (by InstCombine). We should only add folds to DAGCombine if the folded pattern is created by legalization. What is the original context for this change?

[darcangelo.matthew]

In D86578#2239392, @nikic wrote:

What is the motivation for this patch? The added tests should already get folded before reaching the backend (by InstCombine). We should only add folds to DAGCombine if the folded pattern is created by legalization. What is the original context for this change?

This was an unassigned enhancement - https://bugs.llvm.org/show_bug.cgi?id=41182 - that I was interested in and wanted to have a go at. Unfortunately that's all I have for context on my end

[craig.topper]

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

14059 ↗

(On Diff #288003)

I'm not sure if we can really do this from SelectionDAG. Is there anywhere else that does this in tree?

llvm/test/CodeGen/X86/test-shrink.ll

574 ↗

(On Diff #288003)

Can we pre-commit the IR changes here?

[darcangelo.matthew]

@RKSimon Meant to say this before - Thank you for putting up additional reviewers Simon, I appreciate your help with this

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

14059 ↗

(On Diff #288003)

I'm not sure if we can really do this from SelectionDAG. Is there anywhere else that does this in tree?

I found the UnreachableMachineBlockElim pass which may be able to be enhanced for this, but I'm still looking

llvm/test/CodeGen/X86/test-shrink.ll

574 ↗

(On Diff #288003)

Thank you for taking a look at the changes.

Can we pre-commit the IR changes here?

Sorry, would you be able to elaborate what you mean here? Do you mean separate these out into another pre-commit review?

[craig.topper]

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

14059 ↗

(On Diff #288003)

Sorry, I meant is there anywhere else that does something like this while SelectionDAG exists?

llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp

4237–4238

Is this just a formatting change?

llvm/test/CodeGen/X86/test-shrink.ll

574 ↗

(On Diff #288003)

I went ahead and modified the tests in trunk. Can you rebase this patch?

[darcangelo.matthew]

llvm/lib/CodeGen/SelectionDAG/DAGCombiner.cpp

14059 ↗

(On Diff #288003)

Thanks for elaborating, sorry for the confusion. I don't believe there is another place that does something like this while SelectionDAG exists. It seems like BranchFolding might be a good place for me to handle this?

For some additional context, without this change if we have

define i32 @simple(i32 %x) nounwind {
  %1 = and i32 %x, 2147483648
  %2 = icmp sle i32 %1, 0
  br i1 %2, label %yes, label %no

yes:                    ; will always get here
  ret i32 1
no:
  ret i32 2
}

we get

## %bb.0:
         xorl %eax, %eax
         testb %al, %al
	 jne	LBB0_2
## %bb.1:                               ## %yes
	movl	$1, %eax
	retq
LBB0_2:                                 ## %no
	movl	$2, %eax
	retq

so jne will never be taken instead of just removing the branch completely

llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp

4237–4238

Yes this is just formatting, I must have messed up the merge when I rebased and missed this. Sorry about that, should be fixed now

llvm/test/CodeGen/X86/test-shrink.ll

574 ↗

(On Diff #288003)

I went ahead and modified the tests in trunk. Can you rebase this patch?

Sure can, thanks for updating them. Sorry for the confusion

[darcangelo.matthew]

rebase

[RKSimon]

@darcangelo.matthew are you still looking at this?

llvm/include/llvm/Support/KnownBits.h

145 ↗

(On Diff #288883)

Please add unit test coverage in llvm\unittests\Support\KnownBitsTest.cpp

[RKSimon]

@darcangelo.matthew Are you in a position to continue with this, if not I would like to commandeer and complete this please?

[darcangelo.matthew]

In D86578#3243273, @RKSimon wrote:

@darcangelo.matthew Are you in a position to continue with this, if not I would like to commandeer and complete this please?

I’m not able to continue with this. You can go ahead and complete it. Sorry I missed your previous comment as well.

[RKSimon]

Updated the old patch to use the KnownBits comparison helpers that have been added since the original patch was created and add all test changes for review.

I've removed the branch removal code for now - which means we have a number of "constant" conditional branches that we currently have no way to fold to a jump, whatever we go for here handling this in the DAG would be rather ugly.

I'm open to suggestions for any individual test changes - some are definite improvements, some just need some tweaking and others probably affect the original regression the test was reduced from.

[RKSimon]

llvm/test/CodeGen/AMDGPU/wave32.ll

720 ↗

(On Diff #400593)

@foad I guess there's no good way around this if on wave32 targets - unless we duplicate the test with a 16 divergent variant?

llvm/test/CodeGen/X86/avx512-mask-op.ll

623

test7 (and test6) don't look great (and the codegen was already redundant) - I wonder if we should at least have them return something?

[foad]

llvm/test/CodeGen/AMDGPU/wave32.ll

720 ↗

(On Diff #400593)

Let's just replace the "cmp uge 32" with "cmp uge 16", and then your patch won't affect this test at all. (@critson is that OK?) Would you like me to do that in a separate commit?

[RKSimon]

llvm/test/CodeGen/AMDGPU/wave32.ll

720 ↗

(On Diff #400593)

Not sure if the commit question was to me or @critson - but if you can alter the test and then ping this ticket I will rebase the patch.

[critson]

llvm/test/CodeGen/AMDGPU/wave32.ll

720 ↗

(On Diff #400593)

@foad your suggested test change seems fine to me

[foad]

llvm/test/CodeGen/AMDGPU/wave32.ll

720 ↗

(On Diff #400593)

OK, please rebase on 7af959673e67256c5ba711070aca509dce794350.

[RKSimon]

llvm/test/CodeGen/AMDGPU/wave32.ll

720 ↗

(On Diff #400593)

Thanks - looks like we have an equivalent issue in wqm.ll

[RKSimon]

rebase

[xbolva00]

llvm/test/CodeGen/X86/fold-rmw-ops.ll

1830

Regression?

[RKSimon]

llvm/test/CodeGen/X86/fold-rmw-ops.ll

1830

I'm really at a loss as to what is best to do for these cases where we've created a constant conditional branch - the middle-end would have nuked most of these cases already (which probably means doing something in CGP is a waste of time as well) and I'm not certain how often they will be generated in backend.

We can tweak the tests in some cases I suppose, which is a cheat but probably the most realistic approach.

Opinions welcome!

[foad]

llvm/test/CodeGen/AMDGPU/wave32.ll

720 ↗

(On Diff #400593)

Fixed in 0bc14a0a989fe4268b899100aafc07e3d94decbb.

[RKSimon]

rebase

[RKSimon]

rebase

[nikic]

To repeat my previous question, because it's not obvious from tests: Which legalizations does this improve? That is, for input IR that has already gone through the opt -O2 pipeline, which cases does this improve?

[RKSimon]

In D86578#3264329, @nikic wrote:

To repeat my previous question, because it's not obvious from tests: Which legalizations does this improve? That is, for input IR that has already gone through the opt -O2 pipeline, which cases does this improve?

Its quite a long time ago when I first encountered this but IIRC one of the places I hit this was in the sdiv/udiv by constant expansions

[lebedev.ri]

This review may be stuck/dead, consider abandoning if no longer relevant.
Removing myself as reviewer in attempt to clean dashboard.

[foad]

llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp

3644–3646

Just put Result = KnownBits::whatever(LHSKnown, RHSKnown) inside the switch, and sink the if (Result) return ... out?

[RKSimon]

Abandoning as @goldstein.w.n has taken on something similar with D149383

llvm/lib/CodeGen/SelectionDAG/TargetLowering.cpp

SDValue TargetLowering::SimplifySetCC(EVT VT, SDValue N0, SDValue N1,
   // instruction on some targets.
   if (!isConstOrConstSplat(N0) && !isConstOrConstSplat(N1) &&
       (DCI.isBeforeLegalizeOps() ||
        isCondCodeLegal(SwappedCC, N0.getSimpleValueType())) &&
       DAG.doesNodeExist(ISD::SUB, DAG.getVTList(OpVT), {N1, N0}) &&
       !DAG.doesNodeExist(ISD::SUB, DAG.getVTList(OpVT), {N0, N1}))
     return DAG.getSetCC(dl, VT, N1, N0, SwappedCC);
 
+  // Use the known bits of the operands to see if the integer comparison is
+  // guaranteed to be true or false, and replace the setcc with the respective
+  // bool constant.
+  if (OpVT.isInteger()) {
+    KnownBits LHSKnown = DAG.computeKnownBits(N0);
+    KnownBits RHSKnown = DAG.computeKnownBits(N1);
+
+    switch (Cond) {
+    default:
+      llvm_unreachable("Unknown integer setcc!");
+    case ISD::SETEQ:
+      if (Optional<bool> IsEQ = KnownBits::eq(LHSKnown, RHSKnown))
+        return DAG.getBoolConstant(IsEQ.getValue(), dl, VT, OpVT);
+      break;
+    case ISD::SETNE:
+      if (Optional<bool> IsNE = KnownBits::ne(LHSKnown, RHSKnown))
+        return DAG.getBoolConstant(IsNE.getValue(), dl, VT, OpVT);
+      break;
+    case ISD::SETGT:
+      if (Optional<bool> IsSGT = KnownBits::sgt(LHSKnown, RHSKnown))
+        return DAG.getBoolConstant(IsSGT.getValue(), dl, VT, OpVT);
+      break;
+    case ISD::SETGE:
+      if (Optional<bool> IsSGE = KnownBits::sge(LHSKnown, RHSKnown))
+        return DAG.getBoolConstant(IsSGE.getValue(), dl, VT, OpVT);
+      break;
+    case ISD::SETLT:
+      if (Optional<bool> IsSLT = KnownBits::slt(LHSKnown, RHSKnown))
+        return DAG.getBoolConstant(IsSLT.getValue(), dl, VT, OpVT);
+      break;
+    case ISD::SETLE:
+      if (Optional<bool> IsSLE = KnownBits::sle(LHSKnown, RHSKnown))
+        return DAG.getBoolConstant(IsSLE.getValue(), dl, VT, OpVT);
+      break;
+    case ISD::SETUGT:
+      if (Optional<bool> IsUGT = KnownBits::ugt(LHSKnown, RHSKnown))
+        return DAG.getBoolConstant(IsUGT.getValue(), dl, VT, OpVT);
+      break;
+    case ISD::SETUGE:
+      if (Optional<bool> IsUGE = KnownBits::uge(LHSKnown, RHSKnown))
+        return DAG.getBoolConstant(IsUGE.getValue(), dl, VT, OpVT);
+      break;
+    case ISD::SETULT:
+      if (Optional<bool> IsULT = KnownBits::ult(LHSKnown, RHSKnown))
+        return DAG.getBoolConstant(IsULT.getValue(), dl, VT, OpVT);
+      break;
+    case ISD::SETULE:
+      if (Optional<bool> IsULE = KnownBits::ule(LHSKnown, RHSKnown))
+        return DAG.getBoolConstant(IsULE.getValue(), dl, VT, OpVT);
+      break;
+    }
+  }
+
   if (auto *N1C = isConstOrConstSplat(N1)) {
     const APInt &C1 = N1C->getAPIntValue();
 
     // Optimize some CTPOP cases.
     if (SDValue V = simplifySetCCWithCTPOP(*this, VT, N0, C1, Cond, dl, DAG))
       return V;
 
     // If the LHS is '(srl (ctlz x), 5)', the RHS is 0/1, and this is an
if (!VT.isVector() || DCI.isBeforeLegalizeOps()) {
       // SETUGT X, SINTMAX  -> SETLT X, 0
       // SETUGE X, SINTMIN -> SETLT X, 0
       if ((Cond == ISD::SETUGT && C1.isMaxSignedValue()) ||
           (Cond == ISD::SETUGE && C1.isMinSignedValue()))
         return DAG.getSetCC(dl, VT, N0,
                             DAG.getConstant(0, dl, N1.getValueType()),
                             ISD::SETLT);
 
       // SETULT X, SINTMIN  -> SETGT X, -1
       // SETULE X, SINTMAX  -> SETGT X, -1
       if ((Cond == ISD::SETULT && C1.isMinSignedValue()) ||
           (Cond == ISD::SETULE && C1.isMaxSignedValue()))
         return DAG.getSetCC(dl, VT, N0,
                             DAG.getAllOnesConstant(dl, N1.getValueType()),
                             ISD::SETGT);
     }
   }
 

llvm/test/CodeGen/AArch64/aarch64-split-and-bitmask-immediate.ll

entry:
   %conv = zext i1 %cmp to i8
   ret i8 %conv
 }
 
 ; This constant should not be split because it can be handled by one mov.
 define i8 @test2(i32 %a) {
 ; CHECK-LABEL: test2:
 ; CHECK:       // %bb.0: // %entry
-; CHECK-NEXT:    mov w8, #135
-; CHECK-NEXT:    and w8, w0, w8
-; CHECK-NEXT:    cmp w8, #1024
-; CHECK-NEXT:    cset w0, eq
+; CHECK-NEXT:    mov w0, wzr
 ; CHECK-NEXT:    ret
 entry:
   %and = and i32 %a, 135
   %cmp = icmp eq i32 %and, 1024
   %conv = zext i1 %cmp to i8
   ret i8 %conv
 }
 
entry:
   %cmp = icmp eq i64 %and, 1024
   %conv = zext i1 %cmp to i8
   ret i8 %conv
 }
 
 define i8 @test5(i64 %a) {
 ; CHECK-LABEL: test5:
 ; CHECK:       // %bb.0: // %entry
-; CHECK-NEXT:    and x8, x0, #0x3ffffc000
-; CHECK-NEXT:    and x8, x8, #0xfffffffe00007fff
-; CHECK-NEXT:    cmp x8, #1024
-; CHECK-NEXT:    cset w0, eq
+; CHECK-NEXT:    mov w0, wzr
 ; CHECK-NEXT:    ret
 entry:
   %and = and i64 %a, 8589950976
   %cmp = icmp eq i64 %and, 1024
   %conv = zext i1 %cmp to i8
   ret i8 %conv
 }
 
 ; This constant should not be split because it can be handled by one mov.
 define i8 @test6(i64 %a) {
 ; CHECK-LABEL: test6:
 ; CHECK:       // %bb.0: // %entry
-; CHECK-NEXT:    mov w8, #135
-; CHECK-NEXT:    and x8, x0, x8
-; CHECK-NEXT:    cmp x8, #1024
-; CHECK-NEXT:    cset w0, eq
+; CHECK-NEXT:    mov w0, wzr
 ; CHECK-NEXT:    ret
 entry:
   %and = and i64 %a, 135
   %cmp = icmp eq i64 %and, 1024
   %conv = zext i1 %cmp to i8
   ret i8 %conv
 }
 

 ;
 ; MOVi32imm -1610612736
 ; SUBREG_TO_REG
 ;
 ; The constant should be zero-extended to 64 bit and it should not be split.
 define i8 @test11(i64 %a) {
 ; CHECK-LABEL: test11:
 ; CHECK:       // %bb.0: // %entry
-; CHECK-NEXT:    mov w8, #-1610612736
-; CHECK-NEXT:    and x8, x0, x8
-; CHECK-NEXT:    cmp x8, #1024
-; CHECK-NEXT:    cset w0, eq
+; CHECK-NEXT:    mov w0, wzr
 ; CHECK-NEXT:    ret
 entry:
   %and = and i64 %a, 2684354560
   %cmp = icmp eq i64 %and, 1024
   %conv = zext i1 %cmp to i8
   ret i8 %conv
 }

llvm/test/CodeGen/AArch64/hoist-and-by-const-from-shl-in-eqcmp-zero.ll

; CHECK-NEXT:    ret
   %t1 = and i8 %t0, %x
   %res = icmp slt i8 %t1, 0
   ret i1 %res
 }
 
 define i1 @scalar_i8_signbit_eq_with_nonzero(i8 %x, i8 %y) nounwind {
 ; CHECK-LABEL: scalar_i8_signbit_eq_with_nonzero:
 ; CHECK:       // %bb.0:
-; CHECK-NEXT:    mov w8, #-128
-; CHECK-NEXT:    // kill: def $w1 killed $w1 def $x1
-; CHECK-NEXT:    lsl w8, w8, w1
-; CHECK-NEXT:    and w8, w8, w0
-; CHECK-NEXT:    and w8, w8, #0x80
-; CHECK-NEXT:    cmp w8, #1
-; CHECK-NEXT:    cset w0, eq
+; CHECK-NEXT:    mov w0, wzr
 ; CHECK-NEXT:    ret
   %t0 = shl i8 128, %y
   %t1 = and i8 %t0, %x
   %res = icmp eq i8 %t1, 1 ; should be comparing with 0
   ret i1 %res
 }

llvm/test/CodeGen/AMDGPU/wqm.ll

 ; GFX9-W64-NEXT:    v_mov_b32_e32 v0, v2
 ; GFX9-W64-NEXT:    v_add_f32_e32 v0, v1, v0
 ; GFX9-W64-NEXT:  .LBB9_2: ; %endif
 ; GFX9-W64-NEXT:    s_or_b64 exec, exec, s[2:3]
 ; GFX9-W64-NEXT:    ; return to shader part epilog
 ;
 ; GFX10-W32-LABEL: test_wwm3:
 ; GFX10-W32:       ; %bb.0: ; %main_body
-; GFX10-W32-NEXT:    v_mbcnt_lo_u32_b32 v0, -1, 0
-; GFX10-W32-NEXT:    v_mbcnt_hi_u32_b32 v0, -1, v0
-; GFX10-W32-NEXT:    v_cmp_gt_u32_e32 vcc_lo, 32, v0
 ; GFX10-W32-NEXT:    v_mov_b32_e32 v0, 0
-; GFX10-W32-NEXT:    s_and_saveexec_b32 s1, vcc_lo
+; GFX10-W32-NEXT:    s_mov_b32 s2, -1
+; GFX10-W32-NEXT:    s_and_saveexec_b32 s1, s2
 ; GFX10-W32-NEXT:    s_cbranch_execz .LBB9_2
 ; GFX10-W32-NEXT:  ; %bb.1: ; %if
 ; GFX10-W32-NEXT:    s_or_saveexec_b32 s2, -1
 ; GFX10-W32-NEXT:    v_mov_b32_e32 v1, s0
 ; GFX10-W32-NEXT:    buffer_load_dword v1, v1, s[0:3], 0 idxen
 ; GFX10-W32-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-W32-NEXT:    v_add_f32_e32 v2, v1, v1
 ; GFX10-W32-NEXT:    s_mov_b32 exec_lo, s2

 ; GFX9-W64-NEXT:    s_mov_b64 exec, s[4:5]
 ; GFX9-W64-NEXT:    v_mov_b32_e32 v0, v1
 ; GFX9-W64-NEXT:  .LBB10_2: ; %endif
 ; GFX9-W64-NEXT:    s_or_b64 exec, exec, s[2:3]
 ; GFX9-W64-NEXT:    ; return to shader part epilog
 ;
 ; GFX10-W32-LABEL: test_wwm4:
 ; GFX10-W32:       ; %bb.0: ; %main_body
-; GFX10-W32-NEXT:    v_mbcnt_lo_u32_b32 v0, -1, 0
-; GFX10-W32-NEXT:    v_mbcnt_hi_u32_b32 v0, -1, v0
-; GFX10-W32-NEXT:    v_cmp_gt_u32_e32 vcc_lo, 32, v0
 ; GFX10-W32-NEXT:    v_mov_b32_e32 v0, 0
-; GFX10-W32-NEXT:    s_and_saveexec_b32 s1, vcc_lo
+; GFX10-W32-NEXT:    s_mov_b32 s2, -1
+; GFX10-W32-NEXT:    s_and_saveexec_b32 s1, s2
 ; GFX10-W32-NEXT:    s_cbranch_execz .LBB10_2
 ; GFX10-W32-NEXT:  ; %bb.1: ; %if
 ; GFX10-W32-NEXT:    s_or_saveexec_b32 s2, -1
 ; GFX10-W32-NEXT:    v_mov_b32_e32 v1, s0
 ; GFX10-W32-NEXT:    buffer_load_dword v1, v1, s[0:3], 0 idxen
 ; GFX10-W32-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-W32-NEXT:    v_add_f32_e32 v1, v1, v1
 ; GFX10-W32-NEXT:    s_mov_b32 exec_lo, s2

 ; GFX9-W64-NEXT:    ; return to shader part epilog
 ;
 ; GFX10-W32-LABEL: test_wwm6_then:
 ; GFX10-W32:       ; %bb.0: ; %main_body
 ; GFX10-W32-NEXT:    s_or_saveexec_b32 s0, -1
 ; GFX10-W32-NEXT:    global_load_dword v1, v[3:4], off glc dlc
 ; GFX10-W32-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-W32-NEXT:    s_mov_b32 exec_lo, s0
-; GFX10-W32-NEXT:    v_mbcnt_lo_u32_b32 v0, -1, 0
-; GFX10-W32-NEXT:    v_mbcnt_hi_u32_b32 v0, -1, v0
-; GFX10-W32-NEXT:    v_cmp_gt_u32_e32 vcc_lo, 32, v0
 ; GFX10-W32-NEXT:    v_mov_b32_e32 v0, 0
-; GFX10-W32-NEXT:    s_and_saveexec_b32 s0, vcc_lo
+; GFX10-W32-NEXT:    s_mov_b32 s1, -1
+; GFX10-W32-NEXT:    s_and_saveexec_b32 s0, s1
 ; GFX10-W32-NEXT:    s_cbranch_execz .LBB12_2
 ; GFX10-W32-NEXT:  ; %bb.1: ; %if
 ; GFX10-W32-NEXT:    s_or_saveexec_b32 s1, -1
 ; GFX10-W32-NEXT:    global_load_dword v2, v[3:4], off glc dlc
 ; GFX10-W32-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-W32-NEXT:    v_add_f32_e32 v1, v1, v2
 ; GFX10-W32-NEXT:    s_mov_b32 exec_lo, s1
 ; GFX10-W32-NEXT:    v_mov_b32_e32 v0, v1

 ; GFX9-W64-NEXT:    v_mov_b32_e32 v0, v2
 ; GFX9-W64-NEXT:    v_add_f32_e32 v0, v1, v0
 ; GFX9-W64-NEXT:  .LBB17_2: ; %endif
 ; GFX9-W64-NEXT:    s_or_b64 exec, exec, s[2:3]
 ; GFX9-W64-NEXT:    ; return to shader part epilog
 ;
 ; GFX10-W32-LABEL: test_strict_wqm3:
 ; GFX10-W32:       ; %bb.0: ; %main_body
-; GFX10-W32-NEXT:    v_mbcnt_lo_u32_b32 v0, -1, 0
-; GFX10-W32-NEXT:    v_mbcnt_hi_u32_b32 v0, -1, v0
-; GFX10-W32-NEXT:    v_cmp_gt_u32_e32 vcc_lo, 32, v0
 ; GFX10-W32-NEXT:    v_mov_b32_e32 v0, 0
-; GFX10-W32-NEXT:    s_and_saveexec_b32 s1, vcc_lo
+; GFX10-W32-NEXT:    s_mov_b32 s2, -1
+; GFX10-W32-NEXT:    s_and_saveexec_b32 s1, s2
 ; GFX10-W32-NEXT:    s_cbranch_execz .LBB17_2
 ; GFX10-W32-NEXT:  ; %bb.1: ; %if
 ; GFX10-W32-NEXT:    s_mov_b32 s2, exec_lo
 ; GFX10-W32-NEXT:    s_wqm_b32 exec_lo, exec_lo
 ; GFX10-W32-NEXT:    v_mov_b32_e32 v1, s0
 ; GFX10-W32-NEXT:    buffer_load_dword v1, v1, s[0:3], 0 idxen
 ; GFX10-W32-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-W32-NEXT:    v_add_f32_e32 v2, v1, v1

 ; GFX9-W64-NEXT:    s_mov_b64 exec, s[4:5]
 ; GFX9-W64-NEXT:    v_mov_b32_e32 v0, v1
 ; GFX9-W64-NEXT:  .LBB18_2: ; %endif
 ; GFX9-W64-NEXT:    s_or_b64 exec, exec, s[2:3]
 ; GFX9-W64-NEXT:    ; return to shader part epilog
 ;
 ; GFX10-W32-LABEL: test_strict_wqm4:
 ; GFX10-W32:       ; %bb.0: ; %main_body
-; GFX10-W32-NEXT:    v_mbcnt_lo_u32_b32 v0, -1, 0
-; GFX10-W32-NEXT:    v_mbcnt_hi_u32_b32 v0, -1, v0
-; GFX10-W32-NEXT:    v_cmp_gt_u32_e32 vcc_lo, 32, v0
 ; GFX10-W32-NEXT:    v_mov_b32_e32 v0, 0
-; GFX10-W32-NEXT:    s_and_saveexec_b32 s1, vcc_lo
+; GFX10-W32-NEXT:    s_mov_b32 s2, -1
+; GFX10-W32-NEXT:    s_and_saveexec_b32 s1, s2
 ; GFX10-W32-NEXT:    s_cbranch_execz .LBB18_2
 ; GFX10-W32-NEXT:  ; %bb.1: ; %if
 ; GFX10-W32-NEXT:    s_mov_b32 s2, exec_lo
 ; GFX10-W32-NEXT:    s_wqm_b32 exec_lo, exec_lo
 ; GFX10-W32-NEXT:    v_mov_b32_e32 v1, s0
 ; GFX10-W32-NEXT:    buffer_load_dword v1, v1, s[0:3], 0 idxen
 ; GFX10-W32-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-W32-NEXT:    v_add_f32_e32 v1, v1, v1

 ;
 ; GFX10-W32-LABEL: test_strict_wqm6_then:
 ; GFX10-W32:       ; %bb.0: ; %main_body
 ; GFX10-W32-NEXT:    s_mov_b32 s0, exec_lo
 ; GFX10-W32-NEXT:    s_wqm_b32 exec_lo, exec_lo
 ; GFX10-W32-NEXT:    global_load_dword v1, v[3:4], off glc dlc
 ; GFX10-W32-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-W32-NEXT:    s_mov_b32 exec_lo, s0
-; GFX10-W32-NEXT:    v_mbcnt_lo_u32_b32 v0, -1, 0
-; GFX10-W32-NEXT:    v_mbcnt_hi_u32_b32 v0, -1, v0
-; GFX10-W32-NEXT:    v_cmp_gt_u32_e32 vcc_lo, 32, v0
 ; GFX10-W32-NEXT:    v_mov_b32_e32 v0, 0
-; GFX10-W32-NEXT:    s_and_saveexec_b32 s0, vcc_lo
+; GFX10-W32-NEXT:    s_mov_b32 s1, -1
+; GFX10-W32-NEXT:    s_and_saveexec_b32 s0, s1
 ; GFX10-W32-NEXT:    s_cbranch_execz .LBB20_2
 ; GFX10-W32-NEXT:  ; %bb.1: ; %if
 ; GFX10-W32-NEXT:    s_mov_b32 s1, exec_lo
 ; GFX10-W32-NEXT:    s_wqm_b32 exec_lo, exec_lo
 ; GFX10-W32-NEXT:    global_load_dword v2, v[3:4], off glc dlc
 ; GFX10-W32-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-W32-NEXT:    v_add_f32_e32 v1, v1, v2
 ; GFX10-W32-NEXT:    s_mov_b32 exec_lo, s1

 ; GFX9-W64-NEXT:    v_mov_b32_e32 v0, v2
 ; GFX9-W64-NEXT:    v_add_f32_e32 v0, v1, v0
 ; GFX9-W64-NEXT:  .LBB39_2: ; %endif
 ; GFX9-W64-NEXT:    s_or_b64 exec, exec, s[2:3]
 ; GFX9-W64-NEXT:    ; return to shader part epilog
 ;
 ; GFX10-W32-LABEL: test_strict_wwm3:
 ; GFX10-W32:       ; %bb.0: ; %main_body
-; GFX10-W32-NEXT:    v_mbcnt_lo_u32_b32 v0, -1, 0
-; GFX10-W32-NEXT:    v_mbcnt_hi_u32_b32 v0, -1, v0
-; GFX10-W32-NEXT:    v_cmp_gt_u32_e32 vcc_lo, 32, v0
 ; GFX10-W32-NEXT:    v_mov_b32_e32 v0, 0
-; GFX10-W32-NEXT:    s_and_saveexec_b32 s1, vcc_lo
+; GFX10-W32-NEXT:    s_mov_b32 s2, -1
+; GFX10-W32-NEXT:    s_and_saveexec_b32 s1, s2
 ; GFX10-W32-NEXT:    s_cbranch_execz .LBB39_2
 ; GFX10-W32-NEXT:  ; %bb.1: ; %if
 ; GFX10-W32-NEXT:    s_or_saveexec_b32 s2, -1
 ; GFX10-W32-NEXT:    v_mov_b32_e32 v1, s0
 ; GFX10-W32-NEXT:    buffer_load_dword v1, v1, s[0:3], 0 idxen
 ; GFX10-W32-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-W32-NEXT:    v_add_f32_e32 v2, v1, v1
 ; GFX10-W32-NEXT:    s_mov_b32 exec_lo, s2

 ; GFX9-W64-NEXT:    s_mov_b64 exec, s[4:5]
 ; GFX9-W64-NEXT:    v_mov_b32_e32 v0, v1
 ; GFX9-W64-NEXT:  .LBB40_2: ; %endif
 ; GFX9-W64-NEXT:    s_or_b64 exec, exec, s[2:3]
 ; GFX9-W64-NEXT:    ; return to shader part epilog
 ;
 ; GFX10-W32-LABEL: test_strict_wwm4:
 ; GFX10-W32:       ; %bb.0: ; %main_body
-; GFX10-W32-NEXT:    v_mbcnt_lo_u32_b32 v0, -1, 0
-; GFX10-W32-NEXT:    v_mbcnt_hi_u32_b32 v0, -1, v0
-; GFX10-W32-NEXT:    v_cmp_gt_u32_e32 vcc_lo, 32, v0
 ; GFX10-W32-NEXT:    v_mov_b32_e32 v0, 0
-; GFX10-W32-NEXT:    s_and_saveexec_b32 s1, vcc_lo
+; GFX10-W32-NEXT:    s_mov_b32 s2, -1
+; GFX10-W32-NEXT:    s_and_saveexec_b32 s1, s2
 ; GFX10-W32-NEXT:    s_cbranch_execz .LBB40_2
 ; GFX10-W32-NEXT:  ; %bb.1: ; %if
 ; GFX10-W32-NEXT:    s_or_saveexec_b32 s2, -1
 ; GFX10-W32-NEXT:    v_mov_b32_e32 v1, s0
 ; GFX10-W32-NEXT:    buffer_load_dword v1, v1, s[0:3], 0 idxen
 ; GFX10-W32-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-W32-NEXT:    v_add_f32_e32 v1, v1, v1
 ; GFX10-W32-NEXT:    s_mov_b32 exec_lo, s2

 ; GFX9-W64-NEXT:    ; return to shader part epilog
 ;
 ; GFX10-W32-LABEL: test_strict_wwm6_then:
 ; GFX10-W32:       ; %bb.0: ; %main_body
 ; GFX10-W32-NEXT:    s_or_saveexec_b32 s0, -1
 ; GFX10-W32-NEXT:    global_load_dword v1, v[3:4], off glc dlc
 ; GFX10-W32-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-W32-NEXT:    s_mov_b32 exec_lo, s0
-; GFX10-W32-NEXT:    v_mbcnt_lo_u32_b32 v0, -1, 0
-; GFX10-W32-NEXT:    v_mbcnt_hi_u32_b32 v0, -1, v0
-; GFX10-W32-NEXT:    v_cmp_gt_u32_e32 vcc_lo, 32, v0
 ; GFX10-W32-NEXT:    v_mov_b32_e32 v0, 0
-; GFX10-W32-NEXT:    s_and_saveexec_b32 s0, vcc_lo
+; GFX10-W32-NEXT:    s_mov_b32 s1, -1
+; GFX10-W32-NEXT:    s_and_saveexec_b32 s0, s1
 ; GFX10-W32-NEXT:    s_cbranch_execz .LBB42_2
 ; GFX10-W32-NEXT:  ; %bb.1: ; %if
 ; GFX10-W32-NEXT:    s_or_saveexec_b32 s1, -1
 ; GFX10-W32-NEXT:    global_load_dword v2, v[3:4], off glc dlc
 ; GFX10-W32-NEXT:    s_waitcnt vmcnt(0)
 ; GFX10-W32-NEXT:    v_add_f32_e32 v1, v1, v2
 ; GFX10-W32-NEXT:    s_mov_b32 exec_lo, s1
 ; GFX10-W32-NEXT:    v_mov_b32_e32 v0, v1

llvm/test/CodeGen/ARM/bfi.ll

; CHECK-NEXT:    bx lr
   %cmp = icmp eq i32 %and, 0
   %sel = select i1 %cmp, i32 %y2, i32 %or
   ret i32 %sel
 }
 
 define i32 @f13(i32 %x, i32 %y) {
 ; CHECK-LABEL: f13:
 ; CHECK:       @ %bb.0:
-; CHECK-NEXT:    and r2, r0, #4
-; CHECK-NEXT:    bic r0, r1, #255
-; CHECK-NEXT:    cmp r2, #42
-; CHECK-NEXT:    orrne r0, r0, #16
+; CHECK-NEXT:    mov r0, r1
+; CHECK-NEXT:    mov r1, #16
+; CHECK-NEXT:    bfi r0, r1, #0, #8
 ; CHECK-NEXT:    bx lr
   %y2 = and i32 %y, 4294967040 ; 0xFFFFFF00
   %and = and i32 %x, 4
   %or = or i32 %y2, 16
   %cmp = icmp eq i32 %and, 42 ; Not comparing against zero!
   %sel = select i1 %cmp, i32 %y2, i32 %or
   ret i32 %sel
 }

llvm/test/CodeGen/ARM/hoist-and-by-const-from-lshr-in-eqcmp-zero.ll

; THUMB78-NEXT:    bx lr
   ret i1 %res
 }
 
 ;------------------------------------------------------------------------------;
 ; A few negative tests
 ;------------------------------------------------------------------------------;
 
 define i1 @negative_scalar_i8_bitsinmiddle_slt(i8 %x, i8 %y) nounwind {
-; ARM6-LABEL: negative_scalar_i8_bitsinmiddle_slt:
-; ARM6:       @ %bb.0:
-; ARM6-NEXT:    uxtb r1, r1
-; ARM6-NEXT:    mov r2, #24
-; ARM6-NEXT:    and r1, r0, r2, lsr r1
-; ARM6-NEXT:    mov r0, #0
-; ARM6-NEXT:    cmp r1, #0
-; ARM6-NEXT:    movmi r0, #1
-; ARM6-NEXT:    bx lr
-;
-; ARM78-LABEL: negative_scalar_i8_bitsinmiddle_slt:
-; ARM78:       @ %bb.0:
-; ARM78-NEXT:    uxtb r1, r1
-; ARM78-NEXT:    mov r2, #24
-; ARM78-NEXT:    and r1, r0, r2, lsr r1
-; ARM78-NEXT:    mov r0, #0
-; ARM78-NEXT:    cmp r1, #0
-; ARM78-NEXT:    movwmi r0, #1
-; ARM78-NEXT:    bx lr
-;
-; THUMB6-LABEL: negative_scalar_i8_bitsinmiddle_slt:
-; THUMB6:       @ %bb.0:
-; THUMB6-NEXT:    uxtb r1, r1
-; THUMB6-NEXT:    movs r2, #24
-; THUMB6-NEXT:    lsrs r2, r1
-; THUMB6-NEXT:    ands r2, r0
-; THUMB6-NEXT:    bmi .LBB20_2
-; THUMB6-NEXT:  @ %bb.1:
-; THUMB6-NEXT:    movs r0, #0
-; THUMB6-NEXT:    bx lr
-; THUMB6-NEXT:  .LBB20_2:
-; THUMB6-NEXT:    movs r0, #1
-; THUMB6-NEXT:    bx lr
+; ARM-LABEL: negative_scalar_i8_bitsinmiddle_slt:
+; ARM:       @ %bb.0:
+; ARM-NEXT:    mov r0, #0
+; ARM-NEXT:    bx lr
 ;
-; THUMB78-LABEL: negative_scalar_i8_bitsinmiddle_slt:
-; THUMB78:       @ %bb.0:
-; THUMB78-NEXT:    uxtb r1, r1
-; THUMB78-NEXT:    movs r2, #24
-; THUMB78-NEXT:    lsr.w r1, r2, r1
-; THUMB78-NEXT:    ands r0, r1
-; THUMB78-NEXT:    mov.w r0, #0
-; THUMB78-NEXT:    it mi
-; THUMB78-NEXT:    movmi r0, #1
-; THUMB78-NEXT:    bx lr
+; THUMB-LABEL: negative_scalar_i8_bitsinmiddle_slt:
+; THUMB:       @ %bb.0:
+; THUMB-NEXT:    movs r0, #0
+; THUMB-NEXT:    bx lr
   %t0 = lshr i8 24, %y
   %t1 = and i8 %t0, %x
   %res = icmp slt i8 %t1, 0
   ret i1 %res
 }
 
 define i1 @scalar_i8_signbit_eq_with_nonzero(i8 %x, i8 %y) nounwind {
 ; ARM-LABEL: scalar_i8_signbit_eq_with_nonzero:

llvm/test/CodeGen/ARM/hoist-and-by-const-from-shl-in-eqcmp-zero.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=armv6 < %s | FileCheck %s --check-prefixes=ARM,ARM6
 ; RUN: llc -mtriple=armv7 < %s | FileCheck %s --check-prefixes=ARM,ARM78
 ; RUN: llc -mtriple=armv8a < %s | FileCheck %s --check-prefixes=ARM,ARM78
-; RUN: llc -mtriple=thumbv6 < %s | FileCheck %s --check-prefixes=THUMB6
-; RUN: llc -mtriple=thumbv7 < %s | FileCheck %s --check-prefixes=THUMB78,THUMB7
-; RUN: llc -mtriple=thumbv8-eabi < %s | FileCheck %s --check-prefixes=THUMB78,THUMB8
+; RUN: llc -mtriple=thumbv6 < %s | FileCheck %s --check-prefixes=THUMB,THUMB6
+; RUN: llc -mtriple=thumbv7 < %s | FileCheck %s --check-prefixes=THUMB,THUMB78,THUMB7
+; RUN: llc -mtriple=thumbv8-eabi < %s | FileCheck %s --check-prefixes=THUMB,THUMB78,THUMB8
 
 ; We are looking for the following pattern here:
 ;   (X & (C << Y)) ==/!= 0
 ; It may be optimal to hoist the constant:
 ;   ((X l>> Y) & C) ==/!= 0
 
 ;------------------------------------------------------------------------------;
 ; A few scalar test

 }
 
 define i1 @scalar_i8_signbit_eq_with_nonzero(i8 %x, i8 %y) nounwind {
 ; ARM-LABEL: scalar_i8_signbit_eq_with_nonzero:
 ; ARM:       @ %bb.0:
 ; ARM-NEXT:    mov r0, #0
 ; ARM-NEXT:    bx lr
 ;
-; THUMB6-LABEL: scalar_i8_signbit_eq_with_nonzero:
-; THUMB6:       @ %bb.0:
-; THUMB6-NEXT:    uxtb r1, r1
-; THUMB6-NEXT:    movs r2, #127
-; THUMB6-NEXT:    mvns r2, r2
-; THUMB6-NEXT:    lsls r2, r1
-; THUMB6-NEXT:    ands r2, r0
-; THUMB6-NEXT:    uxtb r0, r2
-; THUMB6-NEXT:    subs r1, r0, #1
-; THUMB6-NEXT:    rsbs r0, r1, #0
-; THUMB6-NEXT:    adcs r0, r1
-; THUMB6-NEXT:    bx lr
-;
-; THUMB78-LABEL: scalar_i8_signbit_eq_with_nonzero:
-; THUMB78:       @ %bb.0:
-; THUMB78-NEXT:    movs r0, #0
-; THUMB78-NEXT:    bx lr
+; THUMB-LABEL: scalar_i8_signbit_eq_with_nonzero:
+; THUMB:       @ %bb.0:
+; THUMB-NEXT:    movs r0, #0
+; THUMB-NEXT:    bx lr
   %t0 = shl i8 128, %y
   %t1 = and i8 %t0, %x
   %res = icmp eq i8 %t1, 1 ; should be comparing with 0
   ret i1 %res
 }

llvm/test/CodeGen/Hexagon/vect/zext-v4i1.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -march=hexagon -hexagon-instsimplify=0 < %s | FileCheck %s
 
 ; Check that this compiles successfully.
 
 target datalayout = "e-m:e-p:32:32:32-a:0-n16:32-i64:64:64-i32:32:32-i16:16:16-i1:8:8-f32:32:32-f64:64:64-v32:32:32-v64:64:64-v512:512:512-v1024:1024:1024-v2048:2048:2048"
 target triple = "hexagon"
 
 define i32 @fred(<8 x i16>* %a0) #0 {
 ; CHECK-LABEL: fred:
 ; CHECK:       // %bb.0: // %b0
 ; CHECK-NEXT:    {
-; CHECK-NEXT:     if (p0) jump:nt .LBB0_2
-; CHECK-NEXT:    }
-; CHECK-NEXT:  // %bb.1: // %b2
-; CHECK-NEXT:    {
-; CHECK-NEXT:     r3:2 = combine(#0,#0)
-; CHECK-NEXT:     r1:0 = memd(r0+#0)
-; CHECK-NEXT:    }
-; CHECK-NEXT:    {
-; CHECK-NEXT:     p0 = vcmph.eq(r1:0,r3:2)
-; CHECK-NEXT:    }
-; CHECK-NEXT:    {
-; CHECK-NEXT:     r1:0 = mask(p0)
-; CHECK-NEXT:    }
-; CHECK-NEXT:    {
-; CHECK-NEXT:     r0 = and(r0,#1)
-; CHECK-NEXT:    }
-; CHECK-NEXT:    {
-; CHECK-NEXT:     p0 = cmp.eq(r0,#11)
-; CHECK-NEXT:     r0 = #1
-; CHECK-NEXT:    }
-; CHECK-NEXT:    {
+; CHECK-NEXT:     if (!p0) r0 = #1
 ; CHECK-NEXT:     if (p0) r0 = #0
 ; CHECK-NEXT:     jumpr r31
 ; CHECK-NEXT:    }
-; CHECK-NEXT:  .LBB0_2: // %b14
-; CHECK-NEXT:    {
-; CHECK-NEXT:     r0 = #0
-; CHECK-NEXT:     jumpr r31
-; CHECK-NEXT:    }
 b0:
   switch i32 undef, label %b14 [
     i32 5, label %b2
     i32 3, label %b1
   ]
 
 b1:                                               ; preds = %b0
   br label %b14

llvm/test/CodeGen/X86/2007-10-12-CoalesceExtSubReg.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=i686-- | FileCheck %s
 
 define signext i16 @f(i32* %bp, i32* %ss)   {
 ; CHECK-LABEL: f:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    pushl %esi
-; CHECK-NEXT:    .cfi_def_cfa_offset 8
-; CHECK-NEXT:    .cfi_offset %esi, -8
 ; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %eax
-; CHECK-NEXT:    movl {{[0-9]+}}(%esp), %ecx
+; CHECK-NEXT:    movb $1, %cl
 ; CHECK-NEXT:    .p2align 4, 0x90
 ; CHECK-NEXT:  .LBB0_1: # %cond_next127
 ; CHECK-NEXT:    # =>This Inner Loop Header: Depth=1
 ; CHECK-NEXT:    movl (%eax), %edx
-; CHECK-NEXT:    movl (%ecx), %esi
 ; CHECK-NEXT:    andl $15, %edx
-; CHECK-NEXT:    andl $15, %esi
-; CHECK-NEXT:    addl %esi, (%ecx)
-; CHECK-NEXT:    cmpl $63, %edx
-; CHECK-NEXT:    jb .LBB0_1
+; CHECK-NEXT:    addl %edx, (%eax)
+; CHECK-NEXT:    testb %cl, %cl
+; CHECK-NEXT:    jne .LBB0_1
 ; CHECK-NEXT:  # %bb.2: # %UnifiedReturnBlock
 ; CHECK-NEXT:    xorl %eax, %eax
-; CHECK-NEXT:    popl %esi
-; CHECK-NEXT:    .cfi_def_cfa_offset 4
 ; CHECK-NEXT:    retl
 entry:
   br label %cond_next127
 
 cond_next127:   ; preds = %cond_next391, %entry
   %v.1 = phi i32 [ undef, %entry ], [ %tmp411, %cond_next391 ]    ; <i32> [#uses=1]
   %tmp149 = mul i32 0, %v.1   ; <i32> [#uses=0]
   %tmpss = load i32, i32* %ss, align 4    ; <i32> [#uses=1]

llvm/test/CodeGen/X86/avx512-mask-op.ll

 
 true:
   ret void
 
 false:
   ret void
 }
 define void @test7(<8 x i1> %mask)  {
-; KNL-LABEL: test7:
-; KNL:       ## %bb.0: ## %allocas
-; KNL-NEXT:    vpmovsxwq %xmm0, %zmm0
-; KNL-NEXT:    vpsllq $63, %zmm0, %zmm0
-; KNL-NEXT:    vptestmq %zmm0, %zmm0, %k0
-; KNL-NEXT:    kmovw %k0, %eax
-; KNL-NEXT:    orb $85, %al
-; KNL-NEXT:    vzeroupper
-; KNL-NEXT:    retq
-;
-; SKX-LABEL: test7:
-; SKX:       ## %bb.0: ## %allocas
-; SKX-NEXT:    vpsllw $15, %xmm0, %xmm0
-; SKX-NEXT:    vpmovw2m %xmm0, %k0
-; SKX-NEXT:    kmovd %k0, %eax
-; SKX-NEXT:    orb $85, %al
-; SKX-NEXT:    retq
-;
-; AVX512BW-LABEL: test7:
-; AVX512BW:       ## %bb.0: ## %allocas
-; AVX512BW-NEXT:    vpsllw $15, %xmm0, %xmm0
-; AVX512BW-NEXT:    vpmovw2m %zmm0, %k0
-; AVX512BW-NEXT:    kmovd %k0, %eax
-; AVX512BW-NEXT:    orb $85, %al
-; AVX512BW-NEXT:    vzeroupper
-; AVX512BW-NEXT:    retq
-;
-; AVX512DQ-LABEL: test7:
-; AVX512DQ:       ## %bb.0: ## %allocas
-; AVX512DQ-NEXT:    vpmovsxwq %xmm0, %zmm0
-; AVX512DQ-NEXT:    vpsllq $63, %zmm0, %zmm0
-; AVX512DQ-NEXT:    vpmovq2m %zmm0, %k0
-; AVX512DQ-NEXT:    kmovw %k0, %eax
-; AVX512DQ-NEXT:    orb $85, %al
-; AVX512DQ-NEXT:    vzeroupper
-; AVX512DQ-NEXT:    retq
+; CHECK-LABEL: test7:
+; CHECK:       ## %bb.0: ## %allocas
+; CHECK-NEXT:    movb $1, %al
+; CHECK-NEXT:    testb %al, %al
+; CHECK-NEXT:    retq
 ;
 ; X86-LABEL: test7:
 ; X86:       ## %bb.0: ## %allocas
-; X86-NEXT:    vpsllw $15, %xmm0, %xmm0
-; X86-NEXT:    vpmovw2m %xmm0, %k0
-; X86-NEXT:    kmovd %k0, %eax
-; X86-NEXT:    orb $85, %al
+; X86-NEXT:    movb $1, %al
+; X86-NEXT:    testb %al, %al
 ; X86-NEXT:    retl
 allocas:
   %a= or <8 x i1> %mask, <i1 true, i1 false, i1 true, i1 false, i1 true, i1 false, i1 true, i1 false>
   %b = bitcast <8 x i1> %a to i8
   %c = icmp eq i8 %b, 0
   br i1 %c, label %true, label %false
 
 true:
   ret void

llvm/test/CodeGen/X86/cmp.ll

entry:
   %cond = select i1 %tobool, i32 %intra, i32 %base
   ret i32 %cond
 
 }
 
 define dso_local i32 @test14(i32 %mask, i32 %base, i32 %intra) {
 ; CHECK-LABEL: test14:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    movl %esi, %eax # encoding: [0x89,0xf0]
-; CHECK-NEXT:    shrl $7, %edi # encoding: [0xc1,0xef,0x07]
-; CHECK-NEXT:    cmovnsl %edx, %eax # encoding: [0x0f,0x49,0xc2]
+; CHECK-NEXT:    movl %edx, %eax # encoding: [0x89,0xd0]
 ; CHECK-NEXT:    retq # encoding: [0xc3]
 entry:
   %s = lshr i32 %mask, 7
   %tobool = icmp sgt i32 %s, -1
   %cond = select i1 %tobool, i32 %intra, i32 %base
   ret i32 %cond
 
 }

llvm/test/CodeGen/X86/fold-rmw-ops.ll

 b:
   tail call void @b()
   ret void
 }
 
 define void @or64_imm32_br() nounwind {
 ; CHECK-LABEL: or64_imm32_br:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    orq $16777215, g64(%rip) # encoding: [0x48,0x81,0x0d,A,A,A,A,0xff,0xff,0xff,0x00]
-; CHECK-NEXT:    # fixup A - offset: 3, value: g64-8, kind: reloc_riprel_4byte
+; CHECK-NEXT:    orl $16777215, g64(%rip) # encoding: [0x81,0x0d,A,A,A,A,0xff,0xff,0xff,0x00]
+; CHECK-NEXT:    # fixup A - offset: 2, value: g64-8, kind: reloc_riprel_4byte
 ; CHECK-NEXT:    # imm = 0xFFFFFF
+; CHECK-NEXT:    movb $1, %al # encoding: [0xb0,0x01]
+; CHECK-NEXT:    testb %al, %al # encoding: [0x84,0xc0]
 ; CHECK-NEXT:    je .LBB46_1 # encoding: [0x74,A]
 ; CHECK-NEXT:    # fixup A - offset: 1, value: .LBB46_1-1, kind: FK_PCRel_1
 ; CHECK-NEXT:  # %bb.2: # %b
 ; CHECK-NEXT:    jmp b # TAILCALL
 ; CHECK-NEXT:    # encoding: [0xeb,A]
 ; CHECK-NEXT:    # fixup A - offset: 1, value: b-1, kind: FK_PCRel_1
 ; CHECK-NEXT:  .LBB46_1: # %a
 ; CHECK-NEXT:    jmp a # TAILCALL

 }
 
 define void @or64_sext_imm32_br() nounwind {
 ; CHECK-LABEL: or64_sext_imm32_br:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    orq $-2147483648, g64(%rip) # encoding: [0x48,0x81,0x0d,A,A,A,A,0x00,0x00,0x00,0x80]
 ; CHECK-NEXT:    # fixup A - offset: 3, value: g64-8, kind: reloc_riprel_4byte
 ; CHECK-NEXT:    # imm = 0x80000000
+; CHECK-NEXT:    movb $1, %al # encoding: [0xb0,0x01]
+; CHECK-NEXT:    testb %al, %al # encoding: [0x84,0xc0]
 ; CHECK-NEXT:    je .LBB47_1 # encoding: [0x74,A]
 ; CHECK-NEXT:    # fixup A - offset: 1, value: .LBB47_1-1, kind: FK_PCRel_1
 ; CHECK-NEXT:  # %bb.2: # %b
 ; CHECK-NEXT:    jmp b # TAILCALL
 ; CHECK-NEXT:    # encoding: [0xeb,A]
 ; CHECK-NEXT:    # fixup A - offset: 1, value: b-1, kind: FK_PCRel_1
 ; CHECK-NEXT:  .LBB47_1: # %a
 ; CHECK-NEXT:    jmp a # TAILCALL

 b:
   tail call void @b()
   ret void
 }
 
 define void @or64_imm8_br() nounwind {
 ; CHECK-LABEL: or64_imm8_br:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    orq $15, g64(%rip) # encoding: [0x48,0x83,0x0d,A,A,A,A,0x0f]
-; CHECK-NEXT:    # fixup A - offset: 3, value: g64-5, kind: reloc_riprel_4byte
+; CHECK-NEXT:    orb $15, g64(%rip) # encoding: [0x80,0x0d,A,A,A,A,0x0f]
+; CHECK-NEXT:    # fixup A - offset: 2, value: g64-5, kind: reloc_riprel_4byte
+; CHECK-NEXT:    movb $1, %al # encoding: [0xb0,0x01]
+; CHECK-NEXT:    testb %al, %al # encoding: [0x84,0xc0]
 ; CHECK-NEXT:    je .LBB48_1 # encoding: [0x74,A]
 ; CHECK-NEXT:    # fixup A - offset: 1, value: .LBB48_1-1, kind: FK_PCRel_1
 ; CHECK-NEXT:  # %bb.2: # %b
 ; CHECK-NEXT:    jmp b # TAILCALL
 ; CHECK-NEXT:    # encoding: [0xeb,A]
 ; CHECK-NEXT:    # fixup A - offset: 1, value: b-1, kind: FK_PCRel_1
 ; CHECK-NEXT:  .LBB48_1: # %a
 ; CHECK-NEXT:    jmp a # TAILCALL
b:
   ret void
 }
 
 define void @or64_imm8_neg_br() nounwind {
 ; CHECK-LABEL: or64_imm8_neg_br:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    orq $-4, g64(%rip) # encoding: [0x48,0x83,0x0d,A,A,A,A,0xfc]
 ; CHECK-NEXT:    # fixup A - offset: 3, value: g64-5, kind: reloc_riprel_4byte
+; CHECK-NEXT:    movb $1, %al # encoding: [0xb0,0x01]
+; CHECK-NEXT:    testb %al, %al # encoding: [0x84,0xc0]
 ; CHECK-NEXT:    je .LBB49_1 # encoding: [0x74,A]
 ; CHECK-NEXT:    # fixup A - offset: 1, value: .LBB49_1-1, kind: FK_PCRel_1
 ; CHECK-NEXT:  # %bb.2: # %b
 ; CHECK-NEXT:    jmp b # TAILCALL
 ; CHECK-NEXT:    # encoding: [0xeb,A]
 ; CHECK-NEXT:    # fixup A - offset: 1, value: b-1, kind: FK_PCRel_1
 ; CHECK-NEXT:  .LBB49_1: # %a
 ; CHECK-NEXT:    jmp a # TAILCALL

 b:
   tail call void @b()
   ret void
 }
 
 define void @or32_imm_br() nounwind {
 ; CHECK-LABEL: or32_imm_br:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    orl $-2147483648, g32(%rip) # encoding: [0x81,0x0d,A,A,A,A,0x00,0x00,0x00,0x80]
-; CHECK-NEXT:    # fixup A - offset: 2, value: g32-8, kind: reloc_riprel_4byte
-; CHECK-NEXT:    # imm = 0x80000000
+; CHECK-NEXT:    orb $-128, g32+3(%rip) # encoding: [0x80,0x0d,A,A,A,A,0x80]
+; CHECK-NEXT:    # fixup A - offset: 2, value: (g32+3)-5, kind: reloc_riprel_4byte
+; CHECK-NEXT:    movb $1, %al # encoding: [0xb0,0x01]
+; CHECK-NEXT:    testb %al, %al # encoding: [0x84,0xc0]
 ; CHECK-NEXT:    je .LBB50_1 # encoding: [0x74,A]
 ; CHECK-NEXT:    # fixup A - offset: 1, value: .LBB50_1-1, kind: FK_PCRel_1
 ; CHECK-NEXT:  # %bb.2: # %b
 ; CHECK-NEXT:    jmp b # TAILCALL
 ; CHECK-NEXT:    # encoding: [0xeb,A]
 ; CHECK-NEXT:    # fixup A - offset: 1, value: b-1, kind: FK_PCRel_1
 ; CHECK-NEXT:  .LBB50_1: # %a
 ; CHECK-NEXT:    jmp a # TAILCALL

 b:
   tail call void @b()
   ret void
 }
 
 define void @or32_imm8_br() nounwind {
 ; CHECK-LABEL: or32_imm8_br:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    orl $15, g32(%rip) # encoding: [0x83,0x0d,A,A,A,A,0x0f]
+; CHECK-NEXT:    orb $15, g32(%rip) # encoding: [0x80,0x0d,A,A,A,A,0x0f]
 ; CHECK-NEXT:    # fixup A - offset: 2, value: g32-5, kind: reloc_riprel_4byte
+; CHECK-NEXT:    movb $1, %al # encoding: [0xb0,0x01]
+; CHECK-NEXT:    testb %al, %al # encoding: [0x84,0xc0]
 ; CHECK-NEXT:    je .LBB51_1 # encoding: [0x74,A]
 ; CHECK-NEXT:    # fixup A - offset: 1, value: .LBB51_1-1, kind: FK_PCRel_1
 ; CHECK-NEXT:  # %bb.2: # %b
 ; CHECK-NEXT:    jmp b # TAILCALL
 ; CHECK-NEXT:    # encoding: [0xeb,A]
 ; CHECK-NEXT:    # fixup A - offset: 1, value: b-1, kind: FK_PCRel_1
 ; CHECK-NEXT:  .LBB51_1: # %a
 ; CHECK-NEXT:    jmp a # TAILCALL
b:
   ret void
 }
 
 define void @or32_imm8_neg_br() nounwind {
 ; CHECK-LABEL: or32_imm8_neg_br:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    orl $-4, g32(%rip) # encoding: [0x83,0x0d,A,A,A,A,0xfc]
 ; CHECK-NEXT:    # fixup A - offset: 2, value: g32-5, kind: reloc_riprel_4byte
+; CHECK-NEXT:    movb $1, %al # encoding: [0xb0,0x01]
+; CHECK-NEXT:    testb %al, %al # encoding: [0x84,0xc0]
 ; CHECK-NEXT:    je .LBB52_1 # encoding: [0x74,A]
 ; CHECK-NEXT:    # fixup A - offset: 1, value: .LBB52_1-1, kind: FK_PCRel_1
 ; CHECK-NEXT:  # %bb.2: # %b
 ; CHECK-NEXT:    jmp b # TAILCALL
 ; CHECK-NEXT:    # encoding: [0xeb,A]
 ; CHECK-NEXT:    # fixup A - offset: 1, value: b-1, kind: FK_PCRel_1
 ; CHECK-NEXT:  .LBB52_1: # %a
 ; CHECK-NEXT:    jmp a # TAILCALL

 b:
   tail call void @b()
   ret void
 }
 
 define void @or16_imm_br() nounwind {
 ; CHECK-LABEL: or16_imm_br:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    orw $-32768, g16(%rip) # encoding: [0x66,0x81,0x0d,A,A,A,A,0x00,0x80]
-; CHECK-NEXT:    # fixup A - offset: 3, value: g16-6, kind: reloc_riprel_4byte
-; CHECK-NEXT:    # imm = 0x8000
+; CHECK-NEXT:    orb $-128, g16+1(%rip) # encoding: [0x80,0x0d,A,A,A,A,0x80]
+; CHECK-NEXT:    # fixup A - offset: 2, value: (g16+1)-5, kind: reloc_riprel_4byte
+; CHECK-NEXT:    movb $1, %al # encoding: [0xb0,0x01]
+; CHECK-NEXT:    testb %al, %al # encoding: [0x84,0xc0]
 ; CHECK-NEXT:    je .LBB53_1 # encoding: [0x74,A]
 ; CHECK-NEXT:    # fixup A - offset: 1, value: .LBB53_1-1, kind: FK_PCRel_1
 ; CHECK-NEXT:  # %bb.2: # %b
 ; CHECK-NEXT:    jmp b # TAILCALL
 ; CHECK-NEXT:    # encoding: [0xeb,A]
 ; CHECK-NEXT:    # fixup A - offset: 1, value: b-1, kind: FK_PCRel_1
 ; CHECK-NEXT:  .LBB53_1: # %a
 ; CHECK-NEXT:    jmp a # TAILCALL

 b:
   tail call void @b()
   ret void
 }
 
 define void @or16_imm8_br() nounwind {
 ; CHECK-LABEL: or16_imm8_br:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    orw $15, g16(%rip) # encoding: [0x66,0x83,0x0d,A,A,A,A,0x0f]
-; CHECK-NEXT:    # fixup A - offset: 3, value: g16-5, kind: reloc_riprel_4byte
+; CHECK-NEXT:    orb $15, g16(%rip) # encoding: [0x80,0x0d,A,A,A,A,0x0f]
+; CHECK-NEXT:    # fixup A - offset: 2, value: g16-5, kind: reloc_riprel_4byte
+; CHECK-NEXT:    movb $1, %al # encoding: [0xb0,0x01]
+; CHECK-NEXT:    testb %al, %al # encoding: [0x84,0xc0]
 ; CHECK-NEXT:    je .LBB54_1 # encoding: [0x74,A]
 ; CHECK-NEXT:    # fixup A - offset: 1, value: .LBB54_1-1, kind: FK_PCRel_1
 ; CHECK-NEXT:  # %bb.2: # %b
 ; CHECK-NEXT:    jmp b # TAILCALL
 ; CHECK-NEXT:    # encoding: [0xeb,A]
 ; CHECK-NEXT:    # fixup A - offset: 1, value: b-1, kind: FK_PCRel_1
 ; CHECK-NEXT:  .LBB54_1: # %a
 ; CHECK-NEXT:    jmp a # TAILCALL
b:
   ret void
 }
 
 define void @or16_imm8_neg_br() nounwind {
 ; CHECK-LABEL: or16_imm8_neg_br:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    orw $-4, g16(%rip) # encoding: [0x66,0x83,0x0d,A,A,A,A,0xfc]
 ; CHECK-NEXT:    # fixup A - offset: 3, value: g16-5, kind: reloc_riprel_4byte
+; CHECK-NEXT:    movb $1, %al # encoding: [0xb0,0x01]
+; CHECK-NEXT:    testb %al, %al # encoding: [0x84,0xc0]
 ; CHECK-NEXT:    je .LBB55_1 # encoding: [0x74,A]
 ; CHECK-NEXT:    # fixup A - offset: 1, value: .LBB55_1-1, kind: FK_PCRel_1
 ; CHECK-NEXT:  # %bb.2: # %b
 ; CHECK-NEXT:    jmp b # TAILCALL
 ; CHECK-NEXT:    # encoding: [0xeb,A]
 ; CHECK-NEXT:    # fixup A - offset: 1, value: b-1, kind: FK_PCRel_1
 ; CHECK-NEXT:  .LBB55_1: # %a
 ; CHECK-NEXT:    jmp a # TAILCALL
b:
   ret void
 }
 
 define void @or8_imm_br() nounwind {
 ; CHECK-LABEL: or8_imm_br:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    orb $-4, g8(%rip) # encoding: [0x80,0x0d,A,A,A,A,0xfc]
 ; CHECK-NEXT:    # fixup A - offset: 2, value: g8-5, kind: reloc_riprel_4byte
+; CHECK-NEXT:    movb $1, %al # encoding: [0xb0,0x01]
+; CHECK-NEXT:    testb %al, %al # encoding: [0x84,0xc0]
 ; CHECK-NEXT:    je .LBB56_1 # encoding: [0x74,A]
 ; CHECK-NEXT:    # fixup A - offset: 1, value: .LBB56_1-1, kind: FK_PCRel_1
 ; CHECK-NEXT:  # %bb.2: # %b
 ; CHECK-NEXT:    jmp b # TAILCALL
 ; CHECK-NEXT:    # encoding: [0xeb,A]
 ; CHECK-NEXT:    # fixup A - offset: 1, value: b-1, kind: FK_PCRel_1
 ; CHECK-NEXT:  .LBB56_1: # %a
 ; CHECK-NEXT:    jmp a # TAILCALL

llvm/test/CodeGen/X86/hoist-and-by-const-from-shl-in-eqcmp-zero.ll

; X64-NEXT:    retq
   %t1 = and i8 %t0, %x
   %res = icmp slt i8 %t1, 0
   ret i1 %res
 }
 
 define i1 @scalar_i8_signbit_eq_with_nonzero(i8 %x, i8 %y) nounwind {
 ; X86-LABEL: scalar_i8_signbit_eq_with_nonzero:
 ; X86:       # %bb.0:
-; X86-NEXT:    movb {{[0-9]+}}(%esp), %cl
-; X86-NEXT:    movb $-128, %al
-; X86-NEXT:    shlb %cl, %al
-; X86-NEXT:    andb {{[0-9]+}}(%esp), %al
-; X86-NEXT:    cmpb $1, %al
-; X86-NEXT:    sete %al
+; X86-NEXT:    xorl %eax, %eax
 ; X86-NEXT:    retl
 ;
 ; X64-LABEL: scalar_i8_signbit_eq_with_nonzero:
 ; X64:       # %bb.0:
-; X64-NEXT:    movl %esi, %ecx
-; X64-NEXT:    movb $-128, %al
-; X64-NEXT:    # kill: def $cl killed $cl killed $ecx
-; X64-NEXT:    shlb %cl, %al
-; X64-NEXT:    andb %dil, %al
-; X64-NEXT:    cmpb $1, %al
-; X64-NEXT:    sete %al
+; X64-NEXT:    xorl %eax, %eax
 ; X64-NEXT:    retq
   %t0 = shl i8 128, %y
   %t1 = and i8 %t0, %x
   %res = icmp eq i8 %t1, 1 ; should be comparing with 0
   ret i1 %res
 }

llvm/test/CodeGen/X86/or-with-overflow.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=i686-unknown-unknown | FileCheck %s --check-prefix=X86
 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown -mattr=+cmov | FileCheck %s --check-prefix=X64
 
 ;
 ; PR48768 - 'or' clears the overflow flag, so we don't need a separate 'test'.
 ;
 
 define i8 @or_i8_ri(i8 zeroext %0, i8 zeroext %1) {
 ; X86-LABEL: or_i8_ri:
 ; X86:       # %bb.0:
 ; X86-NEXT:    movb {{[0-9]+}}(%esp), %al
-; X86-NEXT:    movl %eax, %ecx
-; X86-NEXT:    orb $-17, %cl
-; X86-NEXT:    je .LBB0_2
-; X86-NEXT:  # %bb.1:
-; X86-NEXT:    movl %ecx, %eax
-; X86-NEXT:  .LBB0_2:
+; X86-NEXT:    orb $-17, %al
 ; X86-NEXT:    retl
 ;
 ; X64-LABEL: or_i8_ri:
 ; X64:       # %bb.0:
 ; X64-NEXT:    movl %edi, %eax
 ; X64-NEXT:    orb $-17, %al
-; X64-NEXT:    movzbl %al, %eax
-; X64-NEXT:    cmovel %edi, %eax
 ; X64-NEXT:    # kill: def $al killed $al killed $eax
 ; X64-NEXT:    retq
   %3 = or i8 %0, -17
   %4 = icmp eq i8 %3, 0
   %5 = select i1 %4, i8 %0, i8 %3
   ret i8 %5
 }
 
; X64-NEXT:    retq
   %4 = icmp eq i8 %3, 0
   %5 = select i1 %4, i8 %0, i8 %3
   ret i8 %5
 }
 
 define i16 @or_i16_ri(i16 zeroext %0, i16 zeroext %1) {
 ; X86-LABEL: or_i16_ri:
 ; X86:       # %bb.0:
-; X86-NEXT:    movl {{[0-9]+}}(%esp), %eax
-; X86-NEXT:    movl %eax, %ecx
-; X86-NEXT:    orl $-17, %ecx
-; X86-NEXT:    testw %cx, %cx
-; X86-NEXT:    je .LBB2_2
-; X86-NEXT:  # %bb.1:
-; X86-NEXT:    movl %ecx, %eax
-; X86-NEXT:  .LBB2_2:
+; X86-NEXT:    movl $65519, %eax # imm = 0xFFEF
+; X86-NEXT:    orl {{[0-9]+}}(%esp), %eax
 ; X86-NEXT:    # kill: def $ax killed $ax killed $eax
 ; X86-NEXT:    retl
 ;
 ; X64-LABEL: or_i16_ri:
 ; X64:       # %bb.0:
 ; X64-NEXT:    movl %edi, %eax
-; X64-NEXT:    orl $-17, %eax
-; X64-NEXT:    testw %ax, %ax
-; X64-NEXT:    cmovel %edi, %eax
+; X64-NEXT:    orl $65519, %eax # imm = 0xFFEF
 ; X64-NEXT:    # kill: def $ax killed $ax killed $eax
 ; X64-NEXT:    retq
   %3 = or i16 %0, -17
   %4 = icmp eq i16 %3, 0
   %5 = select i1 %4, i16 %0, i16 %3
   ret i16 %5
 }
 
; X64-NEXT:    retq
   %5 = select i1 %4, i16 %0, i16 %3
   ret i16 %5
 }
 
 define i32 @or_i32_ri(i32 %0, i32 %1) {
 ; X86-LABEL: or_i32_ri:
 ; X86:       # %bb.0:
 ; X86-NEXT:    movl {{[0-9]+}}(%esp), %eax
-; X86-NEXT:    movl %eax, %ecx
-; X86-NEXT:    orl $-17, %ecx
-; X86-NEXT:    jle .LBB4_2
-; X86-NEXT:  # %bb.1:
-; X86-NEXT:    movl %ecx, %eax
-; X86-NEXT:  .LBB4_2:
 ; X86-NEXT:    retl
 ;
 ; X64-LABEL: or_i32_ri:
 ; X64:       # %bb.0:
 ; X64-NEXT:    movl %edi, %eax
-; X64-NEXT:    orl $-17, %eax
-; X64-NEXT:    cmovlel %edi, %eax
 ; X64-NEXT:    retq
   %3 = or i32 %0, -17
   %4 = icmp slt i32 %3, 1
   %5 = select i1 %4, i32 %0, i32 %3
   ret i32 %5
 }
 
 define i32 @or_i32_rr(i32 %0, i32 %1) {
; X64-NEXT:    retq
   %4 = icmp slt i32 %3, 1
   %5 = select i1 %4, i32 %0, i32 %3
   ret i32 %5
 }
 
 define i64 @or_i64_ri(i64 %0, i64 %1) nounwind {
 ; X86-LABEL: or_i64_ri:
 ; X86:       # %bb.0:
-; X86-NEXT:    pushl %esi
 ; X86-NEXT:    movl {{[0-9]+}}(%esp), %eax
-; X86-NEXT:    movl %eax, %ecx
-; X86-NEXT:    orl $-17, %ecx
-; X86-NEXT:    cmpl $1, %ecx
-; X86-NEXT:    movl $-1, %edx
-; X86-NEXT:    movl $-1, %esi
-; X86-NEXT:    sbbl $0, %esi
-; X86-NEXT:    jl .LBB6_1
-; X86-NEXT:  # %bb.2:
-; X86-NEXT:    movl %ecx, %eax
-; X86-NEXT:    popl %esi
-; X86-NEXT:    retl
-; X86-NEXT:  .LBB6_1:
 ; X86-NEXT:    movl {{[0-9]+}}(%esp), %edx
-; X86-NEXT:    popl %esi
 ; X86-NEXT:    retl
 ;
 ; X64-LABEL: or_i64_ri:
 ; X64:       # %bb.0:
 ; X64-NEXT:    movq %rdi, %rax
-; X64-NEXT:    orq $-17, %rax
-; X64-NEXT:    cmovleq %rdi, %rax
 ; X64-NEXT:    retq
   %3 = or i64 %0, -17
   %4 = icmp slt i64 %3, 1
   %5 = select i1 %4, i64 %0, i64 %3
   ret i64 %5
 }
 
 define i64 @or_i64_rr(i64 %0, i64 %1) nounwind {

llvm/test/CodeGen/X86/pr16031.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=i386-unknown-linux-gnu -mcpu=corei7-avx -enable-misched=false | FileCheck %s
 
 define i64 @main(i1 %tobool1) nounwind {
 ; CHECK-LABEL: main:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    pushl %esi
-; CHECK-NEXT:    testb $1, {{[0-9]+}}(%esp)
-; CHECK-NEXT:    movl $-12, %eax
-; CHECK-NEXT:    movl $-1, %ecx
-; CHECK-NEXT:    cmovel %ecx, %eax
+; CHECK-NEXT:    xorl %eax, %eax
 ; CHECK-NEXT:    xorl %edx, %edx
-; CHECK-NEXT:    movl %eax, %esi
-; CHECK-NEXT:    addl $-1, %esi
-; CHECK-NEXT:    adcl $-1, %ecx
-; CHECK-NEXT:    cmovsl %edx, %eax
-; CHECK-NEXT:    xorl %edx, %edx
-; CHECK-NEXT:    popl %esi
 ; CHECK-NEXT:    retl
 entry:
   %0 = zext i1 %tobool1 to i32
   %. = xor i32 %0, 1
   %.21 = select i1 %tobool1, i32 -12, i32 -1
   %conv = sext i32 %.21 to i64
   %1 = add i64 %conv, -1
   %cmp10 = icmp slt i64 %1, 0
   %sub17 = select i1 %cmp10, i64 0, i64 %conv
   ret i64 %sub17
 }

llvm/test/CodeGen/X86/scheduler-backtracking.ll

 ; Tests checking backtracking in source scheduler. llc used to crash on them.
 
 define i256 @test1(i256 %a) nounwind {
 ; ILP-LABEL: test1:
 ; ILP:       # %bb.0:
 ; ILP-NEXT:    pushq %r14
 ; ILP-NEXT:    pushq %rbx
 ; ILP-NEXT:    movq %rdi, %rax
-; ILP-NEXT:    xorl %r8d, %r8d
 ; ILP-NEXT:    addl %esi, %esi
-; ILP-NEXT:    leal 3(%rsi), %r9d
-; ILP-NEXT:    movl $1, %r11d
-; ILP-NEXT:    xorl %r14d, %r14d
-; ILP-NEXT:    movl %r9d, %ecx
-; ILP-NEXT:    shldq %cl, %r11, %r14
-; ILP-NEXT:    movl $1, %edx
-; ILP-NEXT:    shlq %cl, %rdx
-; ILP-NEXT:    leal -125(%rsi), %r10d
-; ILP-NEXT:    xorl %ebx, %ebx
+; ILP-NEXT:    leal -125(%rsi), %r9d
+; ILP-NEXT:    xorl %r8d, %r8d
+; ILP-NEXT:    leal 3(%rsi), %r10d
+; ILP-NEXT:    movl $1, %r14d
+; ILP-NEXT:    xorl %r11d, %r11d
 ; ILP-NEXT:    movl %r10d, %ecx
-; ILP-NEXT:    shldq %cl, %r11, %rbx
-; ILP-NEXT:    testb $64, %r9b
-; ILP-NEXT:    cmovneq %rdx, %r14
-; ILP-NEXT:    cmovneq %r8, %rdx
+; ILP-NEXT:    shldq %cl, %r14, %r11
+; ILP-NEXT:    xorl %ebx, %ebx
+; ILP-NEXT:    movl %r9d, %ecx
+; ILP-NEXT:    shldq %cl, %r14, %rbx
 ; ILP-NEXT:    movl $1, %edi
+; ILP-NEXT:    movl %r10d, %ecx
 ; ILP-NEXT:    shlq %cl, %rdi
+; ILP-NEXT:    movl $1, %edx
+; ILP-NEXT:    movl %r9d, %ecx
+; ILP-NEXT:    shlq %cl, %rdx
 ; ILP-NEXT:    movb $125, %cl
 ; ILP-NEXT:    subb %sil, %cl
-; ILP-NEXT:    shrdq %cl, %r8, %r11
+; ILP-NEXT:    shrdq %cl, %r8, %r14
 ; ILP-NEXT:    testb $64, %cl
-; ILP-NEXT:    cmovneq %r8, %r11
+; ILP-NEXT:    cmovneq %r8, %r14
+; ILP-NEXT:    testb $64, %r9b
+; ILP-NEXT:    cmovneq %rdx, %rbx
+; ILP-NEXT:    cmovneq %r8, %rdx
 ; ILP-NEXT:    testb $64, %r10b
-; ILP-NEXT:    cmovneq %rdi, %rbx
+; ILP-NEXT:    cmovneq %rdi, %r11
 ; ILP-NEXT:    cmovneq %r8, %rdi
-; ILP-NEXT:    testb %r9b, %r9b
-; ILP-NEXT:    cmovsq %r8, %r14
-; ILP-NEXT:    cmovsq %r8, %rdx
-; ILP-NEXT:    movq %r14, 8(%rax)
-; ILP-NEXT:    movq %rdx, (%rax)
+; ILP-NEXT:    testb %r10b, %r10b
 ; ILP-NEXT:    cmovnsq %r8, %rbx
-; ILP-NEXT:    cmoveq %r8, %rbx
 ; ILP-NEXT:    movq %rbx, 24(%rax)
-; ILP-NEXT:    cmovnsq %r11, %rdi
-; ILP-NEXT:    cmoveq %r8, %rdi
-; ILP-NEXT:    movq %rdi, 16(%rax)
+; ILP-NEXT:    cmovnsq %r14, %rdx
+; ILP-NEXT:    movq %rdx, 16(%rax)
+; ILP-NEXT:    cmovsq %r8, %r11
+; ILP-NEXT:    movq %r11, 8(%rax)
+; ILP-NEXT:    cmovsq %r8, %rdi
+; ILP-NEXT:    movq %rdi, (%rax)
 ; ILP-NEXT:    popq %rbx
 ; ILP-NEXT:    popq %r14
 ; ILP-NEXT:    retq
 ;
 ; HYBRID-LABEL: test1:
 ; HYBRID:       # %bb.0:
 ; HYBRID-NEXT:    pushq %rbx
 ; HYBRID-NEXT:    movq %rdi, %rax
 ; HYBRID-NEXT:    addl %esi, %esi
 ; HYBRID-NEXT:    movb $125, %cl
 ; HYBRID-NEXT:    subb %sil, %cl
 ; HYBRID-NEXT:    xorl %r8d, %r8d
 ; HYBRID-NEXT:    movl $1, %edi
-; HYBRID-NEXT:    movl $1, %r9d
-; HYBRID-NEXT:    shrdq %cl, %r8, %r9
+; HYBRID-NEXT:    movl $1, %r10d
+; HYBRID-NEXT:    shrdq %cl, %r8, %r10
 ; HYBRID-NEXT:    testb $64, %cl
-; HYBRID-NEXT:    cmovneq %r8, %r9
-; HYBRID-NEXT:    leal 3(%rsi), %r10d
+; HYBRID-NEXT:    cmovneq %r8, %r10
+; HYBRID-NEXT:    leal -125(%rsi), %r9d
+; HYBRID-NEXT:    xorl %edx, %edx
+; HYBRID-NEXT:    movl %r9d, %ecx
+; HYBRID-NEXT:    shldq %cl, %rdi, %rdx
+; HYBRID-NEXT:    addb $3, %sil
 ; HYBRID-NEXT:    xorl %r11d, %r11d
-; HYBRID-NEXT:    movl %r10d, %ecx
-; HYBRID-NEXT:    shldq %cl, %rdi, %r11
-; HYBRID-NEXT:    addb $-125, %sil
-; HYBRID-NEXT:    xorl %ebx, %ebx
 ; HYBRID-NEXT:    movl %esi, %ecx
-; HYBRID-NEXT:    shldq %cl, %rdi, %rbx
-; HYBRID-NEXT:    movl $1, %edx
-; HYBRID-NEXT:    shlq %cl, %rdx
+; HYBRID-NEXT:    shldq %cl, %rdi, %r11
+; HYBRID-NEXT:    movl $1, %ebx
+; HYBRID-NEXT:    shlq %cl, %rbx
 ; HYBRID-NEXT:    testb $64, %sil
-; HYBRID-NEXT:    cmovneq %rdx, %rbx
-; HYBRID-NEXT:    cmovneq %r8, %rdx
-; HYBRID-NEXT:    movl %r10d, %ecx
+; HYBRID-NEXT:    cmovneq %rbx, %r11
+; HYBRID-NEXT:    cmovneq %r8, %rbx
+; HYBRID-NEXT:    movl %r9d, %ecx
 ; HYBRID-NEXT:    shlq %cl, %rdi
-; HYBRID-NEXT:    testb $64, %r10b
-; HYBRID-NEXT:    cmovneq %rdi, %r11
+; HYBRID-NEXT:    testb $64, %r9b
+; HYBRID-NEXT:    cmovneq %rdi, %rdx
 ; HYBRID-NEXT:    cmovneq %r8, %rdi
-; HYBRID-NEXT:    testb %r10b, %r10b
+; HYBRID-NEXT:    testb %sil, %sil
+; HYBRID-NEXT:    cmovnsq %r8, %rdx
+; HYBRID-NEXT:    movq %rdx, 24(%rax)
+; HYBRID-NEXT:    cmovnsq %r10, %rdi
+; HYBRID-NEXT:    movq %rdi, 16(%rax)
 ; HYBRID-NEXT:    cmovsq %r8, %r11
 ; HYBRID-NEXT:    movq %r11, 8(%rax)
-; HYBRID-NEXT:    cmovsq %r8, %rdi
-; HYBRID-NEXT:    movq %rdi, (%rax)
-; HYBRID-NEXT:    cmovnsq %r8, %rbx
-; HYBRID-NEXT:    cmoveq %r8, %rbx
-; HYBRID-NEXT:    movq %rbx, 24(%rax)
-; HYBRID-NEXT:    cmovnsq %r9, %rdx
-; HYBRID-NEXT:    cmoveq %r8, %rdx
-; HYBRID-NEXT:    movq %rdx, 16(%rax)
+; HYBRID-NEXT:    cmovsq %r8, %rbx
+; HYBRID-NEXT:    movq %rbx, (%rax)
 ; HYBRID-NEXT:    popq %rbx
 ; HYBRID-NEXT:    retq
 ;
 ; BURR-LABEL: test1:
 ; BURR:       # %bb.0:
 ; BURR-NEXT:    pushq %rbx
 ; BURR-NEXT:    movq %rdi, %rax
 ; BURR-NEXT:    addl %esi, %esi
 ; BURR-NEXT:    movb $125, %cl
 ; BURR-NEXT:    subb %sil, %cl
 ; BURR-NEXT:    xorl %r8d, %r8d
 ; BURR-NEXT:    movl $1, %edi
-; BURR-NEXT:    movl $1, %r9d
-; BURR-NEXT:    shrdq %cl, %r8, %r9
+; BURR-NEXT:    movl $1, %r10d
+; BURR-NEXT:    shrdq %cl, %r8, %r10
 ; BURR-NEXT:    testb $64, %cl
-; BURR-NEXT:    cmovneq %r8, %r9
-; BURR-NEXT:    leal 3(%rsi), %r10d
+; BURR-NEXT:    cmovneq %r8, %r10
+; BURR-NEXT:    leal -125(%rsi), %r9d
+; BURR-NEXT:    xorl %edx, %edx
+; BURR-NEXT:    movl %r9d, %ecx
+; BURR-NEXT:    shldq %cl, %rdi, %rdx
+; BURR-NEXT:    addb $3, %sil
 ; BURR-NEXT:    xorl %r11d, %r11d
-; BURR-NEXT:    movl %r10d, %ecx
-; BURR-NEXT:    shldq %cl, %rdi, %r11
-; BURR-NEXT:    addb $-125, %sil
-; BURR-NEXT:    xorl %ebx, %ebx
 ; BURR-NEXT:    movl %esi, %ecx
-; BURR-NEXT:    shldq %cl, %rdi, %rbx
-; BURR-NEXT:    movl $1, %edx
-; BURR-NEXT:    shlq %cl, %rdx
+; BURR-NEXT:    shldq %cl, %rdi, %r11
+; BURR-NEXT:    movl $1, %ebx
+; BURR-NEXT:    shlq %cl, %rbx
 ; BURR-NEXT:    testb $64, %sil
-; BURR-NEXT:    cmovneq %rdx, %rbx
-; BURR-NEXT:    cmovneq %r8, %rdx
-; BURR-NEXT:    movl %r10d, %ecx
+; BURR-NEXT:    cmovneq %rbx, %r11
+; BURR-NEXT:    cmovneq %r8, %rbx
+; BURR-NEXT:    movl %r9d, %ecx
 ; BURR-NEXT:    shlq %cl, %rdi
-; BURR-NEXT:    testb $64, %r10b
-; BURR-NEXT:    cmovneq %rdi, %r11
+; BURR-NEXT:    testb $64, %r9b
+; BURR-NEXT:    cmovneq %rdi, %rdx
 ; BURR-NEXT:    cmovneq %r8, %rdi
-; BURR-NEXT:    testb %r10b, %r10b
+; BURR-NEXT:    testb %sil, %sil
+; BURR-NEXT:    cmovnsq %r8, %rdx
+; BURR-NEXT:    movq %rdx, 24(%rax)
+; BURR-NEXT:    cmovnsq %r10, %rdi
+; BURR-NEXT:    movq %rdi, 16(%rax)
 ; BURR-NEXT:    cmovsq %r8, %r11
 ; BURR-NEXT:    movq %r11, 8(%rax)
-; BURR-NEXT:    cmovsq %r8, %rdi
-; BURR-NEXT:    movq %rdi, (%rax)
-; BURR-NEXT:    cmovnsq %r8, %rbx
-; BURR-NEXT:    cmoveq %r8, %rbx
-; BURR-NEXT:    movq %rbx, 24(%rax)
-; BURR-NEXT:    cmovnsq %r9, %rdx
-; BURR-NEXT:    cmoveq %r8, %rdx
-; BURR-NEXT:    movq %rdx, 16(%rax)
+; BURR-NEXT:    cmovsq %r8, %rbx
+; BURR-NEXT:    movq %rbx, (%rax)
 ; BURR-NEXT:    popq %rbx
 ; BURR-NEXT:    retq
 ;
 ; SRC-LABEL: test1:
 ; SRC:       # %bb.0:
 ; SRC-NEXT:    pushq %rbx
 ; SRC-NEXT:    movq %rdi, %rax
 ; SRC-NEXT:    addl %esi, %esi
 ; SRC-NEXT:    leal 3(%rsi), %r9d
 ; SRC-NEXT:    movb $125, %cl
 ; SRC-NEXT:    subb %sil, %cl
 ; SRC-NEXT:    xorl %r8d, %r8d
 ; SRC-NEXT:    movl $1, %edi
 ; SRC-NEXT:    movl $1, %r10d
 ; SRC-NEXT:    shrdq %cl, %r8, %r10
 ; SRC-NEXT:    testb $64, %cl
 ; SRC-NEXT:    cmovneq %r8, %r10
 ; SRC-NEXT:    addb $-125, %sil
-; SRC-NEXT:    xorl %edx, %edx
-; SRC-NEXT:    movl %esi, %ecx
-; SRC-NEXT:    shldq %cl, %rdi, %rdx
 ; SRC-NEXT:    xorl %r11d, %r11d
-; SRC-NEXT:    movl %r9d, %ecx
+; SRC-NEXT:    movl %esi, %ecx
 ; SRC-NEXT:    shldq %cl, %rdi, %r11
+; SRC-NEXT:    xorl %edx, %edx
+; SRC-NEXT:    movl %r9d, %ecx
+; SRC-NEXT:    shldq %cl, %rdi, %rdx
 ; SRC-NEXT:    movl $1, %ebx
 ; SRC-NEXT:    shlq %cl, %rbx
 ; SRC-NEXT:    testb $64, %r9b
-; SRC-NEXT:    cmovneq %rbx, %r11
+; SRC-NEXT:    cmovneq %rbx, %rdx
 ; SRC-NEXT:    cmovneq %r8, %rbx
 ; SRC-NEXT:    movl %esi, %ecx
 ; SRC-NEXT:    shlq %cl, %rdi
 ; SRC-NEXT:    testb $64, %sil
-; SRC-NEXT:    cmovneq %rdi, %rdx
+; SRC-NEXT:    cmovneq %rdi, %r11
 ; SRC-NEXT:    cmovneq %r8, %rdi
 ; SRC-NEXT:    testb %r9b, %r9b
+; SRC-NEXT:    cmovsq %r8, %rdx
 ; SRC-NEXT:    cmovnsq %r10, %rdi
-; SRC-NEXT:    cmoveq %r8, %rdi
-; SRC-NEXT:    cmovnsq %r8, %rdx
-; SRC-NEXT:    cmoveq %r8, %rdx
-; SRC-NEXT:    cmovsq %r8, %r11
+; SRC-NEXT:    cmovnsq %r8, %r11
 ; SRC-NEXT:    cmovsq %r8, %rbx
-; SRC-NEXT:    movq %r11, 8(%rax)
-; SRC-NEXT:    movq %rbx, (%rax)
-; SRC-NEXT:    movq %rdx, 24(%rax)
+; SRC-NEXT:    movq %r11, 24(%rax)
 ; SRC-NEXT:    movq %rdi, 16(%rax)
+; SRC-NEXT:    movq %rdx, 8(%rax)
+; SRC-NEXT:    movq %rbx, (%rax)
 ; SRC-NEXT:    popq %rbx
 ; SRC-NEXT:    retq
 ;
 ; LIN-LABEL: test1:
 ; LIN:       # %bb.0:
 ; LIN-NEXT:    movq %rdi, %rax
 ; LIN-NEXT:    xorl %r9d, %r9d
 ; LIN-NEXT:    movl $1, %r8d

 ; LIN-NEXT:    movq %rdx, (%rax)
 ; LIN-NEXT:    xorl %edx, %edx
 ; LIN-NEXT:    # kill: def $cl killed $cl killed $ecx
 ; LIN-NEXT:    shldq %cl, %r8, %rdx
 ; LIN-NEXT:    cmovneq %rdi, %rdx
 ; LIN-NEXT:    cmovsq %r9, %rdx
 ; LIN-NEXT:    movq %rdx, 8(%rax)
 ; LIN-NEXT:    leal -125(%rsi), %r10d
-; LIN-NEXT:    movl $1, %edx
+; LIN-NEXT:    movl $1, %edi
 ; LIN-NEXT:    movl %r10d, %ecx
-; LIN-NEXT:    shlq %cl, %rdx
+; LIN-NEXT:    shlq %cl, %rdi
 ; LIN-NEXT:    testb $64, %r10b
-; LIN-NEXT:    movq %rdx, %rdi
-; LIN-NEXT:    cmovneq %r9, %rdi
+; LIN-NEXT:    movq %rdi, %rdx
+; LIN-NEXT:    cmovneq %r9, %rdx
 ; LIN-NEXT:    movb $125, %cl
 ; LIN-NEXT:    subb %sil, %cl
 ; LIN-NEXT:    movl $1, %esi
 ; LIN-NEXT:    shrdq %cl, %r9, %rsi
 ; LIN-NEXT:    testb $64, %cl
 ; LIN-NEXT:    cmovneq %r9, %rsi
-; LIN-NEXT:    cmovsq %rdi, %rsi
-; LIN-NEXT:    cmoveq %r9, %rsi
+; LIN-NEXT:    cmovsq %rdx, %rsi
 ; LIN-NEXT:    movq %rsi, 16(%rax)
-; LIN-NEXT:    xorl %esi, %esi
+; LIN-NEXT:    xorl %edx, %edx
 ; LIN-NEXT:    movl %r10d, %ecx
-; LIN-NEXT:    shldq %cl, %r8, %rsi
-; LIN-NEXT:    cmovneq %rdx, %rsi
-; LIN-NEXT:    cmovnsq %r9, %rsi
-; LIN-NEXT:    cmoveq %r9, %rsi
-; LIN-NEXT:    movq %rsi, 24(%rax)
+; LIN-NEXT:    shldq %cl, %r8, %rdx
+; LIN-NEXT:    cmovneq %rdi, %rdx
+; LIN-NEXT:    cmovnsq %r9, %rdx
+; LIN-NEXT:    movq %rdx, 24(%rax)
 ; LIN-NEXT:    retq
   %b = add i256 %a, 1
   %m = shl i256 %b, 1
   %p = add i256 %m, 1
   %v = lshr i256 %b, %p
   %t = trunc i256 %v to i1
   %c = shl i256 1, %p
   %f = select i1 %t, i256 undef, i256 %c

llvm/test/CodeGen/X86/shrink-compare-pgso.ll

 
 if.end:
   ret void
 }
 
 define dso_local void @test2_1(i32 %X) nounwind !prof !14 {
 ; CHECK-LABEL: test2_1:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    movzbl %dil, %eax
-; CHECK-NEXT:    cmpl $256, %eax # imm = 0x100
+; CHECK-NEXT:    movb $1, %al
+; CHECK-NEXT:    testb %al, %al
 ; CHECK-NEXT:    je bar # TAILCALL
 ; CHECK-NEXT:  # %bb.1: # %if.end
 ; CHECK-NEXT:    retq
 entry:
   %and = and i32 %X, 255
   %cmp = icmp eq i32 %and, 256
   br i1 %cmp, label %if.then, label %if.end
 

llvm/test/CodeGen/X86/shrink-compare.ll

 
 if.end:
   ret void
 }
 
 define dso_local void @test2_1(i32 %X) nounwind minsize {
 ; CHECK-LABEL: test2_1:
 ; CHECK:       # %bb.0: # %entry
-; CHECK-NEXT:    movzbl %dil, %eax
-; CHECK-NEXT:    cmpl $256, %eax # imm = 0x100
+; CHECK-NEXT:    movb $1, %al
+; CHECK-NEXT:    testb %al, %al
 ; CHECK-NEXT:    je bar # TAILCALL
 ; CHECK-NEXT:  # %bb.1: # %if.end
 ; CHECK-NEXT:    retq
 entry:
   %and = and i32 %X, 255
   %cmp = icmp eq i32 %and, 256
   br i1 %cmp, label %if.then, label %if.end
 

llvm/test/CodeGen/X86/shuffle-combine-crash-3.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=x86_64-unknown-unknown | FileCheck %s
 
 ; Verify that we don't crash when compiling this. We used to hit an
 ; assert like this
 ;
 ;   llc: ../include/llvm/CodeGen/ValueTypes.h:251: llvm::MVT llvm::EVT::getSimpleVT() const: Assertion `isSimple() && "Expected a SimpleValueType!"' failed.
 ;
 ; due to getFauxShuffleMask not checking that the VT was simple before a call
 ; to getSimpleValueType().
 
 define i1 @dont_hit_assert(i24 signext %d) {
 ; CHECK-LABEL: dont_hit_assert:
 ; CHECK:       # %bb.0: # %for.cond
-; CHECK-NEXT:    movb $-1, %al
-; CHECK-NEXT:    negb %al
-; CHECK-NEXT:    sete %al
+; CHECK-NEXT:    xorl %eax, %eax
 ; CHECK-NEXT:    retq
 for.cond:
   %t0 = insertelement <8 x i24> zeroinitializer, i24 1, i32 0
   %t5 = icmp slt <8 x i24> %t0, zeroinitializer
   %t7 = icmp slt i24 0, %d
   %rdx.shuf = shufflevector <8 x i1> %t5, <8 x i1> undef, <8 x i32> <i32 4, i32 5, i32 6, i32 7, i32 undef, i32 undef, i32 undef, i32 undef>
   %bin.rdx = and <8 x i1> %t5, %rdx.shuf
   %rdx.shuf22 = shufflevector <8 x i1> %bin.rdx, <8 x i1> undef, <8 x i32> <i32 2, i32 3, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
   %bin.rdx23 = and <8 x i1> %bin.rdx, %rdx.shuf22
   %rdx.shuf24 = shufflevector <8 x i1> %bin.rdx23, <8 x i1> undef, <8 x i32> <i32 1, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef, i32 undef>
   %bin.rdx25 = and <8 x i1> %bin.rdx23, %rdx.shuf24
   %t8 = extractelement <8 x i1> %bin.rdx25, i32 0
   ret i1 %t8
 }