- User Since
- Sep 4 2018, 4:49 AM (96 w, 23 h)
Mon, Jul 6
Technically this is NFC with current hardware configurations, but I would like to be able to decouple this from MAD/MAC.
Thu, Jul 2
Tue, Jun 30
- Add comment
- Rename generateEndPgm
- Edit comment for clarity
- Add explicit test to skip-if-dead.ll
Mon, Jun 29
I appreciate there might be some resistance to this way of doing things, i.e. relying on control flow lowering to insert cleanup markers. As an alternative I can rewrite this to look directly at the exec mask processing during the insert skips pass.
Sun, Jun 28
Rework this on top of D77544.
Make insertion of skips near the beginning of blocks work correctly by splitting blocks.
Sat, Jun 27
Fri, Jun 26
This is a stepping stop to adding early termination in more places because it means termination can be added anywhere in a basic block (without splitting basic blocks).
Tue, Jun 23
Fri, Jun 19
Address comments on foldMemoryOperandImpl.
Ping - I would like to get this moving again.
- Add test for foldMemoryOperandImpl
- Rework code in foldMemoryOperandImpl to remove references to specific physical registers
Thu, Jun 18
Wed, Jun 17
This is the simplified version which blocks spill/reload of exec from occuring.
Simplify test changes.
Fix error in test update.
Update spill-special-sgpr.mir for auto updated version.
Tue, Jun 16
Mon, Jun 15
Remove LiveIn parts.
I have concluded that they are wrong, or at least too complicated for a simple test.
In small functions parts of the ScratchRSrcReg may be formed from registers that
are live-ins, and these will work fine.
Sun, Jun 14
Fri, Jun 12
Thu, Jun 11
Jun 5 2020
Change to SReg_64_XEXECRegClass.
Jun 2 2020
May 29 2020
Update spill-wide-sgpr.ll for new tests in master.
May 27 2020
- Address outstanding comments.
- Add stack offset checks to MIR test.
May 26 2020
- Tidy test whitespace
- Directly output buffer_store/load from SGPR spill.
- Add assertion for type of spill slot.
May 21 2020
- Address comments.
- Add MIR test.
May 20 2020
May 19 2020
May 15 2020
May 14 2020
Make test work with amdgpu-waves-per-eu.
- Fix bug where offset register would not be correctly restored
- Modify test to use smaller array (compiles much faster)
- Add checks in test
May 13 2020
Address (1) by only processing on export nodes.
Since there is no way to remove a successor directly, use the
existing removeExportDependencies code and simply apply it to
Add test case.
May 12 2020
- Improve efficiency of sorting position exports
- Comment on why position exports should come before others
- Add test for reordering over loads
May 11 2020
May 10 2020
Simplify the code and improve scheduling by removing unnecessary
dependencies edges on exports.
May 9 2020
Fix failing test.
May 7 2020
Address Jay's comments.
May 6 2020
Apr 28 2020
Update intrinsic parameters:
llvm.amdgcn.wqm.demote - IntrWriteMem, IntrInaccessibleMemOnly
llvm.amdgcn.wqm.helper - IntrReadMem, IntrInaccessibleMemOnly
Add DivergenceAnalysis test.
Mark intrinsics as convergent.
Rename a variable.
Apr 24 2020
Apr 21 2020
Apr 20 2020
Update to move comprehensive implementation now fairly tested
Now preserves LiveInterval analysis.
This is dependent on D78417.