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javed.absar (Javed Absar)
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User Since
Mar 27 2015, 6:20 AM (193 w, 5 d)

Recent Activity

Mon, Dec 10

javed.absar accepted D55509: [NFC][AArch64] Remove duplicate Arch list in target parser tests..

LGTM

Mon, Dec 10, 6:29 AM

Nov 9 2018

javed.absar accepted D54142: [ARM] Cortex-M4 schedule.

LGTM. Thanks for this.

Nov 9 2018, 5:53 AM

Nov 6 2018

javed.absar added inline comments to D54142: [ARM] Cortex-M4 schedule.
Nov 6 2018, 3:46 AM

Oct 30 2018

javed.absar accepted D53319: Add support for AArch64 UDF instruction.
Oct 30 2018, 3:39 AM

Oct 29 2018

javed.absar added a comment to D53319: Add support for AArch64 UDF instruction.

Could you add assembler/disassembler tests for udf ?

Oct 29 2018, 3:06 AM

Oct 16 2018

javed.absar added inline comments to D53319: Add support for AArch64 UDF instruction.
Oct 16 2018, 3:47 AM

Oct 12 2018

javed.absar accepted D52764: [Intrinsic] Add llvm.minimum and llvm.maximum instrinsic functions.
Oct 12 2018, 1:21 AM

Oct 10 2018

javed.absar added inline comments to D51160: Adjust MIScheduler to use ProcResource counts.
Oct 10 2018, 1:39 PM

Oct 2 2018

javed.absar added inline comments to D52764: [Intrinsic] Add llvm.minimum and llvm.maximum instrinsic functions.
Oct 2 2018, 4:04 AM

Oct 1 2018

javed.absar added inline comments to D51429: [AArch64] Return Address Signing B Key Support.
Oct 1 2018, 8:30 AM

Sep 26 2018

javed.absar accepted D52551: [ARM] Allow execute only code on Cortex-m23.
Sep 26 2018, 8:02 AM
javed.absar added a comment to D52551: [ARM] Allow execute only code on Cortex-m23.

Looks like you forgot to add context (git diff -U9999)

Sep 26 2018, 7:44 AM
javed.absar accepted D52472: [AArch64] Refactor instructions that write PSTATE (NFCI).
Sep 26 2018, 7:31 AM

Sep 19 2018

javed.absar added inline comments to D52256: AArch64: Add FuseCryptoEOR fusion rules.
Sep 19 2018, 1:44 AM
javed.absar accepted D52255: MachineScheduler: Add -misched-print-dags flag.
Sep 19 2018, 1:33 AM

Sep 11 2018

javed.absar accepted D50507: [CodeGen][ARM] Coerce FP16 vectors to integer vectors when needed.
Sep 11 2018, 1:57 AM

Aug 29 2018

javed.absar added a comment to D51160: Adjust MIScheduler to use ProcResource counts.

Would it be possible to add a test case that highlights the problem you are solving e.g. take a processor that has multiple resources (e.g. two adders) and show that it now can use both resources in same cycle.

Aug 29 2018, 1:17 AM

Aug 9 2018

javed.absar accepted D50396: [ARM] Replace processor check with feature.
Aug 9 2018, 8:45 AM

Jul 25 2018

javed.absar added inline comments to D49786: Enable some pointer authentication instructions for aarch64 v8a targets.
Jul 25 2018, 7:29 AM
javed.absar added inline comments to D49791: [AArch64] - Generate pointer authentication instructions.
Jul 25 2018, 6:53 AM
javed.absar added a comment to D49793: [AArch64] - return address signing.

Maybe you can provide some more context to this patch (why you need this, or point to some document), if possible.

Jul 25 2018, 6:15 AM

Jul 23 2018

javed.absar accepted D49598: [SystemZ] Use tablegen loops in SchedModels.
Jul 23 2018, 3:02 PM
javed.absar added a comment to D49598: [SystemZ] Use tablegen loops in SchedModels.

Yes Jonas it is purely cosmetic. Sometimes maybe be useful for code maintenance to show that certain records/values are not-possible

Jul 23 2018, 8:54 AM
javed.absar added a comment to D49598: [SystemZ] Use tablegen loops in SchedModels.

Thanks for helping me out with TableGen coding, Javed!

But you have LSU, LSU2, LSU3, ... . The first one would have to change to LSU1

I have sofar tried to avoid LSU1, FXa1, so I did

foreach Num = ["", "2", "3", "4", "5"]

, which seems to work. I would think this is ok, or? Only drawback here is that now there are in the subtarget files a separate definition for the "implicit 1\
" in some places. Not sure which is better...

Compared to trunk, there are in the tablegen file some extra variants, like FXa5 in z14 file, but that did not seem to matter - it seems that the produced cla\
ng binary is identical to that of trunk.

Any suggestions most welcome!

Jul 23 2018, 6:35 AM

Jul 18 2018

javed.absar added a comment to D49286: TableGen : Fix tablegen grammar documentation. NFC..

ping!

Jul 18 2018, 6:11 AM

Jul 13 2018

javed.absar created D49286: TableGen : Fix tablegen grammar documentation. NFC..
Jul 13 2018, 3:57 AM

Jul 2 2018

javed.absar added inline comments to D48832: [ARM] ARMCodeGenPrepare backend pass.
Jul 2 2018, 12:15 PM
javed.absar added a comment to D48811: Fix disassembling ARM instructions as big-endian.

Is this applicable only for ARMv6 case? From the patch it does not seem so and so may be good to add cases for ARMv7 as well.

Jul 2 2018, 2:02 AM

Jun 29 2018

javed.absar accepted D48682: [MachineOutliner] Add always and never options to -enable-machine-outliner.

Thanks. LGTM.

Jun 29 2018, 1:13 AM

Jun 28 2018

Herald updated subscribers of D16829: An implementation of Swing Modulo Scheduling.
Jun 28 2018, 5:39 AM
javed.absar added inline comments to D48682: [MachineOutliner] Add always and never options to -enable-machine-outliner.
Jun 28 2018, 1:09 AM

Jun 14 2018

javed.absar accepted D48074: [ARM] Enable useAA() for the in-order Cortex-R52.
Jun 14 2018, 12:45 AM

Jun 13 2018

javed.absar added a comment to D48074: [ARM] Enable useAA() for the in-order Cortex-R52.

LGTM but will wait for others to comment as well before accepting

Jun 13 2018, 1:26 AM

Jun 11 2018

javed.absar added inline comments to D48013: TableGen/SearchableTables: Support more generic enums and tables.
Jun 11 2018, 4:18 PM
javed.absar added inline comments to D48013: TableGen/SearchableTables: Support more generic enums and tables.
Jun 11 2018, 3:21 PM
javed.absar added a comment to D48015: ARM,AArch64: Use generic tables instead of SearchableTable.

Probably good to mention that this patch relies on https://reviews.llvm.org/D48013

Jun 11 2018, 1:24 PM
javed.absar added a reviewer for D48013: TableGen/SearchableTables: Support more generic enums and tables: javed.absar.
Jun 11 2018, 1:22 PM
javed.absar added a comment to D48015: ARM,AArch64: Use generic tables instead of SearchableTable.

Its not clear to me why 'GenericTable' is more efficient/better than SearchableTable. Maybe you could give some background in the commit message about this. I implemented the ARMSystemRegister bit sometime ago and found SearchableTable quite useful and concise but perhaps GenericTable/Enum is even better.

Jun 11 2018, 7:09 AM

Jun 7 2018

javed.absar added inline comments to D47008: [SystemZ] Reimplent SchedModel IssueWidth and WriteRes/ReadAdvance mappings to operands.
Jun 7 2018, 9:00 AM
javed.absar added a comment to D47008: [SystemZ] Reimplent SchedModel IssueWidth and WriteRes/ReadAdvance mappings to operands.

but did not find a way to do this (I think that it didn't work to express a LSU#I SchedWrite). I guess the current above will have to do?

This will work.

Jun 7 2018, 8:28 AM
javed.absar added a reviewer for D47008: [SystemZ] Reimplent SchedModel IssueWidth and WriteRes/ReadAdvance mappings to operands: javed.absar.
Jun 7 2018, 3:38 AM
javed.absar added a comment to D46837: [MachineScheduler] Skip an implicit def of a super-reg added by regalloc in findDefIdx..

r334161 fixes this issue for SystemZ by fixing the backend per alternative (3) above.

Is there any interest for (1) or (2), or should I abandon them?

Jun 7 2018, 3:37 AM

Jun 6 2018

javed.absar added a reviewer for D46837: [MachineScheduler] Skip an implicit def of a super-reg added by regalloc in findDefIdx.: javed.absar.
Jun 6 2018, 11:12 PM

Jun 5 2018

javed.absar accepted D47712: [AArch64][SVE] Asm: Support for FADD, FMUL and FMAX immediate instructions..
Jun 5 2018, 5:30 AM

Jun 4 2018

javed.absar added inline comments to D47730: [SelectionDAG]Reduce masked data movement chains and memory access widths pt3.
Jun 4 2018, 2:08 PM · Restricted Project

May 31 2018

javed.absar added a comment to D47599: [UBSan] DO NOT COMMIT: precise UBSan checks experiment.

No need to review it, Javed. I uploaded it for sharing and history.

May 31 2018, 1:32 PM

May 30 2018

javed.absar accepted D47518: [AArch64][SVE] Asm: Support for FCPY immediate instructions..
May 30 2018, 3:28 PM
javed.absar added a comment to D47518: [AArch64][SVE] Asm: Support for FCPY immediate instructions..

Should the commit message be " Splat floating-point immediate value to SVE vector". Or may be i am wrong on this?

May 30 2018, 4:12 AM

May 29 2018

javed.absar accepted D47483: [AArch64][AsmParser] Fix segfault on illegal fpimm..
May 29 2018, 9:33 AM
javed.absar added a comment to D46884: [AArch64] Cortex-A55 scheduler model.

When I tried to test this patch, it showed some improvements on several benchmarks like Spec2000/2006.
But other benchmarks like dhrystone, commercial benchmark's sub workloads show performance degradation.

We need to improve this scheduler model & I would be happy to test updated patch.

Thanks.

May 29 2018, 1:27 AM

May 24 2018

javed.absar added inline comments to D47310: [AArch64][SVE] Asm: Support for ADD (immediate) instructions..
May 24 2018, 12:04 PM

May 23 2018

javed.absar added a comment to D47239: [InstCombine] Combine XOR and AES insructions on ARM/ARM64.

I am not an expert in encryption but how likely it is for 'key' to be zero ?
Other than that, LGTM

May 23 2018, 12:31 PM

May 20 2018

javed.absar added inline comments to D46695: [RFC] [Patch 1/3] Add a new class of predicates for variant scheduling classes..
May 20 2018, 9:21 AM

May 17 2018

javed.absar added inline comments to D47000: [AArch64] Use addAliasForDirective to support data directives.
May 17 2018, 1:54 AM

May 15 2018

javed.absar added a comment to D46884: [AArch64] Cortex-A55 scheduler model.

LGTM but then I wrote it originally so better to wait for comments from others.

May 15 2018, 9:09 AM
javed.absar added inline comments to D46870: [MachineScheduler] Don't enforce some hazard checks pre-RA..
May 15 2018, 5:08 AM

May 14 2018

javed.absar accepted D46777: [ARM] Back up R4 and LR if calling the stack probe function.
May 14 2018, 2:00 AM
javed.absar added a comment to D46777: [ARM] Back up R4 and LR if calling the stack probe function.

Separated the blocks, as requested.

May 14 2018, 1:37 AM
javed.absar added a comment to D46682: [AArch64][SVE] Asm: Support for contiguous PRF prefetch instructions..

Suggestion for commit message - "Add support and tests for contiguous Prefetch instructions different variants."
The problem i find sometimes with long title is that it it truncated.

May 14 2018, 1:35 AM

May 13 2018

javed.absar added inline comments to D46695: [RFC] [Patch 1/3] Add a new class of predicates for variant scheduling classes..
May 13 2018, 8:36 AM

May 12 2018

javed.absar added inline comments to D46777: [ARM] Back up R4 and LR if calling the stack probe function.
May 12 2018, 9:06 AM

May 11 2018

javed.absar added inline comments to D46701: [RFC][AArch64] Use the new MCSchedPredicate to rewrite a couple of predicates..
May 11 2018, 5:28 AM

May 10 2018

javed.absar added inline comments to D46695: [RFC] [Patch 1/3] Add a new class of predicates for variant scheduling classes..
May 10 2018, 3:22 PM
javed.absar added inline comments to D46695: [RFC] [Patch 1/3] Add a new class of predicates for variant scheduling classes..
May 10 2018, 3:12 PM
javed.absar added inline comments to D46701: [RFC][AArch64] Use the new MCSchedPredicate to rewrite a couple of predicates..
May 10 2018, 3:09 PM
javed.absar added reviewers for D46695: [RFC] [Patch 1/3] Add a new class of predicates for variant scheduling classes.: atrick, MatzeB, javed.absar.
May 10 2018, 12:32 PM
javed.absar added a comment to D46679: [AArch64][SVE] Asm: Support for structured LD2, LD3 and LD4 (scalar+scalar) load instructions..

Having discussed with Sander and Florian in detail I now agree it is better to add properly grouped Scheds later.

May 10 2018, 6:10 AM
javed.absar added a comment to D46679: [AArch64][SVE] Asm: Support for structured LD2, LD3 and LD4 (scalar+scalar) load instructions..

Hi Florian.
I would then suggest adding the following to AArch64Schedule.td and then simply assigning the appropriate Scheds.
Much less work and neater doing it now when the instruction implementation is being done.

May 10 2018, 4:01 AM
javed.absar added inline comments to D46679: [AArch64][SVE] Asm: Support for structured LD2, LD3 and LD4 (scalar+scalar) load instructions..
May 10 2018, 3:06 AM
javed.absar added a comment to D46682: [AArch64][SVE] Asm: Support for contiguous PRF prefetch instructions..

I might be good to put commit-message/description.

May 10 2018, 2:35 AM

May 9 2018

javed.absar added inline comments to D46591: [AArch64] Fix performPostLD1Combine to check for constant lane index..
May 9 2018, 4:42 AM

May 3 2018

javed.absar added a comment to D46356: [TableGen] Emit a fatal error on inconsistencies in resource units vs cycles..

Does FDIV use both the resources for 8 cycles? Writing [8,8] would imply that.

May 3 2018, 8:47 AM

May 2 2018

javed.absar added a comment to D46356: [TableGen] Emit a fatal error on inconsistencies in resource units vs cycles..

Ah! OK, I see. Thanks for the clarification.

May 2 2018, 8:42 AM
javed.absar added a comment to D46356: [TableGen] Emit a fatal error on inconsistencies in resource units vs cycles..

I think it'd be clearer if we could keep Btver2/Znver1 to the Res = [1] default tbh

Hm, not sure how I can do that without triggering the check for cases when the user erroneously specified [1] when they wanted to use the default (now []). Did I miss a possibility ?
This makes is no difference for the user, but allows more checking. Best of both worlds ? :)

May 2 2018, 8:06 AM
javed.absar added a comment to D46356: [TableGen] Emit a fatal error on inconsistencies in resource units vs cycles..

Thanks for this check.
If ResourceCycles is not specified then it should default to 1 . I believe most people write with that interpretation.
If ResourceCycles is specified for at least one resource, it makes sense from correctness POV that it be specified for all (even though it might get verbose at time).

May 2 2018, 7:35 AM
javed.absar added reviewers for D46356: [TableGen] Emit a fatal error on inconsistencies in resource units vs cycles.: MatzeB, atrick.
May 2 2018, 7:24 AM

May 1 2018

javed.absar added a comment to D46192: Script to match open Phabricator reviews with potential reviewers.

Hi Kristof. Thanks for this.

May 1 2018, 1:55 AM

Apr 30 2018

javed.absar added inline comments to D46273: [InstCombine, ARM] Convert vld1 to llvm load.
Apr 30 2018, 2:47 PM
javed.absar added reviewers for D46243: Move Schedule class to header file for allowing inheritance: MatzeB, javed.absar.
Apr 30 2018, 1:34 AM

Apr 27 2018

javed.absar accepted D46178: [SCEV] Reduce the number of invocation to non trivial getExact function.

Please rephrase this part of commit message as it is hard to read/understand - "And even if statistics is disable and code
related to it will be eliminated the invocation to getExact itself will not be eliminated because it may have side-effects like creation of new SCEVs".

Apr 27 2018, 2:30 AM
javed.absar added a comment to D46178: [SCEV] Reduce the number of invocation to non trivial getExact function.

AFAIU the correctness check would now get gated on STATS colelction and that may not be right. I would recommend separating the two.

Apr 27 2018, 1:25 AM

Apr 26 2018

javed.absar added inline comments to D46133: [InstCombine, ARM, AArch64] Convert table lookup to shuffle vector.
Apr 26 2018, 1:31 PM
javed.absar added inline comments to D46110: [IR] Do not assume that function pointers are aligned.
Apr 26 2018, 6:27 AM

Apr 25 2018

javed.absar added inline comments to D46046: [SCEV] Do not use induction in isKnownPredicate for simplification umax.
Apr 25 2018, 2:18 AM
javed.absar added inline comments to D46047: [SCEV] Introduce bulk umin creation utilities.
Apr 25 2018, 2:16 AM
javed.absar added a comment to D46046: [SCEV] Do not use induction in isKnownPredicate for simplification umax.

Would removing 'isKnownViaInduction' have any impact of the number of cases 'analyzeable by scev?

Apr 25 2018, 2:05 AM

Apr 24 2018

javed.absar accepted D45982: [TTI, AArch64] Add transpose shuffle kind.

LGTM. Probably wait a day before committing in case Renato/others have a comment/suggestion.

Apr 24 2018, 12:57 PM
javed.absar added inline comments to D45191: [LoopReroll] Rewrite induction variable rewriting..
Apr 24 2018, 9:30 AM

Apr 23 2018

javed.absar added inline comments to D45982: [TTI, AArch64] Add transpose shuffle kind.
Apr 23 2018, 2:28 PM
javed.absar added a comment to D45916: Enable MachineOutliner by default under -Oz for AArch64.

Could you please generate diff with -U999 to give more context to the patch. Thanks.

Apr 23 2018, 7:12 AM

Apr 20 2018

javed.absar added a comment to D45874: [LoopUnroll] Split out simplify code after Unroll into a new function. NFC.

Any test possible here?

Apr 20 2018, 5:39 AM
javed.absar added a comment to D45872: [DA] Enable -da-delinearize by default.

AFAIU this change would affect other targets. Probably best to add more reviewers (owners for other targets).

Apr 20 2018, 5:33 AM

Apr 19 2018

javed.absar added a comment to D45821: [AArch64] improve code generation of vectors smaller than 64 bit.

Thanks for this Sebastian. Overall, this definitely look good for vectorization.

Apr 19 2018, 2:37 PM

Apr 18 2018

javed.absar added inline comments to D42447: [LV][VPlan] Detect outer loops for explicit vectorization..
Apr 18 2018, 11:25 AM
javed.absar added a comment to D45690: [AArch64][SVE] Asm: Support for contiguous LD1 (scalar+scalar) load instructions..

Hi Sander.
Its good you mention 'patch [4/4] in a series' in commit message. But could you please also link them up by providing link to previous reviews etc.
Might be easy for tracking later.

Apr 18 2018, 6:08 AM

Apr 4 2018

javed.absar added a comment to D45229: [MI-sched] schedule following instruction latencies.

Hi Sebastian:
For the test case, the change looks good, though I am surprised the current scheduling algorithm does that (i.e. scheduling store just one cycle after load which definitely would result in stalls, especially for in-order processors). I am guessing the latency it is picking up is 1?

Apr 4 2018, 1:17 AM

Apr 3 2018

javed.absar added a comment to D45229: [MI-sched] schedule following instruction latencies.
Apr 3 2018, 11:43 PM
javed.absar added inline comments to D45189: [MachineOutliner][AArch64] Keep track of functions that use a red zone in AArch64MachineFunctionInfo and use that instead of checking for noredzone in the MachineOutliner.
Apr 3 2018, 1:49 AM

Mar 26 2018

javed.absar accepted D44834: [MachineScheduler] Add itinerary to schedcover.py. Make default work in the command line filter.
Mar 26 2018, 2:30 PM

Mar 25 2018

javed.absar accepted D44687: [SchedModel] Remove instregex entries that don't match any instructions (WIP).

LGTM

Mar 25 2018, 11:37 AM