javed.absar (Javed Absar)
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User Since
Mar 27 2015, 6:20 AM (120 w, 6 d)

Recent Activity

Today

javed.absar committed rL308607: [ARM] Simplify ExpandPseudoInst. NFC..
[ARM] Simplify ExpandPseudoInst. NFC.
Thu, Jul 20, 5:36 AM
javed.absar closed D35626: [ARM] Simplify ExpandPseudoInst. NFC. by committing rL308607: [ARM] Simplify ExpandPseudoInst. NFC..
Thu, Jul 20, 5:36 AM

Yesterday

javed.absar created D35626: [ARM] Simplify ExpandPseudoInst. NFC..
Wed, Jul 19, 8:56 AM
javed.absar committed rL308456: [ARM] Unify handling of M-Class system registers.
[ARM] Unify handling of M-Class system registers
Wed, Jul 19, 5:59 AM
javed.absar closed D35209: [ARM] Unify handling of M-Class system registers by committing rL308456: [ARM] Unify handling of M-Class system registers.
Wed, Jul 19, 5:58 AM

Tue, Jul 18

javed.absar added a comment to D35209: [ARM] Unify handling of M-Class system registers.

Ping - @t.p.northover @olista01 @john.brawn
I think all changes requested are done and the initial idea of getting everything in one place etc is met.

Tue, Jul 18, 3:28 AM
javed.absar committed rL308291: [ARM|CodeGen] Improve the code in FastISel.
[ARM|CodeGen] Improve the code in FastISel
Tue, Jul 18, 3:20 AM
javed.absar closed D35494: [ARM|CodeGen] Improve the code in FastISel by committing rL308291: [ARM|CodeGen] Improve the code in FastISel.
Tue, Jul 18, 3:20 AM
javed.absar added a comment to D35494: [ARM|CodeGen] Improve the code in FastISel.

Thanks Tim. Will fix the commented code and commit.

Tue, Jul 18, 1:22 AM

Mon, Jul 17

javed.absar created D35494: [ARM|CodeGen] Improve the code in FastISel.
Mon, Jul 17, 10:40 AM
javed.absar committed rL308173: [CodeGen] Add begin-end iterators to MachineInstr.
[CodeGen] Add begin-end iterators to MachineInstr
Mon, Jul 17, 6:16 AM
javed.absar closed D35419: [CodeGen] Add begin-end iterators to MachineInstr by committing rL308173: [CodeGen] Add begin-end iterators to MachineInstr.
Mon, Jul 17, 6:15 AM
javed.absar updated the diff for D35209: [ARM] Unify handling of M-Class system registers.

Thanks Tim/others for the suggestions. Updated, using 'Requires' , FeatureBits and factoring out common functions. Is much more compact and unified now, as I set out to do.

Mon, Jul 17, 3:39 AM
javed.absar added a comment to D35419: [CodeGen] Add begin-end iterators to MachineInstr.

Thanks Diana.

Mon, Jul 17, 1:34 AM
javed.absar added inline comments to D35293: AMD znver1 Initial Scheduler model.
Mon, Jul 17, 1:32 AM

Sat, Jul 15

javed.absar updated the diff for D35419: [CodeGen] Add begin-end iterators to MachineInstr.
Sat, Jul 15, 2:04 AM

Fri, Jul 14

javed.absar added a comment to D35419: [CodeGen] Add begin-end iterators to MachineInstr.

Ok, I see that now too. Will use MI->operands() as suggested, as that will suffice.

Fri, Jul 14, 3:26 PM
javed.absar created D35419: [CodeGen] Add begin-end iterators to MachineInstr.
Fri, Jul 14, 8:35 AM
javed.absar added a reviewer for D35229: [CodeGen] Add support for instruction clusters: atrick.
Fri, Jul 14, 3:55 AM
javed.absar added inline comments to D35229: [CodeGen] Add support for instruction clusters.
Fri, Jul 14, 3:55 AM
javed.absar updated the diff for D35209: [ARM] Unify handling of M-Class system registers.

I have re-implemented using SearchableTable which improves the code quality immensely (great suggestion by Oliver). I have also create a Utils sub-directory (and ARMUtils library) that allows utility functions such as generated by SearchableTable to be incorporated into both CodeGen and others. seamlessly.

Fri, Jul 14, 3:31 AM

Thu, Jul 13

javed.absar committed rL307897: [ARM] Tidy up and organise better ARM.td. NFC..
[ARM] Tidy up and organise better ARM.td. NFC.
Thu, Jul 13, 3:25 AM
javed.absar closed D35248: [ARM] Tidy up and organise better ARM.td. NFC. by committing rL307897: [ARM] Tidy up and organise better ARM.td. NFC..
Thu, Jul 13, 3:25 AM
javed.absar updated the diff for D35248: [ARM] Tidy up and organise better ARM.td. NFC..
Thu, Jul 13, 1:21 AM

Wed, Jul 12

javed.absar added inline comments to D35229: [CodeGen] Add support for instruction clusters.
Wed, Jul 12, 3:27 PM
javed.absar added a comment to D35248: [ARM] Tidy up and organise better ARM.td. NFC..

Thanks Florian.
Sure, will make the changes and wait till tomorrow before committing, in case Renato or Diana have further comments.

Wed, Jul 12, 2:57 PM
javed.absar added a comment to D35248: [ARM] Tidy up and organise better ARM.td. NFC..

Ping! Renato, Diana, Florian ?

Wed, Jul 12, 2:43 PM
javed.absar updated the diff for D35248: [ARM] Tidy up and organise better ARM.td. NFC..

Hi Florian:

Wed, Jul 12, 9:27 AM
javed.absar added inline comments to D35293: AMD znver1 Initial Scheduler model.
Wed, Jul 12, 1:40 AM

Tue, Jul 11

javed.absar added a comment to D35248: [ARM] Tidy up and organise better ARM.td. NFC..

Thanks Florian. I will fix the indents where I missed out.

Tue, Jul 11, 12:05 PM
javed.absar added a reviewer for D35248: [ARM] Tidy up and organise better ARM.td. NFC.: fhahn.
Tue, Jul 11, 10:50 AM
javed.absar created D35248: [ARM] Tidy up and organise better ARM.td. NFC..
Tue, Jul 11, 4:56 AM
javed.absar added inline comments to D35228: [TableGen] Add support for instruction clusters.
Tue, Jul 11, 1:52 AM

Mon, Jul 10

javed.absar created D35209: [ARM] Unify handling of M-Class system registers.
Mon, Jul 10, 10:04 AM
javed.absar committed rL307531: [ARM] Tidy up ARMBaseRegisterInfo implementation. NFC.
[ARM] Tidy up ARMBaseRegisterInfo implementation. NFC
Mon, Jul 10, 3:43 AM
javed.absar closed D35116: [ARM] Tidy up ARMBaseRegisterInfo implementation. NFC by committing rL307531: [ARM] Tidy up ARMBaseRegisterInfo implementation. NFC.
Mon, Jul 10, 3:43 AM

Fri, Jul 7

javed.absar added a comment to D35116: [ARM] Tidy up ARMBaseRegisterInfo implementation. NFC.

Good catch. Thanks. Will fix these and commit.

Fri, Jul 7, 8:32 AM
javed.absar retitled D35116: [ARM] Tidy up ARMBaseRegisterInfo implementation. NFC from [ARM] Tidy up ARMBaseRegisterInfo implementation to [ARM] Tidy up ARMBaseRegisterInfo implementation. NFC.
Fri, Jul 7, 5:22 AM
javed.absar added a comment to D35116: [ARM] Tidy up ARMBaseRegisterInfo implementation. NFC.

Thanks Florian. I will wait a bit for Renato/Diana to comment before committing, in case they have more comments/suggestions.

Fri, Jul 7, 4:25 AM
javed.absar created D35116: [ARM] Tidy up ARMBaseRegisterInfo implementation. NFC.
Fri, Jul 7, 3:54 AM

Tue, Jul 4

javed.absar added inline comments to D34973: AMDGPU: Add macro fusion schedule DAG mutation.
Tue, Jul 4, 1:27 AM
javed.absar added inline comments to D34958: [AArch64] Add AArch64Subtarget::isFusion function..
Tue, Jul 4, 1:10 AM

Wed, Jun 28

javed.absar added inline comments to D34682: [Triple] Add isThumb and isARM functions NFCI..
Wed, Jun 28, 6:06 AM
javed.absar added a comment to D34398: [ARM] Improve if-conversion for M-class CPUs without branch predictors.

scheduling part LGTM now

Wed, Jun 28, 3:17 AM

Tue, Jun 27

javed.absar committed rL306424: Fix incorrect comment in machine-scheduler.
Fix incorrect comment in machine-scheduler
Tue, Jun 27, 9:50 AM
javed.absar closed D34675: Fix incorrect comment in machine-scheduler by committing rL306424: Fix incorrect comment in machine-scheduler.
Tue, Jun 27, 9:50 AM
javed.absar created D34675: Fix incorrect comment in machine-scheduler.
Tue, Jun 27, 3:04 AM

Thu, Jun 22

javed.absar abandoned D30326: [MS-ABI] Allow #pragma section to choose for ZI data.

Abandoning as there is a separate pragma clang section implementation now.

Thu, Jun 22, 9:41 AM
javed.absar accepted D34142: [ARM] Add macro fusion for AES instructions..
Thu, Jun 22, 1:15 AM

Wed, Jun 21

javed.absar added a comment to D34142: [ARM] Add macro fusion for AES instructions..

LGTM but I will wait a day before accepting to allow time for others to comment too, just in case.
Thanks for this.

Wed, Jun 21, 3:45 AM
javed.absar committed rL305887: Use range-loop in machine-scheduler. NFCI..
Use range-loop in machine-scheduler. NFCI.
Wed, Jun 21, 2:10 AM
javed.absar closed D34320: Use range-loop in machine-scheduler. NFCI. by committing rL305887: Use range-loop in machine-scheduler. NFCI..
Wed, Jun 21, 2:10 AM

Jun 20 2017

javed.absar updated the diff for D34320: Use range-loop in machine-scheduler. NFCI..

Thanks Matthias for review. Please find the changes as requested.

Jun 20 2017, 9:07 AM
javed.absar added inline comments to D34398: [ARM] Improve if-conversion for M-class CPUs without branch predictors.
Jun 20 2017, 7:04 AM

Jun 19 2017

javed.absar updated the summary of D34320: Use range-loop in machine-scheduler. NFCI..
Jun 19 2017, 3:09 AM
javed.absar retitled D34320: Use range-loop in machine-scheduler. NFCI. from Use range-loop in machine-scheduler to Use range-loop in machine-scheduler. NFCI..
Jun 19 2017, 3:05 AM

Jun 18 2017

javed.absar added a reviewer for D34320: Use range-loop in machine-scheduler. NFCI.: chandlerc.
Jun 18 2017, 4:09 AM

Jun 17 2017

javed.absar created D34320: Use range-loop in machine-scheduler. NFCI..
Jun 17 2017, 2:28 PM

Jun 14 2017

javed.absar added inline comments to D34142: [ARM] Add macro fusion for AES instructions..
Jun 14 2017, 9:41 AM

Jun 13 2017

javed.absar added a comment to D34142: [ARM] Add macro fusion for AES instructions..

Thanks Florian for this. Some comments below -

Jun 13 2017, 1:20 PM
javed.absar added a comment to D33836: [AArch64] Enable FeatureFuseAES for the generic processor model..

LGTM. @sbaranga are you also ok with this?

Jun 13 2017, 7:21 AM
javed.absar accepted D34139: [ARM] Add scheduling classes for VFNM[AS].

Thanks Oliver for fixing it.

Jun 13 2017, 5:36 AM

Jun 9 2017

javed.absar committed rL305078: [ARM] Custom machine-scheduler. NFCI..
[ARM] Custom machine-scheduler. NFCI.
Jun 9 2017, 7:07 AM
javed.absar closed D34039: [ARM] Custom machine-scheduler. NFCI. by committing rL305078: [ARM] Custom machine-scheduler. NFCI..
Jun 9 2017, 7:07 AM

Jun 8 2017

javed.absar accepted D34040: [ARM] Add scheduling info for VFMS.
Jun 8 2017, 12:04 PM
javed.absar added a comment to D34040: [ARM] Add scheduling info for VFMS.

Thanks Oliver for adding the missing sched defs. I am surprised there was assertion failures for missing scheds as default behaviour of machine scheduler used to be 'to-silently-ignore'. Anyways, that's a separate issue. Still good to have complete defs.

Jun 8 2017, 12:04 PM
javed.absar created D34039: [ARM] Custom machine-scheduler. NFCI..
Jun 8 2017, 9:19 AM
javed.absar added inline comments to D34028: [Bitcode] Add thumb-mode to target-features in metadata loader..
Jun 8 2017, 5:44 AM

Jun 7 2017

javed.absar added inline comments to D33818: [ScheduleDAG] Don't schedule node with physical register interference.
Jun 7 2017, 4:06 PM
javed.absar added inline comments to D33203: Add scheduler classes to integer/float horizontal operations.
Jun 7 2017, 3:10 AM
javed.absar committed rL304889: [ARM] Fix Neon vector type alignment to 64-bit.
[ARM] Fix Neon vector type alignment to 64-bit
Jun 7 2017, 3:02 AM
javed.absar closed D33786: [ARM] Fix Neon vector type alignment to 64-bit by committing rL304889: [ARM] Fix Neon vector type alignment to 64-bit.
Jun 7 2017, 3:02 AM

Jun 6 2017

javed.absar added a comment to D33786: [ARM] Fix Neon vector type alignment to 64-bit.

Hi Renato:
I have made changes as suggested (unless I got somethings wrong).

  1. Now, except for android, AAPCS => 64-bit alignment
  2. The fix relies only on the triple for I am not sure if 'right cc1' flag test is needed.
  3. Added gnueabi and FreeBSD as suggested.

Please have a look. Thanks.
--Javed

Jun 6 2017, 9:33 AM
javed.absar updated the diff for D33786: [ARM] Fix Neon vector type alignment to 64-bit.
Jun 6 2017, 9:28 AM
javed.absar added a comment to D33836: [AArch64] Enable FeatureFuseAES for the generic processor model..

My two cents. I think this is likely to give gains where pipeline leverages it, and unlikely to cause regressions otherwise.
Joel Jones mentioned checking performance on ThuderX so we should probably wait for him to come back on it.

Jun 6 2017, 8:55 AM
javed.absar added inline comments to D33897: [X86][SandyBridge,Haswell] Updating information on each instruction in HSW and SNB about latency, number of uOps and used ports.
Jun 6 2017, 2:43 AM
javed.absar added a comment to D33924: [llvm] Remove double semicolons.
Jun 6 2017, 1:26 AM

Jun 5 2017

javed.absar committed rL304706: Move ARM specific test to ELF/ARM dir.
Move ARM specific test to ELF/ARM dir
Jun 5 2017, 3:53 AM
javed.absar committed rL304705: Add support for #pragma clang section.
Add support for #pragma clang section
Jun 5 2017, 3:12 AM
javed.absar closed D33412: Add support for #pragma clang section by committing rL304705: Add support for #pragma clang section.
Jun 5 2017, 3:12 AM
javed.absar committed rL304704: Add support for #pragma clang section.
Add support for #pragma clang section
Jun 5 2017, 3:09 AM
javed.absar closed D33413: Add support for #pragma clang section by committing rL304704: Add support for #pragma clang section.
Jun 5 2017, 3:09 AM
javed.absar added a comment to D33786: [ARM] Fix Neon vector type alignment to 64-bit.

Hi Renato. Please could you have a look at this. I had a LGTM from @rovka and @srhines but need final one from you.
Thanks, Javed.

Jun 5 2017, 1:22 AM

Jun 2 2017

javed.absar added inline comments to D33836: [AArch64] Enable FeatureFuseAES for the generic processor model..
Jun 2 2017, 2:49 PM
javed.absar committed rL304530: [ARM] Cortex-A57 scheduling model for ARM backend (AArch32).
[ARM] Cortex-A57 scheduling model for ARM backend (AArch32)
Jun 2 2017, 1:53 AM
javed.absar closed D28152: Cortex-A57 scheduling model for ARM backend (AArch32) by committing rL304530: [ARM] Cortex-A57 scheduling model for ARM backend (AArch32).
Jun 2 2017, 1:53 AM
javed.absar added a comment to D33786: [ARM] Fix Neon vector type alignment to 64-bit.

Thanks Stephen.
Vedant, Diana : Does this look ok to you as well?

Jun 2 2017, 1:36 AM

Jun 1 2017

javed.absar added inline comments to D33786: [ARM] Fix Neon vector type alignment to 64-bit.
Jun 1 2017, 1:01 PM
javed.absar created D33786: [ARM] Fix Neon vector type alignment to 64-bit.
Jun 1 2017, 10:09 AM
javed.absar added a comment to D28152: Cortex-A57 scheduling model for ARM backend (AArch32).

Hi Andrew:

Jun 1 2017, 8:11 AM
javed.absar added inline comments to D33203: Add scheduler classes to integer/float horizontal operations.
Jun 1 2017, 6:10 AM

May 31 2017

javed.absar added inline comments to D33719: Add _Float16 as a C/C++ source language type.
May 31 2017, 7:11 AM
javed.absar added a comment to D33721: [ARM] Add support for target("arm") and target("thumb")..
May 31 2017, 6:41 AM
javed.absar accepted D28152: Cortex-A57 scheduling model for ARM backend (AArch32).

Approving as all actions requested are resolved and the overall geomean is positive. Thanks for this work!

May 31 2017, 5:37 AM
javed.absar updated the diff for D33412: Add support for #pragma clang section.

Thanks Roger for the review and the suggestion to add documentation in LanguageExtensions.rst. I have done so now.
--Javed

May 31 2017, 4:07 AM

May 30 2017

javed.absar committed rL304220: Reverting Neon vector type 64-alignment fix.
Reverting Neon vector type 64-alignment fix
May 30 2017, 10:10 AM
javed.absar committed rL304210: Fix issue with test that caused bildbot failure.
Fix issue with test that caused bildbot failure
May 30 2017, 6:34 AM
javed.absar added a comment to D33627: Fix Crashes when 'AttributeList::get'ing with an ArrayRef<AttributeList> where all pImpl are null.

No problem. Please have a look at http://llvm.org/docs/Phabricator.html (sec. Requesting a review...). Basically, 'git diff -U9999 your-branch' will create a patch with more context.

May 30 2017, 4:11 AM
javed.absar committed rL304201: [ARM] Fix Neon vector type alignment to 64-bit.
[ARM] Fix Neon vector type alignment to 64-bit
May 30 2017, 3:12 AM
javed.absar closed D33205: ARM] Fix Neon vector type alignment to 64-bit by committing rL304201: [ARM] Fix Neon vector type alignment to 64-bit.
May 30 2017, 3:12 AM