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javed.absar (Javed Absar)
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User Since
Mar 27 2015, 6:20 AM (212 w, 5 d)

Recent Activity

Yesterday

javed.absar updated the diff for D60485: [AArch64] Add support for MTE intrinsics.

Hi Tim:
Have made the changes as suggested. Please have a look.

Tue, Apr 23, 12:10 PM
javed.absar committed rG1cdc3dbc5892: [AArch64] Add support for MTE intrinsics (authored by javed.absar).
[AArch64] Add support for MTE intrinsics
Tue, Apr 23, 2:38 AM
javed.absar committed rL358963: [AArch64] Add support for MTE intrinsics.
[AArch64] Add support for MTE intrinsics
Tue, Apr 23, 2:38 AM
javed.absar closed D60486: [AArch64] Add support for MTE intrinsics.
Tue, Apr 23, 2:38 AM · Restricted Project

Mon, Apr 15

javed.absar added a reviewer for D60485: [AArch64] Add support for MTE intrinsics: t.p.northover.
Mon, Apr 15, 3:45 AM
javed.absar added inline comments to D60485: [AArch64] Add support for MTE intrinsics.
Mon, Apr 15, 3:41 AM
javed.absar updated the diff for D60485: [AArch64] Add support for MTE intrinsics.

Tests merged as suggested.

Mon, Apr 15, 2:39 AM
javed.absar added a comment to D60486: [AArch64] Add support for MTE intrinsics.

Fixed as suggested

Mon, Apr 15, 2:37 AM · Restricted Project
javed.absar updated the diff for D60486: [AArch64] Add support for MTE intrinsics.
Mon, Apr 15, 2:37 AM · Restricted Project

Fri, Apr 12

javed.absar accepted D60559: [TableGen] Include schedule model name in diagnostic..
Fri, Apr 12, 5:39 AM · Restricted Project

Thu, Apr 11

javed.absar added inline comments to D60559: [TableGen] Include schedule model name in diagnostic..
Thu, Apr 11, 2:14 PM · Restricted Project

Wed, Apr 10

javed.absar accepted D60367: [TableGen] Introduce !listsplat 'binary' operator.
Wed, Apr 10, 10:46 AM · Restricted Project
javed.absar accepted D60212: [AArch64] Add lowering pattern for scalar fp16 facge and facgt.
Wed, Apr 10, 12:15 AM · Restricted Project

Tue, Apr 9

javed.absar added a comment to D60367: [TableGen] Introduce !listsplat 'binary' operator.

Thanks for this. Its good you show a use-case but probably the use case can be a separate commit.

Tue, Apr 9, 2:34 PM · Restricted Project
javed.absar updated the summary of D60485: [AArch64] Add support for MTE intrinsics.
Tue, Apr 9, 2:02 PM
javed.absar created D60486: [AArch64] Add support for MTE intrinsics.
Tue, Apr 9, 1:59 PM · Restricted Project
javed.absar updated the summary of D60485: [AArch64] Add support for MTE intrinsics.
Tue, Apr 9, 1:47 PM
javed.absar created D60485: [AArch64] Add support for MTE intrinsics.
Tue, Apr 9, 1:47 PM

Wed, Apr 3

javed.absar added inline comments to D60212: [AArch64] Add lowering pattern for scalar fp16 facge and facgt.
Wed, Apr 3, 10:06 PM · Restricted Project
javed.absar committed rG5820db93c925: [AArch64] Update v8.5a MTE LDG/STG instructions (authored by javed.absar).
[AArch64] Update v8.5a MTE LDG/STG instructions
Wed, Apr 3, 7:12 AM
javed.absar committed rL357583: [AArch64] Update v8.5a MTE LDG/STG instructions.
[AArch64] Update v8.5a MTE LDG/STG instructions
Wed, Apr 3, 7:12 AM
javed.absar closed D60188: [AArch64] Update v8.5a MTE instructions.
Wed, Apr 3, 7:12 AM · Restricted Project
javed.absar created D60188: [AArch64] Update v8.5a MTE instructions.
Wed, Apr 3, 2:44 AM · Restricted Project

Mon, Apr 1

javed.absar accepted D60065: [AArch64] Add v8.5-a Memory Tagging STZGM instruction.
Mon, Apr 1, 7:24 AM · Restricted Project
javed.absar accepted D60064: [AArch64] Add v8.5-a Memory Tagging STGM/LDGM instructions.
Mon, Apr 1, 7:24 AM · Restricted Project
javed.absar accepted D60063: [AArch64] Add v8.5-a Memory Tagging GMID_EL1 register.

LGTM , except for a small nitpick.

Mon, Apr 1, 7:22 AM · Restricted Project

Thu, Mar 28

javed.absar added a reviewer for D59879: [ARM][CMSE] Add commandline option and feature macro: snidertm.
Thu, Mar 28, 2:47 PM · Restricted Project

Wed, Mar 27

javed.absar updated the summary of D59888: [ARM][CMSE] Add cmse intrinsics for TT instructions.
Wed, Mar 27, 9:27 AM
javed.absar updated the summary of D59888: [ARM][CMSE] Add cmse intrinsics for TT instructions.
Wed, Mar 27, 9:27 AM
javed.absar created D59888: [ARM][CMSE] Add cmse intrinsics for TT instructions.
Wed, Mar 27, 9:27 AM
javed.absar created D59879: [ARM][CMSE] Add commandline option and feature macro.
Wed, Mar 27, 7:07 AM · Restricted Project

Tue, Mar 26

javed.absar committed rGc85cb2fb5d75: [TableGen] Let list elements have a trailing comma (authored by javed.absar).
[TableGen] Let list elements have a trailing comma
Tue, Mar 26, 4:17 AM
javed.absar committed rL356986: [TableGen] Let list elements have a trailing comma.
[TableGen] Let list elements have a trailing comma
Tue, Mar 26, 4:16 AM
javed.absar closed D59247: [TableGen] Let list elements have a trailing comma.
Tue, Mar 26, 4:16 AM · Restricted Project
javed.absar committed rG33888ff66b19: [TableGen] Give meaningful msg for def use in multiclass (authored by javed.absar).
[TableGen] Give meaningful msg for def use in multiclass
Tue, Mar 26, 3:50 AM
javed.absar committed rL356985: [TableGen] Give meaningful msg for def use in multiclass.
[TableGen] Give meaningful msg for def use in multiclass
Tue, Mar 26, 3:47 AM
javed.absar closed D59294: [TableGen] Give meaningful msg for def use in multiclass.
Tue, Mar 26, 3:47 AM · Restricted Project

Mar 14 2019

javed.absar added a comment to D59247: [TableGen] Let list elements have a trailing comma.

ping!

Mar 14 2019, 4:38 AM · Restricted Project
javed.absar added a comment to D59294: [TableGen] Give meaningful msg for def use in multiclass.

ping!

Mar 14 2019, 4:38 AM · Restricted Project

Mar 13 2019

javed.absar created D59294: [TableGen] Give meaningful msg for def use in multiclass.
Mar 13 2019, 4:56 AM · Restricted Project

Mar 12 2019

javed.absar created D59247: [TableGen] Let list elements have a trailing comma.
Mar 12 2019, 4:28 AM · Restricted Project

Mar 5 2019

javed.absar committed rG34d3b80dbab7: TableGen: Allow lists to be concatenated through '#' (authored by javed.absar).
TableGen: Allow lists to be concatenated through '#'
Mar 5 2019, 9:16 AM
javed.absar committed rL355414: TableGen: Allow lists to be concatenated through '#'.
TableGen: Allow lists to be concatenated through '#'
Mar 5 2019, 9:15 AM
javed.absar closed D58895: [TableGen] Allow lists to be concatenated through '#'.
Mar 5 2019, 9:15 AM · Restricted Project

Jan 25 2019

javed.absar committed rL352212: [TblGen][NFC] Fix documentation formatting.
[TblGen][NFC] Fix documentation formatting
Jan 25 2019, 8:18 AM
javed.absar committed rL352185: [TblGen] Extend !if semantics through new feature !cond.
[TblGen] Extend !if semantics through new feature !cond
Jan 25 2019, 2:27 AM
javed.absar closed D55758: [TableGen] : Extend !if semantics through new language feature !ifs.
Jan 25 2019, 2:27 AM

Jan 24 2019

javed.absar added a comment to D55758: [TableGen] : Extend !if semantics through new language feature !ifs.

Ping!

Jan 24 2019, 9:10 AM

Jan 22 2019

javed.absar updated the diff for D55758: [TableGen] : Extend !if semantics through new language feature !ifs.

Added BNF grammer for !cond as suggested .

Jan 22 2019, 9:16 AM

Jan 16 2019

javed.absar added a comment to D55758: [TableGen] : Extend !if semantics through new language feature !ifs.

Hi all:
I have made the changes as requested. That is, removed explicit 'default' while sticking to overall syntax as before. I found that removing default in fact simplifies the implementation somewhat. Also, have split the tests to cleaner separate ones.

Jan 16 2019, 3:18 AM
javed.absar updated the diff for D55758: [TableGen] : Extend !if semantics through new language feature !ifs.
Jan 16 2019, 3:14 AM

Jan 3 2019

javed.absar added a comment to D55758: [TableGen] : Extend !if semantics through new language feature !ifs.

Hi Hal/Others:

I have changed the syntax from !ifs to '!cond' now, while retaining the others parts from original !ifs (instead of from LISP). Please let me know if changes are ok with you.

Thanks

Jan 3 2019, 1:38 AM

Dec 24 2018

javed.absar updated the diff for D55758: [TableGen] : Extend !if semantics through new language feature !ifs.

Changes based on review comments. The new operator is now called '!cond', and 'default' must be the last clause.

Dec 24 2018, 6:52 AM

Dec 21 2018

javed.absar added inline comments to D56003: [RFC] [CFE] Allocatable Global Register Variables for ARM.
Dec 21 2018, 9:25 AM
javed.absar added a comment to D56007: [AArch64] Add command-line option for Execution and Data Prediction Instructions.

LGTM but will wait for a while to allow others comment as well, if necessary.

Dec 21 2018, 8:41 AM

Dec 19 2018

javed.absar added a comment to D55758: [TableGen] : Extend !if semantics through new language feature !ifs.
Dec 19 2018, 2:27 AM

Dec 18 2018

javed.absar added reviewers for D55758: [TableGen] : Extend !if semantics through new language feature !ifs: tra, arsenm.
Dec 18 2018, 2:45 AM

Dec 17 2018

javed.absar added a reviewer for D55758: [TableGen] : Extend !if semantics through new language feature !ifs: simon_tatham.
Dec 17 2018, 5:41 AM
javed.absar added inline comments to D55758: [TableGen] : Extend !if semantics through new language feature !ifs.
Dec 17 2018, 5:37 AM
javed.absar updated the summary of D55758: [TableGen] : Extend !if semantics through new language feature !ifs.
Dec 17 2018, 1:55 AM
javed.absar created D55758: [TableGen] : Extend !if semantics through new language feature !ifs.
Dec 17 2018, 1:54 AM

Dec 10 2018

javed.absar accepted D55509: [NFC][AArch64] Remove duplicate Arch list in target parser tests..

LGTM

Dec 10 2018, 6:29 AM

Nov 9 2018

javed.absar accepted D54142: [ARM] Cortex-M4 schedule.

LGTM. Thanks for this.

Nov 9 2018, 5:53 AM

Nov 6 2018

javed.absar added inline comments to D54142: [ARM] Cortex-M4 schedule.
Nov 6 2018, 3:46 AM

Oct 30 2018

javed.absar accepted D53319: Add support for AArch64 UDF instruction.
Oct 30 2018, 3:39 AM

Oct 29 2018

javed.absar added a comment to D53319: Add support for AArch64 UDF instruction.

Could you add assembler/disassembler tests for udf ?

Oct 29 2018, 3:06 AM

Oct 16 2018

javed.absar added inline comments to D53319: Add support for AArch64 UDF instruction.
Oct 16 2018, 3:47 AM

Oct 12 2018

javed.absar accepted D52764: [Intrinsic] Add llvm.minimum and llvm.maximum instrinsic functions.
Oct 12 2018, 1:21 AM

Oct 10 2018

javed.absar added inline comments to D51160: Adjust MIScheduler to use ProcResource counts.
Oct 10 2018, 1:39 PM · Restricted Project

Oct 2 2018

javed.absar added inline comments to D52764: [Intrinsic] Add llvm.minimum and llvm.maximum instrinsic functions.
Oct 2 2018, 4:04 AM

Oct 1 2018

javed.absar added inline comments to D51429: [AArch64] Return Address Signing B Key Support.
Oct 1 2018, 8:30 AM

Sep 26 2018

javed.absar accepted D52551: [ARM] Allow execute only code on Cortex-m23.
Sep 26 2018, 8:02 AM
javed.absar added a comment to D52551: [ARM] Allow execute only code on Cortex-m23.

Looks like you forgot to add context (git diff -U9999)

Sep 26 2018, 7:44 AM
javed.absar accepted D52472: [AArch64] Refactor instructions that write PSTATE (NFCI).
Sep 26 2018, 7:31 AM

Sep 19 2018

javed.absar added inline comments to D52256: AArch64: Add FuseCryptoEOR fusion rules.
Sep 19 2018, 1:44 AM
javed.absar accepted D52255: MachineScheduler: Add -misched-print-dags flag.
Sep 19 2018, 1:33 AM

Sep 11 2018

javed.absar accepted D50507: [CodeGen][ARM] Coerce FP16 vectors to integer vectors when needed.
Sep 11 2018, 1:57 AM

Aug 29 2018

javed.absar added a comment to D51160: Adjust MIScheduler to use ProcResource counts.

Would it be possible to add a test case that highlights the problem you are solving e.g. take a processor that has multiple resources (e.g. two adders) and show that it now can use both resources in same cycle.

Aug 29 2018, 1:17 AM · Restricted Project

Aug 9 2018

javed.absar accepted D50396: [ARM] Replace processor check with feature.
Aug 9 2018, 8:45 AM

Jul 25 2018

javed.absar added inline comments to D49786: Enable some pointer authentication instructions for aarch64 v8a targets.
Jul 25 2018, 7:29 AM
javed.absar added inline comments to D49791: [AArch64] - Generate pointer authentication instructions.
Jul 25 2018, 6:53 AM
javed.absar added a comment to D49793: [AArch64] - return address signing.

Maybe you can provide some more context to this patch (why you need this, or point to some document), if possible.

Jul 25 2018, 6:15 AM

Jul 23 2018

javed.absar accepted D49598: [SystemZ] Use tablegen loops in SchedModels.
Jul 23 2018, 3:02 PM
javed.absar added a comment to D49598: [SystemZ] Use tablegen loops in SchedModels.

Yes Jonas it is purely cosmetic. Sometimes maybe be useful for code maintenance to show that certain records/values are not-possible

Jul 23 2018, 8:54 AM
javed.absar added a comment to D49598: [SystemZ] Use tablegen loops in SchedModels.

Thanks for helping me out with TableGen coding, Javed!

But you have LSU, LSU2, LSU3, ... . The first one would have to change to LSU1

I have sofar tried to avoid LSU1, FXa1, so I did

foreach Num = ["", "2", "3", "4", "5"]

, which seems to work. I would think this is ok, or? Only drawback here is that now there are in the subtarget files a separate definition for the "implicit 1\
" in some places. Not sure which is better...

Compared to trunk, there are in the tablegen file some extra variants, like FXa5 in z14 file, but that did not seem to matter - it seems that the produced cla\
ng binary is identical to that of trunk.

Any suggestions most welcome!

Jul 23 2018, 6:35 AM

Jul 18 2018

javed.absar added a comment to D49286: TableGen : Fix tablegen grammar documentation. NFC..

ping!

Jul 18 2018, 6:11 AM

Jul 13 2018

javed.absar created D49286: TableGen : Fix tablegen grammar documentation. NFC..
Jul 13 2018, 3:57 AM

Jul 2 2018

javed.absar added inline comments to D48832: [ARM] ARMCodeGenPrepare backend pass.
Jul 2 2018, 12:15 PM
javed.absar added a comment to D48811: Fix disassembling ARM instructions as big-endian.

Is this applicable only for ARMv6 case? From the patch it does not seem so and so may be good to add cases for ARMv7 as well.

Jul 2 2018, 2:02 AM

Jun 29 2018

javed.absar accepted D48682: [MachineOutliner] Add always and never options to -enable-machine-outliner.

Thanks. LGTM.

Jun 29 2018, 1:13 AM

Jun 28 2018

Herald updated subscribers of D16829: An implementation of Swing Modulo Scheduling.
Jun 28 2018, 5:39 AM
javed.absar added inline comments to D48682: [MachineOutliner] Add always and never options to -enable-machine-outliner.
Jun 28 2018, 1:09 AM

Jun 14 2018

javed.absar accepted D48074: [ARM] Enable useAA() for the in-order Cortex-R52.
Jun 14 2018, 12:45 AM

Jun 13 2018

javed.absar added a comment to D48074: [ARM] Enable useAA() for the in-order Cortex-R52.

LGTM but will wait for others to comment as well before accepting

Jun 13 2018, 1:26 AM

Jun 11 2018

javed.absar added inline comments to D48013: TableGen/SearchableTables: Support more generic enums and tables.
Jun 11 2018, 4:18 PM
javed.absar added inline comments to D48013: TableGen/SearchableTables: Support more generic enums and tables.
Jun 11 2018, 3:21 PM
javed.absar added a comment to D48015: ARM,AArch64: Use generic tables instead of SearchableTable.

Probably good to mention that this patch relies on https://reviews.llvm.org/D48013

Jun 11 2018, 1:24 PM
javed.absar added a reviewer for D48013: TableGen/SearchableTables: Support more generic enums and tables: javed.absar.
Jun 11 2018, 1:22 PM
javed.absar added a comment to D48015: ARM,AArch64: Use generic tables instead of SearchableTable.

Its not clear to me why 'GenericTable' is more efficient/better than SearchableTable. Maybe you could give some background in the commit message about this. I implemented the ARMSystemRegister bit sometime ago and found SearchableTable quite useful and concise but perhaps GenericTable/Enum is even better.

Jun 11 2018, 7:09 AM

Jun 7 2018

javed.absar added inline comments to D47008: [SystemZ] Reimplent SchedModel IssueWidth and WriteRes/ReadAdvance mappings to operands.
Jun 7 2018, 9:00 AM