javed.absar (Javed Absar)
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User Since
Mar 27 2015, 6:20 AM (165 w, 1 d)

Recent Activity

Thu, May 24

javed.absar added inline comments to D47310: [AArch64][SVE] Asm: Support for ADD (immediate) instructions..
Thu, May 24, 12:04 PM

Wed, May 23

javed.absar added a comment to D47239: [InstCombine] Combine XOR and AES insructions on ARM/ARM64.

I am not an expert in encryption but how likely it is for 'key' to be zero ?
Other than that, LGTM

Wed, May 23, 12:31 PM

Sun, May 20

javed.absar added inline comments to D46695: [RFC] [Patch 1/3] Add a new class of predicates for variant scheduling classes..
Sun, May 20, 9:21 AM

Thu, May 17

javed.absar added inline comments to D47000: [AArch64] Use addAliasForDirective to support data directives.
Thu, May 17, 1:54 AM

Tue, May 15

javed.absar added a comment to D46884: [AArch64] Cortex-A55 scheduler model.

LGTM but then I wrote it originally so better to wait for comments from others.

Tue, May 15, 9:09 AM
javed.absar added inline comments to D46870: [MachineScheduler] Don't enforce some hazard checks pre-RA..
Tue, May 15, 5:08 AM

Mon, May 14

javed.absar accepted D46777: [ARM] Back up R4 and LR if calling the stack probe function.
Mon, May 14, 2:00 AM
javed.absar added a comment to D46777: [ARM] Back up R4 and LR if calling the stack probe function.

Separated the blocks, as requested.

Mon, May 14, 1:37 AM
javed.absar added a comment to D46682: [AArch64][SVE] Asm: Support for contiguous PRF prefetch instructions..

Suggestion for commit message - "Add support and tests for contiguous Prefetch instructions different variants."
The problem i find sometimes with long title is that it it truncated.

Mon, May 14, 1:35 AM

Sun, May 13

javed.absar added inline comments to D46695: [RFC] [Patch 1/3] Add a new class of predicates for variant scheduling classes..
Sun, May 13, 8:36 AM

Sat, May 12

javed.absar added inline comments to D46777: [ARM] Back up R4 and LR if calling the stack probe function.
Sat, May 12, 9:06 AM

Fri, May 11

javed.absar added inline comments to D46701: [RFC][AArch64] Use the new MCSchedPredicate to rewrite a couple of predicates..
Fri, May 11, 5:28 AM

Thu, May 10

javed.absar added inline comments to D46695: [RFC] [Patch 1/3] Add a new class of predicates for variant scheduling classes..
Thu, May 10, 3:22 PM
javed.absar added inline comments to D46695: [RFC] [Patch 1/3] Add a new class of predicates for variant scheduling classes..
Thu, May 10, 3:12 PM
javed.absar added inline comments to D46701: [RFC][AArch64] Use the new MCSchedPredicate to rewrite a couple of predicates..
Thu, May 10, 3:09 PM
javed.absar added reviewers for D46695: [RFC] [Patch 1/3] Add a new class of predicates for variant scheduling classes.: atrick, MatzeB, javed.absar.
Thu, May 10, 12:32 PM
javed.absar added a comment to D46679: [AArch64][SVE] Asm: Support for structured LD2, LD3 and LD4 (scalar+scalar) load instructions..

Having discussed with Sander and Florian in detail I now agree it is better to add properly grouped Scheds later.

Thu, May 10, 6:10 AM
javed.absar added a comment to D46679: [AArch64][SVE] Asm: Support for structured LD2, LD3 and LD4 (scalar+scalar) load instructions..

Hi Florian.
I would then suggest adding the following to AArch64Schedule.td and then simply assigning the appropriate Scheds.
Much less work and neater doing it now when the instruction implementation is being done.

Thu, May 10, 4:01 AM
javed.absar added inline comments to D46679: [AArch64][SVE] Asm: Support for structured LD2, LD3 and LD4 (scalar+scalar) load instructions..
Thu, May 10, 3:06 AM
javed.absar added a comment to D46682: [AArch64][SVE] Asm: Support for contiguous PRF prefetch instructions..

I might be good to put commit-message/description.

Thu, May 10, 2:35 AM

Wed, May 9

javed.absar added inline comments to D46591: [AArch64] Fix performPostLD1Combine to check for constant lane index..
Wed, May 9, 4:42 AM

Thu, May 3

javed.absar added a comment to D46356: [TableGen] Emit a fatal error on inconsistencies in resource units vs cycles..

Does FDIV use both the resources for 8 cycles? Writing [8,8] would imply that.

Thu, May 3, 8:47 AM

Wed, May 2

javed.absar added a comment to D46356: [TableGen] Emit a fatal error on inconsistencies in resource units vs cycles..

Ah! OK, I see. Thanks for the clarification.

Wed, May 2, 8:42 AM
javed.absar added a comment to D46356: [TableGen] Emit a fatal error on inconsistencies in resource units vs cycles..

I think it'd be clearer if we could keep Btver2/Znver1 to the Res = [1] default tbh

Hm, not sure how I can do that without triggering the check for cases when the user erroneously specified [1] when they wanted to use the default (now []). Did I miss a possibility ?
This makes is no difference for the user, but allows more checking. Best of both worlds ? :)

Wed, May 2, 8:06 AM
javed.absar added a comment to D46356: [TableGen] Emit a fatal error on inconsistencies in resource units vs cycles..

Thanks for this check.
If ResourceCycles is not specified then it should default to 1 . I believe most people write with that interpretation.
If ResourceCycles is specified for at least one resource, it makes sense from correctness POV that it be specified for all (even though it might get verbose at time).

Wed, May 2, 7:35 AM
javed.absar added reviewers for D46356: [TableGen] Emit a fatal error on inconsistencies in resource units vs cycles.: MatzeB, atrick.
Wed, May 2, 7:24 AM

Tue, May 1

javed.absar added a comment to D46192: Script to match open Phabricator reviews with potential reviewers.

Hi Kristof. Thanks for this.

Tue, May 1, 1:55 AM

Mon, Apr 30

javed.absar added inline comments to D46273: [InstCombine, ARM] Convert vld1 to llvm load.
Mon, Apr 30, 2:47 PM
javed.absar added reviewers for D46243: Move Schedule class to header file for allowing inheritance: MatzeB, javed.absar.
Mon, Apr 30, 1:34 AM

Apr 27 2018

javed.absar accepted D46178: [SCEV] Reduce the number of invocation to non trivial getExact function.

Please rephrase this part of commit message as it is hard to read/understand - "And even if statistics is disable and code
related to it will be eliminated the invocation to getExact itself will not be eliminated because it may have side-effects like creation of new SCEVs".

Apr 27 2018, 2:30 AM
javed.absar added a comment to D46178: [SCEV] Reduce the number of invocation to non trivial getExact function.

AFAIU the correctness check would now get gated on STATS colelction and that may not be right. I would recommend separating the two.

Apr 27 2018, 1:25 AM

Apr 26 2018

javed.absar added inline comments to D46133: [InstCombine, ARM, AArch64] Convert table lookup to shuffle vector.
Apr 26 2018, 1:31 PM
javed.absar added inline comments to D46110: [IR] Do not assume that function pointers are aligned.
Apr 26 2018, 6:27 AM

Apr 25 2018

javed.absar added inline comments to D46046: [SCEV] Do not use induction in isKnownPredicate for simplification umax.
Apr 25 2018, 2:18 AM
javed.absar added inline comments to D46047: [SCEV] Introduce bulk umin creation utilities.
Apr 25 2018, 2:16 AM
javed.absar added a comment to D46046: [SCEV] Do not use induction in isKnownPredicate for simplification umax.

Would removing 'isKnownViaInduction' have any impact of the number of cases 'analyzeable by scev?

Apr 25 2018, 2:05 AM

Apr 24 2018

javed.absar accepted D45982: [TTI, AArch64] Add transpose shuffle kind.

LGTM. Probably wait a day before committing in case Renato/others have a comment/suggestion.

Apr 24 2018, 12:57 PM
javed.absar added inline comments to D45191: [LoopReroll] Rewrite induction variable rewriting..
Apr 24 2018, 9:30 AM

Apr 23 2018

javed.absar added inline comments to D45982: [TTI, AArch64] Add transpose shuffle kind.
Apr 23 2018, 2:28 PM
javed.absar added a comment to D45916: Enable MachineOutliner by default under -Oz for AArch64.

Could you please generate diff with -U999 to give more context to the patch. Thanks.

Apr 23 2018, 7:12 AM

Apr 20 2018

javed.absar added a comment to D45874: [LoopUnroll] Split out simplify code after Unroll into a new function. NFC.

Any test possible here?

Apr 20 2018, 5:39 AM
javed.absar added a comment to D45872: [DA] Enable -da-delinearize by default.

AFAIU this change would affect other targets. Probably best to add more reviewers (owners for other targets).

Apr 20 2018, 5:33 AM

Apr 19 2018

javed.absar added a comment to D45821: [AArch64] improve code generation of vectors smaller than 64 bit.

Thanks for this Sebastian. Overall, this definitely look good for vectorization.

Apr 19 2018, 2:37 PM

Apr 18 2018

javed.absar added inline comments to D42447: [LV][VPlan] Detect outer loops for explicit vectorization..
Apr 18 2018, 11:25 AM
javed.absar added a comment to D45690: [AArch64][SVE] Asm: Support for contiguous LD1 (scalar+scalar) load instructions..

Hi Sander.
Its good you mention 'patch [4/4] in a series' in commit message. But could you please also link them up by providing link to previous reviews etc.
Might be easy for tracking later.

Apr 18 2018, 6:08 AM

Apr 4 2018

javed.absar added a comment to D45229: [MI-sched] schedule following instruction latencies.

Hi Sebastian:
For the test case, the change looks good, though I am surprised the current scheduling algorithm does that (i.e. scheduling store just one cycle after load which definitely would result in stalls, especially for in-order processors). I am guessing the latency it is picking up is 1?

Apr 4 2018, 1:17 AM

Apr 3 2018

javed.absar added a comment to D45229: [MI-sched] schedule following instruction latencies.
Apr 3 2018, 11:43 PM
javed.absar added inline comments to D45189: [MachineOutliner][AArch64] Keep track of functions that use a red zone in AArch64MachineFunctionInfo and use that instead of checking for noredzone in the MachineOutliner.
Apr 3 2018, 1:49 AM

Mar 26 2018

javed.absar accepted D44834: [MachineScheduler] Add itinerary to schedcover.py. Make default work in the command line filter.
Mar 26 2018, 2:30 PM

Mar 25 2018

javed.absar accepted D44687: [SchedModel] Remove instregex entries that don't match any instructions (WIP).

LGTM

Mar 25 2018, 11:37 AM

Mar 22 2018

javed.absar accepted D44767: [ARM] Enable the full InstRW overlap check for ARMScheduleR52.td.

Thanks for this.

Mar 22 2018, 9:55 AM

Mar 21 2018

javed.absar added a comment to D44687: [SchedModel] Remove instregex entries that don't match any instructions (WIP).

This patch makes sure each regular expression covers at least one instruction. We already checked that each InstRW line matched at least one instruction. But if there were multiple regular expressions listed, we didn't check it.

Making sure each instruction is only covered by one instregex or instrs match is already being done. And a hole in it was fixed recently with r327808. Though I had to disable the improved check on some models. Look for FullInstRWOverlapCheck = 0 in the SchedMachineModel in the td files to see if I disabled it for any schedulers you care about. I need to collect the effected schedulers and start getting people to fix it.

Mar 21 2018, 4:14 PM
javed.absar added a comment to D44687: [SchedModel] Remove instregex entries that don't match any instructions (WIP).

Thanks for this. If I am getting this right, just like CompleteModel ensures no instruction has a missing schedule, this patch will ensure no instruction has multiple schedule (instregex) assigned?

Mar 21 2018, 8:17 AM

Mar 6 2018

javed.absar added inline comments to D43973: [AArch64] define isExtractSubvectorCheap.
Mar 6 2018, 1:13 AM

Mar 5 2018

javed.absar accepted D44089: [MachineScheduler] Dump SUnits before calling SchedImpl->initialize().
Mar 5 2018, 8:18 AM
javed.absar added a comment to D44089: [MachineScheduler] Dump SUnits before calling SchedImpl->initialize().

I assume no tests are impacted by this. Otherwise, looks LGTM

Mar 5 2018, 7:01 AM
javed.absar accepted D43374: [ARM]Decoding MSR with unpredictable destination register causes an assert.
Mar 5 2018, 1:20 AM

Feb 27 2018

javed.absar added a comment to D43808: ARM Cortex A57 scheduler fix (missed 16-bit, v8.1/v8.2/v8.3, thumb and pseudo instructions).

By the way, did you do any bench-marking to see if there were any impact of these changes, although from the changes it looks to me there wont be anything significant, and besides I understand this is simply for CompleteModel.

Feb 27 2018, 1:26 AM

Feb 16 2018

javed.absar added inline comments to D43374: [ARM]Decoding MSR with unpredictable destination register causes an assert.
Feb 16 2018, 5:26 AM

Jan 30 2018

javed.absar created D42689: [SCEV] Fix threshold limit check.
Jan 30 2018, 6:39 AM

Jan 18 2018

javed.absar added inline comments to D42033: [RISCV] Initial Machine Scheduler.
Jan 18 2018, 2:09 AM

Jan 17 2018

javed.absar committed rL322765: [SCEV] Fix typo. NFC..
[SCEV] Fix typo. NFC.
Jan 17 2018, 2:00 PM
javed.absar committed rL322629: [SCEV] fix typo.
[SCEV] fix typo
Jan 17 2018, 3:04 AM

Jan 2 2018

javed.absar added inline comments to D41441: [AArch64][SVE] Asm: Add restricted register classes for SVE predicate vectors..
Jan 2 2018, 2:23 AM

Dec 20 2017

javed.absar committed rL321179: [SCEV] Fix Typo. NFC..
[SCEV] Fix Typo. NFC.
Dec 20 2017, 7:07 AM
javed.absar added inline comments to D41430: [ARM] Armv8-R DFB instruction.
Dec 20 2017, 3:20 AM

Dec 4 2017

javed.absar accepted D36747: [Asm, ARM] Add fallback diag for multiple invalid operands.

LGTM. Thanks for this.

Dec 4 2017, 3:39 AM

Nov 28 2017

javed.absar added inline comments to D38279: [MachineScheduler] Enable latency heuristic based on scheduled lat..
Nov 28 2017, 2:22 AM

Nov 27 2017

javed.absar added a comment to D40480: MemorySSA backed Dead Store Elimination. .

Just a suggestion: To ease review, could this be split into smaller patches along the lines you mention - noop stores, partial overwrites, stores before frees/lifetime_ends ?

Nov 27 2017, 3:19 AM

Nov 24 2017

javed.absar committed rL318952: [SCEV] : Simplify loop to range-loop.NFC..
[SCEV] : Simplify loop to range-loop.NFC.
Nov 24 2017, 6:36 AM

Nov 23 2017

javed.absar added a comment to D40370: [arm] Add support for armv7e-m to the .arch directive..

Hi.
Full context (diff -U999) is missing. Also you may want to write a brief intro which you can use as commit message.

Nov 23 2017, 7:17 AM

Nov 22 2017

javed.absar added inline comments to D40333: Separate LoopTraversal and BreakFalseDeps out of ExecutionDomainFix into their own files.
Nov 22 2017, 2:05 AM

Nov 21 2017

javed.absar accepted D40263: [TableGen] Improve error reporting.

LGTM. Thanks for this.

Nov 21 2017, 11:18 AM
javed.absar added inline comments to D36747: [Asm, ARM] Add fallback diag for multiple invalid operands.
Nov 21 2017, 4:11 AM
javed.absar accepted D40254: [MI scheduler] Fix VADD and VSUB in cortex-a57 model.

Thanks for this.

Nov 21 2017, 2:24 AM
javed.absar added a comment to D40263: [TableGen] Improve error reporting.

Thanks for this. Is it possible to put a test? If not, perhaps you can share the output generated for a purposely failing case here (by omitting a referenced resource).

Nov 21 2017, 2:20 AM

Nov 20 2017

javed.absar added inline comments to D40254: [MI scheduler] Fix VADD and VSUB in cortex-a57 model.
Nov 20 2017, 9:44 AM

Nov 16 2017

javed.absar committed rL318401: [SCEV] simplify loop. NFC..
[SCEV] simplify loop. NFC.
Nov 16 2017, 5:49 AM

Nov 10 2017

javed.absar added a comment to D39808: [ARM GlobalISel] Fix call opcode for Thumb .

Gentle reminder.

Nov 10 2017, 1:50 AM

Nov 9 2017

javed.absar added reviewers for D38378: [ARM] Optimize {s,u}{add,sub}.with.overflow.: rovka, rengolin.
Nov 9 2017, 12:39 PM
javed.absar added inline comments to D38378: [ARM] Optimize {s,u}{add,sub}.with.overflow..
Nov 9 2017, 12:39 PM
javed.absar added inline comments to D39712: [ARM] Add an alias for psr and psr_nzcvq.
Nov 9 2017, 5:15 AM

Nov 8 2017

javed.absar added a comment to D39592: [ARM|GlobalISel] : Adding legalizer tests for Thumb.

This patch is now dependent on https://reviews.llvm.org/D39808

Nov 8 2017, 2:52 PM
javed.absar created D39808: [ARM GlobalISel] Fix call opcode for Thumb .
Nov 8 2017, 10:03 AM

Nov 7 2017

javed.absar added a comment to D39712: [ARM] Add an alias for psr and psr_nzcvq.

Hi Leslie:
As Oli mentioned, I did not find reference to PSR in ARM-ARM when preparing these tables. Leaving it to Renato to decide whether it should still be added.
If you do end up adding, and the encoding is same as XPSR, you could use the Mask bits 1,0,1 to differentiate against existing XPSR encoding entry (otherwise Searchable Table will complain about uniqueness).

Nov 7 2017, 4:03 AM

Nov 6 2017

javed.absar added a comment to D39592: [ARM|GlobalISel] : Adding legalizer tests for Thumb.

Thanks Diana for the review.

Nov 6 2017, 10:30 AM
javed.absar updated the diff for D39592: [ARM|GlobalISel] : Adding legalizer tests for Thumb.
Nov 6 2017, 10:26 AM
javed.absar added a comment to D39592: [ARM|GlobalISel] : Adding legalizer tests for Thumb.

It seems the thumb instruction selection will take more work and needs probably split up into smaller ones (as discussed with Diana). So they will come later.

Nov 6 2017, 1:00 AM

Nov 3 2017

javed.absar updated the diff for D39592: [ARM|GlobalISel] : Adding legalizer tests for Thumb.

Added thumb tests to all three. Also renamed the files to make it clear the test run both arm and thumb

Nov 3 2017, 10:32 AM
javed.absar added a comment to D39592: [ARM|GlobalISel] : Adding legalizer tests for Thumb.

Hi Diana.
Yes I too was thinking of adding just the run line, but I don't know when we move to instruction-selection would/could we do the same.
And if not, the separation upfront might be a good idea. Please advise. I am ok either way.

Nov 3 2017, 6:50 AM
javed.absar created D39592: [ARM|GlobalISel] : Adding legalizer tests for Thumb.
Nov 3 2017, 5:00 AM

Nov 2 2017

javed.absar added a comment to D39558: [TargetParser][AArch64] Reorder enum to preserve 5.0.0 libLLVM ABI..

Would it make sense to add a test, so that any future changes doesn't undo this behaviour?

Nov 2 2017, 9:13 AM
javed.absar added a comment to D39507: [AArch64] Fix the number of iterations for the Newton series.

Full context is missing (seems you forgot diff .... -U9999)

Nov 2 2017, 2:15 AM

Oct 30 2017

javed.absar committed rL316960: [AArch64]: range loopify frame-lowering.
[AArch64]: range loopify frame-lowering
Oct 30 2017, 3:00 PM
javed.absar added a comment to D39415: [ARMISelLowering] Better handling of NEON load/store for sequential memory regions.

Hi Eugene:
Thanks for the work. However, in its current form the implementation is bit hard to follow. Would it be possible to, describe -

  1. Your overall approach in the implementation

2.. Describe above the function what it is trying to do (e.g. checkedGetIncrement - which b.t.w looks non-intuitive name).

Oct 30 2017, 11:01 AM
javed.absar committed rL316902: [GlobalISel|ARM] : Allow legalizing G_FSUB.
[GlobalISel|ARM] : Allow legalizing G_FSUB
Oct 30 2017, 6:52 AM
javed.absar closed D39261: [GlobalISel|ARM] : Allow legalizing G_FSUB by committing rL316902: [GlobalISel|ARM] : Allow legalizing G_FSUB.
Oct 30 2017, 6:52 AM

Oct 29 2017

javed.absar updated the diff for D39261: [GlobalISel|ARM] : Allow legalizing G_FSUB.

Thanks Diana for the feedback. I added the missing tests and they now all pass.

Oct 29 2017, 12:36 PM

Oct 26 2017

javed.absar added inline comments to D38196: [AArch64] Avoid interleaved SIMD store instructions for Exynos.
Oct 26 2017, 1:58 AM

Oct 24 2017

javed.absar created D39261: [GlobalISel|ARM] : Allow legalizing G_FSUB.
Oct 24 2017, 2:36 PM