[RISCV][CodeGen] Support Zhinx and Zhinxmin

[realqhc]

Summary

This patch was split from D122918.

Co-Author: @liaolucy @sunshaoce

[realqhc]

rebase

[craig.topper]

Do we need to update RISCVInstrInfo::storeRegToStackSlot and RISCVInstrInfo::loadRegFromStackSlot`?

[realqhc]

In D149811#4328339, @craig.topper wrote:

Do we need to update RISCVInstrInfo::storeRegToStackSlot and RISCVInstrInfo::loadRegFromStackSlot`?

Based on my understanding, it may not require update, as the GPRRegClass load and store is handling it similar to the zfinx patch.

[realqhc]

add missing changes in RISCVInstrInfo.cpp regarding FSGNJ_H_INX

[craig.topper]

In D149811#4328349, @realqhc wrote:

In D149811#4328339, @craig.topper wrote:

Do we need to update RISCVInstrInfo::storeRegToStackSlot and RISCVInstrInfo::loadRegFromStackSlot`?

Based on my understanding, it may not require update, as the GPRRegClass load and store is handling it similar to the zfinx patch.

I hadn't noticed we are using the same spill sizes for GPRF16/GPRF32/GPRF64. So you're correct it doesn't need an update.

[craig.topper]

llvm/test/CodeGen/RISCV/half-select-fcmp.ll

17

Why are these lines deleted?

[realqhc]

This comment was removed by realqhc.

[realqhc]

restore the unintentionally removed test cases, it was caused by wrongly defined check prefix in zhinxmin

[realqhc]

llvm/test/CodeGen/RISCV/half-select-fcmp.ll

17

updated the patch to fix it

[craig.topper]

Can we make this patch not depend on Zdinx RV32 support? That patch needs more work and I don't want it to block Zhinx.

[realqhc]

In D149811#4331256, @craig.topper wrote:

Can we make this patch not depend on Zdinx RV32 support? That patch needs more work and I don't want it to block Zhinx.

I have removed the dependency on phabricator, but I think some modification should be required on RISCVInstrInfoZfh.td, do you think it is better to move them to the rv32zdinx patch instead?

[craig.topper]

In D149811#4331330, @realqhc wrote:

In D149811#4331256, @craig.topper wrote:

Can we make this patch not depend on Zdinx RV32 support? That patch needs more work and I don't want it to block Zhinx.

I have removed the dependency on phabricator, but I think some modification should be required on RISCVInstrInfoZfh.td, do you think it is better to move them to the rv32zdinx patch instead?

In the interest of forward progress, yes.

[realqhc]

run clang-format

[realqhc]

remove the dependency on rv32zdinx patch

[craig.topper]

LGTM

llvm/docs/RISCVUsage.rst

.. table:: Ratified Extensions by Status
      ``Zbkb``         Supported (`See note <#riscv-scalar-crypto-note1>`__)
      ``Zbkc``         Supported
      ``Zbkx``         Supported (`See note <#riscv-scalar-crypto-note1>`__)
      ``Zbs``          Supported
      ``Zdinx``        Supported
      ``Zfh``          Supported
      ``Zfhmin``       Supported
      ``Zfinx``        Supported
-     ``Zhinx``        Assembly Support
-     ``Zhinxmin``     Assembly Support
+     ``Zhinx``        Supported
+     ``Zhinxmin``     Supported
      ``Zicbom``       Assembly Support
      ``Zicbop``       Assembly Support
      ``Zicboz``       Assembly Support
      ``Zicntr``       (`See Note <#riscv-i2p1-note>`__)
      ``Zicsr``        (`See Note <#riscv-i2p1-note>`__)
      ``Zifencei``     (`See Note <#riscv-i2p1-note>`__)
      ``Zihintpause``  Assembly Support
      ``Zihpm``        (`See Note <#riscv-i2p1-note>`__)

llvm/lib/Target/RISCV/RISCVFeatures.td

 
 def FeatureStdExtZhinx
     : SubtargetFeature<"zhinx", "HasStdExtZhinx", "true",
                        "'Zhinx' (Half Float in Integer)",
                        [FeatureStdExtZfinx]>;
 def HasStdExtZhinx : Predicate<"Subtarget->hasStdExtZhinx()">,
                                AssemblerPredicate<(all_of FeatureStdExtZhinx),
                                "'Zhinx' (Half Float in Integer)">;
+def NoStdExtZhinx : Predicate<"!Subtarget->hasStdExtZhinx()">;
 
 def HasStdExtZhinxOrZhinxmin
     : Predicate<"Subtarget->hasStdExtZhinx() || Subtarget->hasStdExtZhinxmin()">,
                 AssemblerPredicate<(any_of FeatureStdExtZhinx, FeatureStdExtZhinxmin),
                                    "'Zhinx' (Half Float in Integer) or "
                                    "'Zhinxmin' (Half Float in Integer Minimal)">;
 
 def FeatureStdExtZfa

llvm/lib/Target/RISCV/RISCVISelDAGToDAG.cpp

else
       Imm = selectImm(CurDAG, DL, XLenVT, APF.bitcastToAPInt().getSExtValue(),
                       *Subtarget);
 
     unsigned Opc;
     switch (VT.SimpleTy) {
     default:
       llvm_unreachable("Unexpected size");
     case MVT::f16:
-      Opc = RISCV::FMV_H_X;
+      Opc = Subtarget->hasStdExtZhinxOrZhinxmin() ? RISCV::COPY : RISCV::FMV_H_X;
       break;
     case MVT::f32:
       Opc = Subtarget->hasStdExtZfinx() ? RISCV::COPY : RISCV::FMV_W_X;
       break;
     case MVT::f64:
       // For RV32, we can't move from a GPR, we need to convert instead. This
       // should only happen for +0.0 and -0.0.
       assert((Subtarget->is64Bit() || APF.isZero()) && "Unexpected constant");

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
   addRegisterClass(XLenVT, &RISCV::GPRRegClass);
 
   if (Subtarget.hasStdExtZfhOrZfhmin())
     addRegisterClass(MVT::f16, &RISCV::FPR16RegClass);
   if (Subtarget.hasStdExtF())
     addRegisterClass(MVT::f32, &RISCV::FPR32RegClass);
   if (Subtarget.hasStdExtD())
     addRegisterClass(MVT::f64, &RISCV::FPR64RegClass);
+  if (Subtarget.hasStdExtZhinxOrZhinxmin())
+    addRegisterClass(MVT::f16, &RISCV::GPRF16RegClass);
   if (Subtarget.hasStdExtZfinx())
     addRegisterClass(MVT::f32, &RISCV::GPRF32RegClass);
   if (Subtarget.hasStdExtZdinx()) {
     if (Subtarget.is64Bit())
       addRegisterClass(MVT::f64, &RISCV::GPRF64RegClass);
     else
       addRegisterClass(MVT::f64, &RISCV::GPRPF64RegClass);
   }
RISCVTargetLowering::RISCVTargetLowering(const TargetMachine &TM,
   static const unsigned FPOpToExpand[] = {
       ISD::FSIN, ISD::FCOS,       ISD::FSINCOS,   ISD::FPOW,
       ISD::FREM, ISD::FP16_TO_FP, ISD::FP_TO_FP16};
 
   static const unsigned FPRndMode[] = {
       ISD::FCEIL, ISD::FFLOOR, ISD::FTRUNC, ISD::FRINT, ISD::FROUND,
       ISD::FROUNDEVEN};
 
-  if (Subtarget.hasStdExtZfhOrZfhmin())
+  if (Subtarget.hasStdExtZfhOrZfhminOrZhinxOrZhinxmin())
     setOperationAction(ISD::BITCAST, MVT::i16, Custom);
 
-  if (Subtarget.hasStdExtZfhOrZfhmin()) {
-    if (Subtarget.hasStdExtZfh()) {
+  if (Subtarget.hasStdExtZfhOrZfhminOrZhinxOrZhinxmin()) {
+    if (Subtarget.hasStdExtZfhOrZhinx()) {
       setOperationAction(FPLegalNodeTypes, MVT::f16, Legal);
       setOperationAction(FPRndMode, MVT::f16,
                          Subtarget.hasStdExtZfa() ? Legal : Custom);
       setOperationAction(ISD::SELECT, MVT::f16, Custom);
       setOperationAction(ISD::IS_FPCLASS, MVT::f16, Custom);
     } else {
       static const unsigned ZfhminPromoteOps[] = {
           ISD::FMINNUM,      ISD::FMAXNUM,       ISD::FADD,
if (Subtarget.useRVVForFixedLengthVectors()) {
              ISD::STRICT_FCEIL, ISD::STRICT_FFLOOR, ISD::STRICT_FROUND,
              ISD::STRICT_FROUNDEVEN, ISD::STRICT_FNEARBYINT},
             VT, Custom);
       }
 
       // Custom-legalize bitcasts from fixed-length vectors to scalar types.
       setOperationAction(ISD::BITCAST, {MVT::i8, MVT::i16, MVT::i32, MVT::i64},
                          Custom);
-      if (Subtarget.hasStdExtZfhOrZfhmin())
+      if (Subtarget.hasStdExtZfhOrZfhminOrZhinxOrZhinxmin())
         setOperationAction(ISD::BITCAST, MVT::f16, Custom);
       if (Subtarget.hasStdExtFOrZfinx())
         setOperationAction(ISD::BITCAST, MVT::f32, Custom);
       if (Subtarget.hasStdExtDOrZdinx())
         setOperationAction(ISD::BITCAST, MVT::f64, Custom);
     }
   }
 

   if (Subtarget.hasStdExtZbb())
     setTargetDAGCombine({ISD::UMAX, ISD::UMIN, ISD::SMAX, ISD::SMIN});
 
   if (Subtarget.hasStdExtZbs() && Subtarget.is64Bit())
     setTargetDAGCombine(ISD::TRUNCATE);
 
   if (Subtarget.hasStdExtZbkb())
     setTargetDAGCombine(ISD::BITREVERSE);
-  if (Subtarget.hasStdExtZfhOrZfhmin())
+  if (Subtarget.hasStdExtZfhOrZfhminOrZhinxOrZhinxmin())
     setTargetDAGCombine(ISD::SIGN_EXTEND_INREG);
   if (Subtarget.hasStdExtFOrZfinx())
     setTargetDAGCombine({ISD::ZERO_EXTEND, ISD::FP_TO_SINT, ISD::FP_TO_UINT,
                          ISD::FP_TO_SINT_SAT, ISD::FP_TO_UINT_SAT});
   if (Subtarget.hasVInstructions())
     setTargetDAGCombine({ISD::FCOPYSIGN, ISD::MGATHER, ISD::MSCATTER,
                          ISD::VP_GATHER, ISD::VP_SCATTER, ISD::SRA, ISD::SRL,
                          ISD::SHL, ISD::STORE, ISD::SPLAT_VECTOR,
int RISCVTargetLowering::getLegalZfaFPImm(const APFloat &Imm, EVT VT) const {
 
   return RISCVLoadFPImm::getLoadFPImm(Imm);
 }
 
 bool RISCVTargetLowering::isFPImmLegal(const APFloat &Imm, EVT VT,
                                        bool ForCodeSize) const {
   bool IsLegalVT = false;
   if (VT == MVT::f16)
-    IsLegalVT = Subtarget.hasStdExtZfhOrZfhmin();
+    IsLegalVT = Subtarget.hasStdExtZfhOrZfhminOrZhinxOrZhinxmin();
   else if (VT == MVT::f32)
     IsLegalVT = Subtarget.hasStdExtFOrZfinx();
   else if (VT == MVT::f64)
     IsLegalVT = Subtarget.hasStdExtDOrZdinx();
 
   if (!IsLegalVT)
     return false;
 

 }
 
 MVT RISCVTargetLowering::getRegisterTypeForCallingConv(LLVMContext &Context,
                                                       CallingConv::ID CC,
                                                       EVT VT) const {
   // Use f32 to pass f16 if it is legal and Zfh/Zfhmin is not enabled.
   // We might still end up using a GPR but that will be decided based on ABI.
   if (VT == MVT::f16 && Subtarget.hasStdExtFOrZfinx() &&
-      !Subtarget.hasStdExtZfhOrZfhmin())
+      !Subtarget.hasStdExtZfhOrZfhminOrZhinxOrZhinxmin())
     return MVT::f32;
 
   return TargetLowering::getRegisterTypeForCallingConv(Context, CC, VT);
 }
 
 unsigned RISCVTargetLowering::getNumRegistersForCallingConv(LLVMContext &Context,
                                                            CallingConv::ID CC,
                                                            EVT VT) const {
   // Use f32 to pass f16 if it is legal and Zfh/Zfhmin is not enabled.
   // We might still end up using a GPR but that will be decided based on ABI.
   if (VT == MVT::f16 && Subtarget.hasStdExtFOrZfinx() &&
-      !Subtarget.hasStdExtZfhOrZfhmin())
+      !Subtarget.hasStdExtZfhOrZfhminOrZhinxOrZhinxmin())
     return 1;
 
   return TargetLowering::getNumRegistersForCallingConv(Context, CC, VT);
 }
 
 // Changes the condition code and swaps operands if necessary, so the SetCC
 // operation matches one of the comparisons supported directly by branches
 // in the RISC-V ISA. May adjust compares to favor compare with 0 over compare
static SDValue lowerFP_TO_INT_SAT(SDValue Op, SelectionDAG &DAG,
 
   MVT DstVT = Op.getSimpleValueType();
   EVT SatVT = cast<VTSDNode>(Op.getOperand(1))->getVT();
 
   bool IsSigned = Op.getOpcode() == ISD::FP_TO_SINT_SAT;
 
   if (!DstVT.isVector()) {
     // In absense of Zfh, promote f16 to f32, then saturate the result.
-    if (Src.getSimpleValueType() == MVT::f16 && !Subtarget.hasStdExtZfh()) {
+    if (Src.getSimpleValueType() == MVT::f16 && !Subtarget.hasStdExtZfhOrZhinx()) {
       Src = DAG.getNode(ISD::FP_EXTEND, SDLoc(Op), MVT::f32, Src);
     }
 
     unsigned Opc;
     if (SatVT == DstVT)
       Opc = IsSigned ? RISCVISD::FCVT_X : RISCVISD::FCVT_XU;
     else if (DstVT == MVT::i64 && SatVT == MVT::i32)
       Opc = IsSigned ? RISCVISD::FCVT_W_RV64 : RISCVISD::FCVT_WU_RV64;
case ISD::SRL_PARTS:
     return lowerShiftRightParts(Op, DAG, false);
   case ISD::BITCAST: {
     SDLoc DL(Op);
     EVT VT = Op.getValueType();
     SDValue Op0 = Op.getOperand(0);
     EVT Op0VT = Op0.getValueType();
     MVT XLenVT = Subtarget.getXLenVT();
     if (VT == MVT::f16 && Op0VT == MVT::i16 &&
-        Subtarget.hasStdExtZfhOrZfhmin()) {
+        Subtarget.hasStdExtZfhOrZfhminOrZhinxOrZhinxmin()) {
       SDValue NewOp0 = DAG.getNode(ISD::ANY_EXTEND, DL, XLenVT, Op0);
       SDValue FPConv = DAG.getNode(RISCVISD::FMV_H_X, DL, MVT::f16, NewOp0);
       return FPConv;
     }
     if (VT == MVT::f32 && Op0VT == MVT::i32 && Subtarget.is64Bit() &&
         Subtarget.hasStdExtFOrZfinx()) {
       SDValue NewOp0 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, Op0);
       SDValue FPConv =
case ISD::FP_TO_UINT: {
     SDValue Op0 = IsStrict ? N->getOperand(1) : N->getOperand(0);
     if (getTypeAction(*DAG.getContext(), Op0.getValueType()) !=
         TargetLowering::TypeSoftenFloat) {
       if (!isTypeLegal(Op0.getValueType()))
         return;
       if (IsStrict) {
         SDValue Chain = N->getOperand(0);
         // In absense of Zfh, promote f16 to f32, then convert.
-        if (Op0.getValueType() == MVT::f16 && !Subtarget.hasStdExtZfh()) {
+        if (Op0.getValueType() == MVT::f16 && !Subtarget.hasStdExtZfhOrZhinx()) {
           Op0 = DAG.getNode(ISD::STRICT_FP_EXTEND, DL, {MVT::f32, MVT::Other},
                             {Chain, Op0});
           Chain = Op0.getValue(1);
         }
         unsigned Opc = IsSigned ? RISCVISD::STRICT_FCVT_W_RV64
                                 : RISCVISD::STRICT_FCVT_WU_RV64;
         SDVTList VTs = DAG.getVTList(MVT::i64, MVT::Other);
         SDValue Res = DAG.getNode(
             Opc, DL, VTs, Chain, Op0,
             DAG.getTargetConstant(RISCVFPRndMode::RTZ, DL, MVT::i64));
         Results.push_back(DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Res));
         Results.push_back(Res.getValue(1));
         return;
       }
       // In absense of Zfh, promote f16 to f32, then convert.
-      if (Op0.getValueType() == MVT::f16 && !Subtarget.hasStdExtZfh())
+      if (Op0.getValueType() == MVT::f16 && !Subtarget.hasStdExtZfhOrZhinx())
         Op0 = DAG.getNode(ISD::FP_EXTEND, DL, MVT::f32, Op0);
 
       unsigned Opc = IsSigned ? RISCVISD::FCVT_W_RV64 : RISCVISD::FCVT_WU_RV64;
       SDValue Res =
           DAG.getNode(Opc, DL, MVT::i64, Op0,
                       DAG.getTargetConstant(RISCVFPRndMode::RTZ, DL, MVT::i64));
       Results.push_back(DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Res));
       return;
case ISD::LROUND: {
     SDValue Op0 = N->getOperand(0);
     EVT Op0VT = Op0.getValueType();
     if (getTypeAction(*DAG.getContext(), Op0.getValueType()) !=
         TargetLowering::TypeSoftenFloat) {
       if (!isTypeLegal(Op0VT))
         return;
 
       // In absense of Zfh, promote f16 to f32, then convert.
-      if (Op0.getValueType() == MVT::f16 && !Subtarget.hasStdExtZfh())
+      if (Op0.getValueType() == MVT::f16 && !Subtarget.hasStdExtZfhOrZhinx())
         Op0 = DAG.getNode(ISD::FP_EXTEND, DL, MVT::f32, Op0);
 
       SDValue Res =
           DAG.getNode(RISCVISD::FCVT_W_RV64, DL, MVT::i64, Op0,
                       DAG.getTargetConstant(RISCVFPRndMode::RMM, DL, MVT::i64));
       Results.push_back(DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, Res));
       return;
     }
void RISCVTargetLowering::ReplaceNodeResults(SDNode *N,
   }
   case ISD::BITCAST: {
     EVT VT = N->getValueType(0);
     assert(VT.isInteger() && !VT.isVector() && "Unexpected VT!");
     SDValue Op0 = N->getOperand(0);
     EVT Op0VT = Op0.getValueType();
     MVT XLenVT = Subtarget.getXLenVT();
     if (VT == MVT::i16 && Op0VT == MVT::f16 &&
-        Subtarget.hasStdExtZfhOrZfhmin()) {
+        Subtarget.hasStdExtZfhOrZfhminOrZhinxOrZhinxmin()) {
       SDValue FPConv = DAG.getNode(RISCVISD::FMV_X_ANYEXTH, DL, XLenVT, Op0);
       Results.push_back(DAG.getNode(ISD::TRUNCATE, DL, MVT::i16, FPConv));
     } else if (VT == MVT::i32 && Op0VT == MVT::f32 && Subtarget.is64Bit() &&
                Subtarget.hasStdExtFOrZfinx()) {
       SDValue FPConv =
           DAG.getNode(RISCVISD::FMV_X_ANYEXTW_RV64, DL, MVT::i64, Op0);
       Results.push_back(DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, FPConv));
     } else if (VT == MVT::i64 && Op0VT == MVT::f64 && XLenVT == MVT::i32 &&

 }
 
 static bool isSelectPseudo(MachineInstr &MI) {
   switch (MI.getOpcode()) {
   default:
     return false;
   case RISCV::Select_GPR_Using_CC_GPR:
   case RISCV::Select_FPR16_Using_CC_GPR:
+  case RISCV::Select_FPR16INX_Using_CC_GPR:
   case RISCV::Select_FPR32_Using_CC_GPR:
   case RISCV::Select_FPR32INX_Using_CC_GPR:
   case RISCV::Select_FPR64_Using_CC_GPR:
   case RISCV::Select_FPR64INX_Using_CC_GPR:
   case RISCV::Select_FPR64IN32X_Using_CC_GPR:
     return true;
   }
 }
static MachineBasicBlock *emitFROUND(MachineInstr &MI, MachineBasicBlock *MBB,
   case RISCV::PseudoFROUND_H:
     CmpOpc = RISCV::FLT_H;
     F2IOpc = RISCV::FCVT_W_H;
     I2FOpc = RISCV::FCVT_H_W;
     FSGNJOpc = RISCV::FSGNJ_H;
     FSGNJXOpc = RISCV::FSGNJX_H;
     RC = &RISCV::FPR16RegClass;
     break;
+  case RISCV::PseudoFROUND_H_INX:
+    CmpOpc = RISCV::FLT_H_INX;
+    F2IOpc = RISCV::FCVT_W_H_INX;
+    I2FOpc = RISCV::FCVT_H_W_INX;
+    FSGNJOpc = RISCV::FSGNJ_H_INX;
+    FSGNJXOpc = RISCV::FSGNJX_H_INX;
+    RC = &RISCV::GPRF16RegClass;
+    break;
   case RISCV::PseudoFROUND_S:
     CmpOpc = RISCV::FLT_S;
     F2IOpc = RISCV::FCVT_W_S;
     I2FOpc = RISCV::FCVT_S_W;
     FSGNJOpc = RISCV::FSGNJ_S;
     FSGNJXOpc = RISCV::FSGNJX_S;
     RC = &RISCV::FPR32RegClass;
     break;
RISCVTargetLowering::EmitInstrWithCustomInserter(MachineInstr &MI,
   default:
     llvm_unreachable("Unexpected instr type to insert");
   case RISCV::ReadCycleWide:
     assert(!Subtarget.is64Bit() &&
            "ReadCycleWrite is only to be used on riscv32");
     return emitReadCycleWidePseudo(MI, BB);
   case RISCV::Select_GPR_Using_CC_GPR:
   case RISCV::Select_FPR16_Using_CC_GPR:
+  case RISCV::Select_FPR16INX_Using_CC_GPR:
   case RISCV::Select_FPR32_Using_CC_GPR:
   case RISCV::Select_FPR32INX_Using_CC_GPR:
   case RISCV::Select_FPR64_Using_CC_GPR:
   case RISCV::Select_FPR64INX_Using_CC_GPR:
   case RISCV::Select_FPR64IN32X_Using_CC_GPR:
     return emitSelectPseudo(MI, BB, Subtarget);
   case RISCV::BuildPairF64Pseudo:
   case RISCV::BuildPairF64Pseudo_INX:
     return emitBuildPairF64Pseudo(MI, BB, Subtarget);
   case RISCV::SplitF64Pseudo:
   case RISCV::SplitF64Pseudo_INX:
     return emitSplitF64Pseudo(MI, BB, Subtarget);
   case RISCV::PseudoQuietFLE_H:
     return emitQuietFCMP(MI, BB, RISCV::FLE_H, RISCV::FEQ_H, Subtarget);
+  case RISCV::PseudoQuietFLE_H_INX:
+    return emitQuietFCMP(MI, BB, RISCV::FLE_H_INX, RISCV::FEQ_H_INX, Subtarget);
   case RISCV::PseudoQuietFLT_H:
     return emitQuietFCMP(MI, BB, RISCV::FLT_H, RISCV::FEQ_H, Subtarget);
+  case RISCV::PseudoQuietFLT_H_INX:
+    return emitQuietFCMP(MI, BB, RISCV::FLT_H_INX, RISCV::FEQ_H_INX, Subtarget);
   case RISCV::PseudoQuietFLE_S:
     return emitQuietFCMP(MI, BB, RISCV::FLE_S, RISCV::FEQ_S, Subtarget);
   case RISCV::PseudoQuietFLE_S_INX:
     return emitQuietFCMP(MI, BB, RISCV::FLE_S_INX, RISCV::FEQ_S_INX, Subtarget);
   case RISCV::PseudoQuietFLT_S:
     return emitQuietFCMP(MI, BB, RISCV::FLT_S, RISCV::FEQ_S, Subtarget);
   case RISCV::PseudoQuietFLT_S_INX:
     return emitQuietFCMP(MI, BB, RISCV::FLT_S_INX, RISCV::FEQ_S_INX, Subtarget);
return emitVFROUND_NOEXCEPT_MASK(MI, BB, RISCV::PseudoVFCVT_X_F_V_M8_MASK,
                                      RISCV::PseudoVFCVT_F_X_V_M8_MASK);
   case RISCV::PseudoVFROUND_NOEXCEPT_V_MF2_MASK:
     return emitVFROUND_NOEXCEPT_MASK(MI, BB, RISCV::PseudoVFCVT_X_F_V_MF2_MASK,
                                      RISCV::PseudoVFCVT_F_X_V_MF2_MASK);
   case RISCV::PseudoVFROUND_NOEXCEPT_V_MF4_MASK:
     return emitVFROUND_NOEXCEPT_MASK(MI, BB, RISCV::PseudoVFCVT_X_F_V_MF4_MASK,
                                      RISCV::PseudoVFCVT_F_X_V_MF4_MASK);
   case RISCV::PseudoFROUND_H:
+  case RISCV::PseudoFROUND_H_INX:
   case RISCV::PseudoFROUND_S:
   case RISCV::PseudoFROUND_S_INX:
   case RISCV::PseudoFROUND_D:
   case RISCV::PseudoFROUND_D_INX:
   case RISCV::PseudoFROUND_D_IN32X:
     return emitFROUND(MI, BB, Subtarget);
   }
 }

 
 bool RISCVTargetLowering::shouldConvertFpToSat(unsigned Op, EVT FPVT,
                                                EVT VT) const {
   if (!isOperationLegalOrCustom(Op, VT) || !FPVT.isSimple())
     return false;
 
   switch (FPVT.getSimpleVT().SimpleTy) {
   case MVT::f16:
-    return Subtarget.hasStdExtZfhOrZfhmin();
+    return Subtarget.hasStdExtZfhOrZfhminOrZhinxOrZhinxmin();
   case MVT::f32:
-    return Subtarget.hasStdExtF();
+    return Subtarget.hasStdExtFOrZfinx();
   case MVT::f64:
     return Subtarget.hasStdExtD();
   default:
     return false;
   }
 }
 
 unsigned RISCVTargetLowering::getJumpTableEncoding() const {
bool RISCVTargetLowering::isFMAFasterThanFMulAndFAdd(const MachineFunction &MF,
   EVT SVT = VT.getScalarType();
 
   if (!SVT.isSimple())
     return false;
 
   switch (SVT.getSimpleVT().SimpleTy) {
   case MVT::f16:
     return VT.isVector() ? Subtarget.hasVInstructionsF16()
-                         : Subtarget.hasStdExtZfh();
+                         : Subtarget.hasStdExtZfhOrZhinx();
   case MVT::f32:
     return Subtarget.hasStdExtFOrZfinx();
   case MVT::f64:
     return Subtarget.hasStdExtDOrZdinx();
   default:
     break;
   }
 

llvm/lib/Target/RISCV/RISCVInstrInfoZfh.td

 
 // Zhinxmin and Zhinx
 
 def FPR16INX : RegisterOperand<GPRF16> {
   let ParserMatchClass = GPRAsFPR;
   let DecoderMethod = "DecodeGPRRegisterClass";
 }
 
-def ZfhExt           : ExtInfo<0, [HasStdExtZfh]>;
-def Zfh64Ext         : ExtInfo<0, [HasStdExtZfh,             IsRV64]>;
-def ZfhminExt        : ExtInfo<0, [HasStdExtZfhOrZfhmin]>;
-def ZhinxExt         : ExtInfo<1, [HasStdExtZhinx]>;
-def ZhinxminExt      : ExtInfo<1, [HasStdExtZhinxOrZhinxmin]>;
-def Zhinx64Ext       : ExtInfo<1, [HasStdExtZhinx,           IsRV64]>;
+def ZfhExt             : ExtInfo<0, [HasStdExtZfh]>;
+def Zfh64Ext           : ExtInfo<0, [HasStdExtZfh,             IsRV64]>;
+def ZfhminExt          : ExtInfo<0, [HasStdExtZfhOrZfhmin]>;
+def ZhinxExt           : ExtInfo<1, [HasStdExtZhinx]>;
+def ZhinxminExt        : ExtInfo<1, [HasStdExtZhinxOrZhinxmin]>;
+def Zhinx64Ext         : ExtInfo<1, [HasStdExtZhinx,           IsRV64]>;
 
-def ZfhminDExt       : ExtInfo<0, [HasStdExtZfhOrZfhmin,     HasStdExtD]>;
-def ZhinxminZdinxExt : ExtInfo<1, [HasStdExtZhinxOrZhinxmin, HasStdExtZdinx]>;
+def ZfhminDExt         : ExtInfo<0, [HasStdExtZfhOrZfhmin,     HasStdExtD]>;
+def ZhinxminZdinxExt   : ExtInfo<1, [HasStdExtZhinxOrZhinxmin, HasStdExtZdinx, IsRV64]>;
+def ZhinxminZdinx32Ext : ExtInfo<2, [HasStdExtZhinxOrZhinxmin, HasStdExtZdinx, IsRV32]>;
 
 def H     : ExtInfo_r<ZfhExt,     FPR16>;
 def H_INX : ExtInfo_r<ZhinxExt, FPR16INX>;
 
-def HH        : ExtInfo_rr<ZfhExt,           FPR16,    FPR16>;
-def HH_INX    : ExtInfo_rr<ZhinxExt,         FPR16INX, FPR16INX>;
-def XH        : ExtInfo_rr<ZfhExt,           GPR,      FPR16>;
-def XH_INX    : ExtInfo_rr<ZhinxExt,         GPR,      FPR16INX>;
-def HX        : ExtInfo_rr<ZfhExt,           FPR16,    GPR>;
-def HX_INX    : ExtInfo_rr<ZhinxExt,         FPR16INX, GPR>;
-def XH_64     : ExtInfo_rr<Zfh64Ext,         GPR,      FPR16>;
-def HX_64     : ExtInfo_rr<Zfh64Ext,         FPR16,    GPR>;
-def XH_INX_64 : ExtInfo_rr<Zhinx64Ext,       GPR,      FPR16INX>;
-def HX_INX_64 : ExtInfo_rr<Zhinx64Ext,       FPR16INX, GPR>;
-def HFmin     : ExtInfo_rr<ZfhminExt,        FPR16,    FPR32>;
-def HF_INXmin : ExtInfo_rr<ZhinxminExt,      FPR16INX, FPR32INX>;
-def HF_INX    : ExtInfo_rr<ZhinxExt,         FPR16INX, FPR32INX>;
-def FHmin     : ExtInfo_rr<ZfhminExt,        FPR32,    FPR16>;
-def FH_INXmin : ExtInfo_rr<ZhinxminExt,      FPR32INX, FPR16INX>;
-def FH_INX    : ExtInfo_rr<ZhinxExt,         FPR32INX, FPR16INX>;
-def DHmin     : ExtInfo_rr<ZfhminDExt,       FPR64,    FPR16>;
-def DH_INXmin : ExtInfo_rr<ZhinxminZdinxExt, FPR64INX, FPR16INX>;
-def HDmin     : ExtInfo_rr<ZfhminDExt,       FPR16,    FPR64>;
-def HD_INXmin : ExtInfo_rr<ZhinxminZdinxExt, FPR16INX, FPR64INX>;
+def HH          : ExtInfo_rr<ZfhExt,             FPR16,      FPR16>;
+def HH_INX      : ExtInfo_rr<ZhinxExt,           FPR16INX,   FPR16INX>;
+def XH          : ExtInfo_rr<ZfhExt,             GPR,        FPR16>;
+def XH_INX      : ExtInfo_rr<ZhinxExt,           GPR,        FPR16INX>;
+def HX          : ExtInfo_rr<ZfhExt,             FPR16,      GPR>;
+def HX_INX      : ExtInfo_rr<ZhinxExt,           FPR16INX,   GPR>;
+def XH_64       : ExtInfo_rr<Zfh64Ext,           GPR,        FPR16>;
+def HX_64       : ExtInfo_rr<Zfh64Ext,           FPR16,      GPR>;
+def XH_INX_64   : ExtInfo_rr<Zhinx64Ext,         GPR,        FPR16INX>;
+def HX_INX_64   : ExtInfo_rr<Zhinx64Ext,         FPR16INX,   GPR>;
+def HFmin       : ExtInfo_rr<ZfhminExt,          FPR16,      FPR32>;
+def HF_INXmin   : ExtInfo_rr<ZhinxminExt,        FPR16INX,   FPR32INX>;
+def HF_INX      : ExtInfo_rr<ZhinxExt,           FPR16INX,   FPR32INX>;
+def FHmin       : ExtInfo_rr<ZfhminExt,          FPR32,      FPR16>;
+def FH_INXmin   : ExtInfo_rr<ZhinxminExt,        FPR32INX,   FPR16INX>;
+def FH_INX      : ExtInfo_rr<ZhinxExt,           FPR32INX,   FPR16INX>;
+def DHmin       : ExtInfo_rr<ZfhminDExt,         FPR64,      FPR16>;
+def DH_INXmin   : ExtInfo_rr<ZhinxminZdinxExt,   FPR64INX,   FPR16INX>;
+def DH_INX32min : ExtInfo_rr<ZhinxminZdinx32Ext, FPR64IN32X, FPR16INX>;
+def HDmin       : ExtInfo_rr<ZfhminDExt,         FPR16,      FPR64>;
+def HD_INXmin   : ExtInfo_rr<ZhinxminZdinxExt,   FPR16INX,   FPR64INX>;
+def HD_INX32min : ExtInfo_rr<ZhinxminZdinx32Ext, FPR16INX,   FPR64IN32X>;
 
 defvar HINX     = [H,     H_INX];
 defvar HHINX    = [HH,    HH_INX];
 defvar XHINX    = [XH,    XH_INX];
 defvar HXINX    = [HX,    HX_INX];
 defvar XHIN64X  = [XH_64, XH_INX_64];
 defvar HXIN64X  = [HX_64, HX_INX_64];
 defvar HFINXmin = [HFmin, HF_INXmin];
 defvar FHINXmin = [FHmin, FH_INXmin];
-defvar DHINXmin = [DHmin, DH_INXmin];
-defvar HDINXmin = [HDmin, HD_INXmin];
+defvar DHINXmin = [DHmin, DH_INXmin, DH_INX32min];
+defvar HDINXmin = [HDmin, HD_INXmin, HD_INX32min];
 
 //===----------------------------------------------------------------------===//
 // Instructions
 //===----------------------------------------------------------------------===//
 
 let Predicates = [HasStdExtZfhOrZfhmin] in {
 def FLH : FPLoad_r<0b001, "flh", FPR16, WriteFLD16>;
 

 def : InstAlias<"fmv.h $rd, $rs",  (FSGNJ_H_INX  FPR16INX:$rd, FPR16INX:$rs, FPR16INX:$rs)>;
 def : InstAlias<"fabs.h $rd, $rs", (FSGNJX_H_INX FPR16INX:$rd, FPR16INX:$rs, FPR16INX:$rs)>;
 def : InstAlias<"fneg.h $rd, $rs", (FSGNJN_H_INX FPR16INX:$rd, FPR16INX:$rs, FPR16INX:$rs)>;
 
 def : InstAlias<"fgt.h $rd, $rs, $rt",
                 (FLT_H_INX GPR:$rd, FPR16INX:$rt, FPR16INX:$rs), 0>;
 def : InstAlias<"fge.h $rd, $rs, $rt",
                 (FLE_H_INX GPR:$rd, FPR16INX:$rt, FPR16INX:$rs), 0>;
-} // Predicates = [HasStdExtZhinx]
+
+let usesCustomInserter = 1 in {
+def PseudoQuietFLE_H_INX : PseudoQuietFCMP<FPR16INX>;
+def PseudoQuietFLT_H_INX : PseudoQuietFCMP<FPR16INX>;
+}
+} // Predicates = [HasStdExtZhinxOrZhinxmin]
 
 //===----------------------------------------------------------------------===//
 // Pseudo-instructions and codegen patterns
 //===----------------------------------------------------------------------===//
 
 let Predicates = [HasStdExtZfh] in {
 
 /// Float conversion operations

 
 // fnmadd: -rs1 * rs2 - rs3
 def : Pat<(any_fma (fneg FPR16:$rs1), FPR16:$rs2, (fneg FPR16:$rs3)),
           (FNMADD_H FPR16:$rs1, FPR16:$rs2, FPR16:$rs3, FRM_DYN)>;
 
 // fnmadd: -(rs1 * rs2 + rs3) (the nsz flag on the FMA)
 def : Pat<(fneg (any_fma_nsz FPR16:$rs1, FPR16:$rs2, FPR16:$rs3)),
           (FNMADD_H FPR16:$rs1, FPR16:$rs2, FPR16:$rs3, FRM_DYN)>;
+} // Predicates = [HasStdExtZfh]
+
+let Predicates = [HasStdExtZhinx] in {
+
+/// Float conversion operations
+
+// [u]int32<->float conversion patterns must be gated on IsRV32 or IsRV64, so
+// are defined later.
+
+/// Float arithmetic operations
+
+def : PatFprFprDynFrm<any_fadd, FADD_H_INX, FPR16INX>;
+def : PatFprFprDynFrm<any_fsub, FSUB_H_INX, FPR16INX>;
+def : PatFprFprDynFrm<any_fmul, FMUL_H_INX, FPR16INX>;
+def : PatFprFprDynFrm<any_fdiv, FDIV_H_INX, FPR16INX>;
+
+def : Pat<(any_fsqrt FPR16INX:$rs1), (FSQRT_H_INX FPR16INX:$rs1, FRM_DYN)>;
+
+def : Pat<(fneg FPR16INX:$rs1), (FSGNJN_H_INX $rs1, $rs1)>;
+def : Pat<(fabs FPR16INX:$rs1), (FSGNJX_H_INX $rs1, $rs1)>;
+
+def : Pat<(riscv_fpclass FPR16INX:$rs1), (FCLASS_H_INX $rs1)>;
+
+def : PatFprFpr<fcopysign, FSGNJ_H_INX, FPR16INX>;
+def : Pat<(fcopysign FPR16INX:$rs1, (fneg FPR16INX:$rs2)), (FSGNJN_H_INX $rs1, $rs2)>;
+def : Pat<(fcopysign FPR16INX:$rs1, FPR32INX:$rs2),
+          (FSGNJ_H_INX $rs1, (FCVT_H_S_INX $rs2, FRM_DYN))>;
+
+// fmadd: rs1 * rs2 + rs3
+def : Pat<(any_fma FPR16INX:$rs1, FPR16INX:$rs2, FPR16INX:$rs3),
+          (FMADD_H_INX $rs1, $rs2, $rs3, FRM_DYN)>;
+
+// fmsub: rs1 * rs2 - rs3
+def : Pat<(any_fma FPR16INX:$rs1, FPR16INX:$rs2, (fneg FPR16INX:$rs3)),
+          (FMSUB_H_INX FPR16INX:$rs1, FPR16INX:$rs2, FPR16INX:$rs3, FRM_DYN)>;
+
+// fnmsub: -rs1 * rs2 + rs3
+def : Pat<(any_fma (fneg FPR16INX:$rs1), FPR16INX:$rs2, FPR16INX:$rs3),
+          (FNMSUB_H_INX FPR16INX:$rs1, FPR16INX:$rs2, FPR16INX:$rs3, FRM_DYN)>;
+
+// fnmadd: -rs1 * rs2 - rs3
+def : Pat<(any_fma (fneg FPR16INX:$rs1), FPR16INX:$rs2, (fneg FPR16INX:$rs3)),
+          (FNMADD_H_INX FPR16INX:$rs1, FPR16INX:$rs2, FPR16INX:$rs3, FRM_DYN)>;
+
+// fnmadd: -(rs1 * rs2 + rs3) (the nsz flag on the FMA)
+def : Pat<(fneg (any_fma_nsz FPR16INX:$rs1, FPR16INX:$rs2, FPR16INX:$rs3)),
+          (FNMADD_H_INX FPR16INX:$rs1, FPR16INX:$rs2, FPR16INX:$rs3, FRM_DYN)>;
+} // Predicates = [HasStdExtZhinx]
 
 // The ratified 20191213 ISA spec defines fmin and fmax in a way that matches
 // LLVM's fminnum and fmaxnum
 // <https://github.com/riscv/riscv-isa-manual/commit/cd20cee7efd9bac7c5aa127ec3b451749d2b3cce>.
-def : PatFprFpr<fminnum, FMIN_H, FPR16>;
-def : PatFprFpr<fmaxnum, FMAX_H, FPR16>;
+defm : PatFprFpr_m<fminnum, FMIN_H, HINX>;
+defm : PatFprFpr_m<fmaxnum, FMAX_H, HINX>;
 
 /// Setcc
 // FIXME: SETEQ/SETLT/SETLE imply nonans, can we pick better instructions for
 // strict versions of those.
 
 // Match non-signaling FEQ_D
-def : PatSetCC<FPR16, any_fsetcc, SETEQ, FEQ_H>;
-def : PatSetCC<FPR16, any_fsetcc, SETOEQ, FEQ_H>;
-def : PatSetCC<FPR16, strict_fsetcc, SETLT, PseudoQuietFLT_H>;
-def : PatSetCC<FPR16, strict_fsetcc, SETOLT, PseudoQuietFLT_H>;
-def : PatSetCC<FPR16, strict_fsetcc, SETLE, PseudoQuietFLE_H>;
-def : PatSetCC<FPR16, strict_fsetcc, SETOLE, PseudoQuietFLE_H>;
+defm : PatSetCC_m<any_fsetcc,    SETEQ,  FEQ_H,            HINX>;
+defm : PatSetCC_m<any_fsetcc,    SETOEQ, FEQ_H,            HINX>;
+defm : PatSetCC_m<strict_fsetcc, SETLT,  PseudoQuietFLT_H, HINX>;
+defm : PatSetCC_m<strict_fsetcc, SETOLT, PseudoQuietFLT_H, HINX>;
+defm : PatSetCC_m<strict_fsetcc, SETLE,  PseudoQuietFLE_H, HINX>;
+defm : PatSetCC_m<strict_fsetcc, SETOLE, PseudoQuietFLE_H, HINX>;
 
+let Predicates = [HasStdExtZfh] in {
 // Match signaling FEQ_H
 def : Pat<(strict_fsetccs FPR16:$rs1, FPR16:$rs2, SETEQ),
           (AND (FLE_H $rs1, $rs2),
                (FLE_H $rs2, $rs1))>;
 def : Pat<(strict_fsetccs FPR16:$rs1, FPR16:$rs2, SETOEQ),
           (AND (FLE_H $rs1, $rs2),
                (FLE_H $rs2, $rs1))>;
 // If both operands are the same, use a single FLE.
 def : Pat<(strict_fsetccs FPR16:$rs1, FPR16:$rs1, SETEQ),
           (FLE_H $rs1, $rs1)>;
 def : Pat<(strict_fsetccs FPR16:$rs1, FPR16:$rs1, SETOEQ),
           (FLE_H $rs1, $rs1)>;
+} // Predicates = [HasStdExtZfh]
+
+let Predicates = [HasStdExtZhinx] in {
+// Match signaling FEQ_H
+def : Pat<(strict_fsetccs FPR16INX:$rs1, FPR16INX:$rs2, SETEQ),
+          (AND (FLE_H_INX $rs1, $rs2),
+               (FLE_H_INX $rs2, $rs1))>;
+def : Pat<(strict_fsetccs FPR16INX:$rs1, FPR16INX:$rs2, SETOEQ),
+          (AND (FLE_H_INX $rs1, $rs2),
+               (FLE_H_INX $rs2, $rs1))>;
+// If both operands are the same, use a single FLE.
+def : Pat<(strict_fsetccs FPR16INX:$rs1, FPR16INX:$rs1, SETEQ),
+          (FLE_H_INX $rs1, $rs1)>;
+def : Pat<(strict_fsetccs FPR16INX:$rs1, FPR16INX:$rs1, SETOEQ),
+          (FLE_H_INX $rs1, $rs1)>;
+} // Predicates = [HasStdExtZhinx]
 
-def : PatSetCC<FPR16, any_fsetccs, SETLT, FLT_H>;
-def : PatSetCC<FPR16, any_fsetccs, SETOLT, FLT_H>;
-def : PatSetCC<FPR16, any_fsetccs, SETLE, FLE_H>;
-def : PatSetCC<FPR16, any_fsetccs, SETOLE, FLE_H>;
+defm : PatSetCC_m<any_fsetccs, SETLT,  FLT_H, HINX>;
+defm : PatSetCC_m<any_fsetccs, SETOLT, FLT_H, HINX>;
+defm : PatSetCC_m<any_fsetccs, SETLE,  FLE_H, HINX>;
+defm : PatSetCC_m<any_fsetccs, SETOLE, FLE_H, HINX>;
 
+let Predicates = [HasStdExtZfh] in {
 defm Select_FPR16 : SelectCC_GPR_rrirr<FPR16>;
 
 def PseudoFROUND_H : PseudoFROUND<FPR16>;
 } // Predicates = [HasStdExtZfh]
 
+let Predicates = [HasStdExtZhinx] in {
+defm Select_FPR16INX : SelectCC_GPR_rrirr<FPR16INX>;
+
+def PseudoFROUND_H_INX : PseudoFROUND<FPR16INX>;
+} // Predicates = [HasStdExtZhinx]
+
 let Predicates = [HasStdExtZfhOrZfhmin] in {
 /// Loads
-
 defm : LdPat<load, FLH, f16>;
 
 /// Stores
-
 defm : StPat<store, FSH, FPR16, f16>;
+} // Predicates = [HasStdExtZfhOrZfhmin]
+
+let Predicates = [HasStdExtZhinxOrZhinxmin] in {
+/// Loads
+def : Pat<(f16 (load GPR:$rs1)), (COPY_TO_REGCLASS (LH GPR:$rs1, 0), GPRF16)>;
+
+/// Stores
+def : Pat<(store (f16 FPR16INX:$rs2), GPR:$rs1),
+          (SH (COPY_TO_REGCLASS FPR16INX:$rs2, GPR), GPR:$rs1, 0)>;
+} // Predicates = [HasStdExtZhinxOrZhinxmin]
 
+let Predicates = [HasStdExtZfhOrZfhmin] in {
 /// Float conversion operations
 
 // f32 -> f16, f16 -> f32
 def : Pat<(any_fpround FPR32:$rs1), (FCVT_H_S FPR32:$rs1, FRM_DYN)>;
 def : Pat<(any_fpextend FPR16:$rs1), (FCVT_S_H FPR16:$rs1)>;
 
 // Moves (no conversion)
 def : Pat<(riscv_fmv_h_x GPR:$src), (FMV_H_X GPR:$src)>;
 def : Pat<(riscv_fmv_x_anyexth FPR16:$src), (FMV_X_H FPR16:$src)>;
 def : Pat<(riscv_fmv_x_signexth FPR16:$src), (FMV_X_H FPR16:$src)>;
 
 def : Pat<(fcopysign FPR32:$rs1, FPR16:$rs2), (FSGNJ_S $rs1, (FCVT_S_H $rs2))>;
 } // Predicates = [HasStdExtZfhOrZfhmin]
 
+let Predicates = [HasStdExtZhinxOrZhinxmin] in {
+/// Float conversion operations
+
+// f32 -> f16, f16 -> f32
+def : Pat<(any_fpround FPR32INX:$rs1), (FCVT_H_S_INX FPR32INX:$rs1, FRM_DYN)>;
+def : Pat<(any_fpextend FPR16INX:$rs1), (FCVT_S_H_INX FPR16INX:$rs1)>;
+
+// Moves (no conversion)
+def : Pat<(riscv_fmv_h_x GPR:$src), (COPY_TO_REGCLASS GPR:$src, GPR)>;
+def : Pat<(riscv_fmv_x_anyexth FPR16INX:$src), (COPY_TO_REGCLASS FPR16INX:$src, GPR)>;
+def : Pat<(riscv_fmv_x_signexth FPR16INX:$src), (COPY_TO_REGCLASS FPR16INX:$src, GPR)>;
+
+def : Pat<(fcopysign FPR32INX:$rs1, FPR16INX:$rs2), (FSGNJ_S_INX $rs1, (FCVT_S_H_INX $rs2))>;
+} // Predicates = [HasStdExtZhinxOrZhinxmin]
+
 let Predicates = [HasStdExtZfh, IsRV32] in {
 // half->[u]int. Round-to-zero must be used.
 def : Pat<(i32 (any_fp_to_sint FPR16:$rs1)), (FCVT_W_H $rs1, 0b001)>;
 def : Pat<(i32 (any_fp_to_uint FPR16:$rs1)), (FCVT_WU_H $rs1, 0b001)>;
 
 // Saturating half->[u]int32.
 def : Pat<(i32 (riscv_fcvt_x FPR16:$rs1, timm:$frm)), (FCVT_W_H $rs1, timm:$frm)>;
 def : Pat<(i32 (riscv_fcvt_xu FPR16:$rs1, timm:$frm)), (FCVT_WU_H $rs1, timm:$frm)>;
 
 // half->int32 with current rounding mode.
 def : Pat<(i32 (any_lrint FPR16:$rs1)), (FCVT_W_H $rs1, FRM_DYN)>;
 
 // half->int32 rounded to nearest with ties rounded away from zero.
 def : Pat<(i32 (any_lround FPR16:$rs1)), (FCVT_W_H $rs1, FRM_RMM)>;
 
 // [u]int->half. Match GCC and default to using dynamic rounding mode.
 def : Pat<(any_sint_to_fp (i32 GPR:$rs1)), (FCVT_H_W $rs1, FRM_DYN)>;
 def : Pat<(any_uint_to_fp (i32 GPR:$rs1)), (FCVT_H_WU $rs1, FRM_DYN)>;
 } // Predicates = [HasStdExtZfh, IsRV32]
 
+let Predicates = [HasStdExtZhinx, IsRV32] in {
+// half->[u]int. Round-to-zero must be used.
+def : Pat<(i32 (any_fp_to_sint FPR16INX:$rs1)), (FCVT_W_H_INX $rs1, 0b001)>;
+def : Pat<(i32 (any_fp_to_uint FPR16INX:$rs1)), (FCVT_WU_H_INX $rs1, 0b001)>;
+
+// Saturating float->[u]int32.
+def : Pat<(i32 (riscv_fcvt_x FPR16INX:$rs1, timm:$frm)), (FCVT_W_H_INX $rs1, timm:$frm)>;
+def : Pat<(i32 (riscv_fcvt_xu FPR16INX:$rs1, timm:$frm)), (FCVT_WU_H_INX $rs1, timm:$frm)>;
+
+// half->int32 with current rounding mode.
+def : Pat<(i32 (any_lrint FPR16INX:$rs1)), (FCVT_W_H_INX $rs1, FRM_DYN)>;
+
+// half->int32 rounded to nearest with ties rounded away from zero.
+def : Pat<(i32 (any_lround FPR16INX:$rs1)), (FCVT_W_H_INX $rs1, FRM_RMM)>;
+
+// [u]int->half. Match GCC and default to using dynamic rounding mode.
+def : Pat<(any_sint_to_fp (i32 GPR:$rs1)), (FCVT_H_W_INX $rs1, FRM_DYN)>;
+def : Pat<(any_uint_to_fp (i32 GPR:$rs1)), (FCVT_H_WU_INX $rs1, FRM_DYN)>;
+} // Predicates = [HasStdExtZhinx, IsRV32]
+
 let Predicates = [HasStdExtZfh, IsRV64] in {
 // Use target specific isd nodes to help us remember the result is sign
 // extended. Matching sext_inreg+fptoui/fptosi may cause the conversion to be
 // duplicated if it has another user that didn't need the sign_extend.
 def : Pat<(riscv_any_fcvt_w_rv64 FPR16:$rs1, timm:$frm),  (FCVT_W_H $rs1, timm:$frm)>;
 def : Pat<(riscv_any_fcvt_wu_rv64 FPR16:$rs1, timm:$frm), (FCVT_WU_H $rs1, timm:$frm)>;
 
 // half->[u]int64. Round-to-zero must be used.

 
 // [u]int->fp. Match GCC and default to using dynamic rounding mode.
 def : Pat<(any_sint_to_fp (i64 (sexti32 (i64 GPR:$rs1)))), (FCVT_H_W $rs1, FRM_DYN)>;
 def : Pat<(any_uint_to_fp (i64 (zexti32 (i64 GPR:$rs1)))), (FCVT_H_WU $rs1, FRM_DYN)>;
 def : Pat<(any_sint_to_fp (i64 GPR:$rs1)), (FCVT_H_L $rs1, FRM_DYN)>;
 def : Pat<(any_uint_to_fp (i64 GPR:$rs1)), (FCVT_H_LU $rs1, FRM_DYN)>;
 } // Predicates = [HasStdExtZfh, IsRV64]
 
+let Predicates = [HasStdExtZhinx, IsRV64] in {
+// Use target specific isd nodes to help us remember the result is sign
+// extended. Matching sext_inreg+fptoui/fptosi may cause the conversion to be
+// duplicated if it has another user that didn't need the sign_extend.
+def : Pat<(riscv_any_fcvt_w_rv64 FPR16INX:$rs1, timm:$frm),  (FCVT_W_H_INX $rs1, timm:$frm)>;
+def : Pat<(riscv_any_fcvt_wu_rv64 FPR16INX:$rs1, timm:$frm), (FCVT_WU_H_INX $rs1, timm:$frm)>;
+
+// half->[u]int64. Round-to-zero must be used.
+def : Pat<(i64 (any_fp_to_sint FPR16INX:$rs1)), (FCVT_L_H_INX $rs1, 0b001)>;
+def : Pat<(i64 (any_fp_to_uint FPR16INX:$rs1)), (FCVT_LU_H_INX $rs1, 0b001)>;
+
+// Saturating float->[u]int64.
+def : Pat<(i64 (riscv_fcvt_x FPR16INX:$rs1, timm:$frm)), (FCVT_L_H_INX $rs1, timm:$frm)>;
+def : Pat<(i64 (riscv_fcvt_xu FPR16INX:$rs1, timm:$frm)), (FCVT_LU_H_INX $rs1, timm:$frm)>;
+
+// half->int64 with current rounding mode.
+def : Pat<(i64 (any_lrint FPR16INX:$rs1)), (FCVT_L_H_INX $rs1, FRM_DYN)>;
+def : Pat<(i64 (any_llrint FPR16INX:$rs1)), (FCVT_L_H_INX $rs1, FRM_DYN)>;
+
+// half->int64 rounded to nearest with ties rounded away from zero.
+def : Pat<(i64 (any_lround FPR16INX:$rs1)), (FCVT_L_H_INX $rs1, FRM_RMM)>;
+def : Pat<(i64 (any_llround FPR16INX:$rs1)), (FCVT_L_H_INX $rs1, FRM_RMM)>;
+
+// [u]int->fp. Match GCC and default to using dynamic rounding mode.
+def : Pat<(any_sint_to_fp (i64 (sexti32 (i64 GPR:$rs1)))), (FCVT_H_W_INX $rs1, FRM_DYN)>;
+def : Pat<(any_uint_to_fp (i64 (zexti32 (i64 GPR:$rs1)))), (FCVT_H_WU_INX $rs1, FRM_DYN)>;
+def : Pat<(any_sint_to_fp (i64 GPR:$rs1)), (FCVT_H_L_INX $rs1, FRM_DYN)>;
+def : Pat<(any_uint_to_fp (i64 GPR:$rs1)), (FCVT_H_LU_INX $rs1, FRM_DYN)>;
+} // Predicates = [HasStdExtZhinx, IsRV64]
+
 let Predicates = [HasStdExtZfhOrZfhmin, HasStdExtD] in {
 /// Float conversion operations
 // f64 -> f16, f16 -> f64
 def : Pat<(any_fpround FPR64:$rs1), (FCVT_H_D FPR64:$rs1, FRM_DYN)>;
 def : Pat<(any_fpextend FPR16:$rs1), (FCVT_D_H FPR16:$rs1)>;
 
 /// Float arithmetic operations
 def : Pat<(fcopysign FPR16:$rs1, FPR64:$rs2),
           (FSGNJ_H $rs1, (FCVT_H_D $rs2, FRM_DYN))>;
 def : Pat<(fcopysign FPR64:$rs1, FPR16:$rs2), (FSGNJ_D $rs1, (FCVT_D_H $rs2))>;
 } // Predicates = [HasStdExtZfhOrZfhmin, HasStdExtD]
 
+let Predicates = [HasStdExtZhinxOrZhinxmin, HasStdExtZdinx, IsRV32] in {
+/// Float conversion operations
+// f64 -> f16, f16 -> f64
+def : Pat<(any_fpround FPR64IN32X:$rs1), (FCVT_H_D_IN32X FPR64IN32X:$rs1, FRM_DYN)>;
+def : Pat<(any_fpextend FPR16INX:$rs1), (FCVT_D_H_IN32X FPR16INX:$rs1)>;
+
+/// Float arithmetic operations
+def : Pat<(fcopysign FPR16INX:$rs1, FPR64IN32X:$rs2),
+          (FSGNJ_H_INX $rs1, (FCVT_H_D_IN32X $rs2, 0b111))>;
+def : Pat<(fcopysign FPR64IN32X:$rs1, FPR16INX:$rs2), (FSGNJ_D_IN32X $rs1, (FCVT_D_H_IN32X $rs2))>;
+} // Predicates = [HasStdExtZhinxOrZhinxmin, HasStdExtZdinx, IsRV32]
+
+let Predicates = [HasStdExtZhinxOrZhinxmin, HasStdExtZdinx, IsRV64] in {
+/// Float conversion operations
+// f64 -> f16, f16 -> f64
+def : Pat<(any_fpround FPR64INX:$rs1), (FCVT_H_D_INX FPR64INX:$rs1, FRM_DYN)>;
+def : Pat<(any_fpextend FPR16INX:$rs1), (FCVT_D_H_INX FPR16INX:$rs1)>;
+
+/// Float arithmetic operations
+def : Pat<(fcopysign FPR16INX:$rs1, FPR64INX:$rs2),
+          (FSGNJ_H_INX $rs1, (FCVT_H_D_INX $rs2, 0b111))>;
+def : Pat<(fcopysign FPR64INX:$rs1, FPR16INX:$rs2), (FSGNJ_D_INX $rs1, (FCVT_D_H_INX $rs2))>;
+} // Predicates = [HasStdExtZhinxOrZhinxmin, HasStdExtZdinx, IsRV64]
+
 let Predicates = [HasStdExtZfhmin, NoStdExtZfh, IsRV32] in {
 // half->[u]int. Round-to-zero must be used.
 def : Pat<(i32 (any_fp_to_sint FPR16:$rs1)), (FCVT_W_S (FCVT_S_H $rs1), FRM_RTZ)>;
 def : Pat<(i32 (any_fp_to_uint FPR16:$rs1)), (FCVT_WU_S (FCVT_S_H $rs1), FRM_RTZ)>;
 
 // half->int32 with current rounding mode.
 def : Pat<(i32 (any_lrint FPR16:$rs1)), (FCVT_W_S (FCVT_S_H $rs1), FRM_DYN)>;
 
 // half->int32 rounded to nearest with ties rounded away from zero.
 def : Pat<(i32 (any_lround FPR16:$rs1)), (FCVT_W_S (FCVT_S_H $rs1), FRM_RMM)>;
 
 // [u]int->half. Match GCC and default to using dynamic rounding mode.
 def : Pat<(any_sint_to_fp (i32 GPR:$rs1)), (FCVT_H_S (FCVT_S_W $rs1, FRM_DYN), FRM_DYN)>;
 def : Pat<(any_uint_to_fp (i32 GPR:$rs1)), (FCVT_H_S (FCVT_S_WU $rs1, FRM_DYN), FRM_DYN)>;
 } // Predicates = [HasStdExtZfhmin, NoStdExtZfh, IsRV32]
 
+let Predicates = [HasStdExtZhinxmin, NoStdExtZhinx, IsRV32] in {
+// half->[u]int. Round-to-zero must be used.
+def : Pat<(i32 (any_fp_to_sint FPR16INX:$rs1)), (FCVT_W_S_INX (FCVT_S_H_INX $rs1), FRM_RTZ)>;
+def : Pat<(i32 (any_fp_to_uint FPR16INX:$rs1)), (FCVT_WU_S_INX (FCVT_S_H_INX $rs1), FRM_RTZ)>;
+
+// half->int32 with current rounding mode.
+def : Pat<(i32 (any_lrint FPR16INX:$rs1)), (FCVT_W_S_INX (FCVT_S_H_INX $rs1), FRM_DYN)>;
+
+// half->int32 rounded to nearest with ties rounded away from zero.
+def : Pat<(i32 (any_lround FPR16INX:$rs1)), (FCVT_W_S_INX (FCVT_S_H_INX $rs1), FRM_RMM)>;
+
+// [u]int->half. Match GCC and default to using dynamic rounding mode.
+def : Pat<(any_sint_to_fp (i32 GPR:$rs1)), (FCVT_H_S_INX (FCVT_S_W_INX $rs1, FRM_DYN), FRM_DYN)>;
+def : Pat<(any_uint_to_fp (i32 GPR:$rs1)), (FCVT_H_S_INX (FCVT_S_WU_INX $rs1, FRM_DYN), FRM_DYN)>;
+} // Predicates = [HasStdExtZhinxmin, NoStdExtZhinx, IsRV32]
+
 let Predicates = [HasStdExtZfhmin, NoStdExtZfh, IsRV64] in {
 // half->[u]int64. Round-to-zero must be used.
 def : Pat<(i64 (any_fp_to_sint FPR16:$rs1)), (FCVT_L_S (FCVT_S_H $rs1), FRM_RTZ)>;
 def : Pat<(i64 (any_fp_to_uint FPR16:$rs1)), (FCVT_LU_S (FCVT_S_H $rs1), FRM_RTZ)>;
 
 // half->int64 with current rounding mode.
 def : Pat<(i64 (any_lrint FPR16:$rs1)), (FCVT_L_S (FCVT_S_H $rs1), FRM_DYN)>;
 def : Pat<(i64 (any_llrint FPR16:$rs1)), (FCVT_L_S (FCVT_S_H $rs1), FRM_DYN)>;
 
 // half->int64 rounded to nearest with ties rounded away from zero.
 def : Pat<(i64 (any_lround FPR16:$rs1)), (FCVT_L_S (FCVT_S_H $rs1), FRM_RMM)>;
 def : Pat<(i64 (any_llround FPR16:$rs1)), (FCVT_L_S (FCVT_S_H $rs1), FRM_RMM)>;
 
 // [u]int->fp. Match GCC and default to using dynamic rounding mode.
 def : Pat<(any_sint_to_fp (i64 GPR:$rs1)), (FCVT_H_S (FCVT_S_L $rs1, FRM_DYN), FRM_DYN)>;
 def : Pat<(any_uint_to_fp (i64 GPR:$rs1)), (FCVT_H_S (FCVT_S_LU $rs1, FRM_DYN), FRM_DYN)>;
 } // Predicates = [HasStdExtZfhmin, NoStdExtZfh, IsRV64]
+
+let Predicates = [HasStdExtZhinxmin, NoStdExtZhinx, IsRV64] in {
+// half->[u]int64. Round-to-zero must be used.
+def : Pat<(i64 (any_fp_to_sint FPR16INX:$rs1)), (FCVT_L_S_INX (FCVT_S_H_INX $rs1), FRM_RTZ)>;
+def : Pat<(i64 (any_fp_to_uint FPR16INX:$rs1)), (FCVT_LU_S_INX (FCVT_S_H_INX $rs1), FRM_RTZ)>;
+
+// half->int64 with current rounding mode.
+def : Pat<(i64 (any_lrint FPR16INX:$rs1)), (FCVT_L_S_INX (FCVT_S_H_INX $rs1), FRM_DYN)>;
+def : Pat<(i64 (any_llrint FPR16INX:$rs1)), (FCVT_L_S_INX (FCVT_S_H_INX $rs1), FRM_DYN)>;
+
+// half->int64 rounded to nearest with ties rounded away from zero.
+def : Pat<(i64 (any_lround FPR16INX:$rs1)), (FCVT_L_S_INX (FCVT_S_H_INX $rs1), FRM_RMM)>;
+def : Pat<(i64 (any_llround FPR16INX:$rs1)), (FCVT_L_S_INX (FCVT_S_H_INX $rs1), FRM_RMM)>;
+
+// [u]int->fp. Match GCC and default to using dynamic rounding mode.
+def : Pat<(any_sint_to_fp (i64 GPR:$rs1)), (FCVT_H_S_INX (FCVT_S_L_INX $rs1, FRM_DYN), FRM_DYN)>;
+def : Pat<(any_uint_to_fp (i64 GPR:$rs1)), (FCVT_H_S_INX (FCVT_S_LU_INX $rs1, FRM_DYN), FRM_DYN)>;
+} // Predicates = [HasStdExtZhinxmin, NoStdExtZhinx, IsRV64]

llvm/lib/Target/RISCV/RISCVSubtarget.h

#define GET_SUBTARGETINFO_MACRO(ATTRIBUTE, DEFAULT, GETTER) \
   bool GETTER() const { return ATTRIBUTE; }
 #include "RISCVGenSubtargetInfo.inc"
 
   bool hasStdExtCOrZca() const { return HasStdExtC || HasStdExtZca; }
   bool hasStdExtZvl() const { return ZvlLen != 0; }
   bool hasStdExtFOrZfinx() const { return HasStdExtF || HasStdExtZfinx; }
   bool hasStdExtDOrZdinx() const { return HasStdExtD || HasStdExtZdinx; }
   bool hasStdExtZfhOrZfhmin() const { return HasStdExtZfh || HasStdExtZfhmin; }
+  bool hasStdExtZfhOrZhinx() const { return HasStdExtZfh || HasStdExtZhinx; }
+  bool hasStdExtZhinxOrZhinxmin() const {
+    return HasStdExtZhinx || HasStdExtZhinxmin;
+  }
+  bool hasStdExtZfhOrZfhminOrZhinxOrZhinxmin() const {
+    return hasStdExtZfhOrZfhmin() || hasStdExtZhinxOrZhinxmin();
+  }
   bool is64Bit() const { return IsRV64; }
   MVT getXLenVT() const { return XLenVT; }
   unsigned getXLen() const { return XLen; }
   unsigned getFLen() const {
     if (HasStdExtD)
       return 64;
 
     if (HasStdExtF)

llvm/test/CodeGen/RISCV/half-arith-strict.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -mattr=+zfh -verify-machineinstrs \
 ; RUN:   -disable-strictnode-mutation -target-abi ilp32f < %s | FileCheck %s
 ; RUN: llc -mtriple=riscv64 -mattr=+zfh -verify-machineinstrs \
 ; RUN:   -disable-strictnode-mutation -target-abi lp64f < %s | FileCheck %s
+; RUN: llc -mtriple=riscv32 -mattr=+zhinx -verify-machineinstrs \
+; RUN:   -disable-strictnode-mutation -target-abi ilp32 < %s \
+; RUN:   | FileCheck -check-prefix=CHECK-ZHINX %s
+; RUN: llc -mtriple=riscv64 -mattr=+zhinx -verify-machineinstrs \
+; RUN:   -disable-strictnode-mutation -target-abi lp64 < %s \
+; RUN:   | FileCheck -check-prefix=CHECK-ZHINX %s
 ; RUN: llc -mtriple=riscv32 -mattr=+zfhmin -verify-machineinstrs \
 ; RUN:   -disable-strictnode-mutation -target-abi ilp32f < %s \
 ; RUN:   | FileCheck -check-prefix=CHECK-ZFHMIN %s
 ; RUN: llc -mtriple=riscv64 -mattr=+zfhmin -verify-machineinstrs \
 ; RUN:   -disable-strictnode-mutation -target-abi lp64f < %s \
 ; RUN:  | FileCheck -check-prefix=CHECK-ZFHMIN %s
+; RUN: llc -mtriple=riscv32 -mattr=+zhinxmin -verify-machineinstrs \
+; RUN:   -disable-strictnode-mutation -target-abi ilp32 < %s \
+; RUN:   | FileCheck -check-prefix=CHECK-ZHINXMIN %s
+; RUN: llc -mtriple=riscv64 -mattr=+zhinxmin -verify-machineinstrs \
+; RUN:   -disable-strictnode-mutation -target-abi lp64 < %s \
+; RUN:   | FileCheck -check-prefix=CHECK-ZHINXMIN %s
 
 ; FIXME: We can't test without Zfh because soft promote legalization isn't
 ; implemented in SelectionDAG for STRICT nodes.
 
 define half @fadd_h(half %a, half %b) nounwind strictfp {
 ; CHECK-LABEL: fadd_h:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    fadd.h fa0, fa0, fa1
 ; CHECK-NEXT:    ret
 ;
+; CHECK-ZHINX-LABEL: fadd_h:
+; CHECK-ZHINX:       # %bb.0:
+; CHECK-ZHINX-NEXT:    fadd.h a0, a0, a1
+; CHECK-ZHINX-NEXT:    ret
+;
 ; CHECK-ZFHMIN-LABEL: fadd_h:
 ; CHECK-ZFHMIN:       # %bb.0:
 ; CHECK-ZFHMIN-NEXT:    fcvt.s.h fa5, fa1
 ; CHECK-ZFHMIN-NEXT:    fcvt.s.h fa4, fa0
 ; CHECK-ZFHMIN-NEXT:    fadd.s fa5, fa4, fa5
 ; CHECK-ZFHMIN-NEXT:    fcvt.h.s fa0, fa5
 ; CHECK-ZFHMIN-NEXT:    ret
+;
+; CHECK-ZHINXMIN-LABEL: fadd_h:
+; CHECK-ZHINXMIN:       # %bb.0:
+; CHECK-ZHINXMIN-NEXT:    fcvt.s.h a1, a1
+; CHECK-ZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECK-ZHINXMIN-NEXT:    fadd.s a0, a0, a1
+; CHECK-ZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; CHECK-ZHINXMIN-NEXT:    ret
   %1 = call half @llvm.experimental.constrained.fadd.f16(half %a, half %b, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
   ret half %1
 }
 declare half @llvm.experimental.constrained.fadd.f16(half, half, metadata, metadata)
 
 define half @fsub_h(half %a, half %b) nounwind strictfp {
 ; CHECK-LABEL: fsub_h:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    fsub.h fa0, fa0, fa1
 ; CHECK-NEXT:    ret
 ;
+; CHECK-ZHINX-LABEL: fsub_h:
+; CHECK-ZHINX:       # %bb.0:
+; CHECK-ZHINX-NEXT:    fsub.h a0, a0, a1
+; CHECK-ZHINX-NEXT:    ret
+;
 ; CHECK-ZFHMIN-LABEL: fsub_h:
 ; CHECK-ZFHMIN:       # %bb.0:
 ; CHECK-ZFHMIN-NEXT:    fcvt.s.h fa5, fa1
 ; CHECK-ZFHMIN-NEXT:    fcvt.s.h fa4, fa0
 ; CHECK-ZFHMIN-NEXT:    fsub.s fa5, fa4, fa5
 ; CHECK-ZFHMIN-NEXT:    fcvt.h.s fa0, fa5
 ; CHECK-ZFHMIN-NEXT:    ret
+;
+; CHECK-ZHINXMIN-LABEL: fsub_h:
+; CHECK-ZHINXMIN:       # %bb.0:
+; CHECK-ZHINXMIN-NEXT:    fcvt.s.h a1, a1
+; CHECK-ZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECK-ZHINXMIN-NEXT:    fsub.s a0, a0, a1
+; CHECK-ZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; CHECK-ZHINXMIN-NEXT:    ret
   %1 = call half @llvm.experimental.constrained.fsub.f16(half %a, half %b, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
   ret half %1
 }
 declare half @llvm.experimental.constrained.fsub.f16(half, half, metadata, metadata)
 
 define half @fmul_h(half %a, half %b) nounwind strictfp {
 ; CHECK-LABEL: fmul_h:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    fmul.h fa0, fa0, fa1
 ; CHECK-NEXT:    ret
 ;
+; CHECK-ZHINX-LABEL: fmul_h:
+; CHECK-ZHINX:       # %bb.0:
+; CHECK-ZHINX-NEXT:    fmul.h a0, a0, a1
+; CHECK-ZHINX-NEXT:    ret
+;
 ; CHECK-ZFHMIN-LABEL: fmul_h:
 ; CHECK-ZFHMIN:       # %bb.0:
 ; CHECK-ZFHMIN-NEXT:    fcvt.s.h fa5, fa1
 ; CHECK-ZFHMIN-NEXT:    fcvt.s.h fa4, fa0
 ; CHECK-ZFHMIN-NEXT:    fmul.s fa5, fa4, fa5
 ; CHECK-ZFHMIN-NEXT:    fcvt.h.s fa0, fa5
 ; CHECK-ZFHMIN-NEXT:    ret
+;
+; CHECK-ZHINXMIN-LABEL: fmul_h:
+; CHECK-ZHINXMIN:       # %bb.0:
+; CHECK-ZHINXMIN-NEXT:    fcvt.s.h a1, a1
+; CHECK-ZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECK-ZHINXMIN-NEXT:    fmul.s a0, a0, a1
+; CHECK-ZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; CHECK-ZHINXMIN-NEXT:    ret
   %1 = call half @llvm.experimental.constrained.fmul.f16(half %a, half %b, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
   ret half %1
 }
 declare half @llvm.experimental.constrained.fmul.f16(half, half, metadata, metadata)
 
 define half @fdiv_h(half %a, half %b) nounwind strictfp {
 ; CHECK-LABEL: fdiv_h:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    fdiv.h fa0, fa0, fa1
 ; CHECK-NEXT:    ret
 ;
+; CHECK-ZHINX-LABEL: fdiv_h:
+; CHECK-ZHINX:       # %bb.0:
+; CHECK-ZHINX-NEXT:    fdiv.h a0, a0, a1
+; CHECK-ZHINX-NEXT:    ret
+;
 ; CHECK-ZFHMIN-LABEL: fdiv_h:
 ; CHECK-ZFHMIN:       # %bb.0:
 ; CHECK-ZFHMIN-NEXT:    fcvt.s.h fa5, fa1
 ; CHECK-ZFHMIN-NEXT:    fcvt.s.h fa4, fa0
 ; CHECK-ZFHMIN-NEXT:    fdiv.s fa5, fa4, fa5
 ; CHECK-ZFHMIN-NEXT:    fcvt.h.s fa0, fa5
 ; CHECK-ZFHMIN-NEXT:    ret
+;
+; CHECK-ZHINXMIN-LABEL: fdiv_h:
+; CHECK-ZHINXMIN:       # %bb.0:
+; CHECK-ZHINXMIN-NEXT:    fcvt.s.h a1, a1
+; CHECK-ZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECK-ZHINXMIN-NEXT:    fdiv.s a0, a0, a1
+; CHECK-ZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; CHECK-ZHINXMIN-NEXT:    ret
   %1 = call half @llvm.experimental.constrained.fdiv.f16(half %a, half %b, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
   ret half %1
 }
 declare half @llvm.experimental.constrained.fdiv.f16(half, half, metadata, metadata)
 
 define half @fsqrt_h(half %a) nounwind strictfp {
 ; CHECK-LABEL: fsqrt_h:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    fsqrt.h fa0, fa0
 ; CHECK-NEXT:    ret
 ;
+; CHECK-ZHINX-LABEL: fsqrt_h:
+; CHECK-ZHINX:       # %bb.0:
+; CHECK-ZHINX-NEXT:    fsqrt.h a0, a0
+; CHECK-ZHINX-NEXT:    ret
+;
 ; CHECK-ZFHMIN-LABEL: fsqrt_h:
 ; CHECK-ZFHMIN:       # %bb.0:
 ; CHECK-ZFHMIN-NEXT:    fcvt.s.h fa5, fa0
 ; CHECK-ZFHMIN-NEXT:    fsqrt.s fa5, fa5
 ; CHECK-ZFHMIN-NEXT:    fcvt.h.s fa0, fa5
 ; CHECK-ZFHMIN-NEXT:    ret
+;
+; CHECK-ZHINXMIN-LABEL: fsqrt_h:
+; CHECK-ZHINXMIN:       # %bb.0:
+; CHECK-ZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECK-ZHINXMIN-NEXT:    fsqrt.s a0, a0
+; CHECK-ZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; CHECK-ZHINXMIN-NEXT:    ret
   %1 = call half @llvm.experimental.constrained.sqrt.f16(half %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
   ret half %1
 }
 declare half @llvm.experimental.constrained.sqrt.f16(half, metadata, metadata)
 
 ; FIXME: fminnum/fmaxnum need libcalls to handle SNaN, but we don't have f16
 ; libcalls and don't support promotion yet.
 ;define half @fmin_h(half %a, half %b) nounwind strictfp {

 ;declare half @llvm.experimental.constrained.maxnum.f16(half, half, metadata) strictfp
 
 define half @fmadd_h(half %a, half %b, half %c) nounwind strictfp {
 ; CHECK-LABEL: fmadd_h:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    fmadd.h fa0, fa0, fa1, fa2
 ; CHECK-NEXT:    ret
 ;
+; CHECK-ZHINX-LABEL: fmadd_h:
+; CHECK-ZHINX:       # %bb.0:
+; CHECK-ZHINX-NEXT:    fmadd.h a0, a0, a1, a2
+; CHECK-ZHINX-NEXT:    ret
+;
 ; CHECK-ZFHMIN-LABEL: fmadd_h:
 ; CHECK-ZFHMIN:       # %bb.0:
 ; CHECK-ZFHMIN-NEXT:    fcvt.s.h fa5, fa2
 ; CHECK-ZFHMIN-NEXT:    fcvt.s.h fa4, fa1
 ; CHECK-ZFHMIN-NEXT:    fcvt.s.h fa3, fa0
 ; CHECK-ZFHMIN-NEXT:    fmadd.s fa5, fa3, fa4, fa5
 ; CHECK-ZFHMIN-NEXT:    fcvt.h.s fa0, fa5
 ; CHECK-ZFHMIN-NEXT:    ret
+;
+; CHECK-ZHINXMIN-LABEL: fmadd_h:
+; CHECK-ZHINXMIN:       # %bb.0:
+; CHECK-ZHINXMIN-NEXT:    fcvt.s.h a2, a2
+; CHECK-ZHINXMIN-NEXT:    fcvt.s.h a1, a1
+; CHECK-ZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECK-ZHINXMIN-NEXT:    fmadd.s a0, a0, a1, a2
+; CHECK-ZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; CHECK-ZHINXMIN-NEXT:    ret
   %1 = call half @llvm.experimental.constrained.fma.f16(half %a, half %b, half %c, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
   ret half %1
 }
 declare half @llvm.experimental.constrained.fma.f16(half, half, half, metadata, metadata) strictfp
 
 define half @fmsub_h(half %a, half %b, half %c) nounwind strictfp {
 ; CHECK-LABEL: fmsub_h:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    fmv.h.x fa5, zero
 ; CHECK-NEXT:    fadd.h fa5, fa2, fa5
 ; CHECK-NEXT:    fmsub.h fa0, fa0, fa1, fa5
 ; CHECK-NEXT:    ret
 ;
+; CHECK-ZHINX-LABEL: fmsub_h:
+; CHECK-ZHINX:       # %bb.0:
+; CHECK-ZHINX-NEXT:    fadd.h a2, a2, zero
+; CHECK-ZHINX-NEXT:    fmsub.h a0, a0, a1, a2
+; CHECK-ZHINX-NEXT:    ret
+;
 ; CHECK-ZFHMIN-LABEL: fmsub_h:
 ; CHECK-ZFHMIN:       # %bb.0:
 ; CHECK-ZFHMIN-NEXT:    fcvt.s.h fa5, fa2
 ; CHECK-ZFHMIN-NEXT:    fmv.w.x fa4, zero
 ; CHECK-ZFHMIN-NEXT:    fadd.s fa5, fa5, fa4
 ; CHECK-ZFHMIN-NEXT:    fcvt.h.s fa5, fa5
 ; CHECK-ZFHMIN-NEXT:    fcvt.s.h fa5, fa5
 ; CHECK-ZFHMIN-NEXT:    fneg.s fa5, fa5
 ; CHECK-ZFHMIN-NEXT:    fcvt.h.s fa5, fa5
 ; CHECK-ZFHMIN-NEXT:    fcvt.s.h fa5, fa5
 ; CHECK-ZFHMIN-NEXT:    fcvt.s.h fa4, fa1
 ; CHECK-ZFHMIN-NEXT:    fcvt.s.h fa3, fa0
 ; CHECK-ZFHMIN-NEXT:    fmadd.s fa5, fa3, fa4, fa5
 ; CHECK-ZFHMIN-NEXT:    fcvt.h.s fa0, fa5
 ; CHECK-ZFHMIN-NEXT:    ret
+;
+; CHECK-ZHINXMIN-LABEL: fmsub_h:
+; CHECK-ZHINXMIN:       # %bb.0:
+; CHECK-ZHINXMIN-NEXT:    fcvt.s.h a2, a2
+; CHECK-ZHINXMIN-NEXT:    fadd.s a2, a2, zero
+; CHECK-ZHINXMIN-NEXT:    fcvt.h.s a2, a2
+; CHECK-ZHINXMIN-NEXT:    fcvt.s.h a2, a2
+; CHECK-ZHINXMIN-NEXT:    fneg.s a2, a2
+; CHECK-ZHINXMIN-NEXT:    fcvt.h.s a2, a2
+; CHECK-ZHINXMIN-NEXT:    fcvt.s.h a2, a2
+; CHECK-ZHINXMIN-NEXT:    fcvt.s.h a1, a1
+; CHECK-ZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECK-ZHINXMIN-NEXT:    fmadd.s a0, a0, a1, a2
+; CHECK-ZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; CHECK-ZHINXMIN-NEXT:    ret
   %c_ = fadd half 0.0, %c ; avoid negation using xor
   %negc = fneg half %c_
   %1 = call half @llvm.experimental.constrained.fma.f16(half %a, half %b, half %negc, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
   ret half %1
 }
 
 define half @fnmadd_h(half %a, half %b, half %c) nounwind strictfp {
 ; CHECK-LABEL: fnmadd_h:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    fmv.h.x fa5, zero
 ; CHECK-NEXT:    fadd.h fa4, fa0, fa5
 ; CHECK-NEXT:    fadd.h fa5, fa2, fa5
 ; CHECK-NEXT:    fnmadd.h fa0, fa4, fa1, fa5
 ; CHECK-NEXT:    ret
 ;
+; CHECK-ZHINX-LABEL: fnmadd_h:
+; CHECK-ZHINX:       # %bb.0:
+; CHECK-ZHINX-NEXT:    fadd.h a0, a0, zero
+; CHECK-ZHINX-NEXT:    fadd.h a2, a2, zero
+; CHECK-ZHINX-NEXT:    fnmadd.h a0, a0, a1, a2
+; CHECK-ZHINX-NEXT:    ret
+;
 ; CHECK-ZFHMIN-LABEL: fnmadd_h:
 ; CHECK-ZFHMIN:       # %bb.0:
 ; CHECK-ZFHMIN-NEXT:    fcvt.s.h fa5, fa0
 ; CHECK-ZFHMIN-NEXT:    fmv.w.x fa4, zero
 ; CHECK-ZFHMIN-NEXT:    fadd.s fa5, fa5, fa4
 ; CHECK-ZFHMIN-NEXT:    fcvt.h.s fa5, fa5
 ; CHECK-ZFHMIN-NEXT:    fcvt.s.h fa3, fa2
 ; CHECK-ZFHMIN-NEXT:    fadd.s fa4, fa3, fa4
 ; CHECK-ZFHMIN-NEXT:    fcvt.h.s fa4, fa4
 ; CHECK-ZFHMIN-NEXT:    fcvt.s.h fa5, fa5
 ; CHECK-ZFHMIN-NEXT:    fneg.s fa5, fa5
 ; CHECK-ZFHMIN-NEXT:    fcvt.h.s fa5, fa5
 ; CHECK-ZFHMIN-NEXT:    fcvt.s.h fa4, fa4
 ; CHECK-ZFHMIN-NEXT:    fneg.s fa4, fa4
 ; CHECK-ZFHMIN-NEXT:    fcvt.h.s fa4, fa4
 ; CHECK-ZFHMIN-NEXT:    fcvt.s.h fa4, fa4
 ; CHECK-ZFHMIN-NEXT:    fcvt.s.h fa5, fa5
 ; CHECK-ZFHMIN-NEXT:    fcvt.s.h fa3, fa1
 ; CHECK-ZFHMIN-NEXT:    fmadd.s fa5, fa5, fa3, fa4
 ; CHECK-ZFHMIN-NEXT:    fcvt.h.s fa0, fa5
 ; CHECK-ZFHMIN-NEXT:    ret
+;
+; CHECK-ZHINXMIN-LABEL: fnmadd_h:
+; CHECK-ZHINXMIN:       # %bb.0:
+; CHECK-ZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECK-ZHINXMIN-NEXT:    fadd.s a0, a0, zero
+; CHECK-ZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; CHECK-ZHINXMIN-NEXT:    fcvt.s.h a2, a2
+; CHECK-ZHINXMIN-NEXT:    fadd.s a2, a2, zero
+; CHECK-ZHINXMIN-NEXT:    fcvt.h.s a2, a2
+; CHECK-ZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECK-ZHINXMIN-NEXT:    fneg.s a0, a0
+; CHECK-ZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; CHECK-ZHINXMIN-NEXT:    fcvt.s.h a2, a2
+; CHECK-ZHINXMIN-NEXT:    fneg.s a2, a2
+; CHECK-ZHINXMIN-NEXT:    fcvt.h.s a2, a2
+; CHECK-ZHINXMIN-NEXT:    fcvt.s.h a2, a2
+; CHECK-ZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECK-ZHINXMIN-NEXT:    fcvt.s.h a1, a1
+; CHECK-ZHINXMIN-NEXT:    fmadd.s a0, a0, a1, a2
+; CHECK-ZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; CHECK-ZHINXMIN-NEXT:    ret
   %a_ = fadd half 0.0, %a
   %c_ = fadd half 0.0, %c
   %nega = fneg half %a_
   %negc = fneg half %c_
   %1 = call half @llvm.experimental.constrained.fma.f16(half %nega, half %b, half %negc, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
   ret half %1
 }
 
 define half @fnmadd_h_2(half %a, half %b, half %c) nounwind strictfp {
 ; CHECK-LABEL: fnmadd_h_2:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    fmv.h.x fa5, zero
 ; CHECK-NEXT:    fadd.h fa4, fa1, fa5
 ; CHECK-NEXT:    fadd.h fa5, fa2, fa5
 ; CHECK-NEXT:    fnmadd.h fa0, fa4, fa0, fa5
 ; CHECK-NEXT:    ret
 ;
+; CHECK-ZHINX-LABEL: fnmadd_h_2:
+; CHECK-ZHINX:       # %bb.0:
+; CHECK-ZHINX-NEXT:    fadd.h a1, a1, zero
+; CHECK-ZHINX-NEXT:    fadd.h a2, a2, zero
+; CHECK-ZHINX-NEXT:    fnmadd.h a0, a1, a0, a2
+; CHECK-ZHINX-NEXT:    ret
+;
 ; CHECK-ZFHMIN-LABEL: fnmadd_h_2:
 ; CHECK-ZFHMIN:       # %bb.0:
 ; CHECK-ZFHMIN-NEXT:    fcvt.s.h fa5, fa1
 ; CHECK-ZFHMIN-NEXT:    fmv.w.x fa4, zero
 ; CHECK-ZFHMIN-NEXT:    fadd.s fa5, fa5, fa4
 ; CHECK-ZFHMIN-NEXT:    fcvt.h.s fa5, fa5
 ; CHECK-ZFHMIN-NEXT:    fcvt.s.h fa3, fa2
 ; CHECK-ZFHMIN-NEXT:    fadd.s fa4, fa3, fa4
 ; CHECK-ZFHMIN-NEXT:    fcvt.h.s fa4, fa4
 ; CHECK-ZFHMIN-NEXT:    fcvt.s.h fa5, fa5
 ; CHECK-ZFHMIN-NEXT:    fneg.s fa5, fa5
 ; CHECK-ZFHMIN-NEXT:    fcvt.h.s fa5, fa5
 ; CHECK-ZFHMIN-NEXT:    fcvt.s.h fa4, fa4
 ; CHECK-ZFHMIN-NEXT:    fneg.s fa4, fa4
 ; CHECK-ZFHMIN-NEXT:    fcvt.h.s fa4, fa4
 ; CHECK-ZFHMIN-NEXT:    fcvt.s.h fa4, fa4
 ; CHECK-ZFHMIN-NEXT:    fcvt.s.h fa5, fa5
 ; CHECK-ZFHMIN-NEXT:    fcvt.s.h fa3, fa0
 ; CHECK-ZFHMIN-NEXT:    fmadd.s fa5, fa3, fa5, fa4
 ; CHECK-ZFHMIN-NEXT:    fcvt.h.s fa0, fa5
 ; CHECK-ZFHMIN-NEXT:    ret
+;
+; CHECK-ZHINXMIN-LABEL: fnmadd_h_2:
+; CHECK-ZHINXMIN:       # %bb.0:
+; CHECK-ZHINXMIN-NEXT:    fcvt.s.h a1, a1
+; CHECK-ZHINXMIN-NEXT:    fadd.s a1, a1, zero
+; CHECK-ZHINXMIN-NEXT:    fcvt.h.s a1, a1
+; CHECK-ZHINXMIN-NEXT:    fcvt.s.h a2, a2
+; CHECK-ZHINXMIN-NEXT:    fadd.s a2, a2, zero
+; CHECK-ZHINXMIN-NEXT:    fcvt.h.s a2, a2
+; CHECK-ZHINXMIN-NEXT:    fcvt.s.h a1, a1
+; CHECK-ZHINXMIN-NEXT:    fneg.s a1, a1
+; CHECK-ZHINXMIN-NEXT:    fcvt.h.s a1, a1
+; CHECK-ZHINXMIN-NEXT:    fcvt.s.h a2, a2
+; CHECK-ZHINXMIN-NEXT:    fneg.s a2, a2
+; CHECK-ZHINXMIN-NEXT:    fcvt.h.s a2, a2
+; CHECK-ZHINXMIN-NEXT:    fcvt.s.h a2, a2
+; CHECK-ZHINXMIN-NEXT:    fcvt.s.h a1, a1
+; CHECK-ZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECK-ZHINXMIN-NEXT:    fmadd.s a0, a0, a1, a2
+; CHECK-ZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; CHECK-ZHINXMIN-NEXT:    ret
   %b_ = fadd half 0.0, %b
   %c_ = fadd half 0.0, %c
   %negb = fneg half %b_
   %negc = fneg half %c_
   %1 = call half @llvm.experimental.constrained.fma.f16(half %a, half %negb, half %negc, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
   ret half %1
 }
 
 define half @fnmsub_h(half %a, half %b, half %c) nounwind strictfp {
 ; CHECK-LABEL: fnmsub_h:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    fmv.h.x fa5, zero
 ; CHECK-NEXT:    fadd.h fa5, fa0, fa5
 ; CHECK-NEXT:    fnmsub.h fa0, fa5, fa1, fa2
 ; CHECK-NEXT:    ret
 ;
+; CHECK-ZHINX-LABEL: fnmsub_h:
+; CHECK-ZHINX:       # %bb.0:
+; CHECK-ZHINX-NEXT:    fadd.h a0, a0, zero
+; CHECK-ZHINX-NEXT:    fnmsub.h a0, a0, a1, a2
+; CHECK-ZHINX-NEXT:    ret
+;
 ; CHECK-ZFHMIN-LABEL: fnmsub_h:
 ; CHECK-ZFHMIN:       # %bb.0:
 ; CHECK-ZFHMIN-NEXT:    fcvt.s.h fa5, fa0
 ; CHECK-ZFHMIN-NEXT:    fmv.w.x fa4, zero
 ; CHECK-ZFHMIN-NEXT:    fadd.s fa5, fa5, fa4
 ; CHECK-ZFHMIN-NEXT:    fcvt.h.s fa5, fa5
 ; CHECK-ZFHMIN-NEXT:    fcvt.s.h fa5, fa5
 ; CHECK-ZFHMIN-NEXT:    fneg.s fa5, fa5
 ; CHECK-ZFHMIN-NEXT:    fcvt.h.s fa5, fa5
 ; CHECK-ZFHMIN-NEXT:    fcvt.s.h fa5, fa5
 ; CHECK-ZFHMIN-NEXT:    fcvt.s.h fa4, fa2
 ; CHECK-ZFHMIN-NEXT:    fcvt.s.h fa3, fa1
 ; CHECK-ZFHMIN-NEXT:    fmadd.s fa5, fa5, fa3, fa4
 ; CHECK-ZFHMIN-NEXT:    fcvt.h.s fa0, fa5
 ; CHECK-ZFHMIN-NEXT:    ret
+;
+; CHECK-ZHINXMIN-LABEL: fnmsub_h:
+; CHECK-ZHINXMIN:       # %bb.0:
+; CHECK-ZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECK-ZHINXMIN-NEXT:    fadd.s a0, a0, zero
+; CHECK-ZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; CHECK-ZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECK-ZHINXMIN-NEXT:    fneg.s a0, a0
+; CHECK-ZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; CHECK-ZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECK-ZHINXMIN-NEXT:    fcvt.s.h a2, a2
+; CHECK-ZHINXMIN-NEXT:    fcvt.s.h a1, a1
+; CHECK-ZHINXMIN-NEXT:    fmadd.s a0, a0, a1, a2
+; CHECK-ZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; CHECK-ZHINXMIN-NEXT:    ret
   %a_ = fadd half 0.0, %a
   %nega = fneg half %a_
   %1 = call half @llvm.experimental.constrained.fma.f16(half %nega, half %b, half %c, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
   ret half %1
 }
 
 define half @fnmsub_h_2(half %a, half %b, half %c) nounwind strictfp {
 ; CHECK-LABEL: fnmsub_h_2:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    fmv.h.x fa5, zero
 ; CHECK-NEXT:    fadd.h fa5, fa1, fa5
 ; CHECK-NEXT:    fnmsub.h fa0, fa5, fa0, fa2
 ; CHECK-NEXT:    ret
 ;
+; CHECK-ZHINX-LABEL: fnmsub_h_2:
+; CHECK-ZHINX:       # %bb.0:
+; CHECK-ZHINX-NEXT:    fadd.h a1, a1, zero
+; CHECK-ZHINX-NEXT:    fnmsub.h a0, a1, a0, a2
+; CHECK-ZHINX-NEXT:    ret
+;
 ; CHECK-ZFHMIN-LABEL: fnmsub_h_2:
 ; CHECK-ZFHMIN:       # %bb.0:
 ; CHECK-ZFHMIN-NEXT:    fcvt.s.h fa5, fa1
 ; CHECK-ZFHMIN-NEXT:    fmv.w.x fa4, zero
 ; CHECK-ZFHMIN-NEXT:    fadd.s fa5, fa5, fa4
 ; CHECK-ZFHMIN-NEXT:    fcvt.h.s fa5, fa5
 ; CHECK-ZFHMIN-NEXT:    fcvt.s.h fa5, fa5
 ; CHECK-ZFHMIN-NEXT:    fneg.s fa5, fa5
 ; CHECK-ZFHMIN-NEXT:    fcvt.h.s fa5, fa5
 ; CHECK-ZFHMIN-NEXT:    fcvt.s.h fa5, fa5
 ; CHECK-ZFHMIN-NEXT:    fcvt.s.h fa4, fa2
 ; CHECK-ZFHMIN-NEXT:    fcvt.s.h fa3, fa0
 ; CHECK-ZFHMIN-NEXT:    fmadd.s fa5, fa3, fa5, fa4
 ; CHECK-ZFHMIN-NEXT:    fcvt.h.s fa0, fa5
 ; CHECK-ZFHMIN-NEXT:    ret
+;
+; CHECK-ZHINXMIN-LABEL: fnmsub_h_2:
+; CHECK-ZHINXMIN:       # %bb.0:
+; CHECK-ZHINXMIN-NEXT:    fcvt.s.h a1, a1
+; CHECK-ZHINXMIN-NEXT:    fadd.s a1, a1, zero
+; CHECK-ZHINXMIN-NEXT:    fcvt.h.s a1, a1
+; CHECK-ZHINXMIN-NEXT:    fcvt.s.h a1, a1
+; CHECK-ZHINXMIN-NEXT:    fneg.s a1, a1
+; CHECK-ZHINXMIN-NEXT:    fcvt.h.s a1, a1
+; CHECK-ZHINXMIN-NEXT:    fcvt.s.h a1, a1
+; CHECK-ZHINXMIN-NEXT:    fcvt.s.h a2, a2
+; CHECK-ZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECK-ZHINXMIN-NEXT:    fmadd.s a0, a0, a1, a2
+; CHECK-ZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; CHECK-ZHINXMIN-NEXT:    ret
   %b_ = fadd half 0.0, %b
   %negb = fneg half %b_
   %1 = call half @llvm.experimental.constrained.fma.f16(half %a, half %negb, half %c, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
   ret half %1
 }

llvm/test/CodeGen/RISCV/half-arith.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -mattr=+zfh -verify-machineinstrs \
 ; RUN:   -target-abi ilp32f < %s | FileCheck -check-prefix=CHECKIZFH %s
 ; RUN: llc -mtriple=riscv64 -mattr=+zfh -verify-machineinstrs \
 ; RUN:   -target-abi lp64f < %s | FileCheck -check-prefix=CHECKIZFH %s
+; RUN: llc -mtriple=riscv32 -mattr=+zhinx -verify-machineinstrs \
+; RUN:   -target-abi ilp32 < %s | FileCheck -check-prefix=CHECK-ZHINX %s
+; RUN: llc -mtriple=riscv64 -mattr=+zhinx -verify-machineinstrs \
+; RUN:   -target-abi lp64 < %s | FileCheck -check-prefix=CHECK-ZHINX %s
 ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
 ; RUN:   | FileCheck -check-prefix=RV32I %s
 ; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
 ; RUN:   | FileCheck -check-prefix=RV64I %s
 ; RUN: llc -mtriple=riscv32 -mattr=+zfhmin -verify-machineinstrs \
 ; RUN:   -target-abi ilp32f < %s | FileCheck -check-prefixes=CHECKIZFHMIN,CHECK-RV32-FSGNJ %s
 ; RUN: llc -mtriple=riscv64 -mattr=+zfhmin -verify-machineinstrs \
 ; RUN:   -target-abi lp64f < %s | FileCheck --check-prefixes=CHECKIZFHMIN,CHECK-RV64-FSGNJ %s
+; RUN: llc -mtriple=riscv32 -mattr=+zhinxmin -verify-machineinstrs \
+; RUN:   -target-abi ilp32 < %s | FileCheck --check-prefixes=CHECKZHINXMIN %s
+; RUN: llc -mtriple=riscv64 -mattr=+zhinxmin -verify-machineinstrs \
+; RUN:   -target-abi lp64 < %s | FileCheck --check-prefixes=CHECKZHINXMIN %s
 
 ; These tests are each targeted at a particular RISC-V FPU instruction.
 ; Compares and conversions can be found in half-fcmp.ll and half-convert.ll
 ; respectively. Some other half-*.ll files in this folder exercise LLVM IR
 ; instructions that don't directly match a RISC-V instruction.
 
 define half @fadd_s(half %a, half %b) nounwind {
 ; CHECKIZFH-LABEL: fadd_s:
 ; CHECKIZFH:       # %bb.0:
 ; CHECKIZFH-NEXT:    fadd.h fa0, fa0, fa1
 ; CHECKIZFH-NEXT:    ret
 ;
+; CHECK-ZHINX-LABEL: fadd_s:
+; CHECK-ZHINX:       # %bb.0:
+; CHECK-ZHINX-NEXT:    fadd.h a0, a0, a1
+; CHECK-ZHINX-NEXT:    ret
+;
 ; RV32I-LABEL: fadd_s:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s2, 0(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    mv s0, a1

 ;
 ; CHECKIZFHMIN-LABEL: fadd_s:
 ; CHECKIZFHMIN:       # %bb.0:
 ; CHECKIZFHMIN-NEXT:    fcvt.s.h fa5, fa1
 ; CHECKIZFHMIN-NEXT:    fcvt.s.h fa4, fa0
 ; CHECKIZFHMIN-NEXT:    fadd.s fa5, fa4, fa5
 ; CHECKIZFHMIN-NEXT:    fcvt.h.s fa0, fa5
 ; CHECKIZFHMIN-NEXT:    ret
+;
+; CHECKZHINXMIN-LABEL: fadd_s:
+; CHECKZHINXMIN:       # %bb.0:
+; CHECKZHINXMIN-NEXT:    fcvt.s.h a1, a1
+; CHECKZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECKZHINXMIN-NEXT:    fadd.s a0, a0, a1
+; CHECKZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; CHECKZHINXMIN-NEXT:    ret
+; CHECK-ZHINXMIN-LABEL: fadd_s:
+; CHECK-ZHINXMIN:       # %bb.0:
+; CHECK-ZHINXMIN-NEXT:    fcvt.s.h a1, a1
+; CHECK-ZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECK-ZHINXMIN-NEXT:    fadd.s a0, a0, a1
+; CHECK-ZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; CHECK-ZHINXMIN-NEXT:    ret
   %1 = fadd half %a, %b
   ret half %1
 }
 
 define half @fsub_s(half %a, half %b) nounwind {
 ; CHECKIZFH-LABEL: fsub_s:
 ; CHECKIZFH:       # %bb.0:
 ; CHECKIZFH-NEXT:    fsub.h fa0, fa0, fa1
 ; CHECKIZFH-NEXT:    ret
 ;
+; CHECK-ZHINX-LABEL: fsub_s:
+; CHECK-ZHINX:       # %bb.0:
+; CHECK-ZHINX-NEXT:    fsub.h a0, a0, a1
+; CHECK-ZHINX-NEXT:    ret
+;
 ; RV32I-LABEL: fsub_s:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s2, 0(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    mv s0, a1

 ;
 ; CHECKIZFHMIN-LABEL: fsub_s:
 ; CHECKIZFHMIN:       # %bb.0:
 ; CHECKIZFHMIN-NEXT:    fcvt.s.h fa5, fa1
 ; CHECKIZFHMIN-NEXT:    fcvt.s.h fa4, fa0
 ; CHECKIZFHMIN-NEXT:    fsub.s fa5, fa4, fa5
 ; CHECKIZFHMIN-NEXT:    fcvt.h.s fa0, fa5
 ; CHECKIZFHMIN-NEXT:    ret
+;
+; CHECKZHINXMIN-LABEL: fsub_s:
+; CHECKZHINXMIN:       # %bb.0:
+; CHECKZHINXMIN-NEXT:    fcvt.s.h a1, a1
+; CHECKZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECKZHINXMIN-NEXT:    fsub.s a0, a0, a1
+; CHECKZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; CHECKZHINXMIN-NEXT:    ret
+; CHECK-ZHINXMIN-LABEL: fsub_s:
+; CHECK-ZHINXMIN:       # %bb.0:
+; CHECK-ZHINXMIN-NEXT:    fcvt.s.h a1, a1
+; CHECK-ZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECK-ZHINXMIN-NEXT:    fsub.s a0, a0, a1
+; CHECK-ZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; CHECK-ZHINXMIN-NEXT:    ret
   %1 = fsub half %a, %b
   ret half %1
 }
 
 define half @fmul_s(half %a, half %b) nounwind {
 ; CHECKIZFH-LABEL: fmul_s:
 ; CHECKIZFH:       # %bb.0:
 ; CHECKIZFH-NEXT:    fmul.h fa0, fa0, fa1
 ; CHECKIZFH-NEXT:    ret
 ;
+; CHECK-ZHINX-LABEL: fmul_s:
+; CHECK-ZHINX:       # %bb.0:
+; CHECK-ZHINX-NEXT:    fmul.h a0, a0, a1
+; CHECK-ZHINX-NEXT:    ret
+;
 ; RV32I-LABEL: fmul_s:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s2, 0(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    mv s0, a1

 ;
 ; CHECKIZFHMIN-LABEL: fmul_s:
 ; CHECKIZFHMIN:       # %bb.0:
 ; CHECKIZFHMIN-NEXT:    fcvt.s.h fa5, fa1
 ; CHECKIZFHMIN-NEXT:    fcvt.s.h fa4, fa0
 ; CHECKIZFHMIN-NEXT:    fmul.s fa5, fa4, fa5
 ; CHECKIZFHMIN-NEXT:    fcvt.h.s fa0, fa5
 ; CHECKIZFHMIN-NEXT:    ret
+;
+; CHECKZHINXMIN-LABEL: fmul_s:
+; CHECKZHINXMIN:       # %bb.0:
+; CHECKZHINXMIN-NEXT:    fcvt.s.h a1, a1
+; CHECKZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECKZHINXMIN-NEXT:    fmul.s a0, a0, a1
+; CHECKZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; CHECKZHINXMIN-NEXT:    ret
+; CHECK-ZHINXMIN-LABEL: fmul_s:
+; CHECK-ZHINXMIN:       # %bb.0:
+; CHECK-ZHINXMIN-NEXT:    fcvt.s.h a1, a1
+; CHECK-ZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECK-ZHINXMIN-NEXT:    fmul.s a0, a0, a1
+; CHECK-ZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; CHECK-ZHINXMIN-NEXT:    ret
   %1 = fmul half %a, %b
   ret half %1
 }
 
 define half @fdiv_s(half %a, half %b) nounwind {
 ; CHECKIZFH-LABEL: fdiv_s:
 ; CHECKIZFH:       # %bb.0:
 ; CHECKIZFH-NEXT:    fdiv.h fa0, fa0, fa1
 ; CHECKIZFH-NEXT:    ret
 ;
+; CHECK-ZHINX-LABEL: fdiv_s:
+; CHECK-ZHINX:       # %bb.0:
+; CHECK-ZHINX-NEXT:    fdiv.h a0, a0, a1
+; CHECK-ZHINX-NEXT:    ret
+;
 ; RV32I-LABEL: fdiv_s:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s2, 0(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    mv s0, a1

 ;
 ; CHECKIZFHMIN-LABEL: fdiv_s:
 ; CHECKIZFHMIN:       # %bb.0:
 ; CHECKIZFHMIN-NEXT:    fcvt.s.h fa5, fa1
 ; CHECKIZFHMIN-NEXT:    fcvt.s.h fa4, fa0
 ; CHECKIZFHMIN-NEXT:    fdiv.s fa5, fa4, fa5
 ; CHECKIZFHMIN-NEXT:    fcvt.h.s fa0, fa5
 ; CHECKIZFHMIN-NEXT:    ret
+;
+; CHECKZHINXMIN-LABEL: fdiv_s:
+; CHECKZHINXMIN:       # %bb.0:
+; CHECKZHINXMIN-NEXT:    fcvt.s.h a1, a1
+; CHECKZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECKZHINXMIN-NEXT:    fdiv.s a0, a0, a1
+; CHECKZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; CHECKZHINXMIN-NEXT:    ret
+; CHECK-ZHINXMIN-LABEL: fdiv_s:
+; CHECK-ZHINXMIN:       # %bb.0:
+; CHECK-ZHINXMIN-NEXT:    fcvt.s.h a1, a1
+; CHECK-ZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECK-ZHINXMIN-NEXT:    fdiv.s a0, a0, a1
+; CHECK-ZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; CHECK-ZHINXMIN-NEXT:    ret
   %1 = fdiv half %a, %b
   ret half %1
 }
 
 declare half @llvm.sqrt.f16(half)
 
 define half @fsqrt_s(half %a) nounwind {
 ; CHECKIZFH-LABEL: fsqrt_s:
 ; CHECKIZFH:       # %bb.0:
 ; CHECKIZFH-NEXT:    fsqrt.h fa0, fa0
 ; CHECKIZFH-NEXT:    ret
 ;
+; CHECK-ZHINX-LABEL: fsqrt_s:
+; CHECK-ZHINX:       # %bb.0:
+; CHECK-ZHINX-NEXT:    fsqrt.h a0, a0
+; CHECK-ZHINX-NEXT:    ret
+;
 ; RV32I-LABEL: fsqrt_s:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    slli a0, a0, 16
 ; RV32I-NEXT:    srli a0, a0, 16
 ; RV32I-NEXT:    call __extendhfsf2@plt
 ; RV32I-NEXT:    call sqrtf@plt

 ; RV64I-NEXT:    ret
 ;
 ; CHECKIZFHMIN-LABEL: fsqrt_s:
 ; CHECKIZFHMIN:       # %bb.0:
 ; CHECKIZFHMIN-NEXT:    fcvt.s.h fa5, fa0
 ; CHECKIZFHMIN-NEXT:    fsqrt.s fa5, fa5
 ; CHECKIZFHMIN-NEXT:    fcvt.h.s fa0, fa5
 ; CHECKIZFHMIN-NEXT:    ret
+;
+; CHECKZHINXMIN-LABEL: fsqrt_s:
+; CHECKZHINXMIN:       # %bb.0:
+; CHECKZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECKZHINXMIN-NEXT:    fsqrt.s a0, a0
+; CHECKZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; CHECKZHINXMIN-NEXT:    ret
+; CHECK-ZHINXMIN-LABEL: fsqrt_s:
+; CHECK-ZHINXMIN:       # %bb.0:
+; CHECK-ZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECK-ZHINXMIN-NEXT:    fsqrt.s a0, a0
+; CHECK-ZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; CHECK-ZHINXMIN-NEXT:    ret
   %1 = call half @llvm.sqrt.f16(half %a)
   ret half %1
 }
 
 declare half @llvm.copysign.f16(half, half)
 
 define half @fsgnj_s(half %a, half %b) nounwind {
 ; CHECKIZFH-LABEL: fsgnj_s:
 ; CHECKIZFH:       # %bb.0:
 ; CHECKIZFH-NEXT:    fsgnj.h fa0, fa0, fa1
 ; CHECKIZFH-NEXT:    ret
 ;
+; CHECK-ZHINX-LABEL: fsgnj_s:
+; CHECK-ZHINX:       # %bb.0:
+; CHECK-ZHINX-NEXT:    fsgnj.h a0, a0, a1
+; CHECK-ZHINX-NEXT:    ret
+;
 ; RV32I-LABEL: fsgnj_s:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    lui a2, 1048568
 ; RV32I-NEXT:    and a1, a1, a2
 ; RV32I-NEXT:    slli a0, a0, 17
 ; RV32I-NEXT:    srli a0, a0, 17
 ; RV32I-NEXT:    or a0, a0, a1
 ; RV32I-NEXT:    ret

 ; CHECK-RV64-FSGNJ-NEXT:    lbu a1, 1(sp)
 ; CHECK-RV64-FSGNJ-NEXT:    andi a0, a0, 128
 ; CHECK-RV64-FSGNJ-NEXT:    andi a1, a1, 127
 ; CHECK-RV64-FSGNJ-NEXT:    or a0, a1, a0
 ; CHECK-RV64-FSGNJ-NEXT:    sb a0, 1(sp)
 ; CHECK-RV64-FSGNJ-NEXT:    flh fa0, 0(sp)
 ; CHECK-RV64-FSGNJ-NEXT:    addi sp, sp, 16
 ; CHECK-RV64-FSGNJ-NEXT:    ret
+; CHECK-ZHINXMIN-LABEL: fsgnj_s:
+; CHECK-ZHINXMIN:       # %bb.0:
+; CHECK-ZHINXMIN-NEXT:    addi sp, sp, -16
+; CHECK-ZHINXMIN-NEXT:    addi a2, sp, 12
+; CHECK-ZHINXMIN-NEXT:    sh a1, 0(a2)
+; CHECK-ZHINXMIN-NEXT:    addi a1, sp, 8
+; CHECK-ZHINXMIN-NEXT:    sh a0, 0(a1)
+; CHECK-ZHINXMIN-NEXT:    lbu a0, 13(sp)
+; CHECK-ZHINXMIN-NEXT:    lbu a2, 9(sp)
+; CHECK-ZHINXMIN-NEXT:    andi a0, a0, 128
+; CHECK-ZHINXMIN-NEXT:    andi a2, a2, 127
+; CHECK-ZHINXMIN-NEXT:    or a0, a2, a0
+; CHECK-ZHINXMIN-NEXT:    sb a0, 9(sp)
+; CHECK-ZHINXMIN-NEXT:    lh a0, 0(a1)
+; CHECK-ZHINXMIN-NEXT:    addi sp, sp, 16
+; CHECK-ZHINXMIN-NEXT:    ret
 ; CHECKFSGNJ-LABEL: fsgnj_s:
 ; CHECKFSGNJ:       # %bb.0:
 ; CHECKFSGNJ-NEXT:    addi sp, sp, -16
 ; CHECKFSGNJ-NEXT:    fsh fa1, 12(sp)
 ; CHECKFSGNJ-NEXT:    fsh fa0, 8(sp)
 ; CHECKFSGNJ-NEXT:    lbu a0, 13(sp)
 ; CHECKFSGNJ-NEXT:    lbu a1, 9(sp)
 ; CHECKFSGNJ-NEXT:    andi a0, a0, 128

 define i32 @fneg_s(half %a, half %b) nounwind {
 ; CHECKIZFH-LABEL: fneg_s:
 ; CHECKIZFH:       # %bb.0:
 ; CHECKIZFH-NEXT:    fadd.h fa5, fa0, fa0
 ; CHECKIZFH-NEXT:    fneg.h fa4, fa5
 ; CHECKIZFH-NEXT:    feq.h a0, fa5, fa4
 ; CHECKIZFH-NEXT:    ret
 ;
+; CHECK-ZHINX-LABEL: fneg_s:
+; CHECK-ZHINX:       # %bb.0:
+; CHECK-ZHINX-NEXT:    fadd.h a0, a0, a0
+; CHECK-ZHINX-NEXT:    fneg.h a1, a0
+; CHECK-ZHINX-NEXT:    feq.h a0, a0, a1
+; CHECK-ZHINX-NEXT:    ret
+;
 ; RV32I-LABEL: fneg_s:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    lui a1, 16
 ; RV32I-NEXT:    addi s1, a1, -1

 ; CHECKIZFHMIN-NEXT:    fadd.s fa5, fa5, fa5
 ; CHECKIZFHMIN-NEXT:    fcvt.h.s fa5, fa5
 ; CHECKIZFHMIN-NEXT:    fcvt.s.h fa5, fa5
 ; CHECKIZFHMIN-NEXT:    fneg.s fa4, fa5
 ; CHECKIZFHMIN-NEXT:    fcvt.h.s fa4, fa4
 ; CHECKIZFHMIN-NEXT:    fcvt.s.h fa4, fa4
 ; CHECKIZFHMIN-NEXT:    feq.s a0, fa5, fa4
 ; CHECKIZFHMIN-NEXT:    ret
+;
+; CHECKZHINXMIN-LABEL: fneg_s:
+; CHECKZHINXMIN:       # %bb.0:
+; CHECKZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECKZHINXMIN-NEXT:    fadd.s a0, a0, a0
+; CHECKZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; CHECKZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECKZHINXMIN-NEXT:    fneg.s a1, a0
+; CHECKZHINXMIN-NEXT:    fcvt.h.s a1, a1
+; CHECKZHINXMIN-NEXT:    fcvt.s.h a1, a1
+; CHECKZHINXMIN-NEXT:    feq.s a0, a0, a1
+; CHECKZHINXMIN-NEXT:    ret
+; CHECK-ZHINXMIN-LABEL: fneg_s:
+; CHECK-ZHINXMIN:       # %bb.0:
+; CHECK-ZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECK-ZHINXMIN-NEXT:    fadd.s a0, a0, a0
+; CHECK-ZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; CHECK-ZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECK-ZHINXMIN-NEXT:    fneg.s a1, a0
+; CHECK-ZHINXMIN-NEXT:    fcvt.h.s a1, a1
+; CHECK-ZHINXMIN-NEXT:    fcvt.s.h a1, a1
+; CHECK-ZHINXMIN-NEXT:    feq.s a0, a0, a1
+; CHECK-ZHINXMIN-NEXT:    ret
   %1 = fadd half %a, %a
   %2 = fneg half %1
   %3 = fcmp oeq half %1, %2
   %4 = zext i1 %3 to i32
   ret i32 %4
 }
 
 ; This function performs extra work to ensure that
 ; DAGCombiner::visitBITCAST doesn't replace the fneg with an xor.
 define half @fsgnjn_s(half %a, half %b) nounwind {
 ; CHECKIZFH-LABEL: fsgnjn_s:
 ; CHECKIZFH:       # %bb.0:
 ; CHECKIZFH-NEXT:    fadd.h fa5, fa0, fa1
 ; CHECKIZFH-NEXT:    fsgnjn.h fa0, fa0, fa5
 ; CHECKIZFH-NEXT:    ret
 ;
+; CHECK-ZHINX-LABEL: fsgnjn_s:
+; CHECK-ZHINX:       # %bb.0:
+; CHECK-ZHINX-NEXT:    fadd.h a1, a0, a1
+; CHECK-ZHINX-NEXT:    fsgnjn.h a0, a0, a1
+; CHECK-ZHINX-NEXT:    ret
+;
 ; RV32I-LABEL: fsgnjn_s:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -32
 ; RV32I-NEXT:    sw ra, 28(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s0, 24(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s1, 20(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s2, 16(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s3, 12(sp) # 4-byte Folded Spill

 ; CHECK-RV64-FSGNJ-NEXT:    lbu a1, 9(sp)
 ; CHECK-RV64-FSGNJ-NEXT:    andi a0, a0, 127
 ; CHECK-RV64-FSGNJ-NEXT:    andi a1, a1, 128
 ; CHECK-RV64-FSGNJ-NEXT:    or a0, a0, a1
 ; CHECK-RV64-FSGNJ-NEXT:    sb a0, 1(sp)
 ; CHECK-RV64-FSGNJ-NEXT:    flh fa0, 0(sp)
 ; CHECK-RV64-FSGNJ-NEXT:    addi sp, sp, 16
 ; CHECK-RV64-FSGNJ-NEXT:    ret
+; CHECK-ZHINXMIN-LABEL: fsgnjn_s:
+; CHECK-ZHINXMIN:       # %bb.0:
+; CHECK-ZHINXMIN-NEXT:    addi sp, sp, -16
+; CHECK-ZHINXMIN-NEXT:    fcvt.s.h a1, a1
+; CHECK-ZHINXMIN-NEXT:    fcvt.s.h a2, a0
+; CHECK-ZHINXMIN-NEXT:    fadd.s a1, a2, a1
+; CHECK-ZHINXMIN-NEXT:    fcvt.h.s a1, a1
+; CHECK-ZHINXMIN-NEXT:    fcvt.s.h a1, a1
+; CHECK-ZHINXMIN-NEXT:    fneg.s a1, a1
+; CHECK-ZHINXMIN-NEXT:    fcvt.h.s a1, a1
+; CHECK-ZHINXMIN-NEXT:    addi a2, sp, 8
+; CHECK-ZHINXMIN-NEXT:    sh a0, 0(a2)
+; CHECK-ZHINXMIN-NEXT:    addi a0, sp, 12
+; CHECK-ZHINXMIN-NEXT:    sh a1, 0(a0)
+; CHECK-ZHINXMIN-NEXT:    lbu a0, 9(sp)
+; CHECK-ZHINXMIN-NEXT:    lbu a1, 13(sp)
+; CHECK-ZHINXMIN-NEXT:    andi a0, a0, 127
+; CHECK-ZHINXMIN-NEXT:    andi a1, a1, 128
+; CHECK-ZHINXMIN-NEXT:    or a0, a0, a1
+; CHECK-ZHINXMIN-NEXT:    sb a0, 9(sp)
+; CHECK-ZHINXMIN-NEXT:    lh a0, 0(a2)
+; CHECK-ZHINXMIN-NEXT:    addi sp, sp, 16
+; CHECK-ZHINXMIN-NEXT:    ret
 ; CHECKFSGNJ-LABEL: fsgnjn_s:
 ; CHECKFSGNJ:       # %bb.0:
 ; CHECKFSGNJ-NEXT:    addi sp, sp, -16
 ; CHECKFSGNJ-NEXT:    fcvt.s.h ft0, fa1
 ; CHECKFSGNJ-NEXT:    fcvt.s.h ft1, fa0
 ; CHECKFSGNJ-NEXT:    fadd.s ft0, ft1, ft0
 ; CHECKFSGNJ-NEXT:    fcvt.h.s ft0, ft0
 ; CHECKFSGNJ-NEXT:    fcvt.s.h ft0, ft0

 define half @fabs_s(half %a, half %b) nounwind {
 ; CHECKIZFH-LABEL: fabs_s:
 ; CHECKIZFH:       # %bb.0:
 ; CHECKIZFH-NEXT:    fadd.h fa5, fa0, fa1
 ; CHECKIZFH-NEXT:    fabs.h fa4, fa5
 ; CHECKIZFH-NEXT:    fadd.h fa0, fa4, fa5
 ; CHECKIZFH-NEXT:    ret
 ;
+; CHECK-ZHINX-LABEL: fabs_s:
+; CHECK-ZHINX:       # %bb.0:
+; CHECK-ZHINX-NEXT:    fadd.h a0, a0, a1
+; CHECK-ZHINX-NEXT:    fabs.h a1, a0
+; CHECK-ZHINX-NEXT:    fadd.h a0, a1, a0
+; CHECK-ZHINX-NEXT:    ret
+;
 ; RV32I-LABEL: fabs_s:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s2, 0(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    mv s0, a1

 ; CHECKIZFHMIN-NEXT:    fcvt.h.s fa5, fa5
 ; CHECKIZFHMIN-NEXT:    fcvt.s.h fa5, fa5
 ; CHECKIZFHMIN-NEXT:    fabs.s fa4, fa5
 ; CHECKIZFHMIN-NEXT:    fcvt.h.s fa4, fa4
 ; CHECKIZFHMIN-NEXT:    fcvt.s.h fa4, fa4
 ; CHECKIZFHMIN-NEXT:    fadd.s fa5, fa4, fa5
 ; CHECKIZFHMIN-NEXT:    fcvt.h.s fa0, fa5
 ; CHECKIZFHMIN-NEXT:    ret
+;
+; CHECKZHINXMIN-LABEL: fabs_s:
+; CHECKZHINXMIN:       # %bb.0:
+; CHECKZHINXMIN-NEXT:    fcvt.s.h a1, a1
+; CHECKZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECKZHINXMIN-NEXT:    fadd.s a0, a0, a1
+; CHECKZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; CHECKZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECKZHINXMIN-NEXT:    fabs.s a1, a0
+; CHECKZHINXMIN-NEXT:    fcvt.h.s a1, a1
+; CHECKZHINXMIN-NEXT:    fcvt.s.h a1, a1
+; CHECKZHINXMIN-NEXT:    fadd.s a0, a1, a0
+; CHECKZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; CHECKZHINXMIN-NEXT:    ret
+; CHECK-ZHINXMIN-LABEL: fabs_s:
+; CHECK-ZHINXMIN:       # %bb.0:
+; CHECK-ZHINXMIN-NEXT:    fcvt.s.h a1, a1
+; CHECK-ZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECK-ZHINXMIN-NEXT:    fadd.s a0, a0, a1
+; CHECK-ZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; CHECK-ZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECK-ZHINXMIN-NEXT:    fabs.s a1, a0
+; CHECK-ZHINXMIN-NEXT:    fcvt.h.s a1, a1
+; CHECK-ZHINXMIN-NEXT:    fcvt.s.h a1, a1
+; CHECK-ZHINXMIN-NEXT:    fadd.s a0, a1, a0
+; CHECK-ZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; CHECK-ZHINXMIN-NEXT:    ret
   %1 = fadd half %a, %b
   %2 = call half @llvm.fabs.f16(half %1)
   %3 = fadd half %2, %1
   ret half %3
 }
 
 declare half @llvm.minnum.f16(half, half)
 
 define half @fmin_s(half %a, half %b) nounwind {
 ; CHECKIZFH-LABEL: fmin_s:
 ; CHECKIZFH:       # %bb.0:
 ; CHECKIZFH-NEXT:    fmin.h fa0, fa0, fa1
 ; CHECKIZFH-NEXT:    ret
 ;
+; CHECK-ZHINX-LABEL: fmin_s:
+; CHECK-ZHINX:       # %bb.0:
+; CHECK-ZHINX-NEXT:    fmin.h a0, a0, a1
+; CHECK-ZHINX-NEXT:    ret
+;
 ; RV32I-LABEL: fmin_s:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s2, 0(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    mv s0, a1

 ;
 ; CHECKIZFHMIN-LABEL: fmin_s:
 ; CHECKIZFHMIN:       # %bb.0:
 ; CHECKIZFHMIN-NEXT:    fcvt.s.h fa5, fa1
 ; CHECKIZFHMIN-NEXT:    fcvt.s.h fa4, fa0
 ; CHECKIZFHMIN-NEXT:    fmin.s fa5, fa4, fa5
 ; CHECKIZFHMIN-NEXT:    fcvt.h.s fa0, fa5
 ; CHECKIZFHMIN-NEXT:    ret
+;
+; CHECKZHINXMIN-LABEL: fmin_s:
+; CHECKZHINXMIN:       # %bb.0:
+; CHECKZHINXMIN-NEXT:    fcvt.s.h a1, a1
+; CHECKZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECKZHINXMIN-NEXT:    fmin.s a0, a0, a1
+; CHECKZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; CHECKZHINXMIN-NEXT:    ret
+; CHECK-ZHINXMIN-LABEL: fmin_s:
+; CHECK-ZHINXMIN:       # %bb.0:
+; CHECK-ZHINXMIN-NEXT:    fcvt.s.h a1, a1
+; CHECK-ZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECK-ZHINXMIN-NEXT:    fmin.s a0, a0, a1
+; CHECK-ZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; CHECK-ZHINXMIN-NEXT:    ret
   %1 = call half @llvm.minnum.f16(half %a, half %b)
   ret half %1
 }
 
 declare half @llvm.maxnum.f16(half, half)
 
 define half @fmax_s(half %a, half %b) nounwind {
 ; CHECKIZFH-LABEL: fmax_s:
 ; CHECKIZFH:       # %bb.0:
 ; CHECKIZFH-NEXT:    fmax.h fa0, fa0, fa1
 ; CHECKIZFH-NEXT:    ret
 ;
+; CHECK-ZHINX-LABEL: fmax_s:
+; CHECK-ZHINX:       # %bb.0:
+; CHECK-ZHINX-NEXT:    fmax.h a0, a0, a1
+; CHECK-ZHINX-NEXT:    ret
+;
 ; RV32I-LABEL: fmax_s:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s2, 0(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    mv s0, a1

 ;
 ; CHECKIZFHMIN-LABEL: fmax_s:
 ; CHECKIZFHMIN:       # %bb.0:
 ; CHECKIZFHMIN-NEXT:    fcvt.s.h fa5, fa1
 ; CHECKIZFHMIN-NEXT:    fcvt.s.h fa4, fa0
 ; CHECKIZFHMIN-NEXT:    fmax.s fa5, fa4, fa5
 ; CHECKIZFHMIN-NEXT:    fcvt.h.s fa0, fa5
 ; CHECKIZFHMIN-NEXT:    ret
+;
+; CHECKZHINXMIN-LABEL: fmax_s:
+; CHECKZHINXMIN:       # %bb.0:
+; CHECKZHINXMIN-NEXT:    fcvt.s.h a1, a1
+; CHECKZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECKZHINXMIN-NEXT:    fmax.s a0, a0, a1
+; CHECKZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; CHECKZHINXMIN-NEXT:    ret
+; CHECK-ZHINXMIN-LABEL: fmax_s:
+; CHECK-ZHINXMIN:       # %bb.0:
+; CHECK-ZHINXMIN-NEXT:    fcvt.s.h a1, a1
+; CHECK-ZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECK-ZHINXMIN-NEXT:    fmax.s a0, a0, a1
+; CHECK-ZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; CHECK-ZHINXMIN-NEXT:    ret
   %1 = call half @llvm.maxnum.f16(half %a, half %b)
   ret half %1
 }
 
 declare half @llvm.fma.f16(half, half, half)
 
 define half @fmadd_s(half %a, half %b, half %c) nounwind {
 ; CHECKIZFH-LABEL: fmadd_s:
 ; CHECKIZFH:       # %bb.0:
 ; CHECKIZFH-NEXT:    fmadd.h fa0, fa0, fa1, fa2
 ; CHECKIZFH-NEXT:    ret
 ;
+; CHECK-ZHINX-LABEL: fmadd_s:
+; CHECK-ZHINX:       # %bb.0:
+; CHECK-ZHINX-NEXT:    fmadd.h a0, a0, a1, a2
+; CHECK-ZHINX-NEXT:    ret
+;
 ; RV32I-LABEL: fmadd_s:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -32
 ; RV32I-NEXT:    sw ra, 28(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s0, 24(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s1, 20(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s2, 16(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s3, 12(sp) # 4-byte Folded Spill

 ; CHECKIZFHMIN-LABEL: fmadd_s:
 ; CHECKIZFHMIN:       # %bb.0:
 ; CHECKIZFHMIN-NEXT:    fcvt.s.h fa5, fa2
 ; CHECKIZFHMIN-NEXT:    fcvt.s.h fa4, fa1
 ; CHECKIZFHMIN-NEXT:    fcvt.s.h fa3, fa0
 ; CHECKIZFHMIN-NEXT:    fmadd.s fa5, fa3, fa4, fa5
 ; CHECKIZFHMIN-NEXT:    fcvt.h.s fa0, fa5
 ; CHECKIZFHMIN-NEXT:    ret
+;
+; CHECKZHINXMIN-LABEL: fmadd_s:
+; CHECKZHINXMIN:       # %bb.0:
+; CHECKZHINXMIN-NEXT:    fcvt.s.h a2, a2
+; CHECKZHINXMIN-NEXT:    fcvt.s.h a1, a1
+; CHECKZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECKZHINXMIN-NEXT:    fmadd.s a0, a0, a1, a2
+; CHECKZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; CHECKZHINXMIN-NEXT:    ret
+; CHECK-ZHINXMIN-LABEL: fmadd_s:
+; CHECK-ZHINXMIN:       # %bb.0:
+; CHECK-ZHINXMIN-NEXT:    fcvt.s.h a2, a2
+; CHECK-ZHINXMIN-NEXT:    fcvt.s.h a1, a1
+; CHECK-ZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECK-ZHINXMIN-NEXT:    fmadd.s a0, a0, a1, a2
+; CHECK-ZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; CHECK-ZHINXMIN-NEXT:    ret
   %1 = call half @llvm.fma.f16(half %a, half %b, half %c)
   ret half %1
 }
 
 define half @fmsub_s(half %a, half %b, half %c) nounwind {
 ; CHECKIZFH-LABEL: fmsub_s:
 ; CHECKIZFH:       # %bb.0:
 ; CHECKIZFH-NEXT:    fmv.h.x fa5, zero
 ; CHECKIZFH-NEXT:    fadd.h fa5, fa2, fa5
 ; CHECKIZFH-NEXT:    fmsub.h fa0, fa0, fa1, fa5
 ; CHECKIZFH-NEXT:    ret
 ;
+; CHECK-ZHINX-LABEL: fmsub_s:
+; CHECK-ZHINX:       # %bb.0:
+; CHECK-ZHINX-NEXT:    fadd.h a2, a2, zero
+; CHECK-ZHINX-NEXT:    fmsub.h a0, a0, a1, a2
+; CHECK-ZHINX-NEXT:    ret
+;
 ; RV32I-LABEL: fmsub_s:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -32
 ; RV32I-NEXT:    sw ra, 28(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s0, 24(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s1, 20(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s2, 16(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s3, 12(sp) # 4-byte Folded Spill

 ; CHECKIZFHMIN-NEXT:    fneg.s fa5, fa5
 ; CHECKIZFHMIN-NEXT:    fcvt.h.s fa5, fa5
 ; CHECKIZFHMIN-NEXT:    fcvt.s.h fa5, fa5
 ; CHECKIZFHMIN-NEXT:    fcvt.s.h fa4, fa1
 ; CHECKIZFHMIN-NEXT:    fcvt.s.h fa3, fa0
 ; CHECKIZFHMIN-NEXT:    fmadd.s fa5, fa3, fa4, fa5
 ; CHECKIZFHMIN-NEXT:    fcvt.h.s fa0, fa5
 ; CHECKIZFHMIN-NEXT:    ret
+;
+; CHECKZHINXMIN-LABEL: fmsub_s:
+; CHECKZHINXMIN:       # %bb.0:
+; CHECKZHINXMIN-NEXT:    fcvt.s.h a2, a2
+; CHECKZHINXMIN-NEXT:    fadd.s a2, a2, zero
+; CHECKZHINXMIN-NEXT:    fcvt.h.s a2, a2
+; CHECKZHINXMIN-NEXT:    fcvt.s.h a2, a2
+; CHECKZHINXMIN-NEXT:    fneg.s a2, a2
+; CHECKZHINXMIN-NEXT:    fcvt.h.s a2, a2
+; CHECKZHINXMIN-NEXT:    fcvt.s.h a2, a2
+; CHECKZHINXMIN-NEXT:    fcvt.s.h a1, a1
+; CHECKZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECKZHINXMIN-NEXT:    fmadd.s a0, a0, a1, a2
+; CHECKZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; CHECKZHINXMIN-NEXT:    ret
+; CHECK-ZHINXMIN-LABEL: fmsub_s:
+; CHECK-ZHINXMIN:       # %bb.0:
+; CHECK-ZHINXMIN-NEXT:    fcvt.s.h a2, a2
+; CHECK-ZHINXMIN-NEXT:    fadd.s a2, a2, zero
+; CHECK-ZHINXMIN-NEXT:    fcvt.h.s a2, a2
+; CHECK-ZHINXMIN-NEXT:    fcvt.s.h a2, a2
+; CHECK-ZHINXMIN-NEXT:    fneg.s a2, a2
+; CHECK-ZHINXMIN-NEXT:    fcvt.h.s a2, a2
+; CHECK-ZHINXMIN-NEXT:    fcvt.s.h a2, a2
+; CHECK-ZHINXMIN-NEXT:    fcvt.s.h a1, a1
+; CHECK-ZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECK-ZHINXMIN-NEXT:    fmadd.s a0, a0, a1, a2
+; CHECK-ZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; CHECK-ZHINXMIN-NEXT:    ret
   %c_ = fadd half 0.0, %c ; avoid negation using xor
   %negc = fsub half -0.0, %c_
   %1 = call half @llvm.fma.f16(half %a, half %b, half %negc)
   ret half %1
 }
 
 define half @fnmadd_s(half %a, half %b, half %c) nounwind {
 ; CHECKIZFH-LABEL: fnmadd_s:
 ; CHECKIZFH:       # %bb.0:
 ; CHECKIZFH-NEXT:    fmv.h.x fa5, zero
 ; CHECKIZFH-NEXT:    fadd.h fa4, fa0, fa5
 ; CHECKIZFH-NEXT:    fadd.h fa5, fa2, fa5
 ; CHECKIZFH-NEXT:    fnmadd.h fa0, fa4, fa1, fa5
 ; CHECKIZFH-NEXT:    ret
 ;
+; CHECK-ZHINX-LABEL: fnmadd_s:
+; CHECK-ZHINX:       # %bb.0:
+; CHECK-ZHINX-NEXT:    fadd.h a0, a0, zero
+; CHECK-ZHINX-NEXT:    fadd.h a2, a2, zero
+; CHECK-ZHINX-NEXT:    fnmadd.h a0, a0, a1, a2
+; CHECK-ZHINX-NEXT:    ret
+;
 ; RV32I-LABEL: fnmadd_s:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -32
 ; RV32I-NEXT:    sw ra, 28(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s0, 24(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s1, 20(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s2, 16(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s3, 12(sp) # 4-byte Folded Spill

 ; CHECKIZFHMIN-NEXT:    fneg.s fa4, fa4
 ; CHECKIZFHMIN-NEXT:    fcvt.h.s fa4, fa4
 ; CHECKIZFHMIN-NEXT:    fcvt.s.h fa4, fa4
 ; CHECKIZFHMIN-NEXT:    fcvt.s.h fa5, fa5
 ; CHECKIZFHMIN-NEXT:    fcvt.s.h fa3, fa1
 ; CHECKIZFHMIN-NEXT:    fmadd.s fa5, fa5, fa3, fa4
 ; CHECKIZFHMIN-NEXT:    fcvt.h.s fa0, fa5
 ; CHECKIZFHMIN-NEXT:    ret
+;
+; CHECKZHINXMIN-LABEL: fnmadd_s:
+; CHECKZHINXMIN:       # %bb.0:
+; CHECKZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECKZHINXMIN-NEXT:    fadd.s a0, a0, zero
+; CHECKZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; CHECKZHINXMIN-NEXT:    fcvt.s.h a2, a2
+; CHECKZHINXMIN-NEXT:    fadd.s a2, a2, zero
+; CHECKZHINXMIN-NEXT:    fcvt.h.s a2, a2
+; CHECKZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECKZHINXMIN-NEXT:    fneg.s a0, a0
+; CHECKZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; CHECKZHINXMIN-NEXT:    fcvt.s.h a2, a2
+; CHECKZHINXMIN-NEXT:    fneg.s a2, a2
+; CHECKZHINXMIN-NEXT:    fcvt.h.s a2, a2
+; CHECKZHINXMIN-NEXT:    fcvt.s.h a2, a2
+; CHECKZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECKZHINXMIN-NEXT:    fcvt.s.h a1, a1
+; CHECKZHINXMIN-NEXT:    fmadd.s a0, a0, a1, a2
+; CHECKZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; CHECKZHINXMIN-NEXT:    ret
+; CHECK-ZHINXMIN-LABEL: fnmadd_s:
+; CHECK-ZHINXMIN:       # %bb.0:
+; CHECK-ZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECK-ZHINXMIN-NEXT:    fadd.s a0, a0, zero
+; CHECK-ZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; CHECK-ZHINXMIN-NEXT:    fcvt.s.h a2, a2
+; CHECK-ZHINXMIN-NEXT:    fadd.s a2, a2, zero
+; CHECK-ZHINXMIN-NEXT:    fcvt.h.s a2, a2
+; CHECK-ZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECK-ZHINXMIN-NEXT:    fneg.s a0, a0
+; CHECK-ZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; CHECK-ZHINXMIN-NEXT:    fcvt.s.h a2, a2
+; CHECK-ZHINXMIN-NEXT:    fneg.s a2, a2
+; CHECK-ZHINXMIN-NEXT:    fcvt.h.s a2, a2
+; CHECK-ZHINXMIN-NEXT:    fcvt.s.h a2, a2
+; CHECK-ZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECK-ZHINXMIN-NEXT:    fcvt.s.h a1, a1
+; CHECK-ZHINXMIN-NEXT:    fmadd.s a0, a0, a1, a2
+; CHECK-ZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; CHECK-ZHINXMIN-NEXT:    ret
   %a_ = fadd half 0.0, %a
   %c_ = fadd half 0.0, %c
   %nega = fsub half -0.0, %a_
   %negc = fsub half -0.0, %c_
   %1 = call half @llvm.fma.f16(half %nega, half %b, half %negc)
   ret half %1
 }
 
 define half @fnmadd_s_2(half %a, half %b, half %c) nounwind {
 ; CHECKIZFH-LABEL: fnmadd_s_2:
 ; CHECKIZFH:       # %bb.0:
 ; CHECKIZFH-NEXT:    fmv.h.x fa5, zero
 ; CHECKIZFH-NEXT:    fadd.h fa4, fa1, fa5
 ; CHECKIZFH-NEXT:    fadd.h fa5, fa2, fa5
 ; CHECKIZFH-NEXT:    fnmadd.h fa0, fa4, fa0, fa5
 ; CHECKIZFH-NEXT:    ret
 ;
+; CHECK-ZHINX-LABEL: fnmadd_s_2:
+; CHECK-ZHINX:       # %bb.0:
+; CHECK-ZHINX-NEXT:    fadd.h a1, a1, zero
+; CHECK-ZHINX-NEXT:    fadd.h a2, a2, zero
+; CHECK-ZHINX-NEXT:    fnmadd.h a0, a1, a0, a2
+; CHECK-ZHINX-NEXT:    ret
+;
 ; RV32I-LABEL: fnmadd_s_2:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -32
 ; RV32I-NEXT:    sw ra, 28(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s0, 24(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s1, 20(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s2, 16(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s3, 12(sp) # 4-byte Folded Spill

 ; CHECKIZFHMIN-NEXT:    fneg.s fa4, fa4
 ; CHECKIZFHMIN-NEXT:    fcvt.h.s fa4, fa4
 ; CHECKIZFHMIN-NEXT:    fcvt.s.h fa4, fa4
 ; CHECKIZFHMIN-NEXT:    fcvt.s.h fa5, fa5
 ; CHECKIZFHMIN-NEXT:    fcvt.s.h fa3, fa0
 ; CHECKIZFHMIN-NEXT:    fmadd.s fa5, fa3, fa5, fa4
 ; CHECKIZFHMIN-NEXT:    fcvt.h.s fa0, fa5
 ; CHECKIZFHMIN-NEXT:    ret
+;
+; CHECKZHINXMIN-LABEL: fnmadd_s_2:
+; CHECKZHINXMIN:       # %bb.0:
+; CHECKZHINXMIN-NEXT:    fcvt.s.h a1, a1
+; CHECKZHINXMIN-NEXT:    fadd.s a1, a1, zero
+; CHECKZHINXMIN-NEXT:    fcvt.h.s a1, a1
+; CHECKZHINXMIN-NEXT:    fcvt.s.h a2, a2
+; CHECKZHINXMIN-NEXT:    fadd.s a2, a2, zero
+; CHECKZHINXMIN-NEXT:    fcvt.h.s a2, a2
+; CHECKZHINXMIN-NEXT:    fcvt.s.h a1, a1
+; CHECKZHINXMIN-NEXT:    fneg.s a1, a1
+; CHECKZHINXMIN-NEXT:    fcvt.h.s a1, a1
+; CHECKZHINXMIN-NEXT:    fcvt.s.h a2, a2
+; CHECKZHINXMIN-NEXT:    fneg.s a2, a2
+; CHECKZHINXMIN-NEXT:    fcvt.h.s a2, a2
+; CHECKZHINXMIN-NEXT:    fcvt.s.h a2, a2
+; CHECKZHINXMIN-NEXT:    fcvt.s.h a1, a1
+; CHECKZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECKZHINXMIN-NEXT:    fmadd.s a0, a0, a1, a2
+; CHECKZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; CHECKZHINXMIN-NEXT:    ret
+; CHECK-ZHINXMIN-LABEL: fnmadd_s_2:
+; CHECK-ZHINXMIN:       # %bb.0:
+; CHECK-ZHINXMIN-NEXT:    fcvt.s.h a1, a1
+; CHECK-ZHINXMIN-NEXT:    fadd.s a1, a1, zero
+; CHECK-ZHINXMIN-NEXT:    fcvt.h.s a1, a1
+; CHECK-ZHINXMIN-NEXT:    fcvt.s.h a2, a2
+; CHECK-ZHINXMIN-NEXT:    fadd.s a2, a2, zero
+; CHECK-ZHINXMIN-NEXT:    fcvt.h.s a2, a2
+; CHECK-ZHINXMIN-NEXT:    fcvt.s.h a1, a1
+; CHECK-ZHINXMIN-NEXT:    fneg.s a1, a1
+; CHECK-ZHINXMIN-NEXT:    fcvt.h.s a1, a1
+; CHECK-ZHINXMIN-NEXT:    fcvt.s.h a2, a2
+; CHECK-ZHINXMIN-NEXT:    fneg.s a2, a2
+; CHECK-ZHINXMIN-NEXT:    fcvt.h.s a2, a2
+; CHECK-ZHINXMIN-NEXT:    fcvt.s.h a2, a2
+; CHECK-ZHINXMIN-NEXT:    fcvt.s.h a1, a1
+; CHECK-ZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECK-ZHINXMIN-NEXT:    fmadd.s a0, a0, a1, a2
+; CHECK-ZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; CHECK-ZHINXMIN-NEXT:    ret
   %b_ = fadd half 0.0, %b
   %c_ = fadd half 0.0, %c
   %negb = fsub half -0.0, %b_
   %negc = fsub half -0.0, %c_
   %1 = call half @llvm.fma.f16(half %a, half %negb, half %negc)
   ret half %1
 }
 

 ; RV64IZFH-NEXT:    ret
 ;
 ; CHECKIZFH-LABEL: fnmadd_s_3:
 ; CHECKIZFH:       # %bb.0:
 ; CHECKIZFH-NEXT:    fmadd.h fa5, fa0, fa1, fa2
 ; CHECKIZFH-NEXT:    fneg.h fa0, fa5
 ; CHECKIZFH-NEXT:    ret
 ;
+; CHECK-ZHINX-LABEL: fnmadd_s_3:
+; CHECK-ZHINX:       # %bb.0:
+; CHECK-ZHINX-NEXT:    fmadd.h a0, a0, a1, a2
+; CHECK-ZHINX-NEXT:    lui a1, 1048568
+; CHECK-ZHINX-NEXT:    xor a0, a0, a1
+; CHECK-ZHINX-NEXT:    ret
+;
 ; RV32I-LABEL: fnmadd_s_3:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -32
 ; RV32I-NEXT:    sw ra, 28(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s0, 24(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s1, 20(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s2, 16(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s3, 12(sp) # 4-byte Folded Spill

 ; CHECKIZFHMIN-NEXT:    fcvt.s.h fa4, fa1
 ; CHECKIZFHMIN-NEXT:    fcvt.s.h fa3, fa0
 ; CHECKIZFHMIN-NEXT:    fmadd.s fa5, fa3, fa4, fa5
 ; CHECKIZFHMIN-NEXT:    fcvt.h.s fa5, fa5
 ; CHECKIZFHMIN-NEXT:    fcvt.s.h fa5, fa5
 ; CHECKIZFHMIN-NEXT:    fneg.s fa5, fa5
 ; CHECKIZFHMIN-NEXT:    fcvt.h.s fa0, fa5
 ; CHECKIZFHMIN-NEXT:    ret
+;
+; CHECKZHINXMIN-LABEL: fnmadd_s_3:
+; CHECKZHINXMIN:       # %bb.0:
+; CHECKZHINXMIN-NEXT:    fcvt.s.h a2, a2
+; CHECKZHINXMIN-NEXT:    fcvt.s.h a1, a1
+; CHECKZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECKZHINXMIN-NEXT:    fmadd.s a0, a0, a1, a2
+; CHECKZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; CHECKZHINXMIN-NEXT:    lui a1, 1048568
+; CHECKZHINXMIN-NEXT:    xor a0, a0, a1
+; CHECKZHINXMIN-NEXT:    ret
+; CHECK-ZHINXMIN-LABEL: fnmadd_s_3:
+; CHECK-ZHINXMIN:       # %bb.0:
+; CHECK-ZHINXMIN-NEXT:    fcvt.s.h a2, a2
+; CHECK-ZHINXMIN-NEXT:    fcvt.s.h a1, a1
+; CHECK-ZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECK-ZHINXMIN-NEXT:    fmadd.s a0, a0, a1, a2
+; CHECK-ZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; CHECK-ZHINXMIN-NEXT:    lui a1, 1048568
+; CHECK-ZHINXMIN-NEXT:    xor a0, a0, a1
+; CHECK-ZHINXMIN-NEXT:    ret
   %1 = call half @llvm.fma.f16(half %a, half %b, half %c)
   %neg = fneg half %1
   ret half %neg
 }
 
 
 define half @fnmadd_nsz(half %a, half %b, half %c) nounwind {
 ; RV32IZFH-LABEL: fnmadd_nsz:
 ; RV32IZFH:       # %bb.0:
 ; RV32IZFH-NEXT:    fnmadd.h fa0, fa0, fa1, fa2
 ; RV32IZFH-NEXT:    ret
 ;
 ; RV64IZFH-LABEL: fnmadd_nsz:
 ; RV64IZFH:       # %bb.0:
 ; RV64IZFH-NEXT:    fnmadd.h fa0, fa0, fa1, fa2
 ; RV64IZFH-NEXT:    ret
 ;
 ; CHECKIZFH-LABEL: fnmadd_nsz:
 ; CHECKIZFH:       # %bb.0:
 ; CHECKIZFH-NEXT:    fnmadd.h fa0, fa0, fa1, fa2
 ; CHECKIZFH-NEXT:    ret
 ;
+; CHECK-ZHINX-LABEL: fnmadd_nsz:
+; CHECK-ZHINX:       # %bb.0:
+; CHECK-ZHINX-NEXT:    fmadd.h a0, a0, a1, a2
+; CHECK-ZHINX-NEXT:    lui a1, 1048568
+; CHECK-ZHINX-NEXT:    xor a0, a0, a1
+; CHECK-ZHINX-NEXT:    ret
+;
 ; RV32I-LABEL: fnmadd_nsz:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -32
 ; RV32I-NEXT:    sw ra, 28(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s0, 24(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s1, 20(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s2, 16(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s3, 12(sp) # 4-byte Folded Spill

 ; CHECKIZFHMIN-NEXT:    fcvt.s.h fa4, fa1
 ; CHECKIZFHMIN-NEXT:    fcvt.s.h fa3, fa0
 ; CHECKIZFHMIN-NEXT:    fmadd.s fa5, fa3, fa4, fa5
 ; CHECKIZFHMIN-NEXT:    fcvt.h.s fa5, fa5
 ; CHECKIZFHMIN-NEXT:    fcvt.s.h fa5, fa5
 ; CHECKIZFHMIN-NEXT:    fneg.s fa5, fa5
 ; CHECKIZFHMIN-NEXT:    fcvt.h.s fa0, fa5
 ; CHECKIZFHMIN-NEXT:    ret
+;
+; CHECKZHINXMIN-LABEL: fnmadd_nsz:
+; CHECKZHINXMIN:       # %bb.0:
+; CHECKZHINXMIN-NEXT:    fcvt.s.h a2, a2
+; CHECKZHINXMIN-NEXT:    fcvt.s.h a1, a1
+; CHECKZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECKZHINXMIN-NEXT:    fmadd.s a0, a0, a1, a2
+; CHECKZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; CHECKZHINXMIN-NEXT:    lui a1, 1048568
+; CHECKZHINXMIN-NEXT:    xor a0, a0, a1
+; CHECKZHINXMIN-NEXT:    ret
+; CHECK-ZHINXMIN-LABEL: fnmadd_nsz:
+; CHECK-ZHINXMIN:       # %bb.0:
+; CHECK-ZHINXMIN-NEXT:    fcvt.s.h a2, a2
+; CHECK-ZHINXMIN-NEXT:    fcvt.s.h a1, a1
+; CHECK-ZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECK-ZHINXMIN-NEXT:    fmadd.s a0, a0, a1, a2
+; CHECK-ZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; CHECK-ZHINXMIN-NEXT:    lui a1, 1048568
+; CHECK-ZHINXMIN-NEXT:    xor a0, a0, a1
+; CHECK-ZHINXMIN-NEXT:    ret
   %1 = call nsz half @llvm.fma.f16(half %a, half %b, half %c)
   %neg = fneg nsz half %1
   ret half %neg
 }
 
 define half @fnmsub_s(half %a, half %b, half %c) nounwind {
 ; CHECKIZFH-LABEL: fnmsub_s:
 ; CHECKIZFH:       # %bb.0:
 ; CHECKIZFH-NEXT:    fmv.h.x fa5, zero
 ; CHECKIZFH-NEXT:    fadd.h fa5, fa0, fa5
 ; CHECKIZFH-NEXT:    fnmsub.h fa0, fa5, fa1, fa2
 ; CHECKIZFH-NEXT:    ret
 ;
+; CHECK-ZHINX-LABEL: fnmsub_s:
+; CHECK-ZHINX:       # %bb.0:
+; CHECK-ZHINX-NEXT:    fadd.h a0, a0, zero
+; CHECK-ZHINX-NEXT:    fnmsub.h a0, a0, a1, a2
+; CHECK-ZHINX-NEXT:    ret
+;
 ; RV32I-LABEL: fnmsub_s:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -32
 ; RV32I-NEXT:    sw ra, 28(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s0, 24(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s1, 20(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s2, 16(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s3, 12(sp) # 4-byte Folded Spill

 ; CHECKIZFHMIN-NEXT:    fneg.s fa5, fa5
 ; CHECKIZFHMIN-NEXT:    fcvt.h.s fa5, fa5
 ; CHECKIZFHMIN-NEXT:    fcvt.s.h fa5, fa5
 ; CHECKIZFHMIN-NEXT:    fcvt.s.h fa4, fa2
 ; CHECKIZFHMIN-NEXT:    fcvt.s.h fa3, fa1
 ; CHECKIZFHMIN-NEXT:    fmadd.s fa5, fa5, fa3, fa4
 ; CHECKIZFHMIN-NEXT:    fcvt.h.s fa0, fa5
 ; CHECKIZFHMIN-NEXT:    ret
+;
+; CHECKZHINXMIN-LABEL: fnmsub_s:
+; CHECKZHINXMIN:       # %bb.0:
+; CHECKZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECKZHINXMIN-NEXT:    fadd.s a0, a0, zero
+; CHECKZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; CHECKZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECKZHINXMIN-NEXT:    fneg.s a0, a0
+; CHECKZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; CHECKZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECKZHINXMIN-NEXT:    fcvt.s.h a2, a2
+; CHECKZHINXMIN-NEXT:    fcvt.s.h a1, a1
+; CHECKZHINXMIN-NEXT:    fmadd.s a0, a0, a1, a2
+; CHECKZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; CHECKZHINXMIN-NEXT:    ret
+; CHECK-ZHINXMIN-LABEL: fnmsub_s:
+; CHECK-ZHINXMIN:       # %bb.0:
+; CHECK-ZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECK-ZHINXMIN-NEXT:    fadd.s a0, a0, zero
+; CHECK-ZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; CHECK-ZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECK-ZHINXMIN-NEXT:    fneg.s a0, a0
+; CHECK-ZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; CHECK-ZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECK-ZHINXMIN-NEXT:    fcvt.s.h a2, a2
+; CHECK-ZHINXMIN-NEXT:    fcvt.s.h a1, a1
+; CHECK-ZHINXMIN-NEXT:    fmadd.s a0, a0, a1, a2
+; CHECK-ZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; CHECK-ZHINXMIN-NEXT:    ret
   %a_ = fadd half 0.0, %a
   %nega = fsub half -0.0, %a_
   %1 = call half @llvm.fma.f16(half %nega, half %b, half %c)
   ret half %1
 }
 
 define half @fnmsub_s_2(half %a, half %b, half %c) nounwind {
 ; CHECKIZFH-LABEL: fnmsub_s_2:
 ; CHECKIZFH:       # %bb.0:
 ; CHECKIZFH-NEXT:    fmv.h.x fa5, zero
 ; CHECKIZFH-NEXT:    fadd.h fa5, fa1, fa5
 ; CHECKIZFH-NEXT:    fnmsub.h fa0, fa5, fa0, fa2
 ; CHECKIZFH-NEXT:    ret
 ;
+; CHECK-ZHINX-LABEL: fnmsub_s_2:
+; CHECK-ZHINX:       # %bb.0:
+; CHECK-ZHINX-NEXT:    fadd.h a1, a1, zero
+; CHECK-ZHINX-NEXT:    fnmsub.h a0, a1, a0, a2
+; CHECK-ZHINX-NEXT:    ret
+;
 ; RV32I-LABEL: fnmsub_s_2:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -32
 ; RV32I-NEXT:    sw ra, 28(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s0, 24(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s1, 20(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s2, 16(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s3, 12(sp) # 4-byte Folded Spill

 ; CHECKIZFHMIN-NEXT:    fneg.s fa5, fa5
 ; CHECKIZFHMIN-NEXT:    fcvt.h.s fa5, fa5
 ; CHECKIZFHMIN-NEXT:    fcvt.s.h fa5, fa5
 ; CHECKIZFHMIN-NEXT:    fcvt.s.h fa4, fa2
 ; CHECKIZFHMIN-NEXT:    fcvt.s.h fa3, fa0
 ; CHECKIZFHMIN-NEXT:    fmadd.s fa5, fa3, fa5, fa4
 ; CHECKIZFHMIN-NEXT:    fcvt.h.s fa0, fa5
 ; CHECKIZFHMIN-NEXT:    ret
+;
+; CHECKZHINXMIN-LABEL: fnmsub_s_2:
+; CHECKZHINXMIN:       # %bb.0:
+; CHECKZHINXMIN-NEXT:    fcvt.s.h a1, a1
+; CHECKZHINXMIN-NEXT:    fadd.s a1, a1, zero
+; CHECKZHINXMIN-NEXT:    fcvt.h.s a1, a1
+; CHECKZHINXMIN-NEXT:    fcvt.s.h a1, a1
+; CHECKZHINXMIN-NEXT:    fneg.s a1, a1
+; CHECKZHINXMIN-NEXT:    fcvt.h.s a1, a1
+; CHECKZHINXMIN-NEXT:    fcvt.s.h a1, a1
+; CHECKZHINXMIN-NEXT:    fcvt.s.h a2, a2
+; CHECKZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECKZHINXMIN-NEXT:    fmadd.s a0, a0, a1, a2
+; CHECKZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; CHECKZHINXMIN-NEXT:    ret
+; CHECK-ZHINXMIN-LABEL: fnmsub_s_2:
+; CHECK-ZHINXMIN:       # %bb.0:
+; CHECK-ZHINXMIN-NEXT:    fcvt.s.h a1, a1
+; CHECK-ZHINXMIN-NEXT:    fadd.s a1, a1, zero
+; CHECK-ZHINXMIN-NEXT:    fcvt.h.s a1, a1
+; CHECK-ZHINXMIN-NEXT:    fcvt.s.h a1, a1
+; CHECK-ZHINXMIN-NEXT:    fneg.s a1, a1
+; CHECK-ZHINXMIN-NEXT:    fcvt.h.s a1, a1
+; CHECK-ZHINXMIN-NEXT:    fcvt.s.h a1, a1
+; CHECK-ZHINXMIN-NEXT:    fcvt.s.h a2, a2
+; CHECK-ZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECK-ZHINXMIN-NEXT:    fmadd.s a0, a0, a1, a2
+; CHECK-ZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; CHECK-ZHINXMIN-NEXT:    ret
   %b_ = fadd half 0.0, %b
   %negb = fsub half -0.0, %b_
   %1 = call half @llvm.fma.f16(half %a, half %negb, half %c)
   ret half %1
 }
 
 define half @fmadd_s_contract(half %a, half %b, half %c) nounwind {
 ; CHECKIZFH-LABEL: fmadd_s_contract:
 ; CHECKIZFH:       # %bb.0:
 ; CHECKIZFH-NEXT:    fmadd.h fa0, fa0, fa1, fa2
 ; CHECKIZFH-NEXT:    ret
 ;
+; CHECK-ZHINX-LABEL: fmadd_s_contract:
+; CHECK-ZHINX:       # %bb.0:
+; CHECK-ZHINX-NEXT:    fmadd.h a0, a0, a1, a2
+; CHECK-ZHINX-NEXT:    ret
+;
 ; RV32I-LABEL: fmadd_s_contract:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -32
 ; RV32I-NEXT:    sw ra, 28(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s0, 24(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s1, 20(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s2, 16(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s3, 12(sp) # 4-byte Folded Spill

 ; CHECKIZFHMIN-NEXT:    fcvt.s.h fa4, fa0
 ; CHECKIZFHMIN-NEXT:    fmul.s fa5, fa4, fa5
 ; CHECKIZFHMIN-NEXT:    fcvt.h.s fa5, fa5
 ; CHECKIZFHMIN-NEXT:    fcvt.s.h fa5, fa5
 ; CHECKIZFHMIN-NEXT:    fcvt.s.h fa4, fa2
 ; CHECKIZFHMIN-NEXT:    fadd.s fa5, fa5, fa4
 ; CHECKIZFHMIN-NEXT:    fcvt.h.s fa0, fa5
 ; CHECKIZFHMIN-NEXT:    ret
+;
+; CHECKZHINXMIN-LABEL: fmadd_s_contract:
+; CHECKZHINXMIN:       # %bb.0:
+; CHECKZHINXMIN-NEXT:    fcvt.s.h a1, a1
+; CHECKZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECKZHINXMIN-NEXT:    fmul.s a0, a0, a1
+; CHECKZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; CHECKZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECKZHINXMIN-NEXT:    fcvt.s.h a1, a2
+; CHECKZHINXMIN-NEXT:    fadd.s a0, a0, a1
+; CHECKZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; CHECKZHINXMIN-NEXT:    ret
+; CHECK-ZHINXMIN-LABEL: fmadd_s_contract:
+; CHECK-ZHINXMIN:       # %bb.0:
+; CHECK-ZHINXMIN-NEXT:    fcvt.s.h a1, a1
+; CHECK-ZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECK-ZHINXMIN-NEXT:    fmul.s a0, a0, a1
+; CHECK-ZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; CHECK-ZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECK-ZHINXMIN-NEXT:    fcvt.s.h a1, a2
+; CHECK-ZHINXMIN-NEXT:    fadd.s a0, a0, a1
+; CHECK-ZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; CHECK-ZHINXMIN-NEXT:    ret
   %1 = fmul contract half %a, %b
   %2 = fadd contract half %1, %c
   ret half %2
 }
 
 define half @fmsub_s_contract(half %a, half %b, half %c) nounwind {
 ; CHECKIZFH-LABEL: fmsub_s_contract:
 ; CHECKIZFH:       # %bb.0:
 ; CHECKIZFH-NEXT:    fmv.h.x fa5, zero
 ; CHECKIZFH-NEXT:    fadd.h fa5, fa2, fa5
 ; CHECKIZFH-NEXT:    fmsub.h fa0, fa0, fa1, fa5
 ; CHECKIZFH-NEXT:    ret
 ;
+; CHECK-ZHINX-LABEL: fmsub_s_contract:
+; CHECK-ZHINX:       # %bb.0:
+; CHECK-ZHINX-NEXT:    fadd.h a2, a2, zero
+; CHECK-ZHINX-NEXT:    fmsub.h a0, a0, a1, a2
+; CHECK-ZHINX-NEXT:    ret
+;
 ; RV32I-LABEL: fmsub_s_contract:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -32
 ; RV32I-NEXT:    sw ra, 28(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s0, 24(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s1, 20(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s2, 16(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s3, 12(sp) # 4-byte Folded Spill

 ; CHECKIZFHMIN-NEXT:    fcvt.s.h fa3, fa0
 ; CHECKIZFHMIN-NEXT:    fmul.s fa4, fa3, fa4
 ; CHECKIZFHMIN-NEXT:    fcvt.h.s fa4, fa4
 ; CHECKIZFHMIN-NEXT:    fcvt.s.h fa5, fa5
 ; CHECKIZFHMIN-NEXT:    fcvt.s.h fa4, fa4
 ; CHECKIZFHMIN-NEXT:    fsub.s fa5, fa4, fa5
 ; CHECKIZFHMIN-NEXT:    fcvt.h.s fa0, fa5
 ; CHECKIZFHMIN-NEXT:    ret
+;
+; CHECKZHINXMIN-LABEL: fmsub_s_contract:
+; CHECKZHINXMIN:       # %bb.0:
+; CHECKZHINXMIN-NEXT:    fcvt.s.h a2, a2
+; CHECKZHINXMIN-NEXT:    fadd.s a2, a2, zero
+; CHECKZHINXMIN-NEXT:    fcvt.h.s a2, a2
+; CHECKZHINXMIN-NEXT:    fcvt.s.h a1, a1
+; CHECKZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECKZHINXMIN-NEXT:    fmul.s a0, a0, a1
+; CHECKZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; CHECKZHINXMIN-NEXT:    fcvt.s.h a1, a2
+; CHECKZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECKZHINXMIN-NEXT:    fsub.s a0, a0, a1
+; CHECKZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; CHECKZHINXMIN-NEXT:    ret
+; CHECK-ZHINXMIN-LABEL: fmsub_s_contract:
+; CHECK-ZHINXMIN:       # %bb.0:
+; CHECK-ZHINXMIN-NEXT:    fcvt.s.h a2, a2
+; CHECK-ZHINXMIN-NEXT:    fadd.s a2, a2, zero
+; CHECK-ZHINXMIN-NEXT:    fcvt.h.s a2, a2
+; CHECK-ZHINXMIN-NEXT:    fcvt.s.h a1, a1
+; CHECK-ZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECK-ZHINXMIN-NEXT:    fmul.s a0, a0, a1
+; CHECK-ZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; CHECK-ZHINXMIN-NEXT:    fcvt.s.h a1, a2
+; CHECK-ZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECK-ZHINXMIN-NEXT:    fsub.s a0, a0, a1
+; CHECK-ZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; CHECK-ZHINXMIN-NEXT:    ret
   %c_ = fadd half 0.0, %c ; avoid negation using xor
   %1 = fmul contract half %a, %b
   %2 = fsub contract half %1, %c_
   ret half %2
 }
 
 define half @fnmadd_s_contract(half %a, half %b, half %c) nounwind {
 ; CHECKIZFH-LABEL: fnmadd_s_contract:
 ; CHECKIZFH:       # %bb.0:
 ; CHECKIZFH-NEXT:    fmv.h.x fa5, zero
 ; CHECKIZFH-NEXT:    fadd.h fa4, fa0, fa5
 ; CHECKIZFH-NEXT:    fadd.h fa3, fa1, fa5
 ; CHECKIZFH-NEXT:    fadd.h fa5, fa2, fa5
 ; CHECKIZFH-NEXT:    fnmadd.h fa0, fa4, fa3, fa5
 ; CHECKIZFH-NEXT:    ret
 ;
+; CHECK-ZHINX-LABEL: fnmadd_s_contract:
+; CHECK-ZHINX:       # %bb.0:
+; CHECK-ZHINX-NEXT:    fadd.h a0, a0, zero
+; CHECK-ZHINX-NEXT:    fadd.h a1, a1, zero
+; CHECK-ZHINX-NEXT:    fadd.h a2, a2, zero
+; CHECK-ZHINX-NEXT:    fnmadd.h a0, a0, a1, a2
+; CHECK-ZHINX-NEXT:    ret
+;
 ; RV32I-LABEL: fnmadd_s_contract:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -32
 ; RV32I-NEXT:    sw ra, 28(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s0, 24(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s1, 20(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s2, 16(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s3, 12(sp) # 4-byte Folded Spill

 ; CHECKIZFHMIN-NEXT:    fcvt.s.h fa5, fa5
 ; CHECKIZFHMIN-NEXT:    fneg.s fa5, fa5
 ; CHECKIZFHMIN-NEXT:    fcvt.h.s fa5, fa5
 ; CHECKIZFHMIN-NEXT:    fcvt.s.h fa5, fa5
 ; CHECKIZFHMIN-NEXT:    fcvt.s.h fa4, fa4
 ; CHECKIZFHMIN-NEXT:    fsub.s fa5, fa5, fa4
 ; CHECKIZFHMIN-NEXT:    fcvt.h.s fa0, fa5
 ; CHECKIZFHMIN-NEXT:    ret
+;
+; CHECKZHINXMIN-LABEL: fnmadd_s_contract:
+; CHECKZHINXMIN:       # %bb.0:
+; CHECKZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECKZHINXMIN-NEXT:    fadd.s a0, a0, zero
+; CHECKZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; CHECKZHINXMIN-NEXT:    fcvt.s.h a1, a1
+; CHECKZHINXMIN-NEXT:    fadd.s a1, a1, zero
+; CHECKZHINXMIN-NEXT:    fcvt.h.s a1, a1
+; CHECKZHINXMIN-NEXT:    fcvt.s.h a2, a2
+; CHECKZHINXMIN-NEXT:    fadd.s a2, a2, zero
+; CHECKZHINXMIN-NEXT:    fcvt.h.s a2, a2
+; CHECKZHINXMIN-NEXT:    fcvt.s.h a1, a1
+; CHECKZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECKZHINXMIN-NEXT:    fmul.s a0, a0, a1
+; CHECKZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; CHECKZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECKZHINXMIN-NEXT:    fneg.s a0, a0
+; CHECKZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; CHECKZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECKZHINXMIN-NEXT:    fcvt.s.h a1, a2
+; CHECKZHINXMIN-NEXT:    fsub.s a0, a0, a1
+; CHECKZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; CHECKZHINXMIN-NEXT:    ret
+; CHECK-ZHINXMIN-LABEL: fnmadd_s_contract:
+; CHECK-ZHINXMIN:       # %bb.0:
+; CHECK-ZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECK-ZHINXMIN-NEXT:    fadd.s a0, a0, zero
+; CHECK-ZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; CHECK-ZHINXMIN-NEXT:    fcvt.s.h a1, a1
+; CHECK-ZHINXMIN-NEXT:    fadd.s a1, a1, zero
+; CHECK-ZHINXMIN-NEXT:    fcvt.h.s a1, a1
+; CHECK-ZHINXMIN-NEXT:    fcvt.s.h a2, a2
+; CHECK-ZHINXMIN-NEXT:    fadd.s a2, a2, zero
+; CHECK-ZHINXMIN-NEXT:    fcvt.h.s a2, a2
+; CHECK-ZHINXMIN-NEXT:    fcvt.s.h a1, a1
+; CHECK-ZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECK-ZHINXMIN-NEXT:    fmul.s a0, a0, a1
+; CHECK-ZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; CHECK-ZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECK-ZHINXMIN-NEXT:    fneg.s a0, a0
+; CHECK-ZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; CHECK-ZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECK-ZHINXMIN-NEXT:    fcvt.s.h a1, a2
+; CHECK-ZHINXMIN-NEXT:    fsub.s a0, a0, a1
+; CHECK-ZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; CHECK-ZHINXMIN-NEXT:    ret
   %a_ = fadd half 0.0, %a ; avoid negation using xor
   %b_ = fadd half 0.0, %b ; avoid negation using xor
   %c_ = fadd half 0.0, %c ; avoid negation using xor
   %1 = fmul contract half %a_, %b_
   %2 = fneg half %1
   %3 = fsub contract half %2, %c_
   ret half %3
 }
 
 define half @fnmsub_s_contract(half %a, half %b, half %c) nounwind {
 ; CHECKIZFH-LABEL: fnmsub_s_contract:
 ; CHECKIZFH:       # %bb.0:
 ; CHECKIZFH-NEXT:    fmv.h.x fa5, zero
 ; CHECKIZFH-NEXT:    fadd.h fa4, fa0, fa5
 ; CHECKIZFH-NEXT:    fadd.h fa5, fa1, fa5
 ; CHECKIZFH-NEXT:    fnmsub.h fa0, fa4, fa5, fa2
 ; CHECKIZFH-NEXT:    ret
 ;
+; CHECK-ZHINX-LABEL: fnmsub_s_contract:
+; CHECK-ZHINX:       # %bb.0:
+; CHECK-ZHINX-NEXT:    fadd.h a0, a0, zero
+; CHECK-ZHINX-NEXT:    fadd.h a1, a1, zero
+; CHECK-ZHINX-NEXT:    fnmsub.h a0, a0, a1, a2
+; CHECK-ZHINX-NEXT:    ret
+;
 ; RV32I-LABEL: fnmsub_s_contract:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -32
 ; RV32I-NEXT:    sw ra, 28(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s0, 24(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s1, 20(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s2, 16(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s3, 12(sp) # 4-byte Folded Spill

 ; CHECKIZFHMIN-NEXT:    fcvt.s.h fa5, fa5
 ; CHECKIZFHMIN-NEXT:    fmul.s fa5, fa5, fa4
 ; CHECKIZFHMIN-NEXT:    fcvt.h.s fa5, fa5
 ; CHECKIZFHMIN-NEXT:    fcvt.s.h fa5, fa5
 ; CHECKIZFHMIN-NEXT:    fcvt.s.h fa4, fa2
 ; CHECKIZFHMIN-NEXT:    fsub.s fa5, fa4, fa5
 ; CHECKIZFHMIN-NEXT:    fcvt.h.s fa0, fa5
 ; CHECKIZFHMIN-NEXT:    ret
+;
+; CHECKZHINXMIN-LABEL: fnmsub_s_contract:
+; CHECKZHINXMIN:       # %bb.0:
+; CHECKZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECKZHINXMIN-NEXT:    fadd.s a0, a0, zero
+; CHECKZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; CHECKZHINXMIN-NEXT:    fcvt.s.h a1, a1
+; CHECKZHINXMIN-NEXT:    fadd.s a1, a1, zero
+; CHECKZHINXMIN-NEXT:    fcvt.h.s a1, a1
+; CHECKZHINXMIN-NEXT:    fcvt.s.h a1, a1
+; CHECKZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECKZHINXMIN-NEXT:    fmul.s a0, a0, a1
+; CHECKZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; CHECKZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECKZHINXMIN-NEXT:    fcvt.s.h a1, a2
+; CHECKZHINXMIN-NEXT:    fsub.s a0, a1, a0
+; CHECKZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; CHECKZHINXMIN-NEXT:    ret
+; CHECK-ZHINXMIN-LABEL: fnmsub_s_contract:
+; CHECK-ZHINXMIN:       # %bb.0:
+; CHECK-ZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECK-ZHINXMIN-NEXT:    fadd.s a0, a0, zero
+; CHECK-ZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; CHECK-ZHINXMIN-NEXT:    fcvt.s.h a1, a1
+; CHECK-ZHINXMIN-NEXT:    fadd.s a1, a1, zero
+; CHECK-ZHINXMIN-NEXT:    fcvt.h.s a1, a1
+; CHECK-ZHINXMIN-NEXT:    fcvt.s.h a1, a1
+; CHECK-ZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECK-ZHINXMIN-NEXT:    fmul.s a0, a0, a1
+; CHECK-ZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; CHECK-ZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECK-ZHINXMIN-NEXT:    fcvt.s.h a1, a2
+; CHECK-ZHINXMIN-NEXT:    fsub.s a0, a1, a0
+; CHECK-ZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; CHECK-ZHINXMIN-NEXT:    ret
   %a_ = fadd half 0.0, %a ; avoid negation using xor
   %b_ = fadd half 0.0, %b ; avoid negation using xor
   %1 = fmul contract half %a_, %b_
   %2 = fsub contract half %c, %1
   ret half %2
 }

llvm/test/CodeGen/RISCV/half-bitmanip-dagcombines.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
 ; RUN:   | FileCheck -check-prefix=RV32I %s
 ; RUN: llc -mtriple=riscv32 -mattr=+zfh -verify-machineinstrs \
 ; RUN:   < %s | FileCheck -check-prefix=RV32IZFH %s
 ; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
 ; RUN:   | FileCheck -check-prefix=RV64I %s
 ; RUN: llc -mtriple=riscv64 -mattr=+zfh -verify-machineinstrs \
 ; RUN:   < %s | FileCheck -check-prefix=RV64IZFH %s
+; RUN: llc -mtriple=riscv32 -mattr=+zhinx -verify-machineinstrs \
+; RUN:   < %s | FileCheck -check-prefix=RV32IZHINX %s
+; RUN: llc -mtriple=riscv64 -mattr=+zhinx -verify-machineinstrs \
+; RUN:   < %s | FileCheck -check-prefix=RV64IZHINX %s
 ; RUN: llc -mtriple=riscv32 -mattr=+zfhmin -verify-machineinstrs \
 ; RUN:   < %s | FileCheck -check-prefix=RV32IZFHMIN %s
 ; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
 ; RUN:   | FileCheck -check-prefix=RV64I %s
 ; RUN: llc -mtriple=riscv64 -mattr=+zfhmin -verify-machineinstrs \
 ; RUN:   < %s | FileCheck -check-prefix=RV64IZFHMIN %s
+; RUN: llc -mtriple=riscv32 -mattr=+zhinxmin -verify-machineinstrs \
+; RUN:   < %s | FileCheck --check-prefixes=RVIZHINXMIN,RV32IZHINXMIN %s
+; RUN: llc -mtriple=riscv64 -mattr=+zhinxmin -verify-machineinstrs \
+; RUN:   < %s | FileCheck --check-prefixes=RVIZHINXMIN,RV64IZHINXMIN %s
 
 ; This file tests cases where simple floating point operations can be
 ; profitably handled though bit manipulation if a soft-float ABI is being used
 ; (e.g. fneg implemented by XORing the sign bit). This is typically handled in
 ; DAGCombiner::visitBITCAST, but this target-independent code may not trigger
 ; in cases where we perform custom legalisation (e.g. RV64F).
 
 define half @fneg(half %a) nounwind {

 ; RV64I-NEXT:    ret
 ;
 ; RV64IZFH-LABEL: fneg:
 ; RV64IZFH:       # %bb.0:
 ; RV64IZFH-NEXT:    lui a1, 1048568
 ; RV64IZFH-NEXT:    xor a0, a0, a1
 ; RV64IZFH-NEXT:    ret
 ;
+; RV32IZHINX-LABEL: fneg:
+; RV32IZHINX:       # %bb.0:
+; RV32IZHINX-NEXT:    lui a1, 1048568
+; RV32IZHINX-NEXT:    xor a0, a0, a1
+; RV32IZHINX-NEXT:    ret
+;
+; RV64IZHINX-LABEL: fneg:
+; RV64IZHINX:       # %bb.0:
+; RV64IZHINX-NEXT:    lui a1, 1048568
+; RV64IZHINX-NEXT:    xor a0, a0, a1
+; RV64IZHINX-NEXT:    ret
+;
 ; RV32IZFHMIN-LABEL: fneg:
 ; RV32IZFHMIN:       # %bb.0:
 ; RV32IZFHMIN-NEXT:    lui a1, 1048568
 ; RV32IZFHMIN-NEXT:    xor a0, a0, a1
 ; RV32IZFHMIN-NEXT:    ret
 ;
 ; RV64IZFHMIN-LABEL: fneg:
 ; RV64IZFHMIN:       # %bb.0:
 ; RV64IZFHMIN-NEXT:    lui a1, 1048568
 ; RV64IZFHMIN-NEXT:    xor a0, a0, a1
 ; RV64IZFHMIN-NEXT:    ret
+;
+; RVIZHINXMIN-LABEL: fneg:
+; RVIZHINXMIN:       # %bb.0:
+; RVIZHINXMIN-NEXT:    lui a1, 1048568
+; RVIZHINXMIN-NEXT:    xor a0, a0, a1
+; RVIZHINXMIN-NEXT:    ret
   %1 = fneg half %a
   ret half %1
 }
 
 declare half @llvm.fabs.f16(half)
 
 define half @fabs(half %a) nounwind {
 ; RV32I-LABEL: fabs:

 ; RV64I-NEXT:    ret
 ;
 ; RV64IZFH-LABEL: fabs:
 ; RV64IZFH:       # %bb.0:
 ; RV64IZFH-NEXT:    slli a0, a0, 49
 ; RV64IZFH-NEXT:    srli a0, a0, 49
 ; RV64IZFH-NEXT:    ret
 ;
+; RV32IZHINX-LABEL: fabs:
+; RV32IZHINX:       # %bb.0:
+; RV32IZHINX-NEXT:    slli a0, a0, 17
+; RV32IZHINX-NEXT:    srli a0, a0, 17
+; RV32IZHINX-NEXT:    ret
+;
+; RV64IZHINX-LABEL: fabs:
+; RV64IZHINX:       # %bb.0:
+; RV64IZHINX-NEXT:    slli a0, a0, 49
+; RV64IZHINX-NEXT:    srli a0, a0, 49
+; RV64IZHINX-NEXT:    ret
+;
 ; RV32IZFHMIN-LABEL: fabs:
 ; RV32IZFHMIN:       # %bb.0:
 ; RV32IZFHMIN-NEXT:    slli a0, a0, 17
 ; RV32IZFHMIN-NEXT:    srli a0, a0, 17
 ; RV32IZFHMIN-NEXT:    ret
 ;
 ; RV64IZFHMIN-LABEL: fabs:
 ; RV64IZFHMIN:       # %bb.0:
 ; RV64IZFHMIN-NEXT:    slli a0, a0, 49
 ; RV64IZFHMIN-NEXT:    srli a0, a0, 49
 ; RV64IZFHMIN-NEXT:    ret
+;
+; RV32IZHINXMIN-LABEL: fabs:
+; RV32IZHINXMIN:       # %bb.0:
+; RV32IZHINXMIN-NEXT:    slli a0, a0, 17
+; RV32IZHINXMIN-NEXT:    srli a0, a0, 17
+; RV32IZHINXMIN-NEXT:    ret
+;
+; RV64IZHINXMIN-LABEL: fabs:
+; RV64IZHINXMIN:       # %bb.0:
+; RV64IZHINXMIN-NEXT:    slli a0, a0, 49
+; RV64IZHINXMIN-NEXT:    srli a0, a0, 49
+; RV64IZHINXMIN-NEXT:    ret
   %1 = call half @llvm.fabs.f16(half %a)
   ret half %1
 }
 
 declare half @llvm.copysign.f16(half, half)
 
 ; DAGTypeLegalizer::SoftenFloatRes_FCOPYSIGN will convert to bitwise
 ; operations if half precision floating point isn't supported. A combine could

 ; RV64IZFH-LABEL: fcopysign_fneg:
 ; RV64IZFH:       # %bb.0:
 ; RV64IZFH-NEXT:    fmv.h.x fa5, a1
 ; RV64IZFH-NEXT:    fmv.h.x fa4, a0
 ; RV64IZFH-NEXT:    fsgnjn.h fa5, fa4, fa5
 ; RV64IZFH-NEXT:    fmv.x.h a0, fa5
 ; RV64IZFH-NEXT:    ret
 ;
+; RV32IZHINX-LABEL: fcopysign_fneg:
+; RV32IZHINX:       # %bb.0:
+; RV32IZHINX-NEXT:    fsgnjn.h a0, a0, a1
+; RV32IZHINX-NEXT:    ret
+;
+; RV64IZHINX-LABEL: fcopysign_fneg:
+; RV64IZHINX:       # %bb.0:
+; RV64IZHINX-NEXT:    fsgnjn.h a0, a0, a1
+; RV64IZHINX-NEXT:    ret
+;
 ; RV32IZFHMIN-LABEL: fcopysign_fneg:
 ; RV32IZFHMIN:       # %bb.0:
 ; RV32IZFHMIN-NEXT:    addi sp, sp, -16
 ; RV32IZFHMIN-NEXT:    fmv.h.x fa5, a0
 ; RV32IZFHMIN-NEXT:    fmv.h.x fa4, a1
 ; RV32IZFHMIN-NEXT:    fcvt.s.h fa4, fa4
 ; RV32IZFHMIN-NEXT:    fneg.s fa4, fa4
 ; RV32IZFHMIN-NEXT:    fcvt.h.s fa4, fa4

 ; RV64IZFHMIN-NEXT:    andi a0, a0, 127
 ; RV64IZFHMIN-NEXT:    andi a1, a1, 128
 ; RV64IZFHMIN-NEXT:    or a0, a0, a1
 ; RV64IZFHMIN-NEXT:    sb a0, 1(sp)
 ; RV64IZFHMIN-NEXT:    flh fa5, 0(sp)
 ; RV64IZFHMIN-NEXT:    fmv.x.h a0, fa5
 ; RV64IZFHMIN-NEXT:    addi sp, sp, 16
 ; RV64IZFHMIN-NEXT:    ret
+;
+; RV32IZHINXMIN-LABEL: fcopysign_fneg:
+; RV32IZHINXMIN:       # %bb.0:
+; RV32IZHINXMIN-NEXT:    addi sp, sp, -16
+; RV32IZHINXMIN-NEXT:    fcvt.s.h a1, a1
+; RV32IZHINXMIN-NEXT:    fneg.s a1, a1
+; RV32IZHINXMIN-NEXT:    fcvt.h.s a1, a1
+; RV32IZHINXMIN-NEXT:    addi a2, sp, 8
+; RV32IZHINXMIN-NEXT:    sh a0, 0(a2)
+; RV32IZHINXMIN-NEXT:    addi a0, sp, 12
+; RV32IZHINXMIN-NEXT:    sh a1, 0(a0)
+; RV32IZHINXMIN-NEXT:    lbu a0, 9(sp)
+; RV32IZHINXMIN-NEXT:    lbu a1, 13(sp)
+; RV32IZHINXMIN-NEXT:    andi a0, a0, 127
+; RV32IZHINXMIN-NEXT:    andi a1, a1, 128
+; RV32IZHINXMIN-NEXT:    or a0, a0, a1
+; RV32IZHINXMIN-NEXT:    sb a0, 9(sp)
+; RV32IZHINXMIN-NEXT:    lh a0, 0(a2)
+; RV32IZHINXMIN-NEXT:    addi sp, sp, 16
+; RV32IZHINXMIN-NEXT:    ret
+;
+; RV64IZHINXMIN-LABEL: fcopysign_fneg:
+; RV64IZHINXMIN:       # %bb.0:
+; RV64IZHINXMIN-NEXT:    addi sp, sp, -16
+; RV64IZHINXMIN-NEXT:    fcvt.s.h a1, a1
+; RV64IZHINXMIN-NEXT:    fneg.s a1, a1
+; RV64IZHINXMIN-NEXT:    fcvt.h.s a1, a1
+; RV64IZHINXMIN-NEXT:    mv a2, sp
+; RV64IZHINXMIN-NEXT:    sh a0, 0(a2)
+; RV64IZHINXMIN-NEXT:    addi a0, sp, 8
+; RV64IZHINXMIN-NEXT:    sh a1, 0(a0)
+; RV64IZHINXMIN-NEXT:    lbu a0, 1(sp)
+; RV64IZHINXMIN-NEXT:    lbu a1, 9(sp)
+; RV64IZHINXMIN-NEXT:    andi a0, a0, 127
+; RV64IZHINXMIN-NEXT:    andi a1, a1, 128
+; RV64IZHINXMIN-NEXT:    or a0, a0, a1
+; RV64IZHINXMIN-NEXT:    sb a0, 1(sp)
+; RV64IZHINXMIN-NEXT:    lh a0, 0(a2)
+; RV64IZHINXMIN-NEXT:    addi sp, sp, 16
+; RV64IZHINXMIN-NEXT:    ret
   %1 = fneg half %b
   %2 = call half @llvm.copysign.f16(half %a, half %1)
   ret half %2
 }

llvm/test/CodeGen/RISCV/half-br-fcmp.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -mattr=+zfh -verify-machineinstrs \
 ; RUN:   -target-abi ilp32f < %s | FileCheck -check-prefix=RV32IZFH %s
 ; RUN: llc -mtriple=riscv64 -mattr=+zfh -verify-machineinstrs \
 ; RUN:   -target-abi lp64f < %s | FileCheck -check-prefix=RV64IZFH %s
+; RUN: llc -mtriple=riscv32 -mattr=+zhinx -verify-machineinstrs \
+; RUN:   -target-abi ilp32 < %s | FileCheck -check-prefix=RV32IZHINX %s
+; RUN: llc -mtriple=riscv64 -mattr=+zhinx -verify-machineinstrs \
+; RUN:   -target-abi lp64 < %s | FileCheck -check-prefix=RV64IZHINX %s
 ; RUN: llc -mtriple=riscv32 -mattr=+zfhmin -verify-machineinstrs \
 ; RUN:   -target-abi ilp32f < %s | FileCheck -check-prefix=RV32IZFHMIN %s
 ; RUN: llc -mtriple=riscv64 -mattr=+zfhmin -verify-machineinstrs \
 ; RUN:   -target-abi lp64f < %s | FileCheck -check-prefix=RV64IZFHMIN %s
+; RUN: llc -mtriple=riscv32 -mattr=+zhinxmin -verify-machineinstrs \
+; RUN:   -target-abi ilp32 < %s | FileCheck -check-prefix=RV32IZHINXMIN %s
+; RUN: llc -mtriple=riscv64 -mattr=+zhinxmin -verify-machineinstrs \
+; RUN:   -target-abi lp64 < %s | FileCheck -check-prefix=RV64IZHINXMIN %s
 
 declare void @abort()
 declare void @exit(i32)
 declare half @dummy(half)
 
 define void @br_fcmp_false(half %a, half %b) nounwind {
 ; RV32IZFH-LABEL: br_fcmp_false:
 ; RV32IZFH:       # %bb.0:

 ; RV64IZFH-NEXT:    bnez a0, .LBB0_2
 ; RV64IZFH-NEXT:  # %bb.1: # %if.then
 ; RV64IZFH-NEXT:    ret
 ; RV64IZFH-NEXT:  .LBB0_2: # %if.else
 ; RV64IZFH-NEXT:    addi sp, sp, -16
 ; RV64IZFH-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64IZFH-NEXT:    call abort@plt
 ;
+; RV32IZHINX-LABEL: br_fcmp_false:
+; RV32IZHINX:       # %bb.0:
+; RV32IZHINX-NEXT:    li a0, 1
+; RV32IZHINX-NEXT:    bnez a0, .LBB0_2
+; RV32IZHINX-NEXT:  # %bb.1: # %if.then
+; RV32IZHINX-NEXT:    ret
+; RV32IZHINX-NEXT:  .LBB0_2: # %if.else
+; RV32IZHINX-NEXT:    addi sp, sp, -16
+; RV32IZHINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZHINX-NEXT:    call abort@plt
+;
+; RV64IZHINX-LABEL: br_fcmp_false:
+; RV64IZHINX:       # %bb.0:
+; RV64IZHINX-NEXT:    li a0, 1
+; RV64IZHINX-NEXT:    bnez a0, .LBB0_2
+; RV64IZHINX-NEXT:  # %bb.1: # %if.then
+; RV64IZHINX-NEXT:    ret
+; RV64IZHINX-NEXT:  .LBB0_2: # %if.else
+; RV64IZHINX-NEXT:    addi sp, sp, -16
+; RV64IZHINX-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IZHINX-NEXT:    call abort@plt
+;
 ; RV32IZFHMIN-LABEL: br_fcmp_false:
 ; RV32IZFHMIN:       # %bb.0:
 ; RV32IZFHMIN-NEXT:    li a0, 1
 ; RV32IZFHMIN-NEXT:    bnez a0, .LBB0_2
 ; RV32IZFHMIN-NEXT:  # %bb.1: # %if.then
 ; RV32IZFHMIN-NEXT:    ret
 ; RV32IZFHMIN-NEXT:  .LBB0_2: # %if.else
 ; RV32IZFHMIN-NEXT:    addi sp, sp, -16
 ; RV32IZFHMIN-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32IZFHMIN-NEXT:    call abort@plt
 ;
 ; RV64IZFHMIN-LABEL: br_fcmp_false:
 ; RV64IZFHMIN:       # %bb.0:
 ; RV64IZFHMIN-NEXT:    li a0, 1
 ; RV64IZFHMIN-NEXT:    bnez a0, .LBB0_2
 ; RV64IZFHMIN-NEXT:  # %bb.1: # %if.then
 ; RV64IZFHMIN-NEXT:    ret
 ; RV64IZFHMIN-NEXT:  .LBB0_2: # %if.else
 ; RV64IZFHMIN-NEXT:    addi sp, sp, -16
 ; RV64IZFHMIN-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64IZFHMIN-NEXT:    call abort@plt
+;
+; RV32IZHINXMIN-LABEL: br_fcmp_false:
+; RV32IZHINXMIN:       # %bb.0:
+; RV32IZHINXMIN-NEXT:    li a0, 1
+; RV32IZHINXMIN-NEXT:    bnez a0, .LBB0_2
+; RV32IZHINXMIN-NEXT:  # %bb.1: # %if.then
+; RV32IZHINXMIN-NEXT:    ret
+; RV32IZHINXMIN-NEXT:  .LBB0_2: # %if.else
+; RV32IZHINXMIN-NEXT:    addi sp, sp, -16
+; RV32IZHINXMIN-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZHINXMIN-NEXT:    call abort@plt
+;
+; RV64IZHINXMIN-LABEL: br_fcmp_false:
+; RV64IZHINXMIN:       # %bb.0:
+; RV64IZHINXMIN-NEXT:    li a0, 1
+; RV64IZHINXMIN-NEXT:    bnez a0, .LBB0_2
+; RV64IZHINXMIN-NEXT:  # %bb.1: # %if.then
+; RV64IZHINXMIN-NEXT:    ret
+; RV64IZHINXMIN-NEXT:  .LBB0_2: # %if.else
+; RV64IZHINXMIN-NEXT:    addi sp, sp, -16
+; RV64IZHINXMIN-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IZHINXMIN-NEXT:    call abort@plt
   %1 = fcmp false half %a, %b
   br i1 %1, label %if.then, label %if.else
 if.then:
   ret void
 if.else:
   tail call void @abort()
   unreachable
 }

 ; RV64IZFH-NEXT:    bnez a0, .LBB1_2
 ; RV64IZFH-NEXT:  # %bb.1: # %if.else
 ; RV64IZFH-NEXT:    ret
 ; RV64IZFH-NEXT:  .LBB1_2: # %if.then
 ; RV64IZFH-NEXT:    addi sp, sp, -16
 ; RV64IZFH-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64IZFH-NEXT:    call abort@plt
 ;
+; RV32IZHINX-LABEL: br_fcmp_oeq:
+; RV32IZHINX:       # %bb.0:
+; RV32IZHINX-NEXT:    feq.h a0, a0, a1
+; RV32IZHINX-NEXT:    bnez a0, .LBB1_2
+; RV32IZHINX-NEXT:  # %bb.1: # %if.else
+; RV32IZHINX-NEXT:    ret
+; RV32IZHINX-NEXT:  .LBB1_2: # %if.then
+; RV32IZHINX-NEXT:    addi sp, sp, -16
+; RV32IZHINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZHINX-NEXT:    call abort@plt
+;
+; RV64IZHINX-LABEL: br_fcmp_oeq:
+; RV64IZHINX:       # %bb.0:
+; RV64IZHINX-NEXT:    feq.h a0, a0, a1
+; RV64IZHINX-NEXT:    bnez a0, .LBB1_2
+; RV64IZHINX-NEXT:  # %bb.1: # %if.else
+; RV64IZHINX-NEXT:    ret
+; RV64IZHINX-NEXT:  .LBB1_2: # %if.then
+; RV64IZHINX-NEXT:    addi sp, sp, -16
+; RV64IZHINX-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IZHINX-NEXT:    call abort@plt
+;
 ; RV32IZFHMIN-LABEL: br_fcmp_oeq:
 ; RV32IZFHMIN:       # %bb.0:
 ; RV32IZFHMIN-NEXT:    fcvt.s.h fa5, fa1
 ; RV32IZFHMIN-NEXT:    fcvt.s.h fa4, fa0
 ; RV32IZFHMIN-NEXT:    feq.s a0, fa4, fa5
 ; RV32IZFHMIN-NEXT:    bnez a0, .LBB1_2
 ; RV32IZFHMIN-NEXT:  # %bb.1: # %if.else
 ; RV32IZFHMIN-NEXT:    ret

 ; RV64IZFHMIN-NEXT:    feq.s a0, fa4, fa5
 ; RV64IZFHMIN-NEXT:    bnez a0, .LBB1_2
 ; RV64IZFHMIN-NEXT:  # %bb.1: # %if.else
 ; RV64IZFHMIN-NEXT:    ret
 ; RV64IZFHMIN-NEXT:  .LBB1_2: # %if.then
 ; RV64IZFHMIN-NEXT:    addi sp, sp, -16
 ; RV64IZFHMIN-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64IZFHMIN-NEXT:    call abort@plt
+;
+; RV32IZHINXMIN-LABEL: br_fcmp_oeq:
+; RV32IZHINXMIN:       # %bb.0:
+; RV32IZHINXMIN-NEXT:    fcvt.s.h a1, a1
+; RV32IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV32IZHINXMIN-NEXT:    feq.s a0, a0, a1
+; RV32IZHINXMIN-NEXT:    bnez a0, .LBB1_2
+; RV32IZHINXMIN-NEXT:  # %bb.1: # %if.else
+; RV32IZHINXMIN-NEXT:    ret
+; RV32IZHINXMIN-NEXT:  .LBB1_2: # %if.then
+; RV32IZHINXMIN-NEXT:    addi sp, sp, -16
+; RV32IZHINXMIN-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZHINXMIN-NEXT:    call abort@plt
+;
+; RV64IZHINXMIN-LABEL: br_fcmp_oeq:
+; RV64IZHINXMIN:       # %bb.0:
+; RV64IZHINXMIN-NEXT:    fcvt.s.h a1, a1
+; RV64IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV64IZHINXMIN-NEXT:    feq.s a0, a0, a1
+; RV64IZHINXMIN-NEXT:    bnez a0, .LBB1_2
+; RV64IZHINXMIN-NEXT:  # %bb.1: # %if.else
+; RV64IZHINXMIN-NEXT:    ret
+; RV64IZHINXMIN-NEXT:  .LBB1_2: # %if.then
+; RV64IZHINXMIN-NEXT:    addi sp, sp, -16
+; RV64IZHINXMIN-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IZHINXMIN-NEXT:    call abort@plt
   %1 = fcmp oeq half %a, %b
   br i1 %1, label %if.then, label %if.else
 if.else:
   ret void
 if.then:
   tail call void @abort()
   unreachable
 }

 ; RV64IZFH-NEXT:    bnez a0, .LBB2_2
 ; RV64IZFH-NEXT:  # %bb.1: # %if.else
 ; RV64IZFH-NEXT:    ret
 ; RV64IZFH-NEXT:  .LBB2_2: # %if.then
 ; RV64IZFH-NEXT:    addi sp, sp, -16
 ; RV64IZFH-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64IZFH-NEXT:    call abort@plt
 ;
+; RV32IZHINX-LABEL: br_fcmp_oeq_alt:
+; RV32IZHINX:       # %bb.0:
+; RV32IZHINX-NEXT:    feq.h a0, a0, a1
+; RV32IZHINX-NEXT:    bnez a0, .LBB2_2
+; RV32IZHINX-NEXT:  # %bb.1: # %if.else
+; RV32IZHINX-NEXT:    ret
+; RV32IZHINX-NEXT:  .LBB2_2: # %if.then
+; RV32IZHINX-NEXT:    addi sp, sp, -16
+; RV32IZHINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZHINX-NEXT:    call abort@plt
+;
+; RV64IZHINX-LABEL: br_fcmp_oeq_alt:
+; RV64IZHINX:       # %bb.0:
+; RV64IZHINX-NEXT:    feq.h a0, a0, a1
+; RV64IZHINX-NEXT:    bnez a0, .LBB2_2
+; RV64IZHINX-NEXT:  # %bb.1: # %if.else
+; RV64IZHINX-NEXT:    ret
+; RV64IZHINX-NEXT:  .LBB2_2: # %if.then
+; RV64IZHINX-NEXT:    addi sp, sp, -16
+; RV64IZHINX-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IZHINX-NEXT:    call abort@plt
+;
 ; RV32IZFHMIN-LABEL: br_fcmp_oeq_alt:
 ; RV32IZFHMIN:       # %bb.0:
 ; RV32IZFHMIN-NEXT:    fcvt.s.h fa5, fa1
 ; RV32IZFHMIN-NEXT:    fcvt.s.h fa4, fa0
 ; RV32IZFHMIN-NEXT:    feq.s a0, fa4, fa5
 ; RV32IZFHMIN-NEXT:    bnez a0, .LBB2_2
 ; RV32IZFHMIN-NEXT:  # %bb.1: # %if.else
 ; RV32IZFHMIN-NEXT:    ret

 ; RV64IZFHMIN-NEXT:    feq.s a0, fa4, fa5
 ; RV64IZFHMIN-NEXT:    bnez a0, .LBB2_2
 ; RV64IZFHMIN-NEXT:  # %bb.1: # %if.else
 ; RV64IZFHMIN-NEXT:    ret
 ; RV64IZFHMIN-NEXT:  .LBB2_2: # %if.then
 ; RV64IZFHMIN-NEXT:    addi sp, sp, -16
 ; RV64IZFHMIN-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64IZFHMIN-NEXT:    call abort@plt
+;
+; RV32IZHINXMIN-LABEL: br_fcmp_oeq_alt:
+; RV32IZHINXMIN:       # %bb.0:
+; RV32IZHINXMIN-NEXT:    fcvt.s.h a1, a1
+; RV32IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV32IZHINXMIN-NEXT:    feq.s a0, a0, a1
+; RV32IZHINXMIN-NEXT:    bnez a0, .LBB2_2
+; RV32IZHINXMIN-NEXT:  # %bb.1: # %if.else
+; RV32IZHINXMIN-NEXT:    ret
+; RV32IZHINXMIN-NEXT:  .LBB2_2: # %if.then
+; RV32IZHINXMIN-NEXT:    addi sp, sp, -16
+; RV32IZHINXMIN-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZHINXMIN-NEXT:    call abort@plt
+;
+; RV64IZHINXMIN-LABEL: br_fcmp_oeq_alt:
+; RV64IZHINXMIN:       # %bb.0:
+; RV64IZHINXMIN-NEXT:    fcvt.s.h a1, a1
+; RV64IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV64IZHINXMIN-NEXT:    feq.s a0, a0, a1
+; RV64IZHINXMIN-NEXT:    bnez a0, .LBB2_2
+; RV64IZHINXMIN-NEXT:  # %bb.1: # %if.else
+; RV64IZHINXMIN-NEXT:    ret
+; RV64IZHINXMIN-NEXT:  .LBB2_2: # %if.then
+; RV64IZHINXMIN-NEXT:    addi sp, sp, -16
+; RV64IZHINXMIN-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IZHINXMIN-NEXT:    call abort@plt
   %1 = fcmp oeq half %a, %b
   br i1 %1, label %if.then, label %if.else
 if.then:
   tail call void @abort()
   unreachable
 if.else:
   ret void
 }

 ; RV64IZFH-NEXT:    bnez a0, .LBB3_2
 ; RV64IZFH-NEXT:  # %bb.1: # %if.else
 ; RV64IZFH-NEXT:    ret
 ; RV64IZFH-NEXT:  .LBB3_2: # %if.then
 ; RV64IZFH-NEXT:    addi sp, sp, -16
 ; RV64IZFH-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64IZFH-NEXT:    call abort@plt
 ;
+; RV32IZHINX-LABEL: br_fcmp_ogt:
+; RV32IZHINX:       # %bb.0:
+; RV32IZHINX-NEXT:    flt.h a0, a1, a0
+; RV32IZHINX-NEXT:    bnez a0, .LBB3_2
+; RV32IZHINX-NEXT:  # %bb.1: # %if.else
+; RV32IZHINX-NEXT:    ret
+; RV32IZHINX-NEXT:  .LBB3_2: # %if.then
+; RV32IZHINX-NEXT:    addi sp, sp, -16
+; RV32IZHINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZHINX-NEXT:    call abort@plt
+;
+; RV64IZHINX-LABEL: br_fcmp_ogt:
+; RV64IZHINX:       # %bb.0:
+; RV64IZHINX-NEXT:    flt.h a0, a1, a0
+; RV64IZHINX-NEXT:    bnez a0, .LBB3_2
+; RV64IZHINX-NEXT:  # %bb.1: # %if.else
+; RV64IZHINX-NEXT:    ret
+; RV64IZHINX-NEXT:  .LBB3_2: # %if.then
+; RV64IZHINX-NEXT:    addi sp, sp, -16
+; RV64IZHINX-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IZHINX-NEXT:    call abort@plt
+;
 ; RV32IZFHMIN-LABEL: br_fcmp_ogt:
 ; RV32IZFHMIN:       # %bb.0:
 ; RV32IZFHMIN-NEXT:    fcvt.s.h fa5, fa0
 ; RV32IZFHMIN-NEXT:    fcvt.s.h fa4, fa1
 ; RV32IZFHMIN-NEXT:    flt.s a0, fa4, fa5
 ; RV32IZFHMIN-NEXT:    bnez a0, .LBB3_2
 ; RV32IZFHMIN-NEXT:  # %bb.1: # %if.else
 ; RV32IZFHMIN-NEXT:    ret

 ; RV64IZFHMIN-NEXT:    flt.s a0, fa4, fa5
 ; RV64IZFHMIN-NEXT:    bnez a0, .LBB3_2
 ; RV64IZFHMIN-NEXT:  # %bb.1: # %if.else
 ; RV64IZFHMIN-NEXT:    ret
 ; RV64IZFHMIN-NEXT:  .LBB3_2: # %if.then
 ; RV64IZFHMIN-NEXT:    addi sp, sp, -16
 ; RV64IZFHMIN-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64IZFHMIN-NEXT:    call abort@plt
+;
+; RV32IZHINXMIN-LABEL: br_fcmp_ogt:
+; RV32IZHINXMIN:       # %bb.0:
+; RV32IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV32IZHINXMIN-NEXT:    fcvt.s.h a1, a1
+; RV32IZHINXMIN-NEXT:    flt.s a0, a1, a0
+; RV32IZHINXMIN-NEXT:    bnez a0, .LBB3_2
+; RV32IZHINXMIN-NEXT:  # %bb.1: # %if.else
+; RV32IZHINXMIN-NEXT:    ret
+; RV32IZHINXMIN-NEXT:  .LBB3_2: # %if.then
+; RV32IZHINXMIN-NEXT:    addi sp, sp, -16
+; RV32IZHINXMIN-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZHINXMIN-NEXT:    call abort@plt
+;
+; RV64IZHINXMIN-LABEL: br_fcmp_ogt:
+; RV64IZHINXMIN:       # %bb.0:
+; RV64IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV64IZHINXMIN-NEXT:    fcvt.s.h a1, a1
+; RV64IZHINXMIN-NEXT:    flt.s a0, a1, a0
+; RV64IZHINXMIN-NEXT:    bnez a0, .LBB3_2
+; RV64IZHINXMIN-NEXT:  # %bb.1: # %if.else
+; RV64IZHINXMIN-NEXT:    ret
+; RV64IZHINXMIN-NEXT:  .LBB3_2: # %if.then
+; RV64IZHINXMIN-NEXT:    addi sp, sp, -16
+; RV64IZHINXMIN-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IZHINXMIN-NEXT:    call abort@plt
   %1 = fcmp ogt half %a, %b
   br i1 %1, label %if.then, label %if.else
 if.else:
   ret void
 if.then:
   tail call void @abort()
   unreachable
 }

 ; RV64IZFH-NEXT:    bnez a0, .LBB4_2
 ; RV64IZFH-NEXT:  # %bb.1: # %if.else
 ; RV64IZFH-NEXT:    ret
 ; RV64IZFH-NEXT:  .LBB4_2: # %if.then
 ; RV64IZFH-NEXT:    addi sp, sp, -16
 ; RV64IZFH-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64IZFH-NEXT:    call abort@plt
 ;
+; RV32IZHINX-LABEL: br_fcmp_oge:
+; RV32IZHINX:       # %bb.0:
+; RV32IZHINX-NEXT:    fle.h a0, a1, a0
+; RV32IZHINX-NEXT:    bnez a0, .LBB4_2
+; RV32IZHINX-NEXT:  # %bb.1: # %if.else
+; RV32IZHINX-NEXT:    ret
+; RV32IZHINX-NEXT:  .LBB4_2: # %if.then
+; RV32IZHINX-NEXT:    addi sp, sp, -16
+; RV32IZHINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZHINX-NEXT:    call abort@plt
+;
+; RV64IZHINX-LABEL: br_fcmp_oge:
+; RV64IZHINX:       # %bb.0:
+; RV64IZHINX-NEXT:    fle.h a0, a1, a0
+; RV64IZHINX-NEXT:    bnez a0, .LBB4_2
+; RV64IZHINX-NEXT:  # %bb.1: # %if.else
+; RV64IZHINX-NEXT:    ret
+; RV64IZHINX-NEXT:  .LBB4_2: # %if.then
+; RV64IZHINX-NEXT:    addi sp, sp, -16
+; RV64IZHINX-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IZHINX-NEXT:    call abort@plt
+;
 ; RV32IZFHMIN-LABEL: br_fcmp_oge:
 ; RV32IZFHMIN:       # %bb.0:
 ; RV32IZFHMIN-NEXT:    fcvt.s.h fa5, fa0
 ; RV32IZFHMIN-NEXT:    fcvt.s.h fa4, fa1
 ; RV32IZFHMIN-NEXT:    fle.s a0, fa4, fa5
 ; RV32IZFHMIN-NEXT:    bnez a0, .LBB4_2
 ; RV32IZFHMIN-NEXT:  # %bb.1: # %if.else
 ; RV32IZFHMIN-NEXT:    ret

 ; RV64IZFHMIN-NEXT:    fle.s a0, fa4, fa5
 ; RV64IZFHMIN-NEXT:    bnez a0, .LBB4_2
 ; RV64IZFHMIN-NEXT:  # %bb.1: # %if.else
 ; RV64IZFHMIN-NEXT:    ret
 ; RV64IZFHMIN-NEXT:  .LBB4_2: # %if.then
 ; RV64IZFHMIN-NEXT:    addi sp, sp, -16
 ; RV64IZFHMIN-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64IZFHMIN-NEXT:    call abort@plt
+;
+; RV32IZHINXMIN-LABEL: br_fcmp_oge:
+; RV32IZHINXMIN:       # %bb.0:
+; RV32IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV32IZHINXMIN-NEXT:    fcvt.s.h a1, a1
+; RV32IZHINXMIN-NEXT:    fle.s a0, a1, a0
+; RV32IZHINXMIN-NEXT:    bnez a0, .LBB4_2
+; RV32IZHINXMIN-NEXT:  # %bb.1: # %if.else
+; RV32IZHINXMIN-NEXT:    ret
+; RV32IZHINXMIN-NEXT:  .LBB4_2: # %if.then
+; RV32IZHINXMIN-NEXT:    addi sp, sp, -16
+; RV32IZHINXMIN-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZHINXMIN-NEXT:    call abort@plt
+;
+; RV64IZHINXMIN-LABEL: br_fcmp_oge:
+; RV64IZHINXMIN:       # %bb.0:
+; RV64IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV64IZHINXMIN-NEXT:    fcvt.s.h a1, a1
+; RV64IZHINXMIN-NEXT:    fle.s a0, a1, a0
+; RV64IZHINXMIN-NEXT:    bnez a0, .LBB4_2
+; RV64IZHINXMIN-NEXT:  # %bb.1: # %if.else
+; RV64IZHINXMIN-NEXT:    ret
+; RV64IZHINXMIN-NEXT:  .LBB4_2: # %if.then
+; RV64IZHINXMIN-NEXT:    addi sp, sp, -16
+; RV64IZHINXMIN-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IZHINXMIN-NEXT:    call abort@plt
   %1 = fcmp oge half %a, %b
   br i1 %1, label %if.then, label %if.else
 if.else:
   ret void
 if.then:
   tail call void @abort()
   unreachable
 }

 ; RV64IZFH-NEXT:    bnez a0, .LBB5_2
 ; RV64IZFH-NEXT:  # %bb.1: # %if.else
 ; RV64IZFH-NEXT:    ret
 ; RV64IZFH-NEXT:  .LBB5_2: # %if.then
 ; RV64IZFH-NEXT:    addi sp, sp, -16
 ; RV64IZFH-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64IZFH-NEXT:    call abort@plt
 ;
+; RV32IZHINX-LABEL: br_fcmp_olt:
+; RV32IZHINX:       # %bb.0:
+; RV32IZHINX-NEXT:    flt.h a0, a0, a1
+; RV32IZHINX-NEXT:    bnez a0, .LBB5_2
+; RV32IZHINX-NEXT:  # %bb.1: # %if.else
+; RV32IZHINX-NEXT:    ret
+; RV32IZHINX-NEXT:  .LBB5_2: # %if.then
+; RV32IZHINX-NEXT:    addi sp, sp, -16
+; RV32IZHINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZHINX-NEXT:    call abort@plt
+;
+; RV64IZHINX-LABEL: br_fcmp_olt:
+; RV64IZHINX:       # %bb.0:
+; RV64IZHINX-NEXT:    flt.h a0, a0, a1
+; RV64IZHINX-NEXT:    bnez a0, .LBB5_2
+; RV64IZHINX-NEXT:  # %bb.1: # %if.else
+; RV64IZHINX-NEXT:    ret
+; RV64IZHINX-NEXT:  .LBB5_2: # %if.then
+; RV64IZHINX-NEXT:    addi sp, sp, -16
+; RV64IZHINX-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IZHINX-NEXT:    call abort@plt
+;
 ; RV32IZFHMIN-LABEL: br_fcmp_olt:
 ; RV32IZFHMIN:       # %bb.0:
 ; RV32IZFHMIN-NEXT:    fcvt.s.h fa5, fa1
 ; RV32IZFHMIN-NEXT:    fcvt.s.h fa4, fa0
 ; RV32IZFHMIN-NEXT:    flt.s a0, fa4, fa5
 ; RV32IZFHMIN-NEXT:    bnez a0, .LBB5_2
 ; RV32IZFHMIN-NEXT:  # %bb.1: # %if.else
 ; RV32IZFHMIN-NEXT:    ret

 ; RV64IZFHMIN-NEXT:    flt.s a0, fa4, fa5
 ; RV64IZFHMIN-NEXT:    bnez a0, .LBB5_2
 ; RV64IZFHMIN-NEXT:  # %bb.1: # %if.else
 ; RV64IZFHMIN-NEXT:    ret
 ; RV64IZFHMIN-NEXT:  .LBB5_2: # %if.then
 ; RV64IZFHMIN-NEXT:    addi sp, sp, -16
 ; RV64IZFHMIN-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64IZFHMIN-NEXT:    call abort@plt
+;
+; RV32IZHINXMIN-LABEL: br_fcmp_olt:
+; RV32IZHINXMIN:       # %bb.0:
+; RV32IZHINXMIN-NEXT:    fcvt.s.h a1, a1
+; RV32IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV32IZHINXMIN-NEXT:    flt.s a0, a0, a1
+; RV32IZHINXMIN-NEXT:    bnez a0, .LBB5_2
+; RV32IZHINXMIN-NEXT:  # %bb.1: # %if.else
+; RV32IZHINXMIN-NEXT:    ret
+; RV32IZHINXMIN-NEXT:  .LBB5_2: # %if.then
+; RV32IZHINXMIN-NEXT:    addi sp, sp, -16
+; RV32IZHINXMIN-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZHINXMIN-NEXT:    call abort@plt
+;
+; RV64IZHINXMIN-LABEL: br_fcmp_olt:
+; RV64IZHINXMIN:       # %bb.0:
+; RV64IZHINXMIN-NEXT:    fcvt.s.h a1, a1
+; RV64IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV64IZHINXMIN-NEXT:    flt.s a0, a0, a1
+; RV64IZHINXMIN-NEXT:    bnez a0, .LBB5_2
+; RV64IZHINXMIN-NEXT:  # %bb.1: # %if.else
+; RV64IZHINXMIN-NEXT:    ret
+; RV64IZHINXMIN-NEXT:  .LBB5_2: # %if.then
+; RV64IZHINXMIN-NEXT:    addi sp, sp, -16
+; RV64IZHINXMIN-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IZHINXMIN-NEXT:    call abort@plt
   %1 = fcmp olt half %a, %b
   br i1 %1, label %if.then, label %if.else
 if.else:
   ret void
 if.then:
   tail call void @abort()
   unreachable
 }

 ; RV64IZFH-NEXT:    bnez a0, .LBB6_2
 ; RV64IZFH-NEXT:  # %bb.1: # %if.else
 ; RV64IZFH-NEXT:    ret
 ; RV64IZFH-NEXT:  .LBB6_2: # %if.then
 ; RV64IZFH-NEXT:    addi sp, sp, -16
 ; RV64IZFH-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64IZFH-NEXT:    call abort@plt
 ;
+; RV32IZHINX-LABEL: br_fcmp_ole:
+; RV32IZHINX:       # %bb.0:
+; RV32IZHINX-NEXT:    fle.h a0, a0, a1
+; RV32IZHINX-NEXT:    bnez a0, .LBB6_2
+; RV32IZHINX-NEXT:  # %bb.1: # %if.else
+; RV32IZHINX-NEXT:    ret
+; RV32IZHINX-NEXT:  .LBB6_2: # %if.then
+; RV32IZHINX-NEXT:    addi sp, sp, -16
+; RV32IZHINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZHINX-NEXT:    call abort@plt
+;
+; RV64IZHINX-LABEL: br_fcmp_ole:
+; RV64IZHINX:       # %bb.0:
+; RV64IZHINX-NEXT:    fle.h a0, a0, a1
+; RV64IZHINX-NEXT:    bnez a0, .LBB6_2
+; RV64IZHINX-NEXT:  # %bb.1: # %if.else
+; RV64IZHINX-NEXT:    ret
+; RV64IZHINX-NEXT:  .LBB6_2: # %if.then
+; RV64IZHINX-NEXT:    addi sp, sp, -16
+; RV64IZHINX-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IZHINX-NEXT:    call abort@plt
+;
 ; RV32IZFHMIN-LABEL: br_fcmp_ole:
 ; RV32IZFHMIN:       # %bb.0:
 ; RV32IZFHMIN-NEXT:    fcvt.s.h fa5, fa1
 ; RV32IZFHMIN-NEXT:    fcvt.s.h fa4, fa0
 ; RV32IZFHMIN-NEXT:    fle.s a0, fa4, fa5
 ; RV32IZFHMIN-NEXT:    bnez a0, .LBB6_2
 ; RV32IZFHMIN-NEXT:  # %bb.1: # %if.else
 ; RV32IZFHMIN-NEXT:    ret

 ; RV64IZFHMIN-NEXT:    fle.s a0, fa4, fa5
 ; RV64IZFHMIN-NEXT:    bnez a0, .LBB6_2
 ; RV64IZFHMIN-NEXT:  # %bb.1: # %if.else
 ; RV64IZFHMIN-NEXT:    ret
 ; RV64IZFHMIN-NEXT:  .LBB6_2: # %if.then
 ; RV64IZFHMIN-NEXT:    addi sp, sp, -16
 ; RV64IZFHMIN-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64IZFHMIN-NEXT:    call abort@plt
+;
+; RV32IZHINXMIN-LABEL: br_fcmp_ole:
+; RV32IZHINXMIN:       # %bb.0:
+; RV32IZHINXMIN-NEXT:    fcvt.s.h a1, a1
+; RV32IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV32IZHINXMIN-NEXT:    fle.s a0, a0, a1
+; RV32IZHINXMIN-NEXT:    bnez a0, .LBB6_2
+; RV32IZHINXMIN-NEXT:  # %bb.1: # %if.else
+; RV32IZHINXMIN-NEXT:    ret
+; RV32IZHINXMIN-NEXT:  .LBB6_2: # %if.then
+; RV32IZHINXMIN-NEXT:    addi sp, sp, -16
+; RV32IZHINXMIN-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZHINXMIN-NEXT:    call abort@plt
+;
+; RV64IZHINXMIN-LABEL: br_fcmp_ole:
+; RV64IZHINXMIN:       # %bb.0:
+; RV64IZHINXMIN-NEXT:    fcvt.s.h a1, a1
+; RV64IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV64IZHINXMIN-NEXT:    fle.s a0, a0, a1
+; RV64IZHINXMIN-NEXT:    bnez a0, .LBB6_2
+; RV64IZHINXMIN-NEXT:  # %bb.1: # %if.else
+; RV64IZHINXMIN-NEXT:    ret
+; RV64IZHINXMIN-NEXT:  .LBB6_2: # %if.then
+; RV64IZHINXMIN-NEXT:    addi sp, sp, -16
+; RV64IZHINXMIN-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IZHINXMIN-NEXT:    call abort@plt
   %1 = fcmp ole half %a, %b
   br i1 %1, label %if.then, label %if.else
 if.else:
   ret void
 if.then:
   tail call void @abort()
   unreachable
 }

 ; RV64IZFH-NEXT:    bnez a0, .LBB7_2
 ; RV64IZFH-NEXT:  # %bb.1: # %if.else
 ; RV64IZFH-NEXT:    ret
 ; RV64IZFH-NEXT:  .LBB7_2: # %if.then
 ; RV64IZFH-NEXT:    addi sp, sp, -16
 ; RV64IZFH-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64IZFH-NEXT:    call abort@plt
 ;
+; RV32IZHINX-LABEL: br_fcmp_one:
+; RV32IZHINX:       # %bb.0:
+; RV32IZHINX-NEXT:    flt.h a2, a0, a1
+; RV32IZHINX-NEXT:    flt.h a0, a1, a0
+; RV32IZHINX-NEXT:    or a0, a0, a2
+; RV32IZHINX-NEXT:    bnez a0, .LBB7_2
+; RV32IZHINX-NEXT:  # %bb.1: # %if.else
+; RV32IZHINX-NEXT:    ret
+; RV32IZHINX-NEXT:  .LBB7_2: # %if.then
+; RV32IZHINX-NEXT:    addi sp, sp, -16
+; RV32IZHINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZHINX-NEXT:    call abort@plt
+;
+; RV64IZHINX-LABEL: br_fcmp_one:
+; RV64IZHINX:       # %bb.0:
+; RV64IZHINX-NEXT:    flt.h a2, a0, a1
+; RV64IZHINX-NEXT:    flt.h a0, a1, a0
+; RV64IZHINX-NEXT:    or a0, a0, a2
+; RV64IZHINX-NEXT:    bnez a0, .LBB7_2
+; RV64IZHINX-NEXT:  # %bb.1: # %if.else
+; RV64IZHINX-NEXT:    ret
+; RV64IZHINX-NEXT:  .LBB7_2: # %if.then
+; RV64IZHINX-NEXT:    addi sp, sp, -16
+; RV64IZHINX-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IZHINX-NEXT:    call abort@plt
+;
 ; RV32IZFHMIN-LABEL: br_fcmp_one:
 ; RV32IZFHMIN:       # %bb.0:
 ; RV32IZFHMIN-NEXT:    fcvt.s.h fa5, fa1
 ; RV32IZFHMIN-NEXT:    fcvt.s.h fa4, fa0
 ; RV32IZFHMIN-NEXT:    flt.s a0, fa4, fa5
 ; RV32IZFHMIN-NEXT:    flt.s a1, fa5, fa4
 ; RV32IZFHMIN-NEXT:    or a0, a1, a0
 ; RV32IZFHMIN-NEXT:    bnez a0, .LBB7_2

 ; RV64IZFHMIN-NEXT:    or a0, a1, a0
 ; RV64IZFHMIN-NEXT:    bnez a0, .LBB7_2
 ; RV64IZFHMIN-NEXT:  # %bb.1: # %if.else
 ; RV64IZFHMIN-NEXT:    ret
 ; RV64IZFHMIN-NEXT:  .LBB7_2: # %if.then
 ; RV64IZFHMIN-NEXT:    addi sp, sp, -16
 ; RV64IZFHMIN-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64IZFHMIN-NEXT:    call abort@plt
+;
+; RV32IZHINXMIN-LABEL: br_fcmp_one:
+; RV32IZHINXMIN:       # %bb.0:
+; RV32IZHINXMIN-NEXT:    fcvt.s.h a1, a1
+; RV32IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV32IZHINXMIN-NEXT:    flt.s a2, a0, a1
+; RV32IZHINXMIN-NEXT:    flt.s a0, a1, a0
+; RV32IZHINXMIN-NEXT:    or a0, a0, a2
+; RV32IZHINXMIN-NEXT:    bnez a0, .LBB7_2
+; RV32IZHINXMIN-NEXT:  # %bb.1: # %if.else
+; RV32IZHINXMIN-NEXT:    ret
+; RV32IZHINXMIN-NEXT:  .LBB7_2: # %if.then
+; RV32IZHINXMIN-NEXT:    addi sp, sp, -16
+; RV32IZHINXMIN-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZHINXMIN-NEXT:    call abort@plt
+;
+; RV64IZHINXMIN-LABEL: br_fcmp_one:
+; RV64IZHINXMIN:       # %bb.0:
+; RV64IZHINXMIN-NEXT:    fcvt.s.h a1, a1
+; RV64IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV64IZHINXMIN-NEXT:    flt.s a2, a0, a1
+; RV64IZHINXMIN-NEXT:    flt.s a0, a1, a0
+; RV64IZHINXMIN-NEXT:    or a0, a0, a2
+; RV64IZHINXMIN-NEXT:    bnez a0, .LBB7_2
+; RV64IZHINXMIN-NEXT:  # %bb.1: # %if.else
+; RV64IZHINXMIN-NEXT:    ret
+; RV64IZHINXMIN-NEXT:  .LBB7_2: # %if.then
+; RV64IZHINXMIN-NEXT:    addi sp, sp, -16
+; RV64IZHINXMIN-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IZHINXMIN-NEXT:    call abort@plt
   %1 = fcmp one half %a, %b
   br i1 %1, label %if.then, label %if.else
 if.else:
   ret void
 if.then:
   tail call void @abort()
   unreachable
 }

 ; RV64IZFH-NEXT:    bnez a0, .LBB8_2
 ; RV64IZFH-NEXT:  # %bb.1: # %if.else
 ; RV64IZFH-NEXT:    ret
 ; RV64IZFH-NEXT:  .LBB8_2: # %if.then
 ; RV64IZFH-NEXT:    addi sp, sp, -16
 ; RV64IZFH-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64IZFH-NEXT:    call abort@plt
 ;
+; RV32IZHINX-LABEL: br_fcmp_ord:
+; RV32IZHINX:       # %bb.0:
+; RV32IZHINX-NEXT:    feq.h a1, a1, a1
+; RV32IZHINX-NEXT:    feq.h a0, a0, a0
+; RV32IZHINX-NEXT:    and a0, a0, a1
+; RV32IZHINX-NEXT:    bnez a0, .LBB8_2
+; RV32IZHINX-NEXT:  # %bb.1: # %if.else
+; RV32IZHINX-NEXT:    ret
+; RV32IZHINX-NEXT:  .LBB8_2: # %if.then
+; RV32IZHINX-NEXT:    addi sp, sp, -16
+; RV32IZHINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZHINX-NEXT:    call abort@plt
+;
+; RV64IZHINX-LABEL: br_fcmp_ord:
+; RV64IZHINX:       # %bb.0:
+; RV64IZHINX-NEXT:    feq.h a1, a1, a1
+; RV64IZHINX-NEXT:    feq.h a0, a0, a0
+; RV64IZHINX-NEXT:    and a0, a0, a1
+; RV64IZHINX-NEXT:    bnez a0, .LBB8_2
+; RV64IZHINX-NEXT:  # %bb.1: # %if.else
+; RV64IZHINX-NEXT:    ret
+; RV64IZHINX-NEXT:  .LBB8_2: # %if.then
+; RV64IZHINX-NEXT:    addi sp, sp, -16
+; RV64IZHINX-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IZHINX-NEXT:    call abort@plt
+;
 ; RV32IZFHMIN-LABEL: br_fcmp_ord:
 ; RV32IZFHMIN:       # %bb.0:
 ; RV32IZFHMIN-NEXT:    fcvt.s.h fa5, fa1
 ; RV32IZFHMIN-NEXT:    feq.s a0, fa5, fa5
 ; RV32IZFHMIN-NEXT:    fcvt.s.h fa5, fa0
 ; RV32IZFHMIN-NEXT:    feq.s a1, fa5, fa5
 ; RV32IZFHMIN-NEXT:    and a0, a1, a0
 ; RV32IZFHMIN-NEXT:    bnez a0, .LBB8_2

 ; RV64IZFHMIN-NEXT:    and a0, a1, a0
 ; RV64IZFHMIN-NEXT:    bnez a0, .LBB8_2
 ; RV64IZFHMIN-NEXT:  # %bb.1: # %if.else
 ; RV64IZFHMIN-NEXT:    ret
 ; RV64IZFHMIN-NEXT:  .LBB8_2: # %if.then
 ; RV64IZFHMIN-NEXT:    addi sp, sp, -16
 ; RV64IZFHMIN-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64IZFHMIN-NEXT:    call abort@plt
+;
+; RV32IZHINXMIN-LABEL: br_fcmp_ord:
+; RV32IZHINXMIN:       # %bb.0:
+; RV32IZHINXMIN-NEXT:    fcvt.s.h a1, a1
+; RV32IZHINXMIN-NEXT:    feq.s a1, a1, a1
+; RV32IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV32IZHINXMIN-NEXT:    feq.s a0, a0, a0
+; RV32IZHINXMIN-NEXT:    and a0, a0, a1
+; RV32IZHINXMIN-NEXT:    bnez a0, .LBB8_2
+; RV32IZHINXMIN-NEXT:  # %bb.1: # %if.else
+; RV32IZHINXMIN-NEXT:    ret
+; RV32IZHINXMIN-NEXT:  .LBB8_2: # %if.then
+; RV32IZHINXMIN-NEXT:    addi sp, sp, -16
+; RV32IZHINXMIN-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZHINXMIN-NEXT:    call abort@plt
+;
+; RV64IZHINXMIN-LABEL: br_fcmp_ord:
+; RV64IZHINXMIN:       # %bb.0:
+; RV64IZHINXMIN-NEXT:    fcvt.s.h a1, a1
+; RV64IZHINXMIN-NEXT:    feq.s a1, a1, a1
+; RV64IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV64IZHINXMIN-NEXT:    feq.s a0, a0, a0
+; RV64IZHINXMIN-NEXT:    and a0, a0, a1
+; RV64IZHINXMIN-NEXT:    bnez a0, .LBB8_2
+; RV64IZHINXMIN-NEXT:  # %bb.1: # %if.else
+; RV64IZHINXMIN-NEXT:    ret
+; RV64IZHINXMIN-NEXT:  .LBB8_2: # %if.then
+; RV64IZHINXMIN-NEXT:    addi sp, sp, -16
+; RV64IZHINXMIN-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IZHINXMIN-NEXT:    call abort@plt
   %1 = fcmp ord half %a, %b
   br i1 %1, label %if.then, label %if.else
 if.else:
   ret void
 if.then:
   tail call void @abort()
   unreachable
 }

 ; RV64IZFH-NEXT:    beqz a0, .LBB9_2
 ; RV64IZFH-NEXT:  # %bb.1: # %if.else
 ; RV64IZFH-NEXT:    ret
 ; RV64IZFH-NEXT:  .LBB9_2: # %if.then
 ; RV64IZFH-NEXT:    addi sp, sp, -16
 ; RV64IZFH-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64IZFH-NEXT:    call abort@plt
 ;
+; RV32IZHINX-LABEL: br_fcmp_ueq:
+; RV32IZHINX:       # %bb.0:
+; RV32IZHINX-NEXT:    flt.h a2, a0, a1
+; RV32IZHINX-NEXT:    flt.h a0, a1, a0
+; RV32IZHINX-NEXT:    or a0, a0, a2
+; RV32IZHINX-NEXT:    beqz a0, .LBB9_2
+; RV32IZHINX-NEXT:  # %bb.1: # %if.else
+; RV32IZHINX-NEXT:    ret
+; RV32IZHINX-NEXT:  .LBB9_2: # %if.then
+; RV32IZHINX-NEXT:    addi sp, sp, -16
+; RV32IZHINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZHINX-NEXT:    call abort@plt
+;
+; RV64IZHINX-LABEL: br_fcmp_ueq:
+; RV64IZHINX:       # %bb.0:
+; RV64IZHINX-NEXT:    flt.h a2, a0, a1
+; RV64IZHINX-NEXT:    flt.h a0, a1, a0
+; RV64IZHINX-NEXT:    or a0, a0, a2
+; RV64IZHINX-NEXT:    beqz a0, .LBB9_2
+; RV64IZHINX-NEXT:  # %bb.1: # %if.else
+; RV64IZHINX-NEXT:    ret
+; RV64IZHINX-NEXT:  .LBB9_2: # %if.then
+; RV64IZHINX-NEXT:    addi sp, sp, -16
+; RV64IZHINX-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IZHINX-NEXT:    call abort@plt
+;
 ; RV32IZFHMIN-LABEL: br_fcmp_ueq:
 ; RV32IZFHMIN:       # %bb.0:
 ; RV32IZFHMIN-NEXT:    fcvt.s.h fa5, fa1
 ; RV32IZFHMIN-NEXT:    fcvt.s.h fa4, fa0
 ; RV32IZFHMIN-NEXT:    flt.s a0, fa4, fa5
 ; RV32IZFHMIN-NEXT:    flt.s a1, fa5, fa4
 ; RV32IZFHMIN-NEXT:    or a0, a1, a0
 ; RV32IZFHMIN-NEXT:    beqz a0, .LBB9_2

 ; RV64IZFHMIN-NEXT:    or a0, a1, a0
 ; RV64IZFHMIN-NEXT:    beqz a0, .LBB9_2
 ; RV64IZFHMIN-NEXT:  # %bb.1: # %if.else
 ; RV64IZFHMIN-NEXT:    ret
 ; RV64IZFHMIN-NEXT:  .LBB9_2: # %if.then
 ; RV64IZFHMIN-NEXT:    addi sp, sp, -16
 ; RV64IZFHMIN-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64IZFHMIN-NEXT:    call abort@plt
+;
+; RV32IZHINXMIN-LABEL: br_fcmp_ueq:
+; RV32IZHINXMIN:       # %bb.0:
+; RV32IZHINXMIN-NEXT:    fcvt.s.h a1, a1
+; RV32IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV32IZHINXMIN-NEXT:    flt.s a2, a0, a1
+; RV32IZHINXMIN-NEXT:    flt.s a0, a1, a0
+; RV32IZHINXMIN-NEXT:    or a0, a0, a2
+; RV32IZHINXMIN-NEXT:    beqz a0, .LBB9_2
+; RV32IZHINXMIN-NEXT:  # %bb.1: # %if.else
+; RV32IZHINXMIN-NEXT:    ret
+; RV32IZHINXMIN-NEXT:  .LBB9_2: # %if.then
+; RV32IZHINXMIN-NEXT:    addi sp, sp, -16
+; RV32IZHINXMIN-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZHINXMIN-NEXT:    call abort@plt
+;
+; RV64IZHINXMIN-LABEL: br_fcmp_ueq:
+; RV64IZHINXMIN:       # %bb.0:
+; RV64IZHINXMIN-NEXT:    fcvt.s.h a1, a1
+; RV64IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV64IZHINXMIN-NEXT:    flt.s a2, a0, a1
+; RV64IZHINXMIN-NEXT:    flt.s a0, a1, a0
+; RV64IZHINXMIN-NEXT:    or a0, a0, a2
+; RV64IZHINXMIN-NEXT:    beqz a0, .LBB9_2
+; RV64IZHINXMIN-NEXT:  # %bb.1: # %if.else
+; RV64IZHINXMIN-NEXT:    ret
+; RV64IZHINXMIN-NEXT:  .LBB9_2: # %if.then
+; RV64IZHINXMIN-NEXT:    addi sp, sp, -16
+; RV64IZHINXMIN-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IZHINXMIN-NEXT:    call abort@plt
   %1 = fcmp ueq half %a, %b
   br i1 %1, label %if.then, label %if.else
 if.else:
   ret void
 if.then:
   tail call void @abort()
   unreachable
 }

 ; RV64IZFH-NEXT:    beqz a0, .LBB10_2
 ; RV64IZFH-NEXT:  # %bb.1: # %if.else
 ; RV64IZFH-NEXT:    ret
 ; RV64IZFH-NEXT:  .LBB10_2: # %if.then
 ; RV64IZFH-NEXT:    addi sp, sp, -16
 ; RV64IZFH-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64IZFH-NEXT:    call abort@plt
 ;
+; RV32IZHINX-LABEL: br_fcmp_ugt:
+; RV32IZHINX:       # %bb.0:
+; RV32IZHINX-NEXT:    fle.h a0, a0, a1
+; RV32IZHINX-NEXT:    beqz a0, .LBB10_2
+; RV32IZHINX-NEXT:  # %bb.1: # %if.else
+; RV32IZHINX-NEXT:    ret
+; RV32IZHINX-NEXT:  .LBB10_2: # %if.then
+; RV32IZHINX-NEXT:    addi sp, sp, -16
+; RV32IZHINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZHINX-NEXT:    call abort@plt
+;
+; RV64IZHINX-LABEL: br_fcmp_ugt:
+; RV64IZHINX:       # %bb.0:
+; RV64IZHINX-NEXT:    fle.h a0, a0, a1
+; RV64IZHINX-NEXT:    beqz a0, .LBB10_2
+; RV64IZHINX-NEXT:  # %bb.1: # %if.else
+; RV64IZHINX-NEXT:    ret
+; RV64IZHINX-NEXT:  .LBB10_2: # %if.then
+; RV64IZHINX-NEXT:    addi sp, sp, -16
+; RV64IZHINX-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IZHINX-NEXT:    call abort@plt
+;
 ; RV32IZFHMIN-LABEL: br_fcmp_ugt:
 ; RV32IZFHMIN:       # %bb.0:
 ; RV32IZFHMIN-NEXT:    fcvt.s.h fa5, fa1
 ; RV32IZFHMIN-NEXT:    fcvt.s.h fa4, fa0
 ; RV32IZFHMIN-NEXT:    fle.s a0, fa4, fa5
 ; RV32IZFHMIN-NEXT:    beqz a0, .LBB10_2
 ; RV32IZFHMIN-NEXT:  # %bb.1: # %if.else
 ; RV32IZFHMIN-NEXT:    ret

 ; RV64IZFHMIN-NEXT:    fle.s a0, fa4, fa5
 ; RV64IZFHMIN-NEXT:    beqz a0, .LBB10_2
 ; RV64IZFHMIN-NEXT:  # %bb.1: # %if.else
 ; RV64IZFHMIN-NEXT:    ret
 ; RV64IZFHMIN-NEXT:  .LBB10_2: # %if.then
 ; RV64IZFHMIN-NEXT:    addi sp, sp, -16
 ; RV64IZFHMIN-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64IZFHMIN-NEXT:    call abort@plt
+;
+; RV32IZHINXMIN-LABEL: br_fcmp_ugt:
+; RV32IZHINXMIN:       # %bb.0:
+; RV32IZHINXMIN-NEXT:    fcvt.s.h a1, a1
+; RV32IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV32IZHINXMIN-NEXT:    fle.s a0, a0, a1
+; RV32IZHINXMIN-NEXT:    beqz a0, .LBB10_2
+; RV32IZHINXMIN-NEXT:  # %bb.1: # %if.else
+; RV32IZHINXMIN-NEXT:    ret
+; RV32IZHINXMIN-NEXT:  .LBB10_2: # %if.then
+; RV32IZHINXMIN-NEXT:    addi sp, sp, -16
+; RV32IZHINXMIN-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZHINXMIN-NEXT:    call abort@plt
+;
+; RV64IZHINXMIN-LABEL: br_fcmp_ugt:
+; RV64IZHINXMIN:       # %bb.0:
+; RV64IZHINXMIN-NEXT:    fcvt.s.h a1, a1
+; RV64IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV64IZHINXMIN-NEXT:    fle.s a0, a0, a1
+; RV64IZHINXMIN-NEXT:    beqz a0, .LBB10_2
+; RV64IZHINXMIN-NEXT:  # %bb.1: # %if.else
+; RV64IZHINXMIN-NEXT:    ret
+; RV64IZHINXMIN-NEXT:  .LBB10_2: # %if.then
+; RV64IZHINXMIN-NEXT:    addi sp, sp, -16
+; RV64IZHINXMIN-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IZHINXMIN-NEXT:    call abort@plt
   %1 = fcmp ugt half %a, %b
   br i1 %1, label %if.then, label %if.else
 if.else:
   ret void
 if.then:
   tail call void @abort()
   unreachable
 }

 ; RV64IZFH-NEXT:    beqz a0, .LBB11_2
 ; RV64IZFH-NEXT:  # %bb.1: # %if.else
 ; RV64IZFH-NEXT:    ret
 ; RV64IZFH-NEXT:  .LBB11_2: # %if.then
 ; RV64IZFH-NEXT:    addi sp, sp, -16
 ; RV64IZFH-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64IZFH-NEXT:    call abort@plt
 ;
+; RV32IZHINX-LABEL: br_fcmp_uge:
+; RV32IZHINX:       # %bb.0:
+; RV32IZHINX-NEXT:    flt.h a0, a0, a1
+; RV32IZHINX-NEXT:    beqz a0, .LBB11_2
+; RV32IZHINX-NEXT:  # %bb.1: # %if.else
+; RV32IZHINX-NEXT:    ret
+; RV32IZHINX-NEXT:  .LBB11_2: # %if.then
+; RV32IZHINX-NEXT:    addi sp, sp, -16
+; RV32IZHINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZHINX-NEXT:    call abort@plt
+;
+; RV64IZHINX-LABEL: br_fcmp_uge:
+; RV64IZHINX:       # %bb.0:
+; RV64IZHINX-NEXT:    flt.h a0, a0, a1
+; RV64IZHINX-NEXT:    beqz a0, .LBB11_2
+; RV64IZHINX-NEXT:  # %bb.1: # %if.else
+; RV64IZHINX-NEXT:    ret
+; RV64IZHINX-NEXT:  .LBB11_2: # %if.then
+; RV64IZHINX-NEXT:    addi sp, sp, -16
+; RV64IZHINX-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IZHINX-NEXT:    call abort@plt
+;
 ; RV32IZFHMIN-LABEL: br_fcmp_uge:
 ; RV32IZFHMIN:       # %bb.0:
 ; RV32IZFHMIN-NEXT:    fcvt.s.h fa5, fa1
 ; RV32IZFHMIN-NEXT:    fcvt.s.h fa4, fa0
 ; RV32IZFHMIN-NEXT:    flt.s a0, fa4, fa5
 ; RV32IZFHMIN-NEXT:    beqz a0, .LBB11_2
 ; RV32IZFHMIN-NEXT:  # %bb.1: # %if.else
 ; RV32IZFHMIN-NEXT:    ret

 ; RV64IZFHMIN-NEXT:    flt.s a0, fa4, fa5
 ; RV64IZFHMIN-NEXT:    beqz a0, .LBB11_2
 ; RV64IZFHMIN-NEXT:  # %bb.1: # %if.else
 ; RV64IZFHMIN-NEXT:    ret
 ; RV64IZFHMIN-NEXT:  .LBB11_2: # %if.then
 ; RV64IZFHMIN-NEXT:    addi sp, sp, -16
 ; RV64IZFHMIN-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64IZFHMIN-NEXT:    call abort@plt
+;
+; RV32IZHINXMIN-LABEL: br_fcmp_uge:
+; RV32IZHINXMIN:       # %bb.0:
+; RV32IZHINXMIN-NEXT:    fcvt.s.h a1, a1
+; RV32IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV32IZHINXMIN-NEXT:    flt.s a0, a0, a1
+; RV32IZHINXMIN-NEXT:    beqz a0, .LBB11_2
+; RV32IZHINXMIN-NEXT:  # %bb.1: # %if.else
+; RV32IZHINXMIN-NEXT:    ret
+; RV32IZHINXMIN-NEXT:  .LBB11_2: # %if.then
+; RV32IZHINXMIN-NEXT:    addi sp, sp, -16
+; RV32IZHINXMIN-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZHINXMIN-NEXT:    call abort@plt
+;
+; RV64IZHINXMIN-LABEL: br_fcmp_uge:
+; RV64IZHINXMIN:       # %bb.0:
+; RV64IZHINXMIN-NEXT:    fcvt.s.h a1, a1
+; RV64IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV64IZHINXMIN-NEXT:    flt.s a0, a0, a1
+; RV64IZHINXMIN-NEXT:    beqz a0, .LBB11_2
+; RV64IZHINXMIN-NEXT:  # %bb.1: # %if.else
+; RV64IZHINXMIN-NEXT:    ret
+; RV64IZHINXMIN-NEXT:  .LBB11_2: # %if.then
+; RV64IZHINXMIN-NEXT:    addi sp, sp, -16
+; RV64IZHINXMIN-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IZHINXMIN-NEXT:    call abort@plt
   %1 = fcmp uge half %a, %b
   br i1 %1, label %if.then, label %if.else
 if.else:
   ret void
 if.then:
   tail call void @abort()
   unreachable
 }

 ; RV64IZFH-NEXT:    beqz a0, .LBB12_2
 ; RV64IZFH-NEXT:  # %bb.1: # %if.else
 ; RV64IZFH-NEXT:    ret
 ; RV64IZFH-NEXT:  .LBB12_2: # %if.then
 ; RV64IZFH-NEXT:    addi sp, sp, -16
 ; RV64IZFH-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64IZFH-NEXT:    call abort@plt
 ;
+; RV32IZHINX-LABEL: br_fcmp_ult:
+; RV32IZHINX:       # %bb.0:
+; RV32IZHINX-NEXT:    fle.h a0, a1, a0
+; RV32IZHINX-NEXT:    beqz a0, .LBB12_2
+; RV32IZHINX-NEXT:  # %bb.1: # %if.else
+; RV32IZHINX-NEXT:    ret
+; RV32IZHINX-NEXT:  .LBB12_2: # %if.then
+; RV32IZHINX-NEXT:    addi sp, sp, -16
+; RV32IZHINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZHINX-NEXT:    call abort@plt
+;
+; RV64IZHINX-LABEL: br_fcmp_ult:
+; RV64IZHINX:       # %bb.0:
+; RV64IZHINX-NEXT:    fle.h a0, a1, a0
+; RV64IZHINX-NEXT:    beqz a0, .LBB12_2
+; RV64IZHINX-NEXT:  # %bb.1: # %if.else
+; RV64IZHINX-NEXT:    ret
+; RV64IZHINX-NEXT:  .LBB12_2: # %if.then
+; RV64IZHINX-NEXT:    addi sp, sp, -16
+; RV64IZHINX-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IZHINX-NEXT:    call abort@plt
+;
 ; RV32IZFHMIN-LABEL: br_fcmp_ult:
 ; RV32IZFHMIN:       # %bb.0:
 ; RV32IZFHMIN-NEXT:    fcvt.s.h fa5, fa0
 ; RV32IZFHMIN-NEXT:    fcvt.s.h fa4, fa1
 ; RV32IZFHMIN-NEXT:    fle.s a0, fa4, fa5
 ; RV32IZFHMIN-NEXT:    beqz a0, .LBB12_2
 ; RV32IZFHMIN-NEXT:  # %bb.1: # %if.else
 ; RV32IZFHMIN-NEXT:    ret

 ; RV64IZFHMIN-NEXT:    fle.s a0, fa4, fa5
 ; RV64IZFHMIN-NEXT:    beqz a0, .LBB12_2
 ; RV64IZFHMIN-NEXT:  # %bb.1: # %if.else
 ; RV64IZFHMIN-NEXT:    ret
 ; RV64IZFHMIN-NEXT:  .LBB12_2: # %if.then
 ; RV64IZFHMIN-NEXT:    addi sp, sp, -16
 ; RV64IZFHMIN-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64IZFHMIN-NEXT:    call abort@plt
+;
+; RV32IZHINXMIN-LABEL: br_fcmp_ult:
+; RV32IZHINXMIN:       # %bb.0:
+; RV32IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV32IZHINXMIN-NEXT:    fcvt.s.h a1, a1
+; RV32IZHINXMIN-NEXT:    fle.s a0, a1, a0
+; RV32IZHINXMIN-NEXT:    beqz a0, .LBB12_2
+; RV32IZHINXMIN-NEXT:  # %bb.1: # %if.else
+; RV32IZHINXMIN-NEXT:    ret
+; RV32IZHINXMIN-NEXT:  .LBB12_2: # %if.then
+; RV32IZHINXMIN-NEXT:    addi sp, sp, -16
+; RV32IZHINXMIN-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZHINXMIN-NEXT:    call abort@plt
+;
+; RV64IZHINXMIN-LABEL: br_fcmp_ult:
+; RV64IZHINXMIN:       # %bb.0:
+; RV64IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV64IZHINXMIN-NEXT:    fcvt.s.h a1, a1
+; RV64IZHINXMIN-NEXT:    fle.s a0, a1, a0
+; RV64IZHINXMIN-NEXT:    beqz a0, .LBB12_2
+; RV64IZHINXMIN-NEXT:  # %bb.1: # %if.else
+; RV64IZHINXMIN-NEXT:    ret
+; RV64IZHINXMIN-NEXT:  .LBB12_2: # %if.then
+; RV64IZHINXMIN-NEXT:    addi sp, sp, -16
+; RV64IZHINXMIN-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IZHINXMIN-NEXT:    call abort@plt
   %1 = fcmp ult half %a, %b
   br i1 %1, label %if.then, label %if.else
 if.else:
   ret void
 if.then:
   tail call void @abort()
   unreachable
 }

 ; RV64IZFH-NEXT:    beqz a0, .LBB13_2
 ; RV64IZFH-NEXT:  # %bb.1: # %if.else
 ; RV64IZFH-NEXT:    ret
 ; RV64IZFH-NEXT:  .LBB13_2: # %if.then
 ; RV64IZFH-NEXT:    addi sp, sp, -16
 ; RV64IZFH-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64IZFH-NEXT:    call abort@plt
 ;
+; RV32IZHINX-LABEL: br_fcmp_ule:
+; RV32IZHINX:       # %bb.0:
+; RV32IZHINX-NEXT:    flt.h a0, a1, a0
+; RV32IZHINX-NEXT:    beqz a0, .LBB13_2
+; RV32IZHINX-NEXT:  # %bb.1: # %if.else
+; RV32IZHINX-NEXT:    ret
+; RV32IZHINX-NEXT:  .LBB13_2: # %if.then
+; RV32IZHINX-NEXT:    addi sp, sp, -16
+; RV32IZHINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZHINX-NEXT:    call abort@plt
+;
+; RV64IZHINX-LABEL: br_fcmp_ule:
+; RV64IZHINX:       # %bb.0:
+; RV64IZHINX-NEXT:    flt.h a0, a1, a0
+; RV64IZHINX-NEXT:    beqz a0, .LBB13_2
+; RV64IZHINX-NEXT:  # %bb.1: # %if.else
+; RV64IZHINX-NEXT:    ret
+; RV64IZHINX-NEXT:  .LBB13_2: # %if.then
+; RV64IZHINX-NEXT:    addi sp, sp, -16
+; RV64IZHINX-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IZHINX-NEXT:    call abort@plt
+;
 ; RV32IZFHMIN-LABEL: br_fcmp_ule:
 ; RV32IZFHMIN:       # %bb.0:
 ; RV32IZFHMIN-NEXT:    fcvt.s.h fa5, fa0
 ; RV32IZFHMIN-NEXT:    fcvt.s.h fa4, fa1
 ; RV32IZFHMIN-NEXT:    flt.s a0, fa4, fa5
 ; RV32IZFHMIN-NEXT:    beqz a0, .LBB13_2
 ; RV32IZFHMIN-NEXT:  # %bb.1: # %if.else
 ; RV32IZFHMIN-NEXT:    ret

 ; RV64IZFHMIN-NEXT:    flt.s a0, fa4, fa5
 ; RV64IZFHMIN-NEXT:    beqz a0, .LBB13_2
 ; RV64IZFHMIN-NEXT:  # %bb.1: # %if.else
 ; RV64IZFHMIN-NEXT:    ret
 ; RV64IZFHMIN-NEXT:  .LBB13_2: # %if.then
 ; RV64IZFHMIN-NEXT:    addi sp, sp, -16
 ; RV64IZFHMIN-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64IZFHMIN-NEXT:    call abort@plt
+;
+; RV32IZHINXMIN-LABEL: br_fcmp_ule:
+; RV32IZHINXMIN:       # %bb.0:
+; RV32IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV32IZHINXMIN-NEXT:    fcvt.s.h a1, a1
+; RV32IZHINXMIN-NEXT:    flt.s a0, a1, a0
+; RV32IZHINXMIN-NEXT:    beqz a0, .LBB13_2
+; RV32IZHINXMIN-NEXT:  # %bb.1: # %if.else
+; RV32IZHINXMIN-NEXT:    ret
+; RV32IZHINXMIN-NEXT:  .LBB13_2: # %if.then
+; RV32IZHINXMIN-NEXT:    addi sp, sp, -16
+; RV32IZHINXMIN-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZHINXMIN-NEXT:    call abort@plt
+;
+; RV64IZHINXMIN-LABEL: br_fcmp_ule:
+; RV64IZHINXMIN:       # %bb.0:
+; RV64IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV64IZHINXMIN-NEXT:    fcvt.s.h a1, a1
+; RV64IZHINXMIN-NEXT:    flt.s a0, a1, a0
+; RV64IZHINXMIN-NEXT:    beqz a0, .LBB13_2
+; RV64IZHINXMIN-NEXT:  # %bb.1: # %if.else
+; RV64IZHINXMIN-NEXT:    ret
+; RV64IZHINXMIN-NEXT:  .LBB13_2: # %if.then
+; RV64IZHINXMIN-NEXT:    addi sp, sp, -16
+; RV64IZHINXMIN-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IZHINXMIN-NEXT:    call abort@plt
   %1 = fcmp ule half %a, %b
   br i1 %1, label %if.then, label %if.else
 if.else:
   ret void
 if.then:
   tail call void @abort()
   unreachable
 }

 ; RV64IZFH-NEXT:    beqz a0, .LBB14_2
 ; RV64IZFH-NEXT:  # %bb.1: # %if.else
 ; RV64IZFH-NEXT:    ret
 ; RV64IZFH-NEXT:  .LBB14_2: # %if.then
 ; RV64IZFH-NEXT:    addi sp, sp, -16
 ; RV64IZFH-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64IZFH-NEXT:    call abort@plt
 ;
+; RV32IZHINX-LABEL: br_fcmp_une:
+; RV32IZHINX:       # %bb.0:
+; RV32IZHINX-NEXT:    feq.h a0, a0, a1
+; RV32IZHINX-NEXT:    beqz a0, .LBB14_2
+; RV32IZHINX-NEXT:  # %bb.1: # %if.else
+; RV32IZHINX-NEXT:    ret
+; RV32IZHINX-NEXT:  .LBB14_2: # %if.then
+; RV32IZHINX-NEXT:    addi sp, sp, -16
+; RV32IZHINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZHINX-NEXT:    call abort@plt
+;
+; RV64IZHINX-LABEL: br_fcmp_une:
+; RV64IZHINX:       # %bb.0:
+; RV64IZHINX-NEXT:    feq.h a0, a0, a1
+; RV64IZHINX-NEXT:    beqz a0, .LBB14_2
+; RV64IZHINX-NEXT:  # %bb.1: # %if.else
+; RV64IZHINX-NEXT:    ret
+; RV64IZHINX-NEXT:  .LBB14_2: # %if.then
+; RV64IZHINX-NEXT:    addi sp, sp, -16
+; RV64IZHINX-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IZHINX-NEXT:    call abort@plt
+;
 ; RV32IZFHMIN-LABEL: br_fcmp_une:
 ; RV32IZFHMIN:       # %bb.0:
 ; RV32IZFHMIN-NEXT:    fcvt.s.h fa5, fa1
 ; RV32IZFHMIN-NEXT:    fcvt.s.h fa4, fa0
 ; RV32IZFHMIN-NEXT:    feq.s a0, fa4, fa5
 ; RV32IZFHMIN-NEXT:    beqz a0, .LBB14_2
 ; RV32IZFHMIN-NEXT:  # %bb.1: # %if.else
 ; RV32IZFHMIN-NEXT:    ret

 ; RV64IZFHMIN-NEXT:    feq.s a0, fa4, fa5
 ; RV64IZFHMIN-NEXT:    beqz a0, .LBB14_2
 ; RV64IZFHMIN-NEXT:  # %bb.1: # %if.else
 ; RV64IZFHMIN-NEXT:    ret
 ; RV64IZFHMIN-NEXT:  .LBB14_2: # %if.then
 ; RV64IZFHMIN-NEXT:    addi sp, sp, -16
 ; RV64IZFHMIN-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64IZFHMIN-NEXT:    call abort@plt
+;
+; RV32IZHINXMIN-LABEL: br_fcmp_une:
+; RV32IZHINXMIN:       # %bb.0:
+; RV32IZHINXMIN-NEXT:    fcvt.s.h a1, a1
+; RV32IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV32IZHINXMIN-NEXT:    feq.s a0, a0, a1
+; RV32IZHINXMIN-NEXT:    beqz a0, .LBB14_2
+; RV32IZHINXMIN-NEXT:  # %bb.1: # %if.else
+; RV32IZHINXMIN-NEXT:    ret
+; RV32IZHINXMIN-NEXT:  .LBB14_2: # %if.then
+; RV32IZHINXMIN-NEXT:    addi sp, sp, -16
+; RV32IZHINXMIN-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZHINXMIN-NEXT:    call abort@plt
+;
+; RV64IZHINXMIN-LABEL: br_fcmp_une:
+; RV64IZHINXMIN:       # %bb.0:
+; RV64IZHINXMIN-NEXT:    fcvt.s.h a1, a1
+; RV64IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV64IZHINXMIN-NEXT:    feq.s a0, a0, a1
+; RV64IZHINXMIN-NEXT:    beqz a0, .LBB14_2
+; RV64IZHINXMIN-NEXT:  # %bb.1: # %if.else
+; RV64IZHINXMIN-NEXT:    ret
+; RV64IZHINXMIN-NEXT:  .LBB14_2: # %if.then
+; RV64IZHINXMIN-NEXT:    addi sp, sp, -16
+; RV64IZHINXMIN-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IZHINXMIN-NEXT:    call abort@plt
   %1 = fcmp une half %a, %b
   br i1 %1, label %if.then, label %if.else
 if.else:
   ret void
 if.then:
   tail call void @abort()
   unreachable
 }

 ; RV64IZFH-NEXT:    beqz a0, .LBB15_2
 ; RV64IZFH-NEXT:  # %bb.1: # %if.else
 ; RV64IZFH-NEXT:    ret
 ; RV64IZFH-NEXT:  .LBB15_2: # %if.then
 ; RV64IZFH-NEXT:    addi sp, sp, -16
 ; RV64IZFH-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64IZFH-NEXT:    call abort@plt
 ;
+; RV32IZHINX-LABEL: br_fcmp_uno:
+; RV32IZHINX:       # %bb.0:
+; RV32IZHINX-NEXT:    feq.h a1, a1, a1
+; RV32IZHINX-NEXT:    feq.h a0, a0, a0
+; RV32IZHINX-NEXT:    and a0, a0, a1
+; RV32IZHINX-NEXT:    beqz a0, .LBB15_2
+; RV32IZHINX-NEXT:  # %bb.1: # %if.else
+; RV32IZHINX-NEXT:    ret
+; RV32IZHINX-NEXT:  .LBB15_2: # %if.then
+; RV32IZHINX-NEXT:    addi sp, sp, -16
+; RV32IZHINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZHINX-NEXT:    call abort@plt
+;
+; RV64IZHINX-LABEL: br_fcmp_uno:
+; RV64IZHINX:       # %bb.0:
+; RV64IZHINX-NEXT:    feq.h a1, a1, a1
+; RV64IZHINX-NEXT:    feq.h a0, a0, a0
+; RV64IZHINX-NEXT:    and a0, a0, a1
+; RV64IZHINX-NEXT:    beqz a0, .LBB15_2
+; RV64IZHINX-NEXT:  # %bb.1: # %if.else
+; RV64IZHINX-NEXT:    ret
+; RV64IZHINX-NEXT:  .LBB15_2: # %if.then
+; RV64IZHINX-NEXT:    addi sp, sp, -16
+; RV64IZHINX-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IZHINX-NEXT:    call abort@plt
+;
 ; RV32IZFHMIN-LABEL: br_fcmp_uno:
 ; RV32IZFHMIN:       # %bb.0:
 ; RV32IZFHMIN-NEXT:    fcvt.s.h fa5, fa1
 ; RV32IZFHMIN-NEXT:    feq.s a0, fa5, fa5
 ; RV32IZFHMIN-NEXT:    fcvt.s.h fa5, fa0
 ; RV32IZFHMIN-NEXT:    feq.s a1, fa5, fa5
 ; RV32IZFHMIN-NEXT:    and a0, a1, a0
 ; RV32IZFHMIN-NEXT:    beqz a0, .LBB15_2

 ; RV64IZFHMIN-NEXT:    and a0, a1, a0
 ; RV64IZFHMIN-NEXT:    beqz a0, .LBB15_2
 ; RV64IZFHMIN-NEXT:  # %bb.1: # %if.else
 ; RV64IZFHMIN-NEXT:    ret
 ; RV64IZFHMIN-NEXT:  .LBB15_2: # %if.then
 ; RV64IZFHMIN-NEXT:    addi sp, sp, -16
 ; RV64IZFHMIN-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64IZFHMIN-NEXT:    call abort@plt
+;
+; RV32IZHINXMIN-LABEL: br_fcmp_uno:
+; RV32IZHINXMIN:       # %bb.0:
+; RV32IZHINXMIN-NEXT:    fcvt.s.h a1, a1
+; RV32IZHINXMIN-NEXT:    feq.s a1, a1, a1
+; RV32IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV32IZHINXMIN-NEXT:    feq.s a0, a0, a0
+; RV32IZHINXMIN-NEXT:    and a0, a0, a1
+; RV32IZHINXMIN-NEXT:    beqz a0, .LBB15_2
+; RV32IZHINXMIN-NEXT:  # %bb.1: # %if.else
+; RV32IZHINXMIN-NEXT:    ret
+; RV32IZHINXMIN-NEXT:  .LBB15_2: # %if.then
+; RV32IZHINXMIN-NEXT:    addi sp, sp, -16
+; RV32IZHINXMIN-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZHINXMIN-NEXT:    call abort@plt
+;
+; RV64IZHINXMIN-LABEL: br_fcmp_uno:
+; RV64IZHINXMIN:       # %bb.0:
+; RV64IZHINXMIN-NEXT:    fcvt.s.h a1, a1
+; RV64IZHINXMIN-NEXT:    feq.s a1, a1, a1
+; RV64IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV64IZHINXMIN-NEXT:    feq.s a0, a0, a0
+; RV64IZHINXMIN-NEXT:    and a0, a0, a1
+; RV64IZHINXMIN-NEXT:    beqz a0, .LBB15_2
+; RV64IZHINXMIN-NEXT:  # %bb.1: # %if.else
+; RV64IZHINXMIN-NEXT:    ret
+; RV64IZHINXMIN-NEXT:  .LBB15_2: # %if.then
+; RV64IZHINXMIN-NEXT:    addi sp, sp, -16
+; RV64IZHINXMIN-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IZHINXMIN-NEXT:    call abort@plt
   %1 = fcmp uno half %a, %b
   br i1 %1, label %if.then, label %if.else
 if.else:
   ret void
 if.then:
   tail call void @abort()
   unreachable
 }

 ; RV64IZFH-NEXT:    bnez a0, .LBB16_2
 ; RV64IZFH-NEXT:  # %bb.1: # %if.else
 ; RV64IZFH-NEXT:    ret
 ; RV64IZFH-NEXT:  .LBB16_2: # %if.then
 ; RV64IZFH-NEXT:    addi sp, sp, -16
 ; RV64IZFH-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64IZFH-NEXT:    call abort@plt
 ;
+; RV32IZHINX-LABEL: br_fcmp_true:
+; RV32IZHINX:       # %bb.0:
+; RV32IZHINX-NEXT:    li a0, 1
+; RV32IZHINX-NEXT:    bnez a0, .LBB16_2
+; RV32IZHINX-NEXT:  # %bb.1: # %if.else
+; RV32IZHINX-NEXT:    ret
+; RV32IZHINX-NEXT:  .LBB16_2: # %if.then
+; RV32IZHINX-NEXT:    addi sp, sp, -16
+; RV32IZHINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZHINX-NEXT:    call abort@plt
+;
+; RV64IZHINX-LABEL: br_fcmp_true:
+; RV64IZHINX:       # %bb.0:
+; RV64IZHINX-NEXT:    li a0, 1
+; RV64IZHINX-NEXT:    bnez a0, .LBB16_2
+; RV64IZHINX-NEXT:  # %bb.1: # %if.else
+; RV64IZHINX-NEXT:    ret
+; RV64IZHINX-NEXT:  .LBB16_2: # %if.then
+; RV64IZHINX-NEXT:    addi sp, sp, -16
+; RV64IZHINX-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IZHINX-NEXT:    call abort@plt
+;
 ; RV32IZFHMIN-LABEL: br_fcmp_true:
 ; RV32IZFHMIN:       # %bb.0:
 ; RV32IZFHMIN-NEXT:    li a0, 1
 ; RV32IZFHMIN-NEXT:    bnez a0, .LBB16_2
 ; RV32IZFHMIN-NEXT:  # %bb.1: # %if.else
 ; RV32IZFHMIN-NEXT:    ret
 ; RV32IZFHMIN-NEXT:  .LBB16_2: # %if.then
 ; RV32IZFHMIN-NEXT:    addi sp, sp, -16
 ; RV32IZFHMIN-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32IZFHMIN-NEXT:    call abort@plt
 ;
 ; RV64IZFHMIN-LABEL: br_fcmp_true:
 ; RV64IZFHMIN:       # %bb.0:
 ; RV64IZFHMIN-NEXT:    li a0, 1
 ; RV64IZFHMIN-NEXT:    bnez a0, .LBB16_2
 ; RV64IZFHMIN-NEXT:  # %bb.1: # %if.else
 ; RV64IZFHMIN-NEXT:    ret
 ; RV64IZFHMIN-NEXT:  .LBB16_2: # %if.then
 ; RV64IZFHMIN-NEXT:    addi sp, sp, -16
 ; RV64IZFHMIN-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64IZFHMIN-NEXT:    call abort@plt
+;
+; RV32IZHINXMIN-LABEL: br_fcmp_true:
+; RV32IZHINXMIN:       # %bb.0:
+; RV32IZHINXMIN-NEXT:    li a0, 1
+; RV32IZHINXMIN-NEXT:    bnez a0, .LBB16_2
+; RV32IZHINXMIN-NEXT:  # %bb.1: # %if.else
+; RV32IZHINXMIN-NEXT:    ret
+; RV32IZHINXMIN-NEXT:  .LBB16_2: # %if.then
+; RV32IZHINXMIN-NEXT:    addi sp, sp, -16
+; RV32IZHINXMIN-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZHINXMIN-NEXT:    call abort@plt
+;
+; RV64IZHINXMIN-LABEL: br_fcmp_true:
+; RV64IZHINXMIN:       # %bb.0:
+; RV64IZHINXMIN-NEXT:    li a0, 1
+; RV64IZHINXMIN-NEXT:    bnez a0, .LBB16_2
+; RV64IZHINXMIN-NEXT:  # %bb.1: # %if.else
+; RV64IZHINXMIN-NEXT:    ret
+; RV64IZHINXMIN-NEXT:  .LBB16_2: # %if.then
+; RV64IZHINXMIN-NEXT:    addi sp, sp, -16
+; RV64IZHINXMIN-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IZHINXMIN-NEXT:    call abort@plt
   %1 = fcmp true half %a, %b
   br i1 %1, label %if.then, label %if.else
 if.else:
   ret void
 if.then:
   tail call void @abort()
   unreachable
 }

llvm/test/CodeGen/RISCV/half-convert-strict.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -mattr=+zfh -verify-machineinstrs \
 ; RUN:   -target-abi ilp32f -disable-strictnode-mutation < %s \
 ; RUN:   | FileCheck -check-prefixes=CHECKIZFH,RV32IZFH %s
 ; RUN: llc -mtriple=riscv64 -mattr=+zfh -verify-machineinstrs \
 ; RUN:   -target-abi lp64f -disable-strictnode-mutation < %s \
 ; RUN:   | FileCheck -check-prefixes=CHECKIZFH,RV64IZFH %s
+; RUN: llc -mtriple=riscv32 -mattr=+zhinx -verify-machineinstrs \
+; RUN:   -target-abi ilp32 -disable-strictnode-mutation < %s \
+; RUN:   | FileCheck -check-prefixes=CHECKIZHINX,RV32IZHINX %s
+; RUN: llc -mtriple=riscv64 -mattr=+zhinx -verify-machineinstrs \
+; RUN:   -target-abi lp64 -disable-strictnode-mutation < %s \
+; RUN:   | FileCheck -check-prefixes=CHECKIZHINX,RV64IZHINX %s
 ; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh -verify-machineinstrs \
 ; RUN:   -target-abi ilp32d -disable-strictnode-mutation < %s \
 ; RUN:   | FileCheck -check-prefix=RV32IDZFH %s
 ; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh -verify-machineinstrs \
 ; RUN:   -target-abi lp64d -disable-strictnode-mutation < %s \
 ; RUN:   | FileCheck -check-prefix=RV64IDZFH %s
+; RUN: llc -mtriple=riscv32 -mattr=+zdinx,+zhinx -verify-machineinstrs \
+; RUN:   -target-abi ilp32 -disable-strictnode-mutation < %s \
+; RUN:   | FileCheck -check-prefix=RV32IZDINXZHINX %s
+; RUN: llc -mtriple=riscv64 -mattr=+zdinx,+zhinx -verify-machineinstrs \
+; RUN:   -target-abi lp64 -disable-strictnode-mutation < %s \
+; RUN:   | FileCheck -check-prefix=RV64IZDINXZHINX %s
 ; RUN: llc -mtriple=riscv32 -mattr=+zfhmin -verify-machineinstrs \
 ; RUN:   -target-abi ilp32f -disable-strictnode-mutation < %s \
 ; RUN:   | FileCheck -check-prefixes=CHECK32-IZFHMIN,RV32IFZFHMIN %s
 ; RUN: llc -mtriple=riscv64 -mattr=+zfhmin -verify-machineinstrs \
 ; RUN:   -target-abi lp64f -disable-strictnode-mutation < %s \
 ; RUN:   | FileCheck -check-prefixes=CHECK64-IZFHMIN,RV64IFZFHMIN %s
+; RUN: llc -mtriple=riscv32 -mattr=+zhinxmin -verify-machineinstrs \
+; RUN:   -target-abi ilp32 -disable-strictnode-mutation < %s \
+; RUN:   | FileCheck -check-prefixes=CHECK32-IZHINXMIN,RV32IZHINXMIN %s
+; RUN: llc -mtriple=riscv64 -mattr=+zhinxmin -verify-machineinstrs \
+; RUN:   -target-abi lp64 -disable-strictnode-mutation < %s \
+; RUN:   | FileCheck -check-prefixes=CHECK64-IZHINXMIN,RV64IZHINXMIN %s
 ; RUN: llc -mtriple=riscv32 -mattr=+d,+zfhmin -verify-machineinstrs \
 ; RUN:   -target-abi ilp32d -disable-strictnode-mutation < %s \
 ; RUN:   | FileCheck -check-prefixes=CHECK32-IZFHMIN,RV32IDZFHMIN %s
 ; RUN: llc -mtriple=riscv64 -mattr=+d,+zfhmin -verify-machineinstrs \
 ; RUN:   -target-abi lp64d -disable-strictnode-mutation < %s \
 ; RUN:   | FileCheck -check-prefixes=CHECK64-IZFHMIN,RV64IDZFHMIN %s
+; RUN: llc -mtriple=riscv32 -mattr=+zdinx,+zhinxmin -verify-machineinstrs \
+; RUN:   -target-abi ilp32 -disable-strictnode-mutation < %s \
+; RUN:   | FileCheck -check-prefixes=CHECK32-IZDINXZHINXMIN,RV32IZDINXZHINXMIN %s
+; RUN: llc -mtriple=riscv64 -mattr=+zdinx,+zhinxmin -verify-machineinstrs \
+; RUN:   -target-abi lp64 -disable-strictnode-mutation < %s \
+; RUN:   | FileCheck -check-prefixes=CHECK64-IZDINXZHINXMIN,RV64IZDINXZHINXMIN %s
 
 ; NOTE: The rounding mode metadata does not effect which instruction is
 ; selected. Dynamic rounding mode is always used for operations that
 ; support rounding mode.
 
 define i16 @fcvt_si_h(half %a) nounwind strictfp {
 ; RV32IZFH-LABEL: fcvt_si_h:
 ; RV32IZFH:       # %bb.0:
 ; RV32IZFH-NEXT:    fcvt.w.h a0, fa0, rtz
 ; RV32IZFH-NEXT:    ret
 ;
 ; RV64IZFH-LABEL: fcvt_si_h:
 ; RV64IZFH:       # %bb.0:
 ; RV64IZFH-NEXT:    fcvt.l.h a0, fa0, rtz
 ; RV64IZFH-NEXT:    ret
 ;
+; RV32IZHINX-LABEL: fcvt_si_h:
+; RV32IZHINX:       # %bb.0:
+; RV32IZHINX-NEXT:    fcvt.w.h a0, a0, rtz
+; RV32IZHINX-NEXT:    ret
+;
+; RV64IZHINX-LABEL: fcvt_si_h:
+; RV64IZHINX:       # %bb.0:
+; RV64IZHINX-NEXT:    fcvt.l.h a0, a0, rtz
+; RV64IZHINX-NEXT:    ret
+;
 ; RV32IDZFH-LABEL: fcvt_si_h:
 ; RV32IDZFH:       # %bb.0:
 ; RV32IDZFH-NEXT:    fcvt.w.h a0, fa0, rtz
 ; RV32IDZFH-NEXT:    ret
 ;
 ; RV64IDZFH-LABEL: fcvt_si_h:
 ; RV64IDZFH:       # %bb.0:
 ; RV64IDZFH-NEXT:    fcvt.l.h a0, fa0, rtz
 ; RV64IDZFH-NEXT:    ret
 ;
+; RV32IZDINXZHINX-LABEL: fcvt_si_h:
+; RV32IZDINXZHINX:       # %bb.0:
+; RV32IZDINXZHINX-NEXT:    fcvt.w.h a0, a0, rtz
+; RV32IZDINXZHINX-NEXT:    ret
+;
+; RV64IZDINXZHINX-LABEL: fcvt_si_h:
+; RV64IZDINXZHINX:       # %bb.0:
+; RV64IZDINXZHINX-NEXT:    fcvt.l.h a0, a0, rtz
+; RV64IZDINXZHINX-NEXT:    ret
+;
 ; CHECK32-IZFHMIN-LABEL: fcvt_si_h:
 ; CHECK32-IZFHMIN:       # %bb.0:
 ; CHECK32-IZFHMIN-NEXT:    fcvt.s.h fa5, fa0
 ; CHECK32-IZFHMIN-NEXT:    fcvt.w.s a0, fa5, rtz
 ; CHECK32-IZFHMIN-NEXT:    ret
 ;
 ; CHECK64-IZFHMIN-LABEL: fcvt_si_h:
 ; CHECK64-IZFHMIN:       # %bb.0:
 ; CHECK64-IZFHMIN-NEXT:    fcvt.s.h fa5, fa0
 ; CHECK64-IZFHMIN-NEXT:    fcvt.l.s a0, fa5, rtz
 ; CHECK64-IZFHMIN-NEXT:    ret
+;
+; CHECK32-IZHINXMIN-LABEL: fcvt_si_h:
+; CHECK32-IZHINXMIN:       # %bb.0:
+; CHECK32-IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECK32-IZHINXMIN-NEXT:    fcvt.w.s a0, a0, rtz
+; CHECK32-IZHINXMIN-NEXT:    ret
+;
+; CHECK64-IZHINXMIN-LABEL: fcvt_si_h:
+; CHECK64-IZHINXMIN:       # %bb.0:
+; CHECK64-IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECK64-IZHINXMIN-NEXT:    fcvt.l.s a0, a0, rtz
+; CHECK64-IZHINXMIN-NEXT:    ret
+;
+; CHECK32-IZDINXZHINXMIN-LABEL: fcvt_si_h:
+; CHECK32-IZDINXZHINXMIN:       # %bb.0:
+; CHECK32-IZDINXZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECK32-IZDINXZHINXMIN-NEXT:    fcvt.w.s a0, a0, rtz
+; CHECK32-IZDINXZHINXMIN-NEXT:    ret
+;
+; CHECK64-IZDINXZHINXMIN-LABEL: fcvt_si_h:
+; CHECK64-IZDINXZHINXMIN:       # %bb.0:
+; CHECK64-IZDINXZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECK64-IZDINXZHINXMIN-NEXT:    fcvt.l.s a0, a0, rtz
+; CHECK64-IZDINXZHINXMIN-NEXT:    ret
   %1 = call i16 @llvm.experimental.constrained.fptosi.i16.f16(half %a, metadata !"fpexcept.strict") strictfp
   ret i16 %1
 }
 declare i16 @llvm.experimental.constrained.fptosi.i16.f16(half, metadata)
 
 define i16 @fcvt_ui_h(half %a) nounwind strictfp {
 ; RV32IZFH-LABEL: fcvt_ui_h:
 ; RV32IZFH:       # %bb.0:
 ; RV32IZFH-NEXT:    fcvt.wu.h a0, fa0, rtz
 ; RV32IZFH-NEXT:    ret
 ;
 ; RV64IZFH-LABEL: fcvt_ui_h:
 ; RV64IZFH:       # %bb.0:
 ; RV64IZFH-NEXT:    fcvt.lu.h a0, fa0, rtz
 ; RV64IZFH-NEXT:    ret
 ;
+; RV32IZHINX-LABEL: fcvt_ui_h:
+; RV32IZHINX:       # %bb.0:
+; RV32IZHINX-NEXT:    fcvt.wu.h a0, a0, rtz
+; RV32IZHINX-NEXT:    ret
+;
+; RV64IZHINX-LABEL: fcvt_ui_h:
+; RV64IZHINX:       # %bb.0:
+; RV64IZHINX-NEXT:    fcvt.lu.h a0, a0, rtz
+; RV64IZHINX-NEXT:    ret
+;
 ; RV32IDZFH-LABEL: fcvt_ui_h:
 ; RV32IDZFH:       # %bb.0:
 ; RV32IDZFH-NEXT:    fcvt.wu.h a0, fa0, rtz
 ; RV32IDZFH-NEXT:    ret
 ;
 ; RV64IDZFH-LABEL: fcvt_ui_h:
 ; RV64IDZFH:       # %bb.0:
 ; RV64IDZFH-NEXT:    fcvt.lu.h a0, fa0, rtz
 ; RV64IDZFH-NEXT:    ret
 ;
+; RV32IZDINXZHINX-LABEL: fcvt_ui_h:
+; RV32IZDINXZHINX:       # %bb.0:
+; RV32IZDINXZHINX-NEXT:    fcvt.wu.h a0, a0, rtz
+; RV32IZDINXZHINX-NEXT:    ret
+;
+; RV64IZDINXZHINX-LABEL: fcvt_ui_h:
+; RV64IZDINXZHINX:       # %bb.0:
+; RV64IZDINXZHINX-NEXT:    fcvt.lu.h a0, a0, rtz
+; RV64IZDINXZHINX-NEXT:    ret
+;
 ; CHECK32-IZFHMIN-LABEL: fcvt_ui_h:
 ; CHECK32-IZFHMIN:       # %bb.0:
 ; CHECK32-IZFHMIN-NEXT:    fcvt.s.h fa5, fa0
 ; CHECK32-IZFHMIN-NEXT:    fcvt.wu.s a0, fa5, rtz
 ; CHECK32-IZFHMIN-NEXT:    ret
 ;
 ; CHECK64-IZFHMIN-LABEL: fcvt_ui_h:
 ; CHECK64-IZFHMIN:       # %bb.0:
 ; CHECK64-IZFHMIN-NEXT:    fcvt.s.h fa5, fa0
 ; CHECK64-IZFHMIN-NEXT:    fcvt.lu.s a0, fa5, rtz
 ; CHECK64-IZFHMIN-NEXT:    ret
+;
+; CHECK32-IZHINXMIN-LABEL: fcvt_ui_h:
+; CHECK32-IZHINXMIN:       # %bb.0:
+; CHECK32-IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECK32-IZHINXMIN-NEXT:    fcvt.wu.s a0, a0, rtz
+; CHECK32-IZHINXMIN-NEXT:    ret
+;
+; CHECK64-IZHINXMIN-LABEL: fcvt_ui_h:
+; CHECK64-IZHINXMIN:       # %bb.0:
+; CHECK64-IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECK64-IZHINXMIN-NEXT:    fcvt.lu.s a0, a0, rtz
+; CHECK64-IZHINXMIN-NEXT:    ret
+;
+; CHECK32-IZDINXZHINXMIN-LABEL: fcvt_ui_h:
+; CHECK32-IZDINXZHINXMIN:       # %bb.0:
+; CHECK32-IZDINXZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECK32-IZDINXZHINXMIN-NEXT:    fcvt.wu.s a0, a0, rtz
+; CHECK32-IZDINXZHINXMIN-NEXT:    ret
+;
+; CHECK64-IZDINXZHINXMIN-LABEL: fcvt_ui_h:
+; CHECK64-IZDINXZHINXMIN:       # %bb.0:
+; CHECK64-IZDINXZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECK64-IZDINXZHINXMIN-NEXT:    fcvt.lu.s a0, a0, rtz
+; CHECK64-IZDINXZHINXMIN-NEXT:    ret
   %1 = call i16 @llvm.experimental.constrained.fptoui.i16.f16(half %a, metadata !"fpexcept.strict") strictfp
   ret i16 %1
 }
 declare i16 @llvm.experimental.constrained.fptoui.i16.f16(half, metadata)
 
 define i32 @fcvt_w_h(half %a) nounwind strictfp {
 ; CHECKIZFH-LABEL: fcvt_w_h:
 ; CHECKIZFH:       # %bb.0:
 ; CHECKIZFH-NEXT:    fcvt.w.h a0, fa0, rtz
 ; CHECKIZFH-NEXT:    ret
 ;
+; CHECKIZHINX-LABEL: fcvt_w_h:
+; CHECKIZHINX:       # %bb.0:
+; CHECKIZHINX-NEXT:    fcvt.w.h a0, a0, rtz
+; CHECKIZHINX-NEXT:    ret
+;
 ; RV32IDZFH-LABEL: fcvt_w_h:
 ; RV32IDZFH:       # %bb.0:
 ; RV32IDZFH-NEXT:    fcvt.w.h a0, fa0, rtz
 ; RV32IDZFH-NEXT:    ret
 ;
 ; RV64IDZFH-LABEL: fcvt_w_h:
 ; RV64IDZFH:       # %bb.0:
 ; RV64IDZFH-NEXT:    fcvt.w.h a0, fa0, rtz
 ; RV64IDZFH-NEXT:    ret
 ;
+; RV32IZDINXZHINX-LABEL: fcvt_w_h:
+; RV32IZDINXZHINX:       # %bb.0:
+; RV32IZDINXZHINX-NEXT:    fcvt.w.h a0, a0, rtz
+; RV32IZDINXZHINX-NEXT:    ret
+;
+; RV64IZDINXZHINX-LABEL: fcvt_w_h:
+; RV64IZDINXZHINX:       # %bb.0:
+; RV64IZDINXZHINX-NEXT:    fcvt.w.h a0, a0, rtz
+; RV64IZDINXZHINX-NEXT:    ret
+;
 ; CHECK32-IZFHMIN-LABEL: fcvt_w_h:
 ; CHECK32-IZFHMIN:       # %bb.0:
 ; CHECK32-IZFHMIN-NEXT:    fcvt.s.h fa5, fa0
 ; CHECK32-IZFHMIN-NEXT:    fcvt.w.s a0, fa5, rtz
 ; CHECK32-IZFHMIN-NEXT:    ret
 ;
 ; CHECK64-IZFHMIN-LABEL: fcvt_w_h:
 ; CHECK64-IZFHMIN:       # %bb.0:
 ; CHECK64-IZFHMIN-NEXT:    fcvt.s.h fa5, fa0
 ; CHECK64-IZFHMIN-NEXT:    fcvt.w.s a0, fa5, rtz
 ; CHECK64-IZFHMIN-NEXT:    ret
+;
+; CHECK32-IZHINXMIN-LABEL: fcvt_w_h:
+; CHECK32-IZHINXMIN:       # %bb.0:
+; CHECK32-IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECK32-IZHINXMIN-NEXT:    fcvt.w.s a0, a0, rtz
+; CHECK32-IZHINXMIN-NEXT:    ret
+;
+; CHECK64-IZHINXMIN-LABEL: fcvt_w_h:
+; CHECK64-IZHINXMIN:       # %bb.0:
+; CHECK64-IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECK64-IZHINXMIN-NEXT:    fcvt.w.s a0, a0, rtz
+; CHECK64-IZHINXMIN-NEXT:    ret
+;
+; CHECK32-IZDINXZHINXMIN-LABEL: fcvt_w_h:
+; CHECK32-IZDINXZHINXMIN:       # %bb.0:
+; CHECK32-IZDINXZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECK32-IZDINXZHINXMIN-NEXT:    fcvt.w.s a0, a0, rtz
+; CHECK32-IZDINXZHINXMIN-NEXT:    ret
+;
+; CHECK64-IZDINXZHINXMIN-LABEL: fcvt_w_h:
+; CHECK64-IZDINXZHINXMIN:       # %bb.0:
+; CHECK64-IZDINXZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECK64-IZDINXZHINXMIN-NEXT:    fcvt.w.s a0, a0, rtz
+; CHECK64-IZDINXZHINXMIN-NEXT:    ret
   %1 = call i32 @llvm.experimental.constrained.fptosi.i32.f16(half %a, metadata !"fpexcept.strict") strictfp
   ret i32 %1
 }
 declare i32 @llvm.experimental.constrained.fptosi.i32.f16(half, metadata)
 
 define i32 @fcvt_wu_h(half %a) nounwind strictfp {
 ; CHECKIZFH-LABEL: fcvt_wu_h:
 ; CHECKIZFH:       # %bb.0:
 ; CHECKIZFH-NEXT:    fcvt.wu.h a0, fa0, rtz
 ; CHECKIZFH-NEXT:    ret
 ;
+; CHECKIZHINX-LABEL: fcvt_wu_h:
+; CHECKIZHINX:       # %bb.0:
+; CHECKIZHINX-NEXT:    fcvt.wu.h a0, a0, rtz
+; CHECKIZHINX-NEXT:    ret
+;
 ; RV32IDZFH-LABEL: fcvt_wu_h:
 ; RV32IDZFH:       # %bb.0:
 ; RV32IDZFH-NEXT:    fcvt.wu.h a0, fa0, rtz
 ; RV32IDZFH-NEXT:    ret
 ;
 ; RV64IDZFH-LABEL: fcvt_wu_h:
 ; RV64IDZFH:       # %bb.0:
 ; RV64IDZFH-NEXT:    fcvt.wu.h a0, fa0, rtz
 ; RV64IDZFH-NEXT:    ret
 ;
+; RV32IZDINXZHINX-LABEL: fcvt_wu_h:
+; RV32IZDINXZHINX:       # %bb.0:
+; RV32IZDINXZHINX-NEXT:    fcvt.wu.h a0, a0, rtz
+; RV32IZDINXZHINX-NEXT:    ret
+;
+; RV64IZDINXZHINX-LABEL: fcvt_wu_h:
+; RV64IZDINXZHINX:       # %bb.0:
+; RV64IZDINXZHINX-NEXT:    fcvt.wu.h a0, a0, rtz
+; RV64IZDINXZHINX-NEXT:    ret
+;
 ; CHECK32-IZFHMIN-LABEL: fcvt_wu_h:
 ; CHECK32-IZFHMIN:       # %bb.0:
 ; CHECK32-IZFHMIN-NEXT:    fcvt.s.h fa5, fa0
 ; CHECK32-IZFHMIN-NEXT:    fcvt.wu.s a0, fa5, rtz
 ; CHECK32-IZFHMIN-NEXT:    ret
 ;
 ; CHECK64-IZFHMIN-LABEL: fcvt_wu_h:
 ; CHECK64-IZFHMIN:       # %bb.0:
 ; CHECK64-IZFHMIN-NEXT:    fcvt.s.h fa5, fa0
 ; CHECK64-IZFHMIN-NEXT:    fcvt.wu.s a0, fa5, rtz
 ; CHECK64-IZFHMIN-NEXT:    ret
+;
+; CHECK32-IZHINXMIN-LABEL: fcvt_wu_h:
+; CHECK32-IZHINXMIN:       # %bb.0:
+; CHECK32-IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECK32-IZHINXMIN-NEXT:    fcvt.wu.s a0, a0, rtz
+; CHECK32-IZHINXMIN-NEXT:    ret
+;
+; CHECK64-IZHINXMIN-LABEL: fcvt_wu_h:
+; CHECK64-IZHINXMIN:       # %bb.0:
+; CHECK64-IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECK64-IZHINXMIN-NEXT:    fcvt.wu.s a0, a0, rtz
+; CHECK64-IZHINXMIN-NEXT:    ret
+;
+; CHECK32-IZDINXZHINXMIN-LABEL: fcvt_wu_h:
+; CHECK32-IZDINXZHINXMIN:       # %bb.0:
+; CHECK32-IZDINXZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECK32-IZDINXZHINXMIN-NEXT:    fcvt.wu.s a0, a0, rtz
+; CHECK32-IZDINXZHINXMIN-NEXT:    ret
+;
+; CHECK64-IZDINXZHINXMIN-LABEL: fcvt_wu_h:
+; CHECK64-IZDINXZHINXMIN:       # %bb.0:
+; CHECK64-IZDINXZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECK64-IZDINXZHINXMIN-NEXT:    fcvt.wu.s a0, a0, rtz
+; CHECK64-IZDINXZHINXMIN-NEXT:    ret
   %1 = call i32 @llvm.experimental.constrained.fptoui.i32.f16(half %a, metadata !"fpexcept.strict") strictfp
   ret i32 %1
 }
 declare i32 @llvm.experimental.constrained.fptoui.i32.f16(half, metadata)
 
 ; Test where the fptoui has multiple uses, one of which causes a sext to be
 ; inserted on RV64.
 ; FIXME: We should not have an fcvt.wu.h and an fcvt.lu.h.
 define i32 @fcvt_wu_h_multiple_use(half %x, ptr %y) {
 ; CHECKIZFH-LABEL: fcvt_wu_h_multiple_use:
 ; CHECKIZFH:       # %bb.0:
 ; CHECKIZFH-NEXT:    fcvt.wu.h a0, fa0, rtz
 ; CHECKIZFH-NEXT:    seqz a1, a0
 ; CHECKIZFH-NEXT:    add a0, a0, a1
 ; CHECKIZFH-NEXT:    ret
 ;
+; CHECKIZHINX-LABEL: fcvt_wu_h_multiple_use:
+; CHECKIZHINX:       # %bb.0:
+; CHECKIZHINX-NEXT:    fcvt.wu.h a0, a0, rtz
+; CHECKIZHINX-NEXT:    seqz a1, a0
+; CHECKIZHINX-NEXT:    add a0, a0, a1
+; CHECKIZHINX-NEXT:    ret
+;
 ; RV32IDZFH-LABEL: fcvt_wu_h_multiple_use:
 ; RV32IDZFH:       # %bb.0:
 ; RV32IDZFH-NEXT:    fcvt.wu.h a0, fa0, rtz
 ; RV32IDZFH-NEXT:    seqz a1, a0
 ; RV32IDZFH-NEXT:    add a0, a0, a1
 ; RV32IDZFH-NEXT:    ret
 ;
 ; RV64IDZFH-LABEL: fcvt_wu_h_multiple_use:
 ; RV64IDZFH:       # %bb.0:
 ; RV64IDZFH-NEXT:    fcvt.wu.h a0, fa0, rtz
 ; RV64IDZFH-NEXT:    seqz a1, a0
 ; RV64IDZFH-NEXT:    add a0, a0, a1
 ; RV64IDZFH-NEXT:    ret
 ;
+; RV32IZDINXZHINX-LABEL: fcvt_wu_h_multiple_use:
+; RV32IZDINXZHINX:       # %bb.0:
+; RV32IZDINXZHINX-NEXT:    fcvt.wu.h a0, a0, rtz
+; RV32IZDINXZHINX-NEXT:    seqz a1, a0
+; RV32IZDINXZHINX-NEXT:    add a0, a0, a1
+; RV32IZDINXZHINX-NEXT:    ret
+;
+; RV64IZDINXZHINX-LABEL: fcvt_wu_h_multiple_use:
+; RV64IZDINXZHINX:       # %bb.0:
+; RV64IZDINXZHINX-NEXT:    fcvt.wu.h a0, a0, rtz
+; RV64IZDINXZHINX-NEXT:    seqz a1, a0
+; RV64IZDINXZHINX-NEXT:    add a0, a0, a1
+; RV64IZDINXZHINX-NEXT:    ret
+;
 ; CHECK32-IZFHMIN-LABEL: fcvt_wu_h_multiple_use:
 ; CHECK32-IZFHMIN:       # %bb.0:
 ; CHECK32-IZFHMIN-NEXT:    fcvt.s.h fa5, fa0
 ; CHECK32-IZFHMIN-NEXT:    fcvt.wu.s a0, fa5, rtz
 ; CHECK32-IZFHMIN-NEXT:    seqz a1, a0
 ; CHECK32-IZFHMIN-NEXT:    add a0, a0, a1
 ; CHECK32-IZFHMIN-NEXT:    ret
 ;
 ; CHECK64-IZFHMIN-LABEL: fcvt_wu_h_multiple_use:
 ; CHECK64-IZFHMIN:       # %bb.0:
 ; CHECK64-IZFHMIN-NEXT:    fcvt.s.h fa5, fa0
 ; CHECK64-IZFHMIN-NEXT:    fcvt.wu.s a0, fa5, rtz
 ; CHECK64-IZFHMIN-NEXT:    seqz a1, a0
 ; CHECK64-IZFHMIN-NEXT:    add a0, a0, a1
 ; CHECK64-IZFHMIN-NEXT:    ret
+;
+; CHECK32-IZHINXMIN-LABEL: fcvt_wu_h_multiple_use:
+; CHECK32-IZHINXMIN:       # %bb.0:
+; CHECK32-IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECK32-IZHINXMIN-NEXT:    fcvt.wu.s a0, a0, rtz
+; CHECK32-IZHINXMIN-NEXT:    seqz a1, a0
+; CHECK32-IZHINXMIN-NEXT:    add a0, a0, a1
+; CHECK32-IZHINXMIN-NEXT:    ret
+;
+; CHECK64-IZHINXMIN-LABEL: fcvt_wu_h_multiple_use:
+; CHECK64-IZHINXMIN:       # %bb.0:
+; CHECK64-IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECK64-IZHINXMIN-NEXT:    fcvt.wu.s a0, a0, rtz
+; CHECK64-IZHINXMIN-NEXT:    seqz a1, a0
+; CHECK64-IZHINXMIN-NEXT:    add a0, a0, a1
+; CHECK64-IZHINXMIN-NEXT:    ret
+;
+; CHECK32-IZDINXZHINXMIN-LABEL: fcvt_wu_h_multiple_use:
+; CHECK32-IZDINXZHINXMIN:       # %bb.0:
+; CHECK32-IZDINXZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECK32-IZDINXZHINXMIN-NEXT:    fcvt.wu.s a0, a0, rtz
+; CHECK32-IZDINXZHINXMIN-NEXT:    seqz a1, a0
+; CHECK32-IZDINXZHINXMIN-NEXT:    add a0, a0, a1
+; CHECK32-IZDINXZHINXMIN-NEXT:    ret
+;
+; CHECK64-IZDINXZHINXMIN-LABEL: fcvt_wu_h_multiple_use:
+; CHECK64-IZDINXZHINXMIN:       # %bb.0:
+; CHECK64-IZDINXZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECK64-IZDINXZHINXMIN-NEXT:    fcvt.wu.s a0, a0, rtz
+; CHECK64-IZDINXZHINXMIN-NEXT:    seqz a1, a0
+; CHECK64-IZDINXZHINXMIN-NEXT:    add a0, a0, a1
+; CHECK64-IZDINXZHINXMIN-NEXT:    ret
   %a = call i32 @llvm.experimental.constrained.fptoui.i32.f16(half %x, metadata !"fpexcept.strict") strictfp
   %b = icmp eq i32 %a, 0
   %c = select i1 %b, i32 1, i32 %a
   ret i32 %c
 }
 
 define i64 @fcvt_l_h(half %a) nounwind strictfp {
 ; RV32IZFH-LABEL: fcvt_l_h:
 ; RV32IZFH:       # %bb.0:
 ; RV32IZFH-NEXT:    addi sp, sp, -16
 ; RV32IZFH-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32IZFH-NEXT:    call __fixhfdi@plt
 ; RV32IZFH-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32IZFH-NEXT:    addi sp, sp, 16
 ; RV32IZFH-NEXT:    ret
 ;
 ; RV64IZFH-LABEL: fcvt_l_h:
 ; RV64IZFH:       # %bb.0:
 ; RV64IZFH-NEXT:    fcvt.l.h a0, fa0, rtz
 ; RV64IZFH-NEXT:    ret
 ;
+; RV32IZHINX-LABEL: fcvt_l_h:
+; RV32IZHINX:       # %bb.0:
+; RV32IZHINX-NEXT:    addi sp, sp, -16
+; RV32IZHINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZHINX-NEXT:    call __fixhfdi@plt
+; RV32IZHINX-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZHINX-NEXT:    addi sp, sp, 16
+; RV32IZHINX-NEXT:    ret
+;
+; RV64IZHINX-LABEL: fcvt_l_h:
+; RV64IZHINX:       # %bb.0:
+; RV64IZHINX-NEXT:    fcvt.l.h a0, a0, rtz
+; RV64IZHINX-NEXT:    ret
+;
 ; RV32IDZFH-LABEL: fcvt_l_h:
 ; RV32IDZFH:       # %bb.0:
 ; RV32IDZFH-NEXT:    addi sp, sp, -16
 ; RV32IDZFH-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32IDZFH-NEXT:    call __fixhfdi@plt
 ; RV32IDZFH-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32IDZFH-NEXT:    addi sp, sp, 16
 ; RV32IDZFH-NEXT:    ret
 ;
 ; RV64IDZFH-LABEL: fcvt_l_h:
 ; RV64IDZFH:       # %bb.0:
 ; RV64IDZFH-NEXT:    fcvt.l.h a0, fa0, rtz
 ; RV64IDZFH-NEXT:    ret
 ;
+; RV32IZDINXZHINX-LABEL: fcvt_l_h:
+; RV32IZDINXZHINX:       # %bb.0:
+; RV32IZDINXZHINX-NEXT:    addi sp, sp, -16
+; RV32IZDINXZHINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZDINXZHINX-NEXT:    call __fixhfdi@plt
+; RV32IZDINXZHINX-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZDINXZHINX-NEXT:    addi sp, sp, 16
+; RV32IZDINXZHINX-NEXT:    ret
+;
+; RV64IZDINXZHINX-LABEL: fcvt_l_h:
+; RV64IZDINXZHINX:       # %bb.0:
+; RV64IZDINXZHINX-NEXT:    fcvt.l.h a0, a0, rtz
+; RV64IZDINXZHINX-NEXT:    ret
+;
 ; CHECK32-IZFHMIN-LABEL: fcvt_l_h:
 ; CHECK32-IZFHMIN:       # %bb.0:
 ; CHECK32-IZFHMIN-NEXT:    addi sp, sp, -16
 ; CHECK32-IZFHMIN-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; CHECK32-IZFHMIN-NEXT:    call __fixhfdi@plt
 ; CHECK32-IZFHMIN-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; CHECK32-IZFHMIN-NEXT:    addi sp, sp, 16
 ; CHECK32-IZFHMIN-NEXT:    ret
 ;
 ; CHECK64-IZFHMIN-LABEL: fcvt_l_h:
 ; CHECK64-IZFHMIN:       # %bb.0:
 ; CHECK64-IZFHMIN-NEXT:    fcvt.s.h fa5, fa0
 ; CHECK64-IZFHMIN-NEXT:    fcvt.l.s a0, fa5, rtz
 ; CHECK64-IZFHMIN-NEXT:    ret
+;
+; CHECK32-IZHINXMIN-LABEL: fcvt_l_h:
+; CHECK32-IZHINXMIN:       # %bb.0:
+; CHECK32-IZHINXMIN-NEXT:    addi sp, sp, -16
+; CHECK32-IZHINXMIN-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; CHECK32-IZHINXMIN-NEXT:    call __fixhfdi@plt
+; CHECK32-IZHINXMIN-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; CHECK32-IZHINXMIN-NEXT:    addi sp, sp, 16
+; CHECK32-IZHINXMIN-NEXT:    ret
+;
+; CHECK64-IZHINXMIN-LABEL: fcvt_l_h:
+; CHECK64-IZHINXMIN:       # %bb.0:
+; CHECK64-IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECK64-IZHINXMIN-NEXT:    fcvt.l.s a0, a0, rtz
+; CHECK64-IZHINXMIN-NEXT:    ret
+;
+; CHECK32-IZDINXZHINXMIN-LABEL: fcvt_l_h:
+; CHECK32-IZDINXZHINXMIN:       # %bb.0:
+; CHECK32-IZDINXZHINXMIN-NEXT:    addi sp, sp, -16
+; CHECK32-IZDINXZHINXMIN-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; CHECK32-IZDINXZHINXMIN-NEXT:    call __fixhfdi@plt
+; CHECK32-IZDINXZHINXMIN-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; CHECK32-IZDINXZHINXMIN-NEXT:    addi sp, sp, 16
+; CHECK32-IZDINXZHINXMIN-NEXT:    ret
+;
+; CHECK64-IZDINXZHINXMIN-LABEL: fcvt_l_h:
+; CHECK64-IZDINXZHINXMIN:       # %bb.0:
+; CHECK64-IZDINXZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECK64-IZDINXZHINXMIN-NEXT:    fcvt.l.s a0, a0, rtz
+; CHECK64-IZDINXZHINXMIN-NEXT:    ret
   %1 = call i64 @llvm.experimental.constrained.fptosi.i64.f16(half %a, metadata !"fpexcept.strict") strictfp
   ret i64 %1
 }
 declare i64 @llvm.experimental.constrained.fptosi.i64.f16(half, metadata)
 
 define i64 @fcvt_lu_h(half %a) nounwind strictfp {
 ; RV32IZFH-LABEL: fcvt_lu_h:
 ; RV32IZFH:       # %bb.0:
 ; RV32IZFH-NEXT:    addi sp, sp, -16
 ; RV32IZFH-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32IZFH-NEXT:    call __fixunshfdi@plt
 ; RV32IZFH-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32IZFH-NEXT:    addi sp, sp, 16
 ; RV32IZFH-NEXT:    ret
 ;
 ; RV64IZFH-LABEL: fcvt_lu_h:
 ; RV64IZFH:       # %bb.0:
 ; RV64IZFH-NEXT:    fcvt.lu.h a0, fa0, rtz
 ; RV64IZFH-NEXT:    ret
 ;
+; RV32IZHINX-LABEL: fcvt_lu_h:
+; RV32IZHINX:       # %bb.0:
+; RV32IZHINX-NEXT:    addi sp, sp, -16
+; RV32IZHINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZHINX-NEXT:    call __fixunshfdi@plt
+; RV32IZHINX-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZHINX-NEXT:    addi sp, sp, 16
+; RV32IZHINX-NEXT:    ret
+;
+; RV64IZHINX-LABEL: fcvt_lu_h:
+; RV64IZHINX:       # %bb.0:
+; RV64IZHINX-NEXT:    fcvt.lu.h a0, a0, rtz
+; RV64IZHINX-NEXT:    ret
+;
 ; RV32IDZFH-LABEL: fcvt_lu_h:
 ; RV32IDZFH:       # %bb.0:
 ; RV32IDZFH-NEXT:    addi sp, sp, -16
 ; RV32IDZFH-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32IDZFH-NEXT:    call __fixunshfdi@plt
 ; RV32IDZFH-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32IDZFH-NEXT:    addi sp, sp, 16
 ; RV32IDZFH-NEXT:    ret
 ;
 ; RV64IDZFH-LABEL: fcvt_lu_h:
 ; RV64IDZFH:       # %bb.0:
 ; RV64IDZFH-NEXT:    fcvt.lu.h a0, fa0, rtz
 ; RV64IDZFH-NEXT:    ret
 ;
+; RV32IZDINXZHINX-LABEL: fcvt_lu_h:
+; RV32IZDINXZHINX:       # %bb.0:
+; RV32IZDINXZHINX-NEXT:    addi sp, sp, -16
+; RV32IZDINXZHINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZDINXZHINX-NEXT:    call __fixunshfdi@plt
+; RV32IZDINXZHINX-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZDINXZHINX-NEXT:    addi sp, sp, 16
+; RV32IZDINXZHINX-NEXT:    ret
+;
+; RV64IZDINXZHINX-LABEL: fcvt_lu_h:
+; RV64IZDINXZHINX:       # %bb.0:
+; RV64IZDINXZHINX-NEXT:    fcvt.lu.h a0, a0, rtz
+; RV64IZDINXZHINX-NEXT:    ret
+;
 ; CHECK32-IZFHMIN-LABEL: fcvt_lu_h:
 ; CHECK32-IZFHMIN:       # %bb.0:
 ; CHECK32-IZFHMIN-NEXT:    addi sp, sp, -16
 ; CHECK32-IZFHMIN-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; CHECK32-IZFHMIN-NEXT:    call __fixunshfdi@plt
 ; CHECK32-IZFHMIN-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; CHECK32-IZFHMIN-NEXT:    addi sp, sp, 16
 ; CHECK32-IZFHMIN-NEXT:    ret
 ;
 ; CHECK64-IZFHMIN-LABEL: fcvt_lu_h:
 ; CHECK64-IZFHMIN:       # %bb.0:
 ; CHECK64-IZFHMIN-NEXT:    fcvt.s.h fa5, fa0
 ; CHECK64-IZFHMIN-NEXT:    fcvt.lu.s a0, fa5, rtz
 ; CHECK64-IZFHMIN-NEXT:    ret
+;
+; CHECK32-IZHINXMIN-LABEL: fcvt_lu_h:
+; CHECK32-IZHINXMIN:       # %bb.0:
+; CHECK32-IZHINXMIN-NEXT:    addi sp, sp, -16
+; CHECK32-IZHINXMIN-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; CHECK32-IZHINXMIN-NEXT:    call __fixunshfdi@plt
+; CHECK32-IZHINXMIN-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; CHECK32-IZHINXMIN-NEXT:    addi sp, sp, 16
+; CHECK32-IZHINXMIN-NEXT:    ret
+;
+; CHECK64-IZHINXMIN-LABEL: fcvt_lu_h:
+; CHECK64-IZHINXMIN:       # %bb.0:
+; CHECK64-IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECK64-IZHINXMIN-NEXT:    fcvt.lu.s a0, a0, rtz
+; CHECK64-IZHINXMIN-NEXT:    ret
+;
+; CHECK32-IZDINXZHINXMIN-LABEL: fcvt_lu_h:
+; CHECK32-IZDINXZHINXMIN:       # %bb.0:
+; CHECK32-IZDINXZHINXMIN-NEXT:    addi sp, sp, -16
+; CHECK32-IZDINXZHINXMIN-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; CHECK32-IZDINXZHINXMIN-NEXT:    call __fixunshfdi@plt
+; CHECK32-IZDINXZHINXMIN-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; CHECK32-IZDINXZHINXMIN-NEXT:    addi sp, sp, 16
+; CHECK32-IZDINXZHINXMIN-NEXT:    ret
+;
+; CHECK64-IZDINXZHINXMIN-LABEL: fcvt_lu_h:
+; CHECK64-IZDINXZHINXMIN:       # %bb.0:
+; CHECK64-IZDINXZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECK64-IZDINXZHINXMIN-NEXT:    fcvt.lu.s a0, a0, rtz
+; CHECK64-IZDINXZHINXMIN-NEXT:    ret
   %1 = call i64 @llvm.experimental.constrained.fptoui.i64.f16(half %a, metadata !"fpexcept.strict") strictfp
   ret i64 %1
 }
 declare i64 @llvm.experimental.constrained.fptoui.i64.f16(half, metadata)
 
 define half @fcvt_h_si(i16 %a) nounwind strictfp {
 ; RV32IZFH-LABEL: fcvt_h_si:
 ; RV32IZFH:       # %bb.0:
 ; RV32IZFH-NEXT:    slli a0, a0, 16
 ; RV32IZFH-NEXT:    srai a0, a0, 16
 ; RV32IZFH-NEXT:    fcvt.h.w fa0, a0
 ; RV32IZFH-NEXT:    ret
 ;
 ; RV64IZFH-LABEL: fcvt_h_si:
 ; RV64IZFH:       # %bb.0:
 ; RV64IZFH-NEXT:    slli a0, a0, 48
 ; RV64IZFH-NEXT:    srai a0, a0, 48
 ; RV64IZFH-NEXT:    fcvt.h.w fa0, a0
 ; RV64IZFH-NEXT:    ret
 ;
+; RV32IZHINX-LABEL: fcvt_h_si:
+; RV32IZHINX:       # %bb.0:
+; RV32IZHINX-NEXT:    slli a0, a0, 16
+; RV32IZHINX-NEXT:    srai a0, a0, 16
+; RV32IZHINX-NEXT:    fcvt.h.w a0, a0
+; RV32IZHINX-NEXT:    ret
+;
+; RV64IZHINX-LABEL: fcvt_h_si:
+; RV64IZHINX:       # %bb.0:
+; RV64IZHINX-NEXT:    slli a0, a0, 48
+; RV64IZHINX-NEXT:    srai a0, a0, 48
+; RV64IZHINX-NEXT:    fcvt.h.w a0, a0
+; RV64IZHINX-NEXT:    ret
+;
 ; RV32IDZFH-LABEL: fcvt_h_si:
 ; RV32IDZFH:       # %bb.0:
 ; RV32IDZFH-NEXT:    slli a0, a0, 16
 ; RV32IDZFH-NEXT:    srai a0, a0, 16
 ; RV32IDZFH-NEXT:    fcvt.h.w fa0, a0
 ; RV32IDZFH-NEXT:    ret
 ;
 ; RV64IDZFH-LABEL: fcvt_h_si:
 ; RV64IDZFH:       # %bb.0:
 ; RV64IDZFH-NEXT:    slli a0, a0, 48
 ; RV64IDZFH-NEXT:    srai a0, a0, 48
 ; RV64IDZFH-NEXT:    fcvt.h.w fa0, a0
 ; RV64IDZFH-NEXT:    ret
 ;
+; RV32IZDINXZHINX-LABEL: fcvt_h_si:
+; RV32IZDINXZHINX:       # %bb.0:
+; RV32IZDINXZHINX-NEXT:    slli a0, a0, 16
+; RV32IZDINXZHINX-NEXT:    srai a0, a0, 16
+; RV32IZDINXZHINX-NEXT:    fcvt.h.w a0, a0
+; RV32IZDINXZHINX-NEXT:    ret
+;
+; RV64IZDINXZHINX-LABEL: fcvt_h_si:
+; RV64IZDINXZHINX:       # %bb.0:
+; RV64IZDINXZHINX-NEXT:    slli a0, a0, 48
+; RV64IZDINXZHINX-NEXT:    srai a0, a0, 48
+; RV64IZDINXZHINX-NEXT:    fcvt.h.w a0, a0
+; RV64IZDINXZHINX-NEXT:    ret
+;
 ; CHECK32-IZFHMIN-LABEL: fcvt_h_si:
 ; CHECK32-IZFHMIN:       # %bb.0:
 ; CHECK32-IZFHMIN-NEXT:    slli a0, a0, 16
 ; CHECK32-IZFHMIN-NEXT:    srai a0, a0, 16
 ; CHECK32-IZFHMIN-NEXT:    fcvt.s.w fa5, a0
 ; CHECK32-IZFHMIN-NEXT:    fcvt.h.s fa0, fa5
 ; CHECK32-IZFHMIN-NEXT:    ret
 ;
 ; CHECK64-IZFHMIN-LABEL: fcvt_h_si:
 ; CHECK64-IZFHMIN:       # %bb.0:
 ; CHECK64-IZFHMIN-NEXT:    slli a0, a0, 48
 ; CHECK64-IZFHMIN-NEXT:    srai a0, a0, 48
 ; CHECK64-IZFHMIN-NEXT:    fcvt.s.l fa5, a0
 ; CHECK64-IZFHMIN-NEXT:    fcvt.h.s fa0, fa5
 ; CHECK64-IZFHMIN-NEXT:    ret
+;
+; CHECK32-IZHINXMIN-LABEL: fcvt_h_si:
+; CHECK32-IZHINXMIN:       # %bb.0:
+; CHECK32-IZHINXMIN-NEXT:    slli a0, a0, 16
+; CHECK32-IZHINXMIN-NEXT:    srai a0, a0, 16
+; CHECK32-IZHINXMIN-NEXT:    fcvt.s.w a0, a0
+; CHECK32-IZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; CHECK32-IZHINXMIN-NEXT:    ret
+;
+; CHECK64-IZHINXMIN-LABEL: fcvt_h_si:
+; CHECK64-IZHINXMIN:       # %bb.0:
+; CHECK64-IZHINXMIN-NEXT:    slli a0, a0, 48
+; CHECK64-IZHINXMIN-NEXT:    srai a0, a0, 48
+; CHECK64-IZHINXMIN-NEXT:    fcvt.s.l a0, a0
+; CHECK64-IZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; CHECK64-IZHINXMIN-NEXT:    ret
+;
+; CHECK32-IZDINXZHINXMIN-LABEL: fcvt_h_si:
+; CHECK32-IZDINXZHINXMIN:       # %bb.0:
+; CHECK32-IZDINXZHINXMIN-NEXT:    slli a0, a0, 16
+; CHECK32-IZDINXZHINXMIN-NEXT:    srai a0, a0, 16
+; CHECK32-IZDINXZHINXMIN-NEXT:    fcvt.s.w a0, a0
+; CHECK32-IZDINXZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; CHECK32-IZDINXZHINXMIN-NEXT:    ret
+;
+; CHECK64-IZDINXZHINXMIN-LABEL: fcvt_h_si:
+; CHECK64-IZDINXZHINXMIN:       # %bb.0:
+; CHECK64-IZDINXZHINXMIN-NEXT:    slli a0, a0, 48
+; CHECK64-IZDINXZHINXMIN-NEXT:    srai a0, a0, 48
+; CHECK64-IZDINXZHINXMIN-NEXT:    fcvt.s.l a0, a0
+; CHECK64-IZDINXZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; CHECK64-IZDINXZHINXMIN-NEXT:    ret
   %1 = call half @llvm.experimental.constrained.sitofp.f16.i16(i16 %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
   ret half %1
 }
 declare half @llvm.experimental.constrained.sitofp.f16.i16(i16, metadata, metadata)
 
 define half @fcvt_h_si_signext(i16 signext %a) nounwind strictfp {
 ; CHECKIZFH-LABEL: fcvt_h_si_signext:
 ; CHECKIZFH:       # %bb.0:
 ; CHECKIZFH-NEXT:    fcvt.h.w fa0, a0
 ; CHECKIZFH-NEXT:    ret
 ;
+; CHECKIZHINX-LABEL: fcvt_h_si_signext:
+; CHECKIZHINX:       # %bb.0:
+; CHECKIZHINX-NEXT:    fcvt.h.w a0, a0
+; CHECKIZHINX-NEXT:    ret
+;
 ; RV32IDZFH-LABEL: fcvt_h_si_signext:
 ; RV32IDZFH:       # %bb.0:
 ; RV32IDZFH-NEXT:    fcvt.h.w fa0, a0
 ; RV32IDZFH-NEXT:    ret
 ;
 ; RV64IDZFH-LABEL: fcvt_h_si_signext:
 ; RV64IDZFH:       # %bb.0:
 ; RV64IDZFH-NEXT:    fcvt.h.w fa0, a0
 ; RV64IDZFH-NEXT:    ret
 ;
+; RV32IZDINXZHINX-LABEL: fcvt_h_si_signext:
+; RV32IZDINXZHINX:       # %bb.0:
+; RV32IZDINXZHINX-NEXT:    fcvt.h.w a0, a0
+; RV32IZDINXZHINX-NEXT:    ret
+;
+; RV64IZDINXZHINX-LABEL: fcvt_h_si_signext:
+; RV64IZDINXZHINX:       # %bb.0:
+; RV64IZDINXZHINX-NEXT:    fcvt.h.w a0, a0
+; RV64IZDINXZHINX-NEXT:    ret
+;
 ; CHECK32-IZFHMIN-LABEL: fcvt_h_si_signext:
 ; CHECK32-IZFHMIN:       # %bb.0:
 ; CHECK32-IZFHMIN-NEXT:    fcvt.s.w fa5, a0
 ; CHECK32-IZFHMIN-NEXT:    fcvt.h.s fa0, fa5
 ; CHECK32-IZFHMIN-NEXT:    ret
 ;
 ; CHECK64-IZFHMIN-LABEL: fcvt_h_si_signext:
 ; CHECK64-IZFHMIN:       # %bb.0:
 ; CHECK64-IZFHMIN-NEXT:    fcvt.s.l fa5, a0
 ; CHECK64-IZFHMIN-NEXT:    fcvt.h.s fa0, fa5
 ; CHECK64-IZFHMIN-NEXT:    ret
+;
+; CHECK32-IZHINXMIN-LABEL: fcvt_h_si_signext:
+; CHECK32-IZHINXMIN:       # %bb.0:
+; CHECK32-IZHINXMIN-NEXT:    fcvt.s.w a0, a0
+; CHECK32-IZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; CHECK32-IZHINXMIN-NEXT:    ret
+;
+; CHECK64-IZHINXMIN-LABEL: fcvt_h_si_signext:
+; CHECK64-IZHINXMIN:       # %bb.0:
+; CHECK64-IZHINXMIN-NEXT:    fcvt.s.l a0, a0
+; CHECK64-IZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; CHECK64-IZHINXMIN-NEXT:    ret
+;
+; CHECK32-IZDINXZHINXMIN-LABEL: fcvt_h_si_signext:
+; CHECK32-IZDINXZHINXMIN:       # %bb.0:
+; CHECK32-IZDINXZHINXMIN-NEXT:    fcvt.s.w a0, a0
+; CHECK32-IZDINXZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; CHECK32-IZDINXZHINXMIN-NEXT:    ret
+;
+; CHECK64-IZDINXZHINXMIN-LABEL: fcvt_h_si_signext:
+; CHECK64-IZDINXZHINXMIN:       # %bb.0:
+; CHECK64-IZDINXZHINXMIN-NEXT:    fcvt.s.l a0, a0
+; CHECK64-IZDINXZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; CHECK64-IZDINXZHINXMIN-NEXT:    ret
   %1 = call half @llvm.experimental.constrained.sitofp.f16.i16(i16 %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
   ret half %1
 }
 
 define half @fcvt_h_ui(i16 %a) nounwind strictfp {
 ; RV32IZFH-LABEL: fcvt_h_ui:
 ; RV32IZFH:       # %bb.0:
 ; RV32IZFH-NEXT:    slli a0, a0, 16
 ; RV32IZFH-NEXT:    srli a0, a0, 16
 ; RV32IZFH-NEXT:    fcvt.h.wu fa0, a0
 ; RV32IZFH-NEXT:    ret
 ;
 ; RV64IZFH-LABEL: fcvt_h_ui:
 ; RV64IZFH:       # %bb.0:
 ; RV64IZFH-NEXT:    slli a0, a0, 48
 ; RV64IZFH-NEXT:    srli a0, a0, 48
 ; RV64IZFH-NEXT:    fcvt.h.wu fa0, a0
 ; RV64IZFH-NEXT:    ret
 ;
+; RV32IZHINX-LABEL: fcvt_h_ui:
+; RV32IZHINX:       # %bb.0:
+; RV32IZHINX-NEXT:    slli a0, a0, 16
+; RV32IZHINX-NEXT:    srli a0, a0, 16
+; RV32IZHINX-NEXT:    fcvt.h.wu a0, a0
+; RV32IZHINX-NEXT:    ret
+;
+; RV64IZHINX-LABEL: fcvt_h_ui:
+; RV64IZHINX:       # %bb.0:
+; RV64IZHINX-NEXT:    slli a0, a0, 48
+; RV64IZHINX-NEXT:    srli a0, a0, 48
+; RV64IZHINX-NEXT:    fcvt.h.wu a0, a0
+; RV64IZHINX-NEXT:    ret
+;
 ; RV32IDZFH-LABEL: fcvt_h_ui:
 ; RV32IDZFH:       # %bb.0:
 ; RV32IDZFH-NEXT:    slli a0, a0, 16
 ; RV32IDZFH-NEXT:    srli a0, a0, 16
 ; RV32IDZFH-NEXT:    fcvt.h.wu fa0, a0
 ; RV32IDZFH-NEXT:    ret
 ;
 ; RV64IDZFH-LABEL: fcvt_h_ui:
 ; RV64IDZFH:       # %bb.0:
 ; RV64IDZFH-NEXT:    slli a0, a0, 48
 ; RV64IDZFH-NEXT:    srli a0, a0, 48
 ; RV64IDZFH-NEXT:    fcvt.h.wu fa0, a0
 ; RV64IDZFH-NEXT:    ret
 ;
+; RV32IZDINXZHINX-LABEL: fcvt_h_ui:
+; RV32IZDINXZHINX:       # %bb.0:
+; RV32IZDINXZHINX-NEXT:    slli a0, a0, 16
+; RV32IZDINXZHINX-NEXT:    srli a0, a0, 16
+; RV32IZDINXZHINX-NEXT:    fcvt.h.wu a0, a0
+; RV32IZDINXZHINX-NEXT:    ret
+;
+; RV64IZDINXZHINX-LABEL: fcvt_h_ui:
+; RV64IZDINXZHINX:       # %bb.0:
+; RV64IZDINXZHINX-NEXT:    slli a0, a0, 48
+; RV64IZDINXZHINX-NEXT:    srli a0, a0, 48
+; RV64IZDINXZHINX-NEXT:    fcvt.h.wu a0, a0
+; RV64IZDINXZHINX-NEXT:    ret
+;
 ; CHECK32-IZFHMIN-LABEL: fcvt_h_ui:
 ; CHECK32-IZFHMIN:       # %bb.0:
 ; CHECK32-IZFHMIN-NEXT:    slli a0, a0, 16
 ; CHECK32-IZFHMIN-NEXT:    srli a0, a0, 16
 ; CHECK32-IZFHMIN-NEXT:    fcvt.s.wu fa5, a0
 ; CHECK32-IZFHMIN-NEXT:    fcvt.h.s fa0, fa5
 ; CHECK32-IZFHMIN-NEXT:    ret
 ;
 ; CHECK64-IZFHMIN-LABEL: fcvt_h_ui:
 ; CHECK64-IZFHMIN:       # %bb.0:
 ; CHECK64-IZFHMIN-NEXT:    slli a0, a0, 48
 ; CHECK64-IZFHMIN-NEXT:    srli a0, a0, 48
 ; CHECK64-IZFHMIN-NEXT:    fcvt.s.lu fa5, a0
 ; CHECK64-IZFHMIN-NEXT:    fcvt.h.s fa0, fa5
 ; CHECK64-IZFHMIN-NEXT:    ret
+;
+; CHECK32-IZHINXMIN-LABEL: fcvt_h_ui:
+; CHECK32-IZHINXMIN:       # %bb.0:
+; CHECK32-IZHINXMIN-NEXT:    slli a0, a0, 16
+; CHECK32-IZHINXMIN-NEXT:    srli a0, a0, 16
+; CHECK32-IZHINXMIN-NEXT:    fcvt.s.wu a0, a0
+; CHECK32-IZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; CHECK32-IZHINXMIN-NEXT:    ret
+;
+; CHECK64-IZHINXMIN-LABEL: fcvt_h_ui:
+; CHECK64-IZHINXMIN:       # %bb.0:
+; CHECK64-IZHINXMIN-NEXT:    slli a0, a0, 48
+; CHECK64-IZHINXMIN-NEXT:    srli a0, a0, 48
+; CHECK64-IZHINXMIN-NEXT:    fcvt.s.lu a0, a0
+; CHECK64-IZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; CHECK64-IZHINXMIN-NEXT:    ret
+;
+; CHECK32-IZDINXZHINXMIN-LABEL: fcvt_h_ui:
+; CHECK32-IZDINXZHINXMIN:       # %bb.0:
+; CHECK32-IZDINXZHINXMIN-NEXT:    slli a0, a0, 16
+; CHECK32-IZDINXZHINXMIN-NEXT:    srli a0, a0, 16
+; CHECK32-IZDINXZHINXMIN-NEXT:    fcvt.s.wu a0, a0
+; CHECK32-IZDINXZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; CHECK32-IZDINXZHINXMIN-NEXT:    ret
+;
+; CHECK64-IZDINXZHINXMIN-LABEL: fcvt_h_ui:
+; CHECK64-IZDINXZHINXMIN:       # %bb.0:
+; CHECK64-IZDINXZHINXMIN-NEXT:    slli a0, a0, 48
+; CHECK64-IZDINXZHINXMIN-NEXT:    srli a0, a0, 48
+; CHECK64-IZDINXZHINXMIN-NEXT:    fcvt.s.lu a0, a0
+; CHECK64-IZDINXZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; CHECK64-IZDINXZHINXMIN-NEXT:    ret
   %1 = call half @llvm.experimental.constrained.uitofp.f16.i16(i16 %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
   ret half %1
 }
 declare half @llvm.experimental.constrained.uitofp.f16.i16(i16, metadata, metadata)
 
 define half @fcvt_h_ui_zeroext(i16 zeroext %a) nounwind strictfp {
 ; CHECKIZFH-LABEL: fcvt_h_ui_zeroext:
 ; CHECKIZFH:       # %bb.0:
 ; CHECKIZFH-NEXT:    fcvt.h.wu fa0, a0
 ; CHECKIZFH-NEXT:    ret
 ;
+; CHECKIZHINX-LABEL: fcvt_h_ui_zeroext:
+; CHECKIZHINX:       # %bb.0:
+; CHECKIZHINX-NEXT:    fcvt.h.wu a0, a0
+; CHECKIZHINX-NEXT:    ret
+;
 ; RV32IDZFH-LABEL: fcvt_h_ui_zeroext:
 ; RV32IDZFH:       # %bb.0:
 ; RV32IDZFH-NEXT:    fcvt.h.wu fa0, a0
 ; RV32IDZFH-NEXT:    ret
 ;
 ; RV64IDZFH-LABEL: fcvt_h_ui_zeroext:
 ; RV64IDZFH:       # %bb.0:
 ; RV64IDZFH-NEXT:    fcvt.h.wu fa0, a0
 ; RV64IDZFH-NEXT:    ret
 ;
+; RV32IZDINXZHINX-LABEL: fcvt_h_ui_zeroext:
+; RV32IZDINXZHINX:       # %bb.0:
+; RV32IZDINXZHINX-NEXT:    fcvt.h.wu a0, a0
+; RV32IZDINXZHINX-NEXT:    ret
+;
+; RV64IZDINXZHINX-LABEL: fcvt_h_ui_zeroext:
+; RV64IZDINXZHINX:       # %bb.0:
+; RV64IZDINXZHINX-NEXT:    fcvt.h.wu a0, a0
+; RV64IZDINXZHINX-NEXT:    ret
+;
 ; CHECK32-IZFHMIN-LABEL: fcvt_h_ui_zeroext:
 ; CHECK32-IZFHMIN:       # %bb.0:
 ; CHECK32-IZFHMIN-NEXT:    fcvt.s.wu fa5, a0
 ; CHECK32-IZFHMIN-NEXT:    fcvt.h.s fa0, fa5
 ; CHECK32-IZFHMIN-NEXT:    ret
 ;
 ; CHECK64-IZFHMIN-LABEL: fcvt_h_ui_zeroext:
 ; CHECK64-IZFHMIN:       # %bb.0:
 ; CHECK64-IZFHMIN-NEXT:    fcvt.s.lu fa5, a0
 ; CHECK64-IZFHMIN-NEXT:    fcvt.h.s fa0, fa5
 ; CHECK64-IZFHMIN-NEXT:    ret
+;
+; CHECK32-IZHINXMIN-LABEL: fcvt_h_ui_zeroext:
+; CHECK32-IZHINXMIN:       # %bb.0:
+; CHECK32-IZHINXMIN-NEXT:    fcvt.s.wu a0, a0
+; CHECK32-IZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; CHECK32-IZHINXMIN-NEXT:    ret
+;
+; CHECK64-IZHINXMIN-LABEL: fcvt_h_ui_zeroext:
+; CHECK64-IZHINXMIN:       # %bb.0:
+; CHECK64-IZHINXMIN-NEXT:    fcvt.s.lu a0, a0
+; CHECK64-IZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; CHECK64-IZHINXMIN-NEXT:    ret
+;
+; CHECK32-IZDINXZHINXMIN-LABEL: fcvt_h_ui_zeroext:
+; CHECK32-IZDINXZHINXMIN:       # %bb.0:
+; CHECK32-IZDINXZHINXMIN-NEXT:    fcvt.s.wu a0, a0
+; CHECK32-IZDINXZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; CHECK32-IZDINXZHINXMIN-NEXT:    ret
+;
+; CHECK64-IZDINXZHINXMIN-LABEL: fcvt_h_ui_zeroext:
+; CHECK64-IZDINXZHINXMIN:       # %bb.0:
+; CHECK64-IZDINXZHINXMIN-NEXT:    fcvt.s.lu a0, a0
+; CHECK64-IZDINXZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; CHECK64-IZDINXZHINXMIN-NEXT:    ret
   %1 = call half @llvm.experimental.constrained.uitofp.f16.i16(i16 %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
   ret half %1
 }
 
 define half @fcvt_h_w(i32 %a) nounwind strictfp {
 ; CHECKIZFH-LABEL: fcvt_h_w:
 ; CHECKIZFH:       # %bb.0:
 ; CHECKIZFH-NEXT:    fcvt.h.w fa0, a0
 ; CHECKIZFH-NEXT:    ret
 ;
+; CHECKIZHINX-LABEL: fcvt_h_w:
+; CHECKIZHINX:       # %bb.0:
+; CHECKIZHINX-NEXT:    fcvt.h.w a0, a0
+; CHECKIZHINX-NEXT:    ret
+;
 ; RV32IDZFH-LABEL: fcvt_h_w:
 ; RV32IDZFH:       # %bb.0:
 ; RV32IDZFH-NEXT:    fcvt.h.w fa0, a0
 ; RV32IDZFH-NEXT:    ret
 ;
 ; RV64IDZFH-LABEL: fcvt_h_w:
 ; RV64IDZFH:       # %bb.0:
 ; RV64IDZFH-NEXT:    fcvt.h.w fa0, a0
 ; RV64IDZFH-NEXT:    ret
 ;
+; RV32IZDINXZHINX-LABEL: fcvt_h_w:
+; RV32IZDINXZHINX:       # %bb.0:
+; RV32IZDINXZHINX-NEXT:    fcvt.h.w a0, a0
+; RV32IZDINXZHINX-NEXT:    ret
+;
+; RV64IZDINXZHINX-LABEL: fcvt_h_w:
+; RV64IZDINXZHINX:       # %bb.0:
+; RV64IZDINXZHINX-NEXT:    fcvt.h.w a0, a0
+; RV64IZDINXZHINX-NEXT:    ret
+;
 ; CHECK32-IZFHMIN-LABEL: fcvt_h_w:
 ; CHECK32-IZFHMIN:       # %bb.0:
 ; CHECK32-IZFHMIN-NEXT:    fcvt.s.w fa5, a0
 ; CHECK32-IZFHMIN-NEXT:    fcvt.h.s fa0, fa5
 ; CHECK32-IZFHMIN-NEXT:    ret
 ;
 ; CHECK64-IZFHMIN-LABEL: fcvt_h_w:
 ; CHECK64-IZFHMIN:       # %bb.0:
 ; CHECK64-IZFHMIN-NEXT:    sext.w a0, a0
 ; CHECK64-IZFHMIN-NEXT:    fcvt.s.l fa5, a0
 ; CHECK64-IZFHMIN-NEXT:    fcvt.h.s fa0, fa5
 ; CHECK64-IZFHMIN-NEXT:    ret
+;
+; CHECK32-IZHINXMIN-LABEL: fcvt_h_w:
+; CHECK32-IZHINXMIN:       # %bb.0:
+; CHECK32-IZHINXMIN-NEXT:    fcvt.s.w a0, a0
+; CHECK32-IZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; CHECK32-IZHINXMIN-NEXT:    ret
+;
+; CHECK64-IZHINXMIN-LABEL: fcvt_h_w:
+; CHECK64-IZHINXMIN:       # %bb.0:
+; CHECK64-IZHINXMIN-NEXT:    sext.w a0, a0
+; CHECK64-IZHINXMIN-NEXT:    fcvt.s.l a0, a0
+; CHECK64-IZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; CHECK64-IZHINXMIN-NEXT:    ret
+;
+; CHECK32-IZDINXZHINXMIN-LABEL: fcvt_h_w:
+; CHECK32-IZDINXZHINXMIN:       # %bb.0:
+; CHECK32-IZDINXZHINXMIN-NEXT:    fcvt.s.w a0, a0
+; CHECK32-IZDINXZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; CHECK32-IZDINXZHINXMIN-NEXT:    ret
+;
+; CHECK64-IZDINXZHINXMIN-LABEL: fcvt_h_w:
+; CHECK64-IZDINXZHINXMIN:       # %bb.0:
+; CHECK64-IZDINXZHINXMIN-NEXT:    sext.w a0, a0
+; CHECK64-IZDINXZHINXMIN-NEXT:    fcvt.s.l a0, a0
+; CHECK64-IZDINXZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; CHECK64-IZDINXZHINXMIN-NEXT:    ret
   %1 = call half @llvm.experimental.constrained.sitofp.f16.i32(i32 %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
   ret half %1
 }
 declare half @llvm.experimental.constrained.sitofp.f16.i32(i32, metadata, metadata)
 
 define half @fcvt_h_w_load(ptr %p) nounwind strictfp {
 ; CHECKIZFH-LABEL: fcvt_h_w_load:
 ; CHECKIZFH:       # %bb.0:
 ; CHECKIZFH-NEXT:    lw a0, 0(a0)
 ; CHECKIZFH-NEXT:    fcvt.h.w fa0, a0
 ; CHECKIZFH-NEXT:    ret
 ;
+; CHECKIZHINX-LABEL: fcvt_h_w_load:
+; CHECKIZHINX:       # %bb.0:
+; CHECKIZHINX-NEXT:    lw a0, 0(a0)
+; CHECKIZHINX-NEXT:    fcvt.h.w a0, a0
+; CHECKIZHINX-NEXT:    ret
+;
 ; RV32IDZFH-LABEL: fcvt_h_w_load:
 ; RV32IDZFH:       # %bb.0:
 ; RV32IDZFH-NEXT:    lw a0, 0(a0)
 ; RV32IDZFH-NEXT:    fcvt.h.w fa0, a0
 ; RV32IDZFH-NEXT:    ret
 ;
 ; RV64IDZFH-LABEL: fcvt_h_w_load:
 ; RV64IDZFH:       # %bb.0:
 ; RV64IDZFH-NEXT:    lw a0, 0(a0)
 ; RV64IDZFH-NEXT:    fcvt.h.w fa0, a0
 ; RV64IDZFH-NEXT:    ret
 ;
+; RV32IZDINXZHINX-LABEL: fcvt_h_w_load:
+; RV32IZDINXZHINX:       # %bb.0:
+; RV32IZDINXZHINX-NEXT:    lw a0, 0(a0)
+; RV32IZDINXZHINX-NEXT:    fcvt.h.w a0, a0
+; RV32IZDINXZHINX-NEXT:    ret
+;
+; RV64IZDINXZHINX-LABEL: fcvt_h_w_load:
+; RV64IZDINXZHINX:       # %bb.0:
+; RV64IZDINXZHINX-NEXT:    lw a0, 0(a0)
+; RV64IZDINXZHINX-NEXT:    fcvt.h.w a0, a0
+; RV64IZDINXZHINX-NEXT:    ret
+;
 ; CHECK32-IZFHMIN-LABEL: fcvt_h_w_load:
 ; CHECK32-IZFHMIN:       # %bb.0:
 ; CHECK32-IZFHMIN-NEXT:    lw a0, 0(a0)
 ; CHECK32-IZFHMIN-NEXT:    fcvt.s.w fa5, a0
 ; CHECK32-IZFHMIN-NEXT:    fcvt.h.s fa0, fa5
 ; CHECK32-IZFHMIN-NEXT:    ret
 ;
 ; CHECK64-IZFHMIN-LABEL: fcvt_h_w_load:
 ; CHECK64-IZFHMIN:       # %bb.0:
 ; CHECK64-IZFHMIN-NEXT:    lw a0, 0(a0)
 ; CHECK64-IZFHMIN-NEXT:    fcvt.s.l fa5, a0
 ; CHECK64-IZFHMIN-NEXT:    fcvt.h.s fa0, fa5
 ; CHECK64-IZFHMIN-NEXT:    ret
+;
+; CHECK32-IZHINXMIN-LABEL: fcvt_h_w_load:
+; CHECK32-IZHINXMIN:       # %bb.0:
+; CHECK32-IZHINXMIN-NEXT:    lw a0, 0(a0)
+; CHECK32-IZHINXMIN-NEXT:    fcvt.s.w a0, a0
+; CHECK32-IZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; CHECK32-IZHINXMIN-NEXT:    ret
+;
+; CHECK64-IZHINXMIN-LABEL: fcvt_h_w_load:
+; CHECK64-IZHINXMIN:       # %bb.0:
+; CHECK64-IZHINXMIN-NEXT:    lw a0, 0(a0)
+; CHECK64-IZHINXMIN-NEXT:    fcvt.s.l a0, a0
+; CHECK64-IZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; CHECK64-IZHINXMIN-NEXT:    ret
+;
+; CHECK32-IZDINXZHINXMIN-LABEL: fcvt_h_w_load:
+; CHECK32-IZDINXZHINXMIN:       # %bb.0:
+; CHECK32-IZDINXZHINXMIN-NEXT:    lw a0, 0(a0)
+; CHECK32-IZDINXZHINXMIN-NEXT:    fcvt.s.w a0, a0
+; CHECK32-IZDINXZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; CHECK32-IZDINXZHINXMIN-NEXT:    ret
+;
+; CHECK64-IZDINXZHINXMIN-LABEL: fcvt_h_w_load:
+; CHECK64-IZDINXZHINXMIN:       # %bb.0:
+; CHECK64-IZDINXZHINXMIN-NEXT:    lw a0, 0(a0)
+; CHECK64-IZDINXZHINXMIN-NEXT:    fcvt.s.l a0, a0
+; CHECK64-IZDINXZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; CHECK64-IZDINXZHINXMIN-NEXT:    ret
   %a = load i32, ptr %p
   %1 = call half @llvm.experimental.constrained.sitofp.f16.i32(i32 %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
   ret half %1
 }
 
 define half @fcvt_h_wu(i32 %a) nounwind strictfp {
 ; CHECKIZFH-LABEL: fcvt_h_wu:
 ; CHECKIZFH:       # %bb.0:
 ; CHECKIZFH-NEXT:    fcvt.h.wu fa0, a0
 ; CHECKIZFH-NEXT:    ret
 ;
+; CHECKIZHINX-LABEL: fcvt_h_wu:
+; CHECKIZHINX:       # %bb.0:
+; CHECKIZHINX-NEXT:    fcvt.h.wu a0, a0
+; CHECKIZHINX-NEXT:    ret
+;
 ; RV32IDZFH-LABEL: fcvt_h_wu:
 ; RV32IDZFH:       # %bb.0:
 ; RV32IDZFH-NEXT:    fcvt.h.wu fa0, a0
 ; RV32IDZFH-NEXT:    ret
 ;
 ; RV64IDZFH-LABEL: fcvt_h_wu:
 ; RV64IDZFH:       # %bb.0:
 ; RV64IDZFH-NEXT:    fcvt.h.wu fa0, a0
 ; RV64IDZFH-NEXT:    ret
 ;
+; RV32IZDINXZHINX-LABEL: fcvt_h_wu:
+; RV32IZDINXZHINX:       # %bb.0:
+; RV32IZDINXZHINX-NEXT:    fcvt.h.wu a0, a0
+; RV32IZDINXZHINX-NEXT:    ret
+;
+; RV64IZDINXZHINX-LABEL: fcvt_h_wu:
+; RV64IZDINXZHINX:       # %bb.0:
+; RV64IZDINXZHINX-NEXT:    fcvt.h.wu a0, a0
+; RV64IZDINXZHINX-NEXT:    ret
+;
 ; CHECK32-IZFHMIN-LABEL: fcvt_h_wu:
 ; CHECK32-IZFHMIN:       # %bb.0:
 ; CHECK32-IZFHMIN-NEXT:    fcvt.s.wu fa5, a0
 ; CHECK32-IZFHMIN-NEXT:    fcvt.h.s fa0, fa5
 ; CHECK32-IZFHMIN-NEXT:    ret
 ;
 ; CHECK64-IZFHMIN-LABEL: fcvt_h_wu:
 ; CHECK64-IZFHMIN:       # %bb.0:
 ; CHECK64-IZFHMIN-NEXT:    slli a0, a0, 32
 ; CHECK64-IZFHMIN-NEXT:    srli a0, a0, 32
 ; CHECK64-IZFHMIN-NEXT:    fcvt.s.lu fa5, a0
 ; CHECK64-IZFHMIN-NEXT:    fcvt.h.s fa0, fa5
 ; CHECK64-IZFHMIN-NEXT:    ret
+;
+; CHECK32-IZHINXMIN-LABEL: fcvt_h_wu:
+; CHECK32-IZHINXMIN:       # %bb.0:
+; CHECK32-IZHINXMIN-NEXT:    fcvt.s.wu a0, a0
+; CHECK32-IZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; CHECK32-IZHINXMIN-NEXT:    ret
+;
+; CHECK64-IZHINXMIN-LABEL: fcvt_h_wu:
+; CHECK64-IZHINXMIN:       # %bb.0:
+; CHECK64-IZHINXMIN-NEXT:    slli a0, a0, 32
+; CHECK64-IZHINXMIN-NEXT:    srli a0, a0, 32
+; CHECK64-IZHINXMIN-NEXT:    fcvt.s.lu a0, a0
+; CHECK64-IZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; CHECK64-IZHINXMIN-NEXT:    ret
+;
+; CHECK32-IZDINXZHINXMIN-LABEL: fcvt_h_wu:
+; CHECK32-IZDINXZHINXMIN:       # %bb.0:
+; CHECK32-IZDINXZHINXMIN-NEXT:    fcvt.s.wu a0, a0
+; CHECK32-IZDINXZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; CHECK32-IZDINXZHINXMIN-NEXT:    ret
+;
+; CHECK64-IZDINXZHINXMIN-LABEL: fcvt_h_wu:
+; CHECK64-IZDINXZHINXMIN:       # %bb.0:
+; CHECK64-IZDINXZHINXMIN-NEXT:    slli a0, a0, 32
+; CHECK64-IZDINXZHINXMIN-NEXT:    srli a0, a0, 32
+; CHECK64-IZDINXZHINXMIN-NEXT:    fcvt.s.lu a0, a0
+; CHECK64-IZDINXZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; CHECK64-IZDINXZHINXMIN-NEXT:    ret
   %1 = call half @llvm.experimental.constrained.uitofp.f16.i32(i32 %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
   ret half %1
 }
 declare half @llvm.experimental.constrained.uitofp.f16.i32(i32, metadata, metadata)
 
 define half @fcvt_h_wu_load(ptr %p) nounwind strictfp {
 ; RV32IZFH-LABEL: fcvt_h_wu_load:
 ; RV32IZFH:       # %bb.0:
 ; RV32IZFH-NEXT:    lw a0, 0(a0)
 ; RV32IZFH-NEXT:    fcvt.h.wu fa0, a0
 ; RV32IZFH-NEXT:    ret
 ;
 ; RV64IZFH-LABEL: fcvt_h_wu_load:
 ; RV64IZFH:       # %bb.0:
 ; RV64IZFH-NEXT:    lwu a0, 0(a0)
 ; RV64IZFH-NEXT:    fcvt.h.wu fa0, a0
 ; RV64IZFH-NEXT:    ret
 ;
+; RV32IZHINX-LABEL: fcvt_h_wu_load:
+; RV32IZHINX:       # %bb.0:
+; RV32IZHINX-NEXT:    lw a0, 0(a0)
+; RV32IZHINX-NEXT:    fcvt.h.wu a0, a0
+; RV32IZHINX-NEXT:    ret
+;
+; RV64IZHINX-LABEL: fcvt_h_wu_load:
+; RV64IZHINX:       # %bb.0:
+; RV64IZHINX-NEXT:    lwu a0, 0(a0)
+; RV64IZHINX-NEXT:    fcvt.h.wu a0, a0
+; RV64IZHINX-NEXT:    ret
+;
 ; RV32IDZFH-LABEL: fcvt_h_wu_load:
 ; RV32IDZFH:       # %bb.0:
 ; RV32IDZFH-NEXT:    lw a0, 0(a0)
 ; RV32IDZFH-NEXT:    fcvt.h.wu fa0, a0
 ; RV32IDZFH-NEXT:    ret
 ;
 ; RV64IDZFH-LABEL: fcvt_h_wu_load:
 ; RV64IDZFH:       # %bb.0:
 ; RV64IDZFH-NEXT:    lwu a0, 0(a0)
 ; RV64IDZFH-NEXT:    fcvt.h.wu fa0, a0
 ; RV64IDZFH-NEXT:    ret
 ;
+; RV32IZDINXZHINX-LABEL: fcvt_h_wu_load:
+; RV32IZDINXZHINX:       # %bb.0:
+; RV32IZDINXZHINX-NEXT:    lw a0, 0(a0)
+; RV32IZDINXZHINX-NEXT:    fcvt.h.wu a0, a0
+; RV32IZDINXZHINX-NEXT:    ret
+;
+; RV64IZDINXZHINX-LABEL: fcvt_h_wu_load:
+; RV64IZDINXZHINX:       # %bb.0:
+; RV64IZDINXZHINX-NEXT:    lwu a0, 0(a0)
+; RV64IZDINXZHINX-NEXT:    fcvt.h.wu a0, a0
+; RV64IZDINXZHINX-NEXT:    ret
+;
 ; CHECK32-IZFHMIN-LABEL: fcvt_h_wu_load:
 ; CHECK32-IZFHMIN:       # %bb.0:
 ; CHECK32-IZFHMIN-NEXT:    lw a0, 0(a0)
 ; CHECK32-IZFHMIN-NEXT:    fcvt.s.wu fa5, a0
 ; CHECK32-IZFHMIN-NEXT:    fcvt.h.s fa0, fa5
 ; CHECK32-IZFHMIN-NEXT:    ret
 ;
 ; CHECK64-IZFHMIN-LABEL: fcvt_h_wu_load:
 ; CHECK64-IZFHMIN:       # %bb.0:
 ; CHECK64-IZFHMIN-NEXT:    lwu a0, 0(a0)
 ; CHECK64-IZFHMIN-NEXT:    fcvt.s.lu fa5, a0
 ; CHECK64-IZFHMIN-NEXT:    fcvt.h.s fa0, fa5
 ; CHECK64-IZFHMIN-NEXT:    ret
+;
+; CHECK32-IZHINXMIN-LABEL: fcvt_h_wu_load:
+; CHECK32-IZHINXMIN:       # %bb.0:
+; CHECK32-IZHINXMIN-NEXT:    lw a0, 0(a0)
+; CHECK32-IZHINXMIN-NEXT:    fcvt.s.wu a0, a0
+; CHECK32-IZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; CHECK32-IZHINXMIN-NEXT:    ret
+;
+; CHECK64-IZHINXMIN-LABEL: fcvt_h_wu_load:
+; CHECK64-IZHINXMIN:       # %bb.0:
+; CHECK64-IZHINXMIN-NEXT:    lwu a0, 0(a0)
+; CHECK64-IZHINXMIN-NEXT:    fcvt.s.lu a0, a0
+; CHECK64-IZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; CHECK64-IZHINXMIN-NEXT:    ret
+;
+; CHECK32-IZDINXZHINXMIN-LABEL: fcvt_h_wu_load:
+; CHECK32-IZDINXZHINXMIN:       # %bb.0:
+; CHECK32-IZDINXZHINXMIN-NEXT:    lw a0, 0(a0)
+; CHECK32-IZDINXZHINXMIN-NEXT:    fcvt.s.wu a0, a0
+; CHECK32-IZDINXZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; CHECK32-IZDINXZHINXMIN-NEXT:    ret
+;
+; CHECK64-IZDINXZHINXMIN-LABEL: fcvt_h_wu_load:
+; CHECK64-IZDINXZHINXMIN:       # %bb.0:
+; CHECK64-IZDINXZHINXMIN-NEXT:    lwu a0, 0(a0)
+; CHECK64-IZDINXZHINXMIN-NEXT:    fcvt.s.lu a0, a0
+; CHECK64-IZDINXZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; CHECK64-IZDINXZHINXMIN-NEXT:    ret
   %a = load i32, ptr %p
   %1 = call half @llvm.experimental.constrained.uitofp.f16.i32(i32 %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
   ret half %1
 }
 
 define half @fcvt_h_l(i64 %a) nounwind strictfp {
 ; RV32IZFH-LABEL: fcvt_h_l:
 ; RV32IZFH:       # %bb.0:
 ; RV32IZFH-NEXT:    addi sp, sp, -16
 ; RV32IZFH-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32IZFH-NEXT:    call __floatdihf@plt
 ; RV32IZFH-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32IZFH-NEXT:    addi sp, sp, 16
 ; RV32IZFH-NEXT:    ret
 ;
 ; RV64IZFH-LABEL: fcvt_h_l:
 ; RV64IZFH:       # %bb.0:
 ; RV64IZFH-NEXT:    fcvt.h.l fa0, a0
 ; RV64IZFH-NEXT:    ret
 ;
+; RV32IZHINX-LABEL: fcvt_h_l:
+; RV32IZHINX:       # %bb.0:
+; RV32IZHINX-NEXT:    addi sp, sp, -16
+; RV32IZHINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZHINX-NEXT:    call __floatdihf@plt
+; RV32IZHINX-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZHINX-NEXT:    addi sp, sp, 16
+; RV32IZHINX-NEXT:    ret
+;
+; RV64IZHINX-LABEL: fcvt_h_l:
+; RV64IZHINX:       # %bb.0:
+; RV64IZHINX-NEXT:    fcvt.h.l a0, a0
+; RV64IZHINX-NEXT:    ret
+;
 ; RV32IDZFH-LABEL: fcvt_h_l:
 ; RV32IDZFH:       # %bb.0:
 ; RV32IDZFH-NEXT:    addi sp, sp, -16
 ; RV32IDZFH-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32IDZFH-NEXT:    call __floatdihf@plt
 ; RV32IDZFH-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32IDZFH-NEXT:    addi sp, sp, 16
 ; RV32IDZFH-NEXT:    ret
 ;
 ; RV64IDZFH-LABEL: fcvt_h_l:
 ; RV64IDZFH:       # %bb.0:
 ; RV64IDZFH-NEXT:    fcvt.h.l fa0, a0
 ; RV64IDZFH-NEXT:    ret
 ;
+; RV32IZDINXZHINX-LABEL: fcvt_h_l:
+; RV32IZDINXZHINX:       # %bb.0:
+; RV32IZDINXZHINX-NEXT:    addi sp, sp, -16
+; RV32IZDINXZHINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZDINXZHINX-NEXT:    call __floatdihf@plt
+; RV32IZDINXZHINX-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZDINXZHINX-NEXT:    addi sp, sp, 16
+; RV32IZDINXZHINX-NEXT:    ret
+;
+; RV64IZDINXZHINX-LABEL: fcvt_h_l:
+; RV64IZDINXZHINX:       # %bb.0:
+; RV64IZDINXZHINX-NEXT:    fcvt.h.l a0, a0
+; RV64IZDINXZHINX-NEXT:    ret
+;
 ; CHECK32-IZFHMIN-LABEL: fcvt_h_l:
 ; CHECK32-IZFHMIN:       # %bb.0:
 ; CHECK32-IZFHMIN-NEXT:    addi sp, sp, -16
 ; CHECK32-IZFHMIN-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; CHECK32-IZFHMIN-NEXT:    call __floatdihf@plt
 ; CHECK32-IZFHMIN-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; CHECK32-IZFHMIN-NEXT:    addi sp, sp, 16
 ; CHECK32-IZFHMIN-NEXT:    ret
 ;
 ; CHECK64-IZFHMIN-LABEL: fcvt_h_l:
 ; CHECK64-IZFHMIN:       # %bb.0:
 ; CHECK64-IZFHMIN-NEXT:    fcvt.s.l fa5, a0
 ; CHECK64-IZFHMIN-NEXT:    fcvt.h.s fa0, fa5
 ; CHECK64-IZFHMIN-NEXT:    ret
+;
+; CHECK32-IZHINXMIN-LABEL: fcvt_h_l:
+; CHECK32-IZHINXMIN:       # %bb.0:
+; CHECK32-IZHINXMIN-NEXT:    addi sp, sp, -16
+; CHECK32-IZHINXMIN-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; CHECK32-IZHINXMIN-NEXT:    call __floatdihf@plt
+; CHECK32-IZHINXMIN-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; CHECK32-IZHINXMIN-NEXT:    addi sp, sp, 16
+; CHECK32-IZHINXMIN-NEXT:    ret
+;
+; CHECK64-IZHINXMIN-LABEL: fcvt_h_l:
+; CHECK64-IZHINXMIN:       # %bb.0:
+; CHECK64-IZHINXMIN-NEXT:    fcvt.s.l a0, a0
+; CHECK64-IZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; CHECK64-IZHINXMIN-NEXT:    ret
+;
+; CHECK32-IZDINXZHINXMIN-LABEL: fcvt_h_l:
+; CHECK32-IZDINXZHINXMIN:       # %bb.0:
+; CHECK32-IZDINXZHINXMIN-NEXT:    addi sp, sp, -16
+; CHECK32-IZDINXZHINXMIN-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; CHECK32-IZDINXZHINXMIN-NEXT:    call __floatdihf@plt
+; CHECK32-IZDINXZHINXMIN-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; CHECK32-IZDINXZHINXMIN-NEXT:    addi sp, sp, 16
+; CHECK32-IZDINXZHINXMIN-NEXT:    ret
+;
+; CHECK64-IZDINXZHINXMIN-LABEL: fcvt_h_l:
+; CHECK64-IZDINXZHINXMIN:       # %bb.0:
+; CHECK64-IZDINXZHINXMIN-NEXT:    fcvt.s.l a0, a0
+; CHECK64-IZDINXZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; CHECK64-IZDINXZHINXMIN-NEXT:    ret
   %1 = call half @llvm.experimental.constrained.sitofp.f16.i64(i64 %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
   ret half %1
 }
 declare half @llvm.experimental.constrained.sitofp.f16.i64(i64, metadata, metadata)
 
 define half @fcvt_h_lu(i64 %a) nounwind strictfp {
 ; RV32IZFH-LABEL: fcvt_h_lu:
 ; RV32IZFH:       # %bb.0:
 ; RV32IZFH-NEXT:    addi sp, sp, -16
 ; RV32IZFH-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32IZFH-NEXT:    call __floatundihf@plt
 ; RV32IZFH-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32IZFH-NEXT:    addi sp, sp, 16
 ; RV32IZFH-NEXT:    ret
 ;
 ; RV64IZFH-LABEL: fcvt_h_lu:
 ; RV64IZFH:       # %bb.0:
 ; RV64IZFH-NEXT:    fcvt.h.lu fa0, a0
 ; RV64IZFH-NEXT:    ret
 ;
+; RV32IZHINX-LABEL: fcvt_h_lu:
+; RV32IZHINX:       # %bb.0:
+; RV32IZHINX-NEXT:    addi sp, sp, -16
+; RV32IZHINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZHINX-NEXT:    call __floatundihf@plt
+; RV32IZHINX-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZHINX-NEXT:    addi sp, sp, 16
+; RV32IZHINX-NEXT:    ret
+;
+; RV64IZHINX-LABEL: fcvt_h_lu:
+; RV64IZHINX:       # %bb.0:
+; RV64IZHINX-NEXT:    fcvt.h.lu a0, a0
+; RV64IZHINX-NEXT:    ret
+;
 ; RV32IDZFH-LABEL: fcvt_h_lu:
 ; RV32IDZFH:       # %bb.0:
 ; RV32IDZFH-NEXT:    addi sp, sp, -16
 ; RV32IDZFH-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32IDZFH-NEXT:    call __floatundihf@plt
 ; RV32IDZFH-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32IDZFH-NEXT:    addi sp, sp, 16
 ; RV32IDZFH-NEXT:    ret
 ;
 ; RV64IDZFH-LABEL: fcvt_h_lu:
 ; RV64IDZFH:       # %bb.0:
 ; RV64IDZFH-NEXT:    fcvt.h.lu fa0, a0
 ; RV64IDZFH-NEXT:    ret
 ;
+; RV32IZDINXZHINX-LABEL: fcvt_h_lu:
+; RV32IZDINXZHINX:       # %bb.0:
+; RV32IZDINXZHINX-NEXT:    addi sp, sp, -16
+; RV32IZDINXZHINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZDINXZHINX-NEXT:    call __floatundihf@plt
+; RV32IZDINXZHINX-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZDINXZHINX-NEXT:    addi sp, sp, 16
+; RV32IZDINXZHINX-NEXT:    ret
+;
+; RV64IZDINXZHINX-LABEL: fcvt_h_lu:
+; RV64IZDINXZHINX:       # %bb.0:
+; RV64IZDINXZHINX-NEXT:    fcvt.h.lu a0, a0
+; RV64IZDINXZHINX-NEXT:    ret
+;
 ; CHECK32-IZFHMIN-LABEL: fcvt_h_lu:
 ; CHECK32-IZFHMIN:       # %bb.0:
 ; CHECK32-IZFHMIN-NEXT:    addi sp, sp, -16
 ; CHECK32-IZFHMIN-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; CHECK32-IZFHMIN-NEXT:    call __floatundihf@plt
 ; CHECK32-IZFHMIN-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; CHECK32-IZFHMIN-NEXT:    addi sp, sp, 16
 ; CHECK32-IZFHMIN-NEXT:    ret
 ;
 ; CHECK64-IZFHMIN-LABEL: fcvt_h_lu:
 ; CHECK64-IZFHMIN:       # %bb.0:
 ; CHECK64-IZFHMIN-NEXT:    fcvt.s.lu fa5, a0
 ; CHECK64-IZFHMIN-NEXT:    fcvt.h.s fa0, fa5
 ; CHECK64-IZFHMIN-NEXT:    ret
+;
+; CHECK32-IZHINXMIN-LABEL: fcvt_h_lu:
+; CHECK32-IZHINXMIN:       # %bb.0:
+; CHECK32-IZHINXMIN-NEXT:    addi sp, sp, -16
+; CHECK32-IZHINXMIN-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; CHECK32-IZHINXMIN-NEXT:    call __floatundihf@plt
+; CHECK32-IZHINXMIN-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; CHECK32-IZHINXMIN-NEXT:    addi sp, sp, 16
+; CHECK32-IZHINXMIN-NEXT:    ret
+;
+; CHECK64-IZHINXMIN-LABEL: fcvt_h_lu:
+; CHECK64-IZHINXMIN:       # %bb.0:
+; CHECK64-IZHINXMIN-NEXT:    fcvt.s.lu a0, a0
+; CHECK64-IZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; CHECK64-IZHINXMIN-NEXT:    ret
+;
+; CHECK32-IZDINXZHINXMIN-LABEL: fcvt_h_lu:
+; CHECK32-IZDINXZHINXMIN:       # %bb.0:
+; CHECK32-IZDINXZHINXMIN-NEXT:    addi sp, sp, -16
+; CHECK32-IZDINXZHINXMIN-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; CHECK32-IZDINXZHINXMIN-NEXT:    call __floatundihf@plt
+; CHECK32-IZDINXZHINXMIN-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; CHECK32-IZDINXZHINXMIN-NEXT:    addi sp, sp, 16
+; CHECK32-IZDINXZHINXMIN-NEXT:    ret
+;
+; CHECK64-IZDINXZHINXMIN-LABEL: fcvt_h_lu:
+; CHECK64-IZDINXZHINXMIN:       # %bb.0:
+; CHECK64-IZDINXZHINXMIN-NEXT:    fcvt.s.lu a0, a0
+; CHECK64-IZDINXZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; CHECK64-IZDINXZHINXMIN-NEXT:    ret
   %1 = call half @llvm.experimental.constrained.uitofp.f16.i64(i64 %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
   ret half %1
 }
 declare half @llvm.experimental.constrained.uitofp.f16.i64(i64, metadata, metadata)
 
 define half @fcvt_h_s(float %a) nounwind strictfp {
 ; CHECKIZFH-LABEL: fcvt_h_s:
 ; CHECKIZFH:       # %bb.0:
 ; CHECKIZFH-NEXT:    fcvt.h.s fa0, fa0
 ; CHECKIZFH-NEXT:    ret
 ;
+; CHECKIZHINX-LABEL: fcvt_h_s:
+; CHECKIZHINX:       # %bb.0:
+; CHECKIZHINX-NEXT:    fcvt.h.s a0, a0
+; CHECKIZHINX-NEXT:    ret
+;
 ; RV32IDZFH-LABEL: fcvt_h_s:
 ; RV32IDZFH:       # %bb.0:
 ; RV32IDZFH-NEXT:    fcvt.h.s fa0, fa0
 ; RV32IDZFH-NEXT:    ret
 ;
 ; RV64IDZFH-LABEL: fcvt_h_s:
 ; RV64IDZFH:       # %bb.0:
 ; RV64IDZFH-NEXT:    fcvt.h.s fa0, fa0
 ; RV64IDZFH-NEXT:    ret
 ;
+; RV32IZDINXZHINX-LABEL: fcvt_h_s:
+; RV32IZDINXZHINX:       # %bb.0:
+; RV32IZDINXZHINX-NEXT:    fcvt.h.s a0, a0
+; RV32IZDINXZHINX-NEXT:    ret
+;
+; RV64IZDINXZHINX-LABEL: fcvt_h_s:
+; RV64IZDINXZHINX:       # %bb.0:
+; RV64IZDINXZHINX-NEXT:    fcvt.h.s a0, a0
+; RV64IZDINXZHINX-NEXT:    ret
+;
 ; CHECK32-IZFHMIN-LABEL: fcvt_h_s:
 ; CHECK32-IZFHMIN:       # %bb.0:
 ; CHECK32-IZFHMIN-NEXT:    fcvt.h.s fa0, fa0
 ; CHECK32-IZFHMIN-NEXT:    ret
 ;
 ; CHECK64-IZFHMIN-LABEL: fcvt_h_s:
 ; CHECK64-IZFHMIN:       # %bb.0:
 ; CHECK64-IZFHMIN-NEXT:    fcvt.h.s fa0, fa0
 ; CHECK64-IZFHMIN-NEXT:    ret
+;
+; CHECK32-IZHINXMIN-LABEL: fcvt_h_s:
+; CHECK32-IZHINXMIN:       # %bb.0:
+; CHECK32-IZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; CHECK32-IZHINXMIN-NEXT:    ret
+;
+; CHECK64-IZHINXMIN-LABEL: fcvt_h_s:
+; CHECK64-IZHINXMIN:       # %bb.0:
+; CHECK64-IZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; CHECK64-IZHINXMIN-NEXT:    ret
+;
+; CHECK32-IZDINXZHINXMIN-LABEL: fcvt_h_s:
+; CHECK32-IZDINXZHINXMIN:       # %bb.0:
+; CHECK32-IZDINXZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; CHECK32-IZDINXZHINXMIN-NEXT:    ret
+;
+; CHECK64-IZDINXZHINXMIN-LABEL: fcvt_h_s:
+; CHECK64-IZDINXZHINXMIN:       # %bb.0:
+; CHECK64-IZDINXZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; CHECK64-IZDINXZHINXMIN-NEXT:    ret
   %1 = call half @llvm.experimental.constrained.fptrunc.f16.f32(float %a, metadata !"round.dynamic", metadata !"fpexcept.strict")
   ret half %1
 }
 declare half @llvm.experimental.constrained.fptrunc.f16.f32(float, metadata, metadata)
 
 define float @fcvt_s_h(half %a) nounwind strictfp {
 ; CHECKIZFH-LABEL: fcvt_s_h:
 ; CHECKIZFH:       # %bb.0:
 ; CHECKIZFH-NEXT:    fcvt.s.h fa0, fa0
 ; CHECKIZFH-NEXT:    ret
 ;
+; CHECKIZHINX-LABEL: fcvt_s_h:
+; CHECKIZHINX:       # %bb.0:
+; CHECKIZHINX-NEXT:    fcvt.s.h a0, a0
+; CHECKIZHINX-NEXT:    ret
+;
 ; RV32IDZFH-LABEL: fcvt_s_h:
 ; RV32IDZFH:       # %bb.0:
 ; RV32IDZFH-NEXT:    fcvt.s.h fa0, fa0
 ; RV32IDZFH-NEXT:    ret
 ;
 ; RV64IDZFH-LABEL: fcvt_s_h:
 ; RV64IDZFH:       # %bb.0:
 ; RV64IDZFH-NEXT:    fcvt.s.h fa0, fa0
 ; RV64IDZFH-NEXT:    ret
 ;
+; RV32IZDINXZHINX-LABEL: fcvt_s_h:
+; RV32IZDINXZHINX:       # %bb.0:
+; RV32IZDINXZHINX-NEXT:    fcvt.s.h a0, a0
+; RV32IZDINXZHINX-NEXT:    ret
+;
+; RV64IZDINXZHINX-LABEL: fcvt_s_h:
+; RV64IZDINXZHINX:       # %bb.0:
+; RV64IZDINXZHINX-NEXT:    fcvt.s.h a0, a0
+; RV64IZDINXZHINX-NEXT:    ret
+;
 ; CHECK32-IZFHMIN-LABEL: fcvt_s_h:
 ; CHECK32-IZFHMIN:       # %bb.0:
 ; CHECK32-IZFHMIN-NEXT:    fcvt.s.h fa0, fa0
 ; CHECK32-IZFHMIN-NEXT:    ret
 ;
 ; CHECK64-IZFHMIN-LABEL: fcvt_s_h:
 ; CHECK64-IZFHMIN:       # %bb.0:
 ; CHECK64-IZFHMIN-NEXT:    fcvt.s.h fa0, fa0
 ; CHECK64-IZFHMIN-NEXT:    ret
+;
+; CHECK32-IZHINXMIN-LABEL: fcvt_s_h:
+; CHECK32-IZHINXMIN:       # %bb.0:
+; CHECK32-IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECK32-IZHINXMIN-NEXT:    ret
+;
+; CHECK64-IZHINXMIN-LABEL: fcvt_s_h:
+; CHECK64-IZHINXMIN:       # %bb.0:
+; CHECK64-IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECK64-IZHINXMIN-NEXT:    ret
+;
+; CHECK32-IZDINXZHINXMIN-LABEL: fcvt_s_h:
+; CHECK32-IZDINXZHINXMIN:       # %bb.0:
+; CHECK32-IZDINXZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECK32-IZDINXZHINXMIN-NEXT:    ret
+;
+; CHECK64-IZDINXZHINXMIN-LABEL: fcvt_s_h:
+; CHECK64-IZDINXZHINXMIN:       # %bb.0:
+; CHECK64-IZDINXZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECK64-IZDINXZHINXMIN-NEXT:    ret
   %1 = call float @llvm.experimental.constrained.fpext.f32.f16(half %a, metadata !"fpexcept.strict")
   ret float %1
 }
 declare float @llvm.experimental.constrained.fpext.f32.f16(half, metadata)
 
 define half @fcvt_h_d(double %a) nounwind strictfp {
 ; RV32IZFH-LABEL: fcvt_h_d:
 ; RV32IZFH:       # %bb.0:
 ; RV32IZFH-NEXT:    addi sp, sp, -16
 ; RV32IZFH-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32IZFH-NEXT:    call __truncdfhf2@plt
 ; RV32IZFH-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32IZFH-NEXT:    addi sp, sp, 16
 ; RV32IZFH-NEXT:    ret
 ;
 ; RV64IZFH-LABEL: fcvt_h_d:
 ; RV64IZFH:       # %bb.0:
 ; RV64IZFH-NEXT:    addi sp, sp, -16
 ; RV64IZFH-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64IZFH-NEXT:    call __truncdfhf2@plt
 ; RV64IZFH-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64IZFH-NEXT:    addi sp, sp, 16
 ; RV64IZFH-NEXT:    ret
 ;
+; RV32IZHINX-LABEL: fcvt_h_d:
+; RV32IZHINX:       # %bb.0:
+; RV32IZHINX-NEXT:    addi sp, sp, -16
+; RV32IZHINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZHINX-NEXT:    call __truncdfhf2@plt
+; RV32IZHINX-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZHINX-NEXT:    addi sp, sp, 16
+; RV32IZHINX-NEXT:    ret
+;
+; RV64IZHINX-LABEL: fcvt_h_d:
+; RV64IZHINX:       # %bb.0:
+; RV64IZHINX-NEXT:    addi sp, sp, -16
+; RV64IZHINX-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IZHINX-NEXT:    call __truncdfhf2@plt
+; RV64IZHINX-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
+; RV64IZHINX-NEXT:    addi sp, sp, 16
+; RV64IZHINX-NEXT:    ret
+;
 ; RV32IDZFH-LABEL: fcvt_h_d:
 ; RV32IDZFH:       # %bb.0:
 ; RV32IDZFH-NEXT:    fcvt.h.d fa0, fa0
 ; RV32IDZFH-NEXT:    ret
 ;
 ; RV64IDZFH-LABEL: fcvt_h_d:
 ; RV64IDZFH:       # %bb.0:
 ; RV64IDZFH-NEXT:    fcvt.h.d fa0, fa0
 ; RV64IDZFH-NEXT:    ret
 ;
+; RV32IZDINXZHINX-LABEL: fcvt_h_d:
+; RV32IZDINXZHINX:       # %bb.0:
+; RV32IZDINXZHINX-NEXT:    addi sp, sp, -16
+; RV32IZDINXZHINX-NEXT:    sw a0, 8(sp)
+; RV32IZDINXZHINX-NEXT:    sw a1, 12(sp)
+; RV32IZDINXZHINX-NEXT:    lw a0, 8(sp)
+; RV32IZDINXZHINX-NEXT:    lw a1, 12(sp)
+; RV32IZDINXZHINX-NEXT:    fcvt.h.d a0, a0
+; RV32IZDINXZHINX-NEXT:    addi sp, sp, 16
+; RV32IZDINXZHINX-NEXT:    ret
+;
+; RV64IZDINXZHINX-LABEL: fcvt_h_d:
+; RV64IZDINXZHINX:       # %bb.0:
+; RV64IZDINXZHINX-NEXT:    fcvt.h.d a0, a0
+; RV64IZDINXZHINX-NEXT:    ret
+;
 ; RV32IFZFHMIN-LABEL: fcvt_h_d:
 ; RV32IFZFHMIN:       # %bb.0:
 ; RV32IFZFHMIN-NEXT:    addi sp, sp, -16
 ; RV32IFZFHMIN-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32IFZFHMIN-NEXT:    call __truncdfhf2@plt
 ; RV32IFZFHMIN-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32IFZFHMIN-NEXT:    addi sp, sp, 16
 ; RV32IFZFHMIN-NEXT:    ret
 ;
 ; RV64IFZFHMIN-LABEL: fcvt_h_d:
 ; RV64IFZFHMIN:       # %bb.0:
 ; RV64IFZFHMIN-NEXT:    addi sp, sp, -16
 ; RV64IFZFHMIN-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64IFZFHMIN-NEXT:    call __truncdfhf2@plt
 ; RV64IFZFHMIN-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64IFZFHMIN-NEXT:    addi sp, sp, 16
 ; RV64IFZFHMIN-NEXT:    ret
 ;
+; CHECK32-IZHINXMIN-LABEL: fcvt_h_d:
+; CHECK32-IZHINXMIN:       # %bb.0:
+; CHECK32-IZHINXMIN-NEXT:    addi sp, sp, -16
+; CHECK32-IZHINXMIN-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; CHECK32-IZHINXMIN-NEXT:    call __truncdfhf2@plt
+; CHECK32-IZHINXMIN-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; CHECK32-IZHINXMIN-NEXT:    addi sp, sp, 16
+; CHECK32-IZHINXMIN-NEXT:    ret
+;
+; CHECK64-IZHINXMIN-LABEL: fcvt_h_d:
+; CHECK64-IZHINXMIN:       # %bb.0:
+; CHECK64-IZHINXMIN-NEXT:    addi sp, sp, -16
+; CHECK64-IZHINXMIN-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; CHECK64-IZHINXMIN-NEXT:    call __truncdfhf2@plt
+; CHECK64-IZHINXMIN-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
+; CHECK64-IZHINXMIN-NEXT:    addi sp, sp, 16
+; CHECK64-IZHINXMIN-NEXT:    ret
+;
 ; RV32IDZFHMIN-LABEL: fcvt_h_d:
 ; RV32IDZFHMIN:       # %bb.0:
 ; RV32IDZFHMIN-NEXT:    fcvt.h.d fa0, fa0
 ; RV32IDZFHMIN-NEXT:    ret
 ;
 ; RV64IDZFHMIN-LABEL: fcvt_h_d:
 ; RV64IDZFHMIN:       # %bb.0:
 ; RV64IDZFHMIN-NEXT:    fcvt.h.d fa0, fa0
 ; RV64IDZFHMIN-NEXT:    ret
+;
+; CHECK32-IZDINXZHINXMIN-LABEL: fcvt_h_d:
+; CHECK32-IZDINXZHINXMIN:       # %bb.0:
+; CHECK32-IZDINXZHINXMIN-NEXT:    addi sp, sp, -16
+; CHECK32-IZDINXZHINXMIN-NEXT:    sw a0, 8(sp)
+; CHECK32-IZDINXZHINXMIN-NEXT:    sw a1, 12(sp)
+; CHECK32-IZDINXZHINXMIN-NEXT:    lw a0, 8(sp)
+; CHECK32-IZDINXZHINXMIN-NEXT:    lw a1, 12(sp)
+; CHECK32-IZDINXZHINXMIN-NEXT:    fcvt.h.d a0, a0
+; CHECK32-IZDINXZHINXMIN-NEXT:    addi sp, sp, 16
+; CHECK32-IZDINXZHINXMIN-NEXT:    ret
+;
+; CHECK64-IZDINXZHINXMIN-LABEL: fcvt_h_d:
+; CHECK64-IZDINXZHINXMIN:       # %bb.0:
+; CHECK64-IZDINXZHINXMIN-NEXT:    fcvt.h.d a0, a0
+; CHECK64-IZDINXZHINXMIN-NEXT:    ret
   %1 = call half @llvm.experimental.constrained.fptrunc.f16.f64(double %a, metadata !"round.dynamic", metadata !"fpexcept.strict")
   ret half %1
 }
 declare half @llvm.experimental.constrained.fptrunc.f16.f64(double, metadata, metadata)
 
 define double @fcvt_d_h(half %a) nounwind strictfp {
 ; RV32IZFH-LABEL: fcvt_d_h:
 ; RV32IZFH:       # %bb.0:

 ; RV64IZFH-NEXT:    addi sp, sp, -16
 ; RV64IZFH-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64IZFH-NEXT:    fcvt.s.h fa0, fa0
 ; RV64IZFH-NEXT:    call __extendsfdf2@plt
 ; RV64IZFH-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64IZFH-NEXT:    addi sp, sp, 16
 ; RV64IZFH-NEXT:    ret
 ;
+; RV32IZHINX-LABEL: fcvt_d_h:
+; RV32IZHINX:       # %bb.0:
+; RV32IZHINX-NEXT:    addi sp, sp, -16
+; RV32IZHINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZHINX-NEXT:    fcvt.s.h a0, a0
+; RV32IZHINX-NEXT:    call __extendsfdf2@plt
+; RV32IZHINX-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZHINX-NEXT:    addi sp, sp, 16
+; RV32IZHINX-NEXT:    ret
+;
+; RV64IZHINX-LABEL: fcvt_d_h:
+; RV64IZHINX:       # %bb.0:
+; RV64IZHINX-NEXT:    addi sp, sp, -16
+; RV64IZHINX-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IZHINX-NEXT:    fcvt.s.h a0, a0
+; RV64IZHINX-NEXT:    call __extendsfdf2@plt
+; RV64IZHINX-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
+; RV64IZHINX-NEXT:    addi sp, sp, 16
+; RV64IZHINX-NEXT:    ret
+;
 ; RV32IDZFH-LABEL: fcvt_d_h:
 ; RV32IDZFH:       # %bb.0:
 ; RV32IDZFH-NEXT:    fcvt.d.h fa0, fa0
 ; RV32IDZFH-NEXT:    ret
 ;
 ; RV64IDZFH-LABEL: fcvt_d_h:
 ; RV64IDZFH:       # %bb.0:
 ; RV64IDZFH-NEXT:    fcvt.d.h fa0, fa0
 ; RV64IDZFH-NEXT:    ret
 ;
+; RV32IZDINXZHINX-LABEL: fcvt_d_h:
+; RV32IZDINXZHINX:       # %bb.0:
+; RV32IZDINXZHINX-NEXT:    addi sp, sp, -16
+; RV32IZDINXZHINX-NEXT:    fcvt.d.h a0, a0
+; RV32IZDINXZHINX-NEXT:    sw a0, 8(sp)
+; RV32IZDINXZHINX-NEXT:    sw a1, 12(sp)
+; RV32IZDINXZHINX-NEXT:    lw a0, 8(sp)
+; RV32IZDINXZHINX-NEXT:    lw a1, 12(sp)
+; RV32IZDINXZHINX-NEXT:    addi sp, sp, 16
+; RV32IZDINXZHINX-NEXT:    ret
+;
+; RV64IZDINXZHINX-LABEL: fcvt_d_h:
+; RV64IZDINXZHINX:       # %bb.0:
+; RV64IZDINXZHINX-NEXT:    fcvt.d.h a0, a0
+; RV64IZDINXZHINX-NEXT:    ret
+;
 ; RV32IFZFHMIN-LABEL: fcvt_d_h:
 ; RV32IFZFHMIN:       # %bb.0:
 ; RV32IFZFHMIN-NEXT:    addi sp, sp, -16
 ; RV32IFZFHMIN-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32IFZFHMIN-NEXT:    fcvt.s.h fa0, fa0
 ; RV32IFZFHMIN-NEXT:    call __extendsfdf2@plt
 ; RV32IFZFHMIN-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32IFZFHMIN-NEXT:    addi sp, sp, 16
 ; RV32IFZFHMIN-NEXT:    ret
 ;
 ; RV64IFZFHMIN-LABEL: fcvt_d_h:
 ; RV64IFZFHMIN:       # %bb.0:
 ; RV64IFZFHMIN-NEXT:    addi sp, sp, -16
 ; RV64IFZFHMIN-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64IFZFHMIN-NEXT:    fcvt.s.h fa0, fa0
 ; RV64IFZFHMIN-NEXT:    call __extendsfdf2@plt
 ; RV64IFZFHMIN-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64IFZFHMIN-NEXT:    addi sp, sp, 16
 ; RV64IFZFHMIN-NEXT:    ret
 ;
+; CHECK32-IZHINXMIN-LABEL: fcvt_d_h:
+; CHECK32-IZHINXMIN:       # %bb.0:
+; CHECK32-IZHINXMIN-NEXT:    addi sp, sp, -16
+; CHECK32-IZHINXMIN-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; CHECK32-IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECK32-IZHINXMIN-NEXT:    call __extendsfdf2@plt
+; CHECK32-IZHINXMIN-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; CHECK32-IZHINXMIN-NEXT:    addi sp, sp, 16
+; CHECK32-IZHINXMIN-NEXT:    ret
+;
+; CHECK64-IZHINXMIN-LABEL: fcvt_d_h:
+; CHECK64-IZHINXMIN:       # %bb.0:
+; CHECK64-IZHINXMIN-NEXT:    addi sp, sp, -16
+; CHECK64-IZHINXMIN-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; CHECK64-IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECK64-IZHINXMIN-NEXT:    call __extendsfdf2@plt
+; CHECK64-IZHINXMIN-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
+; CHECK64-IZHINXMIN-NEXT:    addi sp, sp, 16
+; CHECK64-IZHINXMIN-NEXT:    ret
+;
 ; RV32IDZFHMIN-LABEL: fcvt_d_h:
 ; RV32IDZFHMIN:       # %bb.0:
 ; RV32IDZFHMIN-NEXT:    fcvt.d.h fa0, fa0
 ; RV32IDZFHMIN-NEXT:    ret
 ;
 ; RV64IDZFHMIN-LABEL: fcvt_d_h:
 ; RV64IDZFHMIN:       # %bb.0:
 ; RV64IDZFHMIN-NEXT:    fcvt.d.h fa0, fa0
 ; RV64IDZFHMIN-NEXT:    ret
+;
+; CHECK32-IZDINXZHINXMIN-LABEL: fcvt_d_h:
+; CHECK32-IZDINXZHINXMIN:       # %bb.0:
+; CHECK32-IZDINXZHINXMIN-NEXT:    addi sp, sp, -16
+; CHECK32-IZDINXZHINXMIN-NEXT:    fcvt.d.h a0, a0
+; CHECK32-IZDINXZHINXMIN-NEXT:    sw a0, 8(sp)
+; CHECK32-IZDINXZHINXMIN-NEXT:    sw a1, 12(sp)
+; CHECK32-IZDINXZHINXMIN-NEXT:    lw a0, 8(sp)
+; CHECK32-IZDINXZHINXMIN-NEXT:    lw a1, 12(sp)
+; CHECK32-IZDINXZHINXMIN-NEXT:    addi sp, sp, 16
+; CHECK32-IZDINXZHINXMIN-NEXT:    ret
+;
+; CHECK64-IZDINXZHINXMIN-LABEL: fcvt_d_h:
+; CHECK64-IZDINXZHINXMIN:       # %bb.0:
+; CHECK64-IZDINXZHINXMIN-NEXT:    fcvt.d.h a0, a0
+; CHECK64-IZDINXZHINXMIN-NEXT:    ret
   %1 = call double @llvm.experimental.constrained.fpext.f64.f16(half %a, metadata !"fpexcept.strict")
   ret double %1
 }
 declare double @llvm.experimental.constrained.fpext.f64.f16(half, metadata)
 
 ; Make sure we select W version of addi on RV64.
 define signext i32 @fcvt_h_w_demanded_bits(i32 signext %0, ptr %1) {
 ; RV32IZFH-LABEL: fcvt_h_w_demanded_bits:
 ; RV32IZFH:       # %bb.0:
 ; RV32IZFH-NEXT:    addi a0, a0, 1
 ; RV32IZFH-NEXT:    fcvt.h.w fa5, a0
 ; RV32IZFH-NEXT:    fsh fa5, 0(a1)
 ; RV32IZFH-NEXT:    ret
 ;
 ; RV64IZFH-LABEL: fcvt_h_w_demanded_bits:
 ; RV64IZFH:       # %bb.0:
 ; RV64IZFH-NEXT:    addiw a0, a0, 1
 ; RV64IZFH-NEXT:    fcvt.h.w fa5, a0
 ; RV64IZFH-NEXT:    fsh fa5, 0(a1)
 ; RV64IZFH-NEXT:    ret
 ;
+; RV32IZHINX-LABEL: fcvt_h_w_demanded_bits:
+; RV32IZHINX:       # %bb.0:
+; RV32IZHINX-NEXT:    addi a0, a0, 1
+; RV32IZHINX-NEXT:    fcvt.h.w a2, a0
+; RV32IZHINX-NEXT:    sh a2, 0(a1)
+; RV32IZHINX-NEXT:    ret
+;
+; RV64IZHINX-LABEL: fcvt_h_w_demanded_bits:
+; RV64IZHINX:       # %bb.0:
+; RV64IZHINX-NEXT:    addiw a2, a0, 1
+; RV64IZHINX-NEXT:    addi a0, a0, 1
+; RV64IZHINX-NEXT:    fcvt.h.w a0, a0
+; RV64IZHINX-NEXT:    sh a0, 0(a1)
+; RV64IZHINX-NEXT:    mv a0, a2
+; RV64IZHINX-NEXT:    ret
+;
 ; RV32IDZFH-LABEL: fcvt_h_w_demanded_bits:
 ; RV32IDZFH:       # %bb.0:
 ; RV32IDZFH-NEXT:    addi a0, a0, 1
 ; RV32IDZFH-NEXT:    fcvt.h.w fa5, a0
 ; RV32IDZFH-NEXT:    fsh fa5, 0(a1)
 ; RV32IDZFH-NEXT:    ret
 ;
 ; RV64IDZFH-LABEL: fcvt_h_w_demanded_bits:
 ; RV64IDZFH:       # %bb.0:
 ; RV64IDZFH-NEXT:    addiw a0, a0, 1
 ; RV64IDZFH-NEXT:    fcvt.h.w fa5, a0
 ; RV64IDZFH-NEXT:    fsh fa5, 0(a1)
 ; RV64IDZFH-NEXT:    ret
 ;
+; RV32IZDINXZHINX-LABEL: fcvt_h_w_demanded_bits:
+; RV32IZDINXZHINX:       # %bb.0:
+; RV32IZDINXZHINX-NEXT:    addi a0, a0, 1
+; RV32IZDINXZHINX-NEXT:    fcvt.h.w a2, a0
+; RV32IZDINXZHINX-NEXT:    sh a2, 0(a1)
+; RV32IZDINXZHINX-NEXT:    ret
+;
+; RV64IZDINXZHINX-LABEL: fcvt_h_w_demanded_bits:
+; RV64IZDINXZHINX:       # %bb.0:
+; RV64IZDINXZHINX-NEXT:    addiw a2, a0, 1
+; RV64IZDINXZHINX-NEXT:    addi a0, a0, 1
+; RV64IZDINXZHINX-NEXT:    fcvt.h.w a0, a0
+; RV64IZDINXZHINX-NEXT:    sh a0, 0(a1)
+; RV64IZDINXZHINX-NEXT:    mv a0, a2
+; RV64IZDINXZHINX-NEXT:    ret
+;
 ; CHECK32-IZFHMIN-LABEL: fcvt_h_w_demanded_bits:
 ; CHECK32-IZFHMIN:       # %bb.0:
 ; CHECK32-IZFHMIN-NEXT:    addi a0, a0, 1
 ; CHECK32-IZFHMIN-NEXT:    fcvt.s.w fa5, a0
 ; CHECK32-IZFHMIN-NEXT:    fcvt.h.s fa5, fa5
 ; CHECK32-IZFHMIN-NEXT:    fsh fa5, 0(a1)
 ; CHECK32-IZFHMIN-NEXT:    ret
 ;
 ; CHECK64-IZFHMIN-LABEL: fcvt_h_w_demanded_bits:
 ; CHECK64-IZFHMIN:       # %bb.0:
 ; CHECK64-IZFHMIN-NEXT:    addiw a0, a0, 1
 ; CHECK64-IZFHMIN-NEXT:    fcvt.s.l fa5, a0
 ; CHECK64-IZFHMIN-NEXT:    fcvt.h.s fa5, fa5
 ; CHECK64-IZFHMIN-NEXT:    fsh fa5, 0(a1)
 ; CHECK64-IZFHMIN-NEXT:    ret
+;
+; CHECK32-IZHINXMIN-LABEL: fcvt_h_w_demanded_bits:
+; CHECK32-IZHINXMIN:       # %bb.0:
+; CHECK32-IZHINXMIN-NEXT:    addi a0, a0, 1
+; CHECK32-IZHINXMIN-NEXT:    fcvt.s.w a2, a0
+; CHECK32-IZHINXMIN-NEXT:    fcvt.h.s a2, a2
+; CHECK32-IZHINXMIN-NEXT:    sh a2, 0(a1)
+; CHECK32-IZHINXMIN-NEXT:    ret
+;
+; CHECK64-IZHINXMIN-LABEL: fcvt_h_w_demanded_bits:
+; CHECK64-IZHINXMIN:       # %bb.0:
+; CHECK64-IZHINXMIN-NEXT:    addiw a0, a0, 1
+; CHECK64-IZHINXMIN-NEXT:    fcvt.s.l a2, a0
+; CHECK64-IZHINXMIN-NEXT:    fcvt.h.s a2, a2
+; CHECK64-IZHINXMIN-NEXT:    sh a2, 0(a1)
+; CHECK64-IZHINXMIN-NEXT:    ret
+;
+; CHECK32-IZDINXZHINXMIN-LABEL: fcvt_h_w_demanded_bits:
+; CHECK32-IZDINXZHINXMIN:       # %bb.0:
+; CHECK32-IZDINXZHINXMIN-NEXT:    addi a0, a0, 1
+; CHECK32-IZDINXZHINXMIN-NEXT:    fcvt.s.w a2, a0
+; CHECK32-IZDINXZHINXMIN-NEXT:    fcvt.h.s a2, a2
+; CHECK32-IZDINXZHINXMIN-NEXT:    sh a2, 0(a1)
+; CHECK32-IZDINXZHINXMIN-NEXT:    ret
+;
+; CHECK64-IZDINXZHINXMIN-LABEL: fcvt_h_w_demanded_bits:
+; CHECK64-IZDINXZHINXMIN:       # %bb.0:
+; CHECK64-IZDINXZHINXMIN-NEXT:    addiw a0, a0, 1
+; CHECK64-IZDINXZHINXMIN-NEXT:    fcvt.s.l a2, a0
+; CHECK64-IZDINXZHINXMIN-NEXT:    fcvt.h.s a2, a2
+; CHECK64-IZDINXZHINXMIN-NEXT:    sh a2, 0(a1)
+; CHECK64-IZDINXZHINXMIN-NEXT:    ret
   %3 = add i32 %0, 1
   %4 = call half @llvm.experimental.constrained.sitofp.f16.i32(i32 %3, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
   store half %4, ptr %1, align 2
   ret i32 %3
 }
 
 ; Make sure we select W version of addi on RV64.
 define signext i32 @fcvt_h_wu_demanded_bits(i32 signext %0, ptr %1) {
 ; RV32IZFH-LABEL: fcvt_h_wu_demanded_bits:
 ; RV32IZFH:       # %bb.0:
 ; RV32IZFH-NEXT:    addi a0, a0, 1
 ; RV32IZFH-NEXT:    fcvt.h.wu fa5, a0
 ; RV32IZFH-NEXT:    fsh fa5, 0(a1)
 ; RV32IZFH-NEXT:    ret
 ;
 ; RV64IZFH-LABEL: fcvt_h_wu_demanded_bits:
 ; RV64IZFH:       # %bb.0:
 ; RV64IZFH-NEXT:    addiw a0, a0, 1
 ; RV64IZFH-NEXT:    fcvt.h.wu fa5, a0
 ; RV64IZFH-NEXT:    fsh fa5, 0(a1)
 ; RV64IZFH-NEXT:    ret
 ;
+; RV32IZHINX-LABEL: fcvt_h_wu_demanded_bits:
+; RV32IZHINX:       # %bb.0:
+; RV32IZHINX-NEXT:    addi a0, a0, 1
+; RV32IZHINX-NEXT:    fcvt.h.wu a2, a0
+; RV32IZHINX-NEXT:    sh a2, 0(a1)
+; RV32IZHINX-NEXT:    ret
+;
+; RV64IZHINX-LABEL: fcvt_h_wu_demanded_bits:
+; RV64IZHINX:       # %bb.0:
+; RV64IZHINX-NEXT:    addiw a0, a0, 1
+; RV64IZHINX-NEXT:    fcvt.h.wu a2, a0
+; RV64IZHINX-NEXT:    sh a2, 0(a1)
+; RV64IZHINX-NEXT:    ret
+;
 ; RV32IDZFH-LABEL: fcvt_h_wu_demanded_bits:
 ; RV32IDZFH:       # %bb.0:
 ; RV32IDZFH-NEXT:    addi a0, a0, 1
 ; RV32IDZFH-NEXT:    fcvt.h.wu fa5, a0
 ; RV32IDZFH-NEXT:    fsh fa5, 0(a1)
 ; RV32IDZFH-NEXT:    ret
 ;
 ; RV64IDZFH-LABEL: fcvt_h_wu_demanded_bits:
 ; RV64IDZFH:       # %bb.0:
 ; RV64IDZFH-NEXT:    addiw a0, a0, 1
 ; RV64IDZFH-NEXT:    fcvt.h.wu fa5, a0
 ; RV64IDZFH-NEXT:    fsh fa5, 0(a1)
 ; RV64IDZFH-NEXT:    ret
 ;
+; RV32IZDINXZHINX-LABEL: fcvt_h_wu_demanded_bits:
+; RV32IZDINXZHINX:       # %bb.0:
+; RV32IZDINXZHINX-NEXT:    addi a0, a0, 1
+; RV32IZDINXZHINX-NEXT:    fcvt.h.wu a2, a0
+; RV32IZDINXZHINX-NEXT:    sh a2, 0(a1)
+; RV32IZDINXZHINX-NEXT:    ret
+;
+; RV64IZDINXZHINX-LABEL: fcvt_h_wu_demanded_bits:
+; RV64IZDINXZHINX:       # %bb.0:
+; RV64IZDINXZHINX-NEXT:    addiw a0, a0, 1
+; RV64IZDINXZHINX-NEXT:    fcvt.h.wu a2, a0
+; RV64IZDINXZHINX-NEXT:    sh a2, 0(a1)
+; RV64IZDINXZHINX-NEXT:    ret
+;
 ; CHECK32-IZFHMIN-LABEL: fcvt_h_wu_demanded_bits:
 ; CHECK32-IZFHMIN:       # %bb.0:
 ; CHECK32-IZFHMIN-NEXT:    addi a0, a0, 1
 ; CHECK32-IZFHMIN-NEXT:    fcvt.s.wu fa5, a0
 ; CHECK32-IZFHMIN-NEXT:    fcvt.h.s fa5, fa5
 ; CHECK32-IZFHMIN-NEXT:    fsh fa5, 0(a1)
 ; CHECK32-IZFHMIN-NEXT:    ret
 ;
 ; CHECK64-IZFHMIN-LABEL: fcvt_h_wu_demanded_bits:
 ; CHECK64-IZFHMIN:       # %bb.0:
 ; CHECK64-IZFHMIN-NEXT:    addiw a0, a0, 1
 ; CHECK64-IZFHMIN-NEXT:    slli a2, a0, 32
 ; CHECK64-IZFHMIN-NEXT:    srli a2, a2, 32
 ; CHECK64-IZFHMIN-NEXT:    fcvt.s.lu fa5, a2
 ; CHECK64-IZFHMIN-NEXT:    fcvt.h.s fa5, fa5
 ; CHECK64-IZFHMIN-NEXT:    fsh fa5, 0(a1)
 ; CHECK64-IZFHMIN-NEXT:    ret
+;
+; CHECK32-IZHINXMIN-LABEL: fcvt_h_wu_demanded_bits:
+; CHECK32-IZHINXMIN:       # %bb.0:
+; CHECK32-IZHINXMIN-NEXT:    addi a0, a0, 1
+; CHECK32-IZHINXMIN-NEXT:    fcvt.s.wu a2, a0
+; CHECK32-IZHINXMIN-NEXT:    fcvt.h.s a2, a2
+; CHECK32-IZHINXMIN-NEXT:    sh a2, 0(a1)
+; CHECK32-IZHINXMIN-NEXT:    ret
+;
+; CHECK64-IZHINXMIN-LABEL: fcvt_h_wu_demanded_bits:
+; CHECK64-IZHINXMIN:       # %bb.0:
+; CHECK64-IZHINXMIN-NEXT:    addiw a0, a0, 1
+; CHECK64-IZHINXMIN-NEXT:    slli a2, a0, 32
+; CHECK64-IZHINXMIN-NEXT:    srli a2, a2, 32
+; CHECK64-IZHINXMIN-NEXT:    fcvt.s.lu a2, a2
+; CHECK64-IZHINXMIN-NEXT:    fcvt.h.s a2, a2
+; CHECK64-IZHINXMIN-NEXT:    sh a2, 0(a1)
+; CHECK64-IZHINXMIN-NEXT:    ret
+;
+; CHECK32-IZDINXZHINXMIN-LABEL: fcvt_h_wu_demanded_bits:
+; CHECK32-IZDINXZHINXMIN:       # %bb.0:
+; CHECK32-IZDINXZHINXMIN-NEXT:    addi a0, a0, 1
+; CHECK32-IZDINXZHINXMIN-NEXT:    fcvt.s.wu a2, a0
+; CHECK32-IZDINXZHINXMIN-NEXT:    fcvt.h.s a2, a2
+; CHECK32-IZDINXZHINXMIN-NEXT:    sh a2, 0(a1)
+; CHECK32-IZDINXZHINXMIN-NEXT:    ret
+;
+; CHECK64-IZDINXZHINXMIN-LABEL: fcvt_h_wu_demanded_bits:
+; CHECK64-IZDINXZHINXMIN:       # %bb.0:
+; CHECK64-IZDINXZHINXMIN-NEXT:    addiw a0, a0, 1
+; CHECK64-IZDINXZHINXMIN-NEXT:    slli a2, a0, 32
+; CHECK64-IZDINXZHINXMIN-NEXT:    srli a2, a2, 32
+; CHECK64-IZDINXZHINXMIN-NEXT:    fcvt.s.lu a2, a2
+; CHECK64-IZDINXZHINXMIN-NEXT:    fcvt.h.s a2, a2
+; CHECK64-IZDINXZHINXMIN-NEXT:    sh a2, 0(a1)
+; CHECK64-IZDINXZHINXMIN-NEXT:    ret
   %3 = add i32 %0, 1
   %4 = call half @llvm.experimental.constrained.uitofp.f16.i32(i32 %3, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
   store half %4, ptr %1, align 2
   ret i32 %3
 }
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; RV32IZDINXZHINXMIN: {{.*}}
+; RV32IZHINXMIN: {{.*}}
+; RV64IZDINXZHINXMIN: {{.*}}
+; RV64IZHINXMIN: {{.*}}

llvm/test/CodeGen/RISCV/half-convert.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -mattr=+zfh -verify-machineinstrs \
 ; RUN:   -target-abi ilp32f < %s | FileCheck -check-prefixes=CHECKIZFH,RV32IZFH %s
 ; RUN: llc -mtriple=riscv64 -mattr=+zfh -verify-machineinstrs \
 ; RUN:   -target-abi lp64f < %s | FileCheck -check-prefixes=CHECKIZFH,RV64IZFH %s
 ; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh -verify-machineinstrs \
 ; RUN:   -target-abi ilp32d < %s | FileCheck -check-prefix=RV32IDZFH %s
 ; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh -verify-machineinstrs \
 ; RUN:   -target-abi lp64d < %s | FileCheck -check-prefix=RV64IDZFH %s
+; RUN: llc -mtriple=riscv32 -mattr=+zhinx -verify-machineinstrs \
+; RUN:   -target-abi ilp32 < %s | FileCheck -check-prefixes=CHECKIZHINX,RV32IZHINX %s
+; RUN: llc -mtriple=riscv64 -mattr=+zhinx -verify-machineinstrs \
+; RUN:   -target-abi lp64 < %s | FileCheck -check-prefixes=CHECKIZHINX,RV64IZHINX %s
+; RUN: llc -mtriple=riscv32 -mattr=+zdinx,+zhinx -verify-machineinstrs \
+; RUN:   -target-abi ilp32 < %s | FileCheck -check-prefixes=CHECKIZDINXZHINX,RV32IZDINXZHINX %s
+; RUN: llc -mtriple=riscv64 -mattr=+zdinx,+zhinx -verify-machineinstrs \
+; RUN:   -target-abi lp64 < %s | FileCheck -check-prefixes=CHECKIZDINXZHINX,RV64IZDINXZHINX %s
 ; RUN: llc -mtriple=riscv32 -verify-machineinstrs \
 ; RUN:   < %s | FileCheck -check-prefix=RV32I %s
 ; RUN: llc -mtriple=riscv64 -verify-machineinstrs \
 ; RUN:   < %s | FileCheck -check-prefix=RV64I %s
 ; RUN: llc -mtriple=riscv32 -mattr=+zfhmin -verify-machineinstrs \
 ; RUN:   -target-abi ilp32f < %s | FileCheck -check-prefixes=CHECK32-IZFHMIN,RV32IFZFHMIN %s
 ; RUN: llc -mtriple=riscv64 -mattr=+zfhmin -verify-machineinstrs \
 ; RUN:   -target-abi lp64f < %s | FileCheck -check-prefixes=CHECK64-IZFHMIN,RV64IFZFHMIN %s
 ; RUN: llc -mtriple=riscv32 -mattr=+d,+zfhmin -verify-machineinstrs \
 ; RUN:   -target-abi ilp32d < %s | FileCheck -check-prefixes=CHECK32-IZFHMIN,RV32IDZFHMIN %s
 ; RUN: llc -mtriple=riscv64 -mattr=+d,+zfhmin -verify-machineinstrs \
 ; RUN:   -target-abi lp64d < %s | FileCheck -check-prefixes=CHECK64-IZFHMIN,RV64IDZFHMIN %s
+; RUN: llc -mtriple=riscv32 -mattr=+zhinxmin -verify-machineinstrs \
+; RUN:   -target-abi ilp32 < %s | FileCheck -check-prefixes=CHECK32-IZHINXMIN,RV32IZHINXMIN %s
+; RUN: llc -mtriple=riscv64 -mattr=+zhinxmin -verify-machineinstrs \
+; RUN:   -target-abi lp64 < %s | FileCheck -check-prefixes=CHECK64-IZHINXMIN,RV64IZHINXMIN %s
+; RUN: llc -mtriple=riscv32 -mattr=+zdinx,+zhinxmin -verify-machineinstrs \
+; RUN:   -target-abi ilp32 < %s | FileCheck -check-prefixes=CHECK32-IZDINXZHINXMIN,RV32IZDINXZHINXMIN %s
+; RUN: llc -mtriple=riscv64 -mattr=+zdinx,+zhinxmin -verify-machineinstrs \
+; RUN:   -target-abi lp64 < %s | FileCheck -check-prefixes=CHECK64-IZDINXZHINXMIN,RV64IZDINXZHINXMIN %s
 
 define i16 @fcvt_si_h(half %a) nounwind {
 ; RV32IZFH-LABEL: fcvt_si_h:
 ; RV32IZFH:       # %bb.0:
 ; RV32IZFH-NEXT:    fcvt.w.h a0, fa0, rtz
 ; RV32IZFH-NEXT:    ret
 ;
 ; RV64IZFH-LABEL: fcvt_si_h:
 ; RV64IZFH:       # %bb.0:
 ; RV64IZFH-NEXT:    fcvt.l.h a0, fa0, rtz
 ; RV64IZFH-NEXT:    ret
 ;
 ; RV32IDZFH-LABEL: fcvt_si_h:
 ; RV32IDZFH:       # %bb.0:
 ; RV32IDZFH-NEXT:    fcvt.w.h a0, fa0, rtz
 ; RV32IDZFH-NEXT:    ret
 ;
 ; RV64IDZFH-LABEL: fcvt_si_h:
 ; RV64IDZFH:       # %bb.0:
 ; RV64IDZFH-NEXT:    fcvt.l.h a0, fa0, rtz
 ; RV64IDZFH-NEXT:    ret
 ;
+; RV32IZHINX-LABEL: fcvt_si_h:
+; RV32IZHINX:       # %bb.0:
+; RV32IZHINX-NEXT:    fcvt.w.h a0, a0, rtz
+; RV32IZHINX-NEXT:    ret
+;
+; RV64IZHINX-LABEL: fcvt_si_h:
+; RV64IZHINX:       # %bb.0:
+; RV64IZHINX-NEXT:    fcvt.l.h a0, a0, rtz
+; RV64IZHINX-NEXT:    ret
+;
+; RV32IZDINXZHINX-LABEL: fcvt_si_h:
+; RV32IZDINXZHINX:       # %bb.0:
+; RV32IZDINXZHINX-NEXT:    fcvt.w.h a0, a0, rtz
+; RV32IZDINXZHINX-NEXT:    ret
+;
+; RV64IZDINXZHINX-LABEL: fcvt_si_h:
+; RV64IZDINXZHINX:       # %bb.0:
+; RV64IZDINXZHINX-NEXT:    fcvt.l.h a0, a0, rtz
+; RV64IZDINXZHINX-NEXT:    ret
+;
 ; RV32I-LABEL: fcvt_si_h:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    slli a0, a0, 16
 ; RV32I-NEXT:    srli a0, a0, 16
 ; RV32I-NEXT:    call __extendhfsf2@plt
 ; RV32I-NEXT:    call __fixsfsi@plt

 ; CHECK32-IZFHMIN-NEXT:    fcvt.w.s a0, fa5, rtz
 ; CHECK32-IZFHMIN-NEXT:    ret
 ;
 ; CHECK64-IZFHMIN-LABEL: fcvt_si_h:
 ; CHECK64-IZFHMIN:       # %bb.0:
 ; CHECK64-IZFHMIN-NEXT:    fcvt.s.h fa5, fa0
 ; CHECK64-IZFHMIN-NEXT:    fcvt.l.s a0, fa5, rtz
 ; CHECK64-IZFHMIN-NEXT:    ret
+;
+; CHECK32-IZHINXMIN-LABEL: fcvt_si_h:
+; CHECK32-IZHINXMIN:       # %bb.0:
+; CHECK32-IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECK32-IZHINXMIN-NEXT:    fcvt.w.s a0, a0, rtz
+; CHECK32-IZHINXMIN-NEXT:    ret
+;
+; CHECK64-IZHINXMIN-LABEL: fcvt_si_h:
+; CHECK64-IZHINXMIN:       # %bb.0:
+; CHECK64-IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECK64-IZHINXMIN-NEXT:    fcvt.l.s a0, a0, rtz
+; CHECK64-IZHINXMIN-NEXT:    ret
+;
+; CHECK32-IZDINXZHINXMIN-LABEL: fcvt_si_h:
+; CHECK32-IZDINXZHINXMIN:       # %bb.0:
+; CHECK32-IZDINXZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECK32-IZDINXZHINXMIN-NEXT:    fcvt.w.s a0, a0, rtz
+; CHECK32-IZDINXZHINXMIN-NEXT:    ret
+;
+; CHECK64-IZDINXZHINXMIN-LABEL: fcvt_si_h:
+; CHECK64-IZDINXZHINXMIN:       # %bb.0:
+; CHECK64-IZDINXZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECK64-IZDINXZHINXMIN-NEXT:    fcvt.l.s a0, a0, rtz
+; CHECK64-IZDINXZHINXMIN-NEXT:    ret
   %1 = fptosi half %a to i16
   ret i16 %1
 }
 
 define i16 @fcvt_si_h_sat(half %a) nounwind {
 ; RV32IZFH-LABEL: fcvt_si_h_sat:
 ; RV32IZFH:       # %bb.0: # %start
 ; RV32IZFH-NEXT:    fcvt.s.h fa5, fa0

 ; RV64IDZFH-NEXT:    fmv.w.x fa3, a1
 ; RV64IDZFH-NEXT:    fmax.s fa5, fa5, fa3
 ; RV64IDZFH-NEXT:    neg a0, a0
 ; RV64IDZFH-NEXT:    fmin.s fa5, fa5, fa4
 ; RV64IDZFH-NEXT:    fcvt.l.s a1, fa5, rtz
 ; RV64IDZFH-NEXT:    and a0, a0, a1
 ; RV64IDZFH-NEXT:    ret
 ;
+; RV32IZHINX-LABEL: fcvt_si_h_sat:
+; RV32IZHINX:       # %bb.0: # %start
+; RV32IZHINX-NEXT:    fcvt.s.h a0, a0
+; RV32IZHINX-NEXT:    feq.s a1, a0, a0
+; RV32IZHINX-NEXT:    lui a2, %hi(.LCPI1_0)
+; RV32IZHINX-NEXT:    lw a2, %lo(.LCPI1_0)(a2)
+; RV32IZHINX-NEXT:    neg a1, a1
+; RV32IZHINX-NEXT:    lui a3, 815104
+; RV32IZHINX-NEXT:    fmax.s a0, a0, a3
+; RV32IZHINX-NEXT:    fmin.s a0, a0, a2
+; RV32IZHINX-NEXT:    fcvt.w.s a0, a0, rtz
+; RV32IZHINX-NEXT:    and a0, a1, a0
+; RV32IZHINX-NEXT:    ret
+;
+; RV64IZHINX-LABEL: fcvt_si_h_sat:
+; RV64IZHINX:       # %bb.0: # %start
+; RV64IZHINX-NEXT:    fcvt.s.h a0, a0
+; RV64IZHINX-NEXT:    lui a1, 815104
+; RV64IZHINX-NEXT:    lui a2, %hi(.LCPI1_0)
+; RV64IZHINX-NEXT:    lw a2, %lo(.LCPI1_0)(a2)
+; RV64IZHINX-NEXT:    fmax.s a1, a0, a1
+; RV64IZHINX-NEXT:    feq.s a0, a0, a0
+; RV64IZHINX-NEXT:    neg a0, a0
+; RV64IZHINX-NEXT:    fmin.s a1, a1, a2
+; RV64IZHINX-NEXT:    fcvt.l.s a1, a1, rtz
+; RV64IZHINX-NEXT:    and a0, a0, a1
+; RV64IZHINX-NEXT:    ret
+;
+; RV32IZDINXZHINX-LABEL: fcvt_si_h_sat:
+; RV32IZDINXZHINX:       # %bb.0: # %start
+; RV32IZDINXZHINX-NEXT:    fcvt.s.h a0, a0
+; RV32IZDINXZHINX-NEXT:    feq.s a1, a0, a0
+; RV32IZDINXZHINX-NEXT:    lui a2, %hi(.LCPI1_0)
+; RV32IZDINXZHINX-NEXT:    lw a2, %lo(.LCPI1_0)(a2)
+; RV32IZDINXZHINX-NEXT:    neg a1, a1
+; RV32IZDINXZHINX-NEXT:    lui a3, 815104
+; RV32IZDINXZHINX-NEXT:    fmax.s a0, a0, a3
+; RV32IZDINXZHINX-NEXT:    fmin.s a0, a0, a2
+; RV32IZDINXZHINX-NEXT:    fcvt.w.s a0, a0, rtz
+; RV32IZDINXZHINX-NEXT:    and a0, a1, a0
+; RV32IZDINXZHINX-NEXT:    ret
+;
+; RV64IZDINXZHINX-LABEL: fcvt_si_h_sat:
+; RV64IZDINXZHINX:       # %bb.0: # %start
+; RV64IZDINXZHINX-NEXT:    fcvt.s.h a0, a0
+; RV64IZDINXZHINX-NEXT:    lui a1, 815104
+; RV64IZDINXZHINX-NEXT:    lui a2, %hi(.LCPI1_0)
+; RV64IZDINXZHINX-NEXT:    lw a2, %lo(.LCPI1_0)(a2)
+; RV64IZDINXZHINX-NEXT:    fmax.s a1, a0, a1
+; RV64IZDINXZHINX-NEXT:    feq.s a0, a0, a0
+; RV64IZDINXZHINX-NEXT:    neg a0, a0
+; RV64IZDINXZHINX-NEXT:    fmin.s a1, a1, a2
+; RV64IZDINXZHINX-NEXT:    fcvt.l.s a1, a1, rtz
+; RV64IZDINXZHINX-NEXT:    and a0, a0, a1
+; RV64IZDINXZHINX-NEXT:    ret
+;
 ; RV32I-LABEL: fcvt_si_h_sat:
 ; RV32I:       # %bb.0: # %start
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s2, 0(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    slli a0, a0, 16

 ; CHECK64-IZFHMIN-NEXT:    lui a1, 815104
 ; CHECK64-IZFHMIN-NEXT:    fmv.w.x fa3, a1
 ; CHECK64-IZFHMIN-NEXT:    fmax.s fa5, fa5, fa3
 ; CHECK64-IZFHMIN-NEXT:    neg a0, a0
 ; CHECK64-IZFHMIN-NEXT:    fmin.s fa5, fa5, fa4
 ; CHECK64-IZFHMIN-NEXT:    fcvt.l.s a1, fa5, rtz
 ; CHECK64-IZFHMIN-NEXT:    and a0, a0, a1
 ; CHECK64-IZFHMIN-NEXT:    ret
+;
+; CHECK32-IZHINXMIN-LABEL: fcvt_si_h_sat:
+; CHECK32-IZHINXMIN:       # %bb.0: # %start
+; CHECK32-IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECK32-IZHINXMIN-NEXT:    feq.s a1, a0, a0
+; CHECK32-IZHINXMIN-NEXT:    lui a2, %hi(.LCPI1_0)
+; CHECK32-IZHINXMIN-NEXT:    lw a2, %lo(.LCPI1_0)(a2)
+; CHECK32-IZHINXMIN-NEXT:    neg a1, a1
+; CHECK32-IZHINXMIN-NEXT:    lui a3, 815104
+; CHECK32-IZHINXMIN-NEXT:    fmax.s a0, a0, a3
+; CHECK32-IZHINXMIN-NEXT:    fmin.s a0, a0, a2
+; CHECK32-IZHINXMIN-NEXT:    fcvt.w.s a0, a0, rtz
+; CHECK32-IZHINXMIN-NEXT:    and a0, a1, a0
+; CHECK32-IZHINXMIN-NEXT:    ret
+;
+; CHECK64-IZHINXMIN-LABEL: fcvt_si_h_sat:
+; CHECK64-IZHINXMIN:       # %bb.0: # %start
+; CHECK64-IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECK64-IZHINXMIN-NEXT:    lui a1, 815104
+; CHECK64-IZHINXMIN-NEXT:    lui a2, %hi(.LCPI1_0)
+; CHECK64-IZHINXMIN-NEXT:    lw a2, %lo(.LCPI1_0)(a2)
+; CHECK64-IZHINXMIN-NEXT:    fmax.s a1, a0, a1
+; CHECK64-IZHINXMIN-NEXT:    feq.s a0, a0, a0
+; CHECK64-IZHINXMIN-NEXT:    neg a0, a0
+; CHECK64-IZHINXMIN-NEXT:    fmin.s a1, a1, a2
+; CHECK64-IZHINXMIN-NEXT:    fcvt.l.s a1, a1, rtz
+; CHECK64-IZHINXMIN-NEXT:    and a0, a0, a1
+; CHECK64-IZHINXMIN-NEXT:    ret
+;
+; CHECK32-IZDINXZHINXMIN-LABEL: fcvt_si_h_sat:
+; CHECK32-IZDINXZHINXMIN:       # %bb.0: # %start
+; CHECK32-IZDINXZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECK32-IZDINXZHINXMIN-NEXT:    feq.s a1, a0, a0
+; CHECK32-IZDINXZHINXMIN-NEXT:    lui a2, %hi(.LCPI1_0)
+; CHECK32-IZDINXZHINXMIN-NEXT:    lw a2, %lo(.LCPI1_0)(a2)
+; CHECK32-IZDINXZHINXMIN-NEXT:    neg a1, a1
+; CHECK32-IZDINXZHINXMIN-NEXT:    lui a3, 815104
+; CHECK32-IZDINXZHINXMIN-NEXT:    fmax.s a0, a0, a3
+; CHECK32-IZDINXZHINXMIN-NEXT:    fmin.s a0, a0, a2
+; CHECK32-IZDINXZHINXMIN-NEXT:    fcvt.w.s a0, a0, rtz
+; CHECK32-IZDINXZHINXMIN-NEXT:    and a0, a1, a0
+; CHECK32-IZDINXZHINXMIN-NEXT:    ret
+;
+; CHECK64-IZDINXZHINXMIN-LABEL: fcvt_si_h_sat:
+; CHECK64-IZDINXZHINXMIN:       # %bb.0: # %start
+; CHECK64-IZDINXZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECK64-IZDINXZHINXMIN-NEXT:    lui a1, 815104
+; CHECK64-IZDINXZHINXMIN-NEXT:    lui a2, %hi(.LCPI1_0)
+; CHECK64-IZDINXZHINXMIN-NEXT:    lw a2, %lo(.LCPI1_0)(a2)
+; CHECK64-IZDINXZHINXMIN-NEXT:    fmax.s a1, a0, a1
+; CHECK64-IZDINXZHINXMIN-NEXT:    feq.s a0, a0, a0
+; CHECK64-IZDINXZHINXMIN-NEXT:    neg a0, a0
+; CHECK64-IZDINXZHINXMIN-NEXT:    fmin.s a1, a1, a2
+; CHECK64-IZDINXZHINXMIN-NEXT:    fcvt.l.s a1, a1, rtz
+; CHECK64-IZDINXZHINXMIN-NEXT:    and a0, a0, a1
+; CHECK64-IZDINXZHINXMIN-NEXT:    ret
 start:
   %0 = tail call i16 @llvm.fptosi.sat.i16.f16(half %a)
   ret i16 %0
 }
 declare i16 @llvm.fptosi.sat.i16.f16(half)
 
 define i16 @fcvt_ui_h(half %a) nounwind {
 ; RV32IZFH-LABEL: fcvt_ui_h:

 ; RV32IDZFH-NEXT:    fcvt.wu.h a0, fa0, rtz
 ; RV32IDZFH-NEXT:    ret
 ;
 ; RV64IDZFH-LABEL: fcvt_ui_h:
 ; RV64IDZFH:       # %bb.0:
 ; RV64IDZFH-NEXT:    fcvt.lu.h a0, fa0, rtz
 ; RV64IDZFH-NEXT:    ret
 ;
+; RV32IZHINX-LABEL: fcvt_ui_h:
+; RV32IZHINX:       # %bb.0:
+; RV32IZHINX-NEXT:    fcvt.wu.h a0, a0, rtz
+; RV32IZHINX-NEXT:    ret
+;
+; RV64IZHINX-LABEL: fcvt_ui_h:
+; RV64IZHINX:       # %bb.0:
+; RV64IZHINX-NEXT:    fcvt.lu.h a0, a0, rtz
+; RV64IZHINX-NEXT:    ret
+;
+; RV32IZDINXZHINX-LABEL: fcvt_ui_h:
+; RV32IZDINXZHINX:       # %bb.0:
+; RV32IZDINXZHINX-NEXT:    fcvt.wu.h a0, a0, rtz
+; RV32IZDINXZHINX-NEXT:    ret
+;
+; RV64IZDINXZHINX-LABEL: fcvt_ui_h:
+; RV64IZDINXZHINX:       # %bb.0:
+; RV64IZDINXZHINX-NEXT:    fcvt.lu.h a0, a0, rtz
+; RV64IZDINXZHINX-NEXT:    ret
+;
 ; RV32I-LABEL: fcvt_ui_h:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    slli a0, a0, 16
 ; RV32I-NEXT:    srli a0, a0, 16
 ; RV32I-NEXT:    call __extendhfsf2@plt
 ; RV32I-NEXT:    call __fixunssfsi@plt

 ; CHECK32-IZFHMIN-NEXT:    fcvt.wu.s a0, fa5, rtz
 ; CHECK32-IZFHMIN-NEXT:    ret
 ;
 ; CHECK64-IZFHMIN-LABEL: fcvt_ui_h:
 ; CHECK64-IZFHMIN:       # %bb.0:
 ; CHECK64-IZFHMIN-NEXT:    fcvt.s.h fa5, fa0
 ; CHECK64-IZFHMIN-NEXT:    fcvt.lu.s a0, fa5, rtz
 ; CHECK64-IZFHMIN-NEXT:    ret
+;
+; CHECK32-IZHINXMIN-LABEL: fcvt_ui_h:
+; CHECK32-IZHINXMIN:       # %bb.0:
+; CHECK32-IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECK32-IZHINXMIN-NEXT:    fcvt.wu.s a0, a0, rtz
+; CHECK32-IZHINXMIN-NEXT:    ret
+;
+; CHECK64-IZHINXMIN-LABEL: fcvt_ui_h:
+; CHECK64-IZHINXMIN:       # %bb.0:
+; CHECK64-IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECK64-IZHINXMIN-NEXT:    fcvt.lu.s a0, a0, rtz
+; CHECK64-IZHINXMIN-NEXT:    ret
+;
+; CHECK32-IZDINXZHINXMIN-LABEL: fcvt_ui_h:
+; CHECK32-IZDINXZHINXMIN:       # %bb.0:
+; CHECK32-IZDINXZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECK32-IZDINXZHINXMIN-NEXT:    fcvt.wu.s a0, a0, rtz
+; CHECK32-IZDINXZHINXMIN-NEXT:    ret
+;
+; CHECK64-IZDINXZHINXMIN-LABEL: fcvt_ui_h:
+; CHECK64-IZDINXZHINXMIN:       # %bb.0:
+; CHECK64-IZDINXZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECK64-IZDINXZHINXMIN-NEXT:    fcvt.lu.s a0, a0, rtz
+; CHECK64-IZDINXZHINXMIN-NEXT:    ret
   %1 = fptoui half %a to i16
   ret i16 %1
 }
 
 define i16 @fcvt_ui_h_sat(half %a) nounwind {
 ; RV32IZFH-LABEL: fcvt_ui_h_sat:
 ; RV32IZFH:       # %bb.0: # %start
 ; RV32IZFH-NEXT:    lui a0, %hi(.LCPI3_0)

 ; RV64IDZFH-NEXT:    flw fa5, %lo(.LCPI3_0)(a0)
 ; RV64IDZFH-NEXT:    fcvt.s.h fa4, fa0
 ; RV64IDZFH-NEXT:    fmv.w.x fa3, zero
 ; RV64IDZFH-NEXT:    fmax.s fa4, fa4, fa3
 ; RV64IDZFH-NEXT:    fmin.s fa5, fa4, fa5
 ; RV64IDZFH-NEXT:    fcvt.lu.s a0, fa5, rtz
 ; RV64IDZFH-NEXT:    ret
 ;
+; RV32IZHINX-LABEL: fcvt_ui_h_sat:
+; RV32IZHINX:       # %bb.0: # %start
+; RV32IZHINX-NEXT:    lui a1, %hi(.LCPI3_0)
+; RV32IZHINX-NEXT:    lw a1, %lo(.LCPI3_0)(a1)
+; RV32IZHINX-NEXT:    fcvt.s.h a0, a0
+; RV32IZHINX-NEXT:    fmax.s a0, a0, zero
+; RV32IZHINX-NEXT:    fmin.s a0, a0, a1
+; RV32IZHINX-NEXT:    fcvt.wu.s a0, a0, rtz
+; RV32IZHINX-NEXT:    ret
+;
+; RV64IZHINX-LABEL: fcvt_ui_h_sat:
+; RV64IZHINX:       # %bb.0: # %start
+; RV64IZHINX-NEXT:    lui a1, %hi(.LCPI3_0)
+; RV64IZHINX-NEXT:    lw a1, %lo(.LCPI3_0)(a1)
+; RV64IZHINX-NEXT:    fcvt.s.h a0, a0
+; RV64IZHINX-NEXT:    fmax.s a0, a0, zero
+; RV64IZHINX-NEXT:    fmin.s a0, a0, a1
+; RV64IZHINX-NEXT:    fcvt.lu.s a0, a0, rtz
+; RV64IZHINX-NEXT:    ret
+;
+; RV32IZDINXZHINX-LABEL: fcvt_ui_h_sat:
+; RV32IZDINXZHINX:       # %bb.0: # %start
+; RV32IZDINXZHINX-NEXT:    lui a1, %hi(.LCPI3_0)
+; RV32IZDINXZHINX-NEXT:    lw a1, %lo(.LCPI3_0)(a1)
+; RV32IZDINXZHINX-NEXT:    fcvt.s.h a0, a0
+; RV32IZDINXZHINX-NEXT:    fmax.s a0, a0, zero
+; RV32IZDINXZHINX-NEXT:    fmin.s a0, a0, a1
+; RV32IZDINXZHINX-NEXT:    fcvt.wu.s a0, a0, rtz
+; RV32IZDINXZHINX-NEXT:    ret
+;
+; RV64IZDINXZHINX-LABEL: fcvt_ui_h_sat:
+; RV64IZDINXZHINX:       # %bb.0: # %start
+; RV64IZDINXZHINX-NEXT:    lui a1, %hi(.LCPI3_0)
+; RV64IZDINXZHINX-NEXT:    lw a1, %lo(.LCPI3_0)(a1)
+; RV64IZDINXZHINX-NEXT:    fcvt.s.h a0, a0
+; RV64IZDINXZHINX-NEXT:    fmax.s a0, a0, zero
+; RV64IZDINXZHINX-NEXT:    fmin.s a0, a0, a1
+; RV64IZDINXZHINX-NEXT:    fcvt.lu.s a0, a0, rtz
+; RV64IZDINXZHINX-NEXT:    ret
+;
 ; RV32I-LABEL: fcvt_ui_h_sat:
 ; RV32I:       # %bb.0: # %start
 ; RV32I-NEXT:    addi sp, sp, -32
 ; RV32I-NEXT:    sw ra, 28(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s0, 24(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s1, 20(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s2, 16(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s3, 12(sp) # 4-byte Folded Spill

 ; CHECK64-IZFHMIN-NEXT:    lui a0, %hi(.LCPI3_0)
 ; CHECK64-IZFHMIN-NEXT:    flw fa5, %lo(.LCPI3_0)(a0)
 ; CHECK64-IZFHMIN-NEXT:    fcvt.s.h fa4, fa0
 ; CHECK64-IZFHMIN-NEXT:    fmv.w.x fa3, zero
 ; CHECK64-IZFHMIN-NEXT:    fmax.s fa4, fa4, fa3
 ; CHECK64-IZFHMIN-NEXT:    fmin.s fa5, fa4, fa5
 ; CHECK64-IZFHMIN-NEXT:    fcvt.lu.s a0, fa5, rtz
 ; CHECK64-IZFHMIN-NEXT:    ret
+;
+; CHECK32-IZHINXMIN-LABEL: fcvt_ui_h_sat:
+; CHECK32-IZHINXMIN:       # %bb.0: # %start
+; CHECK32-IZHINXMIN-NEXT:    lui a1, %hi(.LCPI3_0)
+; CHECK32-IZHINXMIN-NEXT:    lw a1, %lo(.LCPI3_0)(a1)
+; CHECK32-IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECK32-IZHINXMIN-NEXT:    fmax.s a0, a0, zero
+; CHECK32-IZHINXMIN-NEXT:    fmin.s a0, a0, a1
+; CHECK32-IZHINXMIN-NEXT:    fcvt.wu.s a0, a0, rtz
+; CHECK32-IZHINXMIN-NEXT:    ret
+;
+; CHECK64-IZHINXMIN-LABEL: fcvt_ui_h_sat:
+; CHECK64-IZHINXMIN:       # %bb.0: # %start
+; CHECK64-IZHINXMIN-NEXT:    lui a1, %hi(.LCPI3_0)
+; CHECK64-IZHINXMIN-NEXT:    lw a1, %lo(.LCPI3_0)(a1)
+; CHECK64-IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECK64-IZHINXMIN-NEXT:    fmax.s a0, a0, zero
+; CHECK64-IZHINXMIN-NEXT:    fmin.s a0, a0, a1
+; CHECK64-IZHINXMIN-NEXT:    fcvt.lu.s a0, a0, rtz
+; CHECK64-IZHINXMIN-NEXT:    ret
+;
+; CHECK32-IZDINXZHINXMIN-LABEL: fcvt_ui_h_sat:
+; CHECK32-IZDINXZHINXMIN:       # %bb.0: # %start
+; CHECK32-IZDINXZHINXMIN-NEXT:    lui a1, %hi(.LCPI3_0)
+; CHECK32-IZDINXZHINXMIN-NEXT:    lw a1, %lo(.LCPI3_0)(a1)
+; CHECK32-IZDINXZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECK32-IZDINXZHINXMIN-NEXT:    fmax.s a0, a0, zero
+; CHECK32-IZDINXZHINXMIN-NEXT:    fmin.s a0, a0, a1
+; CHECK32-IZDINXZHINXMIN-NEXT:    fcvt.wu.s a0, a0, rtz
+; CHECK32-IZDINXZHINXMIN-NEXT:    ret
+;
+; CHECK64-IZDINXZHINXMIN-LABEL: fcvt_ui_h_sat:
+; CHECK64-IZDINXZHINXMIN:       # %bb.0: # %start
+; CHECK64-IZDINXZHINXMIN-NEXT:    lui a1, %hi(.LCPI3_0)
+; CHECK64-IZDINXZHINXMIN-NEXT:    lw a1, %lo(.LCPI3_0)(a1)
+; CHECK64-IZDINXZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECK64-IZDINXZHINXMIN-NEXT:    fmax.s a0, a0, zero
+; CHECK64-IZDINXZHINXMIN-NEXT:    fmin.s a0, a0, a1
+; CHECK64-IZDINXZHINXMIN-NEXT:    fcvt.lu.s a0, a0, rtz
+; CHECK64-IZDINXZHINXMIN-NEXT:    ret
 start:
   %0 = tail call i16 @llvm.fptoui.sat.i16.f16(half %a)
   ret i16 %0
 }
 declare i16 @llvm.fptoui.sat.i16.f16(half)
 
 define i32 @fcvt_w_h(half %a) nounwind {
 ; CHECKIZFH-LABEL: fcvt_w_h:
 ; CHECKIZFH:       # %bb.0:
 ; CHECKIZFH-NEXT:    fcvt.w.h a0, fa0, rtz
 ; CHECKIZFH-NEXT:    ret
 ;
 ; RV32IDZFH-LABEL: fcvt_w_h:
 ; RV32IDZFH:       # %bb.0:
 ; RV32IDZFH-NEXT:    fcvt.w.h a0, fa0, rtz
 ; RV32IDZFH-NEXT:    ret
 ;
 ; RV64IDZFH-LABEL: fcvt_w_h:
 ; RV64IDZFH:       # %bb.0:
 ; RV64IDZFH-NEXT:    fcvt.w.h a0, fa0, rtz
 ; RV64IDZFH-NEXT:    ret
 ;
+; CHECKIZHINX-LABEL: fcvt_w_h:
+; CHECKIZHINX:       # %bb.0:
+; CHECKIZHINX-NEXT:    fcvt.w.h a0, a0, rtz
+; CHECKIZHINX-NEXT:    ret
+;
+; CHECKIZDINXZHINX-LABEL: fcvt_w_h:
+; CHECKIZDINXZHINX:       # %bb.0:
+; CHECKIZDINXZHINX-NEXT:    fcvt.w.h a0, a0, rtz
+; CHECKIZDINXZHINX-NEXT:    ret
+;
 ; RV32I-LABEL: fcvt_w_h:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    slli a0, a0, 16
 ; RV32I-NEXT:    srli a0, a0, 16
 ; RV32I-NEXT:    call __extendhfsf2@plt
 ; RV32I-NEXT:    call __fixsfsi@plt

 ; CHECK32-IZFHMIN-NEXT:    fcvt.w.s a0, fa5, rtz
 ; CHECK32-IZFHMIN-NEXT:    ret
 ;
 ; CHECK64-IZFHMIN-LABEL: fcvt_w_h:
 ; CHECK64-IZFHMIN:       # %bb.0:
 ; CHECK64-IZFHMIN-NEXT:    fcvt.s.h fa5, fa0
 ; CHECK64-IZFHMIN-NEXT:    fcvt.w.s a0, fa5, rtz
 ; CHECK64-IZFHMIN-NEXT:    ret
+;
+; CHECK32-IZHINXMIN-LABEL: fcvt_w_h:
+; CHECK32-IZHINXMIN:       # %bb.0:
+; CHECK32-IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECK32-IZHINXMIN-NEXT:    fcvt.w.s a0, a0, rtz
+; CHECK32-IZHINXMIN-NEXT:    ret
+;
+; CHECK64-IZHINXMIN-LABEL: fcvt_w_h:
+; CHECK64-IZHINXMIN:       # %bb.0:
+; CHECK64-IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECK64-IZHINXMIN-NEXT:    fcvt.w.s a0, a0, rtz
+; CHECK64-IZHINXMIN-NEXT:    ret
+;
+; CHECK32-IZDINXZHINXMIN-LABEL: fcvt_w_h:
+; CHECK32-IZDINXZHINXMIN:       # %bb.0:
+; CHECK32-IZDINXZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECK32-IZDINXZHINXMIN-NEXT:    fcvt.w.s a0, a0, rtz
+; CHECK32-IZDINXZHINXMIN-NEXT:    ret
+;
+; CHECK64-IZDINXZHINXMIN-LABEL: fcvt_w_h:
+; CHECK64-IZDINXZHINXMIN:       # %bb.0:
+; CHECK64-IZDINXZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECK64-IZDINXZHINXMIN-NEXT:    fcvt.w.s a0, a0, rtz
+; CHECK64-IZDINXZHINXMIN-NEXT:    ret
   %1 = fptosi half %a to i32
   ret i32 %1
 }
 
 define i32 @fcvt_w_h_sat(half %a) nounwind {
 ; CHECKIZFH-LABEL: fcvt_w_h_sat:
 ; CHECKIZFH:       # %bb.0: # %start
 ; CHECKIZFH-NEXT:    fcvt.w.h a0, fa0, rtz

 ; RV64IDZFH:       # %bb.0: # %start
 ; RV64IDZFH-NEXT:    fcvt.w.h a0, fa0, rtz
 ; RV64IDZFH-NEXT:    feq.h a1, fa0, fa0
 ; RV64IDZFH-NEXT:    seqz a1, a1
 ; RV64IDZFH-NEXT:    addi a1, a1, -1
 ; RV64IDZFH-NEXT:    and a0, a1, a0
 ; RV64IDZFH-NEXT:    ret
 ;
+; CHECKIZHINX-LABEL: fcvt_w_h_sat:
+; CHECKIZHINX:       # %bb.0: # %start
+; CHECKIZHINX-NEXT:    fcvt.w.h a1, a0, rtz
+; CHECKIZHINX-NEXT:    feq.h a0, a0, a0
+; CHECKIZHINX-NEXT:    seqz a0, a0
+; CHECKIZHINX-NEXT:    addi a0, a0, -1
+; CHECKIZHINX-NEXT:    and a0, a0, a1
+; CHECKIZHINX-NEXT:    ret
+;
+; CHECKIZDINXZHINX-LABEL: fcvt_w_h_sat:
+; CHECKIZDINXZHINX:       # %bb.0: # %start
+; CHECKIZDINXZHINX-NEXT:    fcvt.w.h a1, a0, rtz
+; CHECKIZDINXZHINX-NEXT:    feq.h a0, a0, a0
+; CHECKIZDINXZHINX-NEXT:    seqz a0, a0
+; CHECKIZDINXZHINX-NEXT:    addi a0, a0, -1
+; CHECKIZDINXZHINX-NEXT:    and a0, a0, a1
+; CHECKIZDINXZHINX-NEXT:    ret
+;
 ; RV32I-LABEL: fcvt_w_h_sat:
 ; RV32I:       # %bb.0: # %start
 ; RV32I-NEXT:    addi sp, sp, -32
 ; RV32I-NEXT:    sw ra, 28(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s0, 24(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s1, 20(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s2, 16(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s3, 12(sp) # 4-byte Folded Spill

 ; CHECK64-IZFHMIN:       # %bb.0: # %start
 ; CHECK64-IZFHMIN-NEXT:    fcvt.s.h fa5, fa0
 ; CHECK64-IZFHMIN-NEXT:    fcvt.w.s a0, fa5, rtz
 ; CHECK64-IZFHMIN-NEXT:    feq.s a1, fa5, fa5
 ; CHECK64-IZFHMIN-NEXT:    seqz a1, a1
 ; CHECK64-IZFHMIN-NEXT:    addi a1, a1, -1
 ; CHECK64-IZFHMIN-NEXT:    and a0, a1, a0
 ; CHECK64-IZFHMIN-NEXT:    ret
+;
+; CHECK32-IZHINXMIN-LABEL: fcvt_w_h_sat:
+; CHECK32-IZHINXMIN:       # %bb.0: # %start
+; CHECK32-IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECK32-IZHINXMIN-NEXT:    fcvt.w.s a1, a0, rtz
+; CHECK32-IZHINXMIN-NEXT:    feq.s a0, a0, a0
+; CHECK32-IZHINXMIN-NEXT:    seqz a0, a0
+; CHECK32-IZHINXMIN-NEXT:    addi a0, a0, -1
+; CHECK32-IZHINXMIN-NEXT:    and a0, a0, a1
+; CHECK32-IZHINXMIN-NEXT:    ret
+;
+; CHECK64-IZHINXMIN-LABEL: fcvt_w_h_sat:
+; CHECK64-IZHINXMIN:       # %bb.0: # %start
+; CHECK64-IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECK64-IZHINXMIN-NEXT:    fcvt.w.s a1, a0, rtz
+; CHECK64-IZHINXMIN-NEXT:    feq.s a0, a0, a0
+; CHECK64-IZHINXMIN-NEXT:    seqz a0, a0
+; CHECK64-IZHINXMIN-NEXT:    addi a0, a0, -1
+; CHECK64-IZHINXMIN-NEXT:    and a0, a0, a1
+; CHECK64-IZHINXMIN-NEXT:    ret
+;
+; CHECK32-IZDINXZHINXMIN-LABEL: fcvt_w_h_sat:
+; CHECK32-IZDINXZHINXMIN:       # %bb.0: # %start
+; CHECK32-IZDINXZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECK32-IZDINXZHINXMIN-NEXT:    fcvt.w.s a1, a0, rtz
+; CHECK32-IZDINXZHINXMIN-NEXT:    feq.s a0, a0, a0
+; CHECK32-IZDINXZHINXMIN-NEXT:    seqz a0, a0
+; CHECK32-IZDINXZHINXMIN-NEXT:    addi a0, a0, -1
+; CHECK32-IZDINXZHINXMIN-NEXT:    and a0, a0, a1
+; CHECK32-IZDINXZHINXMIN-NEXT:    ret
+;
+; CHECK64-IZDINXZHINXMIN-LABEL: fcvt_w_h_sat:
+; CHECK64-IZDINXZHINXMIN:       # %bb.0: # %start
+; CHECK64-IZDINXZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECK64-IZDINXZHINXMIN-NEXT:    fcvt.w.s a1, a0, rtz
+; CHECK64-IZDINXZHINXMIN-NEXT:    feq.s a0, a0, a0
+; CHECK64-IZDINXZHINXMIN-NEXT:    seqz a0, a0
+; CHECK64-IZDINXZHINXMIN-NEXT:    addi a0, a0, -1
+; CHECK64-IZDINXZHINXMIN-NEXT:    and a0, a0, a1
+; CHECK64-IZDINXZHINXMIN-NEXT:    ret
 start:
   %0 = tail call i32 @llvm.fptosi.sat.i32.f16(half %a)
   ret i32 %0
 }
 declare i32 @llvm.fptosi.sat.i32.f16(half)
 
 define i32 @fcvt_wu_h(half %a) nounwind {
 ; CHECKIZFH-LABEL: fcvt_wu_h:
 ; CHECKIZFH:       # %bb.0:
 ; CHECKIZFH-NEXT:    fcvt.wu.h a0, fa0, rtz
 ; CHECKIZFH-NEXT:    ret
 ;
 ; RV32IDZFH-LABEL: fcvt_wu_h:
 ; RV32IDZFH:       # %bb.0:
 ; RV32IDZFH-NEXT:    fcvt.wu.h a0, fa0, rtz
 ; RV32IDZFH-NEXT:    ret
 ;
 ; RV64IDZFH-LABEL: fcvt_wu_h:
 ; RV64IDZFH:       # %bb.0:
 ; RV64IDZFH-NEXT:    fcvt.wu.h a0, fa0, rtz
 ; RV64IDZFH-NEXT:    ret
 ;
+; CHECKIZHINX-LABEL: fcvt_wu_h:
+; CHECKIZHINX:       # %bb.0:
+; CHECKIZHINX-NEXT:    fcvt.wu.h a0, a0, rtz
+; CHECKIZHINX-NEXT:    ret
+;
+; CHECKIZDINXZHINX-LABEL: fcvt_wu_h:
+; CHECKIZDINXZHINX:       # %bb.0:
+; CHECKIZDINXZHINX-NEXT:    fcvt.wu.h a0, a0, rtz
+; CHECKIZDINXZHINX-NEXT:    ret
+;
 ; RV32I-LABEL: fcvt_wu_h:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    slli a0, a0, 16
 ; RV32I-NEXT:    srli a0, a0, 16
 ; RV32I-NEXT:    call __extendhfsf2@plt
 ; RV32I-NEXT:    call __fixunssfsi@plt

 ; CHECK32-IZFHMIN-NEXT:    fcvt.wu.s a0, fa5, rtz
 ; CHECK32-IZFHMIN-NEXT:    ret
 ;
 ; CHECK64-IZFHMIN-LABEL: fcvt_wu_h:
 ; CHECK64-IZFHMIN:       # %bb.0:
 ; CHECK64-IZFHMIN-NEXT:    fcvt.s.h fa5, fa0
 ; CHECK64-IZFHMIN-NEXT:    fcvt.wu.s a0, fa5, rtz
 ; CHECK64-IZFHMIN-NEXT:    ret
+;
+; CHECK32-IZHINXMIN-LABEL: fcvt_wu_h:
+; CHECK32-IZHINXMIN:       # %bb.0:
+; CHECK32-IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECK32-IZHINXMIN-NEXT:    fcvt.wu.s a0, a0, rtz
+; CHECK32-IZHINXMIN-NEXT:    ret
+;
+; CHECK64-IZHINXMIN-LABEL: fcvt_wu_h:
+; CHECK64-IZHINXMIN:       # %bb.0:
+; CHECK64-IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECK64-IZHINXMIN-NEXT:    fcvt.wu.s a0, a0, rtz
+; CHECK64-IZHINXMIN-NEXT:    ret
+;
+; CHECK32-IZDINXZHINXMIN-LABEL: fcvt_wu_h:
+; CHECK32-IZDINXZHINXMIN:       # %bb.0:
+; CHECK32-IZDINXZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECK32-IZDINXZHINXMIN-NEXT:    fcvt.wu.s a0, a0, rtz
+; CHECK32-IZDINXZHINXMIN-NEXT:    ret
+;
+; CHECK64-IZDINXZHINXMIN-LABEL: fcvt_wu_h:
+; CHECK64-IZDINXZHINXMIN:       # %bb.0:
+; CHECK64-IZDINXZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECK64-IZDINXZHINXMIN-NEXT:    fcvt.wu.s a0, a0, rtz
+; CHECK64-IZDINXZHINXMIN-NEXT:    ret
   %1 = fptoui half %a to i32
   ret i32 %1
 }
 
 ; Test where the fptoui has multiple uses, one of which causes a sext to be
 ; inserted on RV64.
 define i32 @fcvt_wu_h_multiple_use(half %x, ptr %y) nounwind {
 ; CHECKIZFH-LABEL: fcvt_wu_h_multiple_use:

 ;
 ; RV64IDZFH-LABEL: fcvt_wu_h_multiple_use:
 ; RV64IDZFH:       # %bb.0:
 ; RV64IDZFH-NEXT:    fcvt.wu.h a0, fa0, rtz
 ; RV64IDZFH-NEXT:    seqz a1, a0
 ; RV64IDZFH-NEXT:    add a0, a0, a1
 ; RV64IDZFH-NEXT:    ret
 ;
+; CHECKIZHINX-LABEL: fcvt_wu_h_multiple_use:
+; CHECKIZHINX:       # %bb.0:
+; CHECKIZHINX-NEXT:    fcvt.wu.h a0, a0, rtz
+; CHECKIZHINX-NEXT:    seqz a1, a0
+; CHECKIZHINX-NEXT:    add a0, a0, a1
+; CHECKIZHINX-NEXT:    ret
+;
+; CHECKIZDINXZHINX-LABEL: fcvt_wu_h_multiple_use:
+; CHECKIZDINXZHINX:       # %bb.0:
+; CHECKIZDINXZHINX-NEXT:    fcvt.wu.h a0, a0, rtz
+; CHECKIZDINXZHINX-NEXT:    seqz a1, a0
+; CHECKIZDINXZHINX-NEXT:    add a0, a0, a1
+; CHECKIZDINXZHINX-NEXT:    ret
+;
 ; RV32I-LABEL: fcvt_wu_h_multiple_use:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    slli a0, a0, 16
 ; RV32I-NEXT:    srli a0, a0, 16
 ; RV32I-NEXT:    call __extendhfsf2@plt
 ; RV32I-NEXT:    call __fixunssfsi@plt

 ;
 ; CHECK64-IZFHMIN-LABEL: fcvt_wu_h_multiple_use:
 ; CHECK64-IZFHMIN:       # %bb.0:
 ; CHECK64-IZFHMIN-NEXT:    fcvt.s.h fa5, fa0
 ; CHECK64-IZFHMIN-NEXT:    fcvt.wu.s a0, fa5, rtz
 ; CHECK64-IZFHMIN-NEXT:    seqz a1, a0
 ; CHECK64-IZFHMIN-NEXT:    add a0, a0, a1
 ; CHECK64-IZFHMIN-NEXT:    ret
+;
+; CHECK32-IZHINXMIN-LABEL: fcvt_wu_h_multiple_use:
+; CHECK32-IZHINXMIN:       # %bb.0:
+; CHECK32-IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECK32-IZHINXMIN-NEXT:    fcvt.wu.s a0, a0, rtz
+; CHECK32-IZHINXMIN-NEXT:    seqz a1, a0
+; CHECK32-IZHINXMIN-NEXT:    add a0, a0, a1
+; CHECK32-IZHINXMIN-NEXT:    ret
+;
+; CHECK64-IZHINXMIN-LABEL: fcvt_wu_h_multiple_use:
+; CHECK64-IZHINXMIN:       # %bb.0:
+; CHECK64-IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECK64-IZHINXMIN-NEXT:    fcvt.wu.s a0, a0, rtz
+; CHECK64-IZHINXMIN-NEXT:    seqz a1, a0
+; CHECK64-IZHINXMIN-NEXT:    add a0, a0, a1
+; CHECK64-IZHINXMIN-NEXT:    ret
+;
+; CHECK32-IZDINXZHINXMIN-LABEL: fcvt_wu_h_multiple_use:
+; CHECK32-IZDINXZHINXMIN:       # %bb.0:
+; CHECK32-IZDINXZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECK32-IZDINXZHINXMIN-NEXT:    fcvt.wu.s a0, a0, rtz
+; CHECK32-IZDINXZHINXMIN-NEXT:    seqz a1, a0
+; CHECK32-IZDINXZHINXMIN-NEXT:    add a0, a0, a1
+; CHECK32-IZDINXZHINXMIN-NEXT:    ret
+;
+; CHECK64-IZDINXZHINXMIN-LABEL: fcvt_wu_h_multiple_use:
+; CHECK64-IZDINXZHINXMIN:       # %bb.0:
+; CHECK64-IZDINXZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECK64-IZDINXZHINXMIN-NEXT:    fcvt.wu.s a0, a0, rtz
+; CHECK64-IZDINXZHINXMIN-NEXT:    seqz a1, a0
+; CHECK64-IZDINXZHINXMIN-NEXT:    add a0, a0, a1
+; CHECK64-IZDINXZHINXMIN-NEXT:    ret
   %a = fptoui half %x to i32
   %b = icmp eq i32 %a, 0
   %c = select i1 %b, i32 1, i32 %a
   ret i32 %c
 }
 
 define i32 @fcvt_wu_h_sat(half %a) nounwind {
 ; RV32IZFH-LABEL: fcvt_wu_h_sat:

 ; RV64IDZFH-NEXT:    feq.h a1, fa0, fa0
 ; RV64IDZFH-NEXT:    seqz a1, a1
 ; RV64IDZFH-NEXT:    addiw a1, a1, -1
 ; RV64IDZFH-NEXT:    and a0, a0, a1
 ; RV64IDZFH-NEXT:    slli a0, a0, 32
 ; RV64IDZFH-NEXT:    srli a0, a0, 32
 ; RV64IDZFH-NEXT:    ret
 ;
+; RV32IZHINX-LABEL: fcvt_wu_h_sat:
+; RV32IZHINX:       # %bb.0: # %start
+; RV32IZHINX-NEXT:    fcvt.wu.h a1, a0, rtz
+; RV32IZHINX-NEXT:    feq.h a0, a0, a0
+; RV32IZHINX-NEXT:    seqz a0, a0
+; RV32IZHINX-NEXT:    addi a0, a0, -1
+; RV32IZHINX-NEXT:    and a0, a0, a1
+; RV32IZHINX-NEXT:    ret
+;
+; RV64IZHINX-LABEL: fcvt_wu_h_sat:
+; RV64IZHINX:       # %bb.0: # %start
+; RV64IZHINX-NEXT:    fcvt.wu.h a1, a0, rtz
+; RV64IZHINX-NEXT:    feq.h a0, a0, a0
+; RV64IZHINX-NEXT:    seqz a0, a0
+; RV64IZHINX-NEXT:    addiw a0, a0, -1
+; RV64IZHINX-NEXT:    and a0, a1, a0
+; RV64IZHINX-NEXT:    slli a0, a0, 32
+; RV64IZHINX-NEXT:    srli a0, a0, 32
+; RV64IZHINX-NEXT:    ret
+;
+; RV32IZDINXZHINX-LABEL: fcvt_wu_h_sat:
+; RV32IZDINXZHINX:       # %bb.0: # %start
+; RV32IZDINXZHINX-NEXT:    fcvt.wu.h a1, a0, rtz
+; RV32IZDINXZHINX-NEXT:    feq.h a0, a0, a0
+; RV32IZDINXZHINX-NEXT:    seqz a0, a0
+; RV32IZDINXZHINX-NEXT:    addi a0, a0, -1
+; RV32IZDINXZHINX-NEXT:    and a0, a0, a1
+; RV32IZDINXZHINX-NEXT:    ret
+;
+; RV64IZDINXZHINX-LABEL: fcvt_wu_h_sat:
+; RV64IZDINXZHINX:       # %bb.0: # %start
+; RV64IZDINXZHINX-NEXT:    fcvt.wu.h a1, a0, rtz
+; RV64IZDINXZHINX-NEXT:    feq.h a0, a0, a0
+; RV64IZDINXZHINX-NEXT:    seqz a0, a0
+; RV64IZDINXZHINX-NEXT:    addiw a0, a0, -1
+; RV64IZDINXZHINX-NEXT:    and a0, a1, a0
+; RV64IZDINXZHINX-NEXT:    slli a0, a0, 32
+; RV64IZDINXZHINX-NEXT:    srli a0, a0, 32
+; RV64IZDINXZHINX-NEXT:    ret
+;
 ; RV32I-LABEL: fcvt_wu_h_sat:
 ; RV32I:       # %bb.0: # %start
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s2, 0(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    slli a0, a0, 16

 ; CHECK64-IZFHMIN-NEXT:    fcvt.wu.s a0, fa5, rtz
 ; CHECK64-IZFHMIN-NEXT:    feq.s a1, fa5, fa5
 ; CHECK64-IZFHMIN-NEXT:    seqz a1, a1
 ; CHECK64-IZFHMIN-NEXT:    addiw a1, a1, -1
 ; CHECK64-IZFHMIN-NEXT:    and a0, a0, a1
 ; CHECK64-IZFHMIN-NEXT:    slli a0, a0, 32
 ; CHECK64-IZFHMIN-NEXT:    srli a0, a0, 32
 ; CHECK64-IZFHMIN-NEXT:    ret
+;
+; CHECK32-IZHINXMIN-LABEL: fcvt_wu_h_sat:
+; CHECK32-IZHINXMIN:       # %bb.0: # %start
+; CHECK32-IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECK32-IZHINXMIN-NEXT:    fcvt.wu.s a1, a0, rtz
+; CHECK32-IZHINXMIN-NEXT:    feq.s a0, a0, a0
+; CHECK32-IZHINXMIN-NEXT:    seqz a0, a0
+; CHECK32-IZHINXMIN-NEXT:    addi a0, a0, -1
+; CHECK32-IZHINXMIN-NEXT:    and a0, a0, a1
+; CHECK32-IZHINXMIN-NEXT:    ret
+;
+; CHECK64-IZHINXMIN-LABEL: fcvt_wu_h_sat:
+; CHECK64-IZHINXMIN:       # %bb.0: # %start
+; CHECK64-IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECK64-IZHINXMIN-NEXT:    fcvt.wu.s a1, a0, rtz
+; CHECK64-IZHINXMIN-NEXT:    feq.s a0, a0, a0
+; CHECK64-IZHINXMIN-NEXT:    seqz a0, a0
+; CHECK64-IZHINXMIN-NEXT:    addiw a0, a0, -1
+; CHECK64-IZHINXMIN-NEXT:    and a0, a1, a0
+; CHECK64-IZHINXMIN-NEXT:    slli a0, a0, 32
+; CHECK64-IZHINXMIN-NEXT:    srli a0, a0, 32
+; CHECK64-IZHINXMIN-NEXT:    ret
+;
+; CHECK32-IZDINXZHINXMIN-LABEL: fcvt_wu_h_sat:
+; CHECK32-IZDINXZHINXMIN:       # %bb.0: # %start
+; CHECK32-IZDINXZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECK32-IZDINXZHINXMIN-NEXT:    fcvt.wu.s a1, a0, rtz
+; CHECK32-IZDINXZHINXMIN-NEXT:    feq.s a0, a0, a0
+; CHECK32-IZDINXZHINXMIN-NEXT:    seqz a0, a0
+; CHECK32-IZDINXZHINXMIN-NEXT:    addi a0, a0, -1
+; CHECK32-IZDINXZHINXMIN-NEXT:    and a0, a0, a1
+; CHECK32-IZDINXZHINXMIN-NEXT:    ret
+;
+; CHECK64-IZDINXZHINXMIN-LABEL: fcvt_wu_h_sat:
+; CHECK64-IZDINXZHINXMIN:       # %bb.0: # %start
+; CHECK64-IZDINXZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECK64-IZDINXZHINXMIN-NEXT:    fcvt.wu.s a1, a0, rtz
+; CHECK64-IZDINXZHINXMIN-NEXT:    feq.s a0, a0, a0
+; CHECK64-IZDINXZHINXMIN-NEXT:    seqz a0, a0
+; CHECK64-IZDINXZHINXMIN-NEXT:    addiw a0, a0, -1
+; CHECK64-IZDINXZHINXMIN-NEXT:    and a0, a1, a0
+; CHECK64-IZDINXZHINXMIN-NEXT:    slli a0, a0, 32
+; CHECK64-IZDINXZHINXMIN-NEXT:    srli a0, a0, 32
+; CHECK64-IZDINXZHINXMIN-NEXT:    ret
 start:
   %0 = tail call i32 @llvm.fptoui.sat.i32.f16(half %a)
   ret i32 %0
 }
 declare i32 @llvm.fptoui.sat.i32.f16(half)
 
 define i64 @fcvt_l_h(half %a) nounwind {
 ; RV32IZFH-LABEL: fcvt_l_h:

 ; RV32IDZFH-NEXT:    addi sp, sp, 16
 ; RV32IDZFH-NEXT:    ret
 ;
 ; RV64IDZFH-LABEL: fcvt_l_h:
 ; RV64IDZFH:       # %bb.0:
 ; RV64IDZFH-NEXT:    fcvt.l.h a0, fa0, rtz
 ; RV64IDZFH-NEXT:    ret
 ;
+; RV32IZHINX-LABEL: fcvt_l_h:
+; RV32IZHINX:       # %bb.0:
+; RV32IZHINX-NEXT:    addi sp, sp, -16
+; RV32IZHINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZHINX-NEXT:    call __fixhfdi@plt
+; RV32IZHINX-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZHINX-NEXT:    addi sp, sp, 16
+; RV32IZHINX-NEXT:    ret
+;
+; RV64IZHINX-LABEL: fcvt_l_h:
+; RV64IZHINX:       # %bb.0:
+; RV64IZHINX-NEXT:    fcvt.l.h a0, a0, rtz
+; RV64IZHINX-NEXT:    ret
+;
+; RV32IZDINXZHINX-LABEL: fcvt_l_h:
+; RV32IZDINXZHINX:       # %bb.0:
+; RV32IZDINXZHINX-NEXT:    addi sp, sp, -16
+; RV32IZDINXZHINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZDINXZHINX-NEXT:    call __fixhfdi@plt
+; RV32IZDINXZHINX-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZDINXZHINX-NEXT:    addi sp, sp, 16
+; RV32IZDINXZHINX-NEXT:    ret
+;
+; RV64IZDINXZHINX-LABEL: fcvt_l_h:
+; RV64IZDINXZHINX:       # %bb.0:
+; RV64IZDINXZHINX-NEXT:    fcvt.l.h a0, a0, rtz
+; RV64IZDINXZHINX-NEXT:    ret
+;
 ; RV32I-LABEL: fcvt_l_h:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    slli a0, a0, 16
 ; RV32I-NEXT:    srli a0, a0, 16
 ; RV32I-NEXT:    call __extendhfsf2@plt
 ; RV32I-NEXT:    call __fixsfdi@plt

 ; CHECK32-IZFHMIN-NEXT:    addi sp, sp, 16
 ; CHECK32-IZFHMIN-NEXT:    ret
 ;
 ; CHECK64-IZFHMIN-LABEL: fcvt_l_h:
 ; CHECK64-IZFHMIN:       # %bb.0:
 ; CHECK64-IZFHMIN-NEXT:    fcvt.s.h fa5, fa0
 ; CHECK64-IZFHMIN-NEXT:    fcvt.l.s a0, fa5, rtz
 ; CHECK64-IZFHMIN-NEXT:    ret
+;
+; CHECK32-IZHINXMIN-LABEL: fcvt_l_h:
+; CHECK32-IZHINXMIN:       # %bb.0:
+; CHECK32-IZHINXMIN-NEXT:    addi sp, sp, -16
+; CHECK32-IZHINXMIN-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; CHECK32-IZHINXMIN-NEXT:    call __fixhfdi@plt
+; CHECK32-IZHINXMIN-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; CHECK32-IZHINXMIN-NEXT:    addi sp, sp, 16
+; CHECK32-IZHINXMIN-NEXT:    ret
+;
+; CHECK64-IZHINXMIN-LABEL: fcvt_l_h:
+; CHECK64-IZHINXMIN:       # %bb.0:
+; CHECK64-IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECK64-IZHINXMIN-NEXT:    fcvt.l.s a0, a0, rtz
+; CHECK64-IZHINXMIN-NEXT:    ret
+;
+; CHECK32-IZDINXZHINXMIN-LABEL: fcvt_l_h:
+; CHECK32-IZDINXZHINXMIN:       # %bb.0:
+; CHECK32-IZDINXZHINXMIN-NEXT:    addi sp, sp, -16
+; CHECK32-IZDINXZHINXMIN-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; CHECK32-IZDINXZHINXMIN-NEXT:    call __fixhfdi@plt
+; CHECK32-IZDINXZHINXMIN-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; CHECK32-IZDINXZHINXMIN-NEXT:    addi sp, sp, 16
+; CHECK32-IZDINXZHINXMIN-NEXT:    ret
+;
+; CHECK64-IZDINXZHINXMIN-LABEL: fcvt_l_h:
+; CHECK64-IZDINXZHINXMIN:       # %bb.0:
+; CHECK64-IZDINXZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECK64-IZDINXZHINXMIN-NEXT:    fcvt.l.s a0, a0, rtz
+; CHECK64-IZDINXZHINXMIN-NEXT:    ret
   %1 = fptosi half %a to i64
   ret i64 %1
 }
 
 define i64 @fcvt_l_h_sat(half %a) nounwind {
 ; RV32IZFH-LABEL: fcvt_l_h_sat:
 ; RV32IZFH:       # %bb.0: # %start
 ; RV32IZFH-NEXT:    addi sp, sp, -16

 ; RV64IDZFH:       # %bb.0: # %start
 ; RV64IDZFH-NEXT:    fcvt.l.h a0, fa0, rtz
 ; RV64IDZFH-NEXT:    feq.h a1, fa0, fa0
 ; RV64IDZFH-NEXT:    seqz a1, a1
 ; RV64IDZFH-NEXT:    addi a1, a1, -1
 ; RV64IDZFH-NEXT:    and a0, a1, a0
 ; RV64IDZFH-NEXT:    ret
 ;
+; RV32IZHINX-LABEL: fcvt_l_h_sat:
+; RV32IZHINX:       # %bb.0: # %start
+; RV32IZHINX-NEXT:    addi sp, sp, -32
+; RV32IZHINX-NEXT:    sw ra, 28(sp) # 4-byte Folded Spill
+; RV32IZHINX-NEXT:    sw s0, 24(sp) # 4-byte Folded Spill
+; RV32IZHINX-NEXT:    sw s1, 20(sp) # 4-byte Folded Spill
+; RV32IZHINX-NEXT:    sw s2, 16(sp) # 4-byte Folded Spill
+; RV32IZHINX-NEXT:    sw s3, 12(sp) # 4-byte Folded Spill
+; RV32IZHINX-NEXT:    sw s4, 8(sp) # 4-byte Folded Spill
+; RV32IZHINX-NEXT:    lui a1, %hi(.LCPI10_0)
+; RV32IZHINX-NEXT:    lw a1, %lo(.LCPI10_0)(a1)
+; RV32IZHINX-NEXT:    fcvt.s.h s0, a0
+; RV32IZHINX-NEXT:    flt.s s1, a1, s0
+; RV32IZHINX-NEXT:    neg s2, s1
+; RV32IZHINX-NEXT:    lui a0, 913408
+; RV32IZHINX-NEXT:    fle.s s3, a0, s0
+; RV32IZHINX-NEXT:    neg s4, s3
+; RV32IZHINX-NEXT:    mv a0, s0
+; RV32IZHINX-NEXT:    call __fixsfdi@plt
+; RV32IZHINX-NEXT:    and a0, s4, a0
+; RV32IZHINX-NEXT:    or a0, s2, a0
+; RV32IZHINX-NEXT:    feq.s a2, s0, s0
+; RV32IZHINX-NEXT:    neg a2, a2
+; RV32IZHINX-NEXT:    lui a4, 524288
+; RV32IZHINX-NEXT:    lui a3, 524288
+; RV32IZHINX-NEXT:    beqz s3, .LBB10_2
+; RV32IZHINX-NEXT:  # %bb.1: # %start
+; RV32IZHINX-NEXT:    mv a3, a1
+; RV32IZHINX-NEXT:  .LBB10_2: # %start
+; RV32IZHINX-NEXT:    and a0, a2, a0
+; RV32IZHINX-NEXT:    beqz s1, .LBB10_4
+; RV32IZHINX-NEXT:  # %bb.3:
+; RV32IZHINX-NEXT:    addi a3, a4, -1
+; RV32IZHINX-NEXT:  .LBB10_4: # %start
+; RV32IZHINX-NEXT:    and a1, a2, a3
+; RV32IZHINX-NEXT:    lw ra, 28(sp) # 4-byte Folded Reload
+; RV32IZHINX-NEXT:    lw s0, 24(sp) # 4-byte Folded Reload
+; RV32IZHINX-NEXT:    lw s1, 20(sp) # 4-byte Folded Reload
+; RV32IZHINX-NEXT:    lw s2, 16(sp) # 4-byte Folded Reload
+; RV32IZHINX-NEXT:    lw s3, 12(sp) # 4-byte Folded Reload
+; RV32IZHINX-NEXT:    lw s4, 8(sp) # 4-byte Folded Reload
+; RV32IZHINX-NEXT:    addi sp, sp, 32
+; RV32IZHINX-NEXT:    ret
+;
+; RV64IZHINX-LABEL: fcvt_l_h_sat:
+; RV64IZHINX:       # %bb.0: # %start
+; RV64IZHINX-NEXT:    fcvt.l.h a1, a0, rtz
+; RV64IZHINX-NEXT:    feq.h a0, a0, a0
+; RV64IZHINX-NEXT:    seqz a0, a0
+; RV64IZHINX-NEXT:    addi a0, a0, -1
+; RV64IZHINX-NEXT:    and a0, a0, a1
+; RV64IZHINX-NEXT:    ret
+;
+; RV32IZDINXZHINX-LABEL: fcvt_l_h_sat:
+; RV32IZDINXZHINX:       # %bb.0: # %start
+; RV32IZDINXZHINX-NEXT:    addi sp, sp, -32
+; RV32IZDINXZHINX-NEXT:    sw ra, 28(sp) # 4-byte Folded Spill
+; RV32IZDINXZHINX-NEXT:    sw s0, 24(sp) # 4-byte Folded Spill
+; RV32IZDINXZHINX-NEXT:    sw s1, 20(sp) # 4-byte Folded Spill
+; RV32IZDINXZHINX-NEXT:    sw s2, 16(sp) # 4-byte Folded Spill
+; RV32IZDINXZHINX-NEXT:    sw s3, 12(sp) # 4-byte Folded Spill
+; RV32IZDINXZHINX-NEXT:    sw s4, 8(sp) # 4-byte Folded Spill
+; RV32IZDINXZHINX-NEXT:    lui a1, %hi(.LCPI10_0)
+; RV32IZDINXZHINX-NEXT:    lw a1, %lo(.LCPI10_0)(a1)
+; RV32IZDINXZHINX-NEXT:    fcvt.s.h s0, a0
+; RV32IZDINXZHINX-NEXT:    flt.s s1, a1, s0
+; RV32IZDINXZHINX-NEXT:    neg s2, s1
+; RV32IZDINXZHINX-NEXT:    lui a0, 913408
+; RV32IZDINXZHINX-NEXT:    fle.s s3, a0, s0
+; RV32IZDINXZHINX-NEXT:    neg s4, s3
+; RV32IZDINXZHINX-NEXT:    mv a0, s0
+; RV32IZDINXZHINX-NEXT:    call __fixsfdi@plt
+; RV32IZDINXZHINX-NEXT:    and a0, s4, a0
+; RV32IZDINXZHINX-NEXT:    or a0, s2, a0
+; RV32IZDINXZHINX-NEXT:    feq.s a2, s0, s0
+; RV32IZDINXZHINX-NEXT:    neg a2, a2
+; RV32IZDINXZHINX-NEXT:    lui a4, 524288
+; RV32IZDINXZHINX-NEXT:    lui a3, 524288
+; RV32IZDINXZHINX-NEXT:    beqz s3, .LBB10_2
+; RV32IZDINXZHINX-NEXT:  # %bb.1: # %start
+; RV32IZDINXZHINX-NEXT:    mv a3, a1
+; RV32IZDINXZHINX-NEXT:  .LBB10_2: # %start
+; RV32IZDINXZHINX-NEXT:    and a0, a2, a0
+; RV32IZDINXZHINX-NEXT:    beqz s1, .LBB10_4
+; RV32IZDINXZHINX-NEXT:  # %bb.3:
+; RV32IZDINXZHINX-NEXT:    addi a3, a4, -1
+; RV32IZDINXZHINX-NEXT:  .LBB10_4: # %start
+; RV32IZDINXZHINX-NEXT:    and a1, a2, a3
+; RV32IZDINXZHINX-NEXT:    lw ra, 28(sp) # 4-byte Folded Reload
+; RV32IZDINXZHINX-NEXT:    lw s0, 24(sp) # 4-byte Folded Reload
+; RV32IZDINXZHINX-NEXT:    lw s1, 20(sp) # 4-byte Folded Reload
+; RV32IZDINXZHINX-NEXT:    lw s2, 16(sp) # 4-byte Folded Reload
+; RV32IZDINXZHINX-NEXT:    lw s3, 12(sp) # 4-byte Folded Reload
+; RV32IZDINXZHINX-NEXT:    lw s4, 8(sp) # 4-byte Folded Reload
+; RV32IZDINXZHINX-NEXT:    addi sp, sp, 32
+; RV32IZDINXZHINX-NEXT:    ret
+;
+; RV64IZDINXZHINX-LABEL: fcvt_l_h_sat:
+; RV64IZDINXZHINX:       # %bb.0: # %start
+; RV64IZDINXZHINX-NEXT:    fcvt.l.h a1, a0, rtz
+; RV64IZDINXZHINX-NEXT:    feq.h a0, a0, a0
+; RV64IZDINXZHINX-NEXT:    seqz a0, a0
+; RV64IZDINXZHINX-NEXT:    addi a0, a0, -1
+; RV64IZDINXZHINX-NEXT:    and a0, a0, a1
+; RV64IZDINXZHINX-NEXT:    ret
+;
 ; RV32I-LABEL: fcvt_l_h_sat:
 ; RV32I:       # %bb.0: # %start
 ; RV32I-NEXT:    addi sp, sp, -32
 ; RV32I-NEXT:    sw ra, 28(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s0, 24(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s1, 20(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s2, 16(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s3, 12(sp) # 4-byte Folded Spill

 ; RV32IDZFHMIN-NEXT:    and a0, a3, a0
 ; RV32IDZFHMIN-NEXT:    or a0, a2, a0
 ; RV32IDZFHMIN-NEXT:    and a0, a4, a0
 ; RV32IDZFHMIN-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32IDZFHMIN-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
 ; RV32IDZFHMIN-NEXT:    fld fs0, 0(sp) # 8-byte Folded Reload
 ; RV32IDZFHMIN-NEXT:    addi sp, sp, 16
 ; RV32IDZFHMIN-NEXT:    ret
+;
+; CHECK32-IZHINXMIN-LABEL: fcvt_l_h_sat:
+; CHECK32-IZHINXMIN:       # %bb.0: # %start
+; CHECK32-IZHINXMIN-NEXT:    addi sp, sp, -32
+; CHECK32-IZHINXMIN-NEXT:    sw ra, 28(sp) # 4-byte Folded Spill
+; CHECK32-IZHINXMIN-NEXT:    sw s0, 24(sp) # 4-byte Folded Spill
+; CHECK32-IZHINXMIN-NEXT:    sw s1, 20(sp) # 4-byte Folded Spill
+; CHECK32-IZHINXMIN-NEXT:    sw s2, 16(sp) # 4-byte Folded Spill
+; CHECK32-IZHINXMIN-NEXT:    sw s3, 12(sp) # 4-byte Folded Spill
+; CHECK32-IZHINXMIN-NEXT:    sw s4, 8(sp) # 4-byte Folded Spill
+; CHECK32-IZHINXMIN-NEXT:    lui a1, %hi(.LCPI10_0)
+; CHECK32-IZHINXMIN-NEXT:    lw a1, %lo(.LCPI10_0)(a1)
+; CHECK32-IZHINXMIN-NEXT:    fcvt.s.h s0, a0
+; CHECK32-IZHINXMIN-NEXT:    flt.s s1, a1, s0
+; CHECK32-IZHINXMIN-NEXT:    neg s2, s1
+; CHECK32-IZHINXMIN-NEXT:    lui a0, 913408
+; CHECK32-IZHINXMIN-NEXT:    fle.s s3, a0, s0
+; CHECK32-IZHINXMIN-NEXT:    neg s4, s3
+; CHECK32-IZHINXMIN-NEXT:    mv a0, s0
+; CHECK32-IZHINXMIN-NEXT:    call __fixsfdi@plt
+; CHECK32-IZHINXMIN-NEXT:    and a0, s4, a0
+; CHECK32-IZHINXMIN-NEXT:    or a0, s2, a0
+; CHECK32-IZHINXMIN-NEXT:    feq.s a2, s0, s0
+; CHECK32-IZHINXMIN-NEXT:    neg a2, a2
+; CHECK32-IZHINXMIN-NEXT:    lui a4, 524288
+; CHECK32-IZHINXMIN-NEXT:    lui a3, 524288
+; CHECK32-IZHINXMIN-NEXT:    beqz s3, .LBB10_2
+; CHECK32-IZHINXMIN-NEXT:  # %bb.1: # %start
+; CHECK32-IZHINXMIN-NEXT:    mv a3, a1
+; CHECK32-IZHINXMIN-NEXT:  .LBB10_2: # %start
+; CHECK32-IZHINXMIN-NEXT:    and a0, a2, a0
+; CHECK32-IZHINXMIN-NEXT:    beqz s1, .LBB10_4
+; CHECK32-IZHINXMIN-NEXT:  # %bb.3:
+; CHECK32-IZHINXMIN-NEXT:    addi a3, a4, -1
+; CHECK32-IZHINXMIN-NEXT:  .LBB10_4: # %start
+; CHECK32-IZHINXMIN-NEXT:    and a1, a2, a3
+; CHECK32-IZHINXMIN-NEXT:    lw ra, 28(sp) # 4-byte Folded Reload
+; CHECK32-IZHINXMIN-NEXT:    lw s0, 24(sp) # 4-byte Folded Reload
+; CHECK32-IZHINXMIN-NEXT:    lw s1, 20(sp) # 4-byte Folded Reload
+; CHECK32-IZHINXMIN-NEXT:    lw s2, 16(sp) # 4-byte Folded Reload
+; CHECK32-IZHINXMIN-NEXT:    lw s3, 12(sp) # 4-byte Folded Reload
+; CHECK32-IZHINXMIN-NEXT:    lw s4, 8(sp) # 4-byte Folded Reload
+; CHECK32-IZHINXMIN-NEXT:    addi sp, sp, 32
+; CHECK32-IZHINXMIN-NEXT:    ret
+;
+; CHECK64-IZHINXMIN-LABEL: fcvt_l_h_sat:
+; CHECK64-IZHINXMIN:       # %bb.0: # %start
+; CHECK64-IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECK64-IZHINXMIN-NEXT:    fcvt.l.s a1, a0, rtz
+; CHECK64-IZHINXMIN-NEXT:    feq.s a0, a0, a0
+; CHECK64-IZHINXMIN-NEXT:    seqz a0, a0
+; CHECK64-IZHINXMIN-NEXT:    addi a0, a0, -1
+; CHECK64-IZHINXMIN-NEXT:    and a0, a0, a1
+; CHECK64-IZHINXMIN-NEXT:    ret
+;
+; CHECK32-IZDINXZHINXMIN-LABEL: fcvt_l_h_sat:
+; CHECK32-IZDINXZHINXMIN:       # %bb.0: # %start
+; CHECK32-IZDINXZHINXMIN-NEXT:    addi sp, sp, -32
+; CHECK32-IZDINXZHINXMIN-NEXT:    sw ra, 28(sp) # 4-byte Folded Spill
+; CHECK32-IZDINXZHINXMIN-NEXT:    sw s0, 24(sp) # 4-byte Folded Spill
+; CHECK32-IZDINXZHINXMIN-NEXT:    sw s1, 20(sp) # 4-byte Folded Spill
+; CHECK32-IZDINXZHINXMIN-NEXT:    sw s2, 16(sp) # 4-byte Folded Spill
+; CHECK32-IZDINXZHINXMIN-NEXT:    sw s3, 12(sp) # 4-byte Folded Spill
+; CHECK32-IZDINXZHINXMIN-NEXT:    sw s4, 8(sp) # 4-byte Folded Spill
+; CHECK32-IZDINXZHINXMIN-NEXT:    lui a1, %hi(.LCPI10_0)
+; CHECK32-IZDINXZHINXMIN-NEXT:    lw a1, %lo(.LCPI10_0)(a1)
+; CHECK32-IZDINXZHINXMIN-NEXT:    fcvt.s.h s0, a0
+; CHECK32-IZDINXZHINXMIN-NEXT:    flt.s s1, a1, s0
+; CHECK32-IZDINXZHINXMIN-NEXT:    neg s2, s1
+; CHECK32-IZDINXZHINXMIN-NEXT:    lui a0, 913408
+; CHECK32-IZDINXZHINXMIN-NEXT:    fle.s s3, a0, s0
+; CHECK32-IZDINXZHINXMIN-NEXT:    neg s4, s3
+; CHECK32-IZDINXZHINXMIN-NEXT:    mv a0, s0
+; CHECK32-IZDINXZHINXMIN-NEXT:    call __fixsfdi@plt
+; CHECK32-IZDINXZHINXMIN-NEXT:    and a0, s4, a0
+; CHECK32-IZDINXZHINXMIN-NEXT:    or a0, s2, a0
+; CHECK32-IZDINXZHINXMIN-NEXT:    feq.s a2, s0, s0
+; CHECK32-IZDINXZHINXMIN-NEXT:    neg a2, a2
+; CHECK32-IZDINXZHINXMIN-NEXT:    lui a4, 524288
+; CHECK32-IZDINXZHINXMIN-NEXT:    lui a3, 524288
+; CHECK32-IZDINXZHINXMIN-NEXT:    beqz s3, .LBB10_2
+; CHECK32-IZDINXZHINXMIN-NEXT:  # %bb.1: # %start
+; CHECK32-IZDINXZHINXMIN-NEXT:    mv a3, a1
+; CHECK32-IZDINXZHINXMIN-NEXT:  .LBB10_2: # %start
+; CHECK32-IZDINXZHINXMIN-NEXT:    and a0, a2, a0
+; CHECK32-IZDINXZHINXMIN-NEXT:    beqz s1, .LBB10_4
+; CHECK32-IZDINXZHINXMIN-NEXT:  # %bb.3:
+; CHECK32-IZDINXZHINXMIN-NEXT:    addi a3, a4, -1
+; CHECK32-IZDINXZHINXMIN-NEXT:  .LBB10_4: # %start
+; CHECK32-IZDINXZHINXMIN-NEXT:    and a1, a2, a3
+; CHECK32-IZDINXZHINXMIN-NEXT:    lw ra, 28(sp) # 4-byte Folded Reload
+; CHECK32-IZDINXZHINXMIN-NEXT:    lw s0, 24(sp) # 4-byte Folded Reload
+; CHECK32-IZDINXZHINXMIN-NEXT:    lw s1, 20(sp) # 4-byte Folded Reload
+; CHECK32-IZDINXZHINXMIN-NEXT:    lw s2, 16(sp) # 4-byte Folded Reload
+; CHECK32-IZDINXZHINXMIN-NEXT:    lw s3, 12(sp) # 4-byte Folded Reload
+; CHECK32-IZDINXZHINXMIN-NEXT:    lw s4, 8(sp) # 4-byte Folded Reload
+; CHECK32-IZDINXZHINXMIN-NEXT:    addi sp, sp, 32
+; CHECK32-IZDINXZHINXMIN-NEXT:    ret
+;
+; CHECK64-IZDINXZHINXMIN-LABEL: fcvt_l_h_sat:
+; CHECK64-IZDINXZHINXMIN:       # %bb.0: # %start
+; CHECK64-IZDINXZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECK64-IZDINXZHINXMIN-NEXT:    fcvt.l.s a1, a0, rtz
+; CHECK64-IZDINXZHINXMIN-NEXT:    feq.s a0, a0, a0
+; CHECK64-IZDINXZHINXMIN-NEXT:    seqz a0, a0
+; CHECK64-IZDINXZHINXMIN-NEXT:    addi a0, a0, -1
+; CHECK64-IZDINXZHINXMIN-NEXT:    and a0, a0, a1
+; CHECK64-IZDINXZHINXMIN-NEXT:    ret
 start:
   %0 = tail call i64 @llvm.fptosi.sat.i64.f16(half %a)
   ret i64 %0
 }
 declare i64 @llvm.fptosi.sat.i64.f16(half)
 
 define i64 @fcvt_lu_h(half %a) nounwind {
 ; RV32IZFH-LABEL: fcvt_lu_h:

 ; RV32IDZFH-NEXT:    addi sp, sp, 16
 ; RV32IDZFH-NEXT:    ret
 ;
 ; RV64IDZFH-LABEL: fcvt_lu_h:
 ; RV64IDZFH:       # %bb.0:
 ; RV64IDZFH-NEXT:    fcvt.lu.h a0, fa0, rtz
 ; RV64IDZFH-NEXT:    ret
 ;
+; RV32IZHINX-LABEL: fcvt_lu_h:
+; RV32IZHINX:       # %bb.0:
+; RV32IZHINX-NEXT:    addi sp, sp, -16
+; RV32IZHINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZHINX-NEXT:    call __fixunshfdi@plt
+; RV32IZHINX-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZHINX-NEXT:    addi sp, sp, 16
+; RV32IZHINX-NEXT:    ret
+;
+; RV64IZHINX-LABEL: fcvt_lu_h:
+; RV64IZHINX:       # %bb.0:
+; RV64IZHINX-NEXT:    fcvt.lu.h a0, a0, rtz
+; RV64IZHINX-NEXT:    ret
+;
+; RV32IZDINXZHINX-LABEL: fcvt_lu_h:
+; RV32IZDINXZHINX:       # %bb.0:
+; RV32IZDINXZHINX-NEXT:    addi sp, sp, -16
+; RV32IZDINXZHINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZDINXZHINX-NEXT:    call __fixunshfdi@plt
+; RV32IZDINXZHINX-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZDINXZHINX-NEXT:    addi sp, sp, 16
+; RV32IZDINXZHINX-NEXT:    ret
+;
+; RV64IZDINXZHINX-LABEL: fcvt_lu_h:
+; RV64IZDINXZHINX:       # %bb.0:
+; RV64IZDINXZHINX-NEXT:    fcvt.lu.h a0, a0, rtz
+; RV64IZDINXZHINX-NEXT:    ret
+;
 ; RV32I-LABEL: fcvt_lu_h:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    slli a0, a0, 16
 ; RV32I-NEXT:    srli a0, a0, 16
 ; RV32I-NEXT:    call __extendhfsf2@plt
 ; RV32I-NEXT:    call __fixunssfdi@plt

 ; CHECK32-IZFHMIN-NEXT:    addi sp, sp, 16
 ; CHECK32-IZFHMIN-NEXT:    ret
 ;
 ; CHECK64-IZFHMIN-LABEL: fcvt_lu_h:
 ; CHECK64-IZFHMIN:       # %bb.0:
 ; CHECK64-IZFHMIN-NEXT:    fcvt.s.h fa5, fa0
 ; CHECK64-IZFHMIN-NEXT:    fcvt.lu.s a0, fa5, rtz
 ; CHECK64-IZFHMIN-NEXT:    ret
+;
+; CHECK32-IZHINXMIN-LABEL: fcvt_lu_h:
+; CHECK32-IZHINXMIN:       # %bb.0:
+; CHECK32-IZHINXMIN-NEXT:    addi sp, sp, -16
+; CHECK32-IZHINXMIN-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; CHECK32-IZHINXMIN-NEXT:    call __fixunshfdi@plt
+; CHECK32-IZHINXMIN-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; CHECK32-IZHINXMIN-NEXT:    addi sp, sp, 16
+; CHECK32-IZHINXMIN-NEXT:    ret
+;
+; CHECK64-IZHINXMIN-LABEL: fcvt_lu_h:
+; CHECK64-IZHINXMIN:       # %bb.0:
+; CHECK64-IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECK64-IZHINXMIN-NEXT:    fcvt.lu.s a0, a0, rtz
+; CHECK64-IZHINXMIN-NEXT:    ret
+;
+; CHECK32-IZDINXZHINXMIN-LABEL: fcvt_lu_h:
+; CHECK32-IZDINXZHINXMIN:       # %bb.0:
+; CHECK32-IZDINXZHINXMIN-NEXT:    addi sp, sp, -16
+; CHECK32-IZDINXZHINXMIN-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; CHECK32-IZDINXZHINXMIN-NEXT:    call __fixunshfdi@plt
+; CHECK32-IZDINXZHINXMIN-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; CHECK32-IZDINXZHINXMIN-NEXT:    addi sp, sp, 16
+; CHECK32-IZDINXZHINXMIN-NEXT:    ret
+;
+; CHECK64-IZDINXZHINXMIN-LABEL: fcvt_lu_h:
+; CHECK64-IZDINXZHINXMIN:       # %bb.0:
+; CHECK64-IZDINXZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECK64-IZDINXZHINXMIN-NEXT:    fcvt.lu.s a0, a0, rtz
+; CHECK64-IZDINXZHINXMIN-NEXT:    ret
   %1 = fptoui half %a to i64
   ret i64 %1
 }
 
 define i64 @fcvt_lu_h_sat(half %a) nounwind {
 ; RV32IZFH-LABEL: fcvt_lu_h_sat:
 ; RV32IZFH:       # %bb.0: # %start
 ; RV32IZFH-NEXT:    addi sp, sp, -16

 ; RV64IDZFH:       # %bb.0: # %start
 ; RV64IDZFH-NEXT:    fcvt.lu.h a0, fa0, rtz
 ; RV64IDZFH-NEXT:    feq.h a1, fa0, fa0
 ; RV64IDZFH-NEXT:    seqz a1, a1
 ; RV64IDZFH-NEXT:    addi a1, a1, -1
 ; RV64IDZFH-NEXT:    and a0, a1, a0
 ; RV64IDZFH-NEXT:    ret
 ;
+; RV32IZHINX-LABEL: fcvt_lu_h_sat:
+; RV32IZHINX:       # %bb.0: # %start
+; RV32IZHINX-NEXT:    addi sp, sp, -16
+; RV32IZHINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZHINX-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
+; RV32IZHINX-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
+; RV32IZHINX-NEXT:    lui a1, %hi(.LCPI12_0)
+; RV32IZHINX-NEXT:    lw a1, %lo(.LCPI12_0)(a1)
+; RV32IZHINX-NEXT:    fcvt.s.h a0, a0
+; RV32IZHINX-NEXT:    flt.s a1, a1, a0
+; RV32IZHINX-NEXT:    neg s0, a1
+; RV32IZHINX-NEXT:    fle.s a1, zero, a0
+; RV32IZHINX-NEXT:    neg s1, a1
+; RV32IZHINX-NEXT:    call __fixunssfdi@plt
+; RV32IZHINX-NEXT:    and a0, s1, a0
+; RV32IZHINX-NEXT:    or a0, s0, a0
+; RV32IZHINX-NEXT:    and a1, s1, a1
+; RV32IZHINX-NEXT:    or a1, s0, a1
+; RV32IZHINX-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZHINX-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
+; RV32IZHINX-NEXT:    lw s1, 4(sp) # 4-byte Folded Reload
+; RV32IZHINX-NEXT:    addi sp, sp, 16
+; RV32IZHINX-NEXT:    ret
+;
+; RV64IZHINX-LABEL: fcvt_lu_h_sat:
+; RV64IZHINX:       # %bb.0: # %start
+; RV64IZHINX-NEXT:    fcvt.lu.h a1, a0, rtz
+; RV64IZHINX-NEXT:    feq.h a0, a0, a0
+; RV64IZHINX-NEXT:    seqz a0, a0
+; RV64IZHINX-NEXT:    addi a0, a0, -1
+; RV64IZHINX-NEXT:    and a0, a0, a1
+; RV64IZHINX-NEXT:    ret
+;
+; RV32IZDINXZHINX-LABEL: fcvt_lu_h_sat:
+; RV32IZDINXZHINX:       # %bb.0: # %start
+; RV32IZDINXZHINX-NEXT:    addi sp, sp, -16
+; RV32IZDINXZHINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZDINXZHINX-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
+; RV32IZDINXZHINX-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
+; RV32IZDINXZHINX-NEXT:    lui a1, %hi(.LCPI12_0)
+; RV32IZDINXZHINX-NEXT:    lw a1, %lo(.LCPI12_0)(a1)
+; RV32IZDINXZHINX-NEXT:    fcvt.s.h a0, a0
+; RV32IZDINXZHINX-NEXT:    flt.s a1, a1, a0
+; RV32IZDINXZHINX-NEXT:    neg s0, a1
+; RV32IZDINXZHINX-NEXT:    fle.s a1, zero, a0
+; RV32IZDINXZHINX-NEXT:    neg s1, a1
+; RV32IZDINXZHINX-NEXT:    call __fixunssfdi@plt
+; RV32IZDINXZHINX-NEXT:    and a0, s1, a0
+; RV32IZDINXZHINX-NEXT:    or a0, s0, a0
+; RV32IZDINXZHINX-NEXT:    and a1, s1, a1
+; RV32IZDINXZHINX-NEXT:    or a1, s0, a1
+; RV32IZDINXZHINX-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZDINXZHINX-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
+; RV32IZDINXZHINX-NEXT:    lw s1, 4(sp) # 4-byte Folded Reload
+; RV32IZDINXZHINX-NEXT:    addi sp, sp, 16
+; RV32IZDINXZHINX-NEXT:    ret
+;
+; RV64IZDINXZHINX-LABEL: fcvt_lu_h_sat:
+; RV64IZDINXZHINX:       # %bb.0: # %start
+; RV64IZDINXZHINX-NEXT:    fcvt.lu.h a1, a0, rtz
+; RV64IZDINXZHINX-NEXT:    feq.h a0, a0, a0
+; RV64IZDINXZHINX-NEXT:    seqz a0, a0
+; RV64IZDINXZHINX-NEXT:    addi a0, a0, -1
+; RV64IZDINXZHINX-NEXT:    and a0, a0, a1
+; RV64IZDINXZHINX-NEXT:    ret
+;
 ; RV32I-LABEL: fcvt_lu_h_sat:
 ; RV32I:       # %bb.0: # %start
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s2, 0(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    slli a0, a0, 16

 ; CHECK64-IZFHMIN:       # %bb.0: # %start
 ; CHECK64-IZFHMIN-NEXT:    fcvt.s.h fa5, fa0
 ; CHECK64-IZFHMIN-NEXT:    fcvt.lu.s a0, fa5, rtz
 ; CHECK64-IZFHMIN-NEXT:    feq.s a1, fa5, fa5
 ; CHECK64-IZFHMIN-NEXT:    seqz a1, a1
 ; CHECK64-IZFHMIN-NEXT:    addi a1, a1, -1
 ; CHECK64-IZFHMIN-NEXT:    and a0, a1, a0
 ; CHECK64-IZFHMIN-NEXT:    ret
+;
+; CHECK32-IZHINXMIN-LABEL: fcvt_lu_h_sat:
+; CHECK32-IZHINXMIN:       # %bb.0: # %start
+; CHECK32-IZHINXMIN-NEXT:    addi sp, sp, -16
+; CHECK32-IZHINXMIN-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; CHECK32-IZHINXMIN-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
+; CHECK32-IZHINXMIN-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
+; CHECK32-IZHINXMIN-NEXT:    lui a1, %hi(.LCPI12_0)
+; CHECK32-IZHINXMIN-NEXT:    lw a1, %lo(.LCPI12_0)(a1)
+; CHECK32-IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECK32-IZHINXMIN-NEXT:    flt.s a1, a1, a0
+; CHECK32-IZHINXMIN-NEXT:    neg s0, a1
+; CHECK32-IZHINXMIN-NEXT:    fle.s a1, zero, a0
+; CHECK32-IZHINXMIN-NEXT:    neg s1, a1
+; CHECK32-IZHINXMIN-NEXT:    call __fixunssfdi@plt
+; CHECK32-IZHINXMIN-NEXT:    and a0, s1, a0
+; CHECK32-IZHINXMIN-NEXT:    or a0, s0, a0
+; CHECK32-IZHINXMIN-NEXT:    and a1, s1, a1
+; CHECK32-IZHINXMIN-NEXT:    or a1, s0, a1
+; CHECK32-IZHINXMIN-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; CHECK32-IZHINXMIN-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
+; CHECK32-IZHINXMIN-NEXT:    lw s1, 4(sp) # 4-byte Folded Reload
+; CHECK32-IZHINXMIN-NEXT:    addi sp, sp, 16
+; CHECK32-IZHINXMIN-NEXT:    ret
+;
+; CHECK64-IZHINXMIN-LABEL: fcvt_lu_h_sat:
+; CHECK64-IZHINXMIN:       # %bb.0: # %start
+; CHECK64-IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECK64-IZHINXMIN-NEXT:    fcvt.lu.s a1, a0, rtz
+; CHECK64-IZHINXMIN-NEXT:    feq.s a0, a0, a0
+; CHECK64-IZHINXMIN-NEXT:    seqz a0, a0
+; CHECK64-IZHINXMIN-NEXT:    addi a0, a0, -1
+; CHECK64-IZHINXMIN-NEXT:    and a0, a0, a1
+; CHECK64-IZHINXMIN-NEXT:    ret
+;
+; CHECK32-IZDINXZHINXMIN-LABEL: fcvt_lu_h_sat:
+; CHECK32-IZDINXZHINXMIN:       # %bb.0: # %start
+; CHECK32-IZDINXZHINXMIN-NEXT:    addi sp, sp, -16
+; CHECK32-IZDINXZHINXMIN-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; CHECK32-IZDINXZHINXMIN-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
+; CHECK32-IZDINXZHINXMIN-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
+; CHECK32-IZDINXZHINXMIN-NEXT:    lui a1, %hi(.LCPI12_0)
+; CHECK32-IZDINXZHINXMIN-NEXT:    lw a1, %lo(.LCPI12_0)(a1)
+; CHECK32-IZDINXZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECK32-IZDINXZHINXMIN-NEXT:    flt.s a1, a1, a0
+; CHECK32-IZDINXZHINXMIN-NEXT:    neg s0, a1
+; CHECK32-IZDINXZHINXMIN-NEXT:    fle.s a1, zero, a0
+; CHECK32-IZDINXZHINXMIN-NEXT:    neg s1, a1
+; CHECK32-IZDINXZHINXMIN-NEXT:    call __fixunssfdi@plt
+; CHECK32-IZDINXZHINXMIN-NEXT:    and a0, s1, a0
+; CHECK32-IZDINXZHINXMIN-NEXT:    or a0, s0, a0
+; CHECK32-IZDINXZHINXMIN-NEXT:    and a1, s1, a1
+; CHECK32-IZDINXZHINXMIN-NEXT:    or a1, s0, a1
+; CHECK32-IZDINXZHINXMIN-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; CHECK32-IZDINXZHINXMIN-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
+; CHECK32-IZDINXZHINXMIN-NEXT:    lw s1, 4(sp) # 4-byte Folded Reload
+; CHECK32-IZDINXZHINXMIN-NEXT:    addi sp, sp, 16
+; CHECK32-IZDINXZHINXMIN-NEXT:    ret
+;
+; CHECK64-IZDINXZHINXMIN-LABEL: fcvt_lu_h_sat:
+; CHECK64-IZDINXZHINXMIN:       # %bb.0: # %start
+; CHECK64-IZDINXZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECK64-IZDINXZHINXMIN-NEXT:    fcvt.lu.s a1, a0, rtz
+; CHECK64-IZDINXZHINXMIN-NEXT:    feq.s a0, a0, a0
+; CHECK64-IZDINXZHINXMIN-NEXT:    seqz a0, a0
+; CHECK64-IZDINXZHINXMIN-NEXT:    addi a0, a0, -1
+; CHECK64-IZDINXZHINXMIN-NEXT:    and a0, a0, a1
+; CHECK64-IZDINXZHINXMIN-NEXT:    ret
 start:
   %0 = tail call i64 @llvm.fptoui.sat.i64.f16(half %a)
   ret i64 %0
 }
 declare i64 @llvm.fptoui.sat.i64.f16(half)
 
 define half @fcvt_h_si(i16 %a) nounwind {
 ; RV32IZFH-LABEL: fcvt_h_si:

 ;
 ; RV64IDZFH-LABEL: fcvt_h_si:
 ; RV64IDZFH:       # %bb.0:
 ; RV64IDZFH-NEXT:    slli a0, a0, 48
 ; RV64IDZFH-NEXT:    srai a0, a0, 48
 ; RV64IDZFH-NEXT:    fcvt.h.w fa0, a0
 ; RV64IDZFH-NEXT:    ret
 ;
+; RV32IZHINX-LABEL: fcvt_h_si:
+; RV32IZHINX:       # %bb.0:
+; RV32IZHINX-NEXT:    slli a0, a0, 16
+; RV32IZHINX-NEXT:    srai a0, a0, 16
+; RV32IZHINX-NEXT:    fcvt.h.w a0, a0
+; RV32IZHINX-NEXT:    ret
+;
+; RV64IZHINX-LABEL: fcvt_h_si:
+; RV64IZHINX:       # %bb.0:
+; RV64IZHINX-NEXT:    slli a0, a0, 48
+; RV64IZHINX-NEXT:    srai a0, a0, 48
+; RV64IZHINX-NEXT:    fcvt.h.w a0, a0
+; RV64IZHINX-NEXT:    ret
+;
+; RV32IZDINXZHINX-LABEL: fcvt_h_si:
+; RV32IZDINXZHINX:       # %bb.0:
+; RV32IZDINXZHINX-NEXT:    slli a0, a0, 16
+; RV32IZDINXZHINX-NEXT:    srai a0, a0, 16
+; RV32IZDINXZHINX-NEXT:    fcvt.h.w a0, a0
+; RV32IZDINXZHINX-NEXT:    ret
+;
+; RV64IZDINXZHINX-LABEL: fcvt_h_si:
+; RV64IZDINXZHINX:       # %bb.0:
+; RV64IZDINXZHINX-NEXT:    slli a0, a0, 48
+; RV64IZDINXZHINX-NEXT:    srai a0, a0, 48
+; RV64IZDINXZHINX-NEXT:    fcvt.h.w a0, a0
+; RV64IZDINXZHINX-NEXT:    ret
+;
 ; RV32I-LABEL: fcvt_h_si:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    slli a0, a0, 16
 ; RV32I-NEXT:    srai a0, a0, 16
 ; RV32I-NEXT:    call __floatsisf@plt
 ; RV32I-NEXT:    call __truncsfhf2@plt

 ;
 ; CHECK64-IZFHMIN-LABEL: fcvt_h_si:
 ; CHECK64-IZFHMIN:       # %bb.0:
 ; CHECK64-IZFHMIN-NEXT:    slli a0, a0, 48
 ; CHECK64-IZFHMIN-NEXT:    srai a0, a0, 48
 ; CHECK64-IZFHMIN-NEXT:    fcvt.s.l fa5, a0
 ; CHECK64-IZFHMIN-NEXT:    fcvt.h.s fa0, fa5
 ; CHECK64-IZFHMIN-NEXT:    ret
+;
+; CHECK32-IZHINXMIN-LABEL: fcvt_h_si:
+; CHECK32-IZHINXMIN:       # %bb.0:
+; CHECK32-IZHINXMIN-NEXT:    slli a0, a0, 16
+; CHECK32-IZHINXMIN-NEXT:    srai a0, a0, 16
+; CHECK32-IZHINXMIN-NEXT:    fcvt.s.w a0, a0
+; CHECK32-IZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; CHECK32-IZHINXMIN-NEXT:    ret
+;
+; CHECK64-IZHINXMIN-LABEL: fcvt_h_si:
+; CHECK64-IZHINXMIN:       # %bb.0:
+; CHECK64-IZHINXMIN-NEXT:    slli a0, a0, 48
+; CHECK64-IZHINXMIN-NEXT:    srai a0, a0, 48
+; CHECK64-IZHINXMIN-NEXT:    fcvt.s.l a0, a0
+; CHECK64-IZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; CHECK64-IZHINXMIN-NEXT:    ret
+;
+; CHECK32-IZDINXZHINXMIN-LABEL: fcvt_h_si:
+; CHECK32-IZDINXZHINXMIN:       # %bb.0:
+; CHECK32-IZDINXZHINXMIN-NEXT:    slli a0, a0, 16
+; CHECK32-IZDINXZHINXMIN-NEXT:    srai a0, a0, 16
+; CHECK32-IZDINXZHINXMIN-NEXT:    fcvt.s.w a0, a0
+; CHECK32-IZDINXZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; CHECK32-IZDINXZHINXMIN-NEXT:    ret
+;
+; CHECK64-IZDINXZHINXMIN-LABEL: fcvt_h_si:
+; CHECK64-IZDINXZHINXMIN:       # %bb.0:
+; CHECK64-IZDINXZHINXMIN-NEXT:    slli a0, a0, 48
+; CHECK64-IZDINXZHINXMIN-NEXT:    srai a0, a0, 48
+; CHECK64-IZDINXZHINXMIN-NEXT:    fcvt.s.l a0, a0
+; CHECK64-IZDINXZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; CHECK64-IZDINXZHINXMIN-NEXT:    ret
   %1 = sitofp i16 %a to half
   ret half %1
 }
 
 define half @fcvt_h_si_signext(i16 signext %a) nounwind {
 ; CHECKIZFH-LABEL: fcvt_h_si_signext:
 ; CHECKIZFH:       # %bb.0:
 ; CHECKIZFH-NEXT:    fcvt.h.w fa0, a0
 ; CHECKIZFH-NEXT:    ret
 ;
 ; RV32IDZFH-LABEL: fcvt_h_si_signext:
 ; RV32IDZFH:       # %bb.0:
 ; RV32IDZFH-NEXT:    fcvt.h.w fa0, a0
 ; RV32IDZFH-NEXT:    ret
 ;
 ; RV64IDZFH-LABEL: fcvt_h_si_signext:
 ; RV64IDZFH:       # %bb.0:
 ; RV64IDZFH-NEXT:    fcvt.h.w fa0, a0
 ; RV64IDZFH-NEXT:    ret
 ;
+; CHECKIZHINX-LABEL: fcvt_h_si_signext:
+; CHECKIZHINX:       # %bb.0:
+; CHECKIZHINX-NEXT:    fcvt.h.w a0, a0
+; CHECKIZHINX-NEXT:    ret
+;
+; CHECKIZDINXZHINX-LABEL: fcvt_h_si_signext:
+; CHECKIZDINXZHINX:       # %bb.0:
+; CHECKIZDINXZHINX-NEXT:    fcvt.h.w a0, a0
+; CHECKIZDINXZHINX-NEXT:    ret
+;
 ; RV32I-LABEL: fcvt_h_si_signext:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __floatsisf@plt
 ; RV32I-NEXT:    call __truncsfhf2@plt
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16

 ; CHECK32-IZFHMIN-NEXT:    fcvt.h.s fa0, fa5
 ; CHECK32-IZFHMIN-NEXT:    ret
 ;
 ; CHECK64-IZFHMIN-LABEL: fcvt_h_si_signext:
 ; CHECK64-IZFHMIN:       # %bb.0:
 ; CHECK64-IZFHMIN-NEXT:    fcvt.s.l fa5, a0
 ; CHECK64-IZFHMIN-NEXT:    fcvt.h.s fa0, fa5
 ; CHECK64-IZFHMIN-NEXT:    ret
+;
+; CHECK32-IZHINXMIN-LABEL: fcvt_h_si_signext:
+; CHECK32-IZHINXMIN:       # %bb.0:
+; CHECK32-IZHINXMIN-NEXT:    fcvt.s.w a0, a0
+; CHECK32-IZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; CHECK32-IZHINXMIN-NEXT:    ret
+;
+; CHECK64-IZHINXMIN-LABEL: fcvt_h_si_signext:
+; CHECK64-IZHINXMIN:       # %bb.0:
+; CHECK64-IZHINXMIN-NEXT:    fcvt.s.l a0, a0
+; CHECK64-IZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; CHECK64-IZHINXMIN-NEXT:    ret
+;
+; CHECK32-IZDINXZHINXMIN-LABEL: fcvt_h_si_signext:
+; CHECK32-IZDINXZHINXMIN:       # %bb.0:
+; CHECK32-IZDINXZHINXMIN-NEXT:    fcvt.s.w a0, a0
+; CHECK32-IZDINXZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; CHECK32-IZDINXZHINXMIN-NEXT:    ret
+;
+; CHECK64-IZDINXZHINXMIN-LABEL: fcvt_h_si_signext:
+; CHECK64-IZDINXZHINXMIN:       # %bb.0:
+; CHECK64-IZDINXZHINXMIN-NEXT:    fcvt.s.l a0, a0
+; CHECK64-IZDINXZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; CHECK64-IZDINXZHINXMIN-NEXT:    ret
   %1 = sitofp i16 %a to half
   ret half %1
 }
 
 define half @fcvt_h_ui(i16 %a) nounwind {
 ; RV32IZFH-LABEL: fcvt_h_ui:
 ; RV32IZFH:       # %bb.0:
 ; RV32IZFH-NEXT:    slli a0, a0, 16

 ;
 ; RV64IDZFH-LABEL: fcvt_h_ui:
 ; RV64IDZFH:       # %bb.0:
 ; RV64IDZFH-NEXT:    slli a0, a0, 48
 ; RV64IDZFH-NEXT:    srli a0, a0, 48
 ; RV64IDZFH-NEXT:    fcvt.h.wu fa0, a0
 ; RV64IDZFH-NEXT:    ret
 ;
+; RV32IZHINX-LABEL: fcvt_h_ui:
+; RV32IZHINX:       # %bb.0:
+; RV32IZHINX-NEXT:    slli a0, a0, 16
+; RV32IZHINX-NEXT:    srli a0, a0, 16
+; RV32IZHINX-NEXT:    fcvt.h.wu a0, a0
+; RV32IZHINX-NEXT:    ret
+;
+; RV64IZHINX-LABEL: fcvt_h_ui:
+; RV64IZHINX:       # %bb.0:
+; RV64IZHINX-NEXT:    slli a0, a0, 48
+; RV64IZHINX-NEXT:    srli a0, a0, 48
+; RV64IZHINX-NEXT:    fcvt.h.wu a0, a0
+; RV64IZHINX-NEXT:    ret
+;
+; RV32IZDINXZHINX-LABEL: fcvt_h_ui:
+; RV32IZDINXZHINX:       # %bb.0:
+; RV32IZDINXZHINX-NEXT:    slli a0, a0, 16
+; RV32IZDINXZHINX-NEXT:    srli a0, a0, 16
+; RV32IZDINXZHINX-NEXT:    fcvt.h.wu a0, a0
+; RV32IZDINXZHINX-NEXT:    ret
+;
+; RV64IZDINXZHINX-LABEL: fcvt_h_ui:
+; RV64IZDINXZHINX:       # %bb.0:
+; RV64IZDINXZHINX-NEXT:    slli a0, a0, 48
+; RV64IZDINXZHINX-NEXT:    srli a0, a0, 48
+; RV64IZDINXZHINX-NEXT:    fcvt.h.wu a0, a0
+; RV64IZDINXZHINX-NEXT:    ret
+;
 ; RV32I-LABEL: fcvt_h_ui:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    slli a0, a0, 16
 ; RV32I-NEXT:    srli a0, a0, 16
 ; RV32I-NEXT:    call __floatunsisf@plt
 ; RV32I-NEXT:    call __truncsfhf2@plt

 ;
 ; CHECK64-IZFHMIN-LABEL: fcvt_h_ui:
 ; CHECK64-IZFHMIN:       # %bb.0:
 ; CHECK64-IZFHMIN-NEXT:    slli a0, a0, 48
 ; CHECK64-IZFHMIN-NEXT:    srli a0, a0, 48
 ; CHECK64-IZFHMIN-NEXT:    fcvt.s.lu fa5, a0
 ; CHECK64-IZFHMIN-NEXT:    fcvt.h.s fa0, fa5
 ; CHECK64-IZFHMIN-NEXT:    ret
+;
+; CHECK32-IZHINXMIN-LABEL: fcvt_h_ui:
+; CHECK32-IZHINXMIN:       # %bb.0:
+; CHECK32-IZHINXMIN-NEXT:    slli a0, a0, 16
+; CHECK32-IZHINXMIN-NEXT:    srli a0, a0, 16
+; CHECK32-IZHINXMIN-NEXT:    fcvt.s.wu a0, a0
+; CHECK32-IZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; CHECK32-IZHINXMIN-NEXT:    ret
+;
+; CHECK64-IZHINXMIN-LABEL: fcvt_h_ui:
+; CHECK64-IZHINXMIN:       # %bb.0:
+; CHECK64-IZHINXMIN-NEXT:    slli a0, a0, 48
+; CHECK64-IZHINXMIN-NEXT:    srli a0, a0, 48
+; CHECK64-IZHINXMIN-NEXT:    fcvt.s.lu a0, a0
+; CHECK64-IZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; CHECK64-IZHINXMIN-NEXT:    ret
+;
+; CHECK32-IZDINXZHINXMIN-LABEL: fcvt_h_ui:
+; CHECK32-IZDINXZHINXMIN:       # %bb.0:
+; CHECK32-IZDINXZHINXMIN-NEXT:    slli a0, a0, 16
+; CHECK32-IZDINXZHINXMIN-NEXT:    srli a0, a0, 16
+; CHECK32-IZDINXZHINXMIN-NEXT:    fcvt.s.wu a0, a0
+; CHECK32-IZDINXZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; CHECK32-IZDINXZHINXMIN-NEXT:    ret
+;
+; CHECK64-IZDINXZHINXMIN-LABEL: fcvt_h_ui:
+; CHECK64-IZDINXZHINXMIN:       # %bb.0:
+; CHECK64-IZDINXZHINXMIN-NEXT:    slli a0, a0, 48
+; CHECK64-IZDINXZHINXMIN-NEXT:    srli a0, a0, 48
+; CHECK64-IZDINXZHINXMIN-NEXT:    fcvt.s.lu a0, a0
+; CHECK64-IZDINXZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; CHECK64-IZDINXZHINXMIN-NEXT:    ret
   %1 = uitofp i16 %a to half
   ret half %1
 }
 
 define half @fcvt_h_ui_zeroext(i16 zeroext %a) nounwind {
 ; CHECKIZFH-LABEL: fcvt_h_ui_zeroext:
 ; CHECKIZFH:       # %bb.0:
 ; CHECKIZFH-NEXT:    fcvt.h.wu fa0, a0
 ; CHECKIZFH-NEXT:    ret
 ;
 ; RV32IDZFH-LABEL: fcvt_h_ui_zeroext:
 ; RV32IDZFH:       # %bb.0:
 ; RV32IDZFH-NEXT:    fcvt.h.wu fa0, a0
 ; RV32IDZFH-NEXT:    ret
 ;
 ; RV64IDZFH-LABEL: fcvt_h_ui_zeroext:
 ; RV64IDZFH:       # %bb.0:
 ; RV64IDZFH-NEXT:    fcvt.h.wu fa0, a0
 ; RV64IDZFH-NEXT:    ret
 ;
+; CHECKIZHINX-LABEL: fcvt_h_ui_zeroext:
+; CHECKIZHINX:       # %bb.0:
+; CHECKIZHINX-NEXT:    fcvt.h.wu a0, a0
+; CHECKIZHINX-NEXT:    ret
+;
+; CHECKIZDINXZHINX-LABEL: fcvt_h_ui_zeroext:
+; CHECKIZDINXZHINX:       # %bb.0:
+; CHECKIZDINXZHINX-NEXT:    fcvt.h.wu a0, a0
+; CHECKIZDINXZHINX-NEXT:    ret
+;
 ; RV32I-LABEL: fcvt_h_ui_zeroext:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __floatunsisf@plt
 ; RV32I-NEXT:    call __truncsfhf2@plt
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16

 ; CHECK32-IZFHMIN-NEXT:    fcvt.h.s fa0, fa5
 ; CHECK32-IZFHMIN-NEXT:    ret
 ;
 ; CHECK64-IZFHMIN-LABEL: fcvt_h_ui_zeroext:
 ; CHECK64-IZFHMIN:       # %bb.0:
 ; CHECK64-IZFHMIN-NEXT:    fcvt.s.lu fa5, a0
 ; CHECK64-IZFHMIN-NEXT:    fcvt.h.s fa0, fa5
 ; CHECK64-IZFHMIN-NEXT:    ret
+;
+; CHECK32-IZHINXMIN-LABEL: fcvt_h_ui_zeroext:
+; CHECK32-IZHINXMIN:       # %bb.0:
+; CHECK32-IZHINXMIN-NEXT:    fcvt.s.wu a0, a0
+; CHECK32-IZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; CHECK32-IZHINXMIN-NEXT:    ret
+;
+; CHECK64-IZHINXMIN-LABEL: fcvt_h_ui_zeroext:
+; CHECK64-IZHINXMIN:       # %bb.0:
+; CHECK64-IZHINXMIN-NEXT:    fcvt.s.lu a0, a0
+; CHECK64-IZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; CHECK64-IZHINXMIN-NEXT:    ret
+;
+; CHECK32-IZDINXZHINXMIN-LABEL: fcvt_h_ui_zeroext:
+; CHECK32-IZDINXZHINXMIN:       # %bb.0:
+; CHECK32-IZDINXZHINXMIN-NEXT:    fcvt.s.wu a0, a0
+; CHECK32-IZDINXZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; CHECK32-IZDINXZHINXMIN-NEXT:    ret
+;
+; CHECK64-IZDINXZHINXMIN-LABEL: fcvt_h_ui_zeroext:
+; CHECK64-IZDINXZHINXMIN:       # %bb.0:
+; CHECK64-IZDINXZHINXMIN-NEXT:    fcvt.s.lu a0, a0
+; CHECK64-IZDINXZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; CHECK64-IZDINXZHINXMIN-NEXT:    ret
   %1 = uitofp i16 %a to half
   ret half %1
 }
 
 define half @fcvt_h_w(i32 %a) nounwind {
 ; CHECKIZFH-LABEL: fcvt_h_w:
 ; CHECKIZFH:       # %bb.0:
 ; CHECKIZFH-NEXT:    fcvt.h.w fa0, a0
 ; CHECKIZFH-NEXT:    ret
 ;
 ; RV32IDZFH-LABEL: fcvt_h_w:
 ; RV32IDZFH:       # %bb.0:
 ; RV32IDZFH-NEXT:    fcvt.h.w fa0, a0
 ; RV32IDZFH-NEXT:    ret
 ;
 ; RV64IDZFH-LABEL: fcvt_h_w:
 ; RV64IDZFH:       # %bb.0:
 ; RV64IDZFH-NEXT:    fcvt.h.w fa0, a0
 ; RV64IDZFH-NEXT:    ret
 ;
+; CHECKIZHINX-LABEL: fcvt_h_w:
+; CHECKIZHINX:       # %bb.0:
+; CHECKIZHINX-NEXT:    fcvt.h.w a0, a0
+; CHECKIZHINX-NEXT:    ret
+;
+; CHECKIZDINXZHINX-LABEL: fcvt_h_w:
+; CHECKIZDINXZHINX:       # %bb.0:
+; CHECKIZDINXZHINX-NEXT:    fcvt.h.w a0, a0
+; CHECKIZDINXZHINX-NEXT:    ret
+;
 ; RV32I-LABEL: fcvt_h_w:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __floatsisf@plt
 ; RV32I-NEXT:    call __truncsfhf2@plt
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16

 ; CHECK32-IZFHMIN-NEXT:    ret
 ;
 ; CHECK64-IZFHMIN-LABEL: fcvt_h_w:
 ; CHECK64-IZFHMIN:       # %bb.0:
 ; CHECK64-IZFHMIN-NEXT:    sext.w a0, a0
 ; CHECK64-IZFHMIN-NEXT:    fcvt.s.l fa5, a0
 ; CHECK64-IZFHMIN-NEXT:    fcvt.h.s fa0, fa5
 ; CHECK64-IZFHMIN-NEXT:    ret
+;
+; CHECK32-IZHINXMIN-LABEL: fcvt_h_w:
+; CHECK32-IZHINXMIN:       # %bb.0:
+; CHECK32-IZHINXMIN-NEXT:    fcvt.s.w a0, a0
+; CHECK32-IZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; CHECK32-IZHINXMIN-NEXT:    ret
+;
+; CHECK64-IZHINXMIN-LABEL: fcvt_h_w:
+; CHECK64-IZHINXMIN:       # %bb.0:
+; CHECK64-IZHINXMIN-NEXT:    sext.w a0, a0
+; CHECK64-IZHINXMIN-NEXT:    fcvt.s.l a0, a0
+; CHECK64-IZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; CHECK64-IZHINXMIN-NEXT:    ret
+;
+; CHECK32-IZDINXZHINXMIN-LABEL: fcvt_h_w:
+; CHECK32-IZDINXZHINXMIN:       # %bb.0:
+; CHECK32-IZDINXZHINXMIN-NEXT:    fcvt.s.w a0, a0
+; CHECK32-IZDINXZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; CHECK32-IZDINXZHINXMIN-NEXT:    ret
+;
+; CHECK64-IZDINXZHINXMIN-LABEL: fcvt_h_w:
+; CHECK64-IZDINXZHINXMIN:       # %bb.0:
+; CHECK64-IZDINXZHINXMIN-NEXT:    sext.w a0, a0
+; CHECK64-IZDINXZHINXMIN-NEXT:    fcvt.s.l a0, a0
+; CHECK64-IZDINXZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; CHECK64-IZDINXZHINXMIN-NEXT:    ret
   %1 = sitofp i32 %a to half
   ret half %1
 }
 
 define half @fcvt_h_w_load(ptr %p) nounwind {
 ; CHECKIZFH-LABEL: fcvt_h_w_load:
 ; CHECKIZFH:       # %bb.0:
 ; CHECKIZFH-NEXT:    lw a0, 0(a0)
 ; CHECKIZFH-NEXT:    fcvt.h.w fa0, a0
 ; CHECKIZFH-NEXT:    ret
 ;
 ; RV32IDZFH-LABEL: fcvt_h_w_load:
 ; RV32IDZFH:       # %bb.0:
 ; RV32IDZFH-NEXT:    lw a0, 0(a0)
 ; RV32IDZFH-NEXT:    fcvt.h.w fa0, a0
 ; RV32IDZFH-NEXT:    ret
 ;
 ; RV64IDZFH-LABEL: fcvt_h_w_load:
 ; RV64IDZFH:       # %bb.0:
 ; RV64IDZFH-NEXT:    lw a0, 0(a0)
 ; RV64IDZFH-NEXT:    fcvt.h.w fa0, a0
 ; RV64IDZFH-NEXT:    ret
 ;
+; CHECKIZHINX-LABEL: fcvt_h_w_load:
+; CHECKIZHINX:       # %bb.0:
+; CHECKIZHINX-NEXT:    lw a0, 0(a0)
+; CHECKIZHINX-NEXT:    fcvt.h.w a0, a0
+; CHECKIZHINX-NEXT:    ret
+;
+; CHECKIZDINXZHINX-LABEL: fcvt_h_w_load:
+; CHECKIZDINXZHINX:       # %bb.0:
+; CHECKIZDINXZHINX-NEXT:    lw a0, 0(a0)
+; CHECKIZDINXZHINX-NEXT:    fcvt.h.w a0, a0
+; CHECKIZDINXZHINX-NEXT:    ret
+;
 ; RV32I-LABEL: fcvt_h_w_load:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    lw a0, 0(a0)
 ; RV32I-NEXT:    call __floatsisf@plt
 ; RV32I-NEXT:    call __truncsfhf2@plt
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload

 ; CHECK32-IZFHMIN-NEXT:    ret
 ;
 ; CHECK64-IZFHMIN-LABEL: fcvt_h_w_load:
 ; CHECK64-IZFHMIN:       # %bb.0:
 ; CHECK64-IZFHMIN-NEXT:    lw a0, 0(a0)
 ; CHECK64-IZFHMIN-NEXT:    fcvt.s.l fa5, a0
 ; CHECK64-IZFHMIN-NEXT:    fcvt.h.s fa0, fa5
 ; CHECK64-IZFHMIN-NEXT:    ret
+;
+; CHECK32-IZHINXMIN-LABEL: fcvt_h_w_load:
+; CHECK32-IZHINXMIN:       # %bb.0:
+; CHECK32-IZHINXMIN-NEXT:    lw a0, 0(a0)
+; CHECK32-IZHINXMIN-NEXT:    fcvt.s.w a0, a0
+; CHECK32-IZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; CHECK32-IZHINXMIN-NEXT:    ret
+;
+; CHECK64-IZHINXMIN-LABEL: fcvt_h_w_load:
+; CHECK64-IZHINXMIN:       # %bb.0:
+; CHECK64-IZHINXMIN-NEXT:    lw a0, 0(a0)
+; CHECK64-IZHINXMIN-NEXT:    fcvt.s.l a0, a0
+; CHECK64-IZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; CHECK64-IZHINXMIN-NEXT:    ret
+;
+; CHECK32-IZDINXZHINXMIN-LABEL: fcvt_h_w_load:
+; CHECK32-IZDINXZHINXMIN:       # %bb.0:
+; CHECK32-IZDINXZHINXMIN-NEXT:    lw a0, 0(a0)
+; CHECK32-IZDINXZHINXMIN-NEXT:    fcvt.s.w a0, a0
+; CHECK32-IZDINXZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; CHECK32-IZDINXZHINXMIN-NEXT:    ret
+;
+; CHECK64-IZDINXZHINXMIN-LABEL: fcvt_h_w_load:
+; CHECK64-IZDINXZHINXMIN:       # %bb.0:
+; CHECK64-IZDINXZHINXMIN-NEXT:    lw a0, 0(a0)
+; CHECK64-IZDINXZHINXMIN-NEXT:    fcvt.s.l a0, a0
+; CHECK64-IZDINXZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; CHECK64-IZDINXZHINXMIN-NEXT:    ret
   %a = load i32, ptr %p
   %1 = sitofp i32 %a to half
   ret half %1
 }
 
 define half @fcvt_h_wu(i32 %a) nounwind {
 ; CHECKIZFH-LABEL: fcvt_h_wu:
 ; CHECKIZFH:       # %bb.0:
 ; CHECKIZFH-NEXT:    fcvt.h.wu fa0, a0
 ; CHECKIZFH-NEXT:    ret
 ;
 ; RV32IDZFH-LABEL: fcvt_h_wu:
 ; RV32IDZFH:       # %bb.0:
 ; RV32IDZFH-NEXT:    fcvt.h.wu fa0, a0
 ; RV32IDZFH-NEXT:    ret
 ;
 ; RV64IDZFH-LABEL: fcvt_h_wu:
 ; RV64IDZFH:       # %bb.0:
 ; RV64IDZFH-NEXT:    fcvt.h.wu fa0, a0
 ; RV64IDZFH-NEXT:    ret
 ;
+; CHECKIZHINX-LABEL: fcvt_h_wu:
+; CHECKIZHINX:       # %bb.0:
+; CHECKIZHINX-NEXT:    fcvt.h.wu a0, a0
+; CHECKIZHINX-NEXT:    ret
+;
+; CHECKIZDINXZHINX-LABEL: fcvt_h_wu:
+; CHECKIZDINXZHINX:       # %bb.0:
+; CHECKIZDINXZHINX-NEXT:    fcvt.h.wu a0, a0
+; CHECKIZDINXZHINX-NEXT:    ret
+;
 ; RV32I-LABEL: fcvt_h_wu:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __floatunsisf@plt
 ; RV32I-NEXT:    call __truncsfhf2@plt
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16

 ;
 ; CHECK64-IZFHMIN-LABEL: fcvt_h_wu:
 ; CHECK64-IZFHMIN:       # %bb.0:
 ; CHECK64-IZFHMIN-NEXT:    slli a0, a0, 32
 ; CHECK64-IZFHMIN-NEXT:    srli a0, a0, 32
 ; CHECK64-IZFHMIN-NEXT:    fcvt.s.lu fa5, a0
 ; CHECK64-IZFHMIN-NEXT:    fcvt.h.s fa0, fa5
 ; CHECK64-IZFHMIN-NEXT:    ret
+;
+; CHECK32-IZHINXMIN-LABEL: fcvt_h_wu:
+; CHECK32-IZHINXMIN:       # %bb.0:
+; CHECK32-IZHINXMIN-NEXT:    fcvt.s.wu a0, a0
+; CHECK32-IZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; CHECK32-IZHINXMIN-NEXT:    ret
+;
+; CHECK64-IZHINXMIN-LABEL: fcvt_h_wu:
+; CHECK64-IZHINXMIN:       # %bb.0:
+; CHECK64-IZHINXMIN-NEXT:    slli a0, a0, 32
+; CHECK64-IZHINXMIN-NEXT:    srli a0, a0, 32
+; CHECK64-IZHINXMIN-NEXT:    fcvt.s.lu a0, a0
+; CHECK64-IZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; CHECK64-IZHINXMIN-NEXT:    ret
+;
+; CHECK32-IZDINXZHINXMIN-LABEL: fcvt_h_wu:
+; CHECK32-IZDINXZHINXMIN:       # %bb.0:
+; CHECK32-IZDINXZHINXMIN-NEXT:    fcvt.s.wu a0, a0
+; CHECK32-IZDINXZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; CHECK32-IZDINXZHINXMIN-NEXT:    ret
+;
+; CHECK64-IZDINXZHINXMIN-LABEL: fcvt_h_wu:
+; CHECK64-IZDINXZHINXMIN:       # %bb.0:
+; CHECK64-IZDINXZHINXMIN-NEXT:    slli a0, a0, 32
+; CHECK64-IZDINXZHINXMIN-NEXT:    srli a0, a0, 32
+; CHECK64-IZDINXZHINXMIN-NEXT:    fcvt.s.lu a0, a0
+; CHECK64-IZDINXZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; CHECK64-IZDINXZHINXMIN-NEXT:    ret
   %1 = uitofp i32 %a to half
   ret half %1
 }
 
 define half @fcvt_h_wu_load(ptr %p) nounwind {
 ; RV32IZFH-LABEL: fcvt_h_wu_load:
 ; RV32IZFH:       # %bb.0:
 ; RV32IZFH-NEXT:    lw a0, 0(a0)

 ; RV32IDZFH-NEXT:    ret
 ;
 ; RV64IDZFH-LABEL: fcvt_h_wu_load:
 ; RV64IDZFH:       # %bb.0:
 ; RV64IDZFH-NEXT:    lwu a0, 0(a0)
 ; RV64IDZFH-NEXT:    fcvt.h.wu fa0, a0
 ; RV64IDZFH-NEXT:    ret
 ;
+; RV32IZHINX-LABEL: fcvt_h_wu_load:
+; RV32IZHINX:       # %bb.0:
+; RV32IZHINX-NEXT:    lw a0, 0(a0)
+; RV32IZHINX-NEXT:    fcvt.h.wu a0, a0
+; RV32IZHINX-NEXT:    ret
+;
+; RV64IZHINX-LABEL: fcvt_h_wu_load:
+; RV64IZHINX:       # %bb.0:
+; RV64IZHINX-NEXT:    lwu a0, 0(a0)
+; RV64IZHINX-NEXT:    fcvt.h.wu a0, a0
+; RV64IZHINX-NEXT:    ret
+;
+; RV32IZDINXZHINX-LABEL: fcvt_h_wu_load:
+; RV32IZDINXZHINX:       # %bb.0:
+; RV32IZDINXZHINX-NEXT:    lw a0, 0(a0)
+; RV32IZDINXZHINX-NEXT:    fcvt.h.wu a0, a0
+; RV32IZDINXZHINX-NEXT:    ret
+;
+; RV64IZDINXZHINX-LABEL: fcvt_h_wu_load:
+; RV64IZDINXZHINX:       # %bb.0:
+; RV64IZDINXZHINX-NEXT:    lwu a0, 0(a0)
+; RV64IZDINXZHINX-NEXT:    fcvt.h.wu a0, a0
+; RV64IZDINXZHINX-NEXT:    ret
+;
 ; RV32I-LABEL: fcvt_h_wu_load:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    lw a0, 0(a0)
 ; RV32I-NEXT:    call __floatunsisf@plt
 ; RV32I-NEXT:    call __truncsfhf2@plt
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload

 ; CHECK32-IZFHMIN-NEXT:    ret
 ;
 ; CHECK64-IZFHMIN-LABEL: fcvt_h_wu_load:
 ; CHECK64-IZFHMIN:       # %bb.0:
 ; CHECK64-IZFHMIN-NEXT:    lwu a0, 0(a0)
 ; CHECK64-IZFHMIN-NEXT:    fcvt.s.lu fa5, a0
 ; CHECK64-IZFHMIN-NEXT:    fcvt.h.s fa0, fa5
 ; CHECK64-IZFHMIN-NEXT:    ret
+;
+; CHECK32-IZHINXMIN-LABEL: fcvt_h_wu_load:
+; CHECK32-IZHINXMIN:       # %bb.0:
+; CHECK32-IZHINXMIN-NEXT:    lw a0, 0(a0)
+; CHECK32-IZHINXMIN-NEXT:    fcvt.s.wu a0, a0
+; CHECK32-IZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; CHECK32-IZHINXMIN-NEXT:    ret
+;
+; CHECK64-IZHINXMIN-LABEL: fcvt_h_wu_load:
+; CHECK64-IZHINXMIN:       # %bb.0:
+; CHECK64-IZHINXMIN-NEXT:    lwu a0, 0(a0)
+; CHECK64-IZHINXMIN-NEXT:    fcvt.s.lu a0, a0
+; CHECK64-IZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; CHECK64-IZHINXMIN-NEXT:    ret
+;
+; CHECK32-IZDINXZHINXMIN-LABEL: fcvt_h_wu_load:
+; CHECK32-IZDINXZHINXMIN:       # %bb.0:
+; CHECK32-IZDINXZHINXMIN-NEXT:    lw a0, 0(a0)
+; CHECK32-IZDINXZHINXMIN-NEXT:    fcvt.s.wu a0, a0
+; CHECK32-IZDINXZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; CHECK32-IZDINXZHINXMIN-NEXT:    ret
+;
+; CHECK64-IZDINXZHINXMIN-LABEL: fcvt_h_wu_load:
+; CHECK64-IZDINXZHINXMIN:       # %bb.0:
+; CHECK64-IZDINXZHINXMIN-NEXT:    lwu a0, 0(a0)
+; CHECK64-IZDINXZHINXMIN-NEXT:    fcvt.s.lu a0, a0
+; CHECK64-IZDINXZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; CHECK64-IZDINXZHINXMIN-NEXT:    ret
   %a = load i32, ptr %p
   %1 = uitofp i32 %a to half
   ret half %1
 }
 
 define half @fcvt_h_l(i64 %a) nounwind {
 ; RV32IZFH-LABEL: fcvt_h_l:
 ; RV32IZFH:       # %bb.0:

 ; RV32IDZFH-NEXT:    addi sp, sp, 16
 ; RV32IDZFH-NEXT:    ret
 ;
 ; RV64IDZFH-LABEL: fcvt_h_l:
 ; RV64IDZFH:       # %bb.0:
 ; RV64IDZFH-NEXT:    fcvt.h.l fa0, a0
 ; RV64IDZFH-NEXT:    ret
 ;
+; RV32IZHINX-LABEL: fcvt_h_l:
+; RV32IZHINX:       # %bb.0:
+; RV32IZHINX-NEXT:    addi sp, sp, -16
+; RV32IZHINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZHINX-NEXT:    call __floatdihf@plt
+; RV32IZHINX-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZHINX-NEXT:    addi sp, sp, 16
+; RV32IZHINX-NEXT:    ret
+;
+; RV64IZHINX-LABEL: fcvt_h_l:
+; RV64IZHINX:       # %bb.0:
+; RV64IZHINX-NEXT:    fcvt.h.l a0, a0
+; RV64IZHINX-NEXT:    ret
+;
+; RV32IZDINXZHINX-LABEL: fcvt_h_l:
+; RV32IZDINXZHINX:       # %bb.0:
+; RV32IZDINXZHINX-NEXT:    addi sp, sp, -16
+; RV32IZDINXZHINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZDINXZHINX-NEXT:    call __floatdihf@plt
+; RV32IZDINXZHINX-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZDINXZHINX-NEXT:    addi sp, sp, 16
+; RV32IZDINXZHINX-NEXT:    ret
+;
+; RV64IZDINXZHINX-LABEL: fcvt_h_l:
+; RV64IZDINXZHINX:       # %bb.0:
+; RV64IZDINXZHINX-NEXT:    fcvt.h.l a0, a0
+; RV64IZDINXZHINX-NEXT:    ret
+;
 ; RV32I-LABEL: fcvt_h_l:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __floatdisf@plt
 ; RV32I-NEXT:    call __truncsfhf2@plt
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16

 ; CHECK32-IZFHMIN-NEXT:    addi sp, sp, 16
 ; CHECK32-IZFHMIN-NEXT:    ret
 ;
 ; CHECK64-IZFHMIN-LABEL: fcvt_h_l:
 ; CHECK64-IZFHMIN:       # %bb.0:
 ; CHECK64-IZFHMIN-NEXT:    fcvt.s.l fa5, a0
 ; CHECK64-IZFHMIN-NEXT:    fcvt.h.s fa0, fa5
 ; CHECK64-IZFHMIN-NEXT:    ret
+;
+; CHECK32-IZHINXMIN-LABEL: fcvt_h_l:
+; CHECK32-IZHINXMIN:       # %bb.0:
+; CHECK32-IZHINXMIN-NEXT:    addi sp, sp, -16
+; CHECK32-IZHINXMIN-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; CHECK32-IZHINXMIN-NEXT:    call __floatdihf@plt
+; CHECK32-IZHINXMIN-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; CHECK32-IZHINXMIN-NEXT:    addi sp, sp, 16
+; CHECK32-IZHINXMIN-NEXT:    ret
+;
+; CHECK64-IZHINXMIN-LABEL: fcvt_h_l:
+; CHECK64-IZHINXMIN:       # %bb.0:
+; CHECK64-IZHINXMIN-NEXT:    fcvt.s.l a0, a0
+; CHECK64-IZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; CHECK64-IZHINXMIN-NEXT:    ret
+;
+; CHECK32-IZDINXZHINXMIN-LABEL: fcvt_h_l:
+; CHECK32-IZDINXZHINXMIN:       # %bb.0:
+; CHECK32-IZDINXZHINXMIN-NEXT:    addi sp, sp, -16
+; CHECK32-IZDINXZHINXMIN-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; CHECK32-IZDINXZHINXMIN-NEXT:    call __floatdihf@plt
+; CHECK32-IZDINXZHINXMIN-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; CHECK32-IZDINXZHINXMIN-NEXT:    addi sp, sp, 16
+; CHECK32-IZDINXZHINXMIN-NEXT:    ret
+;
+; CHECK64-IZDINXZHINXMIN-LABEL: fcvt_h_l:
+; CHECK64-IZDINXZHINXMIN:       # %bb.0:
+; CHECK64-IZDINXZHINXMIN-NEXT:    fcvt.s.l a0, a0
+; CHECK64-IZDINXZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; CHECK64-IZDINXZHINXMIN-NEXT:    ret
   %1 = sitofp i64 %a to half
   ret half %1
 }
 
 define half @fcvt_h_lu(i64 %a) nounwind {
 ; RV32IZFH-LABEL: fcvt_h_lu:
 ; RV32IZFH:       # %bb.0:
 ; RV32IZFH-NEXT:    addi sp, sp, -16

 ; RV32IDZFH-NEXT:    addi sp, sp, 16
 ; RV32IDZFH-NEXT:    ret
 ;
 ; RV64IDZFH-LABEL: fcvt_h_lu:
 ; RV64IDZFH:       # %bb.0:
 ; RV64IDZFH-NEXT:    fcvt.h.lu fa0, a0
 ; RV64IDZFH-NEXT:    ret
 ;
+; RV32IZHINX-LABEL: fcvt_h_lu:
+; RV32IZHINX:       # %bb.0:
+; RV32IZHINX-NEXT:    addi sp, sp, -16
+; RV32IZHINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZHINX-NEXT:    call __floatundihf@plt
+; RV32IZHINX-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZHINX-NEXT:    addi sp, sp, 16
+; RV32IZHINX-NEXT:    ret
+;
+; RV64IZHINX-LABEL: fcvt_h_lu:
+; RV64IZHINX:       # %bb.0:
+; RV64IZHINX-NEXT:    fcvt.h.lu a0, a0
+; RV64IZHINX-NEXT:    ret
+;
+; RV32IZDINXZHINX-LABEL: fcvt_h_lu:
+; RV32IZDINXZHINX:       # %bb.0:
+; RV32IZDINXZHINX-NEXT:    addi sp, sp, -16
+; RV32IZDINXZHINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZDINXZHINX-NEXT:    call __floatundihf@plt
+; RV32IZDINXZHINX-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZDINXZHINX-NEXT:    addi sp, sp, 16
+; RV32IZDINXZHINX-NEXT:    ret
+;
+; RV64IZDINXZHINX-LABEL: fcvt_h_lu:
+; RV64IZDINXZHINX:       # %bb.0:
+; RV64IZDINXZHINX-NEXT:    fcvt.h.lu a0, a0
+; RV64IZDINXZHINX-NEXT:    ret
+;
 ; RV32I-LABEL: fcvt_h_lu:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __floatundisf@plt
 ; RV32I-NEXT:    call __truncsfhf2@plt
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16

 ; CHECK32-IZFHMIN-NEXT:    addi sp, sp, 16
 ; CHECK32-IZFHMIN-NEXT:    ret
 ;
 ; CHECK64-IZFHMIN-LABEL: fcvt_h_lu:
 ; CHECK64-IZFHMIN:       # %bb.0:
 ; CHECK64-IZFHMIN-NEXT:    fcvt.s.lu fa5, a0
 ; CHECK64-IZFHMIN-NEXT:    fcvt.h.s fa0, fa5
 ; CHECK64-IZFHMIN-NEXT:    ret
+;
+; CHECK32-IZHINXMIN-LABEL: fcvt_h_lu:
+; CHECK32-IZHINXMIN:       # %bb.0:
+; CHECK32-IZHINXMIN-NEXT:    addi sp, sp, -16
+; CHECK32-IZHINXMIN-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; CHECK32-IZHINXMIN-NEXT:    call __floatundihf@plt
+; CHECK32-IZHINXMIN-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; CHECK32-IZHINXMIN-NEXT:    addi sp, sp, 16
+; CHECK32-IZHINXMIN-NEXT:    ret
+;
+; CHECK64-IZHINXMIN-LABEL: fcvt_h_lu:
+; CHECK64-IZHINXMIN:       # %bb.0:
+; CHECK64-IZHINXMIN-NEXT:    fcvt.s.lu a0, a0
+; CHECK64-IZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; CHECK64-IZHINXMIN-NEXT:    ret
+;
+; CHECK32-IZDINXZHINXMIN-LABEL: fcvt_h_lu:
+; CHECK32-IZDINXZHINXMIN:       # %bb.0:
+; CHECK32-IZDINXZHINXMIN-NEXT:    addi sp, sp, -16
+; CHECK32-IZDINXZHINXMIN-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; CHECK32-IZDINXZHINXMIN-NEXT:    call __floatundihf@plt
+; CHECK32-IZDINXZHINXMIN-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; CHECK32-IZDINXZHINXMIN-NEXT:    addi sp, sp, 16
+; CHECK32-IZDINXZHINXMIN-NEXT:    ret
+;
+; CHECK64-IZDINXZHINXMIN-LABEL: fcvt_h_lu:
+; CHECK64-IZDINXZHINXMIN:       # %bb.0:
+; CHECK64-IZDINXZHINXMIN-NEXT:    fcvt.s.lu a0, a0
+; CHECK64-IZDINXZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; CHECK64-IZDINXZHINXMIN-NEXT:    ret
   %1 = uitofp i64 %a to half
   ret half %1
 }
 
 define half @fcvt_h_s(float %a) nounwind {
 ; CHECKIZFH-LABEL: fcvt_h_s:
 ; CHECKIZFH:       # %bb.0:
 ; CHECKIZFH-NEXT:    fcvt.h.s fa0, fa0
 ; CHECKIZFH-NEXT:    ret
 ;
 ; RV32IDZFH-LABEL: fcvt_h_s:
 ; RV32IDZFH:       # %bb.0:
 ; RV32IDZFH-NEXT:    fcvt.h.s fa0, fa0
 ; RV32IDZFH-NEXT:    ret
 ;
 ; RV64IDZFH-LABEL: fcvt_h_s:
 ; RV64IDZFH:       # %bb.0:
 ; RV64IDZFH-NEXT:    fcvt.h.s fa0, fa0
 ; RV64IDZFH-NEXT:    ret
 ;
+; CHECKIZHINX-LABEL: fcvt_h_s:
+; CHECKIZHINX:       # %bb.0:
+; CHECKIZHINX-NEXT:    fcvt.h.s a0, a0
+; CHECKIZHINX-NEXT:    ret
+;
+; CHECKIZDINXZHINX-LABEL: fcvt_h_s:
+; CHECKIZDINXZHINX:       # %bb.0:
+; CHECKIZDINXZHINX-NEXT:    fcvt.h.s a0, a0
+; CHECKIZDINXZHINX-NEXT:    ret
+;
 ; RV32I-LABEL: fcvt_h_s:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __truncsfhf2@plt
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret

 ; CHECK32-IZFHMIN:       # %bb.0:
 ; CHECK32-IZFHMIN-NEXT:    fcvt.h.s fa0, fa0
 ; CHECK32-IZFHMIN-NEXT:    ret
 ;
 ; CHECK64-IZFHMIN-LABEL: fcvt_h_s:
 ; CHECK64-IZFHMIN:       # %bb.0:
 ; CHECK64-IZFHMIN-NEXT:    fcvt.h.s fa0, fa0
 ; CHECK64-IZFHMIN-NEXT:    ret
+;
+; CHECK32-IZHINXMIN-LABEL: fcvt_h_s:
+; CHECK32-IZHINXMIN:       # %bb.0:
+; CHECK32-IZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; CHECK32-IZHINXMIN-NEXT:    ret
+;
+; CHECK64-IZHINXMIN-LABEL: fcvt_h_s:
+; CHECK64-IZHINXMIN:       # %bb.0:
+; CHECK64-IZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; CHECK64-IZHINXMIN-NEXT:    ret
+;
+; CHECK32-IZDINXZHINXMIN-LABEL: fcvt_h_s:
+; CHECK32-IZDINXZHINXMIN:       # %bb.0:
+; CHECK32-IZDINXZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; CHECK32-IZDINXZHINXMIN-NEXT:    ret
+;
+; CHECK64-IZDINXZHINXMIN-LABEL: fcvt_h_s:
+; CHECK64-IZDINXZHINXMIN:       # %bb.0:
+; CHECK64-IZDINXZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; CHECK64-IZDINXZHINXMIN-NEXT:    ret
   %1 = fptrunc float %a to half
   ret half %1
 }
 
 define float @fcvt_s_h(half %a) nounwind {
 ; CHECKIZFH-LABEL: fcvt_s_h:
 ; CHECKIZFH:       # %bb.0:
 ; CHECKIZFH-NEXT:    fcvt.s.h fa0, fa0
 ; CHECKIZFH-NEXT:    ret
 ;
 ; RV32IDZFH-LABEL: fcvt_s_h:
 ; RV32IDZFH:       # %bb.0:
 ; RV32IDZFH-NEXT:    fcvt.s.h fa0, fa0
 ; RV32IDZFH-NEXT:    ret
 ;
 ; RV64IDZFH-LABEL: fcvt_s_h:
 ; RV64IDZFH:       # %bb.0:
 ; RV64IDZFH-NEXT:    fcvt.s.h fa0, fa0
 ; RV64IDZFH-NEXT:    ret
 ;
+; CHECKIZHINX-LABEL: fcvt_s_h:
+; CHECKIZHINX:       # %bb.0:
+; CHECKIZHINX-NEXT:    fcvt.s.h a0, a0
+; CHECKIZHINX-NEXT:    ret
+;
+; CHECKIZDINXZHINX-LABEL: fcvt_s_h:
+; CHECKIZDINXZHINX:       # %bb.0:
+; CHECKIZDINXZHINX-NEXT:    fcvt.s.h a0, a0
+; CHECKIZDINXZHINX-NEXT:    ret
+;
 ; RV32I-LABEL: fcvt_s_h:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    slli a0, a0, 16
 ; RV32I-NEXT:    srli a0, a0, 16
 ; RV32I-NEXT:    call __extendhfsf2@plt
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload

 ; CHECK32-IZFHMIN:       # %bb.0:
 ; CHECK32-IZFHMIN-NEXT:    fcvt.s.h fa0, fa0
 ; CHECK32-IZFHMIN-NEXT:    ret
 ;
 ; CHECK64-IZFHMIN-LABEL: fcvt_s_h:
 ; CHECK64-IZFHMIN:       # %bb.0:
 ; CHECK64-IZFHMIN-NEXT:    fcvt.s.h fa0, fa0
 ; CHECK64-IZFHMIN-NEXT:    ret
+;
+; CHECK32-IZHINXMIN-LABEL: fcvt_s_h:
+; CHECK32-IZHINXMIN:       # %bb.0:
+; CHECK32-IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECK32-IZHINXMIN-NEXT:    ret
+;
+; CHECK64-IZHINXMIN-LABEL: fcvt_s_h:
+; CHECK64-IZHINXMIN:       # %bb.0:
+; CHECK64-IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECK64-IZHINXMIN-NEXT:    ret
+;
+; CHECK32-IZDINXZHINXMIN-LABEL: fcvt_s_h:
+; CHECK32-IZDINXZHINXMIN:       # %bb.0:
+; CHECK32-IZDINXZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECK32-IZDINXZHINXMIN-NEXT:    ret
+;
+; CHECK64-IZDINXZHINXMIN-LABEL: fcvt_s_h:
+; CHECK64-IZDINXZHINXMIN:       # %bb.0:
+; CHECK64-IZDINXZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECK64-IZDINXZHINXMIN-NEXT:    ret
   %1 = fpext half %a to float
   ret float %1
 }
 
 define half @fcvt_h_d(double %a) nounwind {
 ; RV32IZFH-LABEL: fcvt_h_d:
 ; RV32IZFH:       # %bb.0:
 ; RV32IZFH-NEXT:    addi sp, sp, -16

 ; RV32IDZFH-NEXT:    fcvt.h.d fa0, fa0
 ; RV32IDZFH-NEXT:    ret
 ;
 ; RV64IDZFH-LABEL: fcvt_h_d:
 ; RV64IDZFH:       # %bb.0:
 ; RV64IDZFH-NEXT:    fcvt.h.d fa0, fa0
 ; RV64IDZFH-NEXT:    ret
 ;
+; RV32IZHINX-LABEL: fcvt_h_d:
+; RV32IZHINX:       # %bb.0:
+; RV32IZHINX-NEXT:    addi sp, sp, -16
+; RV32IZHINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZHINX-NEXT:    call __truncdfhf2@plt
+; RV32IZHINX-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZHINX-NEXT:    addi sp, sp, 16
+; RV32IZHINX-NEXT:    ret
+;
+; RV64IZHINX-LABEL: fcvt_h_d:
+; RV64IZHINX:       # %bb.0:
+; RV64IZHINX-NEXT:    addi sp, sp, -16
+; RV64IZHINX-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IZHINX-NEXT:    call __truncdfhf2@plt
+; RV64IZHINX-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
+; RV64IZHINX-NEXT:    addi sp, sp, 16
+; RV64IZHINX-NEXT:    ret
+;
+; RV32IZDINXZHINX-LABEL: fcvt_h_d:
+; RV32IZDINXZHINX:       # %bb.0:
+; RV32IZDINXZHINX-NEXT:    addi sp, sp, -16
+; RV32IZDINXZHINX-NEXT:    sw a0, 8(sp)
+; RV32IZDINXZHINX-NEXT:    sw a1, 12(sp)
+; RV32IZDINXZHINX-NEXT:    lw a0, 8(sp)
+; RV32IZDINXZHINX-NEXT:    lw a1, 12(sp)
+; RV32IZDINXZHINX-NEXT:    fcvt.h.d a0, a0
+; RV32IZDINXZHINX-NEXT:    addi sp, sp, 16
+; RV32IZDINXZHINX-NEXT:    ret
+;
+; RV64IZDINXZHINX-LABEL: fcvt_h_d:
+; RV64IZDINXZHINX:       # %bb.0:
+; RV64IZDINXZHINX-NEXT:    fcvt.h.d a0, a0
+; RV64IZDINXZHINX-NEXT:    ret
+;
 ; RV32I-LABEL: fcvt_h_d:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    call __truncdfhf2@plt
 ; RV32I-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32I-NEXT:    addi sp, sp, 16
 ; RV32I-NEXT:    ret

 ; RV32IDZFHMIN:       # %bb.0:
 ; RV32IDZFHMIN-NEXT:    fcvt.h.d fa0, fa0
 ; RV32IDZFHMIN-NEXT:    ret
 ;
 ; RV64IDZFHMIN-LABEL: fcvt_h_d:
 ; RV64IDZFHMIN:       # %bb.0:
 ; RV64IDZFHMIN-NEXT:    fcvt.h.d fa0, fa0
 ; RV64IDZFHMIN-NEXT:    ret
+;
+; CHECK32-IZHINXMIN-LABEL: fcvt_h_d:
+; CHECK32-IZHINXMIN:       # %bb.0:
+; CHECK32-IZHINXMIN-NEXT:    addi sp, sp, -16
+; CHECK32-IZHINXMIN-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; CHECK32-IZHINXMIN-NEXT:    call __truncdfhf2@plt
+; CHECK32-IZHINXMIN-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; CHECK32-IZHINXMIN-NEXT:    addi sp, sp, 16
+; CHECK32-IZHINXMIN-NEXT:    ret
+;
+; CHECK64-IZHINXMIN-LABEL: fcvt_h_d:
+; CHECK64-IZHINXMIN:       # %bb.0:
+; CHECK64-IZHINXMIN-NEXT:    addi sp, sp, -16
+; CHECK64-IZHINXMIN-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; CHECK64-IZHINXMIN-NEXT:    call __truncdfhf2@plt
+; CHECK64-IZHINXMIN-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
+; CHECK64-IZHINXMIN-NEXT:    addi sp, sp, 16
+; CHECK64-IZHINXMIN-NEXT:    ret
+;
+; CHECK32-IZDINXZHINXMIN-LABEL: fcvt_h_d:
+; CHECK32-IZDINXZHINXMIN:       # %bb.0:
+; CHECK32-IZDINXZHINXMIN-NEXT:    addi sp, sp, -16
+; CHECK32-IZDINXZHINXMIN-NEXT:    sw a0, 8(sp)
+; CHECK32-IZDINXZHINXMIN-NEXT:    sw a1, 12(sp)
+; CHECK32-IZDINXZHINXMIN-NEXT:    lw a0, 8(sp)
+; CHECK32-IZDINXZHINXMIN-NEXT:    lw a1, 12(sp)
+; CHECK32-IZDINXZHINXMIN-NEXT:    fcvt.h.d a0, a0
+; CHECK32-IZDINXZHINXMIN-NEXT:    addi sp, sp, 16
+; CHECK32-IZDINXZHINXMIN-NEXT:    ret
+;
+; CHECK64-IZDINXZHINXMIN-LABEL: fcvt_h_d:
+; CHECK64-IZDINXZHINXMIN:       # %bb.0:
+; CHECK64-IZDINXZHINXMIN-NEXT:    fcvt.h.d a0, a0
+; CHECK64-IZDINXZHINXMIN-NEXT:    ret
   %1 = fptrunc double %a to half
   ret half %1
 }
 
 define double @fcvt_d_h(half %a) nounwind {
 ; RV32IZFH-LABEL: fcvt_d_h:
 ; RV32IZFH:       # %bb.0:
 ; RV32IZFH-NEXT:    addi sp, sp, -16

 ; RV32IDZFH-NEXT:    fcvt.d.h fa0, fa0
 ; RV32IDZFH-NEXT:    ret
 ;
 ; RV64IDZFH-LABEL: fcvt_d_h:
 ; RV64IDZFH:       # %bb.0:
 ; RV64IDZFH-NEXT:    fcvt.d.h fa0, fa0
 ; RV64IDZFH-NEXT:    ret
 ;
+; RV32IZHINX-LABEL: fcvt_d_h:
+; RV32IZHINX:       # %bb.0:
+; RV32IZHINX-NEXT:    addi sp, sp, -16
+; RV32IZHINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZHINX-NEXT:    fcvt.s.h a0, a0
+; RV32IZHINX-NEXT:    call __extendsfdf2@plt
+; RV32IZHINX-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZHINX-NEXT:    addi sp, sp, 16
+; RV32IZHINX-NEXT:    ret
+;
+; RV64IZHINX-LABEL: fcvt_d_h:
+; RV64IZHINX:       # %bb.0:
+; RV64IZHINX-NEXT:    addi sp, sp, -16
+; RV64IZHINX-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IZHINX-NEXT:    fcvt.s.h a0, a0
+; RV64IZHINX-NEXT:    call __extendsfdf2@plt
+; RV64IZHINX-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
+; RV64IZHINX-NEXT:    addi sp, sp, 16
+; RV64IZHINX-NEXT:    ret
+;
+; RV32IZDINXZHINX-LABEL: fcvt_d_h:
+; RV32IZDINXZHINX:       # %bb.0:
+; RV32IZDINXZHINX-NEXT:    addi sp, sp, -16
+; RV32IZDINXZHINX-NEXT:    fcvt.d.h a0, a0
+; RV32IZDINXZHINX-NEXT:    sw a0, 8(sp)
+; RV32IZDINXZHINX-NEXT:    sw a1, 12(sp)
+; RV32IZDINXZHINX-NEXT:    lw a0, 8(sp)
+; RV32IZDINXZHINX-NEXT:    lw a1, 12(sp)
+; RV32IZDINXZHINX-NEXT:    addi sp, sp, 16
+; RV32IZDINXZHINX-NEXT:    ret
+;
+; RV64IZDINXZHINX-LABEL: fcvt_d_h:
+; RV64IZDINXZHINX:       # %bb.0:
+; RV64IZDINXZHINX-NEXT:    fcvt.d.h a0, a0
+; RV64IZDINXZHINX-NEXT:    ret
+;
 ; RV32I-LABEL: fcvt_d_h:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    slli a0, a0, 16
 ; RV32I-NEXT:    srli a0, a0, 16
 ; RV32I-NEXT:    call __extendhfsf2@plt
 ; RV32I-NEXT:    call __extendsfdf2@plt

 ; RV32IDZFHMIN:       # %bb.0:
 ; RV32IDZFHMIN-NEXT:    fcvt.d.h fa0, fa0
 ; RV32IDZFHMIN-NEXT:    ret
 ;
 ; RV64IDZFHMIN-LABEL: fcvt_d_h:
 ; RV64IDZFHMIN:       # %bb.0:
 ; RV64IDZFHMIN-NEXT:    fcvt.d.h fa0, fa0
 ; RV64IDZFHMIN-NEXT:    ret
+;
+; CHECK32-IZHINXMIN-LABEL: fcvt_d_h:
+; CHECK32-IZHINXMIN:       # %bb.0:
+; CHECK32-IZHINXMIN-NEXT:    addi sp, sp, -16
+; CHECK32-IZHINXMIN-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; CHECK32-IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECK32-IZHINXMIN-NEXT:    call __extendsfdf2@plt
+; CHECK32-IZHINXMIN-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; CHECK32-IZHINXMIN-NEXT:    addi sp, sp, 16
+; CHECK32-IZHINXMIN-NEXT:    ret
+;
+; CHECK64-IZHINXMIN-LABEL: fcvt_d_h:
+; CHECK64-IZHINXMIN:       # %bb.0:
+; CHECK64-IZHINXMIN-NEXT:    addi sp, sp, -16
+; CHECK64-IZHINXMIN-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; CHECK64-IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECK64-IZHINXMIN-NEXT:    call __extendsfdf2@plt
+; CHECK64-IZHINXMIN-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
+; CHECK64-IZHINXMIN-NEXT:    addi sp, sp, 16
+; CHECK64-IZHINXMIN-NEXT:    ret
+;
+; CHECK32-IZDINXZHINXMIN-LABEL: fcvt_d_h:
+; CHECK32-IZDINXZHINXMIN:       # %bb.0:
+; CHECK32-IZDINXZHINXMIN-NEXT:    addi sp, sp, -16
+; CHECK32-IZDINXZHINXMIN-NEXT:    fcvt.d.h a0, a0
+; CHECK32-IZDINXZHINXMIN-NEXT:    sw a0, 8(sp)
+; CHECK32-IZDINXZHINXMIN-NEXT:    sw a1, 12(sp)
+; CHECK32-IZDINXZHINXMIN-NEXT:    lw a0, 8(sp)
+; CHECK32-IZDINXZHINXMIN-NEXT:    lw a1, 12(sp)
+; CHECK32-IZDINXZHINXMIN-NEXT:    addi sp, sp, 16
+; CHECK32-IZDINXZHINXMIN-NEXT:    ret
+;
+; CHECK64-IZDINXZHINXMIN-LABEL: fcvt_d_h:
+; CHECK64-IZDINXZHINXMIN:       # %bb.0:
+; CHECK64-IZDINXZHINXMIN-NEXT:    fcvt.d.h a0, a0
+; CHECK64-IZDINXZHINXMIN-NEXT:    ret
   %1 = fpext half %a to double
   ret double %1
 }
 
 define half @bitcast_h_i16(i16 %a) nounwind {
 ; CHECKIZFH-LABEL: bitcast_h_i16:
 ; CHECKIZFH:       # %bb.0:
 ; CHECKIZFH-NEXT:    fmv.h.x fa0, a0
 ; CHECKIZFH-NEXT:    ret
 ;
 ; RV32IDZFH-LABEL: bitcast_h_i16:
 ; RV32IDZFH:       # %bb.0:
 ; RV32IDZFH-NEXT:    fmv.h.x fa0, a0
 ; RV32IDZFH-NEXT:    ret
 ;
 ; RV64IDZFH-LABEL: bitcast_h_i16:
 ; RV64IDZFH:       # %bb.0:
 ; RV64IDZFH-NEXT:    fmv.h.x fa0, a0
 ; RV64IDZFH-NEXT:    ret
 ;
+; CHECKIZHINX-LABEL: bitcast_h_i16:
+; CHECKIZHINX:       # %bb.0:
+; CHECKIZHINX-NEXT:    ret
+;
+; CHECKIZDINXZHINX-LABEL: bitcast_h_i16:
+; CHECKIZDINXZHINX:       # %bb.0:
+; CHECKIZDINXZHINX-NEXT:    ret
+;
 ; RV32I-LABEL: bitcast_h_i16:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: bitcast_h_i16:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    ret
 ;
 ; CHECK32-IZFHMIN-LABEL: bitcast_h_i16:
 ; CHECK32-IZFHMIN:       # %bb.0:
 ; CHECK32-IZFHMIN-NEXT:    fmv.h.x fa0, a0
 ; CHECK32-IZFHMIN-NEXT:    ret
 ;
 ; CHECK64-IZFHMIN-LABEL: bitcast_h_i16:
 ; CHECK64-IZFHMIN:       # %bb.0:
 ; CHECK64-IZFHMIN-NEXT:    fmv.h.x fa0, a0
 ; CHECK64-IZFHMIN-NEXT:    ret
+;
+; CHECK32-IZHINXMIN-LABEL: bitcast_h_i16:
+; CHECK32-IZHINXMIN:       # %bb.0:
+; CHECK32-IZHINXMIN-NEXT:    ret
+;
+; CHECK64-IZHINXMIN-LABEL: bitcast_h_i16:
+; CHECK64-IZHINXMIN:       # %bb.0:
+; CHECK64-IZHINXMIN-NEXT:    ret
+;
+; CHECK32-IZDINXZHINXMIN-LABEL: bitcast_h_i16:
+; CHECK32-IZDINXZHINXMIN:       # %bb.0:
+; CHECK32-IZDINXZHINXMIN-NEXT:    ret
+;
+; CHECK64-IZDINXZHINXMIN-LABEL: bitcast_h_i16:
+; CHECK64-IZDINXZHINXMIN:       # %bb.0:
+; CHECK64-IZDINXZHINXMIN-NEXT:    ret
   %1 = bitcast i16 %a to half
   ret half %1
 }
 
 define i16 @bitcast_i16_h(half %a) nounwind {
 ; CHECKIZFH-LABEL: bitcast_i16_h:
 ; CHECKIZFH:       # %bb.0:
 ; CHECKIZFH-NEXT:    fmv.x.h a0, fa0
 ; CHECKIZFH-NEXT:    ret
 ;
 ; RV32IDZFH-LABEL: bitcast_i16_h:
 ; RV32IDZFH:       # %bb.0:
 ; RV32IDZFH-NEXT:    fmv.x.h a0, fa0
 ; RV32IDZFH-NEXT:    ret
 ;
 ; RV64IDZFH-LABEL: bitcast_i16_h:
 ; RV64IDZFH:       # %bb.0:
 ; RV64IDZFH-NEXT:    fmv.x.h a0, fa0
 ; RV64IDZFH-NEXT:    ret
 ;
+; CHECKIZHINX-LABEL: bitcast_i16_h:
+; CHECKIZHINX:       # %bb.0:
+; CHECKIZHINX-NEXT:    ret
+;
+; CHECKIZDINXZHINX-LABEL: bitcast_i16_h:
+; CHECKIZDINXZHINX:       # %bb.0:
+; CHECKIZDINXZHINX-NEXT:    ret
+;
 ; RV32I-LABEL: bitcast_i16_h:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: bitcast_i16_h:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    ret
 ;
 ; CHECK32-IZFHMIN-LABEL: bitcast_i16_h:
 ; CHECK32-IZFHMIN:       # %bb.0:
 ; CHECK32-IZFHMIN-NEXT:    fmv.x.h a0, fa0
 ; CHECK32-IZFHMIN-NEXT:    ret
 ;
 ; CHECK64-IZFHMIN-LABEL: bitcast_i16_h:
 ; CHECK64-IZFHMIN:       # %bb.0:
 ; CHECK64-IZFHMIN-NEXT:    fmv.x.h a0, fa0
 ; CHECK64-IZFHMIN-NEXT:    ret
+;
+; CHECK32-IZHINXMIN-LABEL: bitcast_i16_h:
+; CHECK32-IZHINXMIN:       # %bb.0:
+; CHECK32-IZHINXMIN-NEXT:    ret
+;
+; CHECK64-IZHINXMIN-LABEL: bitcast_i16_h:
+; CHECK64-IZHINXMIN:       # %bb.0:
+; CHECK64-IZHINXMIN-NEXT:    ret
+;
+; CHECK32-IZDINXZHINXMIN-LABEL: bitcast_i16_h:
+; CHECK32-IZDINXZHINXMIN:       # %bb.0:
+; CHECK32-IZDINXZHINXMIN-NEXT:    ret
+;
+; CHECK64-IZDINXZHINXMIN-LABEL: bitcast_i16_h:
+; CHECK64-IZDINXZHINXMIN:       # %bb.0:
+; CHECK64-IZDINXZHINXMIN-NEXT:    ret
   %1 = bitcast half %a to i16
   ret i16 %1
 }
 
 ; Make sure we select W version of addi on RV64.
 define signext i32 @fcvt_h_w_demanded_bits(i32 signext %0, ptr %1) nounwind {
 ; RV32IZFH-LABEL: fcvt_h_w_demanded_bits:
 ; RV32IZFH:       # %bb.0:

 ;
 ; RV64IDZFH-LABEL: fcvt_h_w_demanded_bits:
 ; RV64IDZFH:       # %bb.0:
 ; RV64IDZFH-NEXT:    addiw a0, a0, 1
 ; RV64IDZFH-NEXT:    fcvt.h.w fa5, a0
 ; RV64IDZFH-NEXT:    fsh fa5, 0(a1)
 ; RV64IDZFH-NEXT:    ret
 ;
+; RV32IZHINX-LABEL: fcvt_h_w_demanded_bits:
+; RV32IZHINX:       # %bb.0:
+; RV32IZHINX-NEXT:    addi a0, a0, 1
+; RV32IZHINX-NEXT:    fcvt.h.w a2, a0
+; RV32IZHINX-NEXT:    sh a2, 0(a1)
+; RV32IZHINX-NEXT:    ret
+;
+; RV64IZHINX-LABEL: fcvt_h_w_demanded_bits:
+; RV64IZHINX:       # %bb.0:
+; RV64IZHINX-NEXT:    addiw a2, a0, 1
+; RV64IZHINX-NEXT:    addi a0, a0, 1
+; RV64IZHINX-NEXT:    fcvt.h.w a0, a0
+; RV64IZHINX-NEXT:    sh a0, 0(a1)
+; RV64IZHINX-NEXT:    mv a0, a2
+; RV64IZHINX-NEXT:    ret
+;
+; RV32IZDINXZHINX-LABEL: fcvt_h_w_demanded_bits:
+; RV32IZDINXZHINX:       # %bb.0:
+; RV32IZDINXZHINX-NEXT:    addi a0, a0, 1
+; RV32IZDINXZHINX-NEXT:    fcvt.h.w a2, a0
+; RV32IZDINXZHINX-NEXT:    sh a2, 0(a1)
+; RV32IZDINXZHINX-NEXT:    ret
+;
+; RV64IZDINXZHINX-LABEL: fcvt_h_w_demanded_bits:
+; RV64IZDINXZHINX:       # %bb.0:
+; RV64IZDINXZHINX-NEXT:    addiw a2, a0, 1
+; RV64IZDINXZHINX-NEXT:    addi a0, a0, 1
+; RV64IZDINXZHINX-NEXT:    fcvt.h.w a0, a0
+; RV64IZDINXZHINX-NEXT:    sh a0, 0(a1)
+; RV64IZDINXZHINX-NEXT:    mv a0, a2
+; RV64IZDINXZHINX-NEXT:    ret
+;
 ; RV32I-LABEL: fcvt_h_w_demanded_bits:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    mv s0, a1
 ; RV32I-NEXT:    addi s1, a0, 1

 ;
 ; CHECK64-IZFHMIN-LABEL: fcvt_h_w_demanded_bits:
 ; CHECK64-IZFHMIN:       # %bb.0:
 ; CHECK64-IZFHMIN-NEXT:    addiw a0, a0, 1
 ; CHECK64-IZFHMIN-NEXT:    fcvt.s.l fa5, a0
 ; CHECK64-IZFHMIN-NEXT:    fcvt.h.s fa5, fa5
 ; CHECK64-IZFHMIN-NEXT:    fsh fa5, 0(a1)
 ; CHECK64-IZFHMIN-NEXT:    ret
+;
+; CHECK32-IZHINXMIN-LABEL: fcvt_h_w_demanded_bits:
+; CHECK32-IZHINXMIN:       # %bb.0:
+; CHECK32-IZHINXMIN-NEXT:    addi a0, a0, 1
+; CHECK32-IZHINXMIN-NEXT:    fcvt.s.w a2, a0
+; CHECK32-IZHINXMIN-NEXT:    fcvt.h.s a2, a2
+; CHECK32-IZHINXMIN-NEXT:    sh a2, 0(a1)
+; CHECK32-IZHINXMIN-NEXT:    ret
+;
+; CHECK64-IZHINXMIN-LABEL: fcvt_h_w_demanded_bits:
+; CHECK64-IZHINXMIN:       # %bb.0:
+; CHECK64-IZHINXMIN-NEXT:    addiw a0, a0, 1
+; CHECK64-IZHINXMIN-NEXT:    fcvt.s.l a2, a0
+; CHECK64-IZHINXMIN-NEXT:    fcvt.h.s a2, a2
+; CHECK64-IZHINXMIN-NEXT:    sh a2, 0(a1)
+; CHECK64-IZHINXMIN-NEXT:    ret
+;
+; CHECK32-IZDINXZHINXMIN-LABEL: fcvt_h_w_demanded_bits:
+; CHECK32-IZDINXZHINXMIN:       # %bb.0:
+; CHECK32-IZDINXZHINXMIN-NEXT:    addi a0, a0, 1
+; CHECK32-IZDINXZHINXMIN-NEXT:    fcvt.s.w a2, a0
+; CHECK32-IZDINXZHINXMIN-NEXT:    fcvt.h.s a2, a2
+; CHECK32-IZDINXZHINXMIN-NEXT:    sh a2, 0(a1)
+; CHECK32-IZDINXZHINXMIN-NEXT:    ret
+;
+; CHECK64-IZDINXZHINXMIN-LABEL: fcvt_h_w_demanded_bits:
+; CHECK64-IZDINXZHINXMIN:       # %bb.0:
+; CHECK64-IZDINXZHINXMIN-NEXT:    addiw a0, a0, 1
+; CHECK64-IZDINXZHINXMIN-NEXT:    fcvt.s.l a2, a0
+; CHECK64-IZDINXZHINXMIN-NEXT:    fcvt.h.s a2, a2
+; CHECK64-IZDINXZHINXMIN-NEXT:    sh a2, 0(a1)
+; CHECK64-IZDINXZHINXMIN-NEXT:    ret
   %3 = add i32 %0, 1
   %4 = sitofp i32 %3 to half
   store half %4, ptr %1, align 2
   ret i32 %3
 }
 
 ; Make sure we select W version of addi on RV64.
 define signext i32 @fcvt_h_wu_demanded_bits(i32 signext %0, ptr %1) nounwind {

 ;
 ; RV64IDZFH-LABEL: fcvt_h_wu_demanded_bits:
 ; RV64IDZFH:       # %bb.0:
 ; RV64IDZFH-NEXT:    addiw a0, a0, 1
 ; RV64IDZFH-NEXT:    fcvt.h.wu fa5, a0
 ; RV64IDZFH-NEXT:    fsh fa5, 0(a1)
 ; RV64IDZFH-NEXT:    ret
 ;
+; RV32IZHINX-LABEL: fcvt_h_wu_demanded_bits:
+; RV32IZHINX:       # %bb.0:
+; RV32IZHINX-NEXT:    addi a0, a0, 1
+; RV32IZHINX-NEXT:    fcvt.h.wu a2, a0
+; RV32IZHINX-NEXT:    sh a2, 0(a1)
+; RV32IZHINX-NEXT:    ret
+;
+; RV64IZHINX-LABEL: fcvt_h_wu_demanded_bits:
+; RV64IZHINX:       # %bb.0:
+; RV64IZHINX-NEXT:    addiw a0, a0, 1
+; RV64IZHINX-NEXT:    fcvt.h.wu a2, a0
+; RV64IZHINX-NEXT:    sh a2, 0(a1)
+; RV64IZHINX-NEXT:    ret
+;
+; RV32IZDINXZHINX-LABEL: fcvt_h_wu_demanded_bits:
+; RV32IZDINXZHINX:       # %bb.0:
+; RV32IZDINXZHINX-NEXT:    addi a0, a0, 1
+; RV32IZDINXZHINX-NEXT:    fcvt.h.wu a2, a0
+; RV32IZDINXZHINX-NEXT:    sh a2, 0(a1)
+; RV32IZDINXZHINX-NEXT:    ret
+;
+; RV64IZDINXZHINX-LABEL: fcvt_h_wu_demanded_bits:
+; RV64IZDINXZHINX:       # %bb.0:
+; RV64IZDINXZHINX-NEXT:    addiw a0, a0, 1
+; RV64IZDINXZHINX-NEXT:    fcvt.h.wu a2, a0
+; RV64IZDINXZHINX-NEXT:    sh a2, 0(a1)
+; RV64IZDINXZHINX-NEXT:    ret
+;
 ; RV32I-LABEL: fcvt_h_wu_demanded_bits:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    mv s0, a1
 ; RV32I-NEXT:    addi s1, a0, 1

 ; CHECK64-IZFHMIN:       # %bb.0:
 ; CHECK64-IZFHMIN-NEXT:    addiw a0, a0, 1
 ; CHECK64-IZFHMIN-NEXT:    slli a2, a0, 32
 ; CHECK64-IZFHMIN-NEXT:    srli a2, a2, 32
 ; CHECK64-IZFHMIN-NEXT:    fcvt.s.lu fa5, a2
 ; CHECK64-IZFHMIN-NEXT:    fcvt.h.s fa5, fa5
 ; CHECK64-IZFHMIN-NEXT:    fsh fa5, 0(a1)
 ; CHECK64-IZFHMIN-NEXT:    ret
+;
+; CHECK32-IZHINXMIN-LABEL: fcvt_h_wu_demanded_bits:
+; CHECK32-IZHINXMIN:       # %bb.0:
+; CHECK32-IZHINXMIN-NEXT:    addi a0, a0, 1
+; CHECK32-IZHINXMIN-NEXT:    fcvt.s.wu a2, a0
+; CHECK32-IZHINXMIN-NEXT:    fcvt.h.s a2, a2
+; CHECK32-IZHINXMIN-NEXT:    sh a2, 0(a1)
+; CHECK32-IZHINXMIN-NEXT:    ret
+;
+; CHECK64-IZHINXMIN-LABEL: fcvt_h_wu_demanded_bits:
+; CHECK64-IZHINXMIN:       # %bb.0:
+; CHECK64-IZHINXMIN-NEXT:    addiw a0, a0, 1
+; CHECK64-IZHINXMIN-NEXT:    slli a2, a0, 32
+; CHECK64-IZHINXMIN-NEXT:    srli a2, a2, 32
+; CHECK64-IZHINXMIN-NEXT:    fcvt.s.lu a2, a2
+; CHECK64-IZHINXMIN-NEXT:    fcvt.h.s a2, a2
+; CHECK64-IZHINXMIN-NEXT:    sh a2, 0(a1)
+; CHECK64-IZHINXMIN-NEXT:    ret
+;
+; CHECK32-IZDINXZHINXMIN-LABEL: fcvt_h_wu_demanded_bits:
+; CHECK32-IZDINXZHINXMIN:       # %bb.0:
+; CHECK32-IZDINXZHINXMIN-NEXT:    addi a0, a0, 1
+; CHECK32-IZDINXZHINXMIN-NEXT:    fcvt.s.wu a2, a0
+; CHECK32-IZDINXZHINXMIN-NEXT:    fcvt.h.s a2, a2
+; CHECK32-IZDINXZHINXMIN-NEXT:    sh a2, 0(a1)
+; CHECK32-IZDINXZHINXMIN-NEXT:    ret
+;
+; CHECK64-IZDINXZHINXMIN-LABEL: fcvt_h_wu_demanded_bits:
+; CHECK64-IZDINXZHINXMIN:       # %bb.0:
+; CHECK64-IZDINXZHINXMIN-NEXT:    addiw a0, a0, 1
+; CHECK64-IZDINXZHINXMIN-NEXT:    slli a2, a0, 32
+; CHECK64-IZDINXZHINXMIN-NEXT:    srli a2, a2, 32
+; CHECK64-IZDINXZHINXMIN-NEXT:    fcvt.s.lu a2, a2
+; CHECK64-IZDINXZHINXMIN-NEXT:    fcvt.h.s a2, a2
+; CHECK64-IZDINXZHINXMIN-NEXT:    sh a2, 0(a1)
+; CHECK64-IZDINXZHINXMIN-NEXT:    ret
   %3 = add i32 %0, 1
   %4 = uitofp i32 %3 to half
   store half %4, ptr %1, align 2
   ret i32 %3
 }
 
 define signext i16 @fcvt_w_s_i16(half %a) nounwind {
 ; RV32IZFH-LABEL: fcvt_w_s_i16:

 ; RV32IDZFH-NEXT:    fcvt.w.h a0, fa0, rtz
 ; RV32IDZFH-NEXT:    ret
 ;
 ; RV64IDZFH-LABEL: fcvt_w_s_i16:
 ; RV64IDZFH:       # %bb.0:
 ; RV64IDZFH-NEXT:    fcvt.l.h a0, fa0, rtz
 ; RV64IDZFH-NEXT:    ret
 ;
+; RV32IZHINX-LABEL: fcvt_w_s_i16:
+; RV32IZHINX:       # %bb.0:
+; RV32IZHINX-NEXT:    fcvt.w.h a0, a0, rtz
+; RV32IZHINX-NEXT:    ret
+;
+; RV64IZHINX-LABEL: fcvt_w_s_i16:
+; RV64IZHINX:       # %bb.0:
+; RV64IZHINX-NEXT:    fcvt.l.h a0, a0, rtz
+; RV64IZHINX-NEXT:    ret
+;
+; RV32IZDINXZHINX-LABEL: fcvt_w_s_i16:
+; RV32IZDINXZHINX:       # %bb.0:
+; RV32IZDINXZHINX-NEXT:    fcvt.w.h a0, a0, rtz
+; RV32IZDINXZHINX-NEXT:    ret
+;
+; RV64IZDINXZHINX-LABEL: fcvt_w_s_i16:
+; RV64IZDINXZHINX:       # %bb.0:
+; RV64IZDINXZHINX-NEXT:    fcvt.l.h a0, a0, rtz
+; RV64IZDINXZHINX-NEXT:    ret
+;
 ; RV32I-LABEL: fcvt_w_s_i16:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    slli a0, a0, 16
 ; RV32I-NEXT:    srli a0, a0, 16
 ; RV32I-NEXT:    call __extendhfsf2@plt
 ; RV32I-NEXT:    call __fixsfsi@plt

 ; CHECK32-IZFHMIN-NEXT:    fcvt.w.s a0, fa5, rtz
 ; CHECK32-IZFHMIN-NEXT:    ret
 ;
 ; CHECK64-IZFHMIN-LABEL: fcvt_w_s_i16:
 ; CHECK64-IZFHMIN:       # %bb.0:
 ; CHECK64-IZFHMIN-NEXT:    fcvt.s.h fa5, fa0
 ; CHECK64-IZFHMIN-NEXT:    fcvt.l.s a0, fa5, rtz
 ; CHECK64-IZFHMIN-NEXT:    ret
+;
+; CHECK32-IZHINXMIN-LABEL: fcvt_w_s_i16:
+; CHECK32-IZHINXMIN:       # %bb.0:
+; CHECK32-IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECK32-IZHINXMIN-NEXT:    fcvt.w.s a0, a0, rtz
+; CHECK32-IZHINXMIN-NEXT:    ret
+;
+; CHECK64-IZHINXMIN-LABEL: fcvt_w_s_i16:
+; CHECK64-IZHINXMIN:       # %bb.0:
+; CHECK64-IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECK64-IZHINXMIN-NEXT:    fcvt.l.s a0, a0, rtz
+; CHECK64-IZHINXMIN-NEXT:    ret
+;
+; CHECK32-IZDINXZHINXMIN-LABEL: fcvt_w_s_i16:
+; CHECK32-IZDINXZHINXMIN:       # %bb.0:
+; CHECK32-IZDINXZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECK32-IZDINXZHINXMIN-NEXT:    fcvt.w.s a0, a0, rtz
+; CHECK32-IZDINXZHINXMIN-NEXT:    ret
+;
+; CHECK64-IZDINXZHINXMIN-LABEL: fcvt_w_s_i16:
+; CHECK64-IZDINXZHINXMIN:       # %bb.0:
+; CHECK64-IZDINXZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECK64-IZDINXZHINXMIN-NEXT:    fcvt.l.s a0, a0, rtz
+; CHECK64-IZDINXZHINXMIN-NEXT:    ret
   %1 = fptosi half %a to i16
   ret i16 %1
 }
 
 define signext i16 @fcvt_w_s_sat_i16(half %a) nounwind {
 ; RV32IZFH-LABEL: fcvt_w_s_sat_i16:
 ; RV32IZFH:       # %bb.0: # %start
 ; RV32IZFH-NEXT:    fcvt.s.h fa5, fa0

 ; RV64IDZFH-NEXT:    fmv.w.x fa3, a1
 ; RV64IDZFH-NEXT:    fmax.s fa5, fa5, fa3
 ; RV64IDZFH-NEXT:    neg a0, a0
 ; RV64IDZFH-NEXT:    fmin.s fa5, fa5, fa4
 ; RV64IDZFH-NEXT:    fcvt.l.s a1, fa5, rtz
 ; RV64IDZFH-NEXT:    and a0, a0, a1
 ; RV64IDZFH-NEXT:    ret
 ;
+; RV32IZHINX-LABEL: fcvt_w_s_sat_i16:
+; RV32IZHINX:       # %bb.0: # %start
+; RV32IZHINX-NEXT:    fcvt.s.h a0, a0
+; RV32IZHINX-NEXT:    feq.s a1, a0, a0
+; RV32IZHINX-NEXT:    lui a2, %hi(.LCPI32_0)
+; RV32IZHINX-NEXT:    lw a2, %lo(.LCPI32_0)(a2)
+; RV32IZHINX-NEXT:    neg a1, a1
+; RV32IZHINX-NEXT:    lui a3, 815104
+; RV32IZHINX-NEXT:    fmax.s a0, a0, a3
+; RV32IZHINX-NEXT:    fmin.s a0, a0, a2
+; RV32IZHINX-NEXT:    fcvt.w.s a0, a0, rtz
+; RV32IZHINX-NEXT:    and a0, a1, a0
+; RV32IZHINX-NEXT:    ret
+;
+; RV64IZHINX-LABEL: fcvt_w_s_sat_i16:
+; RV64IZHINX:       # %bb.0: # %start
+; RV64IZHINX-NEXT:    fcvt.s.h a0, a0
+; RV64IZHINX-NEXT:    lui a1, 815104
+; RV64IZHINX-NEXT:    lui a2, %hi(.LCPI32_0)
+; RV64IZHINX-NEXT:    lw a2, %lo(.LCPI32_0)(a2)
+; RV64IZHINX-NEXT:    fmax.s a1, a0, a1
+; RV64IZHINX-NEXT:    feq.s a0, a0, a0
+; RV64IZHINX-NEXT:    neg a0, a0
+; RV64IZHINX-NEXT:    fmin.s a1, a1, a2
+; RV64IZHINX-NEXT:    fcvt.l.s a1, a1, rtz
+; RV64IZHINX-NEXT:    and a0, a0, a1
+; RV64IZHINX-NEXT:    ret
+;
+; RV32IZDINXZHINX-LABEL: fcvt_w_s_sat_i16:
+; RV32IZDINXZHINX:       # %bb.0: # %start
+; RV32IZDINXZHINX-NEXT:    fcvt.s.h a0, a0
+; RV32IZDINXZHINX-NEXT:    feq.s a1, a0, a0
+; RV32IZDINXZHINX-NEXT:    lui a2, %hi(.LCPI32_0)
+; RV32IZDINXZHINX-NEXT:    lw a2, %lo(.LCPI32_0)(a2)
+; RV32IZDINXZHINX-NEXT:    neg a1, a1
+; RV32IZDINXZHINX-NEXT:    lui a3, 815104
+; RV32IZDINXZHINX-NEXT:    fmax.s a0, a0, a3
+; RV32IZDINXZHINX-NEXT:    fmin.s a0, a0, a2
+; RV32IZDINXZHINX-NEXT:    fcvt.w.s a0, a0, rtz
+; RV32IZDINXZHINX-NEXT:    and a0, a1, a0
+; RV32IZDINXZHINX-NEXT:    ret
+;
+; RV64IZDINXZHINX-LABEL: fcvt_w_s_sat_i16:
+; RV64IZDINXZHINX:       # %bb.0: # %start
+; RV64IZDINXZHINX-NEXT:    fcvt.s.h a0, a0
+; RV64IZDINXZHINX-NEXT:    lui a1, 815104
+; RV64IZDINXZHINX-NEXT:    lui a2, %hi(.LCPI32_0)
+; RV64IZDINXZHINX-NEXT:    lw a2, %lo(.LCPI32_0)(a2)
+; RV64IZDINXZHINX-NEXT:    fmax.s a1, a0, a1
+; RV64IZDINXZHINX-NEXT:    feq.s a0, a0, a0
+; RV64IZDINXZHINX-NEXT:    neg a0, a0
+; RV64IZDINXZHINX-NEXT:    fmin.s a1, a1, a2
+; RV64IZDINXZHINX-NEXT:    fcvt.l.s a1, a1, rtz
+; RV64IZDINXZHINX-NEXT:    and a0, a0, a1
+; RV64IZDINXZHINX-NEXT:    ret
+;
 ; RV32I-LABEL: fcvt_w_s_sat_i16:
 ; RV32I:       # %bb.0: # %start
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s2, 0(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    slli a0, a0, 16

 ; CHECK64-IZFHMIN-NEXT:    lui a1, 815104
 ; CHECK64-IZFHMIN-NEXT:    fmv.w.x fa3, a1
 ; CHECK64-IZFHMIN-NEXT:    fmax.s fa5, fa5, fa3
 ; CHECK64-IZFHMIN-NEXT:    neg a0, a0
 ; CHECK64-IZFHMIN-NEXT:    fmin.s fa5, fa5, fa4
 ; CHECK64-IZFHMIN-NEXT:    fcvt.l.s a1, fa5, rtz
 ; CHECK64-IZFHMIN-NEXT:    and a0, a0, a1
 ; CHECK64-IZFHMIN-NEXT:    ret
+;
+; CHECK32-IZHINXMIN-LABEL: fcvt_w_s_sat_i16:
+; CHECK32-IZHINXMIN:       # %bb.0: # %start
+; CHECK32-IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECK32-IZHINXMIN-NEXT:    feq.s a1, a0, a0
+; CHECK32-IZHINXMIN-NEXT:    lui a2, %hi(.LCPI32_0)
+; CHECK32-IZHINXMIN-NEXT:    lw a2, %lo(.LCPI32_0)(a2)
+; CHECK32-IZHINXMIN-NEXT:    neg a1, a1
+; CHECK32-IZHINXMIN-NEXT:    lui a3, 815104
+; CHECK32-IZHINXMIN-NEXT:    fmax.s a0, a0, a3
+; CHECK32-IZHINXMIN-NEXT:    fmin.s a0, a0, a2
+; CHECK32-IZHINXMIN-NEXT:    fcvt.w.s a0, a0, rtz
+; CHECK32-IZHINXMIN-NEXT:    and a0, a1, a0
+; CHECK32-IZHINXMIN-NEXT:    ret
+;
+; CHECK64-IZHINXMIN-LABEL: fcvt_w_s_sat_i16:
+; CHECK64-IZHINXMIN:       # %bb.0: # %start
+; CHECK64-IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECK64-IZHINXMIN-NEXT:    lui a1, 815104
+; CHECK64-IZHINXMIN-NEXT:    lui a2, %hi(.LCPI32_0)
+; CHECK64-IZHINXMIN-NEXT:    lw a2, %lo(.LCPI32_0)(a2)
+; CHECK64-IZHINXMIN-NEXT:    fmax.s a1, a0, a1
+; CHECK64-IZHINXMIN-NEXT:    feq.s a0, a0, a0
+; CHECK64-IZHINXMIN-NEXT:    neg a0, a0
+; CHECK64-IZHINXMIN-NEXT:    fmin.s a1, a1, a2
+; CHECK64-IZHINXMIN-NEXT:    fcvt.l.s a1, a1, rtz
+; CHECK64-IZHINXMIN-NEXT:    and a0, a0, a1
+; CHECK64-IZHINXMIN-NEXT:    ret
+;
+; CHECK32-IZDINXZHINXMIN-LABEL: fcvt_w_s_sat_i16:
+; CHECK32-IZDINXZHINXMIN:       # %bb.0: # %start
+; CHECK32-IZDINXZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECK32-IZDINXZHINXMIN-NEXT:    feq.s a1, a0, a0
+; CHECK32-IZDINXZHINXMIN-NEXT:    lui a2, %hi(.LCPI32_0)
+; CHECK32-IZDINXZHINXMIN-NEXT:    lw a2, %lo(.LCPI32_0)(a2)
+; CHECK32-IZDINXZHINXMIN-NEXT:    neg a1, a1
+; CHECK32-IZDINXZHINXMIN-NEXT:    lui a3, 815104
+; CHECK32-IZDINXZHINXMIN-NEXT:    fmax.s a0, a0, a3
+; CHECK32-IZDINXZHINXMIN-NEXT:    fmin.s a0, a0, a2
+; CHECK32-IZDINXZHINXMIN-NEXT:    fcvt.w.s a0, a0, rtz
+; CHECK32-IZDINXZHINXMIN-NEXT:    and a0, a1, a0
+; CHECK32-IZDINXZHINXMIN-NEXT:    ret
+;
+; CHECK64-IZDINXZHINXMIN-LABEL: fcvt_w_s_sat_i16:
+; CHECK64-IZDINXZHINXMIN:       # %bb.0: # %start
+; CHECK64-IZDINXZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECK64-IZDINXZHINXMIN-NEXT:    lui a1, 815104
+; CHECK64-IZDINXZHINXMIN-NEXT:    lui a2, %hi(.LCPI32_0)
+; CHECK64-IZDINXZHINXMIN-NEXT:    lw a2, %lo(.LCPI32_0)(a2)
+; CHECK64-IZDINXZHINXMIN-NEXT:    fmax.s a1, a0, a1
+; CHECK64-IZDINXZHINXMIN-NEXT:    feq.s a0, a0, a0
+; CHECK64-IZDINXZHINXMIN-NEXT:    neg a0, a0
+; CHECK64-IZDINXZHINXMIN-NEXT:    fmin.s a1, a1, a2
+; CHECK64-IZDINXZHINXMIN-NEXT:    fcvt.l.s a1, a1, rtz
+; CHECK64-IZDINXZHINXMIN-NEXT:    and a0, a0, a1
+; CHECK64-IZDINXZHINXMIN-NEXT:    ret
 start:
   %0 = tail call i16 @llvm.fptosi.sat.i16.f16(half %a)
   ret i16 %0
 }
 
 define zeroext i16 @fcvt_wu_s_i16(half %a) nounwind {
 ; RV32IZFH-LABEL: fcvt_wu_s_i16:
 ; RV32IZFH:       # %bb.0:

 ; RV32IDZFH-NEXT:    fcvt.wu.h a0, fa0, rtz
 ; RV32IDZFH-NEXT:    ret
 ;
 ; RV64IDZFH-LABEL: fcvt_wu_s_i16:
 ; RV64IDZFH:       # %bb.0:
 ; RV64IDZFH-NEXT:    fcvt.lu.h a0, fa0, rtz
 ; RV64IDZFH-NEXT:    ret
 ;
+; RV32IZHINX-LABEL: fcvt_wu_s_i16:
+; RV32IZHINX:       # %bb.0:
+; RV32IZHINX-NEXT:    fcvt.wu.h a0, a0, rtz
+; RV32IZHINX-NEXT:    ret
+;
+; RV64IZHINX-LABEL: fcvt_wu_s_i16:
+; RV64IZHINX:       # %bb.0:
+; RV64IZHINX-NEXT:    fcvt.lu.h a0, a0, rtz
+; RV64IZHINX-NEXT:    ret
+;
+; RV32IZDINXZHINX-LABEL: fcvt_wu_s_i16:
+; RV32IZDINXZHINX:       # %bb.0:
+; RV32IZDINXZHINX-NEXT:    fcvt.wu.h a0, a0, rtz
+; RV32IZDINXZHINX-NEXT:    ret
+;
+; RV64IZDINXZHINX-LABEL: fcvt_wu_s_i16:
+; RV64IZDINXZHINX:       # %bb.0:
+; RV64IZDINXZHINX-NEXT:    fcvt.lu.h a0, a0, rtz
+; RV64IZDINXZHINX-NEXT:    ret
+;
 ; RV32I-LABEL: fcvt_wu_s_i16:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    slli a0, a0, 16
 ; RV32I-NEXT:    srli a0, a0, 16
 ; RV32I-NEXT:    call __extendhfsf2@plt
 ; RV32I-NEXT:    call __fixunssfsi@plt

 ; CHECK32-IZFHMIN-NEXT:    fcvt.wu.s a0, fa5, rtz
 ; CHECK32-IZFHMIN-NEXT:    ret
 ;
 ; CHECK64-IZFHMIN-LABEL: fcvt_wu_s_i16:
 ; CHECK64-IZFHMIN:       # %bb.0:
 ; CHECK64-IZFHMIN-NEXT:    fcvt.s.h fa5, fa0
 ; CHECK64-IZFHMIN-NEXT:    fcvt.lu.s a0, fa5, rtz
 ; CHECK64-IZFHMIN-NEXT:    ret
+;
+; CHECK32-IZHINXMIN-LABEL: fcvt_wu_s_i16:
+; CHECK32-IZHINXMIN:       # %bb.0:
+; CHECK32-IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECK32-IZHINXMIN-NEXT:    fcvt.wu.s a0, a0, rtz
+; CHECK32-IZHINXMIN-NEXT:    ret
+;
+; CHECK64-IZHINXMIN-LABEL: fcvt_wu_s_i16:
+; CHECK64-IZHINXMIN:       # %bb.0:
+; CHECK64-IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECK64-IZHINXMIN-NEXT:    fcvt.lu.s a0, a0, rtz
+; CHECK64-IZHINXMIN-NEXT:    ret
+;
+; CHECK32-IZDINXZHINXMIN-LABEL: fcvt_wu_s_i16:
+; CHECK32-IZDINXZHINXMIN:       # %bb.0:
+; CHECK32-IZDINXZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECK32-IZDINXZHINXMIN-NEXT:    fcvt.wu.s a0, a0, rtz
+; CHECK32-IZDINXZHINXMIN-NEXT:    ret
+;
+; CHECK64-IZDINXZHINXMIN-LABEL: fcvt_wu_s_i16:
+; CHECK64-IZDINXZHINXMIN:       # %bb.0:
+; CHECK64-IZDINXZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECK64-IZDINXZHINXMIN-NEXT:    fcvt.lu.s a0, a0, rtz
+; CHECK64-IZDINXZHINXMIN-NEXT:    ret
   %1 = fptoui half %a to i16
   ret i16 %1
 }
 
 define zeroext i16 @fcvt_wu_s_sat_i16(half %a) nounwind {
 ; RV32IZFH-LABEL: fcvt_wu_s_sat_i16:
 ; RV32IZFH:       # %bb.0: # %start
 ; RV32IZFH-NEXT:    lui a0, %hi(.LCPI34_0)

 ; RV64IDZFH-NEXT:    flw fa5, %lo(.LCPI34_0)(a0)
 ; RV64IDZFH-NEXT:    fcvt.s.h fa4, fa0
 ; RV64IDZFH-NEXT:    fmv.w.x fa3, zero
 ; RV64IDZFH-NEXT:    fmax.s fa4, fa4, fa3
 ; RV64IDZFH-NEXT:    fmin.s fa5, fa4, fa5
 ; RV64IDZFH-NEXT:    fcvt.lu.s a0, fa5, rtz
 ; RV64IDZFH-NEXT:    ret
 ;
+; RV32IZHINX-LABEL: fcvt_wu_s_sat_i16:
+; RV32IZHINX:       # %bb.0: # %start
+; RV32IZHINX-NEXT:    lui a1, %hi(.LCPI34_0)
+; RV32IZHINX-NEXT:    lw a1, %lo(.LCPI34_0)(a1)
+; RV32IZHINX-NEXT:    fcvt.s.h a0, a0
+; RV32IZHINX-NEXT:    fmax.s a0, a0, zero
+; RV32IZHINX-NEXT:    fmin.s a0, a0, a1
+; RV32IZHINX-NEXT:    fcvt.wu.s a0, a0, rtz
+; RV32IZHINX-NEXT:    ret
+;
+; RV64IZHINX-LABEL: fcvt_wu_s_sat_i16:
+; RV64IZHINX:       # %bb.0: # %start
+; RV64IZHINX-NEXT:    lui a1, %hi(.LCPI34_0)
+; RV64IZHINX-NEXT:    lw a1, %lo(.LCPI34_0)(a1)
+; RV64IZHINX-NEXT:    fcvt.s.h a0, a0
+; RV64IZHINX-NEXT:    fmax.s a0, a0, zero
+; RV64IZHINX-NEXT:    fmin.s a0, a0, a1
+; RV64IZHINX-NEXT:    fcvt.lu.s a0, a0, rtz
+; RV64IZHINX-NEXT:    ret
+;
+; RV32IZDINXZHINX-LABEL: fcvt_wu_s_sat_i16:
+; RV32IZDINXZHINX:       # %bb.0: # %start
+; RV32IZDINXZHINX-NEXT:    lui a1, %hi(.LCPI34_0)
+; RV32IZDINXZHINX-NEXT:    lw a1, %lo(.LCPI34_0)(a1)
+; RV32IZDINXZHINX-NEXT:    fcvt.s.h a0, a0
+; RV32IZDINXZHINX-NEXT:    fmax.s a0, a0, zero
+; RV32IZDINXZHINX-NEXT:    fmin.s a0, a0, a1
+; RV32IZDINXZHINX-NEXT:    fcvt.wu.s a0, a0, rtz
+; RV32IZDINXZHINX-NEXT:    ret
+;
+; RV64IZDINXZHINX-LABEL: fcvt_wu_s_sat_i16:
+; RV64IZDINXZHINX:       # %bb.0: # %start
+; RV64IZDINXZHINX-NEXT:    lui a1, %hi(.LCPI34_0)
+; RV64IZDINXZHINX-NEXT:    lw a1, %lo(.LCPI34_0)(a1)
+; RV64IZDINXZHINX-NEXT:    fcvt.s.h a0, a0
+; RV64IZDINXZHINX-NEXT:    fmax.s a0, a0, zero
+; RV64IZDINXZHINX-NEXT:    fmin.s a0, a0, a1
+; RV64IZDINXZHINX-NEXT:    fcvt.lu.s a0, a0, rtz
+; RV64IZDINXZHINX-NEXT:    ret
+;
 ; RV32I-LABEL: fcvt_wu_s_sat_i16:
 ; RV32I:       # %bb.0: # %start
 ; RV32I-NEXT:    addi sp, sp, -32
 ; RV32I-NEXT:    sw ra, 28(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s0, 24(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s1, 20(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s2, 16(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s3, 12(sp) # 4-byte Folded Spill

 ; CHECK64-IZFHMIN-NEXT:    lui a0, %hi(.LCPI34_0)
 ; CHECK64-IZFHMIN-NEXT:    flw fa5, %lo(.LCPI34_0)(a0)
 ; CHECK64-IZFHMIN-NEXT:    fcvt.s.h fa4, fa0
 ; CHECK64-IZFHMIN-NEXT:    fmv.w.x fa3, zero
 ; CHECK64-IZFHMIN-NEXT:    fmax.s fa4, fa4, fa3
 ; CHECK64-IZFHMIN-NEXT:    fmin.s fa5, fa4, fa5
 ; CHECK64-IZFHMIN-NEXT:    fcvt.lu.s a0, fa5, rtz
 ; CHECK64-IZFHMIN-NEXT:    ret
+;
+; CHECK32-IZHINXMIN-LABEL: fcvt_wu_s_sat_i16:
+; CHECK32-IZHINXMIN:       # %bb.0: # %start
+; CHECK32-IZHINXMIN-NEXT:    lui a1, %hi(.LCPI34_0)
+; CHECK32-IZHINXMIN-NEXT:    lw a1, %lo(.LCPI34_0)(a1)
+; CHECK32-IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECK32-IZHINXMIN-NEXT:    fmax.s a0, a0, zero
+; CHECK32-IZHINXMIN-NEXT:    fmin.s a0, a0, a1
+; CHECK32-IZHINXMIN-NEXT:    fcvt.wu.s a0, a0, rtz
+; CHECK32-IZHINXMIN-NEXT:    ret
+;
+; CHECK64-IZHINXMIN-LABEL: fcvt_wu_s_sat_i16:
+; CHECK64-IZHINXMIN:       # %bb.0: # %start
+; CHECK64-IZHINXMIN-NEXT:    lui a1, %hi(.LCPI34_0)
+; CHECK64-IZHINXMIN-NEXT:    lw a1, %lo(.LCPI34_0)(a1)
+; CHECK64-IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECK64-IZHINXMIN-NEXT:    fmax.s a0, a0, zero
+; CHECK64-IZHINXMIN-NEXT:    fmin.s a0, a0, a1
+; CHECK64-IZHINXMIN-NEXT:    fcvt.lu.s a0, a0, rtz
+; CHECK64-IZHINXMIN-NEXT:    ret
+;
+; CHECK32-IZDINXZHINXMIN-LABEL: fcvt_wu_s_sat_i16:
+; CHECK32-IZDINXZHINXMIN:       # %bb.0: # %start
+; CHECK32-IZDINXZHINXMIN-NEXT:    lui a1, %hi(.LCPI34_0)
+; CHECK32-IZDINXZHINXMIN-NEXT:    lw a1, %lo(.LCPI34_0)(a1)
+; CHECK32-IZDINXZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECK32-IZDINXZHINXMIN-NEXT:    fmax.s a0, a0, zero
+; CHECK32-IZDINXZHINXMIN-NEXT:    fmin.s a0, a0, a1
+; CHECK32-IZDINXZHINXMIN-NEXT:    fcvt.wu.s a0, a0, rtz
+; CHECK32-IZDINXZHINXMIN-NEXT:    ret
+;
+; CHECK64-IZDINXZHINXMIN-LABEL: fcvt_wu_s_sat_i16:
+; CHECK64-IZDINXZHINXMIN:       # %bb.0: # %start
+; CHECK64-IZDINXZHINXMIN-NEXT:    lui a1, %hi(.LCPI34_0)
+; CHECK64-IZDINXZHINXMIN-NEXT:    lw a1, %lo(.LCPI34_0)(a1)
+; CHECK64-IZDINXZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECK64-IZDINXZHINXMIN-NEXT:    fmax.s a0, a0, zero
+; CHECK64-IZDINXZHINXMIN-NEXT:    fmin.s a0, a0, a1
+; CHECK64-IZDINXZHINXMIN-NEXT:    fcvt.lu.s a0, a0, rtz
+; CHECK64-IZDINXZHINXMIN-NEXT:    ret
 start:
   %0 = tail call i16 @llvm.fptoui.sat.i16.f16(half %a)
   ret i16 %0
 }
 
 define signext i8 @fcvt_w_s_i8(half %a) nounwind {
 ; RV32IZFH-LABEL: fcvt_w_s_i8:
 ; RV32IZFH:       # %bb.0:

 ; RV32IDZFH-NEXT:    fcvt.w.h a0, fa0, rtz
 ; RV32IDZFH-NEXT:    ret
 ;
 ; RV64IDZFH-LABEL: fcvt_w_s_i8:
 ; RV64IDZFH:       # %bb.0:
 ; RV64IDZFH-NEXT:    fcvt.l.h a0, fa0, rtz
 ; RV64IDZFH-NEXT:    ret
 ;
+; RV32IZHINX-LABEL: fcvt_w_s_i8:
+; RV32IZHINX:       # %bb.0:
+; RV32IZHINX-NEXT:    fcvt.w.h a0, a0, rtz
+; RV32IZHINX-NEXT:    ret
+;
+; RV64IZHINX-LABEL: fcvt_w_s_i8:
+; RV64IZHINX:       # %bb.0:
+; RV64IZHINX-NEXT:    fcvt.l.h a0, a0, rtz
+; RV64IZHINX-NEXT:    ret
+;
+; RV32IZDINXZHINX-LABEL: fcvt_w_s_i8:
+; RV32IZDINXZHINX:       # %bb.0:
+; RV32IZDINXZHINX-NEXT:    fcvt.w.h a0, a0, rtz
+; RV32IZDINXZHINX-NEXT:    ret
+;
+; RV64IZDINXZHINX-LABEL: fcvt_w_s_i8:
+; RV64IZDINXZHINX:       # %bb.0:
+; RV64IZDINXZHINX-NEXT:    fcvt.l.h a0, a0, rtz
+; RV64IZDINXZHINX-NEXT:    ret
+;
 ; RV32I-LABEL: fcvt_w_s_i8:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    slli a0, a0, 16
 ; RV32I-NEXT:    srli a0, a0, 16
 ; RV32I-NEXT:    call __extendhfsf2@plt
 ; RV32I-NEXT:    call __fixsfsi@plt

 ; CHECK32-IZFHMIN-NEXT:    fcvt.w.s a0, fa5, rtz
 ; CHECK32-IZFHMIN-NEXT:    ret
 ;
 ; CHECK64-IZFHMIN-LABEL: fcvt_w_s_i8:
 ; CHECK64-IZFHMIN:       # %bb.0:
 ; CHECK64-IZFHMIN-NEXT:    fcvt.s.h fa5, fa0
 ; CHECK64-IZFHMIN-NEXT:    fcvt.l.s a0, fa5, rtz
 ; CHECK64-IZFHMIN-NEXT:    ret
+;
+; CHECK32-IZHINXMIN-LABEL: fcvt_w_s_i8:
+; CHECK32-IZHINXMIN:       # %bb.0:
+; CHECK32-IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECK32-IZHINXMIN-NEXT:    fcvt.w.s a0, a0, rtz
+; CHECK32-IZHINXMIN-NEXT:    ret
+;
+; CHECK64-IZHINXMIN-LABEL: fcvt_w_s_i8:
+; CHECK64-IZHINXMIN:       # %bb.0:
+; CHECK64-IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECK64-IZHINXMIN-NEXT:    fcvt.l.s a0, a0, rtz
+; CHECK64-IZHINXMIN-NEXT:    ret
+;
+; CHECK32-IZDINXZHINXMIN-LABEL: fcvt_w_s_i8:
+; CHECK32-IZDINXZHINXMIN:       # %bb.0:
+; CHECK32-IZDINXZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECK32-IZDINXZHINXMIN-NEXT:    fcvt.w.s a0, a0, rtz
+; CHECK32-IZDINXZHINXMIN-NEXT:    ret
+;
+; CHECK64-IZDINXZHINXMIN-LABEL: fcvt_w_s_i8:
+; CHECK64-IZDINXZHINXMIN:       # %bb.0:
+; CHECK64-IZDINXZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECK64-IZDINXZHINXMIN-NEXT:    fcvt.l.s a0, a0, rtz
+; CHECK64-IZDINXZHINXMIN-NEXT:    ret
   %1 = fptosi half %a to i8
   ret i8 %1
 }
 
 define signext i8 @fcvt_w_s_sat_i8(half %a) nounwind {
 ; RV32IZFH-LABEL: fcvt_w_s_sat_i8:
 ; RV32IZFH:       # %bb.0: # %start
 ; RV32IZFH-NEXT:    fcvt.s.h fa5, fa0

 ; RV64IDZFH-NEXT:    fmax.s fa5, fa5, fa4
 ; RV64IDZFH-NEXT:    lui a1, 274400
 ; RV64IDZFH-NEXT:    fmv.w.x fa4, a1
 ; RV64IDZFH-NEXT:    fmin.s fa5, fa5, fa4
 ; RV64IDZFH-NEXT:    fcvt.l.s a1, fa5, rtz
 ; RV64IDZFH-NEXT:    and a0, a0, a1
 ; RV64IDZFH-NEXT:    ret
 ;
+; RV32IZHINX-LABEL: fcvt_w_s_sat_i8:
+; RV32IZHINX:       # %bb.0: # %start
+; RV32IZHINX-NEXT:    fcvt.s.h a0, a0
+; RV32IZHINX-NEXT:    feq.s a1, a0, a0
+; RV32IZHINX-NEXT:    neg a1, a1
+; RV32IZHINX-NEXT:    lui a2, 798720
+; RV32IZHINX-NEXT:    fmax.s a0, a0, a2
+; RV32IZHINX-NEXT:    lui a2, 274400
+; RV32IZHINX-NEXT:    fmin.s a0, a0, a2
+; RV32IZHINX-NEXT:    fcvt.w.s a0, a0, rtz
+; RV32IZHINX-NEXT:    and a0, a1, a0
+; RV32IZHINX-NEXT:    ret
+;
+; RV64IZHINX-LABEL: fcvt_w_s_sat_i8:
+; RV64IZHINX:       # %bb.0: # %start
+; RV64IZHINX-NEXT:    fcvt.s.h a0, a0
+; RV64IZHINX-NEXT:    feq.s a1, a0, a0
+; RV64IZHINX-NEXT:    neg a1, a1
+; RV64IZHINX-NEXT:    lui a2, 798720
+; RV64IZHINX-NEXT:    fmax.s a0, a0, a2
+; RV64IZHINX-NEXT:    lui a2, 274400
+; RV64IZHINX-NEXT:    fmin.s a0, a0, a2
+; RV64IZHINX-NEXT:    fcvt.l.s a0, a0, rtz
+; RV64IZHINX-NEXT:    and a0, a1, a0
+; RV64IZHINX-NEXT:    ret
+;
+; RV32IZDINXZHINX-LABEL: fcvt_w_s_sat_i8:
+; RV32IZDINXZHINX:       # %bb.0: # %start
+; RV32IZDINXZHINX-NEXT:    fcvt.s.h a0, a0
+; RV32IZDINXZHINX-NEXT:    feq.s a1, a0, a0
+; RV32IZDINXZHINX-NEXT:    neg a1, a1
+; RV32IZDINXZHINX-NEXT:    lui a2, 798720
+; RV32IZDINXZHINX-NEXT:    fmax.s a0, a0, a2
+; RV32IZDINXZHINX-NEXT:    lui a2, 274400
+; RV32IZDINXZHINX-NEXT:    fmin.s a0, a0, a2
+; RV32IZDINXZHINX-NEXT:    fcvt.w.s a0, a0, rtz
+; RV32IZDINXZHINX-NEXT:    and a0, a1, a0
+; RV32IZDINXZHINX-NEXT:    ret
+;
+; RV64IZDINXZHINX-LABEL: fcvt_w_s_sat_i8:
+; RV64IZDINXZHINX:       # %bb.0: # %start
+; RV64IZDINXZHINX-NEXT:    fcvt.s.h a0, a0
+; RV64IZDINXZHINX-NEXT:    feq.s a1, a0, a0
+; RV64IZDINXZHINX-NEXT:    neg a1, a1
+; RV64IZDINXZHINX-NEXT:    lui a2, 798720
+; RV64IZDINXZHINX-NEXT:    fmax.s a0, a0, a2
+; RV64IZDINXZHINX-NEXT:    lui a2, 274400
+; RV64IZDINXZHINX-NEXT:    fmin.s a0, a0, a2
+; RV64IZDINXZHINX-NEXT:    fcvt.l.s a0, a0, rtz
+; RV64IZDINXZHINX-NEXT:    and a0, a1, a0
+; RV64IZDINXZHINX-NEXT:    ret
+;
 ; RV32I-LABEL: fcvt_w_s_sat_i8:
 ; RV32I:       # %bb.0: # %start
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s2, 0(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    slli a0, a0, 16

 ; CHECK64-IZFHMIN-NEXT:    fmv.w.x fa4, a1
 ; CHECK64-IZFHMIN-NEXT:    fmax.s fa5, fa5, fa4
 ; CHECK64-IZFHMIN-NEXT:    lui a1, 274400
 ; CHECK64-IZFHMIN-NEXT:    fmv.w.x fa4, a1
 ; CHECK64-IZFHMIN-NEXT:    fmin.s fa5, fa5, fa4
 ; CHECK64-IZFHMIN-NEXT:    fcvt.l.s a1, fa5, rtz
 ; CHECK64-IZFHMIN-NEXT:    and a0, a0, a1
 ; CHECK64-IZFHMIN-NEXT:    ret
+;
+; CHECK32-IZHINXMIN-LABEL: fcvt_w_s_sat_i8:
+; CHECK32-IZHINXMIN:       # %bb.0: # %start
+; CHECK32-IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECK32-IZHINXMIN-NEXT:    feq.s a1, a0, a0
+; CHECK32-IZHINXMIN-NEXT:    neg a1, a1
+; CHECK32-IZHINXMIN-NEXT:    lui a2, 798720
+; CHECK32-IZHINXMIN-NEXT:    fmax.s a0, a0, a2
+; CHECK32-IZHINXMIN-NEXT:    lui a2, 274400
+; CHECK32-IZHINXMIN-NEXT:    fmin.s a0, a0, a2
+; CHECK32-IZHINXMIN-NEXT:    fcvt.w.s a0, a0, rtz
+; CHECK32-IZHINXMIN-NEXT:    and a0, a1, a0
+; CHECK32-IZHINXMIN-NEXT:    ret
+;
+; CHECK64-IZHINXMIN-LABEL: fcvt_w_s_sat_i8:
+; CHECK64-IZHINXMIN:       # %bb.0: # %start
+; CHECK64-IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECK64-IZHINXMIN-NEXT:    feq.s a1, a0, a0
+; CHECK64-IZHINXMIN-NEXT:    neg a1, a1
+; CHECK64-IZHINXMIN-NEXT:    lui a2, 798720
+; CHECK64-IZHINXMIN-NEXT:    fmax.s a0, a0, a2
+; CHECK64-IZHINXMIN-NEXT:    lui a2, 274400
+; CHECK64-IZHINXMIN-NEXT:    fmin.s a0, a0, a2
+; CHECK64-IZHINXMIN-NEXT:    fcvt.l.s a0, a0, rtz
+; CHECK64-IZHINXMIN-NEXT:    and a0, a1, a0
+; CHECK64-IZHINXMIN-NEXT:    ret
+;
+; CHECK32-IZDINXZHINXMIN-LABEL: fcvt_w_s_sat_i8:
+; CHECK32-IZDINXZHINXMIN:       # %bb.0: # %start
+; CHECK32-IZDINXZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECK32-IZDINXZHINXMIN-NEXT:    feq.s a1, a0, a0
+; CHECK32-IZDINXZHINXMIN-NEXT:    neg a1, a1
+; CHECK32-IZDINXZHINXMIN-NEXT:    lui a2, 798720
+; CHECK32-IZDINXZHINXMIN-NEXT:    fmax.s a0, a0, a2
+; CHECK32-IZDINXZHINXMIN-NEXT:    lui a2, 274400
+; CHECK32-IZDINXZHINXMIN-NEXT:    fmin.s a0, a0, a2
+; CHECK32-IZDINXZHINXMIN-NEXT:    fcvt.w.s a0, a0, rtz
+; CHECK32-IZDINXZHINXMIN-NEXT:    and a0, a1, a0
+; CHECK32-IZDINXZHINXMIN-NEXT:    ret
+;
+; CHECK64-IZDINXZHINXMIN-LABEL: fcvt_w_s_sat_i8:
+; CHECK64-IZDINXZHINXMIN:       # %bb.0: # %start
+; CHECK64-IZDINXZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECK64-IZDINXZHINXMIN-NEXT:    feq.s a1, a0, a0
+; CHECK64-IZDINXZHINXMIN-NEXT:    neg a1, a1
+; CHECK64-IZDINXZHINXMIN-NEXT:    lui a2, 798720
+; CHECK64-IZDINXZHINXMIN-NEXT:    fmax.s a0, a0, a2
+; CHECK64-IZDINXZHINXMIN-NEXT:    lui a2, 274400
+; CHECK64-IZDINXZHINXMIN-NEXT:    fmin.s a0, a0, a2
+; CHECK64-IZDINXZHINXMIN-NEXT:    fcvt.l.s a0, a0, rtz
+; CHECK64-IZDINXZHINXMIN-NEXT:    and a0, a1, a0
+; CHECK64-IZDINXZHINXMIN-NEXT:    ret
 start:
   %0 = tail call i8 @llvm.fptosi.sat.i8.f16(half %a)
   ret i8 %0
 }
 declare i8 @llvm.fptosi.sat.i8.f16(half)
 
 define zeroext i8 @fcvt_wu_s_i8(half %a) nounwind {
 ; RV32IZFH-LABEL: fcvt_wu_s_i8:

 ; RV32IDZFH-NEXT:    fcvt.wu.h a0, fa0, rtz
 ; RV32IDZFH-NEXT:    ret
 ;
 ; RV64IDZFH-LABEL: fcvt_wu_s_i8:
 ; RV64IDZFH:       # %bb.0:
 ; RV64IDZFH-NEXT:    fcvt.lu.h a0, fa0, rtz
 ; RV64IDZFH-NEXT:    ret
 ;
+; RV32IZHINX-LABEL: fcvt_wu_s_i8:
+; RV32IZHINX:       # %bb.0:
+; RV32IZHINX-NEXT:    fcvt.wu.h a0, a0, rtz
+; RV32IZHINX-NEXT:    ret
+;
+; RV64IZHINX-LABEL: fcvt_wu_s_i8:
+; RV64IZHINX:       # %bb.0:
+; RV64IZHINX-NEXT:    fcvt.lu.h a0, a0, rtz
+; RV64IZHINX-NEXT:    ret
+;
+; RV32IZDINXZHINX-LABEL: fcvt_wu_s_i8:
+; RV32IZDINXZHINX:       # %bb.0:
+; RV32IZDINXZHINX-NEXT:    fcvt.wu.h a0, a0, rtz
+; RV32IZDINXZHINX-NEXT:    ret
+;
+; RV64IZDINXZHINX-LABEL: fcvt_wu_s_i8:
+; RV64IZDINXZHINX:       # %bb.0:
+; RV64IZDINXZHINX-NEXT:    fcvt.lu.h a0, a0, rtz
+; RV64IZDINXZHINX-NEXT:    ret
+;
 ; RV32I-LABEL: fcvt_wu_s_i8:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    slli a0, a0, 16
 ; RV32I-NEXT:    srli a0, a0, 16
 ; RV32I-NEXT:    call __extendhfsf2@plt
 ; RV32I-NEXT:    call __fixunssfsi@plt

 ; CHECK32-IZFHMIN-NEXT:    fcvt.wu.s a0, fa5, rtz
 ; CHECK32-IZFHMIN-NEXT:    ret
 ;
 ; CHECK64-IZFHMIN-LABEL: fcvt_wu_s_i8:
 ; CHECK64-IZFHMIN:       # %bb.0:
 ; CHECK64-IZFHMIN-NEXT:    fcvt.s.h fa5, fa0
 ; CHECK64-IZFHMIN-NEXT:    fcvt.lu.s a0, fa5, rtz
 ; CHECK64-IZFHMIN-NEXT:    ret
+;
+; CHECK32-IZHINXMIN-LABEL: fcvt_wu_s_i8:
+; CHECK32-IZHINXMIN:       # %bb.0:
+; CHECK32-IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECK32-IZHINXMIN-NEXT:    fcvt.wu.s a0, a0, rtz
+; CHECK32-IZHINXMIN-NEXT:    ret
+;
+; CHECK64-IZHINXMIN-LABEL: fcvt_wu_s_i8:
+; CHECK64-IZHINXMIN:       # %bb.0:
+; CHECK64-IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECK64-IZHINXMIN-NEXT:    fcvt.lu.s a0, a0, rtz
+; CHECK64-IZHINXMIN-NEXT:    ret
+;
+; CHECK32-IZDINXZHINXMIN-LABEL: fcvt_wu_s_i8:
+; CHECK32-IZDINXZHINXMIN:       # %bb.0:
+; CHECK32-IZDINXZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECK32-IZDINXZHINXMIN-NEXT:    fcvt.wu.s a0, a0, rtz
+; CHECK32-IZDINXZHINXMIN-NEXT:    ret
+;
+; CHECK64-IZDINXZHINXMIN-LABEL: fcvt_wu_s_i8:
+; CHECK64-IZDINXZHINXMIN:       # %bb.0:
+; CHECK64-IZDINXZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECK64-IZDINXZHINXMIN-NEXT:    fcvt.lu.s a0, a0, rtz
+; CHECK64-IZDINXZHINXMIN-NEXT:    ret
   %1 = fptoui half %a to i8
   ret i8 %1
 }
 
 define zeroext i8 @fcvt_wu_s_sat_i8(half %a) nounwind {
 ; RV32IZFH-LABEL: fcvt_wu_s_sat_i8:
 ; RV32IZFH:       # %bb.0: # %start
 ; RV32IZFH-NEXT:    fcvt.s.h fa5, fa0

 ; RV64IDZFH-NEXT:    fmv.w.x fa4, zero
 ; RV64IDZFH-NEXT:    fmax.s fa5, fa5, fa4
 ; RV64IDZFH-NEXT:    lui a0, 276464
 ; RV64IDZFH-NEXT:    fmv.w.x fa4, a0
 ; RV64IDZFH-NEXT:    fmin.s fa5, fa5, fa4
 ; RV64IDZFH-NEXT:    fcvt.lu.s a0, fa5, rtz
 ; RV64IDZFH-NEXT:    ret
 ;
+; RV32IZHINX-LABEL: fcvt_wu_s_sat_i8:
+; RV32IZHINX:       # %bb.0: # %start
+; RV32IZHINX-NEXT:    fcvt.s.h a0, a0
+; RV32IZHINX-NEXT:    fmax.s a0, a0, zero
+; RV32IZHINX-NEXT:    lui a1, 276464
+; RV32IZHINX-NEXT:    fmin.s a0, a0, a1
+; RV32IZHINX-NEXT:    fcvt.wu.s a0, a0, rtz
+; RV32IZHINX-NEXT:    ret
+;
+; RV64IZHINX-LABEL: fcvt_wu_s_sat_i8:
+; RV64IZHINX:       # %bb.0: # %start
+; RV64IZHINX-NEXT:    fcvt.s.h a0, a0
+; RV64IZHINX-NEXT:    fmax.s a0, a0, zero
+; RV64IZHINX-NEXT:    lui a1, 276464
+; RV64IZHINX-NEXT:    fmin.s a0, a0, a1
+; RV64IZHINX-NEXT:    fcvt.lu.s a0, a0, rtz
+; RV64IZHINX-NEXT:    ret
+;
+; RV32IZDINXZHINX-LABEL: fcvt_wu_s_sat_i8:
+; RV32IZDINXZHINX:       # %bb.0: # %start
+; RV32IZDINXZHINX-NEXT:    fcvt.s.h a0, a0
+; RV32IZDINXZHINX-NEXT:    fmax.s a0, a0, zero
+; RV32IZDINXZHINX-NEXT:    lui a1, 276464
+; RV32IZDINXZHINX-NEXT:    fmin.s a0, a0, a1
+; RV32IZDINXZHINX-NEXT:    fcvt.wu.s a0, a0, rtz
+; RV32IZDINXZHINX-NEXT:    ret
+;
+; RV64IZDINXZHINX-LABEL: fcvt_wu_s_sat_i8:
+; RV64IZDINXZHINX:       # %bb.0: # %start
+; RV64IZDINXZHINX-NEXT:    fcvt.s.h a0, a0
+; RV64IZDINXZHINX-NEXT:    fmax.s a0, a0, zero
+; RV64IZDINXZHINX-NEXT:    lui a1, 276464
+; RV64IZDINXZHINX-NEXT:    fmin.s a0, a0, a1
+; RV64IZDINXZHINX-NEXT:    fcvt.lu.s a0, a0, rtz
+; RV64IZDINXZHINX-NEXT:    ret
+;
 ; RV32I-LABEL: fcvt_wu_s_sat_i8:
 ; RV32I:       # %bb.0: # %start
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s2, 0(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    slli a0, a0, 16

 ; CHECK64-IZFHMIN-NEXT:    fcvt.s.h fa5, fa0
 ; CHECK64-IZFHMIN-NEXT:    fmv.w.x fa4, zero
 ; CHECK64-IZFHMIN-NEXT:    fmax.s fa5, fa5, fa4
 ; CHECK64-IZFHMIN-NEXT:    lui a0, 276464
 ; CHECK64-IZFHMIN-NEXT:    fmv.w.x fa4, a0
 ; CHECK64-IZFHMIN-NEXT:    fmin.s fa5, fa5, fa4
 ; CHECK64-IZFHMIN-NEXT:    fcvt.lu.s a0, fa5, rtz
 ; CHECK64-IZFHMIN-NEXT:    ret
+;
+; CHECK32-IZHINXMIN-LABEL: fcvt_wu_s_sat_i8:
+; CHECK32-IZHINXMIN:       # %bb.0: # %start
+; CHECK32-IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECK32-IZHINXMIN-NEXT:    fmax.s a0, a0, zero
+; CHECK32-IZHINXMIN-NEXT:    lui a1, 276464
+; CHECK32-IZHINXMIN-NEXT:    fmin.s a0, a0, a1
+; CHECK32-IZHINXMIN-NEXT:    fcvt.wu.s a0, a0, rtz
+; CHECK32-IZHINXMIN-NEXT:    ret
+;
+; CHECK64-IZHINXMIN-LABEL: fcvt_wu_s_sat_i8:
+; CHECK64-IZHINXMIN:       # %bb.0: # %start
+; CHECK64-IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECK64-IZHINXMIN-NEXT:    fmax.s a0, a0, zero
+; CHECK64-IZHINXMIN-NEXT:    lui a1, 276464
+; CHECK64-IZHINXMIN-NEXT:    fmin.s a0, a0, a1
+; CHECK64-IZHINXMIN-NEXT:    fcvt.lu.s a0, a0, rtz
+; CHECK64-IZHINXMIN-NEXT:    ret
+;
+; CHECK32-IZDINXZHINXMIN-LABEL: fcvt_wu_s_sat_i8:
+; CHECK32-IZDINXZHINXMIN:       # %bb.0: # %start
+; CHECK32-IZDINXZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECK32-IZDINXZHINXMIN-NEXT:    fmax.s a0, a0, zero
+; CHECK32-IZDINXZHINXMIN-NEXT:    lui a1, 276464
+; CHECK32-IZDINXZHINXMIN-NEXT:    fmin.s a0, a0, a1
+; CHECK32-IZDINXZHINXMIN-NEXT:    fcvt.wu.s a0, a0, rtz
+; CHECK32-IZDINXZHINXMIN-NEXT:    ret
+;
+; CHECK64-IZDINXZHINXMIN-LABEL: fcvt_wu_s_sat_i8:
+; CHECK64-IZDINXZHINXMIN:       # %bb.0: # %start
+; CHECK64-IZDINXZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECK64-IZDINXZHINXMIN-NEXT:    fmax.s a0, a0, zero
+; CHECK64-IZDINXZHINXMIN-NEXT:    lui a1, 276464
+; CHECK64-IZDINXZHINXMIN-NEXT:    fmin.s a0, a0, a1
+; CHECK64-IZDINXZHINXMIN-NEXT:    fcvt.lu.s a0, a0, rtz
+; CHECK64-IZDINXZHINXMIN-NEXT:    ret
 start:
   %0 = tail call i8 @llvm.fptoui.sat.i8.f16(half %a)
   ret i8 %0
 }
 declare i8 @llvm.fptoui.sat.i8.f16(half)
 
 define zeroext i32 @fcvt_wu_h_sat_zext(half %a) nounwind {
 ; RV32IZFH-LABEL: fcvt_wu_h_sat_zext:

 ; RV64IDZFH-NEXT:    feq.h a1, fa0, fa0
 ; RV64IDZFH-NEXT:    seqz a1, a1
 ; RV64IDZFH-NEXT:    addiw a1, a1, -1
 ; RV64IDZFH-NEXT:    and a0, a0, a1
 ; RV64IDZFH-NEXT:    slli a0, a0, 32
 ; RV64IDZFH-NEXT:    srli a0, a0, 32
 ; RV64IDZFH-NEXT:    ret
 ;
+; RV32IZHINX-LABEL: fcvt_wu_h_sat_zext:
+; RV32IZHINX:       # %bb.0: # %start
+; RV32IZHINX-NEXT:    fcvt.wu.h a1, a0, rtz
+; RV32IZHINX-NEXT:    feq.h a0, a0, a0
+; RV32IZHINX-NEXT:    seqz a0, a0
+; RV32IZHINX-NEXT:    addi a0, a0, -1
+; RV32IZHINX-NEXT:    and a0, a0, a1
+; RV32IZHINX-NEXT:    ret
+;
+; RV64IZHINX-LABEL: fcvt_wu_h_sat_zext:
+; RV64IZHINX:       # %bb.0: # %start
+; RV64IZHINX-NEXT:    fcvt.wu.h a1, a0, rtz
+; RV64IZHINX-NEXT:    feq.h a0, a0, a0
+; RV64IZHINX-NEXT:    seqz a0, a0
+; RV64IZHINX-NEXT:    addiw a0, a0, -1
+; RV64IZHINX-NEXT:    and a0, a1, a0
+; RV64IZHINX-NEXT:    slli a0, a0, 32
+; RV64IZHINX-NEXT:    srli a0, a0, 32
+; RV64IZHINX-NEXT:    ret
+;
+; RV32IZDINXZHINX-LABEL: fcvt_wu_h_sat_zext:
+; RV32IZDINXZHINX:       # %bb.0: # %start
+; RV32IZDINXZHINX-NEXT:    fcvt.wu.h a1, a0, rtz
+; RV32IZDINXZHINX-NEXT:    feq.h a0, a0, a0
+; RV32IZDINXZHINX-NEXT:    seqz a0, a0
+; RV32IZDINXZHINX-NEXT:    addi a0, a0, -1
+; RV32IZDINXZHINX-NEXT:    and a0, a0, a1
+; RV32IZDINXZHINX-NEXT:    ret
+;
+; RV64IZDINXZHINX-LABEL: fcvt_wu_h_sat_zext:
+; RV64IZDINXZHINX:       # %bb.0: # %start
+; RV64IZDINXZHINX-NEXT:    fcvt.wu.h a1, a0, rtz
+; RV64IZDINXZHINX-NEXT:    feq.h a0, a0, a0
+; RV64IZDINXZHINX-NEXT:    seqz a0, a0
+; RV64IZDINXZHINX-NEXT:    addiw a0, a0, -1
+; RV64IZDINXZHINX-NEXT:    and a0, a1, a0
+; RV64IZDINXZHINX-NEXT:    slli a0, a0, 32
+; RV64IZDINXZHINX-NEXT:    srli a0, a0, 32
+; RV64IZDINXZHINX-NEXT:    ret
+;
 ; RV32I-LABEL: fcvt_wu_h_sat_zext:
 ; RV32I:       # %bb.0: # %start
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s2, 0(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    slli a0, a0, 16

 ; CHECK64-IZFHMIN-NEXT:    fcvt.wu.s a0, fa5, rtz
 ; CHECK64-IZFHMIN-NEXT:    feq.s a1, fa5, fa5
 ; CHECK64-IZFHMIN-NEXT:    seqz a1, a1
 ; CHECK64-IZFHMIN-NEXT:    addiw a1, a1, -1
 ; CHECK64-IZFHMIN-NEXT:    and a0, a0, a1
 ; CHECK64-IZFHMIN-NEXT:    slli a0, a0, 32
 ; CHECK64-IZFHMIN-NEXT:    srli a0, a0, 32
 ; CHECK64-IZFHMIN-NEXT:    ret
+;
+; CHECK32-IZHINXMIN-LABEL: fcvt_wu_h_sat_zext:
+; CHECK32-IZHINXMIN:       # %bb.0: # %start
+; CHECK32-IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECK32-IZHINXMIN-NEXT:    fcvt.wu.s a1, a0, rtz
+; CHECK32-IZHINXMIN-NEXT:    feq.s a0, a0, a0
+; CHECK32-IZHINXMIN-NEXT:    seqz a0, a0
+; CHECK32-IZHINXMIN-NEXT:    addi a0, a0, -1
+; CHECK32-IZHINXMIN-NEXT:    and a0, a0, a1
+; CHECK32-IZHINXMIN-NEXT:    ret
+;
+; CHECK64-IZHINXMIN-LABEL: fcvt_wu_h_sat_zext:
+; CHECK64-IZHINXMIN:       # %bb.0: # %start
+; CHECK64-IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECK64-IZHINXMIN-NEXT:    fcvt.wu.s a1, a0, rtz
+; CHECK64-IZHINXMIN-NEXT:    feq.s a0, a0, a0
+; CHECK64-IZHINXMIN-NEXT:    seqz a0, a0
+; CHECK64-IZHINXMIN-NEXT:    addiw a0, a0, -1
+; CHECK64-IZHINXMIN-NEXT:    and a0, a1, a0
+; CHECK64-IZHINXMIN-NEXT:    slli a0, a0, 32
+; CHECK64-IZHINXMIN-NEXT:    srli a0, a0, 32
+; CHECK64-IZHINXMIN-NEXT:    ret
+;
+; CHECK32-IZDINXZHINXMIN-LABEL: fcvt_wu_h_sat_zext:
+; CHECK32-IZDINXZHINXMIN:       # %bb.0: # %start
+; CHECK32-IZDINXZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECK32-IZDINXZHINXMIN-NEXT:    fcvt.wu.s a1, a0, rtz
+; CHECK32-IZDINXZHINXMIN-NEXT:    feq.s a0, a0, a0
+; CHECK32-IZDINXZHINXMIN-NEXT:    seqz a0, a0
+; CHECK32-IZDINXZHINXMIN-NEXT:    addi a0, a0, -1
+; CHECK32-IZDINXZHINXMIN-NEXT:    and a0, a0, a1
+; CHECK32-IZDINXZHINXMIN-NEXT:    ret
+;
+; CHECK64-IZDINXZHINXMIN-LABEL: fcvt_wu_h_sat_zext:
+; CHECK64-IZDINXZHINXMIN:       # %bb.0: # %start
+; CHECK64-IZDINXZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECK64-IZDINXZHINXMIN-NEXT:    fcvt.wu.s a1, a0, rtz
+; CHECK64-IZDINXZHINXMIN-NEXT:    feq.s a0, a0, a0
+; CHECK64-IZDINXZHINXMIN-NEXT:    seqz a0, a0
+; CHECK64-IZDINXZHINXMIN-NEXT:    addiw a0, a0, -1
+; CHECK64-IZDINXZHINXMIN-NEXT:    and a0, a1, a0
+; CHECK64-IZDINXZHINXMIN-NEXT:    slli a0, a0, 32
+; CHECK64-IZDINXZHINXMIN-NEXT:    srli a0, a0, 32
+; CHECK64-IZDINXZHINXMIN-NEXT:    ret
 start:
   %0 = tail call i32 @llvm.fptoui.sat.i32.f16(half %a)
   ret i32 %0
 }
 
 define signext i32 @fcvt_w_h_sat_sext(half %a) nounwind {
 ; CHECKIZFH-LABEL: fcvt_w_h_sat_sext:
 ; CHECKIZFH:       # %bb.0: # %start

 ; RV64IDZFH:       # %bb.0: # %start
 ; RV64IDZFH-NEXT:    fcvt.w.h a0, fa0, rtz
 ; RV64IDZFH-NEXT:    feq.h a1, fa0, fa0
 ; RV64IDZFH-NEXT:    seqz a1, a1
 ; RV64IDZFH-NEXT:    addi a1, a1, -1
 ; RV64IDZFH-NEXT:    and a0, a1, a0
 ; RV64IDZFH-NEXT:    ret
 ;
+; CHECKIZHINX-LABEL: fcvt_w_h_sat_sext:
+; CHECKIZHINX:       # %bb.0: # %start
+; CHECKIZHINX-NEXT:    fcvt.w.h a1, a0, rtz
+; CHECKIZHINX-NEXT:    feq.h a0, a0, a0
+; CHECKIZHINX-NEXT:    seqz a0, a0
+; CHECKIZHINX-NEXT:    addi a0, a0, -1
+; CHECKIZHINX-NEXT:    and a0, a0, a1
+; CHECKIZHINX-NEXT:    ret
+;
+; CHECKIZDINXZHINX-LABEL: fcvt_w_h_sat_sext:
+; CHECKIZDINXZHINX:       # %bb.0: # %start
+; CHECKIZDINXZHINX-NEXT:    fcvt.w.h a1, a0, rtz
+; CHECKIZDINXZHINX-NEXT:    feq.h a0, a0, a0
+; CHECKIZDINXZHINX-NEXT:    seqz a0, a0
+; CHECKIZDINXZHINX-NEXT:    addi a0, a0, -1
+; CHECKIZDINXZHINX-NEXT:    and a0, a0, a1
+; CHECKIZDINXZHINX-NEXT:    ret
+;
 ; RV32I-LABEL: fcvt_w_h_sat_sext:
 ; RV32I:       # %bb.0: # %start
 ; RV32I-NEXT:    addi sp, sp, -32
 ; RV32I-NEXT:    sw ra, 28(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s0, 24(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s1, 20(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s2, 16(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s3, 12(sp) # 4-byte Folded Spill

 ; CHECK64-IZFHMIN:       # %bb.0: # %start
 ; CHECK64-IZFHMIN-NEXT:    fcvt.s.h fa5, fa0
 ; CHECK64-IZFHMIN-NEXT:    fcvt.w.s a0, fa5, rtz
 ; CHECK64-IZFHMIN-NEXT:    feq.s a1, fa5, fa5
 ; CHECK64-IZFHMIN-NEXT:    seqz a1, a1
 ; CHECK64-IZFHMIN-NEXT:    addi a1, a1, -1
 ; CHECK64-IZFHMIN-NEXT:    and a0, a1, a0
 ; CHECK64-IZFHMIN-NEXT:    ret
+;
+; CHECK32-IZHINXMIN-LABEL: fcvt_w_h_sat_sext:
+; CHECK32-IZHINXMIN:       # %bb.0: # %start
+; CHECK32-IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECK32-IZHINXMIN-NEXT:    fcvt.w.s a1, a0, rtz
+; CHECK32-IZHINXMIN-NEXT:    feq.s a0, a0, a0
+; CHECK32-IZHINXMIN-NEXT:    seqz a0, a0
+; CHECK32-IZHINXMIN-NEXT:    addi a0, a0, -1
+; CHECK32-IZHINXMIN-NEXT:    and a0, a0, a1
+; CHECK32-IZHINXMIN-NEXT:    ret
+;
+; CHECK64-IZHINXMIN-LABEL: fcvt_w_h_sat_sext:
+; CHECK64-IZHINXMIN:       # %bb.0: # %start
+; CHECK64-IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECK64-IZHINXMIN-NEXT:    fcvt.w.s a1, a0, rtz
+; CHECK64-IZHINXMIN-NEXT:    feq.s a0, a0, a0
+; CHECK64-IZHINXMIN-NEXT:    seqz a0, a0
+; CHECK64-IZHINXMIN-NEXT:    addi a0, a0, -1
+; CHECK64-IZHINXMIN-NEXT:    and a0, a0, a1
+; CHECK64-IZHINXMIN-NEXT:    ret
+;
+; CHECK32-IZDINXZHINXMIN-LABEL: fcvt_w_h_sat_sext:
+; CHECK32-IZDINXZHINXMIN:       # %bb.0: # %start
+; CHECK32-IZDINXZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECK32-IZDINXZHINXMIN-NEXT:    fcvt.w.s a1, a0, rtz
+; CHECK32-IZDINXZHINXMIN-NEXT:    feq.s a0, a0, a0
+; CHECK32-IZDINXZHINXMIN-NEXT:    seqz a0, a0
+; CHECK32-IZDINXZHINXMIN-NEXT:    addi a0, a0, -1
+; CHECK32-IZDINXZHINXMIN-NEXT:    and a0, a0, a1
+; CHECK32-IZDINXZHINXMIN-NEXT:    ret
+;
+; CHECK64-IZDINXZHINXMIN-LABEL: fcvt_w_h_sat_sext:
+; CHECK64-IZDINXZHINXMIN:       # %bb.0: # %start
+; CHECK64-IZDINXZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECK64-IZDINXZHINXMIN-NEXT:    fcvt.w.s a1, a0, rtz
+; CHECK64-IZDINXZHINXMIN-NEXT:    feq.s a0, a0, a0
+; CHECK64-IZDINXZHINXMIN-NEXT:    seqz a0, a0
+; CHECK64-IZDINXZHINXMIN-NEXT:    addi a0, a0, -1
+; CHECK64-IZDINXZHINXMIN-NEXT:    and a0, a0, a1
+; CHECK64-IZDINXZHINXMIN-NEXT:    ret
 start:
   %0 = tail call i32 @llvm.fptosi.sat.i32.f16(half %a)
   ret i32 %0
 }
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; RV32IZDINXZHINXMIN: {{.*}}
+; RV32IZHINXMIN: {{.*}}
+; RV64IZDINXZHINXMIN: {{.*}}
+; RV64IZHINXMIN: {{.*}}

llvm/test/CodeGen/RISCV/half-fcmp-strict.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -mattr=+zfh -verify-machineinstrs \
 ; RUN:   -target-abi ilp32f -disable-strictnode-mutation < %s | FileCheck %s
 ; RUN: llc -mtriple=riscv64 -mattr=+zfh -verify-machineinstrs \
 ; RUN:   -target-abi lp64f -disable-strictnode-mutation < %s | FileCheck %s
+; RUN: llc -mtriple=riscv32 -mattr=+zhinx -verify-machineinstrs \
+; RUN:   -target-abi ilp32 -disable-strictnode-mutation < %s \
+; RUN:   | FileCheck -check-prefix=CHECKIZHINX %s
+; RUN: llc -mtriple=riscv64 -mattr=+zhinx -verify-machineinstrs \
+; RUN:   -target-abi lp64 -disable-strictnode-mutation < %s  \
+; RUN:   | FileCheck -check-prefix=CHECKIZHINX %s
 ; RUN: llc -mtriple=riscv32 -mattr=+zfh -verify-machineinstrs \
 ; RUN:   -target-abi ilp32f -disable-strictnode-mutation < %s \
 ; RUN:   | FileCheck -check-prefix=CHECKIZFHMIN %s
 ; RUN: llc -mtriple=riscv64 -mattr=+zfh -verify-machineinstrs \
 ; RUN:   -target-abi lp64f -disable-strictnode-mutation < %s  \
 ; RUN:   | FileCheck -check-prefix=CHECKIZFHMIN %s
+; RUN: llc -mtriple=riscv32 -mattr=+zhinxmin -verify-machineinstrs \
+; RUN:   -target-abi ilp32 -disable-strictnode-mutation < %s \
+; RUN:   | FileCheck -check-prefix=CHECKIZHINXMIN %s
+; RUN: llc -mtriple=riscv64 -mattr=+zhinxmin -verify-machineinstrs \
+; RUN:   -target-abi lp64 -disable-strictnode-mutation < %s  \
+; RUN:   | FileCheck -check-prefix=CHECKIZHINXMIN %s
 
 define i32 @fcmp_oeq(half %a, half %b) nounwind strictfp {
 ; CHECK-LABEL: fcmp_oeq:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    feq.h a0, fa0, fa1
 ; CHECK-NEXT:    ret
 ;
+; CHECKIZHINX-LABEL: fcmp_oeq:
+; CHECKIZHINX:       # %bb.0:
+; CHECKIZHINX-NEXT:    feq.h a0, a0, a1
+; CHECKIZHINX-NEXT:    ret
+;
 ; CHECKIZFHMIN-LABEL: fcmp_oeq:
 ; CHECKIZFHMIN:       # %bb.0:
 ; CHECKIZFHMIN-NEXT:    feq.h a0, fa0, fa1
 ; CHECKIZFHMIN-NEXT:    ret
+;
+; CHECKIZHINXMIN-LABEL: fcmp_oeq:
+; CHECKIZHINXMIN:       # %bb.0:
+; CHECKIZHINXMIN-NEXT:    fcvt.s.h a1, a1
+; CHECKIZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECKIZHINXMIN-NEXT:    feq.s a0, a0, a1
+; CHECKIZHINXMIN-NEXT:    ret
   %1 = call i1 @llvm.experimental.constrained.fcmp.f16(half %a, half %b, metadata !"oeq", metadata !"fpexcept.strict") strictfp
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 declare i1 @llvm.experimental.constrained.fcmp.f16(half, half, metadata, metadata)
 
 define i32 @fcmp_ogt(half %a, half %b) nounwind strictfp {
 ; CHECK-LABEL: fcmp_ogt:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    frflags a1
 ; CHECK-NEXT:    flt.h a0, fa1, fa0
 ; CHECK-NEXT:    fsflags a1
 ; CHECK-NEXT:    feq.h zero, fa1, fa0
 ; CHECK-NEXT:    ret
 ;
+; CHECKIZHINX-LABEL: fcmp_ogt:
+; CHECKIZHINX:       # %bb.0:
+; CHECKIZHINX-NEXT:    csrr a3, fflags
+; CHECKIZHINX-NEXT:    flt.h a2, a1, a0
+; CHECKIZHINX-NEXT:    csrw fflags, a3
+; CHECKIZHINX-NEXT:    feq.h zero, a1, a0
+; CHECKIZHINX-NEXT:    mv a0, a2
+; CHECKIZHINX-NEXT:    ret
+;
 ; CHECKIZFHMIN-LABEL: fcmp_ogt:
 ; CHECKIZFHMIN:       # %bb.0:
 ; CHECKIZFHMIN-NEXT:    frflags a1
 ; CHECKIZFHMIN-NEXT:    flt.h a0, fa1, fa0
 ; CHECKIZFHMIN-NEXT:    fsflags a1
 ; CHECKIZFHMIN-NEXT:    feq.h zero, fa1, fa0
 ; CHECKIZFHMIN-NEXT:    ret
+;
+; CHECKIZHINXMIN-LABEL: fcmp_ogt:
+; CHECKIZHINXMIN:       # %bb.0:
+; CHECKIZHINXMIN-NEXT:    fcvt.s.h a2, a0
+; CHECKIZHINXMIN-NEXT:    fcvt.s.h a1, a1
+; CHECKIZHINXMIN-NEXT:    csrr a3, fflags
+; CHECKIZHINXMIN-NEXT:    flt.s a0, a1, a2
+; CHECKIZHINXMIN-NEXT:    csrw fflags, a3
+; CHECKIZHINXMIN-NEXT:    feq.s zero, a1, a2
+; CHECKIZHINXMIN-NEXT:    ret
   %1 = call i1 @llvm.experimental.constrained.fcmp.f16(half %a, half %b, metadata !"ogt", metadata !"fpexcept.strict") strictfp
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmp_oge(half %a, half %b) nounwind strictfp {
 ; CHECK-LABEL: fcmp_oge:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    frflags a1
 ; CHECK-NEXT:    fle.h a0, fa1, fa0
 ; CHECK-NEXT:    fsflags a1
 ; CHECK-NEXT:    feq.h zero, fa1, fa0
 ; CHECK-NEXT:    ret
 ;
+; CHECKIZHINX-LABEL: fcmp_oge:
+; CHECKIZHINX:       # %bb.0:
+; CHECKIZHINX-NEXT:    csrr a3, fflags
+; CHECKIZHINX-NEXT:    fle.h a2, a1, a0
+; CHECKIZHINX-NEXT:    csrw fflags, a3
+; CHECKIZHINX-NEXT:    feq.h zero, a1, a0
+; CHECKIZHINX-NEXT:    mv a0, a2
+; CHECKIZHINX-NEXT:    ret
+;
 ; CHECKIZFHMIN-LABEL: fcmp_oge:
 ; CHECKIZFHMIN:       # %bb.0:
 ; CHECKIZFHMIN-NEXT:    frflags a1
 ; CHECKIZFHMIN-NEXT:    fle.h a0, fa1, fa0
 ; CHECKIZFHMIN-NEXT:    fsflags a1
 ; CHECKIZFHMIN-NEXT:    feq.h zero, fa1, fa0
 ; CHECKIZFHMIN-NEXT:    ret
+;
+; CHECKIZHINXMIN-LABEL: fcmp_oge:
+; CHECKIZHINXMIN:       # %bb.0:
+; CHECKIZHINXMIN-NEXT:    fcvt.s.h a2, a0
+; CHECKIZHINXMIN-NEXT:    fcvt.s.h a1, a1
+; CHECKIZHINXMIN-NEXT:    csrr a3, fflags
+; CHECKIZHINXMIN-NEXT:    fle.s a0, a1, a2
+; CHECKIZHINXMIN-NEXT:    csrw fflags, a3
+; CHECKIZHINXMIN-NEXT:    feq.s zero, a1, a2
+; CHECKIZHINXMIN-NEXT:    ret
   %1 = call i1 @llvm.experimental.constrained.fcmp.f16(half %a, half %b, metadata !"oge", metadata !"fpexcept.strict") strictfp
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmp_olt(half %a, half %b) nounwind strictfp {
 ; CHECK-LABEL: fcmp_olt:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    frflags a1
 ; CHECK-NEXT:    flt.h a0, fa0, fa1
 ; CHECK-NEXT:    fsflags a1
 ; CHECK-NEXT:    feq.h zero, fa0, fa1
 ; CHECK-NEXT:    ret
 ;
+; CHECKIZHINX-LABEL: fcmp_olt:
+; CHECKIZHINX:       # %bb.0:
+; CHECKIZHINX-NEXT:    csrr a3, fflags
+; CHECKIZHINX-NEXT:    flt.h a2, a0, a1
+; CHECKIZHINX-NEXT:    csrw fflags, a3
+; CHECKIZHINX-NEXT:    feq.h zero, a0, a1
+; CHECKIZHINX-NEXT:    mv a0, a2
+; CHECKIZHINX-NEXT:    ret
+;
 ; CHECKIZFHMIN-LABEL: fcmp_olt:
 ; CHECKIZFHMIN:       # %bb.0:
 ; CHECKIZFHMIN-NEXT:    frflags a1
 ; CHECKIZFHMIN-NEXT:    flt.h a0, fa0, fa1
 ; CHECKIZFHMIN-NEXT:    fsflags a1
 ; CHECKIZFHMIN-NEXT:    feq.h zero, fa0, fa1
 ; CHECKIZFHMIN-NEXT:    ret
+;
+; CHECKIZHINXMIN-LABEL: fcmp_olt:
+; CHECKIZHINXMIN:       # %bb.0:
+; CHECKIZHINXMIN-NEXT:    fcvt.s.h a1, a1
+; CHECKIZHINXMIN-NEXT:    fcvt.s.h a2, a0
+; CHECKIZHINXMIN-NEXT:    csrr a3, fflags
+; CHECKIZHINXMIN-NEXT:    flt.s a0, a2, a1
+; CHECKIZHINXMIN-NEXT:    csrw fflags, a3
+; CHECKIZHINXMIN-NEXT:    feq.s zero, a2, a1
+; CHECKIZHINXMIN-NEXT:    ret
   %1 = call i1 @llvm.experimental.constrained.fcmp.f16(half %a, half %b, metadata !"olt", metadata !"fpexcept.strict") strictfp
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmp_ole(half %a, half %b) nounwind strictfp {
 ; CHECK-LABEL: fcmp_ole:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    frflags a1
 ; CHECK-NEXT:    fle.h a0, fa0, fa1
 ; CHECK-NEXT:    fsflags a1
 ; CHECK-NEXT:    feq.h zero, fa0, fa1
 ; CHECK-NEXT:    ret
 ;
+; CHECKIZHINX-LABEL: fcmp_ole:
+; CHECKIZHINX:       # %bb.0:
+; CHECKIZHINX-NEXT:    csrr a3, fflags
+; CHECKIZHINX-NEXT:    fle.h a2, a0, a1
+; CHECKIZHINX-NEXT:    csrw fflags, a3
+; CHECKIZHINX-NEXT:    feq.h zero, a0, a1
+; CHECKIZHINX-NEXT:    mv a0, a2
+; CHECKIZHINX-NEXT:    ret
+;
 ; CHECKIZFHMIN-LABEL: fcmp_ole:
 ; CHECKIZFHMIN:       # %bb.0:
 ; CHECKIZFHMIN-NEXT:    frflags a1
 ; CHECKIZFHMIN-NEXT:    fle.h a0, fa0, fa1
 ; CHECKIZFHMIN-NEXT:    fsflags a1
 ; CHECKIZFHMIN-NEXT:    feq.h zero, fa0, fa1
 ; CHECKIZFHMIN-NEXT:    ret
+;
+; CHECKIZHINXMIN-LABEL: fcmp_ole:
+; CHECKIZHINXMIN:       # %bb.0:
+; CHECKIZHINXMIN-NEXT:    fcvt.s.h a1, a1
+; CHECKIZHINXMIN-NEXT:    fcvt.s.h a2, a0
+; CHECKIZHINXMIN-NEXT:    csrr a3, fflags
+; CHECKIZHINXMIN-NEXT:    fle.s a0, a2, a1
+; CHECKIZHINXMIN-NEXT:    csrw fflags, a3
+; CHECKIZHINXMIN-NEXT:    feq.s zero, a2, a1
+; CHECKIZHINXMIN-NEXT:    ret
   %1 = call i1 @llvm.experimental.constrained.fcmp.f16(half %a, half %b, metadata !"ole", metadata !"fpexcept.strict") strictfp
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 ; FIXME: We only need one frflags before the two flts and one fsflags after the
 ; two flts.
 define i32 @fcmp_one(half %a, half %b) nounwind strictfp {
 ; CHECK-LABEL: fcmp_one:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    frflags a0
 ; CHECK-NEXT:    flt.h a1, fa0, fa1
 ; CHECK-NEXT:    fsflags a0
 ; CHECK-NEXT:    feq.h zero, fa0, fa1
 ; CHECK-NEXT:    frflags a0
 ; CHECK-NEXT:    flt.h a2, fa1, fa0
 ; CHECK-NEXT:    fsflags a0
 ; CHECK-NEXT:    or a0, a2, a1
 ; CHECK-NEXT:    feq.h zero, fa1, fa0
 ; CHECK-NEXT:    ret
 ;
+; CHECKIZHINX-LABEL: fcmp_one:
+; CHECKIZHINX:       # %bb.0:
+; CHECKIZHINX-NEXT:    csrr a2, fflags
+; CHECKIZHINX-NEXT:    flt.h a3, a0, a1
+; CHECKIZHINX-NEXT:    csrw fflags, a2
+; CHECKIZHINX-NEXT:    feq.h zero, a0, a1
+; CHECKIZHINX-NEXT:    csrr a2, fflags
+; CHECKIZHINX-NEXT:    flt.h a4, a1, a0
+; CHECKIZHINX-NEXT:    csrw fflags, a2
+; CHECKIZHINX-NEXT:    or a2, a4, a3
+; CHECKIZHINX-NEXT:    feq.h zero, a1, a0
+; CHECKIZHINX-NEXT:    mv a0, a2
+; CHECKIZHINX-NEXT:    ret
+;
 ; CHECKIZFHMIN-LABEL: fcmp_one:
 ; CHECKIZFHMIN:       # %bb.0:
 ; CHECKIZFHMIN-NEXT:    frflags a0
 ; CHECKIZFHMIN-NEXT:    flt.h a1, fa0, fa1
 ; CHECKIZFHMIN-NEXT:    fsflags a0
 ; CHECKIZFHMIN-NEXT:    feq.h zero, fa0, fa1
 ; CHECKIZFHMIN-NEXT:    frflags a0
 ; CHECKIZFHMIN-NEXT:    flt.h a2, fa1, fa0
 ; CHECKIZFHMIN-NEXT:    fsflags a0
 ; CHECKIZFHMIN-NEXT:    or a0, a2, a1
 ; CHECKIZFHMIN-NEXT:    feq.h zero, fa1, fa0
 ; CHECKIZFHMIN-NEXT:    ret
+;
+; CHECKIZHINXMIN-LABEL: fcmp_one:
+; CHECKIZHINXMIN:       # %bb.0:
+; CHECKIZHINXMIN-NEXT:    fcvt.s.h a1, a1
+; CHECKIZHINXMIN-NEXT:    fcvt.s.h a2, a0
+; CHECKIZHINXMIN-NEXT:    csrr a0, fflags
+; CHECKIZHINXMIN-NEXT:    flt.s a3, a2, a1
+; CHECKIZHINXMIN-NEXT:    csrw fflags, a0
+; CHECKIZHINXMIN-NEXT:    feq.s zero, a2, a1
+; CHECKIZHINXMIN-NEXT:    csrr a0, fflags
+; CHECKIZHINXMIN-NEXT:    flt.s a4, a1, a2
+; CHECKIZHINXMIN-NEXT:    csrw fflags, a0
+; CHECKIZHINXMIN-NEXT:    or a0, a4, a3
+; CHECKIZHINXMIN-NEXT:    feq.s zero, a1, a2
+; CHECKIZHINXMIN-NEXT:    ret
   %1 = call i1 @llvm.experimental.constrained.fcmp.f16(half %a, half %b, metadata !"one", metadata !"fpexcept.strict") strictfp
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmp_ord(half %a, half %b) nounwind strictfp {
 ; CHECK-LABEL: fcmp_ord:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    feq.h a0, fa1, fa1
 ; CHECK-NEXT:    feq.h a1, fa0, fa0
 ; CHECK-NEXT:    and a0, a1, a0
 ; CHECK-NEXT:    ret
 ;
+; CHECKIZHINX-LABEL: fcmp_ord:
+; CHECKIZHINX:       # %bb.0:
+; CHECKIZHINX-NEXT:    feq.h a1, a1, a1
+; CHECKIZHINX-NEXT:    feq.h a0, a0, a0
+; CHECKIZHINX-NEXT:    and a0, a0, a1
+; CHECKIZHINX-NEXT:    ret
+;
 ; CHECKIZFHMIN-LABEL: fcmp_ord:
 ; CHECKIZFHMIN:       # %bb.0:
 ; CHECKIZFHMIN-NEXT:    feq.h a0, fa1, fa1
 ; CHECKIZFHMIN-NEXT:    feq.h a1, fa0, fa0
 ; CHECKIZFHMIN-NEXT:    and a0, a1, a0
 ; CHECKIZFHMIN-NEXT:    ret
+;
+; CHECKIZHINXMIN-LABEL: fcmp_ord:
+; CHECKIZHINXMIN:       # %bb.0:
+; CHECKIZHINXMIN-NEXT:    fcvt.s.h a1, a1
+; CHECKIZHINXMIN-NEXT:    feq.s a1, a1, a1
+; CHECKIZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECKIZHINXMIN-NEXT:    feq.s a0, a0, a0
+; CHECKIZHINXMIN-NEXT:    and a0, a0, a1
+; CHECKIZHINXMIN-NEXT:    ret
   %1 = call i1 @llvm.experimental.constrained.fcmp.f16(half %a, half %b, metadata !"ord", metadata !"fpexcept.strict") strictfp
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 ; FIXME: We only need one frflags before the two flts and one fsflags after the
 ; two flts.
 define i32 @fcmp_ueq(half %a, half %b) nounwind strictfp {
 ; CHECK-LABEL: fcmp_ueq:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    frflags a0
 ; CHECK-NEXT:    flt.h a1, fa0, fa1
 ; CHECK-NEXT:    fsflags a0
 ; CHECK-NEXT:    feq.h zero, fa0, fa1
 ; CHECK-NEXT:    frflags a0
 ; CHECK-NEXT:    flt.h a2, fa1, fa0
 ; CHECK-NEXT:    fsflags a0
 ; CHECK-NEXT:    or a1, a2, a1
 ; CHECK-NEXT:    xori a0, a1, 1
 ; CHECK-NEXT:    feq.h zero, fa1, fa0
 ; CHECK-NEXT:    ret
 ;
+; CHECKIZHINX-LABEL: fcmp_ueq:
+; CHECKIZHINX:       # %bb.0:
+; CHECKIZHINX-NEXT:    csrr a2, fflags
+; CHECKIZHINX-NEXT:    flt.h a3, a0, a1
+; CHECKIZHINX-NEXT:    csrw fflags, a2
+; CHECKIZHINX-NEXT:    feq.h zero, a0, a1
+; CHECKIZHINX-NEXT:    csrr a2, fflags
+; CHECKIZHINX-NEXT:    flt.h a4, a1, a0
+; CHECKIZHINX-NEXT:    csrw fflags, a2
+; CHECKIZHINX-NEXT:    or a3, a4, a3
+; CHECKIZHINX-NEXT:    xori a2, a3, 1
+; CHECKIZHINX-NEXT:    feq.h zero, a1, a0
+; CHECKIZHINX-NEXT:    mv a0, a2
+; CHECKIZHINX-NEXT:    ret
+;
 ; CHECKIZFHMIN-LABEL: fcmp_ueq:
 ; CHECKIZFHMIN:       # %bb.0:
 ; CHECKIZFHMIN-NEXT:    frflags a0
 ; CHECKIZFHMIN-NEXT:    flt.h a1, fa0, fa1
 ; CHECKIZFHMIN-NEXT:    fsflags a0
 ; CHECKIZFHMIN-NEXT:    feq.h zero, fa0, fa1
 ; CHECKIZFHMIN-NEXT:    frflags a0
 ; CHECKIZFHMIN-NEXT:    flt.h a2, fa1, fa0
 ; CHECKIZFHMIN-NEXT:    fsflags a0
 ; CHECKIZFHMIN-NEXT:    or a1, a2, a1
 ; CHECKIZFHMIN-NEXT:    xori a0, a1, 1
 ; CHECKIZFHMIN-NEXT:    feq.h zero, fa1, fa0
 ; CHECKIZFHMIN-NEXT:    ret
+;
+; CHECKIZHINXMIN-LABEL: fcmp_ueq:
+; CHECKIZHINXMIN:       # %bb.0:
+; CHECKIZHINXMIN-NEXT:    fcvt.s.h a1, a1
+; CHECKIZHINXMIN-NEXT:    fcvt.s.h a2, a0
+; CHECKIZHINXMIN-NEXT:    csrr a0, fflags
+; CHECKIZHINXMIN-NEXT:    flt.s a3, a2, a1
+; CHECKIZHINXMIN-NEXT:    csrw fflags, a0
+; CHECKIZHINXMIN-NEXT:    feq.s zero, a2, a1
+; CHECKIZHINXMIN-NEXT:    csrr a0, fflags
+; CHECKIZHINXMIN-NEXT:    flt.s a4, a1, a2
+; CHECKIZHINXMIN-NEXT:    csrw fflags, a0
+; CHECKIZHINXMIN-NEXT:    or a3, a4, a3
+; CHECKIZHINXMIN-NEXT:    xori a0, a3, 1
+; CHECKIZHINXMIN-NEXT:    feq.s zero, a1, a2
+; CHECKIZHINXMIN-NEXT:    ret
   %1 = call i1 @llvm.experimental.constrained.fcmp.f16(half %a, half %b, metadata !"ueq", metadata !"fpexcept.strict") strictfp
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmp_ugt(half %a, half %b) nounwind strictfp {
 ; CHECK-LABEL: fcmp_ugt:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    frflags a0
 ; CHECK-NEXT:    fle.h a1, fa0, fa1
 ; CHECK-NEXT:    fsflags a0
 ; CHECK-NEXT:    xori a0, a1, 1
 ; CHECK-NEXT:    feq.h zero, fa0, fa1
 ; CHECK-NEXT:    ret
 ;
+; CHECKIZHINX-LABEL: fcmp_ugt:
+; CHECKIZHINX:       # %bb.0:
+; CHECKIZHINX-NEXT:    csrr a2, fflags
+; CHECKIZHINX-NEXT:    fle.h a3, a0, a1
+; CHECKIZHINX-NEXT:    csrw fflags, a2
+; CHECKIZHINX-NEXT:    xori a2, a3, 1
+; CHECKIZHINX-NEXT:    feq.h zero, a0, a1
+; CHECKIZHINX-NEXT:    mv a0, a2
+; CHECKIZHINX-NEXT:    ret
+;
 ; CHECKIZFHMIN-LABEL: fcmp_ugt:
 ; CHECKIZFHMIN:       # %bb.0:
 ; CHECKIZFHMIN-NEXT:    frflags a0
 ; CHECKIZFHMIN-NEXT:    fle.h a1, fa0, fa1
 ; CHECKIZFHMIN-NEXT:    fsflags a0
 ; CHECKIZFHMIN-NEXT:    xori a0, a1, 1
 ; CHECKIZFHMIN-NEXT:    feq.h zero, fa0, fa1
 ; CHECKIZFHMIN-NEXT:    ret
+;
+; CHECKIZHINXMIN-LABEL: fcmp_ugt:
+; CHECKIZHINXMIN:       # %bb.0:
+; CHECKIZHINXMIN-NEXT:    fcvt.s.h a1, a1
+; CHECKIZHINXMIN-NEXT:    fcvt.s.h a2, a0
+; CHECKIZHINXMIN-NEXT:    csrr a0, fflags
+; CHECKIZHINXMIN-NEXT:    fle.s a3, a2, a1
+; CHECKIZHINXMIN-NEXT:    csrw fflags, a0
+; CHECKIZHINXMIN-NEXT:    xori a0, a3, 1
+; CHECKIZHINXMIN-NEXT:    feq.s zero, a2, a1
+; CHECKIZHINXMIN-NEXT:    ret
   %1 = call i1 @llvm.experimental.constrained.fcmp.f16(half %a, half %b, metadata !"ugt", metadata !"fpexcept.strict") strictfp
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmp_uge(half %a, half %b) nounwind strictfp {
 ; CHECK-LABEL: fcmp_uge:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    frflags a0
 ; CHECK-NEXT:    flt.h a1, fa0, fa1
 ; CHECK-NEXT:    fsflags a0
 ; CHECK-NEXT:    xori a0, a1, 1
 ; CHECK-NEXT:    feq.h zero, fa0, fa1
 ; CHECK-NEXT:    ret
 ;
+; CHECKIZHINX-LABEL: fcmp_uge:
+; CHECKIZHINX:       # %bb.0:
+; CHECKIZHINX-NEXT:    csrr a2, fflags
+; CHECKIZHINX-NEXT:    flt.h a3, a0, a1
+; CHECKIZHINX-NEXT:    csrw fflags, a2
+; CHECKIZHINX-NEXT:    xori a2, a3, 1
+; CHECKIZHINX-NEXT:    feq.h zero, a0, a1
+; CHECKIZHINX-NEXT:    mv a0, a2
+; CHECKIZHINX-NEXT:    ret
+;
 ; CHECKIZFHMIN-LABEL: fcmp_uge:
 ; CHECKIZFHMIN:       # %bb.0:
 ; CHECKIZFHMIN-NEXT:    frflags a0
 ; CHECKIZFHMIN-NEXT:    flt.h a1, fa0, fa1
 ; CHECKIZFHMIN-NEXT:    fsflags a0
 ; CHECKIZFHMIN-NEXT:    xori a0, a1, 1
 ; CHECKIZFHMIN-NEXT:    feq.h zero, fa0, fa1
 ; CHECKIZFHMIN-NEXT:    ret
+;
+; CHECKIZHINXMIN-LABEL: fcmp_uge:
+; CHECKIZHINXMIN:       # %bb.0:
+; CHECKIZHINXMIN-NEXT:    fcvt.s.h a1, a1
+; CHECKIZHINXMIN-NEXT:    fcvt.s.h a2, a0
+; CHECKIZHINXMIN-NEXT:    csrr a0, fflags
+; CHECKIZHINXMIN-NEXT:    flt.s a3, a2, a1
+; CHECKIZHINXMIN-NEXT:    csrw fflags, a0
+; CHECKIZHINXMIN-NEXT:    xori a0, a3, 1
+; CHECKIZHINXMIN-NEXT:    feq.s zero, a2, a1
+; CHECKIZHINXMIN-NEXT:    ret
   %1 = call i1 @llvm.experimental.constrained.fcmp.f16(half %a, half %b, metadata !"uge", metadata !"fpexcept.strict") strictfp
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmp_ult(half %a, half %b) nounwind strictfp {
 ; CHECK-LABEL: fcmp_ult:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    frflags a0
 ; CHECK-NEXT:    fle.h a1, fa1, fa0
 ; CHECK-NEXT:    fsflags a0
 ; CHECK-NEXT:    xori a0, a1, 1
 ; CHECK-NEXT:    feq.h zero, fa1, fa0
 ; CHECK-NEXT:    ret
 ;
+; CHECKIZHINX-LABEL: fcmp_ult:
+; CHECKIZHINX:       # %bb.0:
+; CHECKIZHINX-NEXT:    csrr a2, fflags
+; CHECKIZHINX-NEXT:    fle.h a3, a1, a0
+; CHECKIZHINX-NEXT:    csrw fflags, a2
+; CHECKIZHINX-NEXT:    xori a2, a3, 1
+; CHECKIZHINX-NEXT:    feq.h zero, a1, a0
+; CHECKIZHINX-NEXT:    mv a0, a2
+; CHECKIZHINX-NEXT:    ret
+;
 ; CHECKIZFHMIN-LABEL: fcmp_ult:
 ; CHECKIZFHMIN:       # %bb.0:
 ; CHECKIZFHMIN-NEXT:    frflags a0
 ; CHECKIZFHMIN-NEXT:    fle.h a1, fa1, fa0
 ; CHECKIZFHMIN-NEXT:    fsflags a0
 ; CHECKIZFHMIN-NEXT:    xori a0, a1, 1
 ; CHECKIZFHMIN-NEXT:    feq.h zero, fa1, fa0
 ; CHECKIZFHMIN-NEXT:    ret
+;
+; CHECKIZHINXMIN-LABEL: fcmp_ult:
+; CHECKIZHINXMIN:       # %bb.0:
+; CHECKIZHINXMIN-NEXT:    fcvt.s.h a2, a0
+; CHECKIZHINXMIN-NEXT:    fcvt.s.h a1, a1
+; CHECKIZHINXMIN-NEXT:    csrr a0, fflags
+; CHECKIZHINXMIN-NEXT:    fle.s a3, a1, a2
+; CHECKIZHINXMIN-NEXT:    csrw fflags, a0
+; CHECKIZHINXMIN-NEXT:    xori a0, a3, 1
+; CHECKIZHINXMIN-NEXT:    feq.s zero, a1, a2
+; CHECKIZHINXMIN-NEXT:    ret
   %1 = call i1 @llvm.experimental.constrained.fcmp.f16(half %a, half %b, metadata !"ult", metadata !"fpexcept.strict") strictfp
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmp_ule(half %a, half %b) nounwind strictfp {
 ; CHECK-LABEL: fcmp_ule:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    frflags a0
 ; CHECK-NEXT:    flt.h a1, fa1, fa0
 ; CHECK-NEXT:    fsflags a0
 ; CHECK-NEXT:    xori a0, a1, 1
 ; CHECK-NEXT:    feq.h zero, fa1, fa0
 ; CHECK-NEXT:    ret
 ;
+; CHECKIZHINX-LABEL: fcmp_ule:
+; CHECKIZHINX:       # %bb.0:
+; CHECKIZHINX-NEXT:    csrr a2, fflags
+; CHECKIZHINX-NEXT:    flt.h a3, a1, a0
+; CHECKIZHINX-NEXT:    csrw fflags, a2
+; CHECKIZHINX-NEXT:    xori a2, a3, 1
+; CHECKIZHINX-NEXT:    feq.h zero, a1, a0
+; CHECKIZHINX-NEXT:    mv a0, a2
+; CHECKIZHINX-NEXT:    ret
+;
 ; CHECKIZFHMIN-LABEL: fcmp_ule:
 ; CHECKIZFHMIN:       # %bb.0:
 ; CHECKIZFHMIN-NEXT:    frflags a0
 ; CHECKIZFHMIN-NEXT:    flt.h a1, fa1, fa0
 ; CHECKIZFHMIN-NEXT:    fsflags a0
 ; CHECKIZFHMIN-NEXT:    xori a0, a1, 1
 ; CHECKIZFHMIN-NEXT:    feq.h zero, fa1, fa0
 ; CHECKIZFHMIN-NEXT:    ret
+;
+; CHECKIZHINXMIN-LABEL: fcmp_ule:
+; CHECKIZHINXMIN:       # %bb.0:
+; CHECKIZHINXMIN-NEXT:    fcvt.s.h a2, a0
+; CHECKIZHINXMIN-NEXT:    fcvt.s.h a1, a1
+; CHECKIZHINXMIN-NEXT:    csrr a0, fflags
+; CHECKIZHINXMIN-NEXT:    flt.s a3, a1, a2
+; CHECKIZHINXMIN-NEXT:    csrw fflags, a0
+; CHECKIZHINXMIN-NEXT:    xori a0, a3, 1
+; CHECKIZHINXMIN-NEXT:    feq.s zero, a1, a2
+; CHECKIZHINXMIN-NEXT:    ret
   %1 = call i1 @llvm.experimental.constrained.fcmp.f16(half %a, half %b, metadata !"ule", metadata !"fpexcept.strict") strictfp
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmp_une(half %a, half %b) nounwind strictfp {
 ; CHECK-LABEL: fcmp_une:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    feq.h a0, fa0, fa1
 ; CHECK-NEXT:    xori a0, a0, 1
 ; CHECK-NEXT:    ret
 ;
+; CHECKIZHINX-LABEL: fcmp_une:
+; CHECKIZHINX:       # %bb.0:
+; CHECKIZHINX-NEXT:    feq.h a0, a0, a1
+; CHECKIZHINX-NEXT:    xori a0, a0, 1
+; CHECKIZHINX-NEXT:    ret
+;
 ; CHECKIZFHMIN-LABEL: fcmp_une:
 ; CHECKIZFHMIN:       # %bb.0:
 ; CHECKIZFHMIN-NEXT:    feq.h a0, fa0, fa1
 ; CHECKIZFHMIN-NEXT:    xori a0, a0, 1
 ; CHECKIZFHMIN-NEXT:    ret
+;
+; CHECKIZHINXMIN-LABEL: fcmp_une:
+; CHECKIZHINXMIN:       # %bb.0:
+; CHECKIZHINXMIN-NEXT:    fcvt.s.h a1, a1
+; CHECKIZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECKIZHINXMIN-NEXT:    feq.s a0, a0, a1
+; CHECKIZHINXMIN-NEXT:    xori a0, a0, 1
+; CHECKIZHINXMIN-NEXT:    ret
   %1 = call i1 @llvm.experimental.constrained.fcmp.f16(half %a, half %b, metadata !"une", metadata !"fpexcept.strict") strictfp
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmp_uno(half %a, half %b) nounwind strictfp {
 ; CHECK-LABEL: fcmp_uno:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    feq.h a0, fa1, fa1
 ; CHECK-NEXT:    feq.h a1, fa0, fa0
 ; CHECK-NEXT:    and a0, a1, a0
 ; CHECK-NEXT:    xori a0, a0, 1
 ; CHECK-NEXT:    ret
 ;
+; CHECKIZHINX-LABEL: fcmp_uno:
+; CHECKIZHINX:       # %bb.0:
+; CHECKIZHINX-NEXT:    feq.h a1, a1, a1
+; CHECKIZHINX-NEXT:    feq.h a0, a0, a0
+; CHECKIZHINX-NEXT:    and a0, a0, a1
+; CHECKIZHINX-NEXT:    xori a0, a0, 1
+; CHECKIZHINX-NEXT:    ret
+;
 ; CHECKIZFHMIN-LABEL: fcmp_uno:
 ; CHECKIZFHMIN:       # %bb.0:
 ; CHECKIZFHMIN-NEXT:    feq.h a0, fa1, fa1
 ; CHECKIZFHMIN-NEXT:    feq.h a1, fa0, fa0
 ; CHECKIZFHMIN-NEXT:    and a0, a1, a0
 ; CHECKIZFHMIN-NEXT:    xori a0, a0, 1
 ; CHECKIZFHMIN-NEXT:    ret
+;
+; CHECKIZHINXMIN-LABEL: fcmp_uno:
+; CHECKIZHINXMIN:       # %bb.0:
+; CHECKIZHINXMIN-NEXT:    fcvt.s.h a1, a1
+; CHECKIZHINXMIN-NEXT:    feq.s a1, a1, a1
+; CHECKIZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECKIZHINXMIN-NEXT:    feq.s a0, a0, a0
+; CHECKIZHINXMIN-NEXT:    and a0, a0, a1
+; CHECKIZHINXMIN-NEXT:    xori a0, a0, 1
+; CHECKIZHINXMIN-NEXT:    ret
   %1 = call i1 @llvm.experimental.constrained.fcmp.f16(half %a, half %b, metadata !"uno", metadata !"fpexcept.strict") strictfp
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmps_oeq(half %a, half %b) nounwind strictfp {
 ; CHECK-LABEL: fcmps_oeq:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    fle.h a0, fa1, fa0
 ; CHECK-NEXT:    fle.h a1, fa0, fa1
 ; CHECK-NEXT:    and a0, a1, a0
 ; CHECK-NEXT:    ret
 ;
+; CHECKIZHINX-LABEL: fcmps_oeq:
+; CHECKIZHINX:       # %bb.0:
+; CHECKIZHINX-NEXT:    fle.h a2, a1, a0
+; CHECKIZHINX-NEXT:    fle.h a0, a0, a1
+; CHECKIZHINX-NEXT:    and a0, a0, a2
+; CHECKIZHINX-NEXT:    ret
+;
 ; CHECKIZFHMIN-LABEL: fcmps_oeq:
 ; CHECKIZFHMIN:       # %bb.0:
 ; CHECKIZFHMIN-NEXT:    fle.h a0, fa1, fa0
 ; CHECKIZFHMIN-NEXT:    fle.h a1, fa0, fa1
 ; CHECKIZFHMIN-NEXT:    and a0, a1, a0
 ; CHECKIZFHMIN-NEXT:    ret
+;
+; CHECKIZHINXMIN-LABEL: fcmps_oeq:
+; CHECKIZHINXMIN:       # %bb.0:
+; CHECKIZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECKIZHINXMIN-NEXT:    fcvt.s.h a1, a1
+; CHECKIZHINXMIN-NEXT:    fle.s a2, a1, a0
+; CHECKIZHINXMIN-NEXT:    fle.s a0, a0, a1
+; CHECKIZHINXMIN-NEXT:    and a0, a0, a2
+; CHECKIZHINXMIN-NEXT:    ret
   %1 = call i1 @llvm.experimental.constrained.fcmps.f16(half %a, half %b, metadata !"oeq", metadata !"fpexcept.strict") strictfp
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 declare i1 @llvm.experimental.constrained.fcmps.f16(half, half, metadata, metadata)
 
 define i32 @fcmps_ogt(half %a, half %b) nounwind strictfp {
 ; CHECK-LABEL: fcmps_ogt:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    flt.h a0, fa1, fa0
 ; CHECK-NEXT:    ret
 ;
+; CHECKIZHINX-LABEL: fcmps_ogt:
+; CHECKIZHINX:       # %bb.0:
+; CHECKIZHINX-NEXT:    flt.h a0, a1, a0
+; CHECKIZHINX-NEXT:    ret
+;
 ; CHECKIZFHMIN-LABEL: fcmps_ogt:
 ; CHECKIZFHMIN:       # %bb.0:
 ; CHECKIZFHMIN-NEXT:    flt.h a0, fa1, fa0
 ; CHECKIZFHMIN-NEXT:    ret
+;
+; CHECKIZHINXMIN-LABEL: fcmps_ogt:
+; CHECKIZHINXMIN:       # %bb.0:
+; CHECKIZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECKIZHINXMIN-NEXT:    fcvt.s.h a1, a1
+; CHECKIZHINXMIN-NEXT:    flt.s a0, a1, a0
+; CHECKIZHINXMIN-NEXT:    ret
   %1 = call i1 @llvm.experimental.constrained.fcmps.f16(half %a, half %b, metadata !"ogt", metadata !"fpexcept.strict") strictfp
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmps_oge(half %a, half %b) nounwind strictfp {
 ; CHECK-LABEL: fcmps_oge:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    fle.h a0, fa1, fa0
 ; CHECK-NEXT:    ret
 ;
+; CHECKIZHINX-LABEL: fcmps_oge:
+; CHECKIZHINX:       # %bb.0:
+; CHECKIZHINX-NEXT:    fle.h a0, a1, a0
+; CHECKIZHINX-NEXT:    ret
+;
 ; CHECKIZFHMIN-LABEL: fcmps_oge:
 ; CHECKIZFHMIN:       # %bb.0:
 ; CHECKIZFHMIN-NEXT:    fle.h a0, fa1, fa0
 ; CHECKIZFHMIN-NEXT:    ret
+;
+; CHECKIZHINXMIN-LABEL: fcmps_oge:
+; CHECKIZHINXMIN:       # %bb.0:
+; CHECKIZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECKIZHINXMIN-NEXT:    fcvt.s.h a1, a1
+; CHECKIZHINXMIN-NEXT:    fle.s a0, a1, a0
+; CHECKIZHINXMIN-NEXT:    ret
   %1 = call i1 @llvm.experimental.constrained.fcmps.f16(half %a, half %b, metadata !"oge", metadata !"fpexcept.strict") strictfp
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmps_olt(half %a, half %b) nounwind strictfp {
 ; CHECK-LABEL: fcmps_olt:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    flt.h a0, fa0, fa1
 ; CHECK-NEXT:    ret
 ;
+; CHECKIZHINX-LABEL: fcmps_olt:
+; CHECKIZHINX:       # %bb.0:
+; CHECKIZHINX-NEXT:    flt.h a0, a0, a1
+; CHECKIZHINX-NEXT:    ret
+;
 ; CHECKIZFHMIN-LABEL: fcmps_olt:
 ; CHECKIZFHMIN:       # %bb.0:
 ; CHECKIZFHMIN-NEXT:    flt.h a0, fa0, fa1
 ; CHECKIZFHMIN-NEXT:    ret
+;
+; CHECKIZHINXMIN-LABEL: fcmps_olt:
+; CHECKIZHINXMIN:       # %bb.0:
+; CHECKIZHINXMIN-NEXT:    fcvt.s.h a1, a1
+; CHECKIZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECKIZHINXMIN-NEXT:    flt.s a0, a0, a1
+; CHECKIZHINXMIN-NEXT:    ret
   %1 = call i1 @llvm.experimental.constrained.fcmps.f16(half %a, half %b, metadata !"olt", metadata !"fpexcept.strict") strictfp
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmps_ole(half %a, half %b) nounwind strictfp {
 ; CHECK-LABEL: fcmps_ole:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    fle.h a0, fa0, fa1
 ; CHECK-NEXT:    ret
 ;
+; CHECKIZHINX-LABEL: fcmps_ole:
+; CHECKIZHINX:       # %bb.0:
+; CHECKIZHINX-NEXT:    fle.h a0, a0, a1
+; CHECKIZHINX-NEXT:    ret
+;
 ; CHECKIZFHMIN-LABEL: fcmps_ole:
 ; CHECKIZFHMIN:       # %bb.0:
 ; CHECKIZFHMIN-NEXT:    fle.h a0, fa0, fa1
 ; CHECKIZFHMIN-NEXT:    ret
+;
+; CHECKIZHINXMIN-LABEL: fcmps_ole:
+; CHECKIZHINXMIN:       # %bb.0:
+; CHECKIZHINXMIN-NEXT:    fcvt.s.h a1, a1
+; CHECKIZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECKIZHINXMIN-NEXT:    fle.s a0, a0, a1
+; CHECKIZHINXMIN-NEXT:    ret
   %1 = call i1 @llvm.experimental.constrained.fcmps.f16(half %a, half %b, metadata !"ole", metadata !"fpexcept.strict") strictfp
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmps_one(half %a, half %b) nounwind strictfp {
 ; CHECK-LABEL: fcmps_one:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    flt.h a0, fa0, fa1
 ; CHECK-NEXT:    flt.h a1, fa1, fa0
 ; CHECK-NEXT:    or a0, a1, a0
 ; CHECK-NEXT:    ret
 ;
+; CHECKIZHINX-LABEL: fcmps_one:
+; CHECKIZHINX:       # %bb.0:
+; CHECKIZHINX-NEXT:    flt.h a2, a0, a1
+; CHECKIZHINX-NEXT:    flt.h a0, a1, a0
+; CHECKIZHINX-NEXT:    or a0, a0, a2
+; CHECKIZHINX-NEXT:    ret
+;
 ; CHECKIZFHMIN-LABEL: fcmps_one:
 ; CHECKIZFHMIN:       # %bb.0:
 ; CHECKIZFHMIN-NEXT:    flt.h a0, fa0, fa1
 ; CHECKIZFHMIN-NEXT:    flt.h a1, fa1, fa0
 ; CHECKIZFHMIN-NEXT:    or a0, a1, a0
 ; CHECKIZFHMIN-NEXT:    ret
+;
+; CHECKIZHINXMIN-LABEL: fcmps_one:
+; CHECKIZHINXMIN:       # %bb.0:
+; CHECKIZHINXMIN-NEXT:    fcvt.s.h a1, a1
+; CHECKIZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECKIZHINXMIN-NEXT:    flt.s a2, a0, a1
+; CHECKIZHINXMIN-NEXT:    flt.s a0, a1, a0
+; CHECKIZHINXMIN-NEXT:    or a0, a0, a2
+; CHECKIZHINXMIN-NEXT:    ret
   %1 = call i1 @llvm.experimental.constrained.fcmps.f16(half %a, half %b, metadata !"one", metadata !"fpexcept.strict") strictfp
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmps_ord(half %a, half %b) nounwind strictfp {
 ; CHECK-LABEL: fcmps_ord:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    fle.h a0, fa1, fa1
 ; CHECK-NEXT:    fle.h a1, fa0, fa0
 ; CHECK-NEXT:    and a0, a1, a0
 ; CHECK-NEXT:    ret
 ;
+; CHECKIZHINX-LABEL: fcmps_ord:
+; CHECKIZHINX:       # %bb.0:
+; CHECKIZHINX-NEXT:    fle.h a1, a1, a1
+; CHECKIZHINX-NEXT:    fle.h a0, a0, a0
+; CHECKIZHINX-NEXT:    and a0, a0, a1
+; CHECKIZHINX-NEXT:    ret
+;
 ; CHECKIZFHMIN-LABEL: fcmps_ord:
 ; CHECKIZFHMIN:       # %bb.0:
 ; CHECKIZFHMIN-NEXT:    fle.h a0, fa1, fa1
 ; CHECKIZFHMIN-NEXT:    fle.h a1, fa0, fa0
 ; CHECKIZFHMIN-NEXT:    and a0, a1, a0
 ; CHECKIZFHMIN-NEXT:    ret
+;
+; CHECKIZHINXMIN-LABEL: fcmps_ord:
+; CHECKIZHINXMIN:       # %bb.0:
+; CHECKIZHINXMIN-NEXT:    fcvt.s.h a1, a1
+; CHECKIZHINXMIN-NEXT:    fle.s a1, a1, a1
+; CHECKIZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECKIZHINXMIN-NEXT:    fle.s a0, a0, a0
+; CHECKIZHINXMIN-NEXT:    and a0, a0, a1
+; CHECKIZHINXMIN-NEXT:    ret
   %1 = call i1 @llvm.experimental.constrained.fcmps.f16(half %a, half %b, metadata !"ord", metadata !"fpexcept.strict") strictfp
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmps_ueq(half %a, half %b) nounwind strictfp {
 ; CHECK-LABEL: fcmps_ueq:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    flt.h a0, fa0, fa1
 ; CHECK-NEXT:    flt.h a1, fa1, fa0
 ; CHECK-NEXT:    or a0, a1, a0
 ; CHECK-NEXT:    xori a0, a0, 1
 ; CHECK-NEXT:    ret
 ;
+; CHECKIZHINX-LABEL: fcmps_ueq:
+; CHECKIZHINX:       # %bb.0:
+; CHECKIZHINX-NEXT:    flt.h a2, a0, a1
+; CHECKIZHINX-NEXT:    flt.h a0, a1, a0
+; CHECKIZHINX-NEXT:    or a0, a0, a2
+; CHECKIZHINX-NEXT:    xori a0, a0, 1
+; CHECKIZHINX-NEXT:    ret
+;
 ; CHECKIZFHMIN-LABEL: fcmps_ueq:
 ; CHECKIZFHMIN:       # %bb.0:
 ; CHECKIZFHMIN-NEXT:    flt.h a0, fa0, fa1
 ; CHECKIZFHMIN-NEXT:    flt.h a1, fa1, fa0
 ; CHECKIZFHMIN-NEXT:    or a0, a1, a0
 ; CHECKIZFHMIN-NEXT:    xori a0, a0, 1
 ; CHECKIZFHMIN-NEXT:    ret
+;
+; CHECKIZHINXMIN-LABEL: fcmps_ueq:
+; CHECKIZHINXMIN:       # %bb.0:
+; CHECKIZHINXMIN-NEXT:    fcvt.s.h a1, a1
+; CHECKIZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECKIZHINXMIN-NEXT:    flt.s a2, a0, a1
+; CHECKIZHINXMIN-NEXT:    flt.s a0, a1, a0
+; CHECKIZHINXMIN-NEXT:    or a0, a0, a2
+; CHECKIZHINXMIN-NEXT:    xori a0, a0, 1
+; CHECKIZHINXMIN-NEXT:    ret
   %1 = call i1 @llvm.experimental.constrained.fcmps.f16(half %a, half %b, metadata !"ueq", metadata !"fpexcept.strict") strictfp
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmps_ugt(half %a, half %b) nounwind strictfp {
 ; CHECK-LABEL: fcmps_ugt:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    fle.h a0, fa0, fa1
 ; CHECK-NEXT:    xori a0, a0, 1
 ; CHECK-NEXT:    ret
 ;
+; CHECKIZHINX-LABEL: fcmps_ugt:
+; CHECKIZHINX:       # %bb.0:
+; CHECKIZHINX-NEXT:    fle.h a0, a0, a1
+; CHECKIZHINX-NEXT:    xori a0, a0, 1
+; CHECKIZHINX-NEXT:    ret
+;
 ; CHECKIZFHMIN-LABEL: fcmps_ugt:
 ; CHECKIZFHMIN:       # %bb.0:
 ; CHECKIZFHMIN-NEXT:    fle.h a0, fa0, fa1
 ; CHECKIZFHMIN-NEXT:    xori a0, a0, 1
 ; CHECKIZFHMIN-NEXT:    ret
+;
+; CHECKIZHINXMIN-LABEL: fcmps_ugt:
+; CHECKIZHINXMIN:       # %bb.0:
+; CHECKIZHINXMIN-NEXT:    fcvt.s.h a1, a1
+; CHECKIZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECKIZHINXMIN-NEXT:    fle.s a0, a0, a1
+; CHECKIZHINXMIN-NEXT:    xori a0, a0, 1
+; CHECKIZHINXMIN-NEXT:    ret
   %1 = call i1 @llvm.experimental.constrained.fcmps.f16(half %a, half %b, metadata !"ugt", metadata !"fpexcept.strict") strictfp
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmps_uge(half %a, half %b) nounwind strictfp {
 ; CHECK-LABEL: fcmps_uge:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    flt.h a0, fa0, fa1
 ; CHECK-NEXT:    xori a0, a0, 1
 ; CHECK-NEXT:    ret
 ;
+; CHECKIZHINX-LABEL: fcmps_uge:
+; CHECKIZHINX:       # %bb.0:
+; CHECKIZHINX-NEXT:    flt.h a0, a0, a1
+; CHECKIZHINX-NEXT:    xori a0, a0, 1
+; CHECKIZHINX-NEXT:    ret
+;
 ; CHECKIZFHMIN-LABEL: fcmps_uge:
 ; CHECKIZFHMIN:       # %bb.0:
 ; CHECKIZFHMIN-NEXT:    flt.h a0, fa0, fa1
 ; CHECKIZFHMIN-NEXT:    xori a0, a0, 1
 ; CHECKIZFHMIN-NEXT:    ret
+;
+; CHECKIZHINXMIN-LABEL: fcmps_uge:
+; CHECKIZHINXMIN:       # %bb.0:
+; CHECKIZHINXMIN-NEXT:    fcvt.s.h a1, a1
+; CHECKIZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECKIZHINXMIN-NEXT:    flt.s a0, a0, a1
+; CHECKIZHINXMIN-NEXT:    xori a0, a0, 1
+; CHECKIZHINXMIN-NEXT:    ret
   %1 = call i1 @llvm.experimental.constrained.fcmps.f16(half %a, half %b, metadata !"uge", metadata !"fpexcept.strict") strictfp
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmps_ult(half %a, half %b) nounwind strictfp {
 ; CHECK-LABEL: fcmps_ult:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    fle.h a0, fa1, fa0
 ; CHECK-NEXT:    xori a0, a0, 1
 ; CHECK-NEXT:    ret
 ;
+; CHECKIZHINX-LABEL: fcmps_ult:
+; CHECKIZHINX:       # %bb.0:
+; CHECKIZHINX-NEXT:    fle.h a0, a1, a0
+; CHECKIZHINX-NEXT:    xori a0, a0, 1
+; CHECKIZHINX-NEXT:    ret
+;
 ; CHECKIZFHMIN-LABEL: fcmps_ult:
 ; CHECKIZFHMIN:       # %bb.0:
 ; CHECKIZFHMIN-NEXT:    fle.h a0, fa1, fa0
 ; CHECKIZFHMIN-NEXT:    xori a0, a0, 1
 ; CHECKIZFHMIN-NEXT:    ret
+;
+; CHECKIZHINXMIN-LABEL: fcmps_ult:
+; CHECKIZHINXMIN:       # %bb.0:
+; CHECKIZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECKIZHINXMIN-NEXT:    fcvt.s.h a1, a1
+; CHECKIZHINXMIN-NEXT:    fle.s a0, a1, a0
+; CHECKIZHINXMIN-NEXT:    xori a0, a0, 1
+; CHECKIZHINXMIN-NEXT:    ret
   %1 = call i1 @llvm.experimental.constrained.fcmps.f16(half %a, half %b, metadata !"ult", metadata !"fpexcept.strict") strictfp
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmps_ule(half %a, half %b) nounwind strictfp {
 ; CHECK-LABEL: fcmps_ule:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    flt.h a0, fa1, fa0
 ; CHECK-NEXT:    xori a0, a0, 1
 ; CHECK-NEXT:    ret
 ;
+; CHECKIZHINX-LABEL: fcmps_ule:
+; CHECKIZHINX:       # %bb.0:
+; CHECKIZHINX-NEXT:    flt.h a0, a1, a0
+; CHECKIZHINX-NEXT:    xori a0, a0, 1
+; CHECKIZHINX-NEXT:    ret
+;
 ; CHECKIZFHMIN-LABEL: fcmps_ule:
 ; CHECKIZFHMIN:       # %bb.0:
 ; CHECKIZFHMIN-NEXT:    flt.h a0, fa1, fa0
 ; CHECKIZFHMIN-NEXT:    xori a0, a0, 1
 ; CHECKIZFHMIN-NEXT:    ret
+;
+; CHECKIZHINXMIN-LABEL: fcmps_ule:
+; CHECKIZHINXMIN:       # %bb.0:
+; CHECKIZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECKIZHINXMIN-NEXT:    fcvt.s.h a1, a1
+; CHECKIZHINXMIN-NEXT:    flt.s a0, a1, a0
+; CHECKIZHINXMIN-NEXT:    xori a0, a0, 1
+; CHECKIZHINXMIN-NEXT:    ret
   %1 = call i1 @llvm.experimental.constrained.fcmps.f16(half %a, half %b, metadata !"ule", metadata !"fpexcept.strict") strictfp
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmps_une(half %a, half %b) nounwind strictfp {
 ; CHECK-LABEL: fcmps_une:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    fle.h a0, fa1, fa0
 ; CHECK-NEXT:    fle.h a1, fa0, fa1
 ; CHECK-NEXT:    and a0, a1, a0
 ; CHECK-NEXT:    xori a0, a0, 1
 ; CHECK-NEXT:    ret
 ;
+; CHECKIZHINX-LABEL: fcmps_une:
+; CHECKIZHINX:       # %bb.0:
+; CHECKIZHINX-NEXT:    fle.h a2, a1, a0
+; CHECKIZHINX-NEXT:    fle.h a0, a0, a1
+; CHECKIZHINX-NEXT:    and a0, a0, a2
+; CHECKIZHINX-NEXT:    xori a0, a0, 1
+; CHECKIZHINX-NEXT:    ret
+;
 ; CHECKIZFHMIN-LABEL: fcmps_une:
 ; CHECKIZFHMIN:       # %bb.0:
 ; CHECKIZFHMIN-NEXT:    fle.h a0, fa1, fa0
 ; CHECKIZFHMIN-NEXT:    fle.h a1, fa0, fa1
 ; CHECKIZFHMIN-NEXT:    and a0, a1, a0
 ; CHECKIZFHMIN-NEXT:    xori a0, a0, 1
 ; CHECKIZFHMIN-NEXT:    ret
+;
+; CHECKIZHINXMIN-LABEL: fcmps_une:
+; CHECKIZHINXMIN:       # %bb.0:
+; CHECKIZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECKIZHINXMIN-NEXT:    fcvt.s.h a1, a1
+; CHECKIZHINXMIN-NEXT:    fle.s a2, a1, a0
+; CHECKIZHINXMIN-NEXT:    fle.s a0, a0, a1
+; CHECKIZHINXMIN-NEXT:    and a0, a0, a2
+; CHECKIZHINXMIN-NEXT:    xori a0, a0, 1
+; CHECKIZHINXMIN-NEXT:    ret
   %1 = call i1 @llvm.experimental.constrained.fcmps.f16(half %a, half %b, metadata !"une", metadata !"fpexcept.strict") strictfp
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmps_uno(half %a, half %b) nounwind strictfp {
 ; CHECK-LABEL: fcmps_uno:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    fle.h a0, fa1, fa1
 ; CHECK-NEXT:    fle.h a1, fa0, fa0
 ; CHECK-NEXT:    and a0, a1, a0
 ; CHECK-NEXT:    xori a0, a0, 1
 ; CHECK-NEXT:    ret
 ;
+; CHECKIZHINX-LABEL: fcmps_uno:
+; CHECKIZHINX:       # %bb.0:
+; CHECKIZHINX-NEXT:    fle.h a1, a1, a1
+; CHECKIZHINX-NEXT:    fle.h a0, a0, a0
+; CHECKIZHINX-NEXT:    and a0, a0, a1
+; CHECKIZHINX-NEXT:    xori a0, a0, 1
+; CHECKIZHINX-NEXT:    ret
+;
 ; CHECKIZFHMIN-LABEL: fcmps_uno:
 ; CHECKIZFHMIN:       # %bb.0:
 ; CHECKIZFHMIN-NEXT:    fle.h a0, fa1, fa1
 ; CHECKIZFHMIN-NEXT:    fle.h a1, fa0, fa0
 ; CHECKIZFHMIN-NEXT:    and a0, a1, a0
 ; CHECKIZFHMIN-NEXT:    xori a0, a0, 1
 ; CHECKIZFHMIN-NEXT:    ret
+;
+; CHECKIZHINXMIN-LABEL: fcmps_uno:
+; CHECKIZHINXMIN:       # %bb.0:
+; CHECKIZHINXMIN-NEXT:    fcvt.s.h a1, a1
+; CHECKIZHINXMIN-NEXT:    fle.s a1, a1, a1
+; CHECKIZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECKIZHINXMIN-NEXT:    fle.s a0, a0, a0
+; CHECKIZHINXMIN-NEXT:    and a0, a0, a1
+; CHECKIZHINXMIN-NEXT:    xori a0, a0, 1
+; CHECKIZHINXMIN-NEXT:    ret
   %1 = call i1 @llvm.experimental.constrained.fcmps.f16(half %a, half %b, metadata !"uno", metadata !"fpexcept.strict") strictfp
   %2 = zext i1 %1 to i32
   ret i32 %2
 }

llvm/test/CodeGen/RISCV/half-fcmp.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -mattr=+zfh -verify-machineinstrs \
 ; RUN:   -target-abi ilp32f < %s | FileCheck -check-prefix=CHECKIZFH %s
 ; RUN: llc -mtriple=riscv64 -mattr=+zfh -verify-machineinstrs \
 ; RUN:   -target-abi lp64f < %s | FileCheck -check-prefix=CHECKIZFH %s
+; RUN: llc -mtriple=riscv32 -mattr=+zhinx -verify-machineinstrs \
+; RUN:   -target-abi ilp32 < %s | FileCheck -check-prefix=CHECKIZHINX %s
+; RUN: llc -mtriple=riscv64 -mattr=+zhinx -verify-machineinstrs \
+; RUN:   -target-abi lp64 < %s | FileCheck -check-prefix=CHECKIZHINX %s
 ; RUN: llc -mtriple=riscv32 -mattr=+zfh -verify-machineinstrs \
 ; RUN:   < %s | FileCheck -check-prefix=RV32I %s
 ; RUN: llc -mtriple=riscv64 -mattr=+zfh -verify-machineinstrs \
 ; RUN:   < %s | FileCheck -check-prefix=RV64I %s
 ; RUN: llc -mtriple=riscv32 -mattr=+zfhmin -verify-machineinstrs \
 ; RUN:   -target-abi ilp32f < %s | FileCheck -check-prefix=CHECKIZFHMIN-ILP32F-LP64F %s
 ; RUN: llc -mtriple=riscv64 -mattr=+zfhmin -verify-machineinstrs \
 ; RUN:   -target-abi lp64f < %s | FileCheck -check-prefix=CHECKIZFHMIN-ILP32F-LP64F %s
 ; RUN: llc -mtriple=riscv32 -mattr=+zfhmin -verify-machineinstrs \
 ; RUN:   < %s | FileCheck -check-prefix=CHECKIZFHMIN %s
 ; RUN: llc -mtriple=riscv64 -mattr=+zfhmin -verify-machineinstrs \
 ; RUN:   < %s | FileCheck -check-prefix=CHECKIZFHMIN %s
+; RUN: llc -mtriple=riscv32 -mattr=+zhinxmin -verify-machineinstrs \
+; RUN:   -target-abi ilp32 < %s | FileCheck -check-prefix=CHECKIZHINXMIN %s
+; RUN: llc -mtriple=riscv64 -mattr=+zhinxmin -verify-machineinstrs \
+; RUN:   -target-abi lp64 < %s | FileCheck -check-prefix=CHECKIZHINXMIN %s
 
 define i32 @fcmp_false(half %a, half %b) nounwind {
 ; CHECKIZFH-LABEL: fcmp_false:
 ; CHECKIZFH:       # %bb.0:
 ; CHECKIZFH-NEXT:    li a0, 0
 ; CHECKIZFH-NEXT:    ret
 ;
+; CHECKIZHINX-LABEL: fcmp_false:
+; CHECKIZHINX:       # %bb.0:
+; CHECKIZHINX-NEXT:    li a0, 0
+; CHECKIZHINX-NEXT:    ret
+;
 ; RV32I-LABEL: fcmp_false:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    li a0, 0
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: fcmp_false:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    li a0, 0
 ; RV64I-NEXT:    ret
 ;
 ; CHECKIZFHMIN-ILP32F-LP64F-LABEL: fcmp_false:
 ; CHECKIZFHMIN-ILP32F-LP64F:       # %bb.0:
 ; CHECKIZFHMIN-ILP32F-LP64F-NEXT:    li a0, 0
 ; CHECKIZFHMIN-ILP32F-LP64F-NEXT:    ret
 ;
 ; CHECKIZFHMIN-LABEL: fcmp_false:
 ; CHECKIZFHMIN:       # %bb.0:
 ; CHECKIZFHMIN-NEXT:    li a0, 0
 ; CHECKIZFHMIN-NEXT:    ret
+;
+; CHECKIZHINXMIN-LABEL: fcmp_false:
+; CHECKIZHINXMIN:       # %bb.0:
+; CHECKIZHINXMIN-NEXT:    li a0, 0
+; CHECKIZHINXMIN-NEXT:    ret
   %1 = fcmp false half %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmp_oeq(half %a, half %b) nounwind {
 ; CHECKIZFH-LABEL: fcmp_oeq:
 ; CHECKIZFH:       # %bb.0:
 ; CHECKIZFH-NEXT:    feq.h a0, fa0, fa1
 ; CHECKIZFH-NEXT:    ret
 ;
+; CHECKIZHINX-LABEL: fcmp_oeq:
+; CHECKIZHINX:       # %bb.0:
+; CHECKIZHINX-NEXT:    feq.h a0, a0, a1
+; CHECKIZHINX-NEXT:    ret
+;
 ; RV32I-LABEL: fcmp_oeq:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    fmv.h.x fa5, a1
 ; RV32I-NEXT:    fmv.h.x fa4, a0
 ; RV32I-NEXT:    feq.h a0, fa4, fa5
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: fcmp_oeq:

 ; CHECKIZFHMIN-LABEL: fcmp_oeq:
 ; CHECKIZFHMIN:       # %bb.0:
 ; CHECKIZFHMIN-NEXT:    fmv.h.x fa5, a0
 ; CHECKIZFHMIN-NEXT:    fmv.h.x fa4, a1
 ; CHECKIZFHMIN-NEXT:    fcvt.s.h fa4, fa4
 ; CHECKIZFHMIN-NEXT:    fcvt.s.h fa5, fa5
 ; CHECKIZFHMIN-NEXT:    feq.s a0, fa5, fa4
 ; CHECKIZFHMIN-NEXT:    ret
+;
+; CHECKIZHINXMIN-LABEL: fcmp_oeq:
+; CHECKIZHINXMIN:       # %bb.0:
+; CHECKIZHINXMIN-NEXT:    fcvt.s.h a1, a1
+; CHECKIZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECKIZHINXMIN-NEXT:    feq.s a0, a0, a1
+; CHECKIZHINXMIN-NEXT:    ret
   %1 = fcmp oeq half %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmp_ogt(half %a, half %b) nounwind {
 ; CHECKIZFH-LABEL: fcmp_ogt:
 ; CHECKIZFH:       # %bb.0:
 ; CHECKIZFH-NEXT:    flt.h a0, fa1, fa0
 ; CHECKIZFH-NEXT:    ret
 ;
+; CHECKIZHINX-LABEL: fcmp_ogt:
+; CHECKIZHINX:       # %bb.0:
+; CHECKIZHINX-NEXT:    flt.h a0, a1, a0
+; CHECKIZHINX-NEXT:    ret
+;
 ; RV32I-LABEL: fcmp_ogt:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    fmv.h.x fa5, a0
 ; RV32I-NEXT:    fmv.h.x fa4, a1
 ; RV32I-NEXT:    flt.h a0, fa4, fa5
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: fcmp_ogt:

 ; CHECKIZFHMIN-LABEL: fcmp_ogt:
 ; CHECKIZFHMIN:       # %bb.0:
 ; CHECKIZFHMIN-NEXT:    fmv.h.x fa5, a1
 ; CHECKIZFHMIN-NEXT:    fmv.h.x fa4, a0
 ; CHECKIZFHMIN-NEXT:    fcvt.s.h fa4, fa4
 ; CHECKIZFHMIN-NEXT:    fcvt.s.h fa5, fa5
 ; CHECKIZFHMIN-NEXT:    flt.s a0, fa5, fa4
 ; CHECKIZFHMIN-NEXT:    ret
+;
+; CHECKIZHINXMIN-LABEL: fcmp_ogt:
+; CHECKIZHINXMIN:       # %bb.0:
+; CHECKIZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECKIZHINXMIN-NEXT:    fcvt.s.h a1, a1
+; CHECKIZHINXMIN-NEXT:    flt.s a0, a1, a0
+; CHECKIZHINXMIN-NEXT:    ret
   %1 = fcmp ogt half %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmp_oge(half %a, half %b) nounwind {
 ; CHECKIZFH-LABEL: fcmp_oge:
 ; CHECKIZFH:       # %bb.0:
 ; CHECKIZFH-NEXT:    fle.h a0, fa1, fa0
 ; CHECKIZFH-NEXT:    ret
 ;
+; CHECKIZHINX-LABEL: fcmp_oge:
+; CHECKIZHINX:       # %bb.0:
+; CHECKIZHINX-NEXT:    fle.h a0, a1, a0
+; CHECKIZHINX-NEXT:    ret
+;
 ; RV32I-LABEL: fcmp_oge:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    fmv.h.x fa5, a0
 ; RV32I-NEXT:    fmv.h.x fa4, a1
 ; RV32I-NEXT:    fle.h a0, fa4, fa5
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: fcmp_oge:

 ; CHECKIZFHMIN-LABEL: fcmp_oge:
 ; CHECKIZFHMIN:       # %bb.0:
 ; CHECKIZFHMIN-NEXT:    fmv.h.x fa5, a1
 ; CHECKIZFHMIN-NEXT:    fmv.h.x fa4, a0
 ; CHECKIZFHMIN-NEXT:    fcvt.s.h fa4, fa4
 ; CHECKIZFHMIN-NEXT:    fcvt.s.h fa5, fa5
 ; CHECKIZFHMIN-NEXT:    fle.s a0, fa5, fa4
 ; CHECKIZFHMIN-NEXT:    ret
+;
+; CHECKIZHINXMIN-LABEL: fcmp_oge:
+; CHECKIZHINXMIN:       # %bb.0:
+; CHECKIZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECKIZHINXMIN-NEXT:    fcvt.s.h a1, a1
+; CHECKIZHINXMIN-NEXT:    fle.s a0, a1, a0
+; CHECKIZHINXMIN-NEXT:    ret
   %1 = fcmp oge half %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmp_olt(half %a, half %b) nounwind {
 ; CHECKIZFH-LABEL: fcmp_olt:
 ; CHECKIZFH:       # %bb.0:
 ; CHECKIZFH-NEXT:    flt.h a0, fa0, fa1
 ; CHECKIZFH-NEXT:    ret
 ;
+; CHECKIZHINX-LABEL: fcmp_olt:
+; CHECKIZHINX:       # %bb.0:
+; CHECKIZHINX-NEXT:    flt.h a0, a0, a1
+; CHECKIZHINX-NEXT:    ret
+;
 ; RV32I-LABEL: fcmp_olt:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    fmv.h.x fa5, a1
 ; RV32I-NEXT:    fmv.h.x fa4, a0
 ; RV32I-NEXT:    flt.h a0, fa4, fa5
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: fcmp_olt:

 ; CHECKIZFHMIN-LABEL: fcmp_olt:
 ; CHECKIZFHMIN:       # %bb.0:
 ; CHECKIZFHMIN-NEXT:    fmv.h.x fa5, a0
 ; CHECKIZFHMIN-NEXT:    fmv.h.x fa4, a1
 ; CHECKIZFHMIN-NEXT:    fcvt.s.h fa4, fa4
 ; CHECKIZFHMIN-NEXT:    fcvt.s.h fa5, fa5
 ; CHECKIZFHMIN-NEXT:    flt.s a0, fa5, fa4
 ; CHECKIZFHMIN-NEXT:    ret
+;
+; CHECKIZHINXMIN-LABEL: fcmp_olt:
+; CHECKIZHINXMIN:       # %bb.0:
+; CHECKIZHINXMIN-NEXT:    fcvt.s.h a1, a1
+; CHECKIZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECKIZHINXMIN-NEXT:    flt.s a0, a0, a1
+; CHECKIZHINXMIN-NEXT:    ret
   %1 = fcmp olt half %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmp_ole(half %a, half %b) nounwind {
 ; CHECKIZFH-LABEL: fcmp_ole:
 ; CHECKIZFH:       # %bb.0:
 ; CHECKIZFH-NEXT:    fle.h a0, fa0, fa1
 ; CHECKIZFH-NEXT:    ret
 ;
+; CHECKIZHINX-LABEL: fcmp_ole:
+; CHECKIZHINX:       # %bb.0:
+; CHECKIZHINX-NEXT:    fle.h a0, a0, a1
+; CHECKIZHINX-NEXT:    ret
+;
 ; RV32I-LABEL: fcmp_ole:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    fmv.h.x fa5, a1
 ; RV32I-NEXT:    fmv.h.x fa4, a0
 ; RV32I-NEXT:    fle.h a0, fa4, fa5
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: fcmp_ole:

 ; CHECKIZFHMIN-LABEL: fcmp_ole:
 ; CHECKIZFHMIN:       # %bb.0:
 ; CHECKIZFHMIN-NEXT:    fmv.h.x fa5, a0
 ; CHECKIZFHMIN-NEXT:    fmv.h.x fa4, a1
 ; CHECKIZFHMIN-NEXT:    fcvt.s.h fa4, fa4
 ; CHECKIZFHMIN-NEXT:    fcvt.s.h fa5, fa5
 ; CHECKIZFHMIN-NEXT:    fle.s a0, fa5, fa4
 ; CHECKIZFHMIN-NEXT:    ret
+;
+; CHECKIZHINXMIN-LABEL: fcmp_ole:
+; CHECKIZHINXMIN:       # %bb.0:
+; CHECKIZHINXMIN-NEXT:    fcvt.s.h a1, a1
+; CHECKIZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECKIZHINXMIN-NEXT:    fle.s a0, a0, a1
+; CHECKIZHINXMIN-NEXT:    ret
   %1 = fcmp ole half %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmp_one(half %a, half %b) nounwind {
 ; CHECKIZFH-LABEL: fcmp_one:
 ; CHECKIZFH:       # %bb.0:
 ; CHECKIZFH-NEXT:    flt.h a0, fa0, fa1
 ; CHECKIZFH-NEXT:    flt.h a1, fa1, fa0
 ; CHECKIZFH-NEXT:    or a0, a1, a0
 ; CHECKIZFH-NEXT:    ret
 ;
+; CHECKIZHINX-LABEL: fcmp_one:
+; CHECKIZHINX:       # %bb.0:
+; CHECKIZHINX-NEXT:    flt.h a2, a0, a1
+; CHECKIZHINX-NEXT:    flt.h a0, a1, a0
+; CHECKIZHINX-NEXT:    or a0, a0, a2
+; CHECKIZHINX-NEXT:    ret
+;
 ; RV32I-LABEL: fcmp_one:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    fmv.h.x fa5, a1
 ; RV32I-NEXT:    fmv.h.x fa4, a0
 ; RV32I-NEXT:    flt.h a0, fa4, fa5
 ; RV32I-NEXT:    flt.h a1, fa5, fa4
 ; RV32I-NEXT:    or a0, a1, a0
 ; RV32I-NEXT:    ret

 ; CHECKIZFHMIN-NEXT:    fmv.h.x fa5, a0
 ; CHECKIZFHMIN-NEXT:    fmv.h.x fa4, a1
 ; CHECKIZFHMIN-NEXT:    fcvt.s.h fa4, fa4
 ; CHECKIZFHMIN-NEXT:    fcvt.s.h fa5, fa5
 ; CHECKIZFHMIN-NEXT:    flt.s a0, fa5, fa4
 ; CHECKIZFHMIN-NEXT:    flt.s a1, fa4, fa5
 ; CHECKIZFHMIN-NEXT:    or a0, a1, a0
 ; CHECKIZFHMIN-NEXT:    ret
+;
+; CHECKIZHINXMIN-LABEL: fcmp_one:
+; CHECKIZHINXMIN:       # %bb.0:
+; CHECKIZHINXMIN-NEXT:    fcvt.s.h a1, a1
+; CHECKIZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECKIZHINXMIN-NEXT:    flt.s a2, a0, a1
+; CHECKIZHINXMIN-NEXT:    flt.s a0, a1, a0
+; CHECKIZHINXMIN-NEXT:    or a0, a0, a2
+; CHECKIZHINXMIN-NEXT:    ret
   %1 = fcmp one half %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmp_ord(half %a, half %b) nounwind {
 ; CHECKIZFH-LABEL: fcmp_ord:
 ; CHECKIZFH:       # %bb.0:
 ; CHECKIZFH-NEXT:    feq.h a0, fa1, fa1
 ; CHECKIZFH-NEXT:    feq.h a1, fa0, fa0
 ; CHECKIZFH-NEXT:    and a0, a1, a0
 ; CHECKIZFH-NEXT:    ret
 ;
+; CHECKIZHINX-LABEL: fcmp_ord:
+; CHECKIZHINX:       # %bb.0:
+; CHECKIZHINX-NEXT:    feq.h a1, a1, a1
+; CHECKIZHINX-NEXT:    feq.h a0, a0, a0
+; CHECKIZHINX-NEXT:    and a0, a0, a1
+; CHECKIZHINX-NEXT:    ret
+;
 ; RV32I-LABEL: fcmp_ord:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    fmv.h.x fa5, a0
 ; RV32I-NEXT:    fmv.h.x fa4, a1
 ; RV32I-NEXT:    feq.h a0, fa4, fa4
 ; RV32I-NEXT:    feq.h a1, fa5, fa5
 ; RV32I-NEXT:    and a0, a1, a0
 ; RV32I-NEXT:    ret

 ; CHECKIZFHMIN-NEXT:    fmv.h.x fa5, a0
 ; CHECKIZFHMIN-NEXT:    fmv.h.x fa4, a1
 ; CHECKIZFHMIN-NEXT:    fcvt.s.h fa4, fa4
 ; CHECKIZFHMIN-NEXT:    feq.s a0, fa4, fa4
 ; CHECKIZFHMIN-NEXT:    fcvt.s.h fa5, fa5
 ; CHECKIZFHMIN-NEXT:    feq.s a1, fa5, fa5
 ; CHECKIZFHMIN-NEXT:    and a0, a1, a0
 ; CHECKIZFHMIN-NEXT:    ret
+;
+; CHECKIZHINXMIN-LABEL: fcmp_ord:
+; CHECKIZHINXMIN:       # %bb.0:
+; CHECKIZHINXMIN-NEXT:    fcvt.s.h a1, a1
+; CHECKIZHINXMIN-NEXT:    feq.s a1, a1, a1
+; CHECKIZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECKIZHINXMIN-NEXT:    feq.s a0, a0, a0
+; CHECKIZHINXMIN-NEXT:    and a0, a0, a1
+; CHECKIZHINXMIN-NEXT:    ret
   %1 = fcmp ord half %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmp_ueq(half %a, half %b) nounwind {
 ; CHECKIZFH-LABEL: fcmp_ueq:
 ; CHECKIZFH:       # %bb.0:
 ; CHECKIZFH-NEXT:    flt.h a0, fa0, fa1
 ; CHECKIZFH-NEXT:    flt.h a1, fa1, fa0
 ; CHECKIZFH-NEXT:    or a0, a1, a0
 ; CHECKIZFH-NEXT:    xori a0, a0, 1
 ; CHECKIZFH-NEXT:    ret
 ;
+; CHECKIZHINX-LABEL: fcmp_ueq:
+; CHECKIZHINX:       # %bb.0:
+; CHECKIZHINX-NEXT:    flt.h a2, a0, a1
+; CHECKIZHINX-NEXT:    flt.h a0, a1, a0
+; CHECKIZHINX-NEXT:    or a0, a0, a2
+; CHECKIZHINX-NEXT:    xori a0, a0, 1
+; CHECKIZHINX-NEXT:    ret
+;
 ; RV32I-LABEL: fcmp_ueq:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    fmv.h.x fa5, a1
 ; RV32I-NEXT:    fmv.h.x fa4, a0
 ; RV32I-NEXT:    flt.h a0, fa4, fa5
 ; RV32I-NEXT:    flt.h a1, fa5, fa4
 ; RV32I-NEXT:    or a0, a1, a0
 ; RV32I-NEXT:    xori a0, a0, 1

 ; CHECKIZFHMIN-NEXT:    fmv.h.x fa4, a1
 ; CHECKIZFHMIN-NEXT:    fcvt.s.h fa4, fa4
 ; CHECKIZFHMIN-NEXT:    fcvt.s.h fa5, fa5
 ; CHECKIZFHMIN-NEXT:    flt.s a0, fa5, fa4
 ; CHECKIZFHMIN-NEXT:    flt.s a1, fa4, fa5
 ; CHECKIZFHMIN-NEXT:    or a0, a1, a0
 ; CHECKIZFHMIN-NEXT:    xori a0, a0, 1
 ; CHECKIZFHMIN-NEXT:    ret
+;
+; CHECKIZHINXMIN-LABEL: fcmp_ueq:
+; CHECKIZHINXMIN:       # %bb.0:
+; CHECKIZHINXMIN-NEXT:    fcvt.s.h a1, a1
+; CHECKIZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECKIZHINXMIN-NEXT:    flt.s a2, a0, a1
+; CHECKIZHINXMIN-NEXT:    flt.s a0, a1, a0
+; CHECKIZHINXMIN-NEXT:    or a0, a0, a2
+; CHECKIZHINXMIN-NEXT:    xori a0, a0, 1
+; CHECKIZHINXMIN-NEXT:    ret
   %1 = fcmp ueq half %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmp_ugt(half %a, half %b) nounwind {
 ; CHECKIZFH-LABEL: fcmp_ugt:
 ; CHECKIZFH:       # %bb.0:
 ; CHECKIZFH-NEXT:    fle.h a0, fa0, fa1
 ; CHECKIZFH-NEXT:    xori a0, a0, 1
 ; CHECKIZFH-NEXT:    ret
 ;
+; CHECKIZHINX-LABEL: fcmp_ugt:
+; CHECKIZHINX:       # %bb.0:
+; CHECKIZHINX-NEXT:    fle.h a0, a0, a1
+; CHECKIZHINX-NEXT:    xori a0, a0, 1
+; CHECKIZHINX-NEXT:    ret
+;
 ; RV32I-LABEL: fcmp_ugt:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    fmv.h.x fa5, a1
 ; RV32I-NEXT:    fmv.h.x fa4, a0
 ; RV32I-NEXT:    fle.h a0, fa4, fa5
 ; RV32I-NEXT:    xori a0, a0, 1
 ; RV32I-NEXT:    ret
 ;

 ; CHECKIZFHMIN:       # %bb.0:
 ; CHECKIZFHMIN-NEXT:    fmv.h.x fa5, a0
 ; CHECKIZFHMIN-NEXT:    fmv.h.x fa4, a1
 ; CHECKIZFHMIN-NEXT:    fcvt.s.h fa4, fa4
 ; CHECKIZFHMIN-NEXT:    fcvt.s.h fa5, fa5
 ; CHECKIZFHMIN-NEXT:    fle.s a0, fa5, fa4
 ; CHECKIZFHMIN-NEXT:    xori a0, a0, 1
 ; CHECKIZFHMIN-NEXT:    ret
+;
+; CHECKIZHINXMIN-LABEL: fcmp_ugt:
+; CHECKIZHINXMIN:       # %bb.0:
+; CHECKIZHINXMIN-NEXT:    fcvt.s.h a1, a1
+; CHECKIZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECKIZHINXMIN-NEXT:    fle.s a0, a0, a1
+; CHECKIZHINXMIN-NEXT:    xori a0, a0, 1
+; CHECKIZHINXMIN-NEXT:    ret
   %1 = fcmp ugt half %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmp_uge(half %a, half %b) nounwind {
 ; CHECKIZFH-LABEL: fcmp_uge:
 ; CHECKIZFH:       # %bb.0:
 ; CHECKIZFH-NEXT:    flt.h a0, fa0, fa1
 ; CHECKIZFH-NEXT:    xori a0, a0, 1
 ; CHECKIZFH-NEXT:    ret
 ;
+; CHECKIZHINX-LABEL: fcmp_uge:
+; CHECKIZHINX:       # %bb.0:
+; CHECKIZHINX-NEXT:    flt.h a0, a0, a1
+; CHECKIZHINX-NEXT:    xori a0, a0, 1
+; CHECKIZHINX-NEXT:    ret
+;
 ; RV32I-LABEL: fcmp_uge:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    fmv.h.x fa5, a1
 ; RV32I-NEXT:    fmv.h.x fa4, a0
 ; RV32I-NEXT:    flt.h a0, fa4, fa5
 ; RV32I-NEXT:    xori a0, a0, 1
 ; RV32I-NEXT:    ret
 ;

 ; CHECKIZFHMIN:       # %bb.0:
 ; CHECKIZFHMIN-NEXT:    fmv.h.x fa5, a0
 ; CHECKIZFHMIN-NEXT:    fmv.h.x fa4, a1
 ; CHECKIZFHMIN-NEXT:    fcvt.s.h fa4, fa4
 ; CHECKIZFHMIN-NEXT:    fcvt.s.h fa5, fa5
 ; CHECKIZFHMIN-NEXT:    flt.s a0, fa5, fa4
 ; CHECKIZFHMIN-NEXT:    xori a0, a0, 1
 ; CHECKIZFHMIN-NEXT:    ret
+;
+; CHECKIZHINXMIN-LABEL: fcmp_uge:
+; CHECKIZHINXMIN:       # %bb.0:
+; CHECKIZHINXMIN-NEXT:    fcvt.s.h a1, a1
+; CHECKIZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECKIZHINXMIN-NEXT:    flt.s a0, a0, a1
+; CHECKIZHINXMIN-NEXT:    xori a0, a0, 1
+; CHECKIZHINXMIN-NEXT:    ret
   %1 = fcmp uge half %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmp_ult(half %a, half %b) nounwind {
 ; CHECKIZFH-LABEL: fcmp_ult:
 ; CHECKIZFH:       # %bb.0:
 ; CHECKIZFH-NEXT:    fle.h a0, fa1, fa0
 ; CHECKIZFH-NEXT:    xori a0, a0, 1
 ; CHECKIZFH-NEXT:    ret
 ;
+; CHECKIZHINX-LABEL: fcmp_ult:
+; CHECKIZHINX:       # %bb.0:
+; CHECKIZHINX-NEXT:    fle.h a0, a1, a0
+; CHECKIZHINX-NEXT:    xori a0, a0, 1
+; CHECKIZHINX-NEXT:    ret
+;
 ; RV32I-LABEL: fcmp_ult:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    fmv.h.x fa5, a0
 ; RV32I-NEXT:    fmv.h.x fa4, a1
 ; RV32I-NEXT:    fle.h a0, fa4, fa5
 ; RV32I-NEXT:    xori a0, a0, 1
 ; RV32I-NEXT:    ret
 ;

 ; CHECKIZFHMIN:       # %bb.0:
 ; CHECKIZFHMIN-NEXT:    fmv.h.x fa5, a1
 ; CHECKIZFHMIN-NEXT:    fmv.h.x fa4, a0
 ; CHECKIZFHMIN-NEXT:    fcvt.s.h fa4, fa4
 ; CHECKIZFHMIN-NEXT:    fcvt.s.h fa5, fa5
 ; CHECKIZFHMIN-NEXT:    fle.s a0, fa5, fa4
 ; CHECKIZFHMIN-NEXT:    xori a0, a0, 1
 ; CHECKIZFHMIN-NEXT:    ret
+;
+; CHECKIZHINXMIN-LABEL: fcmp_ult:
+; CHECKIZHINXMIN:       # %bb.0:
+; CHECKIZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECKIZHINXMIN-NEXT:    fcvt.s.h a1, a1
+; CHECKIZHINXMIN-NEXT:    fle.s a0, a1, a0
+; CHECKIZHINXMIN-NEXT:    xori a0, a0, 1
+; CHECKIZHINXMIN-NEXT:    ret
   %1 = fcmp ult half %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmp_ule(half %a, half %b) nounwind {
 ; CHECKIZFH-LABEL: fcmp_ule:
 ; CHECKIZFH:       # %bb.0:
 ; CHECKIZFH-NEXT:    flt.h a0, fa1, fa0
 ; CHECKIZFH-NEXT:    xori a0, a0, 1
 ; CHECKIZFH-NEXT:    ret
 ;
+; CHECKIZHINX-LABEL: fcmp_ule:
+; CHECKIZHINX:       # %bb.0:
+; CHECKIZHINX-NEXT:    flt.h a0, a1, a0
+; CHECKIZHINX-NEXT:    xori a0, a0, 1
+; CHECKIZHINX-NEXT:    ret
+;
 ; RV32I-LABEL: fcmp_ule:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    fmv.h.x fa5, a0
 ; RV32I-NEXT:    fmv.h.x fa4, a1
 ; RV32I-NEXT:    flt.h a0, fa4, fa5
 ; RV32I-NEXT:    xori a0, a0, 1
 ; RV32I-NEXT:    ret
 ;

 ; CHECKIZFHMIN:       # %bb.0:
 ; CHECKIZFHMIN-NEXT:    fmv.h.x fa5, a1
 ; CHECKIZFHMIN-NEXT:    fmv.h.x fa4, a0
 ; CHECKIZFHMIN-NEXT:    fcvt.s.h fa4, fa4
 ; CHECKIZFHMIN-NEXT:    fcvt.s.h fa5, fa5
 ; CHECKIZFHMIN-NEXT:    flt.s a0, fa5, fa4
 ; CHECKIZFHMIN-NEXT:    xori a0, a0, 1
 ; CHECKIZFHMIN-NEXT:    ret
+;
+; CHECKIZHINXMIN-LABEL: fcmp_ule:
+; CHECKIZHINXMIN:       # %bb.0:
+; CHECKIZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECKIZHINXMIN-NEXT:    fcvt.s.h a1, a1
+; CHECKIZHINXMIN-NEXT:    flt.s a0, a1, a0
+; CHECKIZHINXMIN-NEXT:    xori a0, a0, 1
+; CHECKIZHINXMIN-NEXT:    ret
   %1 = fcmp ule half %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmp_une(half %a, half %b) nounwind {
 ; CHECKIZFH-LABEL: fcmp_une:
 ; CHECKIZFH:       # %bb.0:
 ; CHECKIZFH-NEXT:    feq.h a0, fa0, fa1
 ; CHECKIZFH-NEXT:    xori a0, a0, 1
 ; CHECKIZFH-NEXT:    ret
 ;
+; CHECKIZHINX-LABEL: fcmp_une:
+; CHECKIZHINX:       # %bb.0:
+; CHECKIZHINX-NEXT:    feq.h a0, a0, a1
+; CHECKIZHINX-NEXT:    xori a0, a0, 1
+; CHECKIZHINX-NEXT:    ret
+;
 ; RV32I-LABEL: fcmp_une:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    fmv.h.x fa5, a1
 ; RV32I-NEXT:    fmv.h.x fa4, a0
 ; RV32I-NEXT:    feq.h a0, fa4, fa5
 ; RV32I-NEXT:    xori a0, a0, 1
 ; RV32I-NEXT:    ret
 ;

 ; CHECKIZFHMIN:       # %bb.0:
 ; CHECKIZFHMIN-NEXT:    fmv.h.x fa5, a0
 ; CHECKIZFHMIN-NEXT:    fmv.h.x fa4, a1
 ; CHECKIZFHMIN-NEXT:    fcvt.s.h fa4, fa4
 ; CHECKIZFHMIN-NEXT:    fcvt.s.h fa5, fa5
 ; CHECKIZFHMIN-NEXT:    feq.s a0, fa5, fa4
 ; CHECKIZFHMIN-NEXT:    xori a0, a0, 1
 ; CHECKIZFHMIN-NEXT:    ret
+;
+; CHECKIZHINXMIN-LABEL: fcmp_une:
+; CHECKIZHINXMIN:       # %bb.0:
+; CHECKIZHINXMIN-NEXT:    fcvt.s.h a1, a1
+; CHECKIZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECKIZHINXMIN-NEXT:    feq.s a0, a0, a1
+; CHECKIZHINXMIN-NEXT:    xori a0, a0, 1
+; CHECKIZHINXMIN-NEXT:    ret
   %1 = fcmp une half %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmp_uno(half %a, half %b) nounwind {
 ; CHECKIZFH-LABEL: fcmp_uno:
 ; CHECKIZFH:       # %bb.0:
 ; CHECKIZFH-NEXT:    feq.h a0, fa1, fa1
 ; CHECKIZFH-NEXT:    feq.h a1, fa0, fa0
 ; CHECKIZFH-NEXT:    and a0, a1, a0
 ; CHECKIZFH-NEXT:    xori a0, a0, 1
 ; CHECKIZFH-NEXT:    ret
 ;
+; CHECKIZHINX-LABEL: fcmp_uno:
+; CHECKIZHINX:       # %bb.0:
+; CHECKIZHINX-NEXT:    feq.h a1, a1, a1
+; CHECKIZHINX-NEXT:    feq.h a0, a0, a0
+; CHECKIZHINX-NEXT:    and a0, a0, a1
+; CHECKIZHINX-NEXT:    xori a0, a0, 1
+; CHECKIZHINX-NEXT:    ret
+;
 ; RV32I-LABEL: fcmp_uno:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    fmv.h.x fa5, a0
 ; RV32I-NEXT:    fmv.h.x fa4, a1
 ; RV32I-NEXT:    feq.h a0, fa4, fa4
 ; RV32I-NEXT:    feq.h a1, fa5, fa5
 ; RV32I-NEXT:    and a0, a1, a0
 ; RV32I-NEXT:    xori a0, a0, 1

 ; CHECKIZFHMIN-NEXT:    fmv.h.x fa4, a1
 ; CHECKIZFHMIN-NEXT:    fcvt.s.h fa4, fa4
 ; CHECKIZFHMIN-NEXT:    feq.s a0, fa4, fa4
 ; CHECKIZFHMIN-NEXT:    fcvt.s.h fa5, fa5
 ; CHECKIZFHMIN-NEXT:    feq.s a1, fa5, fa5
 ; CHECKIZFHMIN-NEXT:    and a0, a1, a0
 ; CHECKIZFHMIN-NEXT:    xori a0, a0, 1
 ; CHECKIZFHMIN-NEXT:    ret
+;
+; CHECKIZHINXMIN-LABEL: fcmp_uno:
+; CHECKIZHINXMIN:       # %bb.0:
+; CHECKIZHINXMIN-NEXT:    fcvt.s.h a1, a1
+; CHECKIZHINXMIN-NEXT:    feq.s a1, a1, a1
+; CHECKIZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECKIZHINXMIN-NEXT:    feq.s a0, a0, a0
+; CHECKIZHINXMIN-NEXT:    and a0, a0, a1
+; CHECKIZHINXMIN-NEXT:    xori a0, a0, 1
+; CHECKIZHINXMIN-NEXT:    ret
   %1 = fcmp uno half %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }
 
 define i32 @fcmp_true(half %a, half %b) nounwind {
 ; CHECKIZFH-LABEL: fcmp_true:
 ; CHECKIZFH:       # %bb.0:
 ; CHECKIZFH-NEXT:    li a0, 1
 ; CHECKIZFH-NEXT:    ret
 ;
+; CHECKIZHINX-LABEL: fcmp_true:
+; CHECKIZHINX:       # %bb.0:
+; CHECKIZHINX-NEXT:    li a0, 1
+; CHECKIZHINX-NEXT:    ret
+;
 ; RV32I-LABEL: fcmp_true:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    li a0, 1
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: fcmp_true:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    li a0, 1
 ; RV64I-NEXT:    ret
 ;
 ; CHECKIZFHMIN-ILP32F-LP64F-LABEL: fcmp_true:
 ; CHECKIZFHMIN-ILP32F-LP64F:       # %bb.0:
 ; CHECKIZFHMIN-ILP32F-LP64F-NEXT:    li a0, 1
 ; CHECKIZFHMIN-ILP32F-LP64F-NEXT:    ret
 ;
 ; CHECKIZFHMIN-LABEL: fcmp_true:
 ; CHECKIZFHMIN:       # %bb.0:
 ; CHECKIZFHMIN-NEXT:    li a0, 1
 ; CHECKIZFHMIN-NEXT:    ret
+;
+; CHECKIZHINXMIN-LABEL: fcmp_true:
+; CHECKIZHINXMIN:       # %bb.0:
+; CHECKIZHINXMIN-NEXT:    li a0, 1
+; CHECKIZHINXMIN-NEXT:    ret
   %1 = fcmp true half %a, %b
   %2 = zext i1 %1 to i32
   ret i32 %2
 }

llvm/test/CodeGen/RISCV/half-frem.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -mattr=+zfh -verify-machineinstrs \
 ; RUN:   -target-abi ilp32f < %s \
 ; RUN:   | FileCheck -check-prefix=RV32IZFH %s
 ; RUN: llc -mtriple=riscv64 -mattr=+zfh -verify-machineinstrs \
 ; RUN:   -target-abi lp64f < %s \
 ; RUN:   | FileCheck -check-prefix=RV64IZFH %s
+; RUN: llc -mtriple=riscv32 -mattr=+zhinx -verify-machineinstrs \
+; RUN:   -target-abi ilp32 < %s \
+; RUN:   | FileCheck -check-prefix=RV32IZHINX %s
+; RUN: llc -mtriple=riscv64 -mattr=+zhinx -verify-machineinstrs \
+; RUN:   -target-abi lp64 < %s \
+; RUN:   | FileCheck -check-prefix=RV64IZHINX %s
 ; RUN: llc -mtriple=riscv32 -mattr=+zfhmin -verify-machineinstrs \
 ; RUN:   -target-abi ilp32f < %s \
 ; RUN:   | FileCheck -check-prefix=RV32IZFHMIN %s
 ; RUN: llc -mtriple=riscv64 -mattr=+zfhmin -verify-machineinstrs \
 ; RUN:   -target-abi lp64f < %s \
 ; RUN:   | FileCheck -check-prefix=RV64IZFHMIN %s
+; RUN: llc -mtriple=riscv32 -mattr=+zhinxmin -verify-machineinstrs \
+; RUN:   -target-abi ilp32 < %s \
+; RUN:   | FileCheck -check-prefix=RV32IZHINXMIN %s
+; RUN: llc -mtriple=riscv64 -mattr=+zhinxmin -verify-machineinstrs \
+; RUN:   -target-abi lp64 < %s \
+; RUN:   | FileCheck -check-prefix=RV64IZHINXMIN %s
 
 define half @frem_f16(half %a, half %b) nounwind {
 ; RV32IZFH-LABEL: frem_f16:
 ; RV32IZFH:       # %bb.0:
 ; RV32IZFH-NEXT:    addi sp, sp, -16
 ; RV32IZFH-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32IZFH-NEXT:    fcvt.s.h fa0, fa0
 ; RV32IZFH-NEXT:    fcvt.s.h fa1, fa1

 ; RV64IZFH-NEXT:    fcvt.s.h fa0, fa0
 ; RV64IZFH-NEXT:    fcvt.s.h fa1, fa1
 ; RV64IZFH-NEXT:    call fmodf@plt
 ; RV64IZFH-NEXT:    fcvt.h.s fa0, fa0
 ; RV64IZFH-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64IZFH-NEXT:    addi sp, sp, 16
 ; RV64IZFH-NEXT:    ret
 ;
+; RV32IZHINX-LABEL: frem_f16:
+; RV32IZHINX:       # %bb.0:
+; RV32IZHINX-NEXT:    addi sp, sp, -16
+; RV32IZHINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZHINX-NEXT:    fcvt.s.h a0, a0
+; RV32IZHINX-NEXT:    fcvt.s.h a1, a1
+; RV32IZHINX-NEXT:    call fmodf@plt
+; RV32IZHINX-NEXT:    fcvt.h.s a0, a0
+; RV32IZHINX-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZHINX-NEXT:    addi sp, sp, 16
+; RV32IZHINX-NEXT:    ret
+;
+; RV64IZHINX-LABEL: frem_f16:
+; RV64IZHINX:       # %bb.0:
+; RV64IZHINX-NEXT:    addi sp, sp, -16
+; RV64IZHINX-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IZHINX-NEXT:    fcvt.s.h a0, a0
+; RV64IZHINX-NEXT:    fcvt.s.h a1, a1
+; RV64IZHINX-NEXT:    call fmodf@plt
+; RV64IZHINX-NEXT:    fcvt.h.s a0, a0
+; RV64IZHINX-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
+; RV64IZHINX-NEXT:    addi sp, sp, 16
+; RV64IZHINX-NEXT:    ret
+;
 ; RV32IZFHMIN-LABEL: frem_f16:
 ; RV32IZFHMIN:       # %bb.0:
 ; RV32IZFHMIN-NEXT:    addi sp, sp, -16
 ; RV32IZFHMIN-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32IZFHMIN-NEXT:    fcvt.s.h fa0, fa0
 ; RV32IZFHMIN-NEXT:    fcvt.s.h fa1, fa1
 ; RV32IZFHMIN-NEXT:    call fmodf@plt
 ; RV32IZFHMIN-NEXT:    fcvt.h.s fa0, fa0
 ; RV32IZFHMIN-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32IZFHMIN-NEXT:    addi sp, sp, 16
 ; RV32IZFHMIN-NEXT:    ret
 ;
 ; RV64IZFHMIN-LABEL: frem_f16:
 ; RV64IZFHMIN:       # %bb.0:
 ; RV64IZFHMIN-NEXT:    addi sp, sp, -16
 ; RV64IZFHMIN-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64IZFHMIN-NEXT:    fcvt.s.h fa0, fa0
 ; RV64IZFHMIN-NEXT:    fcvt.s.h fa1, fa1
 ; RV64IZFHMIN-NEXT:    call fmodf@plt
 ; RV64IZFHMIN-NEXT:    fcvt.h.s fa0, fa0
 ; RV64IZFHMIN-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64IZFHMIN-NEXT:    addi sp, sp, 16
 ; RV64IZFHMIN-NEXT:    ret
+;
+; RV32IZHINXMIN-LABEL: frem_f16:
+; RV32IZHINXMIN:       # %bb.0:
+; RV32IZHINXMIN-NEXT:    addi sp, sp, -16
+; RV32IZHINXMIN-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV32IZHINXMIN-NEXT:    fcvt.s.h a1, a1
+; RV32IZHINXMIN-NEXT:    call fmodf@plt
+; RV32IZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; RV32IZHINXMIN-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZHINXMIN-NEXT:    addi sp, sp, 16
+; RV32IZHINXMIN-NEXT:    ret
+;
+; RV64IZHINXMIN-LABEL: frem_f16:
+; RV64IZHINXMIN:       # %bb.0:
+; RV64IZHINXMIN-NEXT:    addi sp, sp, -16
+; RV64IZHINXMIN-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV64IZHINXMIN-NEXT:    fcvt.s.h a1, a1
+; RV64IZHINXMIN-NEXT:    call fmodf@plt
+; RV64IZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; RV64IZHINXMIN-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
+; RV64IZHINXMIN-NEXT:    addi sp, sp, 16
+; RV64IZHINXMIN-NEXT:    ret
   %1 = frem half %a, %b
   ret half %1
 }

llvm/test/CodeGen/RISCV/half-imm.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -mattr=+zfh -verify-machineinstrs \
 ; RUN:   -target-abi ilp32f < %s | FileCheck %s
 ; RUN: llc -mtriple=riscv64 -mattr=+zfh -verify-machineinstrs \
 ; RUN:   -target-abi lp64f < %s | FileCheck %s
+; RUN: llc -mtriple=riscv32 -mattr=+zhinx -verify-machineinstrs \
+; RUN:   -target-abi ilp32 < %s \
+; RUN:   | FileCheck -check-prefix=RV32IZHINX %s
+; RUN: llc -mtriple=riscv64 -mattr=+zhinx -verify-machineinstrs \
+; RUN:   -target-abi lp64 < %s \
+; RUN:   | FileCheck -check-prefix=RV64IZHINX %s
 ; RUN: llc -mtriple=riscv32 -mattr=+zfhmin -verify-machineinstrs \
 ; RUN:   -target-abi ilp32f < %s | FileCheck -check-prefixes=CHECKIZFHMIN %s
 ; RUN: llc -mtriple=riscv64 -mattr=+zfhmin -verify-machineinstrs \
 ; RUN:   -target-abi lp64f < %s | FileCheck -check-prefixes=CHECKIZFHMIN %s
+; RUN: llc -mtriple=riscv32 -mattr=+zhinxmin -verify-machineinstrs \
+; RUN:   -target-abi ilp32 < %s \
+; RUN:   | FileCheck -check-prefixes=CHECKIZHINXMIN %s
+; RUN: llc -mtriple=riscv64 -mattr=+zhinxmin -verify-machineinstrs \
+; RUN:   -target-abi lp64 < %s \
+; RUN:   | FileCheck -check-prefixes=CHECKIZHINXMIN %s
 
 ; TODO: constant pool shouldn't be necessary for RV32IZfh and RV64IZfh
 define half @half_imm() nounwind {
 ; CHECK-LABEL: half_imm:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    lui a0, %hi(.LCPI0_0)
 ; CHECK-NEXT:    flh fa0, %lo(.LCPI0_0)(a0)
 ; CHECK-NEXT:    ret
 ;
+; RV32IZHINX-LABEL: half_imm:
+; RV32IZHINX:       # %bb.0:
+; RV32IZHINX-NEXT:    lui a0, %hi(.LCPI0_0)
+; RV32IZHINX-NEXT:    lh a0, %lo(.LCPI0_0)(a0)
+; RV32IZHINX-NEXT:    ret
+;
+; RV64IZHINX-LABEL: half_imm:
+; RV64IZHINX:       # %bb.0:
+; RV64IZHINX-NEXT:    lui a0, %hi(.LCPI0_0)
+; RV64IZHINX-NEXT:    lh a0, %lo(.LCPI0_0)(a0)
+; RV64IZHINX-NEXT:    ret
+;
 ; CHECKIZFHMIN-LABEL: half_imm:
 ; CHECKIZFHMIN:       # %bb.0:
 ; CHECKIZFHMIN-NEXT:    lui a0, %hi(.LCPI0_0)
 ; CHECKIZFHMIN-NEXT:    flh fa0, %lo(.LCPI0_0)(a0)
 ; CHECKIZFHMIN-NEXT:    ret
+;
+; CHECKIZHINXMIN-LABEL: half_imm:
+; CHECKIZHINXMIN:       # %bb.0:
+; CHECKIZHINXMIN-NEXT:    lui a0, %hi(.LCPI0_0)
+; CHECKIZHINXMIN-NEXT:    lh a0, %lo(.LCPI0_0)(a0)
+; CHECKIZHINXMIN-NEXT:    ret
   ret half 3.0
 }
 
 define half @half_imm_op(half %a) nounwind {
 ; CHECK-LABEL: half_imm_op:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    lui a0, %hi(.LCPI1_0)
 ; CHECK-NEXT:    flh fa5, %lo(.LCPI1_0)(a0)
 ; CHECK-NEXT:    fadd.h fa0, fa0, fa5
 ; CHECK-NEXT:    ret
 ;
+; RV32IZHINX-LABEL: half_imm_op:
+; RV32IZHINX:       # %bb.0:
+; RV32IZHINX-NEXT:    lui a1, %hi(.LCPI1_0)
+; RV32IZHINX-NEXT:    lh a1, %lo(.LCPI1_0)(a1)
+; RV32IZHINX-NEXT:    fadd.h a0, a0, a1
+; RV32IZHINX-NEXT:    ret
+;
+; RV64IZHINX-LABEL: half_imm_op:
+; RV64IZHINX:       # %bb.0:
+; RV64IZHINX-NEXT:    lui a1, %hi(.LCPI1_0)
+; RV64IZHINX-NEXT:    lh a1, %lo(.LCPI1_0)(a1)
+; RV64IZHINX-NEXT:    fadd.h a0, a0, a1
+; RV64IZHINX-NEXT:    ret
+;
 ; CHECKIZFHMIN-LABEL: half_imm_op:
 ; CHECKIZFHMIN:       # %bb.0:
 ; CHECKIZFHMIN-NEXT:    fcvt.s.h fa5, fa0
 ; CHECKIZFHMIN-NEXT:    lui a0, 260096
 ; CHECKIZFHMIN-NEXT:    fmv.w.x fa4, a0
 ; CHECKIZFHMIN-NEXT:    fadd.s fa5, fa5, fa4
 ; CHECKIZFHMIN-NEXT:    fcvt.h.s fa0, fa5
 ; CHECKIZFHMIN-NEXT:    ret
+;
+; CHECKIZHINXMIN-LABEL: half_imm_op:
+; CHECKIZHINXMIN:       # %bb.0:
+; CHECKIZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECKIZHINXMIN-NEXT:    lui a1, 260096
+; CHECKIZHINXMIN-NEXT:    fadd.s a0, a0, a1
+; CHECKIZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; CHECKIZHINXMIN-NEXT:    ret
   %1 = fadd half %a, 1.0
   ret half %1
 }

llvm/test/CodeGen/RISCV/half-intrinsics.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+zfh \
 ; RUN:   -verify-machineinstrs -target-abi ilp32f | \
 ; RUN:   FileCheck -check-prefixes=CHECKIZFH,RV32IZFH,RV32IFZFH %s
 ; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+zfh \
 ; RUN:   -verify-machineinstrs -target-abi lp64f | \
 ; RUN:   FileCheck -check-prefixes=CHECKIZFH,RV64IZFH,RV64IFZFH %s
+; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+zhinx \
+; RUN:   -verify-machineinstrs -target-abi ilp32 | \
+; RUN:   FileCheck -check-prefixes=CHECKIZHINX,RV32IZHINX %s
+; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+zhinx \
+; RUN:   -verify-machineinstrs -target-abi lp64 | \
+; RUN:   FileCheck -check-prefixes=CHECKIZHINX,RV64IZHINX %s
 ; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+d \
 ; RUN:   -mattr=+zfh -verify-machineinstrs -target-abi ilp32d | \
 ; RUN:   FileCheck -check-prefixes=CHECKIZFH,RV32IZFH,RV32IDZFH %s
 ; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+d \
 ; RUN:   -mattr=+zfh -verify-machineinstrs -target-abi lp64d | \
 ; RUN:   FileCheck -check-prefixes=CHECKIZFH,RV64IZFH,RV64IDZFH %s
+; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+zdinx \
+; RUN:   -mattr=+zhinx -verify-machineinstrs -target-abi ilp32 | \
+; RUN:   FileCheck -check-prefixes=CHECKIZHINX,RV32IZHINX,RV32IZDINXZHINX %s
+; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+zdinx \
+; RUN:   -mattr=+zhinx -verify-machineinstrs -target-abi lp64 | \
+; RUN:   FileCheck -check-prefixes=CHECKIZHINX,RV64IZHINX,RV64IZDINXZHINX %s
 ; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 \
 ; RUN:   -verify-machineinstrs | \
 ; RUN:   FileCheck -check-prefix=RV32I %s
 ; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 \
 ; RUN:   -verify-machineinstrs | \
 ; RUN:   FileCheck -check-prefix=RV64I %s
 
 ; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+zfhmin \
 ; RUN:   -verify-machineinstrs -target-abi ilp32f | \
 ; RUN:   FileCheck -check-prefixes=CHECKIZFHMIN,RV32IZFHMIN,RV32IFZFHMIN %s
 ; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+zfhmin \
 ; RUN:   -verify-machineinstrs -target-abi lp64f | \
 ; RUN:   FileCheck -check-prefixes=CHECKIZFHMIN,RV64IZFHMIN,RV64IFZFHMIN %s
 ; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+d \
 ; RUN:   -mattr=+zfhmin -verify-machineinstrs -target-abi ilp32d | \
 ; RUN:   FileCheck -check-prefixes=CHECKIZFHMIN,RV32IZFHMIN,RV32IDZFHMIN %s
 ; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+d \
 ; RUN:   -mattr=+zfhmin -verify-machineinstrs -target-abi lp64d | \
 ; RUN:   FileCheck -check-prefixes=CHECKIZFHMIN,RV64IZFHMIN,RV64IDZFHMIN %s
 
+; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+zhinxmin \
+; RUN:   -verify-machineinstrs -target-abi ilp32 | \
+; RUN:   FileCheck -check-prefixes=CHECKIZHINXMIN,RV32IZHINXMIN %s
+; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+zhinxmin \
+; RUN:   -verify-machineinstrs -target-abi lp64 | \
+; RUN:   FileCheck -check-prefixes=CHECKIZHINXMIN,RV64IZHINXMIN %s
+; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+zdinx \
+; RUN:   -mattr=+zhinxmin -verify-machineinstrs -target-abi ilp32 | \
+; RUN:   FileCheck -check-prefixes=CHECKIZHINXMIN,RV32IZHINXMIN,RV32IZDINXZHINXMIN %s
+; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+zdinx \
+; RUN:   -mattr=+zhinxmin -verify-machineinstrs -target-abi lp64 | \
+; RUN:   FileCheck -check-prefixes=CHECKIZHINXMIN,RV64IZHINXMIN,RV64IZDINXZHINXMIN %s
+
 declare half @llvm.sqrt.f16(half)
 
 define half @sqrt_f16(half %a) nounwind {
 ; CHECKIZFH-LABEL: sqrt_f16:
 ; CHECKIZFH:       # %bb.0:
 ; CHECKIZFH-NEXT:    fsqrt.h fa0, fa0
 ; CHECKIZFH-NEXT:    ret
 ;
+; CHECKIZHINX-LABEL: sqrt_f16:
+; CHECKIZHINX:       # %bb.0:
+; CHECKIZHINX-NEXT:    fsqrt.h a0, a0
+; CHECKIZHINX-NEXT:    ret
+;
 ; RV32I-LABEL: sqrt_f16:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    slli a0, a0, 16
 ; RV32I-NEXT:    srli a0, a0, 16
 ; RV32I-NEXT:    call __extendhfsf2@plt
 ; RV32I-NEXT:    call sqrtf@plt

 ; RV64I-NEXT:    ret
 ;
 ; CHECKIZFHMIN-LABEL: sqrt_f16:
 ; CHECKIZFHMIN:       # %bb.0:
 ; CHECKIZFHMIN-NEXT:    fcvt.s.h fa5, fa0
 ; CHECKIZFHMIN-NEXT:    fsqrt.s fa5, fa5
 ; CHECKIZFHMIN-NEXT:    fcvt.h.s fa0, fa5
 ; CHECKIZFHMIN-NEXT:    ret
+;
+; CHECKIZHINXMIN-LABEL: sqrt_f16:
+; CHECKIZHINXMIN:       # %bb.0:
+; CHECKIZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECKIZHINXMIN-NEXT:    fsqrt.s a0, a0
+; CHECKIZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; CHECKIZHINXMIN-NEXT:    ret
   %1 = call half @llvm.sqrt.f16(half %a)
   ret half %1
 }
 
 declare half @llvm.powi.f16.i32(half, i32)
 
 define half @powi_f16(half %a, i32 %b) nounwind {
 ; RV32IZFH-LABEL: powi_f16:

 ; RV64IZFH-NEXT:    fcvt.s.h fa0, fa0
 ; RV64IZFH-NEXT:    sext.w a0, a0
 ; RV64IZFH-NEXT:    call __powisf2@plt
 ; RV64IZFH-NEXT:    fcvt.h.s fa0, fa0
 ; RV64IZFH-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64IZFH-NEXT:    addi sp, sp, 16
 ; RV64IZFH-NEXT:    ret
 ;
+; RV32IZHINX-LABEL: powi_f16:
+; RV32IZHINX:       # %bb.0:
+; RV32IZHINX-NEXT:    addi sp, sp, -16
+; RV32IZHINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZHINX-NEXT:    fcvt.s.h a0, a0
+; RV32IZHINX-NEXT:    call __powisf2@plt
+; RV32IZHINX-NEXT:    fcvt.h.s a0, a0
+; RV32IZHINX-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZHINX-NEXT:    addi sp, sp, 16
+; RV32IZHINX-NEXT:    ret
+;
+; RV64IZHINX-LABEL: powi_f16:
+; RV64IZHINX:       # %bb.0:
+; RV64IZHINX-NEXT:    addi sp, sp, -16
+; RV64IZHINX-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IZHINX-NEXT:    sext.w a1, a1
+; RV64IZHINX-NEXT:    fcvt.s.h a0, a0
+; RV64IZHINX-NEXT:    call __powisf2@plt
+; RV64IZHINX-NEXT:    fcvt.h.s a0, a0
+; RV64IZHINX-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
+; RV64IZHINX-NEXT:    addi sp, sp, 16
+; RV64IZHINX-NEXT:    ret
+;
 ; RV32I-LABEL: powi_f16:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    mv s0, a1
 ; RV32I-NEXT:    slli a0, a0, 16
 ; RV32I-NEXT:    srli a0, a0, 16

 ; RV64IZFHMIN-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64IZFHMIN-NEXT:    fcvt.s.h fa0, fa0
 ; RV64IZFHMIN-NEXT:    sext.w a0, a0
 ; RV64IZFHMIN-NEXT:    call __powisf2@plt
 ; RV64IZFHMIN-NEXT:    fcvt.h.s fa0, fa0
 ; RV64IZFHMIN-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64IZFHMIN-NEXT:    addi sp, sp, 16
 ; RV64IZFHMIN-NEXT:    ret
+;
+; RV32IZHINXMIN-LABEL: powi_f16:
+; RV32IZHINXMIN:       # %bb.0:
+; RV32IZHINXMIN-NEXT:    addi sp, sp, -16
+; RV32IZHINXMIN-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV32IZHINXMIN-NEXT:    call __powisf2@plt
+; RV32IZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; RV32IZHINXMIN-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZHINXMIN-NEXT:    addi sp, sp, 16
+; RV32IZHINXMIN-NEXT:    ret
+;
+; RV64IZHINXMIN-LABEL: powi_f16:
+; RV64IZHINXMIN:       # %bb.0:
+; RV64IZHINXMIN-NEXT:    addi sp, sp, -16
+; RV64IZHINXMIN-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IZHINXMIN-NEXT:    sext.w a1, a1
+; RV64IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV64IZHINXMIN-NEXT:    call __powisf2@plt
+; RV64IZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; RV64IZHINXMIN-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
+; RV64IZHINXMIN-NEXT:    addi sp, sp, 16
+; RV64IZHINXMIN-NEXT:    ret
   %1 = call half @llvm.powi.f16.i32(half %a, i32 %b)
   ret half %1
 }
 
 declare half @llvm.sin.f16(half)
 
 define half @sin_f16(half %a) nounwind {
 ; RV32IZFH-LABEL: sin_f16:

 ; RV64IZFH-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64IZFH-NEXT:    fcvt.s.h fa0, fa0
 ; RV64IZFH-NEXT:    call sinf@plt
 ; RV64IZFH-NEXT:    fcvt.h.s fa0, fa0
 ; RV64IZFH-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64IZFH-NEXT:    addi sp, sp, 16
 ; RV64IZFH-NEXT:    ret
 ;
+; RV32IZHINX-LABEL: sin_f16:
+; RV32IZHINX:       # %bb.0:
+; RV32IZHINX-NEXT:    addi sp, sp, -16
+; RV32IZHINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZHINX-NEXT:    fcvt.s.h a0, a0
+; RV32IZHINX-NEXT:    call sinf@plt
+; RV32IZHINX-NEXT:    fcvt.h.s a0, a0
+; RV32IZHINX-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZHINX-NEXT:    addi sp, sp, 16
+; RV32IZHINX-NEXT:    ret
+;
+; RV64IZHINX-LABEL: sin_f16:
+; RV64IZHINX:       # %bb.0:
+; RV64IZHINX-NEXT:    addi sp, sp, -16
+; RV64IZHINX-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IZHINX-NEXT:    fcvt.s.h a0, a0
+; RV64IZHINX-NEXT:    call sinf@plt
+; RV64IZHINX-NEXT:    fcvt.h.s a0, a0
+; RV64IZHINX-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
+; RV64IZHINX-NEXT:    addi sp, sp, 16
+; RV64IZHINX-NEXT:    ret
+;
 ; RV32I-LABEL: sin_f16:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    slli a0, a0, 16
 ; RV32I-NEXT:    srli a0, a0, 16
 ; RV32I-NEXT:    call __extendhfsf2@plt
 ; RV32I-NEXT:    call sinf@plt

 ; RV64IZFHMIN-NEXT:    addi sp, sp, -16
 ; RV64IZFHMIN-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64IZFHMIN-NEXT:    fcvt.s.h fa0, fa0
 ; RV64IZFHMIN-NEXT:    call sinf@plt
 ; RV64IZFHMIN-NEXT:    fcvt.h.s fa0, fa0
 ; RV64IZFHMIN-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64IZFHMIN-NEXT:    addi sp, sp, 16
 ; RV64IZFHMIN-NEXT:    ret
+;
+; RV32IZHINXMIN-LABEL: sin_f16:
+; RV32IZHINXMIN:       # %bb.0:
+; RV32IZHINXMIN-NEXT:    addi sp, sp, -16
+; RV32IZHINXMIN-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV32IZHINXMIN-NEXT:    call sinf@plt
+; RV32IZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; RV32IZHINXMIN-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZHINXMIN-NEXT:    addi sp, sp, 16
+; RV32IZHINXMIN-NEXT:    ret
+;
+; RV64IZHINXMIN-LABEL: sin_f16:
+; RV64IZHINXMIN:       # %bb.0:
+; RV64IZHINXMIN-NEXT:    addi sp, sp, -16
+; RV64IZHINXMIN-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV64IZHINXMIN-NEXT:    call sinf@plt
+; RV64IZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; RV64IZHINXMIN-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
+; RV64IZHINXMIN-NEXT:    addi sp, sp, 16
+; RV64IZHINXMIN-NEXT:    ret
   %1 = call half @llvm.sin.f16(half %a)
   ret half %1
 }
 
 declare half @llvm.cos.f16(half)
 
 define half @cos_f16(half %a) nounwind {
 ; RV32IZFH-LABEL: cos_f16:

 ; RV64IZFH-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64IZFH-NEXT:    fcvt.s.h fa0, fa0
 ; RV64IZFH-NEXT:    call cosf@plt
 ; RV64IZFH-NEXT:    fcvt.h.s fa0, fa0
 ; RV64IZFH-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64IZFH-NEXT:    addi sp, sp, 16
 ; RV64IZFH-NEXT:    ret
 ;
+; RV32IZHINX-LABEL: cos_f16:
+; RV32IZHINX:       # %bb.0:
+; RV32IZHINX-NEXT:    addi sp, sp, -16
+; RV32IZHINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZHINX-NEXT:    fcvt.s.h a0, a0
+; RV32IZHINX-NEXT:    call cosf@plt
+; RV32IZHINX-NEXT:    fcvt.h.s a0, a0
+; RV32IZHINX-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZHINX-NEXT:    addi sp, sp, 16
+; RV32IZHINX-NEXT:    ret
+;
+; RV64IZHINX-LABEL: cos_f16:
+; RV64IZHINX:       # %bb.0:
+; RV64IZHINX-NEXT:    addi sp, sp, -16
+; RV64IZHINX-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IZHINX-NEXT:    fcvt.s.h a0, a0
+; RV64IZHINX-NEXT:    call cosf@plt
+; RV64IZHINX-NEXT:    fcvt.h.s a0, a0
+; RV64IZHINX-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
+; RV64IZHINX-NEXT:    addi sp, sp, 16
+; RV64IZHINX-NEXT:    ret
+;
 ; RV32I-LABEL: cos_f16:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    slli a0, a0, 16
 ; RV32I-NEXT:    srli a0, a0, 16
 ; RV32I-NEXT:    call __extendhfsf2@plt
 ; RV32I-NEXT:    call cosf@plt

 ; RV64IZFHMIN-NEXT:    addi sp, sp, -16
 ; RV64IZFHMIN-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64IZFHMIN-NEXT:    fcvt.s.h fa0, fa0
 ; RV64IZFHMIN-NEXT:    call cosf@plt
 ; RV64IZFHMIN-NEXT:    fcvt.h.s fa0, fa0
 ; RV64IZFHMIN-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64IZFHMIN-NEXT:    addi sp, sp, 16
 ; RV64IZFHMIN-NEXT:    ret
+;
+; RV32IZHINXMIN-LABEL: cos_f16:
+; RV32IZHINXMIN:       # %bb.0:
+; RV32IZHINXMIN-NEXT:    addi sp, sp, -16
+; RV32IZHINXMIN-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV32IZHINXMIN-NEXT:    call cosf@plt
+; RV32IZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; RV32IZHINXMIN-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZHINXMIN-NEXT:    addi sp, sp, 16
+; RV32IZHINXMIN-NEXT:    ret
+;
+; RV64IZHINXMIN-LABEL: cos_f16:
+; RV64IZHINXMIN:       # %bb.0:
+; RV64IZHINXMIN-NEXT:    addi sp, sp, -16
+; RV64IZHINXMIN-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV64IZHINXMIN-NEXT:    call cosf@plt
+; RV64IZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; RV64IZHINXMIN-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
+; RV64IZHINXMIN-NEXT:    addi sp, sp, 16
+; RV64IZHINXMIN-NEXT:    ret
   %1 = call half @llvm.cos.f16(half %a)
   ret half %1
 }
 
 ; The sin+cos combination results in an FSINCOS SelectionDAG node.
 define half @sincos_f16(half %a) nounwind {
 ; RV32IFZFH-LABEL: sincos_f16:
 ; RV32IFZFH:       # %bb.0:

 ; RV64IFZFH-NEXT:    fcvt.h.s fa5, fa0
 ; RV64IFZFH-NEXT:    fadd.h fa0, fs1, fa5
 ; RV64IFZFH-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64IFZFH-NEXT:    flw fs0, 4(sp) # 4-byte Folded Reload
 ; RV64IFZFH-NEXT:    flw fs1, 0(sp) # 4-byte Folded Reload
 ; RV64IFZFH-NEXT:    addi sp, sp, 16
 ; RV64IFZFH-NEXT:    ret
 ;
+; RV32IZHINX-LABEL: sincos_f16:
+; RV32IZHINX:       # %bb.0:
+; RV32IZHINX-NEXT:    addi sp, sp, -16
+; RV32IZHINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZHINX-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
+; RV32IZHINX-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
+; RV32IZHINX-NEXT:    fcvt.s.h s0, a0
+; RV32IZHINX-NEXT:    mv a0, s0
+; RV32IZHINX-NEXT:    call sinf@plt
+; RV32IZHINX-NEXT:    fcvt.h.s s1, a0
+; RV32IZHINX-NEXT:    mv a0, s0
+; RV32IZHINX-NEXT:    call cosf@plt
+; RV32IZHINX-NEXT:    fcvt.h.s a0, a0
+; RV32IZHINX-NEXT:    fadd.h a0, s1, a0
+; RV32IZHINX-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZHINX-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
+; RV32IZHINX-NEXT:    lw s1, 4(sp) # 4-byte Folded Reload
+; RV32IZHINX-NEXT:    addi sp, sp, 16
+; RV32IZHINX-NEXT:    ret
+;
+; RV64IZHINX-LABEL: sincos_f16:
+; RV64IZHINX:       # %bb.0:
+; RV64IZHINX-NEXT:    addi sp, sp, -32
+; RV64IZHINX-NEXT:    sd ra, 24(sp) # 8-byte Folded Spill
+; RV64IZHINX-NEXT:    sd s0, 16(sp) # 8-byte Folded Spill
+; RV64IZHINX-NEXT:    sd s1, 8(sp) # 8-byte Folded Spill
+; RV64IZHINX-NEXT:    fcvt.s.h s0, a0
+; RV64IZHINX-NEXT:    mv a0, s0
+; RV64IZHINX-NEXT:    call sinf@plt
+; RV64IZHINX-NEXT:    fcvt.h.s s1, a0
+; RV64IZHINX-NEXT:    mv a0, s0
+; RV64IZHINX-NEXT:    call cosf@plt
+; RV64IZHINX-NEXT:    fcvt.h.s a0, a0
+; RV64IZHINX-NEXT:    fadd.h a0, s1, a0
+; RV64IZHINX-NEXT:    ld ra, 24(sp) # 8-byte Folded Reload
+; RV64IZHINX-NEXT:    ld s0, 16(sp) # 8-byte Folded Reload
+; RV64IZHINX-NEXT:    ld s1, 8(sp) # 8-byte Folded Reload
+; RV64IZHINX-NEXT:    addi sp, sp, 32
+; RV64IZHINX-NEXT:    ret
+;
 ; RV32IDZFH-LABEL: sincos_f16:
 ; RV32IDZFH:       # %bb.0:
 ; RV32IDZFH-NEXT:    addi sp, sp, -32
 ; RV32IDZFH-NEXT:    sw ra, 28(sp) # 4-byte Folded Spill
 ; RV32IDZFH-NEXT:    fsd fs0, 16(sp) # 8-byte Folded Spill
 ; RV32IDZFH-NEXT:    fsd fs1, 8(sp) # 8-byte Folded Spill
 ; RV32IDZFH-NEXT:    fcvt.s.h fs0, fa0
 ; RV32IDZFH-NEXT:    fmv.s fa0, fs0

 ; RV64IDZFHMIN-NEXT:    fcvt.s.h fa4, fs1
 ; RV64IDZFHMIN-NEXT:    fadd.s fa5, fa4, fa5
 ; RV64IDZFHMIN-NEXT:    fcvt.h.s fa0, fa5
 ; RV64IDZFHMIN-NEXT:    ld ra, 24(sp) # 8-byte Folded Reload
 ; RV64IDZFHMIN-NEXT:    fld fs0, 16(sp) # 8-byte Folded Reload
 ; RV64IDZFHMIN-NEXT:    fld fs1, 8(sp) # 8-byte Folded Reload
 ; RV64IDZFHMIN-NEXT:    addi sp, sp, 32
 ; RV64IDZFHMIN-NEXT:    ret
+;
+; RV32IZHINXMIN-LABEL: sincos_f16:
+; RV32IZHINXMIN:       # %bb.0:
+; RV32IZHINXMIN-NEXT:    addi sp, sp, -16
+; RV32IZHINXMIN-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZHINXMIN-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
+; RV32IZHINXMIN-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
+; RV32IZHINXMIN-NEXT:    fcvt.s.h s0, a0
+; RV32IZHINXMIN-NEXT:    mv a0, s0
+; RV32IZHINXMIN-NEXT:    call sinf@plt
+; RV32IZHINXMIN-NEXT:    fcvt.h.s s1, a0
+; RV32IZHINXMIN-NEXT:    mv a0, s0
+; RV32IZHINXMIN-NEXT:    call cosf@plt
+; RV32IZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; RV32IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV32IZHINXMIN-NEXT:    fcvt.s.h a1, s1
+; RV32IZHINXMIN-NEXT:    fadd.s a0, a1, a0
+; RV32IZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; RV32IZHINXMIN-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZHINXMIN-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
+; RV32IZHINXMIN-NEXT:    lw s1, 4(sp) # 4-byte Folded Reload
+; RV32IZHINXMIN-NEXT:    addi sp, sp, 16
+; RV32IZHINXMIN-NEXT:    ret
+;
+; RV64IZHINXMIN-LABEL: sincos_f16:
+; RV64IZHINXMIN:       # %bb.0:
+; RV64IZHINXMIN-NEXT:    addi sp, sp, -32
+; RV64IZHINXMIN-NEXT:    sd ra, 24(sp) # 8-byte Folded Spill
+; RV64IZHINXMIN-NEXT:    sd s0, 16(sp) # 8-byte Folded Spill
+; RV64IZHINXMIN-NEXT:    sd s1, 8(sp) # 8-byte Folded Spill
+; RV64IZHINXMIN-NEXT:    fcvt.s.h s0, a0
+; RV64IZHINXMIN-NEXT:    mv a0, s0
+; RV64IZHINXMIN-NEXT:    call sinf@plt
+; RV64IZHINXMIN-NEXT:    fcvt.h.s s1, a0
+; RV64IZHINXMIN-NEXT:    mv a0, s0
+; RV64IZHINXMIN-NEXT:    call cosf@plt
+; RV64IZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; RV64IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV64IZHINXMIN-NEXT:    fcvt.s.h a1, s1
+; RV64IZHINXMIN-NEXT:    fadd.s a0, a1, a0
+; RV64IZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; RV64IZHINXMIN-NEXT:    ld ra, 24(sp) # 8-byte Folded Reload
+; RV64IZHINXMIN-NEXT:    ld s0, 16(sp) # 8-byte Folded Reload
+; RV64IZHINXMIN-NEXT:    ld s1, 8(sp) # 8-byte Folded Reload
+; RV64IZHINXMIN-NEXT:    addi sp, sp, 32
+; RV64IZHINXMIN-NEXT:    ret
   %1 = call half @llvm.sin.f16(half %a)
   %2 = call half @llvm.cos.f16(half %a)
   %3 = fadd half %1, %2
   ret half %3
 }
 
 declare half @llvm.pow.f16(half, half)
 

 ; RV64IZFH-NEXT:    fcvt.s.h fa0, fa0
 ; RV64IZFH-NEXT:    fcvt.s.h fa1, fa1
 ; RV64IZFH-NEXT:    call powf@plt
 ; RV64IZFH-NEXT:    fcvt.h.s fa0, fa0
 ; RV64IZFH-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64IZFH-NEXT:    addi sp, sp, 16
 ; RV64IZFH-NEXT:    ret
 ;
+; RV32IZHINX-LABEL: pow_f16:
+; RV32IZHINX:       # %bb.0:
+; RV32IZHINX-NEXT:    addi sp, sp, -16
+; RV32IZHINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZHINX-NEXT:    fcvt.s.h a0, a0
+; RV32IZHINX-NEXT:    fcvt.s.h a1, a1
+; RV32IZHINX-NEXT:    call powf@plt
+; RV32IZHINX-NEXT:    fcvt.h.s a0, a0
+; RV32IZHINX-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZHINX-NEXT:    addi sp, sp, 16
+; RV32IZHINX-NEXT:    ret
+;
+; RV64IZHINX-LABEL: pow_f16:
+; RV64IZHINX:       # %bb.0:
+; RV64IZHINX-NEXT:    addi sp, sp, -16
+; RV64IZHINX-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IZHINX-NEXT:    fcvt.s.h a0, a0
+; RV64IZHINX-NEXT:    fcvt.s.h a1, a1
+; RV64IZHINX-NEXT:    call powf@plt
+; RV64IZHINX-NEXT:    fcvt.h.s a0, a0
+; RV64IZHINX-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
+; RV64IZHINX-NEXT:    addi sp, sp, 16
+; RV64IZHINX-NEXT:    ret
+;
 ; RV32I-LABEL: pow_f16:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s2, 0(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    mv s0, a1

 ; RV64IZFHMIN-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64IZFHMIN-NEXT:    fcvt.s.h fa0, fa0
 ; RV64IZFHMIN-NEXT:    fcvt.s.h fa1, fa1
 ; RV64IZFHMIN-NEXT:    call powf@plt
 ; RV64IZFHMIN-NEXT:    fcvt.h.s fa0, fa0
 ; RV64IZFHMIN-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64IZFHMIN-NEXT:    addi sp, sp, 16
 ; RV64IZFHMIN-NEXT:    ret
+;
+; RV32IZHINXMIN-LABEL: pow_f16:
+; RV32IZHINXMIN:       # %bb.0:
+; RV32IZHINXMIN-NEXT:    addi sp, sp, -16
+; RV32IZHINXMIN-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV32IZHINXMIN-NEXT:    fcvt.s.h a1, a1
+; RV32IZHINXMIN-NEXT:    call powf@plt
+; RV32IZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; RV32IZHINXMIN-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZHINXMIN-NEXT:    addi sp, sp, 16
+; RV32IZHINXMIN-NEXT:    ret
+;
+; RV64IZHINXMIN-LABEL: pow_f16:
+; RV64IZHINXMIN:       # %bb.0:
+; RV64IZHINXMIN-NEXT:    addi sp, sp, -16
+; RV64IZHINXMIN-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV64IZHINXMIN-NEXT:    fcvt.s.h a1, a1
+; RV64IZHINXMIN-NEXT:    call powf@plt
+; RV64IZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; RV64IZHINXMIN-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
+; RV64IZHINXMIN-NEXT:    addi sp, sp, 16
+; RV64IZHINXMIN-NEXT:    ret
   %1 = call half @llvm.pow.f16(half %a, half %b)
   ret half %1
 }
 
 declare half @llvm.exp.f16(half)
 
 define half @exp_f16(half %a) nounwind {
 ; RV32IZFH-LABEL: exp_f16:

 ; RV64IZFH-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64IZFH-NEXT:    fcvt.s.h fa0, fa0
 ; RV64IZFH-NEXT:    call expf@plt
 ; RV64IZFH-NEXT:    fcvt.h.s fa0, fa0
 ; RV64IZFH-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64IZFH-NEXT:    addi sp, sp, 16
 ; RV64IZFH-NEXT:    ret
 ;
+; RV32IZHINX-LABEL: exp_f16:
+; RV32IZHINX:       # %bb.0:
+; RV32IZHINX-NEXT:    addi sp, sp, -16
+; RV32IZHINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZHINX-NEXT:    fcvt.s.h a0, a0
+; RV32IZHINX-NEXT:    call expf@plt
+; RV32IZHINX-NEXT:    fcvt.h.s a0, a0
+; RV32IZHINX-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZHINX-NEXT:    addi sp, sp, 16
+; RV32IZHINX-NEXT:    ret
+;
+; RV64IZHINX-LABEL: exp_f16:
+; RV64IZHINX:       # %bb.0:
+; RV64IZHINX-NEXT:    addi sp, sp, -16
+; RV64IZHINX-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IZHINX-NEXT:    fcvt.s.h a0, a0
+; RV64IZHINX-NEXT:    call expf@plt
+; RV64IZHINX-NEXT:    fcvt.h.s a0, a0
+; RV64IZHINX-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
+; RV64IZHINX-NEXT:    addi sp, sp, 16
+; RV64IZHINX-NEXT:    ret
+;
 ; RV32I-LABEL: exp_f16:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    slli a0, a0, 16
 ; RV32I-NEXT:    srli a0, a0, 16
 ; RV32I-NEXT:    call __extendhfsf2@plt
 ; RV32I-NEXT:    call expf@plt

 ; RV64IZFHMIN-NEXT:    addi sp, sp, -16
 ; RV64IZFHMIN-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64IZFHMIN-NEXT:    fcvt.s.h fa0, fa0
 ; RV64IZFHMIN-NEXT:    call expf@plt
 ; RV64IZFHMIN-NEXT:    fcvt.h.s fa0, fa0
 ; RV64IZFHMIN-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64IZFHMIN-NEXT:    addi sp, sp, 16
 ; RV64IZFHMIN-NEXT:    ret
+;
+; RV32IZHINXMIN-LABEL: exp_f16:
+; RV32IZHINXMIN:       # %bb.0:
+; RV32IZHINXMIN-NEXT:    addi sp, sp, -16
+; RV32IZHINXMIN-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV32IZHINXMIN-NEXT:    call expf@plt
+; RV32IZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; RV32IZHINXMIN-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZHINXMIN-NEXT:    addi sp, sp, 16
+; RV32IZHINXMIN-NEXT:    ret
+;
+; RV64IZHINXMIN-LABEL: exp_f16:
+; RV64IZHINXMIN:       # %bb.0:
+; RV64IZHINXMIN-NEXT:    addi sp, sp, -16
+; RV64IZHINXMIN-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV64IZHINXMIN-NEXT:    call expf@plt
+; RV64IZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; RV64IZHINXMIN-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
+; RV64IZHINXMIN-NEXT:    addi sp, sp, 16
+; RV64IZHINXMIN-NEXT:    ret
   %1 = call half @llvm.exp.f16(half %a)
   ret half %1
 }
 
 declare half @llvm.exp2.f16(half)
 
 define half @exp2_f16(half %a) nounwind {
 ; RV32IZFH-LABEL: exp2_f16:

 ; RV64IZFH-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64IZFH-NEXT:    fcvt.s.h fa0, fa0
 ; RV64IZFH-NEXT:    call exp2f@plt
 ; RV64IZFH-NEXT:    fcvt.h.s fa0, fa0
 ; RV64IZFH-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64IZFH-NEXT:    addi sp, sp, 16
 ; RV64IZFH-NEXT:    ret
 ;
+; RV32IZHINX-LABEL: exp2_f16:
+; RV32IZHINX:       # %bb.0:
+; RV32IZHINX-NEXT:    addi sp, sp, -16
+; RV32IZHINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZHINX-NEXT:    fcvt.s.h a0, a0
+; RV32IZHINX-NEXT:    call exp2f@plt
+; RV32IZHINX-NEXT:    fcvt.h.s a0, a0
+; RV32IZHINX-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZHINX-NEXT:    addi sp, sp, 16
+; RV32IZHINX-NEXT:    ret
+;
+; RV64IZHINX-LABEL: exp2_f16:
+; RV64IZHINX:       # %bb.0:
+; RV64IZHINX-NEXT:    addi sp, sp, -16
+; RV64IZHINX-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IZHINX-NEXT:    fcvt.s.h a0, a0
+; RV64IZHINX-NEXT:    call exp2f@plt
+; RV64IZHINX-NEXT:    fcvt.h.s a0, a0
+; RV64IZHINX-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
+; RV64IZHINX-NEXT:    addi sp, sp, 16
+; RV64IZHINX-NEXT:    ret
+;
 ; RV32I-LABEL: exp2_f16:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    slli a0, a0, 16
 ; RV32I-NEXT:    srli a0, a0, 16
 ; RV32I-NEXT:    call __extendhfsf2@plt
 ; RV32I-NEXT:    call exp2f@plt

 ; RV64IZFHMIN-NEXT:    addi sp, sp, -16
 ; RV64IZFHMIN-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64IZFHMIN-NEXT:    fcvt.s.h fa0, fa0
 ; RV64IZFHMIN-NEXT:    call exp2f@plt
 ; RV64IZFHMIN-NEXT:    fcvt.h.s fa0, fa0
 ; RV64IZFHMIN-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64IZFHMIN-NEXT:    addi sp, sp, 16
 ; RV64IZFHMIN-NEXT:    ret
+;
+; RV32IZHINXMIN-LABEL: exp2_f16:
+; RV32IZHINXMIN:       # %bb.0:
+; RV32IZHINXMIN-NEXT:    addi sp, sp, -16
+; RV32IZHINXMIN-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV32IZHINXMIN-NEXT:    call exp2f@plt
+; RV32IZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; RV32IZHINXMIN-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZHINXMIN-NEXT:    addi sp, sp, 16
+; RV32IZHINXMIN-NEXT:    ret
+;
+; RV64IZHINXMIN-LABEL: exp2_f16:
+; RV64IZHINXMIN:       # %bb.0:
+; RV64IZHINXMIN-NEXT:    addi sp, sp, -16
+; RV64IZHINXMIN-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV64IZHINXMIN-NEXT:    call exp2f@plt
+; RV64IZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; RV64IZHINXMIN-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
+; RV64IZHINXMIN-NEXT:    addi sp, sp, 16
+; RV64IZHINXMIN-NEXT:    ret
   %1 = call half @llvm.exp2.f16(half %a)
   ret half %1
 }
 
 declare half @llvm.log.f16(half)
 
 define half @log_f16(half %a) nounwind {
 ; RV32IZFH-LABEL: log_f16:

 ; RV64IZFH-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64IZFH-NEXT:    fcvt.s.h fa0, fa0
 ; RV64IZFH-NEXT:    call logf@plt
 ; RV64IZFH-NEXT:    fcvt.h.s fa0, fa0
 ; RV64IZFH-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64IZFH-NEXT:    addi sp, sp, 16
 ; RV64IZFH-NEXT:    ret
 ;
+; RV32IZHINX-LABEL: log_f16:
+; RV32IZHINX:       # %bb.0:
+; RV32IZHINX-NEXT:    addi sp, sp, -16
+; RV32IZHINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZHINX-NEXT:    fcvt.s.h a0, a0
+; RV32IZHINX-NEXT:    call logf@plt
+; RV32IZHINX-NEXT:    fcvt.h.s a0, a0
+; RV32IZHINX-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZHINX-NEXT:    addi sp, sp, 16
+; RV32IZHINX-NEXT:    ret
+;
+; RV64IZHINX-LABEL: log_f16:
+; RV64IZHINX:       # %bb.0:
+; RV64IZHINX-NEXT:    addi sp, sp, -16
+; RV64IZHINX-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IZHINX-NEXT:    fcvt.s.h a0, a0
+; RV64IZHINX-NEXT:    call logf@plt
+; RV64IZHINX-NEXT:    fcvt.h.s a0, a0
+; RV64IZHINX-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
+; RV64IZHINX-NEXT:    addi sp, sp, 16
+; RV64IZHINX-NEXT:    ret
+;
 ; RV32I-LABEL: log_f16:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    slli a0, a0, 16
 ; RV32I-NEXT:    srli a0, a0, 16
 ; RV32I-NEXT:    call __extendhfsf2@plt
 ; RV32I-NEXT:    call logf@plt

 ; RV64IZFHMIN-NEXT:    addi sp, sp, -16
 ; RV64IZFHMIN-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64IZFHMIN-NEXT:    fcvt.s.h fa0, fa0
 ; RV64IZFHMIN-NEXT:    call logf@plt
 ; RV64IZFHMIN-NEXT:    fcvt.h.s fa0, fa0
 ; RV64IZFHMIN-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64IZFHMIN-NEXT:    addi sp, sp, 16
 ; RV64IZFHMIN-NEXT:    ret
+;
+; RV32IZHINXMIN-LABEL: log_f16:
+; RV32IZHINXMIN:       # %bb.0:
+; RV32IZHINXMIN-NEXT:    addi sp, sp, -16
+; RV32IZHINXMIN-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV32IZHINXMIN-NEXT:    call logf@plt
+; RV32IZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; RV32IZHINXMIN-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZHINXMIN-NEXT:    addi sp, sp, 16
+; RV32IZHINXMIN-NEXT:    ret
+;
+; RV64IZHINXMIN-LABEL: log_f16:
+; RV64IZHINXMIN:       # %bb.0:
+; RV64IZHINXMIN-NEXT:    addi sp, sp, -16
+; RV64IZHINXMIN-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV64IZHINXMIN-NEXT:    call logf@plt
+; RV64IZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; RV64IZHINXMIN-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
+; RV64IZHINXMIN-NEXT:    addi sp, sp, 16
+; RV64IZHINXMIN-NEXT:    ret
   %1 = call half @llvm.log.f16(half %a)
   ret half %1
 }
 
 declare half @llvm.log10.f16(half)
 
 define half @log10_f16(half %a) nounwind {
 ; RV32IZFH-LABEL: log10_f16:

 ; RV64IZFH-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64IZFH-NEXT:    fcvt.s.h fa0, fa0
 ; RV64IZFH-NEXT:    call log10f@plt
 ; RV64IZFH-NEXT:    fcvt.h.s fa0, fa0
 ; RV64IZFH-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64IZFH-NEXT:    addi sp, sp, 16
 ; RV64IZFH-NEXT:    ret
 ;
+; RV32IZHINX-LABEL: log10_f16:
+; RV32IZHINX:       # %bb.0:
+; RV32IZHINX-NEXT:    addi sp, sp, -16
+; RV32IZHINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZHINX-NEXT:    fcvt.s.h a0, a0
+; RV32IZHINX-NEXT:    call log10f@plt
+; RV32IZHINX-NEXT:    fcvt.h.s a0, a0
+; RV32IZHINX-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZHINX-NEXT:    addi sp, sp, 16
+; RV32IZHINX-NEXT:    ret
+;
+; RV64IZHINX-LABEL: log10_f16:
+; RV64IZHINX:       # %bb.0:
+; RV64IZHINX-NEXT:    addi sp, sp, -16
+; RV64IZHINX-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IZHINX-NEXT:    fcvt.s.h a0, a0
+; RV64IZHINX-NEXT:    call log10f@plt
+; RV64IZHINX-NEXT:    fcvt.h.s a0, a0
+; RV64IZHINX-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
+; RV64IZHINX-NEXT:    addi sp, sp, 16
+; RV64IZHINX-NEXT:    ret
+;
 ; RV32I-LABEL: log10_f16:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    slli a0, a0, 16
 ; RV32I-NEXT:    srli a0, a0, 16
 ; RV32I-NEXT:    call __extendhfsf2@plt
 ; RV32I-NEXT:    call log10f@plt

 ; RV64IZFHMIN-NEXT:    addi sp, sp, -16
 ; RV64IZFHMIN-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64IZFHMIN-NEXT:    fcvt.s.h fa0, fa0
 ; RV64IZFHMIN-NEXT:    call log10f@plt
 ; RV64IZFHMIN-NEXT:    fcvt.h.s fa0, fa0
 ; RV64IZFHMIN-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64IZFHMIN-NEXT:    addi sp, sp, 16
 ; RV64IZFHMIN-NEXT:    ret
+;
+; RV32IZHINXMIN-LABEL: log10_f16:
+; RV32IZHINXMIN:       # %bb.0:
+; RV32IZHINXMIN-NEXT:    addi sp, sp, -16
+; RV32IZHINXMIN-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV32IZHINXMIN-NEXT:    call log10f@plt
+; RV32IZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; RV32IZHINXMIN-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZHINXMIN-NEXT:    addi sp, sp, 16
+; RV32IZHINXMIN-NEXT:    ret
+;
+; RV64IZHINXMIN-LABEL: log10_f16:
+; RV64IZHINXMIN:       # %bb.0:
+; RV64IZHINXMIN-NEXT:    addi sp, sp, -16
+; RV64IZHINXMIN-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV64IZHINXMIN-NEXT:    call log10f@plt
+; RV64IZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; RV64IZHINXMIN-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
+; RV64IZHINXMIN-NEXT:    addi sp, sp, 16
+; RV64IZHINXMIN-NEXT:    ret
   %1 = call half @llvm.log10.f16(half %a)
   ret half %1
 }
 
 declare half @llvm.log2.f16(half)
 
 define half @log2_f16(half %a) nounwind {
 ; RV32IZFH-LABEL: log2_f16:

 ; RV64IZFH-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64IZFH-NEXT:    fcvt.s.h fa0, fa0
 ; RV64IZFH-NEXT:    call log2f@plt
 ; RV64IZFH-NEXT:    fcvt.h.s fa0, fa0
 ; RV64IZFH-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64IZFH-NEXT:    addi sp, sp, 16
 ; RV64IZFH-NEXT:    ret
 ;
+; RV32IZHINX-LABEL: log2_f16:
+; RV32IZHINX:       # %bb.0:
+; RV32IZHINX-NEXT:    addi sp, sp, -16
+; RV32IZHINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZHINX-NEXT:    fcvt.s.h a0, a0
+; RV32IZHINX-NEXT:    call log2f@plt
+; RV32IZHINX-NEXT:    fcvt.h.s a0, a0
+; RV32IZHINX-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZHINX-NEXT:    addi sp, sp, 16
+; RV32IZHINX-NEXT:    ret
+;
+; RV64IZHINX-LABEL: log2_f16:
+; RV64IZHINX:       # %bb.0:
+; RV64IZHINX-NEXT:    addi sp, sp, -16
+; RV64IZHINX-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IZHINX-NEXT:    fcvt.s.h a0, a0
+; RV64IZHINX-NEXT:    call log2f@plt
+; RV64IZHINX-NEXT:    fcvt.h.s a0, a0
+; RV64IZHINX-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
+; RV64IZHINX-NEXT:    addi sp, sp, 16
+; RV64IZHINX-NEXT:    ret
+;
 ; RV32I-LABEL: log2_f16:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    slli a0, a0, 16
 ; RV32I-NEXT:    srli a0, a0, 16
 ; RV32I-NEXT:    call __extendhfsf2@plt
 ; RV32I-NEXT:    call log2f@plt

 ; RV64IZFHMIN-NEXT:    addi sp, sp, -16
 ; RV64IZFHMIN-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64IZFHMIN-NEXT:    fcvt.s.h fa0, fa0
 ; RV64IZFHMIN-NEXT:    call log2f@plt
 ; RV64IZFHMIN-NEXT:    fcvt.h.s fa0, fa0
 ; RV64IZFHMIN-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64IZFHMIN-NEXT:    addi sp, sp, 16
 ; RV64IZFHMIN-NEXT:    ret
+;
+; RV32IZHINXMIN-LABEL: log2_f16:
+; RV32IZHINXMIN:       # %bb.0:
+; RV32IZHINXMIN-NEXT:    addi sp, sp, -16
+; RV32IZHINXMIN-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV32IZHINXMIN-NEXT:    call log2f@plt
+; RV32IZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; RV32IZHINXMIN-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZHINXMIN-NEXT:    addi sp, sp, 16
+; RV32IZHINXMIN-NEXT:    ret
+;
+; RV64IZHINXMIN-LABEL: log2_f16:
+; RV64IZHINXMIN:       # %bb.0:
+; RV64IZHINXMIN-NEXT:    addi sp, sp, -16
+; RV64IZHINXMIN-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV64IZHINXMIN-NEXT:    call log2f@plt
+; RV64IZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; RV64IZHINXMIN-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
+; RV64IZHINXMIN-NEXT:    addi sp, sp, 16
+; RV64IZHINXMIN-NEXT:    ret
   %1 = call half @llvm.log2.f16(half %a)
   ret half %1
 }
 
 declare half @llvm.fma.f16(half, half, half)
 
 define half @fma_f16(half %a, half %b, half %c) nounwind {
 ; CHECKIZFH-LABEL: fma_f16:
 ; CHECKIZFH:       # %bb.0:
 ; CHECKIZFH-NEXT:    fmadd.h fa0, fa0, fa1, fa2
 ; CHECKIZFH-NEXT:    ret
 ;
+; CHECKIZHINX-LABEL: fma_f16:
+; CHECKIZHINX:       # %bb.0:
+; CHECKIZHINX-NEXT:    fmadd.h a0, a0, a1, a2
+; CHECKIZHINX-NEXT:    ret
+;
 ; RV32I-LABEL: fma_f16:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -32
 ; RV32I-NEXT:    sw ra, 28(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s0, 24(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s1, 20(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s2, 16(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s3, 12(sp) # 4-byte Folded Spill

 ; CHECKIZFHMIN-LABEL: fma_f16:
 ; CHECKIZFHMIN:       # %bb.0:
 ; CHECKIZFHMIN-NEXT:    fcvt.s.h fa5, fa2
 ; CHECKIZFHMIN-NEXT:    fcvt.s.h fa4, fa1
 ; CHECKIZFHMIN-NEXT:    fcvt.s.h fa3, fa0
 ; CHECKIZFHMIN-NEXT:    fmadd.s fa5, fa3, fa4, fa5
 ; CHECKIZFHMIN-NEXT:    fcvt.h.s fa0, fa5
 ; CHECKIZFHMIN-NEXT:    ret
+;
+; CHECKIZHINXMIN-LABEL: fma_f16:
+; CHECKIZHINXMIN:       # %bb.0:
+; CHECKIZHINXMIN-NEXT:    fcvt.s.h a2, a2
+; CHECKIZHINXMIN-NEXT:    fcvt.s.h a1, a1
+; CHECKIZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECKIZHINXMIN-NEXT:    fmadd.s a0, a0, a1, a2
+; CHECKIZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; CHECKIZHINXMIN-NEXT:    ret
   %1 = call half @llvm.fma.f16(half %a, half %b, half %c)
   ret half %1
 }
 
 declare half @llvm.fmuladd.f16(half, half, half)
 
 define half @fmuladd_f16(half %a, half %b, half %c) nounwind {
 ; CHECKIZFH-LABEL: fmuladd_f16:
 ; CHECKIZFH:       # %bb.0:
 ; CHECKIZFH-NEXT:    fmadd.h fa0, fa0, fa1, fa2
 ; CHECKIZFH-NEXT:    ret
 ;
+; CHECKIZHINX-LABEL: fmuladd_f16:
+; CHECKIZHINX:       # %bb.0:
+; CHECKIZHINX-NEXT:    fmadd.h a0, a0, a1, a2
+; CHECKIZHINX-NEXT:    ret
+;
 ; RV32I-LABEL: fmuladd_f16:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -32
 ; RV32I-NEXT:    sw ra, 28(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s0, 24(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s1, 20(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s2, 16(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s3, 12(sp) # 4-byte Folded Spill

 ; CHECKIZFHMIN-NEXT:    fcvt.s.h fa4, fa0
 ; CHECKIZFHMIN-NEXT:    fmul.s fa5, fa4, fa5
 ; CHECKIZFHMIN-NEXT:    fcvt.h.s fa5, fa5
 ; CHECKIZFHMIN-NEXT:    fcvt.s.h fa5, fa5
 ; CHECKIZFHMIN-NEXT:    fcvt.s.h fa4, fa2
 ; CHECKIZFHMIN-NEXT:    fadd.s fa5, fa5, fa4
 ; CHECKIZFHMIN-NEXT:    fcvt.h.s fa0, fa5
 ; CHECKIZFHMIN-NEXT:    ret
+;
+; CHECKIZHINXMIN-LABEL: fmuladd_f16:
+; CHECKIZHINXMIN:       # %bb.0:
+; CHECKIZHINXMIN-NEXT:    fcvt.s.h a1, a1
+; CHECKIZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECKIZHINXMIN-NEXT:    fmul.s a0, a0, a1
+; CHECKIZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; CHECKIZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECKIZHINXMIN-NEXT:    fcvt.s.h a1, a2
+; CHECKIZHINXMIN-NEXT:    fadd.s a0, a0, a1
+; CHECKIZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; CHECKIZHINXMIN-NEXT:    ret
   %1 = call half @llvm.fmuladd.f16(half %a, half %b, half %c)
   ret half %1
 }
 
 declare half @llvm.fabs.f16(half)
 
 define half @fabs_f16(half %a) nounwind {
 ; CHECKIZFH-LABEL: fabs_f16:
 ; CHECKIZFH:       # %bb.0:
 ; CHECKIZFH-NEXT:    fabs.h fa0, fa0
 ; CHECKIZFH-NEXT:    ret
 ;
+; RV32IZHINX-LABEL: fabs_f16:
+; RV32IZHINX:       # %bb.0:
+; RV32IZHINX-NEXT:    slli a0, a0, 17
+; RV32IZHINX-NEXT:    srli a0, a0, 17
+; RV32IZHINX-NEXT:    ret
+;
+; RV64IZHINX-LABEL: fabs_f16:
+; RV64IZHINX:       # %bb.0:
+; RV64IZHINX-NEXT:    slli a0, a0, 49
+; RV64IZHINX-NEXT:    srli a0, a0, 49
+; RV64IZHINX-NEXT:    ret
+;
 ; RV32I-LABEL: fabs_f16:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    slli a0, a0, 17
 ; RV32I-NEXT:    srli a0, a0, 17
 ; RV32I-NEXT:    ret
 ;
 ; RV64I-LABEL: fabs_f16:
 ; RV64I:       # %bb.0:
 ; RV64I-NEXT:    slli a0, a0, 49
 ; RV64I-NEXT:    srli a0, a0, 49
 ; RV64I-NEXT:    ret
 ;
 ; CHECKIZFHMIN-LABEL: fabs_f16:
 ; CHECKIZFHMIN:       # %bb.0:
 ; CHECKIZFHMIN-NEXT:    fcvt.s.h fa5, fa0
 ; CHECKIZFHMIN-NEXT:    fabs.s fa5, fa5
 ; CHECKIZFHMIN-NEXT:    fcvt.h.s fa0, fa5
 ; CHECKIZFHMIN-NEXT:    ret
+;
+; RV32IZHINXMIN-LABEL: fabs_f16:
+; RV32IZHINXMIN:       # %bb.0:
+; RV32IZHINXMIN-NEXT:    slli a0, a0, 17
+; RV32IZHINXMIN-NEXT:    srli a0, a0, 17
+; RV32IZHINXMIN-NEXT:    ret
+;
+; RV64IZHINXMIN-LABEL: fabs_f16:
+; RV64IZHINXMIN:       # %bb.0:
+; RV64IZHINXMIN-NEXT:    slli a0, a0, 49
+; RV64IZHINXMIN-NEXT:    srli a0, a0, 49
+; RV64IZHINXMIN-NEXT:    ret
   %1 = call half @llvm.fabs.f16(half %a)
   ret half %1
 }
 
 declare half @llvm.minnum.f16(half, half)
 
 define half @minnum_f16(half %a, half %b) nounwind {
 ; CHECKIZFH-LABEL: minnum_f16:
 ; CHECKIZFH:       # %bb.0:
 ; CHECKIZFH-NEXT:    fmin.h fa0, fa0, fa1
 ; CHECKIZFH-NEXT:    ret
 ;
+; CHECKIZHINX-LABEL: minnum_f16:
+; CHECKIZHINX:       # %bb.0:
+; CHECKIZHINX-NEXT:    fmin.h a0, a0, a1
+; CHECKIZHINX-NEXT:    ret
+;
 ; RV32I-LABEL: minnum_f16:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s2, 0(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    mv s0, a1

 ;
 ; CHECKIZFHMIN-LABEL: minnum_f16:
 ; CHECKIZFHMIN:       # %bb.0:
 ; CHECKIZFHMIN-NEXT:    fcvt.s.h fa5, fa1
 ; CHECKIZFHMIN-NEXT:    fcvt.s.h fa4, fa0
 ; CHECKIZFHMIN-NEXT:    fmin.s fa5, fa4, fa5
 ; CHECKIZFHMIN-NEXT:    fcvt.h.s fa0, fa5
 ; CHECKIZFHMIN-NEXT:    ret
+;
+; CHECKIZHINXMIN-LABEL: minnum_f16:
+; CHECKIZHINXMIN:       # %bb.0:
+; CHECKIZHINXMIN-NEXT:    fcvt.s.h a1, a1
+; CHECKIZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECKIZHINXMIN-NEXT:    fmin.s a0, a0, a1
+; CHECKIZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; CHECKIZHINXMIN-NEXT:    ret
   %1 = call half @llvm.minnum.f16(half %a, half %b)
   ret half %1
 }
 
 declare half @llvm.maxnum.f16(half, half)
 
 define half @maxnum_f16(half %a, half %b) nounwind {
 ; CHECKIZFH-LABEL: maxnum_f16:
 ; CHECKIZFH:       # %bb.0:
 ; CHECKIZFH-NEXT:    fmax.h fa0, fa0, fa1
 ; CHECKIZFH-NEXT:    ret
 ;
+; CHECKIZHINX-LABEL: maxnum_f16:
+; CHECKIZHINX:       # %bb.0:
+; CHECKIZHINX-NEXT:    fmax.h a0, a0, a1
+; CHECKIZHINX-NEXT:    ret
+;
 ; RV32I-LABEL: maxnum_f16:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    sw s2, 0(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    mv s0, a1

 ;
 ; CHECKIZFHMIN-LABEL: maxnum_f16:
 ; CHECKIZFHMIN:       # %bb.0:
 ; CHECKIZFHMIN-NEXT:    fcvt.s.h fa5, fa1
 ; CHECKIZFHMIN-NEXT:    fcvt.s.h fa4, fa0
 ; CHECKIZFHMIN-NEXT:    fmax.s fa5, fa4, fa5
 ; CHECKIZFHMIN-NEXT:    fcvt.h.s fa0, fa5
 ; CHECKIZFHMIN-NEXT:    ret
+;
+; CHECKIZHINXMIN-LABEL: maxnum_f16:
+; CHECKIZHINXMIN:       # %bb.0:
+; CHECKIZHINXMIN-NEXT:    fcvt.s.h a1, a1
+; CHECKIZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECKIZHINXMIN-NEXT:    fmax.s a0, a0, a1
+; CHECKIZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; CHECKIZHINXMIN-NEXT:    ret
   %1 = call half @llvm.maxnum.f16(half %a, half %b)
   ret half %1
 }
 
 ; TODO: FMINNAN and FMAXNAN aren't handled in
 ; SelectionDAGLegalize::ExpandNode.
 
 ; declare half @llvm.minimum.f16(half, half)

 declare half @llvm.copysign.f16(half, half)
 
 define half @copysign_f16(half %a, half %b) nounwind {
 ; CHECKIZFH-LABEL: copysign_f16:
 ; CHECKIZFH:       # %bb.0:
 ; CHECKIZFH-NEXT:    fsgnj.h fa0, fa0, fa1
 ; CHECKIZFH-NEXT:    ret
 ;
+; CHECKIZHINX-LABEL: copysign_f16:
+; CHECKIZHINX:       # %bb.0:
+; CHECKIZHINX-NEXT:    fsgnj.h a0, a0, a1
+; CHECKIZHINX-NEXT:    ret
+;
 ; RV32I-LABEL: copysign_f16:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    lui a2, 1048568
 ; RV32I-NEXT:    and a1, a1, a2
 ; RV32I-NEXT:    slli a0, a0, 17
 ; RV32I-NEXT:    srli a0, a0, 17
 ; RV32I-NEXT:    or a0, a0, a1
 ; RV32I-NEXT:    ret

 ; RV64IZFHMIN-NEXT:    lbu a1, 1(sp)
 ; RV64IZFHMIN-NEXT:    andi a0, a0, 128
 ; RV64IZFHMIN-NEXT:    andi a1, a1, 127
 ; RV64IZFHMIN-NEXT:    or a0, a1, a0
 ; RV64IZFHMIN-NEXT:    sb a0, 1(sp)
 ; RV64IZFHMIN-NEXT:    flh fa0, 0(sp)
 ; RV64IZFHMIN-NEXT:    addi sp, sp, 16
 ; RV64IZFHMIN-NEXT:    ret
+;
+; RV32IZHINXMIN-LABEL: copysign_f16:
+; RV32IZHINXMIN:       # %bb.0:
+; RV32IZHINXMIN-NEXT:    addi sp, sp, -16
+; RV32IZHINXMIN-NEXT:    addi a2, sp, 12
+; RV32IZHINXMIN-NEXT:    sh a1, 0(a2)
+; RV32IZHINXMIN-NEXT:    addi a1, sp, 8
+; RV32IZHINXMIN-NEXT:    sh a0, 0(a1)
+; RV32IZHINXMIN-NEXT:    lbu a0, 13(sp)
+; RV32IZHINXMIN-NEXT:    lbu a2, 9(sp)
+; RV32IZHINXMIN-NEXT:    andi a0, a0, 128
+; RV32IZHINXMIN-NEXT:    andi a2, a2, 127
+; RV32IZHINXMIN-NEXT:    or a0, a2, a0
+; RV32IZHINXMIN-NEXT:    sb a0, 9(sp)
+; RV32IZHINXMIN-NEXT:    lh a0, 0(a1)
+; RV32IZHINXMIN-NEXT:    addi sp, sp, 16
+; RV32IZHINXMIN-NEXT:    ret
+;
+; RV64IZHINXMIN-LABEL: copysign_f16:
+; RV64IZHINXMIN:       # %bb.0:
+; RV64IZHINXMIN-NEXT:    addi sp, sp, -16
+; RV64IZHINXMIN-NEXT:    addi a2, sp, 8
+; RV64IZHINXMIN-NEXT:    sh a1, 0(a2)
+; RV64IZHINXMIN-NEXT:    mv a1, sp
+; RV64IZHINXMIN-NEXT:    sh a0, 0(a1)
+; RV64IZHINXMIN-NEXT:    lbu a0, 9(sp)
+; RV64IZHINXMIN-NEXT:    lbu a2, 1(sp)
+; RV64IZHINXMIN-NEXT:    andi a0, a0, 128
+; RV64IZHINXMIN-NEXT:    andi a2, a2, 127
+; RV64IZHINXMIN-NEXT:    or a0, a2, a0
+; RV64IZHINXMIN-NEXT:    sb a0, 1(sp)
+; RV64IZHINXMIN-NEXT:    lh a0, 0(a1)
+; RV64IZHINXMIN-NEXT:    addi sp, sp, 16
+; RV64IZHINXMIN-NEXT:    ret
   %1 = call half @llvm.copysign.f16(half %a, half %b)
   ret half %1
 }
 
 declare half @llvm.floor.f16(half)
 
 define half @floor_f16(half %a) nounwind {
 ; CHECKIZFH-LABEL: floor_f16:
 ; CHECKIZFH:       # %bb.0:
 ; CHECKIZFH-NEXT:    lui a0, %hi(.LCPI17_0)
 ; CHECKIZFH-NEXT:    flh fa5, %lo(.LCPI17_0)(a0)
 ; CHECKIZFH-NEXT:    fabs.h fa4, fa0
 ; CHECKIZFH-NEXT:    flt.h a0, fa4, fa5
 ; CHECKIZFH-NEXT:    beqz a0, .LBB17_2
 ; CHECKIZFH-NEXT:  # %bb.1:
 ; CHECKIZFH-NEXT:    fcvt.w.h a0, fa0, rdn
 ; CHECKIZFH-NEXT:    fcvt.h.w fa5, a0, rdn
 ; CHECKIZFH-NEXT:    fsgnj.h fa0, fa5, fa0
 ; CHECKIZFH-NEXT:  .LBB17_2:
 ; CHECKIZFH-NEXT:    ret
 ;
+; CHECKIZHINX-LABEL: floor_f16:
+; CHECKIZHINX:       # %bb.0:
+; CHECKIZHINX-NEXT:    lui a1, %hi(.LCPI17_0)
+; CHECKIZHINX-NEXT:    lh a1, %lo(.LCPI17_0)(a1)
+; CHECKIZHINX-NEXT:    fabs.h a2, a0
+; CHECKIZHINX-NEXT:    flt.h a1, a2, a1
+; CHECKIZHINX-NEXT:    beqz a1, .LBB17_2
+; CHECKIZHINX-NEXT:  # %bb.1:
+; CHECKIZHINX-NEXT:    fcvt.w.h a1, a0, rdn
+; CHECKIZHINX-NEXT:    fcvt.h.w a1, a1, rdn
+; CHECKIZHINX-NEXT:    fsgnj.h a0, a1, a0
+; CHECKIZHINX-NEXT:  .LBB17_2:
+; CHECKIZHINX-NEXT:    ret
+;
 ; RV32I-LABEL: floor_f16:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    slli a0, a0, 16
 ; RV32I-NEXT:    srli a0, a0, 16
 ; RV32I-NEXT:    call __extendhfsf2@plt
 ; RV32I-NEXT:    call floorf@plt

 ; CHECKIZFHMIN-NEXT:    beqz a0, .LBB17_2
 ; CHECKIZFHMIN-NEXT:  # %bb.1:
 ; CHECKIZFHMIN-NEXT:    fcvt.w.s a0, fa5, rdn
 ; CHECKIZFHMIN-NEXT:    fcvt.s.w fa4, a0, rdn
 ; CHECKIZFHMIN-NEXT:    fsgnj.s fa5, fa4, fa5
 ; CHECKIZFHMIN-NEXT:  .LBB17_2:
 ; CHECKIZFHMIN-NEXT:    fcvt.h.s fa0, fa5
 ; CHECKIZFHMIN-NEXT:    ret
+;
+; CHECKIZHINXMIN-LABEL: floor_f16:
+; CHECKIZHINXMIN:       # %bb.0:
+; CHECKIZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECKIZHINXMIN-NEXT:    lui a1, 307200
+; CHECKIZHINXMIN-NEXT:    fabs.s a2, a0
+; CHECKIZHINXMIN-NEXT:    flt.s a1, a2, a1
+; CHECKIZHINXMIN-NEXT:    beqz a1, .LBB17_2
+; CHECKIZHINXMIN-NEXT:  # %bb.1:
+; CHECKIZHINXMIN-NEXT:    fcvt.w.s a1, a0, rdn
+; CHECKIZHINXMIN-NEXT:    fcvt.s.w a1, a1, rdn
+; CHECKIZHINXMIN-NEXT:    fsgnj.s a0, a1, a0
+; CHECKIZHINXMIN-NEXT:  .LBB17_2:
+; CHECKIZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; CHECKIZHINXMIN-NEXT:    ret
   %1 = call half @llvm.floor.f16(half %a)
   ret half %1
 }
 
 declare half @llvm.ceil.f16(half)
 
 define half @ceil_f16(half %a) nounwind {
 ; CHECKIZFH-LABEL: ceil_f16:
 ; CHECKIZFH:       # %bb.0:
 ; CHECKIZFH-NEXT:    lui a0, %hi(.LCPI18_0)
 ; CHECKIZFH-NEXT:    flh fa5, %lo(.LCPI18_0)(a0)
 ; CHECKIZFH-NEXT:    fabs.h fa4, fa0
 ; CHECKIZFH-NEXT:    flt.h a0, fa4, fa5
 ; CHECKIZFH-NEXT:    beqz a0, .LBB18_2
 ; CHECKIZFH-NEXT:  # %bb.1:
 ; CHECKIZFH-NEXT:    fcvt.w.h a0, fa0, rup
 ; CHECKIZFH-NEXT:    fcvt.h.w fa5, a0, rup
 ; CHECKIZFH-NEXT:    fsgnj.h fa0, fa5, fa0
 ; CHECKIZFH-NEXT:  .LBB18_2:
 ; CHECKIZFH-NEXT:    ret
 ;
+; CHECKIZHINX-LABEL: ceil_f16:
+; CHECKIZHINX:       # %bb.0:
+; CHECKIZHINX-NEXT:    lui a1, %hi(.LCPI18_0)
+; CHECKIZHINX-NEXT:    lh a1, %lo(.LCPI18_0)(a1)
+; CHECKIZHINX-NEXT:    fabs.h a2, a0
+; CHECKIZHINX-NEXT:    flt.h a1, a2, a1
+; CHECKIZHINX-NEXT:    beqz a1, .LBB18_2
+; CHECKIZHINX-NEXT:  # %bb.1:
+; CHECKIZHINX-NEXT:    fcvt.w.h a1, a0, rup
+; CHECKIZHINX-NEXT:    fcvt.h.w a1, a1, rup
+; CHECKIZHINX-NEXT:    fsgnj.h a0, a1, a0
+; CHECKIZHINX-NEXT:  .LBB18_2:
+; CHECKIZHINX-NEXT:    ret
+;
 ; RV32I-LABEL: ceil_f16:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    slli a0, a0, 16
 ; RV32I-NEXT:    srli a0, a0, 16
 ; RV32I-NEXT:    call __extendhfsf2@plt
 ; RV32I-NEXT:    call ceilf@plt

 ; CHECKIZFHMIN-NEXT:    beqz a0, .LBB18_2
 ; CHECKIZFHMIN-NEXT:  # %bb.1:
 ; CHECKIZFHMIN-NEXT:    fcvt.w.s a0, fa5, rup
 ; CHECKIZFHMIN-NEXT:    fcvt.s.w fa4, a0, rup
 ; CHECKIZFHMIN-NEXT:    fsgnj.s fa5, fa4, fa5
 ; CHECKIZFHMIN-NEXT:  .LBB18_2:
 ; CHECKIZFHMIN-NEXT:    fcvt.h.s fa0, fa5
 ; CHECKIZFHMIN-NEXT:    ret
+;
+; CHECKIZHINXMIN-LABEL: ceil_f16:
+; CHECKIZHINXMIN:       # %bb.0:
+; CHECKIZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECKIZHINXMIN-NEXT:    lui a1, 307200
+; CHECKIZHINXMIN-NEXT:    fabs.s a2, a0
+; CHECKIZHINXMIN-NEXT:    flt.s a1, a2, a1
+; CHECKIZHINXMIN-NEXT:    beqz a1, .LBB18_2
+; CHECKIZHINXMIN-NEXT:  # %bb.1:
+; CHECKIZHINXMIN-NEXT:    fcvt.w.s a1, a0, rup
+; CHECKIZHINXMIN-NEXT:    fcvt.s.w a1, a1, rup
+; CHECKIZHINXMIN-NEXT:    fsgnj.s a0, a1, a0
+; CHECKIZHINXMIN-NEXT:  .LBB18_2:
+; CHECKIZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; CHECKIZHINXMIN-NEXT:    ret
   %1 = call half @llvm.ceil.f16(half %a)
   ret half %1
 }
 
 declare half @llvm.trunc.f16(half)
 
 define half @trunc_f16(half %a) nounwind {
 ; CHECKIZFH-LABEL: trunc_f16:
 ; CHECKIZFH:       # %bb.0:
 ; CHECKIZFH-NEXT:    lui a0, %hi(.LCPI19_0)
 ; CHECKIZFH-NEXT:    flh fa5, %lo(.LCPI19_0)(a0)
 ; CHECKIZFH-NEXT:    fabs.h fa4, fa0
 ; CHECKIZFH-NEXT:    flt.h a0, fa4, fa5
 ; CHECKIZFH-NEXT:    beqz a0, .LBB19_2
 ; CHECKIZFH-NEXT:  # %bb.1:
 ; CHECKIZFH-NEXT:    fcvt.w.h a0, fa0, rtz
 ; CHECKIZFH-NEXT:    fcvt.h.w fa5, a0, rtz
 ; CHECKIZFH-NEXT:    fsgnj.h fa0, fa5, fa0
 ; CHECKIZFH-NEXT:  .LBB19_2:
 ; CHECKIZFH-NEXT:    ret
 ;
+; CHECKIZHINX-LABEL: trunc_f16:
+; CHECKIZHINX:       # %bb.0:
+; CHECKIZHINX-NEXT:    lui a1, %hi(.LCPI19_0)
+; CHECKIZHINX-NEXT:    lh a1, %lo(.LCPI19_0)(a1)
+; CHECKIZHINX-NEXT:    fabs.h a2, a0
+; CHECKIZHINX-NEXT:    flt.h a1, a2, a1
+; CHECKIZHINX-NEXT:    beqz a1, .LBB19_2
+; CHECKIZHINX-NEXT:  # %bb.1:
+; CHECKIZHINX-NEXT:    fcvt.w.h a1, a0, rtz
+; CHECKIZHINX-NEXT:    fcvt.h.w a1, a1, rtz
+; CHECKIZHINX-NEXT:    fsgnj.h a0, a1, a0
+; CHECKIZHINX-NEXT:  .LBB19_2:
+; CHECKIZHINX-NEXT:    ret
+;
 ; RV32I-LABEL: trunc_f16:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    slli a0, a0, 16
 ; RV32I-NEXT:    srli a0, a0, 16
 ; RV32I-NEXT:    call __extendhfsf2@plt
 ; RV32I-NEXT:    call truncf@plt

 ; CHECKIZFHMIN-NEXT:    beqz a0, .LBB19_2
 ; CHECKIZFHMIN-NEXT:  # %bb.1:
 ; CHECKIZFHMIN-NEXT:    fcvt.w.s a0, fa5, rtz
 ; CHECKIZFHMIN-NEXT:    fcvt.s.w fa4, a0, rtz
 ; CHECKIZFHMIN-NEXT:    fsgnj.s fa5, fa4, fa5
 ; CHECKIZFHMIN-NEXT:  .LBB19_2:
 ; CHECKIZFHMIN-NEXT:    fcvt.h.s fa0, fa5
 ; CHECKIZFHMIN-NEXT:    ret
+;
+; CHECKIZHINXMIN-LABEL: trunc_f16:
+; CHECKIZHINXMIN:       # %bb.0:
+; CHECKIZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECKIZHINXMIN-NEXT:    lui a1, 307200
+; CHECKIZHINXMIN-NEXT:    fabs.s a2, a0
+; CHECKIZHINXMIN-NEXT:    flt.s a1, a2, a1
+; CHECKIZHINXMIN-NEXT:    beqz a1, .LBB19_2
+; CHECKIZHINXMIN-NEXT:  # %bb.1:
+; CHECKIZHINXMIN-NEXT:    fcvt.w.s a1, a0, rtz
+; CHECKIZHINXMIN-NEXT:    fcvt.s.w a1, a1, rtz
+; CHECKIZHINXMIN-NEXT:    fsgnj.s a0, a1, a0
+; CHECKIZHINXMIN-NEXT:  .LBB19_2:
+; CHECKIZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; CHECKIZHINXMIN-NEXT:    ret
   %1 = call half @llvm.trunc.f16(half %a)
   ret half %1
 }
 
 declare half @llvm.rint.f16(half)
 
 define half @rint_f16(half %a) nounwind {
 ; CHECKIZFH-LABEL: rint_f16:
 ; CHECKIZFH:       # %bb.0:
 ; CHECKIZFH-NEXT:    lui a0, %hi(.LCPI20_0)
 ; CHECKIZFH-NEXT:    flh fa5, %lo(.LCPI20_0)(a0)
 ; CHECKIZFH-NEXT:    fabs.h fa4, fa0
 ; CHECKIZFH-NEXT:    flt.h a0, fa4, fa5
 ; CHECKIZFH-NEXT:    beqz a0, .LBB20_2
 ; CHECKIZFH-NEXT:  # %bb.1:
 ; CHECKIZFH-NEXT:    fcvt.w.h a0, fa0
 ; CHECKIZFH-NEXT:    fcvt.h.w fa5, a0
 ; CHECKIZFH-NEXT:    fsgnj.h fa0, fa5, fa0
 ; CHECKIZFH-NEXT:  .LBB20_2:
 ; CHECKIZFH-NEXT:    ret
 ;
+; CHECKIZHINX-LABEL: rint_f16:
+; CHECKIZHINX:       # %bb.0:
+; CHECKIZHINX-NEXT:    lui a1, %hi(.LCPI20_0)
+; CHECKIZHINX-NEXT:    lh a1, %lo(.LCPI20_0)(a1)
+; CHECKIZHINX-NEXT:    fabs.h a2, a0
+; CHECKIZHINX-NEXT:    flt.h a1, a2, a1
+; CHECKIZHINX-NEXT:    beqz a1, .LBB20_2
+; CHECKIZHINX-NEXT:  # %bb.1:
+; CHECKIZHINX-NEXT:    fcvt.w.h a1, a0
+; CHECKIZHINX-NEXT:    fcvt.h.w a1, a1
+; CHECKIZHINX-NEXT:    fsgnj.h a0, a1, a0
+; CHECKIZHINX-NEXT:  .LBB20_2:
+; CHECKIZHINX-NEXT:    ret
+;
 ; RV32I-LABEL: rint_f16:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    slli a0, a0, 16
 ; RV32I-NEXT:    srli a0, a0, 16
 ; RV32I-NEXT:    call __extendhfsf2@plt
 ; RV32I-NEXT:    call rintf@plt

 ; CHECKIZFHMIN-NEXT:    beqz a0, .LBB20_2
 ; CHECKIZFHMIN-NEXT:  # %bb.1:
 ; CHECKIZFHMIN-NEXT:    fcvt.w.s a0, fa5
 ; CHECKIZFHMIN-NEXT:    fcvt.s.w fa4, a0
 ; CHECKIZFHMIN-NEXT:    fsgnj.s fa5, fa4, fa5
 ; CHECKIZFHMIN-NEXT:  .LBB20_2:
 ; CHECKIZFHMIN-NEXT:    fcvt.h.s fa0, fa5
 ; CHECKIZFHMIN-NEXT:    ret
+;
+; CHECKIZHINXMIN-LABEL: rint_f16:
+; CHECKIZHINXMIN:       # %bb.0:
+; CHECKIZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECKIZHINXMIN-NEXT:    lui a1, 307200
+; CHECKIZHINXMIN-NEXT:    fabs.s a2, a0
+; CHECKIZHINXMIN-NEXT:    flt.s a1, a2, a1
+; CHECKIZHINXMIN-NEXT:    beqz a1, .LBB20_2
+; CHECKIZHINXMIN-NEXT:  # %bb.1:
+; CHECKIZHINXMIN-NEXT:    fcvt.w.s a1, a0
+; CHECKIZHINXMIN-NEXT:    fcvt.s.w a1, a1
+; CHECKIZHINXMIN-NEXT:    fsgnj.s a0, a1, a0
+; CHECKIZHINXMIN-NEXT:  .LBB20_2:
+; CHECKIZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; CHECKIZHINXMIN-NEXT:    ret
   %1 = call half @llvm.rint.f16(half %a)
   ret half %1
 }
 
 declare half @llvm.nearbyint.f16(half)
 
 define half @nearbyint_f16(half %a) nounwind {
 ; RV32IZFH-LABEL: nearbyint_f16:

 ; RV64IZFH-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64IZFH-NEXT:    fcvt.s.h fa0, fa0
 ; RV64IZFH-NEXT:    call nearbyintf@plt
 ; RV64IZFH-NEXT:    fcvt.h.s fa0, fa0
 ; RV64IZFH-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64IZFH-NEXT:    addi sp, sp, 16
 ; RV64IZFH-NEXT:    ret
 ;
+; RV32IZHINX-LABEL: nearbyint_f16:
+; RV32IZHINX:       # %bb.0:
+; RV32IZHINX-NEXT:    addi sp, sp, -16
+; RV32IZHINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZHINX-NEXT:    fcvt.s.h a0, a0
+; RV32IZHINX-NEXT:    call nearbyintf@plt
+; RV32IZHINX-NEXT:    fcvt.h.s a0, a0
+; RV32IZHINX-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZHINX-NEXT:    addi sp, sp, 16
+; RV32IZHINX-NEXT:    ret
+;
+; RV64IZHINX-LABEL: nearbyint_f16:
+; RV64IZHINX:       # %bb.0:
+; RV64IZHINX-NEXT:    addi sp, sp, -16
+; RV64IZHINX-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IZHINX-NEXT:    fcvt.s.h a0, a0
+; RV64IZHINX-NEXT:    call nearbyintf@plt
+; RV64IZHINX-NEXT:    fcvt.h.s a0, a0
+; RV64IZHINX-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
+; RV64IZHINX-NEXT:    addi sp, sp, 16
+; RV64IZHINX-NEXT:    ret
+;
 ; RV32I-LABEL: nearbyint_f16:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    slli a0, a0, 16
 ; RV32I-NEXT:    srli a0, a0, 16
 ; RV32I-NEXT:    call __extendhfsf2@plt
 ; RV32I-NEXT:    call nearbyintf@plt

 ; RV64IZFHMIN-NEXT:    addi sp, sp, -16
 ; RV64IZFHMIN-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64IZFHMIN-NEXT:    fcvt.s.h fa0, fa0
 ; RV64IZFHMIN-NEXT:    call nearbyintf@plt
 ; RV64IZFHMIN-NEXT:    fcvt.h.s fa0, fa0
 ; RV64IZFHMIN-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64IZFHMIN-NEXT:    addi sp, sp, 16
 ; RV64IZFHMIN-NEXT:    ret
+;
+; RV32IZHINXMIN-LABEL: nearbyint_f16:
+; RV32IZHINXMIN:       # %bb.0:
+; RV32IZHINXMIN-NEXT:    addi sp, sp, -16
+; RV32IZHINXMIN-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV32IZHINXMIN-NEXT:    call nearbyintf@plt
+; RV32IZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; RV32IZHINXMIN-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZHINXMIN-NEXT:    addi sp, sp, 16
+; RV32IZHINXMIN-NEXT:    ret
+;
+; RV64IZHINXMIN-LABEL: nearbyint_f16:
+; RV64IZHINXMIN:       # %bb.0:
+; RV64IZHINXMIN-NEXT:    addi sp, sp, -16
+; RV64IZHINXMIN-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV64IZHINXMIN-NEXT:    call nearbyintf@plt
+; RV64IZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; RV64IZHINXMIN-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
+; RV64IZHINXMIN-NEXT:    addi sp, sp, 16
+; RV64IZHINXMIN-NEXT:    ret
   %1 = call half @llvm.nearbyint.f16(half %a)
   ret half %1
 }
 
 declare half @llvm.round.f16(half)
 
 define half @round_f16(half %a) nounwind {
 ; CHECKIZFH-LABEL: round_f16:
 ; CHECKIZFH:       # %bb.0:
 ; CHECKIZFH-NEXT:    lui a0, %hi(.LCPI22_0)
 ; CHECKIZFH-NEXT:    flh fa5, %lo(.LCPI22_0)(a0)
 ; CHECKIZFH-NEXT:    fabs.h fa4, fa0
 ; CHECKIZFH-NEXT:    flt.h a0, fa4, fa5
 ; CHECKIZFH-NEXT:    beqz a0, .LBB22_2
 ; CHECKIZFH-NEXT:  # %bb.1:
 ; CHECKIZFH-NEXT:    fcvt.w.h a0, fa0, rmm
 ; CHECKIZFH-NEXT:    fcvt.h.w fa5, a0, rmm
 ; CHECKIZFH-NEXT:    fsgnj.h fa0, fa5, fa0
 ; CHECKIZFH-NEXT:  .LBB22_2:
 ; CHECKIZFH-NEXT:    ret
 ;
+; CHECKIZHINX-LABEL: round_f16:
+; CHECKIZHINX:       # %bb.0:
+; CHECKIZHINX-NEXT:    lui a1, %hi(.LCPI22_0)
+; CHECKIZHINX-NEXT:    lh a1, %lo(.LCPI22_0)(a1)
+; CHECKIZHINX-NEXT:    fabs.h a2, a0
+; CHECKIZHINX-NEXT:    flt.h a1, a2, a1
+; CHECKIZHINX-NEXT:    beqz a1, .LBB22_2
+; CHECKIZHINX-NEXT:  # %bb.1:
+; CHECKIZHINX-NEXT:    fcvt.w.h a1, a0, rmm
+; CHECKIZHINX-NEXT:    fcvt.h.w a1, a1, rmm
+; CHECKIZHINX-NEXT:    fsgnj.h a0, a1, a0
+; CHECKIZHINX-NEXT:  .LBB22_2:
+; CHECKIZHINX-NEXT:    ret
+;
 ; RV32I-LABEL: round_f16:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    slli a0, a0, 16
 ; RV32I-NEXT:    srli a0, a0, 16
 ; RV32I-NEXT:    call __extendhfsf2@plt
 ; RV32I-NEXT:    call roundf@plt

 ; CHECKIZFHMIN-NEXT:    beqz a0, .LBB22_2
 ; CHECKIZFHMIN-NEXT:  # %bb.1:
 ; CHECKIZFHMIN-NEXT:    fcvt.w.s a0, fa5, rmm
 ; CHECKIZFHMIN-NEXT:    fcvt.s.w fa4, a0, rmm
 ; CHECKIZFHMIN-NEXT:    fsgnj.s fa5, fa4, fa5
 ; CHECKIZFHMIN-NEXT:  .LBB22_2:
 ; CHECKIZFHMIN-NEXT:    fcvt.h.s fa0, fa5
 ; CHECKIZFHMIN-NEXT:    ret
+;
+; CHECKIZHINXMIN-LABEL: round_f16:
+; CHECKIZHINXMIN:       # %bb.0:
+; CHECKIZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECKIZHINXMIN-NEXT:    lui a1, 307200
+; CHECKIZHINXMIN-NEXT:    fabs.s a2, a0
+; CHECKIZHINXMIN-NEXT:    flt.s a1, a2, a1
+; CHECKIZHINXMIN-NEXT:    beqz a1, .LBB22_2
+; CHECKIZHINXMIN-NEXT:  # %bb.1:
+; CHECKIZHINXMIN-NEXT:    fcvt.w.s a1, a0, rmm
+; CHECKIZHINXMIN-NEXT:    fcvt.s.w a1, a1, rmm
+; CHECKIZHINXMIN-NEXT:    fsgnj.s a0, a1, a0
+; CHECKIZHINXMIN-NEXT:  .LBB22_2:
+; CHECKIZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; CHECKIZHINXMIN-NEXT:    ret
   %1 = call half @llvm.round.f16(half %a)
   ret half %1
 }
 
 declare half @llvm.roundeven.f16(half)
 
 define half @roundeven_f16(half %a) nounwind {
 ; CHECKIZFH-LABEL: roundeven_f16:
 ; CHECKIZFH:       # %bb.0:
 ; CHECKIZFH-NEXT:    lui a0, %hi(.LCPI23_0)
 ; CHECKIZFH-NEXT:    flh fa5, %lo(.LCPI23_0)(a0)
 ; CHECKIZFH-NEXT:    fabs.h fa4, fa0
 ; CHECKIZFH-NEXT:    flt.h a0, fa4, fa5
 ; CHECKIZFH-NEXT:    beqz a0, .LBB23_2
 ; CHECKIZFH-NEXT:  # %bb.1:
 ; CHECKIZFH-NEXT:    fcvt.w.h a0, fa0, rne
 ; CHECKIZFH-NEXT:    fcvt.h.w fa5, a0, rne
 ; CHECKIZFH-NEXT:    fsgnj.h fa0, fa5, fa0
 ; CHECKIZFH-NEXT:  .LBB23_2:
 ; CHECKIZFH-NEXT:    ret
 ;
+; CHECKIZHINX-LABEL: roundeven_f16:
+; CHECKIZHINX:       # %bb.0:
+; CHECKIZHINX-NEXT:    lui a1, %hi(.LCPI23_0)
+; CHECKIZHINX-NEXT:    lh a1, %lo(.LCPI23_0)(a1)
+; CHECKIZHINX-NEXT:    fabs.h a2, a0
+; CHECKIZHINX-NEXT:    flt.h a1, a2, a1
+; CHECKIZHINX-NEXT:    beqz a1, .LBB23_2
+; CHECKIZHINX-NEXT:  # %bb.1:
+; CHECKIZHINX-NEXT:    fcvt.w.h a1, a0, rne
+; CHECKIZHINX-NEXT:    fcvt.h.w a1, a1, rne
+; CHECKIZHINX-NEXT:    fsgnj.h a0, a1, a0
+; CHECKIZHINX-NEXT:  .LBB23_2:
+; CHECKIZHINX-NEXT:    ret
+;
 ; RV32I-LABEL: roundeven_f16:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    addi sp, sp, -16
 ; RV32I-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32I-NEXT:    slli a0, a0, 16
 ; RV32I-NEXT:    srli a0, a0, 16
 ; RV32I-NEXT:    call __extendhfsf2@plt
 ; RV32I-NEXT:    call roundevenf@plt

 ; CHECKIZFHMIN-NEXT:    beqz a0, .LBB23_2
 ; CHECKIZFHMIN-NEXT:  # %bb.1:
 ; CHECKIZFHMIN-NEXT:    fcvt.w.s a0, fa5, rne
 ; CHECKIZFHMIN-NEXT:    fcvt.s.w fa4, a0, rne
 ; CHECKIZFHMIN-NEXT:    fsgnj.s fa5, fa4, fa5
 ; CHECKIZFHMIN-NEXT:  .LBB23_2:
 ; CHECKIZFHMIN-NEXT:    fcvt.h.s fa0, fa5
 ; CHECKIZFHMIN-NEXT:    ret
+;
+; CHECKIZHINXMIN-LABEL: roundeven_f16:
+; CHECKIZHINXMIN:       # %bb.0:
+; CHECKIZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECKIZHINXMIN-NEXT:    lui a1, 307200
+; CHECKIZHINXMIN-NEXT:    fabs.s a2, a0
+; CHECKIZHINXMIN-NEXT:    flt.s a1, a2, a1
+; CHECKIZHINXMIN-NEXT:    beqz a1, .LBB23_2
+; CHECKIZHINXMIN-NEXT:  # %bb.1:
+; CHECKIZHINXMIN-NEXT:    fcvt.w.s a1, a0, rne
+; CHECKIZHINXMIN-NEXT:    fcvt.s.w a1, a1, rne
+; CHECKIZHINXMIN-NEXT:    fsgnj.s a0, a1, a0
+; CHECKIZHINXMIN-NEXT:  .LBB23_2:
+; CHECKIZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; CHECKIZHINXMIN-NEXT:    ret
   %1 = call half @llvm.roundeven.f16(half %a)
   ret half %1
 }
 
 declare i1 @llvm.is.fpclass.f16(half, i32)
 define i1 @isnan_d_fpclass(half %x) {
 ; CHECKIZFH-LABEL: isnan_d_fpclass:
 ; CHECKIZFH:       # %bb.0:
 ; CHECKIZFH-NEXT:    fclass.h a0, fa0
 ; CHECKIZFH-NEXT:    andi a0, a0, 768
 ; CHECKIZFH-NEXT:    snez a0, a0
 ; CHECKIZFH-NEXT:    ret
 ;
+; CHECKIZHINX-LABEL: isnan_d_fpclass:
+; CHECKIZHINX:       # %bb.0:
+; CHECKIZHINX-NEXT:    fclass.h a0, a0
+; CHECKIZHINX-NEXT:    andi a0, a0, 768
+; CHECKIZHINX-NEXT:    snez a0, a0
+; CHECKIZHINX-NEXT:    ret
+;
 ; RV32I-LABEL: isnan_d_fpclass:
 ; RV32I:       # %bb.0:
 ; RV32I-NEXT:    slli a0, a0, 17
 ; RV32I-NEXT:    srli a0, a0, 17
 ; RV32I-NEXT:    li a1, 31
 ; RV32I-NEXT:    slli a1, a1, 10
 ; RV32I-NEXT:    slt a0, a1, a0
 ; RV32I-NEXT:    ret

 ; RV64IZFHMIN:       # %bb.0:
 ; RV64IZFHMIN-NEXT:    fmv.x.h a0, fa0
 ; RV64IZFHMIN-NEXT:    slli a0, a0, 49
 ; RV64IZFHMIN-NEXT:    srli a0, a0, 49
 ; RV64IZFHMIN-NEXT:    li a1, 31
 ; RV64IZFHMIN-NEXT:    slli a1, a1, 10
 ; RV64IZFHMIN-NEXT:    slt a0, a1, a0
 ; RV64IZFHMIN-NEXT:    ret
+;
+; RV32IZHINXMIN-LABEL: isnan_d_fpclass:
+; RV32IZHINXMIN:       # %bb.0:
+; RV32IZHINXMIN-NEXT:    slli a0, a0, 17
+; RV32IZHINXMIN-NEXT:    srli a0, a0, 17
+; RV32IZHINXMIN-NEXT:    li a1, 31
+; RV32IZHINXMIN-NEXT:    slli a1, a1, 10
+; RV32IZHINXMIN-NEXT:    slt a0, a1, a0
+; RV32IZHINXMIN-NEXT:    ret
+;
+; RV64IZHINXMIN-LABEL: isnan_d_fpclass:
+; RV64IZHINXMIN:       # %bb.0:
+; RV64IZHINXMIN-NEXT:    slli a0, a0, 49
+; RV64IZHINXMIN-NEXT:    srli a0, a0, 49
+; RV64IZHINXMIN-NEXT:    li a1, 31
+; RV64IZHINXMIN-NEXT:    slli a1, a1, 10
+; RV64IZHINXMIN-NEXT:    slt a0, a1, a0
+; RV64IZHINXMIN-NEXT:    ret
   %1 = call i1 @llvm.is.fpclass.f16(half %x, i32 3)  ; nan
   ret i1 %1
 }
+;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
+; RV32IZDINXZHINX: {{.*}}
+; RV32IZDINXZHINXMIN: {{.*}}
+; RV64IZDINXZHINX: {{.*}}
+; RV64IZDINXZHINXMIN: {{.*}}

llvm/test/CodeGen/RISCV/half-isnan.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -mattr=+zfh -verify-machineinstrs \
 ; RUN:   -target-abi ilp32f < %s | FileCheck %s
 ; RUN: llc -mtriple=riscv64 -mattr=+zfh -verify-machineinstrs \
 ; RUN:   -target-abi lp64f < %s | FileCheck %s
+; RUN: llc -mtriple=riscv32 -mattr=+zhinx -verify-machineinstrs \
+; RUN:   -target-abi ilp32 < %s | FileCheck -check-prefixes=CHECKIZHINX %s
+; RUN: llc -mtriple=riscv64 -mattr=+zhinx -verify-machineinstrs \
+; RUN:   -target-abi lp64 < %s | FileCheck -check-prefixes=CHECKIZHINX %s
 ; RUN: llc -mtriple=riscv32 -mattr=+zfhmin -verify-machineinstrs \
 ; RUN:   -target-abi ilp32f < %s | FileCheck -check-prefixes=CHECKIZFHMIN %s
 ; RUN: llc -mtriple=riscv64 -mattr=+zfhmin -verify-machineinstrs \
 ; RUN:   -target-abi lp64f < %s | FileCheck -check-prefixes=CHECKIZFHMIN %s
+; RUN: llc -mtriple=riscv32 -mattr=+zhinxmin -verify-machineinstrs \
+; RUN:   -target-abi ilp32 < %s | FileCheck -check-prefixes=CHECKIZHINXMIN %s
+; RUN: llc -mtriple=riscv64 -mattr=+zhinxmin -verify-machineinstrs \
+; RUN:   -target-abi lp64 < %s | FileCheck -check-prefixes=CHECKIZHINXMIN %s
 
 define zeroext i1 @half_is_nan(half %a) nounwind {
 ; CHECK-LABEL: half_is_nan:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    feq.h a0, fa0, fa0
 ; CHECK-NEXT:    xori a0, a0, 1
 ; CHECK-NEXT:    ret
 ;
+; CHECKIZHINX-LABEL: half_is_nan:
+; CHECKIZHINX:       # %bb.0:
+; CHECKIZHINX-NEXT:    feq.h a0, a0, a0
+; CHECKIZHINX-NEXT:    xori a0, a0, 1
+; CHECKIZHINX-NEXT:    ret
+;
 ; CHECKIZFHMIN-LABEL: half_is_nan:
 ; CHECKIZFHMIN:       # %bb.0:
 ; CHECKIZFHMIN-NEXT:    fcvt.s.h fa5, fa0
 ; CHECKIZFHMIN-NEXT:    feq.s a0, fa5, fa5
 ; CHECKIZFHMIN-NEXT:    xori a0, a0, 1
 ; CHECKIZFHMIN-NEXT:    ret
+;
+; CHECKIZHINXMIN-LABEL: half_is_nan:
+; CHECKIZHINXMIN:       # %bb.0:
+; CHECKIZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECKIZHINXMIN-NEXT:    feq.s a0, a0, a0
+; CHECKIZHINXMIN-NEXT:    xori a0, a0, 1
+; CHECKIZHINXMIN-NEXT:    ret
   %1 = fcmp uno half %a, 0.000000e+00
   ret i1 %1
 }
 
 define zeroext i1 @half_not_nan(half %a) nounwind {
 ; CHECK-LABEL: half_not_nan:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    feq.h a0, fa0, fa0
 ; CHECK-NEXT:    ret
 ;
+; CHECKIZHINX-LABEL: half_not_nan:
+; CHECKIZHINX:       # %bb.0:
+; CHECKIZHINX-NEXT:    feq.h a0, a0, a0
+; CHECKIZHINX-NEXT:    ret
+;
 ; CHECKIZFHMIN-LABEL: half_not_nan:
 ; CHECKIZFHMIN:       # %bb.0:
 ; CHECKIZFHMIN-NEXT:    fcvt.s.h fa5, fa0
 ; CHECKIZFHMIN-NEXT:    feq.s a0, fa5, fa5
 ; CHECKIZFHMIN-NEXT:    ret
+;
+; CHECKIZHINXMIN-LABEL: half_not_nan:
+; CHECKIZHINXMIN:       # %bb.0:
+; CHECKIZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECKIZHINXMIN-NEXT:    feq.s a0, a0, a0
+; CHECKIZHINXMIN-NEXT:    ret
   %1 = fcmp ord half %a, 0.000000e+00
   ret i1 %1
 }

llvm/test/CodeGen/RISCV/half-mem.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -mattr=+zfh -verify-machineinstrs \
 ; RUN:   -target-abi ilp32f < %s | FileCheck -check-prefixes=CHECKIZFH,RV32IZFH %s
 ; RUN: llc -mtriple=riscv64 -mattr=+zfh -verify-machineinstrs \
 ; RUN:   -target-abi lp64f < %s | FileCheck -check-prefixes=CHECKIZFH,RV64IZFH %s
+; RUN: llc -mtriple=riscv32 -mattr=+zhinx -verify-machineinstrs \
+; RUN:   -target-abi ilp32 < %s | FileCheck -check-prefixes=CHECKIZHINX,RV32IZHINX %s
+; RUN: llc -mtriple=riscv64 -mattr=+zhinx -verify-machineinstrs \
+; RUN:   -target-abi lp64 < %s | FileCheck -check-prefixes=CHECKIZHINX,RV64IZHINX %s
 ; RUN: llc -mtriple=riscv32 -mattr=+zfhmin -verify-machineinstrs \
 ; RUN:   -target-abi ilp32f < %s | FileCheck -check-prefixes=CHECKIZFHMIN,RV32IZFHMIN %s
 ; RUN: llc -mtriple=riscv64 -mattr=+zfhmin -verify-machineinstrs \
 ; RUN:   -target-abi lp64f < %s | FileCheck -check-prefixes=CHECKIZFHMIN,RV64IZFHMIN %s
+; RUN: llc -mtriple=riscv32 -mattr=+zhinxmin -verify-machineinstrs \
+; RUN:   -target-abi ilp32 < %s | FileCheck -check-prefixes=CHECKIZHINXMIN,RV32IZHINXMIN %s
+; RUN: llc -mtriple=riscv64 -mattr=+zhinxmin -verify-machineinstrs \
+; RUN:   -target-abi lp64 < %s | FileCheck -check-prefixes=CHECKIZHINXMIN,RV64IZHINXMIN %s
 
 define half @flh(ptr %a) nounwind {
 ; CHECKIZFH-LABEL: flh:
 ; CHECKIZFH:       # %bb.0:
 ; CHECKIZFH-NEXT:    flh fa5, 0(a0)
 ; CHECKIZFH-NEXT:    flh fa4, 6(a0)
 ; CHECKIZFH-NEXT:    fadd.h fa0, fa5, fa4
 ; CHECKIZFH-NEXT:    ret
 ;
+; CHECKIZHINX-LABEL: flh:
+; CHECKIZHINX:       # %bb.0:
+; CHECKIZHINX-NEXT:    lh a1, 0(a0)
+; CHECKIZHINX-NEXT:    addi a0, a0, 6
+; CHECKIZHINX-NEXT:    lh a0, 0(a0)
+; CHECKIZHINX-NEXT:    fadd.h a0, a1, a0
+; CHECKIZHINX-NEXT:    ret
+;
 ; CHECKIZFHMIN-LABEL: flh:
 ; CHECKIZFHMIN:       # %bb.0:
 ; CHECKIZFHMIN-NEXT:    flh fa5, 6(a0)
 ; CHECKIZFHMIN-NEXT:    flh fa4, 0(a0)
 ; CHECKIZFHMIN-NEXT:    fcvt.s.h fa5, fa5
 ; CHECKIZFHMIN-NEXT:    fcvt.s.h fa4, fa4
 ; CHECKIZFHMIN-NEXT:    fadd.s fa5, fa4, fa5
 ; CHECKIZFHMIN-NEXT:    fcvt.h.s fa0, fa5
 ; CHECKIZFHMIN-NEXT:    ret
+;
+; CHECKIZHINXMIN-LABEL: flh:
+; CHECKIZHINXMIN:       # %bb.0:
+; CHECKIZHINXMIN-NEXT:    lh a1, 0(a0)
+; CHECKIZHINXMIN-NEXT:    addi a0, a0, 6
+; CHECKIZHINXMIN-NEXT:    lh a0, 0(a0)
+; CHECKIZHINXMIN-NEXT:    fcvt.s.h a1, a1
+; CHECKIZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECKIZHINXMIN-NEXT:    fadd.s a0, a1, a0
+; CHECKIZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; CHECKIZHINXMIN-NEXT:    ret
   %1 = load half, ptr %a
   %2 = getelementptr half, ptr %a, i32 3
   %3 = load half, ptr %2
 ; Use both loaded values in an FP op to ensure an flh is used, even for the
 ; soft half ABI
   %4 = fadd half %1, %3
   ret half %4
 }
 
 define dso_local void @fsh(ptr %a, half %b, half %c) nounwind {
 ; Use %b and %c in an FP op to ensure half precision floating point registers
 ; are used, even for the soft half ABI
 ; CHECKIZFH-LABEL: fsh:
 ; CHECKIZFH:       # %bb.0:
 ; CHECKIZFH-NEXT:    fadd.h fa5, fa0, fa1
 ; CHECKIZFH-NEXT:    fsh fa5, 0(a0)
 ; CHECKIZFH-NEXT:    fsh fa5, 16(a0)
 ; CHECKIZFH-NEXT:    ret
 ;
+; CHECKIZHINX-LABEL: fsh:
+; CHECKIZHINX:       # %bb.0:
+; CHECKIZHINX-NEXT:    fadd.h a1, a1, a2
+; CHECKIZHINX-NEXT:    sh a1, 0(a0)
+; CHECKIZHINX-NEXT:    addi a0, a0, 16
+; CHECKIZHINX-NEXT:    sh a1, 0(a0)
+; CHECKIZHINX-NEXT:    ret
+;
 ; CHECKIZFHMIN-LABEL: fsh:
 ; CHECKIZFHMIN:       # %bb.0:
 ; CHECKIZFHMIN-NEXT:    fcvt.s.h fa5, fa1
 ; CHECKIZFHMIN-NEXT:    fcvt.s.h fa4, fa0
 ; CHECKIZFHMIN-NEXT:    fadd.s fa5, fa4, fa5
 ; CHECKIZFHMIN-NEXT:    fcvt.h.s fa5, fa5
 ; CHECKIZFHMIN-NEXT:    fsh fa5, 0(a0)
 ; CHECKIZFHMIN-NEXT:    fsh fa5, 16(a0)
 ; CHECKIZFHMIN-NEXT:    ret
+;
+; CHECKIZHINXMIN-LABEL: fsh:
+; CHECKIZHINXMIN:       # %bb.0:
+; CHECKIZHINXMIN-NEXT:    fcvt.s.h a2, a2
+; CHECKIZHINXMIN-NEXT:    fcvt.s.h a1, a1
+; CHECKIZHINXMIN-NEXT:    fadd.s a1, a1, a2
+; CHECKIZHINXMIN-NEXT:    fcvt.h.s a1, a1
+; CHECKIZHINXMIN-NEXT:    sh a1, 0(a0)
+; CHECKIZHINXMIN-NEXT:    addi a0, a0, 16
+; CHECKIZHINXMIN-NEXT:    sh a1, 0(a0)
+; CHECKIZHINXMIN-NEXT:    ret
   %1 = fadd half %b, %c
   store half %1, ptr %a
   %2 = getelementptr half, ptr %a, i32 8
   store half %1, ptr %2
   ret void
 }
 
 ; Check load and store to a global
 @G = dso_local global half 0.0
 
 define half @flh_fsh_global(half %a, half %b) nounwind {
 ; Use %a and %b in an FP op to ensure half precision floating point registers
 ; are used, even for the soft half ABI
 ; CHECKIZFH-LABEL: flh_fsh_global:
 ; CHECKIZFH:       # %bb.0:
 ; CHECKIZFH-NEXT:    fadd.h fa0, fa0, fa1
 ; CHECKIZFH-NEXT:    lui a0, %hi(G)
 ; CHECKIZFH-NEXT:    flh fa5, %lo(G)(a0)
 ; CHECKIZFH-NEXT:    addi a1, a0, %lo(G)
 ; CHECKIZFH-NEXT:    fsh fa0, %lo(G)(a0)
 ; CHECKIZFH-NEXT:    flh fa5, 18(a1)
 ; CHECKIZFH-NEXT:    fsh fa0, 18(a1)
 ; CHECKIZFH-NEXT:    ret
 ;
+; CHECKIZHINX-LABEL: flh_fsh_global:
+; CHECKIZHINX:       # %bb.0:
+; CHECKIZHINX-NEXT:    fadd.h a0, a0, a1
+; CHECKIZHINX-NEXT:    lui a1, %hi(G)
+; CHECKIZHINX-NEXT:    addi a1, a1, %lo(G)
+; CHECKIZHINX-NEXT:    lh a2, 0(a1)
+; CHECKIZHINX-NEXT:    sh a0, 0(a1)
+; CHECKIZHINX-NEXT:    addi a1, a1, 18
+; CHECKIZHINX-NEXT:    lh a2, 0(a1)
+; CHECKIZHINX-NEXT:    sh a0, 0(a1)
+; CHECKIZHINX-NEXT:    ret
+;
 ; CHECKIZFHMIN-LABEL: flh_fsh_global:
 ; CHECKIZFHMIN:       # %bb.0:
 ; CHECKIZFHMIN-NEXT:    fcvt.s.h fa5, fa1
 ; CHECKIZFHMIN-NEXT:    fcvt.s.h fa4, fa0
 ; CHECKIZFHMIN-NEXT:    fadd.s fa5, fa4, fa5
 ; CHECKIZFHMIN-NEXT:    fcvt.h.s fa0, fa5
 ; CHECKIZFHMIN-NEXT:    lui a0, %hi(G)
 ; CHECKIZFHMIN-NEXT:    flh fa5, %lo(G)(a0)
 ; CHECKIZFHMIN-NEXT:    addi a1, a0, %lo(G)
 ; CHECKIZFHMIN-NEXT:    fsh fa0, %lo(G)(a0)
 ; CHECKIZFHMIN-NEXT:    flh fa5, 18(a1)
 ; CHECKIZFHMIN-NEXT:    fsh fa0, 18(a1)
 ; CHECKIZFHMIN-NEXT:    ret
+;
+; CHECKIZHINXMIN-LABEL: flh_fsh_global:
+; CHECKIZHINXMIN:       # %bb.0:
+; CHECKIZHINXMIN-NEXT:    fcvt.s.h a1, a1
+; CHECKIZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECKIZHINXMIN-NEXT:    fadd.s a0, a0, a1
+; CHECKIZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; CHECKIZHINXMIN-NEXT:    lui a1, %hi(G)
+; CHECKIZHINXMIN-NEXT:    addi a1, a1, %lo(G)
+; CHECKIZHINXMIN-NEXT:    lh a2, 0(a1)
+; CHECKIZHINXMIN-NEXT:    sh a0, 0(a1)
+; CHECKIZHINXMIN-NEXT:    addi a1, a1, 18
+; CHECKIZHINXMIN-NEXT:    lh a2, 0(a1)
+; CHECKIZHINXMIN-NEXT:    sh a0, 0(a1)
+; CHECKIZHINXMIN-NEXT:    ret
   %1 = fadd half %a, %b
   %2 = load volatile half, ptr @G
   store half %1, ptr @G
   %3 = getelementptr half, ptr @G, i32 9
   %4 = load volatile half, ptr %3
   store half %1, ptr %3
   ret half %1
 }

 ; RV64IZFH:       # %bb.0:
 ; RV64IZFH-NEXT:    lui a0, 228023
 ; RV64IZFH-NEXT:    slli a0, a0, 2
 ; RV64IZFH-NEXT:    flh fa5, -273(a0)
 ; RV64IZFH-NEXT:    fadd.h fa0, fa0, fa5
 ; RV64IZFH-NEXT:    fsh fa0, -273(a0)
 ; RV64IZFH-NEXT:    ret
 ;
+; RV32IZHINX-LABEL: flh_fsh_constant:
+; RV32IZHINX:       # %bb.0:
+; RV32IZHINX-NEXT:    lui a1, 912092
+; RV32IZHINX-NEXT:    addi a1, a1, -273
+; RV32IZHINX-NEXT:    lh a2, 0(a1)
+; RV32IZHINX-NEXT:    fadd.h a0, a0, a2
+; RV32IZHINX-NEXT:    sh a0, 0(a1)
+; RV32IZHINX-NEXT:    ret
+;
+; RV64IZHINX-LABEL: flh_fsh_constant:
+; RV64IZHINX:       # %bb.0:
+; RV64IZHINX-NEXT:    lui a1, 228023
+; RV64IZHINX-NEXT:    slli a1, a1, 2
+; RV64IZHINX-NEXT:    addi a1, a1, -273
+; RV64IZHINX-NEXT:    lh a2, 0(a1)
+; RV64IZHINX-NEXT:    fadd.h a0, a0, a2
+; RV64IZHINX-NEXT:    sh a0, 0(a1)
+; RV64IZHINX-NEXT:    ret
+;
 ; RV32IZFHMIN-LABEL: flh_fsh_constant:
 ; RV32IZFHMIN:       # %bb.0:
 ; RV32IZFHMIN-NEXT:    lui a0, 912092
 ; RV32IZFHMIN-NEXT:    flh fa5, -273(a0)
 ; RV32IZFHMIN-NEXT:    fcvt.s.h fa4, fa0
 ; RV32IZFHMIN-NEXT:    fcvt.s.h fa5, fa5
 ; RV32IZFHMIN-NEXT:    fadd.s fa5, fa4, fa5
 ; RV32IZFHMIN-NEXT:    fcvt.h.s fa0, fa5
 ; RV32IZFHMIN-NEXT:    fsh fa0, -273(a0)
 ; RV32IZFHMIN-NEXT:    ret
 ;
 ; RV64IZFHMIN-LABEL: flh_fsh_constant:
 ; RV64IZFHMIN:       # %bb.0:
 ; RV64IZFHMIN-NEXT:    lui a0, 228023
 ; RV64IZFHMIN-NEXT:    slli a0, a0, 2
 ; RV64IZFHMIN-NEXT:    flh fa5, -273(a0)
 ; RV64IZFHMIN-NEXT:    fcvt.s.h fa4, fa0
 ; RV64IZFHMIN-NEXT:    fcvt.s.h fa5, fa5
 ; RV64IZFHMIN-NEXT:    fadd.s fa5, fa4, fa5
 ; RV64IZFHMIN-NEXT:    fcvt.h.s fa0, fa5
 ; RV64IZFHMIN-NEXT:    fsh fa0, -273(a0)
 ; RV64IZFHMIN-NEXT:    ret
+;
+; RV32IZHINXMIN-LABEL: flh_fsh_constant:
+; RV32IZHINXMIN:       # %bb.0:
+; RV32IZHINXMIN-NEXT:    lui a1, 912092
+; RV32IZHINXMIN-NEXT:    addi a1, a1, -273
+; RV32IZHINXMIN-NEXT:    lh a2, 0(a1)
+; RV32IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV32IZHINXMIN-NEXT:    fcvt.s.h a2, a2
+; RV32IZHINXMIN-NEXT:    fadd.s a0, a0, a2
+; RV32IZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; RV32IZHINXMIN-NEXT:    sh a0, 0(a1)
+; RV32IZHINXMIN-NEXT:    ret
+;
+; RV64IZHINXMIN-LABEL: flh_fsh_constant:
+; RV64IZHINXMIN:       # %bb.0:
+; RV64IZHINXMIN-NEXT:    lui a1, 228023
+; RV64IZHINXMIN-NEXT:    slli a1, a1, 2
+; RV64IZHINXMIN-NEXT:    addi a1, a1, -273
+; RV64IZHINXMIN-NEXT:    lh a2, 0(a1)
+; RV64IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV64IZHINXMIN-NEXT:    fcvt.s.h a2, a2
+; RV64IZHINXMIN-NEXT:    fadd.s a0, a0, a2
+; RV64IZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; RV64IZHINXMIN-NEXT:    sh a0, 0(a1)
+; RV64IZHINXMIN-NEXT:    ret
   %1 = inttoptr i32 3735928559 to ptr
   %2 = load volatile half, ptr %1
   %3 = fadd half %a, %2
   store half %3, ptr %1
   ret half %3
 }
 
 declare void @notdead(ptr)

 ; RV64IZFH-NEXT:    call notdead@plt
 ; RV64IZFH-NEXT:    flh fa5, 0(sp)
 ; RV64IZFH-NEXT:    fadd.h fa0, fa5, fs0
 ; RV64IZFH-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64IZFH-NEXT:    flw fs0, 4(sp) # 4-byte Folded Reload
 ; RV64IZFH-NEXT:    addi sp, sp, 16
 ; RV64IZFH-NEXT:    ret
 ;
+; RV32IZHINX-LABEL: flh_stack:
+; RV32IZHINX:       # %bb.0:
+; RV32IZHINX-NEXT:    addi sp, sp, -16
+; RV32IZHINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZHINX-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
+; RV32IZHINX-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
+; RV32IZHINX-NEXT:    mv s0, a0
+; RV32IZHINX-NEXT:    mv a0, sp
+; RV32IZHINX-NEXT:    mv s1, sp
+; RV32IZHINX-NEXT:    call notdead@plt
+; RV32IZHINX-NEXT:    lh a0, 0(s1)
+; RV32IZHINX-NEXT:    fadd.h a0, a0, s0
+; RV32IZHINX-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZHINX-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
+; RV32IZHINX-NEXT:    lw s1, 4(sp) # 4-byte Folded Reload
+; RV32IZHINX-NEXT:    addi sp, sp, 16
+; RV32IZHINX-NEXT:    ret
+;
+; RV64IZHINX-LABEL: flh_stack:
+; RV64IZHINX:       # %bb.0:
+; RV64IZHINX-NEXT:    addi sp, sp, -32
+; RV64IZHINX-NEXT:    sd ra, 24(sp) # 8-byte Folded Spill
+; RV64IZHINX-NEXT:    sd s0, 16(sp) # 8-byte Folded Spill
+; RV64IZHINX-NEXT:    sd s1, 8(sp) # 8-byte Folded Spill
+; RV64IZHINX-NEXT:    mv s0, a0
+; RV64IZHINX-NEXT:    addi a0, sp, 4
+; RV64IZHINX-NEXT:    addi s1, sp, 4
+; RV64IZHINX-NEXT:    call notdead@plt
+; RV64IZHINX-NEXT:    lh a0, 0(s1)
+; RV64IZHINX-NEXT:    fadd.h a0, a0, s0
+; RV64IZHINX-NEXT:    ld ra, 24(sp) # 8-byte Folded Reload
+; RV64IZHINX-NEXT:    ld s0, 16(sp) # 8-byte Folded Reload
+; RV64IZHINX-NEXT:    ld s1, 8(sp) # 8-byte Folded Reload
+; RV64IZHINX-NEXT:    addi sp, sp, 32
+; RV64IZHINX-NEXT:    ret
+;
 ; RV32IZFHMIN-LABEL: flh_stack:
 ; RV32IZFHMIN:       # %bb.0:
 ; RV32IZFHMIN-NEXT:    addi sp, sp, -16
 ; RV32IZFHMIN-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32IZFHMIN-NEXT:    fsw fs0, 8(sp) # 4-byte Folded Spill
 ; RV32IZFHMIN-NEXT:    fmv.s fs0, fa0
 ; RV32IZFHMIN-NEXT:    addi a0, sp, 4
 ; RV32IZFHMIN-NEXT:    call notdead@plt

 ; RV64IZFHMIN-NEXT:    fcvt.s.h fa4, fs0
 ; RV64IZFHMIN-NEXT:    fcvt.s.h fa5, fa5
 ; RV64IZFHMIN-NEXT:    fadd.s fa5, fa5, fa4
 ; RV64IZFHMIN-NEXT:    fcvt.h.s fa0, fa5
 ; RV64IZFHMIN-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64IZFHMIN-NEXT:    flw fs0, 4(sp) # 4-byte Folded Reload
 ; RV64IZFHMIN-NEXT:    addi sp, sp, 16
 ; RV64IZFHMIN-NEXT:    ret
+;
+; RV32IZHINXMIN-LABEL: flh_stack:
+; RV32IZHINXMIN:       # %bb.0:
+; RV32IZHINXMIN-NEXT:    addi sp, sp, -16
+; RV32IZHINXMIN-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZHINXMIN-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
+; RV32IZHINXMIN-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
+; RV32IZHINXMIN-NEXT:    mv s0, a0
+; RV32IZHINXMIN-NEXT:    mv a0, sp
+; RV32IZHINXMIN-NEXT:    mv s1, sp
+; RV32IZHINXMIN-NEXT:    call notdead@plt
+; RV32IZHINXMIN-NEXT:    lh a0, 0(s1)
+; RV32IZHINXMIN-NEXT:    fcvt.s.h a1, s0
+; RV32IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV32IZHINXMIN-NEXT:    fadd.s a0, a0, a1
+; RV32IZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; RV32IZHINXMIN-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZHINXMIN-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
+; RV32IZHINXMIN-NEXT:    lw s1, 4(sp) # 4-byte Folded Reload
+; RV32IZHINXMIN-NEXT:    addi sp, sp, 16
+; RV32IZHINXMIN-NEXT:    ret
+;
+; RV64IZHINXMIN-LABEL: flh_stack:
+; RV64IZHINXMIN:       # %bb.0:
+; RV64IZHINXMIN-NEXT:    addi sp, sp, -32
+; RV64IZHINXMIN-NEXT:    sd ra, 24(sp) # 8-byte Folded Spill
+; RV64IZHINXMIN-NEXT:    sd s0, 16(sp) # 8-byte Folded Spill
+; RV64IZHINXMIN-NEXT:    sd s1, 8(sp) # 8-byte Folded Spill
+; RV64IZHINXMIN-NEXT:    mv s0, a0
+; RV64IZHINXMIN-NEXT:    addi a0, sp, 4
+; RV64IZHINXMIN-NEXT:    addi s1, sp, 4
+; RV64IZHINXMIN-NEXT:    call notdead@plt
+; RV64IZHINXMIN-NEXT:    lh a0, 0(s1)
+; RV64IZHINXMIN-NEXT:    fcvt.s.h a1, s0
+; RV64IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV64IZHINXMIN-NEXT:    fadd.s a0, a0, a1
+; RV64IZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; RV64IZHINXMIN-NEXT:    ld ra, 24(sp) # 8-byte Folded Reload
+; RV64IZHINXMIN-NEXT:    ld s0, 16(sp) # 8-byte Folded Reload
+; RV64IZHINXMIN-NEXT:    ld s1, 8(sp) # 8-byte Folded Reload
+; RV64IZHINXMIN-NEXT:    addi sp, sp, 32
+; RV64IZHINXMIN-NEXT:    ret
   %1 = alloca half, align 4
   call void @notdead(ptr %1)
   %2 = load half, ptr %1
   %3 = fadd half %2, %a ; force load in to FPR16
   ret half %3
 }
 
 define dso_local void @fsh_stack(half %a, half %b) nounwind {

 ; RV64IZFH-NEXT:    fadd.h fa5, fa0, fa1
 ; RV64IZFH-NEXT:    fsh fa5, 4(sp)
 ; RV64IZFH-NEXT:    addi a0, sp, 4
 ; RV64IZFH-NEXT:    call notdead@plt
 ; RV64IZFH-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64IZFH-NEXT:    addi sp, sp, 16
 ; RV64IZFH-NEXT:    ret
 ;
+; RV32IZHINX-LABEL: fsh_stack:
+; RV32IZHINX:       # %bb.0:
+; RV32IZHINX-NEXT:    addi sp, sp, -16
+; RV32IZHINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZHINX-NEXT:    fadd.h a0, a0, a1
+; RV32IZHINX-NEXT:    addi a1, sp, 8
+; RV32IZHINX-NEXT:    sh a0, 0(a1)
+; RV32IZHINX-NEXT:    addi a0, sp, 8
+; RV32IZHINX-NEXT:    call notdead@plt
+; RV32IZHINX-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZHINX-NEXT:    addi sp, sp, 16
+; RV32IZHINX-NEXT:    ret
+;
+; RV64IZHINX-LABEL: fsh_stack:
+; RV64IZHINX:       # %bb.0:
+; RV64IZHINX-NEXT:    addi sp, sp, -16
+; RV64IZHINX-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IZHINX-NEXT:    fadd.h a0, a0, a1
+; RV64IZHINX-NEXT:    addi a1, sp, 4
+; RV64IZHINX-NEXT:    sh a0, 0(a1)
+; RV64IZHINX-NEXT:    addi a0, sp, 4
+; RV64IZHINX-NEXT:    call notdead@plt
+; RV64IZHINX-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
+; RV64IZHINX-NEXT:    addi sp, sp, 16
+; RV64IZHINX-NEXT:    ret
+;
 ; RV32IZFHMIN-LABEL: fsh_stack:
 ; RV32IZFHMIN:       # %bb.0:
 ; RV32IZFHMIN-NEXT:    addi sp, sp, -16
 ; RV32IZFHMIN-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32IZFHMIN-NEXT:    fcvt.s.h fa5, fa1
 ; RV32IZFHMIN-NEXT:    fcvt.s.h fa4, fa0
 ; RV32IZFHMIN-NEXT:    fadd.s fa5, fa4, fa5
 ; RV32IZFHMIN-NEXT:    fcvt.h.s fa5, fa5

 ; RV64IZFHMIN-NEXT:    fadd.s fa5, fa4, fa5
 ; RV64IZFHMIN-NEXT:    fcvt.h.s fa5, fa5
 ; RV64IZFHMIN-NEXT:    fsh fa5, 4(sp)
 ; RV64IZFHMIN-NEXT:    addi a0, sp, 4
 ; RV64IZFHMIN-NEXT:    call notdead@plt
 ; RV64IZFHMIN-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64IZFHMIN-NEXT:    addi sp, sp, 16
 ; RV64IZFHMIN-NEXT:    ret
+;
+; RV32IZHINXMIN-LABEL: fsh_stack:
+; RV32IZHINXMIN:       # %bb.0:
+; RV32IZHINXMIN-NEXT:    addi sp, sp, -16
+; RV32IZHINXMIN-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZHINXMIN-NEXT:    fcvt.s.h a1, a1
+; RV32IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV32IZHINXMIN-NEXT:    fadd.s a0, a0, a1
+; RV32IZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; RV32IZHINXMIN-NEXT:    addi a1, sp, 8
+; RV32IZHINXMIN-NEXT:    sh a0, 0(a1)
+; RV32IZHINXMIN-NEXT:    addi a0, sp, 8
+; RV32IZHINXMIN-NEXT:    call notdead@plt
+; RV32IZHINXMIN-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZHINXMIN-NEXT:    addi sp, sp, 16
+; RV32IZHINXMIN-NEXT:    ret
+;
+; RV64IZHINXMIN-LABEL: fsh_stack:
+; RV64IZHINXMIN:       # %bb.0:
+; RV64IZHINXMIN-NEXT:    addi sp, sp, -16
+; RV64IZHINXMIN-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IZHINXMIN-NEXT:    fcvt.s.h a1, a1
+; RV64IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV64IZHINXMIN-NEXT:    fadd.s a0, a0, a1
+; RV64IZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; RV64IZHINXMIN-NEXT:    addi a1, sp, 4
+; RV64IZHINXMIN-NEXT:    sh a0, 0(a1)
+; RV64IZHINXMIN-NEXT:    addi a0, sp, 4
+; RV64IZHINXMIN-NEXT:    call notdead@plt
+; RV64IZHINXMIN-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
+; RV64IZHINXMIN-NEXT:    addi sp, sp, 16
+; RV64IZHINXMIN-NEXT:    ret
   %1 = fadd half %a, %b ; force store from FPR16
   %2 = alloca half, align 4
   store half %1, ptr %2
   call void @notdead(ptr %2)
   ret void
 }

llvm/test/CodeGen/RISCV/half-round-conv-sat.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -mattr=+zfh -verify-machineinstrs < %s \
 ; RUN:   -target-abi=ilp32f | FileCheck -check-prefixes=CHECKIZFH,RV32IZFH %s
 ; RUN: llc -mtriple=riscv64 -mattr=+zfh -verify-machineinstrs < %s \
 ; RUN:   -target-abi=lp64f | FileCheck -check-prefixes=CHECKIZFH,RV64IZFH %s
+; RUN: llc -mtriple=riscv32 -mattr=+zhinx -verify-machineinstrs < %s \
+; RUN:   -target-abi=ilp32 | FileCheck -check-prefixes=CHECKIZHINX,RV32IZHINX %s
+; RUN: llc -mtriple=riscv64 -mattr=+zhinx -verify-machineinstrs < %s \
+; RUN:   -target-abi=lp64 | FileCheck -check-prefixes=CHECKIZHINX,RV64IZHINX %s
 ; RUN: llc -mtriple=riscv32 -mattr=+zfhmin -verify-machineinstrs < %s \
 ; RUN:   -target-abi=ilp32f | FileCheck -check-prefixes=CHECKIZFHMIN,RV32IZFHMIN %s
 ; RUN: llc -mtriple=riscv64 -mattr=+zfhmin -verify-machineinstrs < %s \
 ; RUN:   -target-abi=lp64f | FileCheck -check-prefixes=CHECKIZFHMIN,RV64IZFHMIN %s
+; RUN: llc -mtriple=riscv32 -mattr=+zhinxmin -verify-machineinstrs < %s \
+; RUN:   -target-abi=ilp32 | FileCheck -check-prefixes=CHECKIZHINXMIN,RV32IZHINXMIN %s
+; RUN: llc -mtriple=riscv64 -mattr=+zhinxmin -verify-machineinstrs < %s \
+; RUN:   -target-abi=lp64 | FileCheck -check-prefixes=CHECKIZHINXMIN,RV64IZHINXMIN %s
 
 define signext i32 @test_floor_si32(half %x) {
 ; CHECKIZFH-LABEL: test_floor_si32:
 ; CHECKIZFH:       # %bb.0:
 ; CHECKIZFH-NEXT:    fcvt.w.h a0, fa0, rdn
 ; CHECKIZFH-NEXT:    feq.h a1, fa0, fa0
 ; CHECKIZFH-NEXT:    seqz a1, a1
 ; CHECKIZFH-NEXT:    addi a1, a1, -1
 ; CHECKIZFH-NEXT:    and a0, a1, a0
 ; CHECKIZFH-NEXT:    ret
 ;
+; CHECKIZHINX-LABEL: test_floor_si32:
+; CHECKIZHINX:       # %bb.0:
+; CHECKIZHINX-NEXT:    lui a1, %hi(.LCPI0_0)
+; CHECKIZHINX-NEXT:    lh a1, %lo(.LCPI0_0)(a1)
+; CHECKIZHINX-NEXT:    fabs.h a2, a0
+; CHECKIZHINX-NEXT:    flt.h a1, a2, a1
+; CHECKIZHINX-NEXT:    beqz a1, .LBB0_2
+; CHECKIZHINX-NEXT:  # %bb.1:
+; CHECKIZHINX-NEXT:    fcvt.w.h a1, a0, rdn
+; CHECKIZHINX-NEXT:    fcvt.h.w a1, a1, rdn
+; CHECKIZHINX-NEXT:    fsgnj.h a0, a1, a0
+; CHECKIZHINX-NEXT:  .LBB0_2:
+; CHECKIZHINX-NEXT:    fcvt.w.h a1, a0, rtz
+; CHECKIZHINX-NEXT:    feq.h a0, a0, a0
+; CHECKIZHINX-NEXT:    seqz a0, a0
+; CHECKIZHINX-NEXT:    addi a0, a0, -1
+; CHECKIZHINX-NEXT:    and a0, a0, a1
+; CHECKIZHINX-NEXT:    ret
+;
 ; CHECKIZFHMIN-LABEL: test_floor_si32:
 ; CHECKIZFHMIN:       # %bb.0:
 ; CHECKIZFHMIN-NEXT:    fcvt.s.h fa5, fa0
 ; CHECKIZFHMIN-NEXT:    lui a0, 307200
 ; CHECKIZFHMIN-NEXT:    fmv.w.x fa4, a0
 ; CHECKIZFHMIN-NEXT:    fabs.s fa3, fa5
 ; CHECKIZFHMIN-NEXT:    flt.s a0, fa3, fa4
 ; CHECKIZFHMIN-NEXT:    beqz a0, .LBB0_2
 ; CHECKIZFHMIN-NEXT:  # %bb.1:
 ; CHECKIZFHMIN-NEXT:    fcvt.w.s a0, fa5, rdn
 ; CHECKIZFHMIN-NEXT:    fcvt.s.w fa4, a0, rdn
 ; CHECKIZFHMIN-NEXT:    fsgnj.s fa5, fa4, fa5
 ; CHECKIZFHMIN-NEXT:  .LBB0_2:
 ; CHECKIZFHMIN-NEXT:    fcvt.h.s fa5, fa5
 ; CHECKIZFHMIN-NEXT:    fcvt.s.h fa5, fa5
 ; CHECKIZFHMIN-NEXT:    fcvt.w.s a0, fa5, rtz
 ; CHECKIZFHMIN-NEXT:    feq.s a1, fa5, fa5
 ; CHECKIZFHMIN-NEXT:    seqz a1, a1
 ; CHECKIZFHMIN-NEXT:    addi a1, a1, -1
 ; CHECKIZFHMIN-NEXT:    and a0, a1, a0
 ; CHECKIZFHMIN-NEXT:    ret
+;
+; CHECKIZHINXMIN-LABEL: test_floor_si32:
+; CHECKIZHINXMIN:       # %bb.0:
+; CHECKIZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECKIZHINXMIN-NEXT:    lui a1, 307200
+; CHECKIZHINXMIN-NEXT:    fabs.s a2, a0
+; CHECKIZHINXMIN-NEXT:    flt.s a1, a2, a1
+; CHECKIZHINXMIN-NEXT:    beqz a1, .LBB0_2
+; CHECKIZHINXMIN-NEXT:  # %bb.1:
+; CHECKIZHINXMIN-NEXT:    fcvt.w.s a1, a0, rdn
+; CHECKIZHINXMIN-NEXT:    fcvt.s.w a1, a1, rdn
+; CHECKIZHINXMIN-NEXT:    fsgnj.s a0, a1, a0
+; CHECKIZHINXMIN-NEXT:  .LBB0_2:
+; CHECKIZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; CHECKIZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECKIZHINXMIN-NEXT:    fcvt.w.s a1, a0, rtz
+; CHECKIZHINXMIN-NEXT:    feq.s a0, a0, a0
+; CHECKIZHINXMIN-NEXT:    seqz a0, a0
+; CHECKIZHINXMIN-NEXT:    addi a0, a0, -1
+; CHECKIZHINXMIN-NEXT:    and a0, a0, a1
+; CHECKIZHINXMIN-NEXT:    ret
   %a = call half @llvm.floor.f16(half %x)
   %b = call i32 @llvm.fptosi.sat.i32.f16(half %a)
   ret i32 %b
 }
 
 define i64 @test_floor_si64(half %x) nounwind {
 ; RV32IZFH-LABEL: test_floor_si64:
 ; RV32IZFH:       # %bb.0:

 ; RV64IZFH:       # %bb.0:
 ; RV64IZFH-NEXT:    fcvt.l.h a0, fa0, rdn
 ; RV64IZFH-NEXT:    feq.h a1, fa0, fa0
 ; RV64IZFH-NEXT:    seqz a1, a1
 ; RV64IZFH-NEXT:    addi a1, a1, -1
 ; RV64IZFH-NEXT:    and a0, a1, a0
 ; RV64IZFH-NEXT:    ret
 ;
+; RV32IZHINX-LABEL: test_floor_si64:
+; RV32IZHINX:       # %bb.0:
+; RV32IZHINX-NEXT:    addi sp, sp, -16
+; RV32IZHINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZHINX-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
+; RV32IZHINX-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
+; RV32IZHINX-NEXT:    sw s2, 0(sp) # 4-byte Folded Spill
+; RV32IZHINX-NEXT:    lui a1, %hi(.LCPI1_0)
+; RV32IZHINX-NEXT:    lh a1, %lo(.LCPI1_0)(a1)
+; RV32IZHINX-NEXT:    fabs.h a2, a0
+; RV32IZHINX-NEXT:    flt.h a1, a2, a1
+; RV32IZHINX-NEXT:    beqz a1, .LBB1_2
+; RV32IZHINX-NEXT:  # %bb.1:
+; RV32IZHINX-NEXT:    fcvt.w.h a1, a0, rdn
+; RV32IZHINX-NEXT:    fcvt.h.w a1, a1, rdn
+; RV32IZHINX-NEXT:    fsgnj.h a0, a1, a0
+; RV32IZHINX-NEXT:  .LBB1_2:
+; RV32IZHINX-NEXT:    fcvt.s.h s0, a0
+; RV32IZHINX-NEXT:    lui a0, 913408
+; RV32IZHINX-NEXT:    fle.s s1, a0, s0
+; RV32IZHINX-NEXT:    neg s2, s1
+; RV32IZHINX-NEXT:    mv a0, s0
+; RV32IZHINX-NEXT:    call __fixsfdi@plt
+; RV32IZHINX-NEXT:    lui a2, %hi(.LCPI1_1)
+; RV32IZHINX-NEXT:    lw a2, %lo(.LCPI1_1)(a2)
+; RV32IZHINX-NEXT:    and a0, s2, a0
+; RV32IZHINX-NEXT:    flt.s a4, a2, s0
+; RV32IZHINX-NEXT:    neg a2, a4
+; RV32IZHINX-NEXT:    or a0, a2, a0
+; RV32IZHINX-NEXT:    feq.s a2, s0, s0
+; RV32IZHINX-NEXT:    neg a2, a2
+; RV32IZHINX-NEXT:    lui a5, 524288
+; RV32IZHINX-NEXT:    lui a3, 524288
+; RV32IZHINX-NEXT:    beqz s1, .LBB1_4
+; RV32IZHINX-NEXT:  # %bb.3:
+; RV32IZHINX-NEXT:    mv a3, a1
+; RV32IZHINX-NEXT:  .LBB1_4:
+; RV32IZHINX-NEXT:    and a0, a2, a0
+; RV32IZHINX-NEXT:    beqz a4, .LBB1_6
+; RV32IZHINX-NEXT:  # %bb.5:
+; RV32IZHINX-NEXT:    addi a3, a5, -1
+; RV32IZHINX-NEXT:  .LBB1_6:
+; RV32IZHINX-NEXT:    and a1, a2, a3
+; RV32IZHINX-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZHINX-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
+; RV32IZHINX-NEXT:    lw s1, 4(sp) # 4-byte Folded Reload
+; RV32IZHINX-NEXT:    lw s2, 0(sp) # 4-byte Folded Reload
+; RV32IZHINX-NEXT:    addi sp, sp, 16
+; RV32IZHINX-NEXT:    ret
+;
+; RV64IZHINX-LABEL: test_floor_si64:
+; RV64IZHINX:       # %bb.0:
+; RV64IZHINX-NEXT:    lui a1, %hi(.LCPI1_0)
+; RV64IZHINX-NEXT:    lh a1, %lo(.LCPI1_0)(a1)
+; RV64IZHINX-NEXT:    fabs.h a2, a0
+; RV64IZHINX-NEXT:    flt.h a1, a2, a1
+; RV64IZHINX-NEXT:    beqz a1, .LBB1_2
+; RV64IZHINX-NEXT:  # %bb.1:
+; RV64IZHINX-NEXT:    fcvt.w.h a1, a0, rdn
+; RV64IZHINX-NEXT:    fcvt.h.w a1, a1, rdn
+; RV64IZHINX-NEXT:    fsgnj.h a0, a1, a0
+; RV64IZHINX-NEXT:  .LBB1_2:
+; RV64IZHINX-NEXT:    fcvt.l.h a1, a0, rtz
+; RV64IZHINX-NEXT:    feq.h a0, a0, a0
+; RV64IZHINX-NEXT:    seqz a0, a0
+; RV64IZHINX-NEXT:    addi a0, a0, -1
+; RV64IZHINX-NEXT:    and a0, a0, a1
+; RV64IZHINX-NEXT:    ret
+;
 ; RV32IZFHMIN-LABEL: test_floor_si64:
 ; RV32IZFHMIN:       # %bb.0:
 ; RV32IZFHMIN-NEXT:    fcvt.s.h fa5, fa0
 ; RV32IZFHMIN-NEXT:    lui a0, 307200
 ; RV32IZFHMIN-NEXT:    fmv.w.x fa4, a0
 ; RV32IZFHMIN-NEXT:    fabs.s fa3, fa5
 ; RV32IZFHMIN-NEXT:    flt.s a0, fa3, fa4
 ; RV32IZFHMIN-NEXT:    beqz a0, .LBB1_2

 ; RV64IZFHMIN-NEXT:    fcvt.h.s fa5, fa5
 ; RV64IZFHMIN-NEXT:    fcvt.s.h fa5, fa5
 ; RV64IZFHMIN-NEXT:    fcvt.l.s a0, fa5, rtz
 ; RV64IZFHMIN-NEXT:    feq.s a1, fa5, fa5
 ; RV64IZFHMIN-NEXT:    seqz a1, a1
 ; RV64IZFHMIN-NEXT:    addi a1, a1, -1
 ; RV64IZFHMIN-NEXT:    and a0, a1, a0
 ; RV64IZFHMIN-NEXT:    ret
+;
+; RV32IZHINXMIN-LABEL: test_floor_si64:
+; RV32IZHINXMIN:       # %bb.0:
+; RV32IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV32IZHINXMIN-NEXT:    lui a1, 307200
+; RV32IZHINXMIN-NEXT:    fabs.s a2, a0
+; RV32IZHINXMIN-NEXT:    flt.s a1, a2, a1
+; RV32IZHINXMIN-NEXT:    beqz a1, .LBB1_2
+; RV32IZHINXMIN-NEXT:  # %bb.1:
+; RV32IZHINXMIN-NEXT:    fcvt.w.s a1, a0, rdn
+; RV32IZHINXMIN-NEXT:    fcvt.s.w a1, a1, rdn
+; RV32IZHINXMIN-NEXT:    fsgnj.s a0, a1, a0
+; RV32IZHINXMIN-NEXT:  .LBB1_2:
+; RV32IZHINXMIN-NEXT:    addi sp, sp, -16
+; RV32IZHINXMIN-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZHINXMIN-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
+; RV32IZHINXMIN-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
+; RV32IZHINXMIN-NEXT:    sw s2, 0(sp) # 4-byte Folded Spill
+; RV32IZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; RV32IZHINXMIN-NEXT:    fcvt.s.h s0, a0
+; RV32IZHINXMIN-NEXT:    lui a0, 913408
+; RV32IZHINXMIN-NEXT:    fle.s s1, a0, s0
+; RV32IZHINXMIN-NEXT:    neg s2, s1
+; RV32IZHINXMIN-NEXT:    mv a0, s0
+; RV32IZHINXMIN-NEXT:    call __fixsfdi@plt
+; RV32IZHINXMIN-NEXT:    lui a2, %hi(.LCPI1_0)
+; RV32IZHINXMIN-NEXT:    lw a2, %lo(.LCPI1_0)(a2)
+; RV32IZHINXMIN-NEXT:    and a0, s2, a0
+; RV32IZHINXMIN-NEXT:    flt.s a4, a2, s0
+; RV32IZHINXMIN-NEXT:    neg a2, a4
+; RV32IZHINXMIN-NEXT:    or a0, a2, a0
+; RV32IZHINXMIN-NEXT:    feq.s a2, s0, s0
+; RV32IZHINXMIN-NEXT:    neg a2, a2
+; RV32IZHINXMIN-NEXT:    lui a5, 524288
+; RV32IZHINXMIN-NEXT:    lui a3, 524288
+; RV32IZHINXMIN-NEXT:    beqz s1, .LBB1_4
+; RV32IZHINXMIN-NEXT:  # %bb.3:
+; RV32IZHINXMIN-NEXT:    mv a3, a1
+; RV32IZHINXMIN-NEXT:  .LBB1_4:
+; RV32IZHINXMIN-NEXT:    and a0, a2, a0
+; RV32IZHINXMIN-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZHINXMIN-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
+; RV32IZHINXMIN-NEXT:    lw s1, 4(sp) # 4-byte Folded Reload
+; RV32IZHINXMIN-NEXT:    lw s2, 0(sp) # 4-byte Folded Reload
+; RV32IZHINXMIN-NEXT:    addi sp, sp, 16
+; RV32IZHINXMIN-NEXT:    beqz a4, .LBB1_6
+; RV32IZHINXMIN-NEXT:  # %bb.5:
+; RV32IZHINXMIN-NEXT:    addi a3, a5, -1
+; RV32IZHINXMIN-NEXT:  .LBB1_6:
+; RV32IZHINXMIN-NEXT:    and a1, a2, a3
+; RV32IZHINXMIN-NEXT:    ret
+;
+; RV64IZHINXMIN-LABEL: test_floor_si64:
+; RV64IZHINXMIN:       # %bb.0:
+; RV64IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV64IZHINXMIN-NEXT:    lui a1, 307200
+; RV64IZHINXMIN-NEXT:    fabs.s a2, a0
+; RV64IZHINXMIN-NEXT:    flt.s a1, a2, a1
+; RV64IZHINXMIN-NEXT:    beqz a1, .LBB1_2
+; RV64IZHINXMIN-NEXT:  # %bb.1:
+; RV64IZHINXMIN-NEXT:    fcvt.w.s a1, a0, rdn
+; RV64IZHINXMIN-NEXT:    fcvt.s.w a1, a1, rdn
+; RV64IZHINXMIN-NEXT:    fsgnj.s a0, a1, a0
+; RV64IZHINXMIN-NEXT:  .LBB1_2:
+; RV64IZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; RV64IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV64IZHINXMIN-NEXT:    fcvt.l.s a1, a0, rtz
+; RV64IZHINXMIN-NEXT:    feq.s a0, a0, a0
+; RV64IZHINXMIN-NEXT:    seqz a0, a0
+; RV64IZHINXMIN-NEXT:    addi a0, a0, -1
+; RV64IZHINXMIN-NEXT:    and a0, a0, a1
+; RV64IZHINXMIN-NEXT:    ret
   %a = call half @llvm.floor.f16(half %x)
   %b = call i64 @llvm.fptosi.sat.i64.f16(half %a)
   ret i64 %b
 }
 
 define signext i32 @test_floor_ui32(half %x) {
 ; CHECKIZFH-LABEL: test_floor_ui32:
 ; CHECKIZFH:       # %bb.0:
 ; CHECKIZFH-NEXT:    fcvt.wu.h a0, fa0, rdn
 ; CHECKIZFH-NEXT:    feq.h a1, fa0, fa0
 ; CHECKIZFH-NEXT:    seqz a1, a1
 ; CHECKIZFH-NEXT:    addi a1, a1, -1
 ; CHECKIZFH-NEXT:    and a0, a1, a0
 ; CHECKIZFH-NEXT:    ret
 ;
+; RV32IZHINX-LABEL: test_floor_ui32:
+; RV32IZHINX:       # %bb.0:
+; RV32IZHINX-NEXT:    lui a1, %hi(.LCPI2_0)
+; RV32IZHINX-NEXT:    lh a1, %lo(.LCPI2_0)(a1)
+; RV32IZHINX-NEXT:    fabs.h a2, a0
+; RV32IZHINX-NEXT:    flt.h a1, a2, a1
+; RV32IZHINX-NEXT:    beqz a1, .LBB2_2
+; RV32IZHINX-NEXT:  # %bb.1:
+; RV32IZHINX-NEXT:    fcvt.w.h a1, a0, rdn
+; RV32IZHINX-NEXT:    fcvt.h.w a1, a1, rdn
+; RV32IZHINX-NEXT:    fsgnj.h a0, a1, a0
+; RV32IZHINX-NEXT:  .LBB2_2:
+; RV32IZHINX-NEXT:    fcvt.wu.h a1, a0, rtz
+; RV32IZHINX-NEXT:    feq.h a0, a0, a0
+; RV32IZHINX-NEXT:    seqz a0, a0
+; RV32IZHINX-NEXT:    addi a0, a0, -1
+; RV32IZHINX-NEXT:    and a0, a0, a1
+; RV32IZHINX-NEXT:    ret
+;
+; RV64IZHINX-LABEL: test_floor_ui32:
+; RV64IZHINX:       # %bb.0:
+; RV64IZHINX-NEXT:    lui a1, %hi(.LCPI2_0)
+; RV64IZHINX-NEXT:    lh a1, %lo(.LCPI2_0)(a1)
+; RV64IZHINX-NEXT:    fabs.h a2, a0
+; RV64IZHINX-NEXT:    flt.h a1, a2, a1
+; RV64IZHINX-NEXT:    beqz a1, .LBB2_2
+; RV64IZHINX-NEXT:  # %bb.1:
+; RV64IZHINX-NEXT:    fcvt.w.h a1, a0, rdn
+; RV64IZHINX-NEXT:    fcvt.h.w a1, a1, rdn
+; RV64IZHINX-NEXT:    fsgnj.h a0, a1, a0
+; RV64IZHINX-NEXT:  .LBB2_2:
+; RV64IZHINX-NEXT:    fcvt.wu.h a1, a0, rtz
+; RV64IZHINX-NEXT:    feq.h a0, a0, a0
+; RV64IZHINX-NEXT:    seqz a0, a0
+; RV64IZHINX-NEXT:    addi a0, a0, -1
+; RV64IZHINX-NEXT:    and a0, a1, a0
+; RV64IZHINX-NEXT:    ret
+;
 ; RV32IZFHMIN-LABEL: test_floor_ui32:
 ; RV32IZFHMIN:       # %bb.0:
 ; RV32IZFHMIN-NEXT:    fcvt.s.h fa5, fa0
 ; RV32IZFHMIN-NEXT:    lui a0, 307200
 ; RV32IZFHMIN-NEXT:    fmv.w.x fa4, a0
 ; RV32IZFHMIN-NEXT:    fabs.s fa3, fa5
 ; RV32IZFHMIN-NEXT:    flt.s a0, fa3, fa4
 ; RV32IZFHMIN-NEXT:    beqz a0, .LBB2_2

 ; RV64IZFHMIN-NEXT:    fcvt.h.s fa5, fa5
 ; RV64IZFHMIN-NEXT:    fcvt.s.h fa5, fa5
 ; RV64IZFHMIN-NEXT:    fcvt.wu.s a0, fa5, rtz
 ; RV64IZFHMIN-NEXT:    feq.s a1, fa5, fa5
 ; RV64IZFHMIN-NEXT:    seqz a1, a1
 ; RV64IZFHMIN-NEXT:    addi a1, a1, -1
 ; RV64IZFHMIN-NEXT:    and a0, a0, a1
 ; RV64IZFHMIN-NEXT:    ret
+;
+; RV32IZHINXMIN-LABEL: test_floor_ui32:
+; RV32IZHINXMIN:       # %bb.0:
+; RV32IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV32IZHINXMIN-NEXT:    lui a1, 307200
+; RV32IZHINXMIN-NEXT:    fabs.s a2, a0
+; RV32IZHINXMIN-NEXT:    flt.s a1, a2, a1
+; RV32IZHINXMIN-NEXT:    beqz a1, .LBB2_2
+; RV32IZHINXMIN-NEXT:  # %bb.1:
+; RV32IZHINXMIN-NEXT:    fcvt.w.s a1, a0, rdn
+; RV32IZHINXMIN-NEXT:    fcvt.s.w a1, a1, rdn
+; RV32IZHINXMIN-NEXT:    fsgnj.s a0, a1, a0
+; RV32IZHINXMIN-NEXT:  .LBB2_2:
+; RV32IZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; RV32IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV32IZHINXMIN-NEXT:    fcvt.wu.s a1, a0, rtz
+; RV32IZHINXMIN-NEXT:    feq.s a0, a0, a0
+; RV32IZHINXMIN-NEXT:    seqz a0, a0
+; RV32IZHINXMIN-NEXT:    addi a0, a0, -1
+; RV32IZHINXMIN-NEXT:    and a0, a0, a1
+; RV32IZHINXMIN-NEXT:    ret
+;
+; RV64IZHINXMIN-LABEL: test_floor_ui32:
+; RV64IZHINXMIN:       # %bb.0:
+; RV64IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV64IZHINXMIN-NEXT:    lui a1, 307200
+; RV64IZHINXMIN-NEXT:    fabs.s a2, a0
+; RV64IZHINXMIN-NEXT:    flt.s a1, a2, a1
+; RV64IZHINXMIN-NEXT:    beqz a1, .LBB2_2
+; RV64IZHINXMIN-NEXT:  # %bb.1:
+; RV64IZHINXMIN-NEXT:    fcvt.w.s a1, a0, rdn
+; RV64IZHINXMIN-NEXT:    fcvt.s.w a1, a1, rdn
+; RV64IZHINXMIN-NEXT:    fsgnj.s a0, a1, a0
+; RV64IZHINXMIN-NEXT:  .LBB2_2:
+; RV64IZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; RV64IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV64IZHINXMIN-NEXT:    fcvt.wu.s a1, a0, rtz
+; RV64IZHINXMIN-NEXT:    feq.s a0, a0, a0
+; RV64IZHINXMIN-NEXT:    seqz a0, a0
+; RV64IZHINXMIN-NEXT:    addi a0, a0, -1
+; RV64IZHINXMIN-NEXT:    and a0, a1, a0
+; RV64IZHINXMIN-NEXT:    ret
   %a = call half @llvm.floor.f16(half %x)
   %b = call i32 @llvm.fptoui.sat.i32.f16(half %a)
   ret i32 %b
 }
 
 define i64 @test_floor_ui64(half %x) nounwind {
 ; RV32IZFH-LABEL: test_floor_ui64:
 ; RV32IZFH:       # %bb.0:

 ; RV64IZFH:       # %bb.0:
 ; RV64IZFH-NEXT:    fcvt.lu.h a0, fa0, rdn
 ; RV64IZFH-NEXT:    feq.h a1, fa0, fa0
 ; RV64IZFH-NEXT:    seqz a1, a1
 ; RV64IZFH-NEXT:    addi a1, a1, -1
 ; RV64IZFH-NEXT:    and a0, a1, a0
 ; RV64IZFH-NEXT:    ret
 ;
+; RV32IZHINX-LABEL: test_floor_ui64:
+; RV32IZHINX:       # %bb.0:
+; RV32IZHINX-NEXT:    addi sp, sp, -16
+; RV32IZHINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZHINX-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
+; RV32IZHINX-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
+; RV32IZHINX-NEXT:    lui a1, %hi(.LCPI3_0)
+; RV32IZHINX-NEXT:    lh a1, %lo(.LCPI3_0)(a1)
+; RV32IZHINX-NEXT:    fabs.h a2, a0
+; RV32IZHINX-NEXT:    flt.h a1, a2, a1
+; RV32IZHINX-NEXT:    beqz a1, .LBB3_2
+; RV32IZHINX-NEXT:  # %bb.1:
+; RV32IZHINX-NEXT:    fcvt.w.h a1, a0, rdn
+; RV32IZHINX-NEXT:    fcvt.h.w a1, a1, rdn
+; RV32IZHINX-NEXT:    fsgnj.h a0, a1, a0
+; RV32IZHINX-NEXT:  .LBB3_2:
+; RV32IZHINX-NEXT:    fcvt.s.h s0, a0
+; RV32IZHINX-NEXT:    fle.s a0, zero, s0
+; RV32IZHINX-NEXT:    neg s1, a0
+; RV32IZHINX-NEXT:    mv a0, s0
+; RV32IZHINX-NEXT:    call __fixunssfdi@plt
+; RV32IZHINX-NEXT:    lui a2, %hi(.LCPI3_1)
+; RV32IZHINX-NEXT:    lw a2, %lo(.LCPI3_1)(a2)
+; RV32IZHINX-NEXT:    and a0, s1, a0
+; RV32IZHINX-NEXT:    flt.s a2, a2, s0
+; RV32IZHINX-NEXT:    neg a2, a2
+; RV32IZHINX-NEXT:    or a0, a2, a0
+; RV32IZHINX-NEXT:    and a1, s1, a1
+; RV32IZHINX-NEXT:    or a1, a2, a1
+; RV32IZHINX-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZHINX-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
+; RV32IZHINX-NEXT:    lw s1, 4(sp) # 4-byte Folded Reload
+; RV32IZHINX-NEXT:    addi sp, sp, 16
+; RV32IZHINX-NEXT:    ret
+;
+; RV64IZHINX-LABEL: test_floor_ui64:
+; RV64IZHINX:       # %bb.0:
+; RV64IZHINX-NEXT:    lui a1, %hi(.LCPI3_0)
+; RV64IZHINX-NEXT:    lh a1, %lo(.LCPI3_0)(a1)
+; RV64IZHINX-NEXT:    fabs.h a2, a0
+; RV64IZHINX-NEXT:    flt.h a1, a2, a1
+; RV64IZHINX-NEXT:    beqz a1, .LBB3_2
+; RV64IZHINX-NEXT:  # %bb.1:
+; RV64IZHINX-NEXT:    fcvt.w.h a1, a0, rdn
+; RV64IZHINX-NEXT:    fcvt.h.w a1, a1, rdn
+; RV64IZHINX-NEXT:    fsgnj.h a0, a1, a0
+; RV64IZHINX-NEXT:  .LBB3_2:
+; RV64IZHINX-NEXT:    fcvt.lu.h a1, a0, rtz
+; RV64IZHINX-NEXT:    feq.h a0, a0, a0
+; RV64IZHINX-NEXT:    seqz a0, a0
+; RV64IZHINX-NEXT:    addi a0, a0, -1
+; RV64IZHINX-NEXT:    and a0, a0, a1
+; RV64IZHINX-NEXT:    ret
+;
 ; RV32IZFHMIN-LABEL: test_floor_ui64:
 ; RV32IZFHMIN:       # %bb.0:
 ; RV32IZFHMIN-NEXT:    fcvt.s.h fa5, fa0
 ; RV32IZFHMIN-NEXT:    lui a0, 307200
 ; RV32IZFHMIN-NEXT:    fmv.w.x fa4, a0
 ; RV32IZFHMIN-NEXT:    fabs.s fa3, fa5
 ; RV32IZFHMIN-NEXT:    flt.s a0, fa3, fa4
 ; RV32IZFHMIN-NEXT:    beqz a0, .LBB3_2

 ; RV64IZFHMIN-NEXT:    fcvt.h.s fa5, fa5
 ; RV64IZFHMIN-NEXT:    fcvt.s.h fa5, fa5
 ; RV64IZFHMIN-NEXT:    fcvt.lu.s a0, fa5, rtz
 ; RV64IZFHMIN-NEXT:    feq.s a1, fa5, fa5
 ; RV64IZFHMIN-NEXT:    seqz a1, a1
 ; RV64IZFHMIN-NEXT:    addi a1, a1, -1
 ; RV64IZFHMIN-NEXT:    and a0, a1, a0
 ; RV64IZFHMIN-NEXT:    ret
+;
+; RV32IZHINXMIN-LABEL: test_floor_ui64:
+; RV32IZHINXMIN:       # %bb.0:
+; RV32IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV32IZHINXMIN-NEXT:    lui a1, 307200
+; RV32IZHINXMIN-NEXT:    fabs.s a2, a0
+; RV32IZHINXMIN-NEXT:    flt.s a1, a2, a1
+; RV32IZHINXMIN-NEXT:    beqz a1, .LBB3_2
+; RV32IZHINXMIN-NEXT:  # %bb.1:
+; RV32IZHINXMIN-NEXT:    fcvt.w.s a1, a0, rdn
+; RV32IZHINXMIN-NEXT:    fcvt.s.w a1, a1, rdn
+; RV32IZHINXMIN-NEXT:    fsgnj.s a0, a1, a0
+; RV32IZHINXMIN-NEXT:  .LBB3_2:
+; RV32IZHINXMIN-NEXT:    addi sp, sp, -16
+; RV32IZHINXMIN-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZHINXMIN-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
+; RV32IZHINXMIN-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
+; RV32IZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; RV32IZHINXMIN-NEXT:    fcvt.s.h s0, a0
+; RV32IZHINXMIN-NEXT:    fle.s a0, zero, s0
+; RV32IZHINXMIN-NEXT:    neg s1, a0
+; RV32IZHINXMIN-NEXT:    mv a0, s0
+; RV32IZHINXMIN-NEXT:    call __fixunssfdi@plt
+; RV32IZHINXMIN-NEXT:    lui a2, %hi(.LCPI3_0)
+; RV32IZHINXMIN-NEXT:    lw a2, %lo(.LCPI3_0)(a2)
+; RV32IZHINXMIN-NEXT:    and a0, s1, a0
+; RV32IZHINXMIN-NEXT:    flt.s a2, a2, s0
+; RV32IZHINXMIN-NEXT:    neg a2, a2
+; RV32IZHINXMIN-NEXT:    or a0, a2, a0
+; RV32IZHINXMIN-NEXT:    and a1, s1, a1
+; RV32IZHINXMIN-NEXT:    or a1, a2, a1
+; RV32IZHINXMIN-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZHINXMIN-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
+; RV32IZHINXMIN-NEXT:    lw s1, 4(sp) # 4-byte Folded Reload
+; RV32IZHINXMIN-NEXT:    addi sp, sp, 16
+; RV32IZHINXMIN-NEXT:    ret
+;
+; RV64IZHINXMIN-LABEL: test_floor_ui64:
+; RV64IZHINXMIN:       # %bb.0:
+; RV64IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV64IZHINXMIN-NEXT:    lui a1, 307200
+; RV64IZHINXMIN-NEXT:    fabs.s a2, a0
+; RV64IZHINXMIN-NEXT:    flt.s a1, a2, a1
+; RV64IZHINXMIN-NEXT:    beqz a1, .LBB3_2
+; RV64IZHINXMIN-NEXT:  # %bb.1:
+; RV64IZHINXMIN-NEXT:    fcvt.w.s a1, a0, rdn
+; RV64IZHINXMIN-NEXT:    fcvt.s.w a1, a1, rdn
+; RV64IZHINXMIN-NEXT:    fsgnj.s a0, a1, a0
+; RV64IZHINXMIN-NEXT:  .LBB3_2:
+; RV64IZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; RV64IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV64IZHINXMIN-NEXT:    fcvt.lu.s a1, a0, rtz
+; RV64IZHINXMIN-NEXT:    feq.s a0, a0, a0
+; RV64IZHINXMIN-NEXT:    seqz a0, a0
+; RV64IZHINXMIN-NEXT:    addi a0, a0, -1
+; RV64IZHINXMIN-NEXT:    and a0, a0, a1
+; RV64IZHINXMIN-NEXT:    ret
   %a = call half @llvm.floor.f16(half %x)
   %b = call i64 @llvm.fptoui.sat.i64.f16(half %a)
   ret i64 %b
 }
 
 define signext i32 @test_ceil_si32(half %x) {
 ; CHECKIZFH-LABEL: test_ceil_si32:
 ; CHECKIZFH:       # %bb.0:
 ; CHECKIZFH-NEXT:    fcvt.w.h a0, fa0, rup
 ; CHECKIZFH-NEXT:    feq.h a1, fa0, fa0
 ; CHECKIZFH-NEXT:    seqz a1, a1
 ; CHECKIZFH-NEXT:    addi a1, a1, -1
 ; CHECKIZFH-NEXT:    and a0, a1, a0
 ; CHECKIZFH-NEXT:    ret
 ;
+; CHECKIZHINX-LABEL: test_ceil_si32:
+; CHECKIZHINX:       # %bb.0:
+; CHECKIZHINX-NEXT:    lui a1, %hi(.LCPI4_0)
+; CHECKIZHINX-NEXT:    lh a1, %lo(.LCPI4_0)(a1)
+; CHECKIZHINX-NEXT:    fabs.h a2, a0
+; CHECKIZHINX-NEXT:    flt.h a1, a2, a1
+; CHECKIZHINX-NEXT:    beqz a1, .LBB4_2
+; CHECKIZHINX-NEXT:  # %bb.1:
+; CHECKIZHINX-NEXT:    fcvt.w.h a1, a0, rup
+; CHECKIZHINX-NEXT:    fcvt.h.w a1, a1, rup
+; CHECKIZHINX-NEXT:    fsgnj.h a0, a1, a0
+; CHECKIZHINX-NEXT:  .LBB4_2:
+; CHECKIZHINX-NEXT:    fcvt.w.h a1, a0, rtz
+; CHECKIZHINX-NEXT:    feq.h a0, a0, a0
+; CHECKIZHINX-NEXT:    seqz a0, a0
+; CHECKIZHINX-NEXT:    addi a0, a0, -1
+; CHECKIZHINX-NEXT:    and a0, a0, a1
+; CHECKIZHINX-NEXT:    ret
+;
 ; CHECKIZFHMIN-LABEL: test_ceil_si32:
 ; CHECKIZFHMIN:       # %bb.0:
 ; CHECKIZFHMIN-NEXT:    fcvt.s.h fa5, fa0
 ; CHECKIZFHMIN-NEXT:    lui a0, 307200
 ; CHECKIZFHMIN-NEXT:    fmv.w.x fa4, a0
 ; CHECKIZFHMIN-NEXT:    fabs.s fa3, fa5
 ; CHECKIZFHMIN-NEXT:    flt.s a0, fa3, fa4
 ; CHECKIZFHMIN-NEXT:    beqz a0, .LBB4_2
 ; CHECKIZFHMIN-NEXT:  # %bb.1:
 ; CHECKIZFHMIN-NEXT:    fcvt.w.s a0, fa5, rup
 ; CHECKIZFHMIN-NEXT:    fcvt.s.w fa4, a0, rup
 ; CHECKIZFHMIN-NEXT:    fsgnj.s fa5, fa4, fa5
 ; CHECKIZFHMIN-NEXT:  .LBB4_2:
 ; CHECKIZFHMIN-NEXT:    fcvt.h.s fa5, fa5
 ; CHECKIZFHMIN-NEXT:    fcvt.s.h fa5, fa5
 ; CHECKIZFHMIN-NEXT:    fcvt.w.s a0, fa5, rtz
 ; CHECKIZFHMIN-NEXT:    feq.s a1, fa5, fa5
 ; CHECKIZFHMIN-NEXT:    seqz a1, a1
 ; CHECKIZFHMIN-NEXT:    addi a1, a1, -1
 ; CHECKIZFHMIN-NEXT:    and a0, a1, a0
 ; CHECKIZFHMIN-NEXT:    ret
+;
+; CHECKIZHINXMIN-LABEL: test_ceil_si32:
+; CHECKIZHINXMIN:       # %bb.0:
+; CHECKIZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECKIZHINXMIN-NEXT:    lui a1, 307200
+; CHECKIZHINXMIN-NEXT:    fabs.s a2, a0
+; CHECKIZHINXMIN-NEXT:    flt.s a1, a2, a1
+; CHECKIZHINXMIN-NEXT:    beqz a1, .LBB4_2
+; CHECKIZHINXMIN-NEXT:  # %bb.1:
+; CHECKIZHINXMIN-NEXT:    fcvt.w.s a1, a0, rup
+; CHECKIZHINXMIN-NEXT:    fcvt.s.w a1, a1, rup
+; CHECKIZHINXMIN-NEXT:    fsgnj.s a0, a1, a0
+; CHECKIZHINXMIN-NEXT:  .LBB4_2:
+; CHECKIZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; CHECKIZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECKIZHINXMIN-NEXT:    fcvt.w.s a1, a0, rtz
+; CHECKIZHINXMIN-NEXT:    feq.s a0, a0, a0
+; CHECKIZHINXMIN-NEXT:    seqz a0, a0
+; CHECKIZHINXMIN-NEXT:    addi a0, a0, -1
+; CHECKIZHINXMIN-NEXT:    and a0, a0, a1
+; CHECKIZHINXMIN-NEXT:    ret
   %a = call half @llvm.ceil.f16(half %x)
   %b = call i32 @llvm.fptosi.sat.i32.f16(half %a)
   ret i32 %b
 }
 
 define i64 @test_ceil_si64(half %x) nounwind {
 ; RV32IZFH-LABEL: test_ceil_si64:
 ; RV32IZFH:       # %bb.0:

 ; RV64IZFH:       # %bb.0:
 ; RV64IZFH-NEXT:    fcvt.l.h a0, fa0, rup
 ; RV64IZFH-NEXT:    feq.h a1, fa0, fa0
 ; RV64IZFH-NEXT:    seqz a1, a1
 ; RV64IZFH-NEXT:    addi a1, a1, -1
 ; RV64IZFH-NEXT:    and a0, a1, a0
 ; RV64IZFH-NEXT:    ret
 ;
+; RV32IZHINX-LABEL: test_ceil_si64:
+; RV32IZHINX:       # %bb.0:
+; RV32IZHINX-NEXT:    addi sp, sp, -16
+; RV32IZHINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZHINX-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
+; RV32IZHINX-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
+; RV32IZHINX-NEXT:    sw s2, 0(sp) # 4-byte Folded Spill
+; RV32IZHINX-NEXT:    lui a1, %hi(.LCPI5_0)
+; RV32IZHINX-NEXT:    lh a1, %lo(.LCPI5_0)(a1)
+; RV32IZHINX-NEXT:    fabs.h a2, a0
+; RV32IZHINX-NEXT:    flt.h a1, a2, a1
+; RV32IZHINX-NEXT:    beqz a1, .LBB5_2
+; RV32IZHINX-NEXT:  # %bb.1:
+; RV32IZHINX-NEXT:    fcvt.w.h a1, a0, rup
+; RV32IZHINX-NEXT:    fcvt.h.w a1, a1, rup
+; RV32IZHINX-NEXT:    fsgnj.h a0, a1, a0
+; RV32IZHINX-NEXT:  .LBB5_2:
+; RV32IZHINX-NEXT:    fcvt.s.h s0, a0
+; RV32IZHINX-NEXT:    lui a0, 913408
+; RV32IZHINX-NEXT:    fle.s s1, a0, s0
+; RV32IZHINX-NEXT:    neg s2, s1
+; RV32IZHINX-NEXT:    mv a0, s0
+; RV32IZHINX-NEXT:    call __fixsfdi@plt
+; RV32IZHINX-NEXT:    lui a2, %hi(.LCPI5_1)
+; RV32IZHINX-NEXT:    lw a2, %lo(.LCPI5_1)(a2)
+; RV32IZHINX-NEXT:    and a0, s2, a0
+; RV32IZHINX-NEXT:    flt.s a4, a2, s0
+; RV32IZHINX-NEXT:    neg a2, a4
+; RV32IZHINX-NEXT:    or a0, a2, a0
+; RV32IZHINX-NEXT:    feq.s a2, s0, s0
+; RV32IZHINX-NEXT:    neg a2, a2
+; RV32IZHINX-NEXT:    lui a5, 524288
+; RV32IZHINX-NEXT:    lui a3, 524288
+; RV32IZHINX-NEXT:    beqz s1, .LBB5_4
+; RV32IZHINX-NEXT:  # %bb.3:
+; RV32IZHINX-NEXT:    mv a3, a1
+; RV32IZHINX-NEXT:  .LBB5_4:
+; RV32IZHINX-NEXT:    and a0, a2, a0
+; RV32IZHINX-NEXT:    beqz a4, .LBB5_6
+; RV32IZHINX-NEXT:  # %bb.5:
+; RV32IZHINX-NEXT:    addi a3, a5, -1
+; RV32IZHINX-NEXT:  .LBB5_6:
+; RV32IZHINX-NEXT:    and a1, a2, a3
+; RV32IZHINX-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZHINX-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
+; RV32IZHINX-NEXT:    lw s1, 4(sp) # 4-byte Folded Reload
+; RV32IZHINX-NEXT:    lw s2, 0(sp) # 4-byte Folded Reload
+; RV32IZHINX-NEXT:    addi sp, sp, 16
+; RV32IZHINX-NEXT:    ret
+;
+; RV64IZHINX-LABEL: test_ceil_si64:
+; RV64IZHINX:       # %bb.0:
+; RV64IZHINX-NEXT:    lui a1, %hi(.LCPI5_0)
+; RV64IZHINX-NEXT:    lh a1, %lo(.LCPI5_0)(a1)
+; RV64IZHINX-NEXT:    fabs.h a2, a0
+; RV64IZHINX-NEXT:    flt.h a1, a2, a1
+; RV64IZHINX-NEXT:    beqz a1, .LBB5_2
+; RV64IZHINX-NEXT:  # %bb.1:
+; RV64IZHINX-NEXT:    fcvt.w.h a1, a0, rup
+; RV64IZHINX-NEXT:    fcvt.h.w a1, a1, rup
+; RV64IZHINX-NEXT:    fsgnj.h a0, a1, a0
+; RV64IZHINX-NEXT:  .LBB5_2:
+; RV64IZHINX-NEXT:    fcvt.l.h a1, a0, rtz
+; RV64IZHINX-NEXT:    feq.h a0, a0, a0
+; RV64IZHINX-NEXT:    seqz a0, a0
+; RV64IZHINX-NEXT:    addi a0, a0, -1
+; RV64IZHINX-NEXT:    and a0, a0, a1
+; RV64IZHINX-NEXT:    ret
+;
 ; RV32IZFHMIN-LABEL: test_ceil_si64:
 ; RV32IZFHMIN:       # %bb.0:
 ; RV32IZFHMIN-NEXT:    fcvt.s.h fa5, fa0
 ; RV32IZFHMIN-NEXT:    lui a0, 307200
 ; RV32IZFHMIN-NEXT:    fmv.w.x fa4, a0
 ; RV32IZFHMIN-NEXT:    fabs.s fa3, fa5
 ; RV32IZFHMIN-NEXT:    flt.s a0, fa3, fa4
 ; RV32IZFHMIN-NEXT:    beqz a0, .LBB5_2

 ; RV64IZFHMIN-NEXT:    fcvt.h.s fa5, fa5
 ; RV64IZFHMIN-NEXT:    fcvt.s.h fa5, fa5
 ; RV64IZFHMIN-NEXT:    fcvt.l.s a0, fa5, rtz
 ; RV64IZFHMIN-NEXT:    feq.s a1, fa5, fa5
 ; RV64IZFHMIN-NEXT:    seqz a1, a1
 ; RV64IZFHMIN-NEXT:    addi a1, a1, -1
 ; RV64IZFHMIN-NEXT:    and a0, a1, a0
 ; RV64IZFHMIN-NEXT:    ret
+;
+; RV32IZHINXMIN-LABEL: test_ceil_si64:
+; RV32IZHINXMIN:       # %bb.0:
+; RV32IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV32IZHINXMIN-NEXT:    lui a1, 307200
+; RV32IZHINXMIN-NEXT:    fabs.s a2, a0
+; RV32IZHINXMIN-NEXT:    flt.s a1, a2, a1
+; RV32IZHINXMIN-NEXT:    beqz a1, .LBB5_2
+; RV32IZHINXMIN-NEXT:  # %bb.1:
+; RV32IZHINXMIN-NEXT:    fcvt.w.s a1, a0, rup
+; RV32IZHINXMIN-NEXT:    fcvt.s.w a1, a1, rup
+; RV32IZHINXMIN-NEXT:    fsgnj.s a0, a1, a0
+; RV32IZHINXMIN-NEXT:  .LBB5_2:
+; RV32IZHINXMIN-NEXT:    addi sp, sp, -16
+; RV32IZHINXMIN-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZHINXMIN-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
+; RV32IZHINXMIN-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
+; RV32IZHINXMIN-NEXT:    sw s2, 0(sp) # 4-byte Folded Spill
+; RV32IZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; RV32IZHINXMIN-NEXT:    fcvt.s.h s0, a0
+; RV32IZHINXMIN-NEXT:    lui a0, 913408
+; RV32IZHINXMIN-NEXT:    fle.s s1, a0, s0
+; RV32IZHINXMIN-NEXT:    neg s2, s1
+; RV32IZHINXMIN-NEXT:    mv a0, s0
+; RV32IZHINXMIN-NEXT:    call __fixsfdi@plt
+; RV32IZHINXMIN-NEXT:    lui a2, %hi(.LCPI5_0)
+; RV32IZHINXMIN-NEXT:    lw a2, %lo(.LCPI5_0)(a2)
+; RV32IZHINXMIN-NEXT:    and a0, s2, a0
+; RV32IZHINXMIN-NEXT:    flt.s a4, a2, s0
+; RV32IZHINXMIN-NEXT:    neg a2, a4
+; RV32IZHINXMIN-NEXT:    or a0, a2, a0
+; RV32IZHINXMIN-NEXT:    feq.s a2, s0, s0
+; RV32IZHINXMIN-NEXT:    neg a2, a2
+; RV32IZHINXMIN-NEXT:    lui a5, 524288
+; RV32IZHINXMIN-NEXT:    lui a3, 524288
+; RV32IZHINXMIN-NEXT:    beqz s1, .LBB5_4
+; RV32IZHINXMIN-NEXT:  # %bb.3:
+; RV32IZHINXMIN-NEXT:    mv a3, a1
+; RV32IZHINXMIN-NEXT:  .LBB5_4:
+; RV32IZHINXMIN-NEXT:    and a0, a2, a0
+; RV32IZHINXMIN-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZHINXMIN-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
+; RV32IZHINXMIN-NEXT:    lw s1, 4(sp) # 4-byte Folded Reload
+; RV32IZHINXMIN-NEXT:    lw s2, 0(sp) # 4-byte Folded Reload
+; RV32IZHINXMIN-NEXT:    addi sp, sp, 16
+; RV32IZHINXMIN-NEXT:    beqz a4, .LBB5_6
+; RV32IZHINXMIN-NEXT:  # %bb.5:
+; RV32IZHINXMIN-NEXT:    addi a3, a5, -1
+; RV32IZHINXMIN-NEXT:  .LBB5_6:
+; RV32IZHINXMIN-NEXT:    and a1, a2, a3
+; RV32IZHINXMIN-NEXT:    ret
+;
+; RV64IZHINXMIN-LABEL: test_ceil_si64:
+; RV64IZHINXMIN:       # %bb.0:
+; RV64IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV64IZHINXMIN-NEXT:    lui a1, 307200
+; RV64IZHINXMIN-NEXT:    fabs.s a2, a0
+; RV64IZHINXMIN-NEXT:    flt.s a1, a2, a1
+; RV64IZHINXMIN-NEXT:    beqz a1, .LBB5_2
+; RV64IZHINXMIN-NEXT:  # %bb.1:
+; RV64IZHINXMIN-NEXT:    fcvt.w.s a1, a0, rup
+; RV64IZHINXMIN-NEXT:    fcvt.s.w a1, a1, rup
+; RV64IZHINXMIN-NEXT:    fsgnj.s a0, a1, a0
+; RV64IZHINXMIN-NEXT:  .LBB5_2:
+; RV64IZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; RV64IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV64IZHINXMIN-NEXT:    fcvt.l.s a1, a0, rtz
+; RV64IZHINXMIN-NEXT:    feq.s a0, a0, a0
+; RV64IZHINXMIN-NEXT:    seqz a0, a0
+; RV64IZHINXMIN-NEXT:    addi a0, a0, -1
+; RV64IZHINXMIN-NEXT:    and a0, a0, a1
+; RV64IZHINXMIN-NEXT:    ret
   %a = call half @llvm.ceil.f16(half %x)
   %b = call i64 @llvm.fptosi.sat.i64.f16(half %a)
   ret i64 %b
 }
 
 define signext i32 @test_ceil_ui32(half %x) {
 ; CHECKIZFH-LABEL: test_ceil_ui32:
 ; CHECKIZFH:       # %bb.0:
 ; CHECKIZFH-NEXT:    fcvt.wu.h a0, fa0, rup
 ; CHECKIZFH-NEXT:    feq.h a1, fa0, fa0
 ; CHECKIZFH-NEXT:    seqz a1, a1
 ; CHECKIZFH-NEXT:    addi a1, a1, -1
 ; CHECKIZFH-NEXT:    and a0, a1, a0
 ; CHECKIZFH-NEXT:    ret
 ;
+; RV32IZHINX-LABEL: test_ceil_ui32:
+; RV32IZHINX:       # %bb.0:
+; RV32IZHINX-NEXT:    lui a1, %hi(.LCPI6_0)
+; RV32IZHINX-NEXT:    lh a1, %lo(.LCPI6_0)(a1)
+; RV32IZHINX-NEXT:    fabs.h a2, a0
+; RV32IZHINX-NEXT:    flt.h a1, a2, a1
+; RV32IZHINX-NEXT:    beqz a1, .LBB6_2
+; RV32IZHINX-NEXT:  # %bb.1:
+; RV32IZHINX-NEXT:    fcvt.w.h a1, a0, rup
+; RV32IZHINX-NEXT:    fcvt.h.w a1, a1, rup
+; RV32IZHINX-NEXT:    fsgnj.h a0, a1, a0
+; RV32IZHINX-NEXT:  .LBB6_2:
+; RV32IZHINX-NEXT:    fcvt.wu.h a1, a0, rtz
+; RV32IZHINX-NEXT:    feq.h a0, a0, a0
+; RV32IZHINX-NEXT:    seqz a0, a0
+; RV32IZHINX-NEXT:    addi a0, a0, -1
+; RV32IZHINX-NEXT:    and a0, a0, a1
+; RV32IZHINX-NEXT:    ret
+;
+; RV64IZHINX-LABEL: test_ceil_ui32:
+; RV64IZHINX:       # %bb.0:
+; RV64IZHINX-NEXT:    lui a1, %hi(.LCPI6_0)
+; RV64IZHINX-NEXT:    lh a1, %lo(.LCPI6_0)(a1)
+; RV64IZHINX-NEXT:    fabs.h a2, a0
+; RV64IZHINX-NEXT:    flt.h a1, a2, a1
+; RV64IZHINX-NEXT:    beqz a1, .LBB6_2
+; RV64IZHINX-NEXT:  # %bb.1:
+; RV64IZHINX-NEXT:    fcvt.w.h a1, a0, rup
+; RV64IZHINX-NEXT:    fcvt.h.w a1, a1, rup
+; RV64IZHINX-NEXT:    fsgnj.h a0, a1, a0
+; RV64IZHINX-NEXT:  .LBB6_2:
+; RV64IZHINX-NEXT:    fcvt.wu.h a1, a0, rtz
+; RV64IZHINX-NEXT:    feq.h a0, a0, a0
+; RV64IZHINX-NEXT:    seqz a0, a0
+; RV64IZHINX-NEXT:    addi a0, a0, -1
+; RV64IZHINX-NEXT:    and a0, a1, a0
+; RV64IZHINX-NEXT:    ret
+;
 ; RV32IZFHMIN-LABEL: test_ceil_ui32:
 ; RV32IZFHMIN:       # %bb.0:
 ; RV32IZFHMIN-NEXT:    fcvt.s.h fa5, fa0
 ; RV32IZFHMIN-NEXT:    lui a0, 307200
 ; RV32IZFHMIN-NEXT:    fmv.w.x fa4, a0
 ; RV32IZFHMIN-NEXT:    fabs.s fa3, fa5
 ; RV32IZFHMIN-NEXT:    flt.s a0, fa3, fa4
 ; RV32IZFHMIN-NEXT:    beqz a0, .LBB6_2

 ; RV64IZFHMIN-NEXT:    fcvt.h.s fa5, fa5
 ; RV64IZFHMIN-NEXT:    fcvt.s.h fa5, fa5
 ; RV64IZFHMIN-NEXT:    fcvt.wu.s a0, fa5, rtz
 ; RV64IZFHMIN-NEXT:    feq.s a1, fa5, fa5
 ; RV64IZFHMIN-NEXT:    seqz a1, a1
 ; RV64IZFHMIN-NEXT:    addi a1, a1, -1
 ; RV64IZFHMIN-NEXT:    and a0, a0, a1
 ; RV64IZFHMIN-NEXT:    ret
+;
+; RV32IZHINXMIN-LABEL: test_ceil_ui32:
+; RV32IZHINXMIN:       # %bb.0:
+; RV32IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV32IZHINXMIN-NEXT:    lui a1, 307200
+; RV32IZHINXMIN-NEXT:    fabs.s a2, a0
+; RV32IZHINXMIN-NEXT:    flt.s a1, a2, a1
+; RV32IZHINXMIN-NEXT:    beqz a1, .LBB6_2
+; RV32IZHINXMIN-NEXT:  # %bb.1:
+; RV32IZHINXMIN-NEXT:    fcvt.w.s a1, a0, rup
+; RV32IZHINXMIN-NEXT:    fcvt.s.w a1, a1, rup
+; RV32IZHINXMIN-NEXT:    fsgnj.s a0, a1, a0
+; RV32IZHINXMIN-NEXT:  .LBB6_2:
+; RV32IZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; RV32IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV32IZHINXMIN-NEXT:    fcvt.wu.s a1, a0, rtz
+; RV32IZHINXMIN-NEXT:    feq.s a0, a0, a0
+; RV32IZHINXMIN-NEXT:    seqz a0, a0
+; RV32IZHINXMIN-NEXT:    addi a0, a0, -1
+; RV32IZHINXMIN-NEXT:    and a0, a0, a1
+; RV32IZHINXMIN-NEXT:    ret
+;
+; RV64IZHINXMIN-LABEL: test_ceil_ui32:
+; RV64IZHINXMIN:       # %bb.0:
+; RV64IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV64IZHINXMIN-NEXT:    lui a1, 307200
+; RV64IZHINXMIN-NEXT:    fabs.s a2, a0
+; RV64IZHINXMIN-NEXT:    flt.s a1, a2, a1
+; RV64IZHINXMIN-NEXT:    beqz a1, .LBB6_2
+; RV64IZHINXMIN-NEXT:  # %bb.1:
+; RV64IZHINXMIN-NEXT:    fcvt.w.s a1, a0, rup
+; RV64IZHINXMIN-NEXT:    fcvt.s.w a1, a1, rup
+; RV64IZHINXMIN-NEXT:    fsgnj.s a0, a1, a0
+; RV64IZHINXMIN-NEXT:  .LBB6_2:
+; RV64IZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; RV64IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV64IZHINXMIN-NEXT:    fcvt.wu.s a1, a0, rtz
+; RV64IZHINXMIN-NEXT:    feq.s a0, a0, a0
+; RV64IZHINXMIN-NEXT:    seqz a0, a0
+; RV64IZHINXMIN-NEXT:    addi a0, a0, -1
+; RV64IZHINXMIN-NEXT:    and a0, a1, a0
+; RV64IZHINXMIN-NEXT:    ret
   %a = call half @llvm.ceil.f16(half %x)
   %b = call i32 @llvm.fptoui.sat.i32.f16(half %a)
   ret i32 %b
 }
 
 define i64 @test_ceil_ui64(half %x) nounwind {
 ; RV32IZFH-LABEL: test_ceil_ui64:
 ; RV32IZFH:       # %bb.0:

 ; RV64IZFH:       # %bb.0:
 ; RV64IZFH-NEXT:    fcvt.lu.h a0, fa0, rup
 ; RV64IZFH-NEXT:    feq.h a1, fa0, fa0
 ; RV64IZFH-NEXT:    seqz a1, a1
 ; RV64IZFH-NEXT:    addi a1, a1, -1
 ; RV64IZFH-NEXT:    and a0, a1, a0
 ; RV64IZFH-NEXT:    ret
 ;
+; RV32IZHINX-LABEL: test_ceil_ui64:
+; RV32IZHINX:       # %bb.0:
+; RV32IZHINX-NEXT:    addi sp, sp, -16
+; RV32IZHINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZHINX-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
+; RV32IZHINX-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
+; RV32IZHINX-NEXT:    lui a1, %hi(.LCPI7_0)
+; RV32IZHINX-NEXT:    lh a1, %lo(.LCPI7_0)(a1)
+; RV32IZHINX-NEXT:    fabs.h a2, a0
+; RV32IZHINX-NEXT:    flt.h a1, a2, a1
+; RV32IZHINX-NEXT:    beqz a1, .LBB7_2
+; RV32IZHINX-NEXT:  # %bb.1:
+; RV32IZHINX-NEXT:    fcvt.w.h a1, a0, rup
+; RV32IZHINX-NEXT:    fcvt.h.w a1, a1, rup
+; RV32IZHINX-NEXT:    fsgnj.h a0, a1, a0
+; RV32IZHINX-NEXT:  .LBB7_2:
+; RV32IZHINX-NEXT:    fcvt.s.h s0, a0
+; RV32IZHINX-NEXT:    fle.s a0, zero, s0
+; RV32IZHINX-NEXT:    neg s1, a0
+; RV32IZHINX-NEXT:    mv a0, s0
+; RV32IZHINX-NEXT:    call __fixunssfdi@plt
+; RV32IZHINX-NEXT:    lui a2, %hi(.LCPI7_1)
+; RV32IZHINX-NEXT:    lw a2, %lo(.LCPI7_1)(a2)
+; RV32IZHINX-NEXT:    and a0, s1, a0
+; RV32IZHINX-NEXT:    flt.s a2, a2, s0
+; RV32IZHINX-NEXT:    neg a2, a2
+; RV32IZHINX-NEXT:    or a0, a2, a0
+; RV32IZHINX-NEXT:    and a1, s1, a1
+; RV32IZHINX-NEXT:    or a1, a2, a1
+; RV32IZHINX-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZHINX-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
+; RV32IZHINX-NEXT:    lw s1, 4(sp) # 4-byte Folded Reload
+; RV32IZHINX-NEXT:    addi sp, sp, 16
+; RV32IZHINX-NEXT:    ret
+;
+; RV64IZHINX-LABEL: test_ceil_ui64:
+; RV64IZHINX:       # %bb.0:
+; RV64IZHINX-NEXT:    lui a1, %hi(.LCPI7_0)
+; RV64IZHINX-NEXT:    lh a1, %lo(.LCPI7_0)(a1)
+; RV64IZHINX-NEXT:    fabs.h a2, a0
+; RV64IZHINX-NEXT:    flt.h a1, a2, a1
+; RV64IZHINX-NEXT:    beqz a1, .LBB7_2
+; RV64IZHINX-NEXT:  # %bb.1:
+; RV64IZHINX-NEXT:    fcvt.w.h a1, a0, rup
+; RV64IZHINX-NEXT:    fcvt.h.w a1, a1, rup
+; RV64IZHINX-NEXT:    fsgnj.h a0, a1, a0
+; RV64IZHINX-NEXT:  .LBB7_2:
+; RV64IZHINX-NEXT:    fcvt.lu.h a1, a0, rtz
+; RV64IZHINX-NEXT:    feq.h a0, a0, a0
+; RV64IZHINX-NEXT:    seqz a0, a0
+; RV64IZHINX-NEXT:    addi a0, a0, -1
+; RV64IZHINX-NEXT:    and a0, a0, a1
+; RV64IZHINX-NEXT:    ret
+;
 ; RV32IZFHMIN-LABEL: test_ceil_ui64:
 ; RV32IZFHMIN:       # %bb.0:
 ; RV32IZFHMIN-NEXT:    fcvt.s.h fa5, fa0
 ; RV32IZFHMIN-NEXT:    lui a0, 307200
 ; RV32IZFHMIN-NEXT:    fmv.w.x fa4, a0
 ; RV32IZFHMIN-NEXT:    fabs.s fa3, fa5
 ; RV32IZFHMIN-NEXT:    flt.s a0, fa3, fa4
 ; RV32IZFHMIN-NEXT:    beqz a0, .LBB7_2

 ; RV64IZFHMIN-NEXT:    fcvt.h.s fa5, fa5
 ; RV64IZFHMIN-NEXT:    fcvt.s.h fa5, fa5
 ; RV64IZFHMIN-NEXT:    fcvt.lu.s a0, fa5, rtz
 ; RV64IZFHMIN-NEXT:    feq.s a1, fa5, fa5
 ; RV64IZFHMIN-NEXT:    seqz a1, a1
 ; RV64IZFHMIN-NEXT:    addi a1, a1, -1
 ; RV64IZFHMIN-NEXT:    and a0, a1, a0
 ; RV64IZFHMIN-NEXT:    ret
+;
+; RV32IZHINXMIN-LABEL: test_ceil_ui64:
+; RV32IZHINXMIN:       # %bb.0:
+; RV32IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV32IZHINXMIN-NEXT:    lui a1, 307200
+; RV32IZHINXMIN-NEXT:    fabs.s a2, a0
+; RV32IZHINXMIN-NEXT:    flt.s a1, a2, a1
+; RV32IZHINXMIN-NEXT:    beqz a1, .LBB7_2
+; RV32IZHINXMIN-NEXT:  # %bb.1:
+; RV32IZHINXMIN-NEXT:    fcvt.w.s a1, a0, rup
+; RV32IZHINXMIN-NEXT:    fcvt.s.w a1, a1, rup
+; RV32IZHINXMIN-NEXT:    fsgnj.s a0, a1, a0
+; RV32IZHINXMIN-NEXT:  .LBB7_2:
+; RV32IZHINXMIN-NEXT:    addi sp, sp, -16
+; RV32IZHINXMIN-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZHINXMIN-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
+; RV32IZHINXMIN-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
+; RV32IZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; RV32IZHINXMIN-NEXT:    fcvt.s.h s0, a0
+; RV32IZHINXMIN-NEXT:    fle.s a0, zero, s0
+; RV32IZHINXMIN-NEXT:    neg s1, a0
+; RV32IZHINXMIN-NEXT:    mv a0, s0
+; RV32IZHINXMIN-NEXT:    call __fixunssfdi@plt
+; RV32IZHINXMIN-NEXT:    lui a2, %hi(.LCPI7_0)
+; RV32IZHINXMIN-NEXT:    lw a2, %lo(.LCPI7_0)(a2)
+; RV32IZHINXMIN-NEXT:    and a0, s1, a0
+; RV32IZHINXMIN-NEXT:    flt.s a2, a2, s0
+; RV32IZHINXMIN-NEXT:    neg a2, a2
+; RV32IZHINXMIN-NEXT:    or a0, a2, a0
+; RV32IZHINXMIN-NEXT:    and a1, s1, a1
+; RV32IZHINXMIN-NEXT:    or a1, a2, a1
+; RV32IZHINXMIN-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZHINXMIN-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
+; RV32IZHINXMIN-NEXT:    lw s1, 4(sp) # 4-byte Folded Reload
+; RV32IZHINXMIN-NEXT:    addi sp, sp, 16
+; RV32IZHINXMIN-NEXT:    ret
+;
+; RV64IZHINXMIN-LABEL: test_ceil_ui64:
+; RV64IZHINXMIN:       # %bb.0:
+; RV64IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV64IZHINXMIN-NEXT:    lui a1, 307200
+; RV64IZHINXMIN-NEXT:    fabs.s a2, a0
+; RV64IZHINXMIN-NEXT:    flt.s a1, a2, a1
+; RV64IZHINXMIN-NEXT:    beqz a1, .LBB7_2
+; RV64IZHINXMIN-NEXT:  # %bb.1:
+; RV64IZHINXMIN-NEXT:    fcvt.w.s a1, a0, rup
+; RV64IZHINXMIN-NEXT:    fcvt.s.w a1, a1, rup
+; RV64IZHINXMIN-NEXT:    fsgnj.s a0, a1, a0
+; RV64IZHINXMIN-NEXT:  .LBB7_2:
+; RV64IZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; RV64IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV64IZHINXMIN-NEXT:    fcvt.lu.s a1, a0, rtz
+; RV64IZHINXMIN-NEXT:    feq.s a0, a0, a0
+; RV64IZHINXMIN-NEXT:    seqz a0, a0
+; RV64IZHINXMIN-NEXT:    addi a0, a0, -1
+; RV64IZHINXMIN-NEXT:    and a0, a0, a1
+; RV64IZHINXMIN-NEXT:    ret
   %a = call half @llvm.ceil.f16(half %x)
   %b = call i64 @llvm.fptoui.sat.i64.f16(half %a)
   ret i64 %b
 }
 
 define signext i32 @test_trunc_si32(half %x) {
 ; CHECKIZFH-LABEL: test_trunc_si32:
 ; CHECKIZFH:       # %bb.0:
 ; CHECKIZFH-NEXT:    fcvt.w.h a0, fa0, rtz
 ; CHECKIZFH-NEXT:    feq.h a1, fa0, fa0
 ; CHECKIZFH-NEXT:    seqz a1, a1
 ; CHECKIZFH-NEXT:    addi a1, a1, -1
 ; CHECKIZFH-NEXT:    and a0, a1, a0
 ; CHECKIZFH-NEXT:    ret
 ;
+; CHECKIZHINX-LABEL: test_trunc_si32:
+; CHECKIZHINX:       # %bb.0:
+; CHECKIZHINX-NEXT:    lui a1, %hi(.LCPI8_0)
+; CHECKIZHINX-NEXT:    lh a1, %lo(.LCPI8_0)(a1)
+; CHECKIZHINX-NEXT:    fabs.h a2, a0
+; CHECKIZHINX-NEXT:    flt.h a1, a2, a1
+; CHECKIZHINX-NEXT:    beqz a1, .LBB8_2
+; CHECKIZHINX-NEXT:  # %bb.1:
+; CHECKIZHINX-NEXT:    fcvt.w.h a1, a0, rtz
+; CHECKIZHINX-NEXT:    fcvt.h.w a1, a1, rtz
+; CHECKIZHINX-NEXT:    fsgnj.h a0, a1, a0
+; CHECKIZHINX-NEXT:  .LBB8_2:
+; CHECKIZHINX-NEXT:    fcvt.w.h a1, a0, rtz
+; CHECKIZHINX-NEXT:    feq.h a0, a0, a0
+; CHECKIZHINX-NEXT:    seqz a0, a0
+; CHECKIZHINX-NEXT:    addi a0, a0, -1
+; CHECKIZHINX-NEXT:    and a0, a0, a1
+; CHECKIZHINX-NEXT:    ret
+;
 ; CHECKIZFHMIN-LABEL: test_trunc_si32:
 ; CHECKIZFHMIN:       # %bb.0:
 ; CHECKIZFHMIN-NEXT:    fcvt.s.h fa5, fa0
 ; CHECKIZFHMIN-NEXT:    lui a0, 307200
 ; CHECKIZFHMIN-NEXT:    fmv.w.x fa4, a0
 ; CHECKIZFHMIN-NEXT:    fabs.s fa3, fa5
 ; CHECKIZFHMIN-NEXT:    flt.s a0, fa3, fa4
 ; CHECKIZFHMIN-NEXT:    beqz a0, .LBB8_2
 ; CHECKIZFHMIN-NEXT:  # %bb.1:
 ; CHECKIZFHMIN-NEXT:    fcvt.w.s a0, fa5, rtz
 ; CHECKIZFHMIN-NEXT:    fcvt.s.w fa4, a0, rtz
 ; CHECKIZFHMIN-NEXT:    fsgnj.s fa5, fa4, fa5
 ; CHECKIZFHMIN-NEXT:  .LBB8_2:
 ; CHECKIZFHMIN-NEXT:    fcvt.h.s fa5, fa5
 ; CHECKIZFHMIN-NEXT:    fcvt.s.h fa5, fa5
 ; CHECKIZFHMIN-NEXT:    fcvt.w.s a0, fa5, rtz
 ; CHECKIZFHMIN-NEXT:    feq.s a1, fa5, fa5
 ; CHECKIZFHMIN-NEXT:    seqz a1, a1
 ; CHECKIZFHMIN-NEXT:    addi a1, a1, -1
 ; CHECKIZFHMIN-NEXT:    and a0, a1, a0
 ; CHECKIZFHMIN-NEXT:    ret
+;
+; CHECKIZHINXMIN-LABEL: test_trunc_si32:
+; CHECKIZHINXMIN:       # %bb.0:
+; CHECKIZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECKIZHINXMIN-NEXT:    lui a1, 307200
+; CHECKIZHINXMIN-NEXT:    fabs.s a2, a0
+; CHECKIZHINXMIN-NEXT:    flt.s a1, a2, a1
+; CHECKIZHINXMIN-NEXT:    beqz a1, .LBB8_2
+; CHECKIZHINXMIN-NEXT:  # %bb.1:
+; CHECKIZHINXMIN-NEXT:    fcvt.w.s a1, a0, rtz
+; CHECKIZHINXMIN-NEXT:    fcvt.s.w a1, a1, rtz
+; CHECKIZHINXMIN-NEXT:    fsgnj.s a0, a1, a0
+; CHECKIZHINXMIN-NEXT:  .LBB8_2:
+; CHECKIZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; CHECKIZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECKIZHINXMIN-NEXT:    fcvt.w.s a1, a0, rtz
+; CHECKIZHINXMIN-NEXT:    feq.s a0, a0, a0
+; CHECKIZHINXMIN-NEXT:    seqz a0, a0
+; CHECKIZHINXMIN-NEXT:    addi a0, a0, -1
+; CHECKIZHINXMIN-NEXT:    and a0, a0, a1
+; CHECKIZHINXMIN-NEXT:    ret
   %a = call half @llvm.trunc.f16(half %x)
   %b = call i32 @llvm.fptosi.sat.i32.f16(half %a)
   ret i32 %b
 }
 
 define i64 @test_trunc_si64(half %x) nounwind {
 ; RV32IZFH-LABEL: test_trunc_si64:
 ; RV32IZFH:       # %bb.0:

 ; RV64IZFH:       # %bb.0:
 ; RV64IZFH-NEXT:    fcvt.l.h a0, fa0, rtz
 ; RV64IZFH-NEXT:    feq.h a1, fa0, fa0
 ; RV64IZFH-NEXT:    seqz a1, a1
 ; RV64IZFH-NEXT:    addi a1, a1, -1
 ; RV64IZFH-NEXT:    and a0, a1, a0
 ; RV64IZFH-NEXT:    ret
 ;
+; RV32IZHINX-LABEL: test_trunc_si64:
+; RV32IZHINX:       # %bb.0:
+; RV32IZHINX-NEXT:    addi sp, sp, -16
+; RV32IZHINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZHINX-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
+; RV32IZHINX-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
+; RV32IZHINX-NEXT:    sw s2, 0(sp) # 4-byte Folded Spill
+; RV32IZHINX-NEXT:    lui a1, %hi(.LCPI9_0)
+; RV32IZHINX-NEXT:    lh a1, %lo(.LCPI9_0)(a1)
+; RV32IZHINX-NEXT:    fabs.h a2, a0
+; RV32IZHINX-NEXT:    flt.h a1, a2, a1
+; RV32IZHINX-NEXT:    beqz a1, .LBB9_2
+; RV32IZHINX-NEXT:  # %bb.1:
+; RV32IZHINX-NEXT:    fcvt.w.h a1, a0, rtz
+; RV32IZHINX-NEXT:    fcvt.h.w a1, a1, rtz
+; RV32IZHINX-NEXT:    fsgnj.h a0, a1, a0
+; RV32IZHINX-NEXT:  .LBB9_2:
+; RV32IZHINX-NEXT:    fcvt.s.h s0, a0
+; RV32IZHINX-NEXT:    lui a0, 913408
+; RV32IZHINX-NEXT:    fle.s s1, a0, s0
+; RV32IZHINX-NEXT:    neg s2, s1
+; RV32IZHINX-NEXT:    mv a0, s0
+; RV32IZHINX-NEXT:    call __fixsfdi@plt
+; RV32IZHINX-NEXT:    lui a2, %hi(.LCPI9_1)
+; RV32IZHINX-NEXT:    lw a2, %lo(.LCPI9_1)(a2)
+; RV32IZHINX-NEXT:    and a0, s2, a0
+; RV32IZHINX-NEXT:    flt.s a4, a2, s0
+; RV32IZHINX-NEXT:    neg a2, a4
+; RV32IZHINX-NEXT:    or a0, a2, a0
+; RV32IZHINX-NEXT:    feq.s a2, s0, s0
+; RV32IZHINX-NEXT:    neg a2, a2
+; RV32IZHINX-NEXT:    lui a5, 524288
+; RV32IZHINX-NEXT:    lui a3, 524288
+; RV32IZHINX-NEXT:    beqz s1, .LBB9_4
+; RV32IZHINX-NEXT:  # %bb.3:
+; RV32IZHINX-NEXT:    mv a3, a1
+; RV32IZHINX-NEXT:  .LBB9_4:
+; RV32IZHINX-NEXT:    and a0, a2, a0
+; RV32IZHINX-NEXT:    beqz a4, .LBB9_6
+; RV32IZHINX-NEXT:  # %bb.5:
+; RV32IZHINX-NEXT:    addi a3, a5, -1
+; RV32IZHINX-NEXT:  .LBB9_6:
+; RV32IZHINX-NEXT:    and a1, a2, a3
+; RV32IZHINX-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZHINX-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
+; RV32IZHINX-NEXT:    lw s1, 4(sp) # 4-byte Folded Reload
+; RV32IZHINX-NEXT:    lw s2, 0(sp) # 4-byte Folded Reload
+; RV32IZHINX-NEXT:    addi sp, sp, 16
+; RV32IZHINX-NEXT:    ret
+;
+; RV64IZHINX-LABEL: test_trunc_si64:
+; RV64IZHINX:       # %bb.0:
+; RV64IZHINX-NEXT:    lui a1, %hi(.LCPI9_0)
+; RV64IZHINX-NEXT:    lh a1, %lo(.LCPI9_0)(a1)
+; RV64IZHINX-NEXT:    fabs.h a2, a0
+; RV64IZHINX-NEXT:    flt.h a1, a2, a1
+; RV64IZHINX-NEXT:    beqz a1, .LBB9_2
+; RV64IZHINX-NEXT:  # %bb.1:
+; RV64IZHINX-NEXT:    fcvt.w.h a1, a0, rtz
+; RV64IZHINX-NEXT:    fcvt.h.w a1, a1, rtz
+; RV64IZHINX-NEXT:    fsgnj.h a0, a1, a0
+; RV64IZHINX-NEXT:  .LBB9_2:
+; RV64IZHINX-NEXT:    fcvt.l.h a1, a0, rtz
+; RV64IZHINX-NEXT:    feq.h a0, a0, a0
+; RV64IZHINX-NEXT:    seqz a0, a0
+; RV64IZHINX-NEXT:    addi a0, a0, -1
+; RV64IZHINX-NEXT:    and a0, a0, a1
+; RV64IZHINX-NEXT:    ret
+;
 ; RV32IZFHMIN-LABEL: test_trunc_si64:
 ; RV32IZFHMIN:       # %bb.0:
 ; RV32IZFHMIN-NEXT:    fcvt.s.h fa5, fa0
 ; RV32IZFHMIN-NEXT:    lui a0, 307200
 ; RV32IZFHMIN-NEXT:    fmv.w.x fa4, a0
 ; RV32IZFHMIN-NEXT:    fabs.s fa3, fa5
 ; RV32IZFHMIN-NEXT:    flt.s a0, fa3, fa4
 ; RV32IZFHMIN-NEXT:    beqz a0, .LBB9_2

 ; RV64IZFHMIN-NEXT:    fcvt.h.s fa5, fa5
 ; RV64IZFHMIN-NEXT:    fcvt.s.h fa5, fa5
 ; RV64IZFHMIN-NEXT:    fcvt.l.s a0, fa5, rtz
 ; RV64IZFHMIN-NEXT:    feq.s a1, fa5, fa5
 ; RV64IZFHMIN-NEXT:    seqz a1, a1
 ; RV64IZFHMIN-NEXT:    addi a1, a1, -1
 ; RV64IZFHMIN-NEXT:    and a0, a1, a0
 ; RV64IZFHMIN-NEXT:    ret
+;
+; RV32IZHINXMIN-LABEL: test_trunc_si64:
+; RV32IZHINXMIN:       # %bb.0:
+; RV32IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV32IZHINXMIN-NEXT:    lui a1, 307200
+; RV32IZHINXMIN-NEXT:    fabs.s a2, a0
+; RV32IZHINXMIN-NEXT:    flt.s a1, a2, a1
+; RV32IZHINXMIN-NEXT:    beqz a1, .LBB9_2
+; RV32IZHINXMIN-NEXT:  # %bb.1:
+; RV32IZHINXMIN-NEXT:    fcvt.w.s a1, a0, rtz
+; RV32IZHINXMIN-NEXT:    fcvt.s.w a1, a1, rtz
+; RV32IZHINXMIN-NEXT:    fsgnj.s a0, a1, a0
+; RV32IZHINXMIN-NEXT:  .LBB9_2:
+; RV32IZHINXMIN-NEXT:    addi sp, sp, -16
+; RV32IZHINXMIN-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZHINXMIN-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
+; RV32IZHINXMIN-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
+; RV32IZHINXMIN-NEXT:    sw s2, 0(sp) # 4-byte Folded Spill
+; RV32IZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; RV32IZHINXMIN-NEXT:    fcvt.s.h s0, a0
+; RV32IZHINXMIN-NEXT:    lui a0, 913408
+; RV32IZHINXMIN-NEXT:    fle.s s1, a0, s0
+; RV32IZHINXMIN-NEXT:    neg s2, s1
+; RV32IZHINXMIN-NEXT:    mv a0, s0
+; RV32IZHINXMIN-NEXT:    call __fixsfdi@plt
+; RV32IZHINXMIN-NEXT:    lui a2, %hi(.LCPI9_0)
+; RV32IZHINXMIN-NEXT:    lw a2, %lo(.LCPI9_0)(a2)
+; RV32IZHINXMIN-NEXT:    and a0, s2, a0
+; RV32IZHINXMIN-NEXT:    flt.s a4, a2, s0
+; RV32IZHINXMIN-NEXT:    neg a2, a4
+; RV32IZHINXMIN-NEXT:    or a0, a2, a0
+; RV32IZHINXMIN-NEXT:    feq.s a2, s0, s0
+; RV32IZHINXMIN-NEXT:    neg a2, a2
+; RV32IZHINXMIN-NEXT:    lui a5, 524288
+; RV32IZHINXMIN-NEXT:    lui a3, 524288
+; RV32IZHINXMIN-NEXT:    beqz s1, .LBB9_4
+; RV32IZHINXMIN-NEXT:  # %bb.3:
+; RV32IZHINXMIN-NEXT:    mv a3, a1
+; RV32IZHINXMIN-NEXT:  .LBB9_4:
+; RV32IZHINXMIN-NEXT:    and a0, a2, a0
+; RV32IZHINXMIN-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZHINXMIN-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
+; RV32IZHINXMIN-NEXT:    lw s1, 4(sp) # 4-byte Folded Reload
+; RV32IZHINXMIN-NEXT:    lw s2, 0(sp) # 4-byte Folded Reload
+; RV32IZHINXMIN-NEXT:    addi sp, sp, 16
+; RV32IZHINXMIN-NEXT:    beqz a4, .LBB9_6
+; RV32IZHINXMIN-NEXT:  # %bb.5:
+; RV32IZHINXMIN-NEXT:    addi a3, a5, -1
+; RV32IZHINXMIN-NEXT:  .LBB9_6:
+; RV32IZHINXMIN-NEXT:    and a1, a2, a3
+; RV32IZHINXMIN-NEXT:    ret
+;
+; RV64IZHINXMIN-LABEL: test_trunc_si64:
+; RV64IZHINXMIN:       # %bb.0:
+; RV64IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV64IZHINXMIN-NEXT:    lui a1, 307200
+; RV64IZHINXMIN-NEXT:    fabs.s a2, a0
+; RV64IZHINXMIN-NEXT:    flt.s a1, a2, a1
+; RV64IZHINXMIN-NEXT:    beqz a1, .LBB9_2
+; RV64IZHINXMIN-NEXT:  # %bb.1:
+; RV64IZHINXMIN-NEXT:    fcvt.w.s a1, a0, rtz
+; RV64IZHINXMIN-NEXT:    fcvt.s.w a1, a1, rtz
+; RV64IZHINXMIN-NEXT:    fsgnj.s a0, a1, a0
+; RV64IZHINXMIN-NEXT:  .LBB9_2:
+; RV64IZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; RV64IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV64IZHINXMIN-NEXT:    fcvt.l.s a1, a0, rtz
+; RV64IZHINXMIN-NEXT:    feq.s a0, a0, a0
+; RV64IZHINXMIN-NEXT:    seqz a0, a0
+; RV64IZHINXMIN-NEXT:    addi a0, a0, -1
+; RV64IZHINXMIN-NEXT:    and a0, a0, a1
+; RV64IZHINXMIN-NEXT:    ret
   %a = call half @llvm.trunc.f16(half %x)
   %b = call i64 @llvm.fptosi.sat.i64.f16(half %a)
   ret i64 %b
 }
 
 define signext i32 @test_trunc_ui32(half %x) {
 ; CHECKIZFH-LABEL: test_trunc_ui32:
 ; CHECKIZFH:       # %bb.0:
 ; CHECKIZFH-NEXT:    fcvt.wu.h a0, fa0, rtz
 ; CHECKIZFH-NEXT:    feq.h a1, fa0, fa0
 ; CHECKIZFH-NEXT:    seqz a1, a1
 ; CHECKIZFH-NEXT:    addi a1, a1, -1
 ; CHECKIZFH-NEXT:    and a0, a1, a0
 ; CHECKIZFH-NEXT:    ret
 ;
+; RV32IZHINX-LABEL: test_trunc_ui32:
+; RV32IZHINX:       # %bb.0:
+; RV32IZHINX-NEXT:    lui a1, %hi(.LCPI10_0)
+; RV32IZHINX-NEXT:    lh a1, %lo(.LCPI10_0)(a1)
+; RV32IZHINX-NEXT:    fabs.h a2, a0
+; RV32IZHINX-NEXT:    flt.h a1, a2, a1
+; RV32IZHINX-NEXT:    beqz a1, .LBB10_2
+; RV32IZHINX-NEXT:  # %bb.1:
+; RV32IZHINX-NEXT:    fcvt.w.h a1, a0, rtz
+; RV32IZHINX-NEXT:    fcvt.h.w a1, a1, rtz
+; RV32IZHINX-NEXT:    fsgnj.h a0, a1, a0
+; RV32IZHINX-NEXT:  .LBB10_2:
+; RV32IZHINX-NEXT:    fcvt.wu.h a1, a0, rtz
+; RV32IZHINX-NEXT:    feq.h a0, a0, a0
+; RV32IZHINX-NEXT:    seqz a0, a0
+; RV32IZHINX-NEXT:    addi a0, a0, -1
+; RV32IZHINX-NEXT:    and a0, a0, a1
+; RV32IZHINX-NEXT:    ret
+;
+; RV64IZHINX-LABEL: test_trunc_ui32:
+; RV64IZHINX:       # %bb.0:
+; RV64IZHINX-NEXT:    lui a1, %hi(.LCPI10_0)
+; RV64IZHINX-NEXT:    lh a1, %lo(.LCPI10_0)(a1)
+; RV64IZHINX-NEXT:    fabs.h a2, a0
+; RV64IZHINX-NEXT:    flt.h a1, a2, a1
+; RV64IZHINX-NEXT:    beqz a1, .LBB10_2
+; RV64IZHINX-NEXT:  # %bb.1:
+; RV64IZHINX-NEXT:    fcvt.w.h a1, a0, rtz
+; RV64IZHINX-NEXT:    fcvt.h.w a1, a1, rtz
+; RV64IZHINX-NEXT:    fsgnj.h a0, a1, a0
+; RV64IZHINX-NEXT:  .LBB10_2:
+; RV64IZHINX-NEXT:    fcvt.wu.h a1, a0, rtz
+; RV64IZHINX-NEXT:    feq.h a0, a0, a0
+; RV64IZHINX-NEXT:    seqz a0, a0
+; RV64IZHINX-NEXT:    addi a0, a0, -1
+; RV64IZHINX-NEXT:    and a0, a1, a0
+; RV64IZHINX-NEXT:    ret
+;
 ; RV32IZFHMIN-LABEL: test_trunc_ui32:
 ; RV32IZFHMIN:       # %bb.0:
 ; RV32IZFHMIN-NEXT:    fcvt.s.h fa5, fa0
 ; RV32IZFHMIN-NEXT:    lui a0, 307200
 ; RV32IZFHMIN-NEXT:    fmv.w.x fa4, a0
 ; RV32IZFHMIN-NEXT:    fabs.s fa3, fa5
 ; RV32IZFHMIN-NEXT:    flt.s a0, fa3, fa4
 ; RV32IZFHMIN-NEXT:    beqz a0, .LBB10_2

 ; RV64IZFHMIN-NEXT:    fcvt.h.s fa5, fa5
 ; RV64IZFHMIN-NEXT:    fcvt.s.h fa5, fa5
 ; RV64IZFHMIN-NEXT:    fcvt.wu.s a0, fa5, rtz
 ; RV64IZFHMIN-NEXT:    feq.s a1, fa5, fa5
 ; RV64IZFHMIN-NEXT:    seqz a1, a1
 ; RV64IZFHMIN-NEXT:    addi a1, a1, -1
 ; RV64IZFHMIN-NEXT:    and a0, a0, a1
 ; RV64IZFHMIN-NEXT:    ret
+;
+; RV32IZHINXMIN-LABEL: test_trunc_ui32:
+; RV32IZHINXMIN:       # %bb.0:
+; RV32IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV32IZHINXMIN-NEXT:    lui a1, 307200
+; RV32IZHINXMIN-NEXT:    fabs.s a2, a0
+; RV32IZHINXMIN-NEXT:    flt.s a1, a2, a1
+; RV32IZHINXMIN-NEXT:    beqz a1, .LBB10_2
+; RV32IZHINXMIN-NEXT:  # %bb.1:
+; RV32IZHINXMIN-NEXT:    fcvt.w.s a1, a0, rtz
+; RV32IZHINXMIN-NEXT:    fcvt.s.w a1, a1, rtz
+; RV32IZHINXMIN-NEXT:    fsgnj.s a0, a1, a0
+; RV32IZHINXMIN-NEXT:  .LBB10_2:
+; RV32IZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; RV32IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV32IZHINXMIN-NEXT:    fcvt.wu.s a1, a0, rtz
+; RV32IZHINXMIN-NEXT:    feq.s a0, a0, a0
+; RV32IZHINXMIN-NEXT:    seqz a0, a0
+; RV32IZHINXMIN-NEXT:    addi a0, a0, -1
+; RV32IZHINXMIN-NEXT:    and a0, a0, a1
+; RV32IZHINXMIN-NEXT:    ret
+;
+; RV64IZHINXMIN-LABEL: test_trunc_ui32:
+; RV64IZHINXMIN:       # %bb.0:
+; RV64IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV64IZHINXMIN-NEXT:    lui a1, 307200
+; RV64IZHINXMIN-NEXT:    fabs.s a2, a0
+; RV64IZHINXMIN-NEXT:    flt.s a1, a2, a1
+; RV64IZHINXMIN-NEXT:    beqz a1, .LBB10_2
+; RV64IZHINXMIN-NEXT:  # %bb.1:
+; RV64IZHINXMIN-NEXT:    fcvt.w.s a1, a0, rtz
+; RV64IZHINXMIN-NEXT:    fcvt.s.w a1, a1, rtz
+; RV64IZHINXMIN-NEXT:    fsgnj.s a0, a1, a0
+; RV64IZHINXMIN-NEXT:  .LBB10_2:
+; RV64IZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; RV64IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV64IZHINXMIN-NEXT:    fcvt.wu.s a1, a0, rtz
+; RV64IZHINXMIN-NEXT:    feq.s a0, a0, a0
+; RV64IZHINXMIN-NEXT:    seqz a0, a0
+; RV64IZHINXMIN-NEXT:    addi a0, a0, -1
+; RV64IZHINXMIN-NEXT:    and a0, a1, a0
+; RV64IZHINXMIN-NEXT:    ret
   %a = call half @llvm.trunc.f16(half %x)
   %b = call i32 @llvm.fptoui.sat.i32.f16(half %a)
   ret i32 %b
 }
 
 define i64 @test_trunc_ui64(half %x) nounwind {
 ; RV32IZFH-LABEL: test_trunc_ui64:
 ; RV32IZFH:       # %bb.0:

 ; RV64IZFH:       # %bb.0:
 ; RV64IZFH-NEXT:    fcvt.lu.h a0, fa0, rtz
 ; RV64IZFH-NEXT:    feq.h a1, fa0, fa0
 ; RV64IZFH-NEXT:    seqz a1, a1
 ; RV64IZFH-NEXT:    addi a1, a1, -1
 ; RV64IZFH-NEXT:    and a0, a1, a0
 ; RV64IZFH-NEXT:    ret
 ;
+; RV32IZHINX-LABEL: test_trunc_ui64:
+; RV32IZHINX:       # %bb.0:
+; RV32IZHINX-NEXT:    addi sp, sp, -16
+; RV32IZHINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZHINX-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
+; RV32IZHINX-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
+; RV32IZHINX-NEXT:    lui a1, %hi(.LCPI11_0)
+; RV32IZHINX-NEXT:    lh a1, %lo(.LCPI11_0)(a1)
+; RV32IZHINX-NEXT:    fabs.h a2, a0
+; RV32IZHINX-NEXT:    flt.h a1, a2, a1
+; RV32IZHINX-NEXT:    beqz a1, .LBB11_2
+; RV32IZHINX-NEXT:  # %bb.1:
+; RV32IZHINX-NEXT:    fcvt.w.h a1, a0, rtz
+; RV32IZHINX-NEXT:    fcvt.h.w a1, a1, rtz
+; RV32IZHINX-NEXT:    fsgnj.h a0, a1, a0
+; RV32IZHINX-NEXT:  .LBB11_2:
+; RV32IZHINX-NEXT:    fcvt.s.h s0, a0
+; RV32IZHINX-NEXT:    fle.s a0, zero, s0
+; RV32IZHINX-NEXT:    neg s1, a0
+; RV32IZHINX-NEXT:    mv a0, s0
+; RV32IZHINX-NEXT:    call __fixunssfdi@plt
+; RV32IZHINX-NEXT:    lui a2, %hi(.LCPI11_1)
+; RV32IZHINX-NEXT:    lw a2, %lo(.LCPI11_1)(a2)
+; RV32IZHINX-NEXT:    and a0, s1, a0
+; RV32IZHINX-NEXT:    flt.s a2, a2, s0
+; RV32IZHINX-NEXT:    neg a2, a2
+; RV32IZHINX-NEXT:    or a0, a2, a0
+; RV32IZHINX-NEXT:    and a1, s1, a1
+; RV32IZHINX-NEXT:    or a1, a2, a1
+; RV32IZHINX-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZHINX-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
+; RV32IZHINX-NEXT:    lw s1, 4(sp) # 4-byte Folded Reload
+; RV32IZHINX-NEXT:    addi sp, sp, 16
+; RV32IZHINX-NEXT:    ret
+;
+; RV64IZHINX-LABEL: test_trunc_ui64:
+; RV64IZHINX:       # %bb.0:
+; RV64IZHINX-NEXT:    lui a1, %hi(.LCPI11_0)
+; RV64IZHINX-NEXT:    lh a1, %lo(.LCPI11_0)(a1)
+; RV64IZHINX-NEXT:    fabs.h a2, a0
+; RV64IZHINX-NEXT:    flt.h a1, a2, a1
+; RV64IZHINX-NEXT:    beqz a1, .LBB11_2
+; RV64IZHINX-NEXT:  # %bb.1:
+; RV64IZHINX-NEXT:    fcvt.w.h a1, a0, rtz
+; RV64IZHINX-NEXT:    fcvt.h.w a1, a1, rtz
+; RV64IZHINX-NEXT:    fsgnj.h a0, a1, a0
+; RV64IZHINX-NEXT:  .LBB11_2:
+; RV64IZHINX-NEXT:    fcvt.lu.h a1, a0, rtz
+; RV64IZHINX-NEXT:    feq.h a0, a0, a0
+; RV64IZHINX-NEXT:    seqz a0, a0
+; RV64IZHINX-NEXT:    addi a0, a0, -1
+; RV64IZHINX-NEXT:    and a0, a0, a1
+; RV64IZHINX-NEXT:    ret
+;
 ; RV32IZFHMIN-LABEL: test_trunc_ui64:
 ; RV32IZFHMIN:       # %bb.0:
 ; RV32IZFHMIN-NEXT:    fcvt.s.h fa5, fa0
 ; RV32IZFHMIN-NEXT:    lui a0, 307200
 ; RV32IZFHMIN-NEXT:    fmv.w.x fa4, a0
 ; RV32IZFHMIN-NEXT:    fabs.s fa3, fa5
 ; RV32IZFHMIN-NEXT:    flt.s a0, fa3, fa4
 ; RV32IZFHMIN-NEXT:    beqz a0, .LBB11_2

 ; RV64IZFHMIN-NEXT:    fcvt.h.s fa5, fa5
 ; RV64IZFHMIN-NEXT:    fcvt.s.h fa5, fa5
 ; RV64IZFHMIN-NEXT:    fcvt.lu.s a0, fa5, rtz
 ; RV64IZFHMIN-NEXT:    feq.s a1, fa5, fa5
 ; RV64IZFHMIN-NEXT:    seqz a1, a1
 ; RV64IZFHMIN-NEXT:    addi a1, a1, -1
 ; RV64IZFHMIN-NEXT:    and a0, a1, a0
 ; RV64IZFHMIN-NEXT:    ret
+;
+; RV32IZHINXMIN-LABEL: test_trunc_ui64:
+; RV32IZHINXMIN:       # %bb.0:
+; RV32IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV32IZHINXMIN-NEXT:    lui a1, 307200
+; RV32IZHINXMIN-NEXT:    fabs.s a2, a0
+; RV32IZHINXMIN-NEXT:    flt.s a1, a2, a1
+; RV32IZHINXMIN-NEXT:    beqz a1, .LBB11_2
+; RV32IZHINXMIN-NEXT:  # %bb.1:
+; RV32IZHINXMIN-NEXT:    fcvt.w.s a1, a0, rtz
+; RV32IZHINXMIN-NEXT:    fcvt.s.w a1, a1, rtz
+; RV32IZHINXMIN-NEXT:    fsgnj.s a0, a1, a0
+; RV32IZHINXMIN-NEXT:  .LBB11_2:
+; RV32IZHINXMIN-NEXT:    addi sp, sp, -16
+; RV32IZHINXMIN-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZHINXMIN-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
+; RV32IZHINXMIN-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
+; RV32IZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; RV32IZHINXMIN-NEXT:    fcvt.s.h s0, a0
+; RV32IZHINXMIN-NEXT:    fle.s a0, zero, s0
+; RV32IZHINXMIN-NEXT:    neg s1, a0
+; RV32IZHINXMIN-NEXT:    mv a0, s0
+; RV32IZHINXMIN-NEXT:    call __fixunssfdi@plt
+; RV32IZHINXMIN-NEXT:    lui a2, %hi(.LCPI11_0)
+; RV32IZHINXMIN-NEXT:    lw a2, %lo(.LCPI11_0)(a2)
+; RV32IZHINXMIN-NEXT:    and a0, s1, a0
+; RV32IZHINXMIN-NEXT:    flt.s a2, a2, s0
+; RV32IZHINXMIN-NEXT:    neg a2, a2
+; RV32IZHINXMIN-NEXT:    or a0, a2, a0
+; RV32IZHINXMIN-NEXT:    and a1, s1, a1
+; RV32IZHINXMIN-NEXT:    or a1, a2, a1
+; RV32IZHINXMIN-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZHINXMIN-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
+; RV32IZHINXMIN-NEXT:    lw s1, 4(sp) # 4-byte Folded Reload
+; RV32IZHINXMIN-NEXT:    addi sp, sp, 16
+; RV32IZHINXMIN-NEXT:    ret
+;
+; RV64IZHINXMIN-LABEL: test_trunc_ui64:
+; RV64IZHINXMIN:       # %bb.0:
+; RV64IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV64IZHINXMIN-NEXT:    lui a1, 307200
+; RV64IZHINXMIN-NEXT:    fabs.s a2, a0
+; RV64IZHINXMIN-NEXT:    flt.s a1, a2, a1
+; RV64IZHINXMIN-NEXT:    beqz a1, .LBB11_2
+; RV64IZHINXMIN-NEXT:  # %bb.1:
+; RV64IZHINXMIN-NEXT:    fcvt.w.s a1, a0, rtz
+; RV64IZHINXMIN-NEXT:    fcvt.s.w a1, a1, rtz
+; RV64IZHINXMIN-NEXT:    fsgnj.s a0, a1, a0
+; RV64IZHINXMIN-NEXT:  .LBB11_2:
+; RV64IZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; RV64IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV64IZHINXMIN-NEXT:    fcvt.lu.s a1, a0, rtz
+; RV64IZHINXMIN-NEXT:    feq.s a0, a0, a0
+; RV64IZHINXMIN-NEXT:    seqz a0, a0
+; RV64IZHINXMIN-NEXT:    addi a0, a0, -1
+; RV64IZHINXMIN-NEXT:    and a0, a0, a1
+; RV64IZHINXMIN-NEXT:    ret
   %a = call half @llvm.trunc.f16(half %x)
   %b = call i64 @llvm.fptoui.sat.i64.f16(half %a)
   ret i64 %b
 }
 
 define signext i32 @test_round_si32(half %x) {
 ; CHECKIZFH-LABEL: test_round_si32:
 ; CHECKIZFH:       # %bb.0:
 ; CHECKIZFH-NEXT:    fcvt.w.h a0, fa0, rmm
 ; CHECKIZFH-NEXT:    feq.h a1, fa0, fa0
 ; CHECKIZFH-NEXT:    seqz a1, a1
 ; CHECKIZFH-NEXT:    addi a1, a1, -1
 ; CHECKIZFH-NEXT:    and a0, a1, a0
 ; CHECKIZFH-NEXT:    ret
 ;
+; CHECKIZHINX-LABEL: test_round_si32:
+; CHECKIZHINX:       # %bb.0:
+; CHECKIZHINX-NEXT:    lui a1, %hi(.LCPI12_0)
+; CHECKIZHINX-NEXT:    lh a1, %lo(.LCPI12_0)(a1)
+; CHECKIZHINX-NEXT:    fabs.h a2, a0
+; CHECKIZHINX-NEXT:    flt.h a1, a2, a1
+; CHECKIZHINX-NEXT:    beqz a1, .LBB12_2
+; CHECKIZHINX-NEXT:  # %bb.1:
+; CHECKIZHINX-NEXT:    fcvt.w.h a1, a0, rmm
+; CHECKIZHINX-NEXT:    fcvt.h.w a1, a1, rmm
+; CHECKIZHINX-NEXT:    fsgnj.h a0, a1, a0
+; CHECKIZHINX-NEXT:  .LBB12_2:
+; CHECKIZHINX-NEXT:    fcvt.w.h a1, a0, rtz
+; CHECKIZHINX-NEXT:    feq.h a0, a0, a0
+; CHECKIZHINX-NEXT:    seqz a0, a0
+; CHECKIZHINX-NEXT:    addi a0, a0, -1
+; CHECKIZHINX-NEXT:    and a0, a0, a1
+; CHECKIZHINX-NEXT:    ret
+;
 ; CHECKIZFHMIN-LABEL: test_round_si32:
 ; CHECKIZFHMIN:       # %bb.0:
 ; CHECKIZFHMIN-NEXT:    fcvt.s.h fa5, fa0
 ; CHECKIZFHMIN-NEXT:    lui a0, 307200
 ; CHECKIZFHMIN-NEXT:    fmv.w.x fa4, a0
 ; CHECKIZFHMIN-NEXT:    fabs.s fa3, fa5
 ; CHECKIZFHMIN-NEXT:    flt.s a0, fa3, fa4
 ; CHECKIZFHMIN-NEXT:    beqz a0, .LBB12_2
 ; CHECKIZFHMIN-NEXT:  # %bb.1:
 ; CHECKIZFHMIN-NEXT:    fcvt.w.s a0, fa5, rmm
 ; CHECKIZFHMIN-NEXT:    fcvt.s.w fa4, a0, rmm
 ; CHECKIZFHMIN-NEXT:    fsgnj.s fa5, fa4, fa5
 ; CHECKIZFHMIN-NEXT:  .LBB12_2:
 ; CHECKIZFHMIN-NEXT:    fcvt.h.s fa5, fa5
 ; CHECKIZFHMIN-NEXT:    fcvt.s.h fa5, fa5
 ; CHECKIZFHMIN-NEXT:    fcvt.w.s a0, fa5, rtz
 ; CHECKIZFHMIN-NEXT:    feq.s a1, fa5, fa5
 ; CHECKIZFHMIN-NEXT:    seqz a1, a1
 ; CHECKIZFHMIN-NEXT:    addi a1, a1, -1
 ; CHECKIZFHMIN-NEXT:    and a0, a1, a0
 ; CHECKIZFHMIN-NEXT:    ret
+;
+; CHECKIZHINXMIN-LABEL: test_round_si32:
+; CHECKIZHINXMIN:       # %bb.0:
+; CHECKIZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECKIZHINXMIN-NEXT:    lui a1, 307200
+; CHECKIZHINXMIN-NEXT:    fabs.s a2, a0
+; CHECKIZHINXMIN-NEXT:    flt.s a1, a2, a1
+; CHECKIZHINXMIN-NEXT:    beqz a1, .LBB12_2
+; CHECKIZHINXMIN-NEXT:  # %bb.1:
+; CHECKIZHINXMIN-NEXT:    fcvt.w.s a1, a0, rmm
+; CHECKIZHINXMIN-NEXT:    fcvt.s.w a1, a1, rmm
+; CHECKIZHINXMIN-NEXT:    fsgnj.s a0, a1, a0
+; CHECKIZHINXMIN-NEXT:  .LBB12_2:
+; CHECKIZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; CHECKIZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECKIZHINXMIN-NEXT:    fcvt.w.s a1, a0, rtz
+; CHECKIZHINXMIN-NEXT:    feq.s a0, a0, a0
+; CHECKIZHINXMIN-NEXT:    seqz a0, a0
+; CHECKIZHINXMIN-NEXT:    addi a0, a0, -1
+; CHECKIZHINXMIN-NEXT:    and a0, a0, a1
+; CHECKIZHINXMIN-NEXT:    ret
   %a = call half @llvm.round.f16(half %x)
   %b = call i32 @llvm.fptosi.sat.i32.f16(half %a)
   ret i32 %b
 }
 
 define i64 @test_round_si64(half %x) nounwind {
 ; RV32IZFH-LABEL: test_round_si64:
 ; RV32IZFH:       # %bb.0:

 ; RV64IZFH:       # %bb.0:
 ; RV64IZFH-NEXT:    fcvt.l.h a0, fa0, rmm
 ; RV64IZFH-NEXT:    feq.h a1, fa0, fa0
 ; RV64IZFH-NEXT:    seqz a1, a1
 ; RV64IZFH-NEXT:    addi a1, a1, -1
 ; RV64IZFH-NEXT:    and a0, a1, a0
 ; RV64IZFH-NEXT:    ret
 ;
+; RV32IZHINX-LABEL: test_round_si64:
+; RV32IZHINX:       # %bb.0:
+; RV32IZHINX-NEXT:    addi sp, sp, -16
+; RV32IZHINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZHINX-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
+; RV32IZHINX-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
+; RV32IZHINX-NEXT:    sw s2, 0(sp) # 4-byte Folded Spill
+; RV32IZHINX-NEXT:    lui a1, %hi(.LCPI13_0)
+; RV32IZHINX-NEXT:    lh a1, %lo(.LCPI13_0)(a1)
+; RV32IZHINX-NEXT:    fabs.h a2, a0
+; RV32IZHINX-NEXT:    flt.h a1, a2, a1
+; RV32IZHINX-NEXT:    beqz a1, .LBB13_2
+; RV32IZHINX-NEXT:  # %bb.1:
+; RV32IZHINX-NEXT:    fcvt.w.h a1, a0, rmm
+; RV32IZHINX-NEXT:    fcvt.h.w a1, a1, rmm
+; RV32IZHINX-NEXT:    fsgnj.h a0, a1, a0
+; RV32IZHINX-NEXT:  .LBB13_2:
+; RV32IZHINX-NEXT:    fcvt.s.h s0, a0
+; RV32IZHINX-NEXT:    lui a0, 913408
+; RV32IZHINX-NEXT:    fle.s s1, a0, s0
+; RV32IZHINX-NEXT:    neg s2, s1
+; RV32IZHINX-NEXT:    mv a0, s0
+; RV32IZHINX-NEXT:    call __fixsfdi@plt
+; RV32IZHINX-NEXT:    lui a2, %hi(.LCPI13_1)
+; RV32IZHINX-NEXT:    lw a2, %lo(.LCPI13_1)(a2)
+; RV32IZHINX-NEXT:    and a0, s2, a0
+; RV32IZHINX-NEXT:    flt.s a4, a2, s0
+; RV32IZHINX-NEXT:    neg a2, a4
+; RV32IZHINX-NEXT:    or a0, a2, a0
+; RV32IZHINX-NEXT:    feq.s a2, s0, s0
+; RV32IZHINX-NEXT:    neg a2, a2
+; RV32IZHINX-NEXT:    lui a5, 524288
+; RV32IZHINX-NEXT:    lui a3, 524288
+; RV32IZHINX-NEXT:    beqz s1, .LBB13_4
+; RV32IZHINX-NEXT:  # %bb.3:
+; RV32IZHINX-NEXT:    mv a3, a1
+; RV32IZHINX-NEXT:  .LBB13_4:
+; RV32IZHINX-NEXT:    and a0, a2, a0
+; RV32IZHINX-NEXT:    beqz a4, .LBB13_6
+; RV32IZHINX-NEXT:  # %bb.5:
+; RV32IZHINX-NEXT:    addi a3, a5, -1
+; RV32IZHINX-NEXT:  .LBB13_6:
+; RV32IZHINX-NEXT:    and a1, a2, a3
+; RV32IZHINX-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZHINX-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
+; RV32IZHINX-NEXT:    lw s1, 4(sp) # 4-byte Folded Reload
+; RV32IZHINX-NEXT:    lw s2, 0(sp) # 4-byte Folded Reload
+; RV32IZHINX-NEXT:    addi sp, sp, 16
+; RV32IZHINX-NEXT:    ret
+;
+; RV64IZHINX-LABEL: test_round_si64:
+; RV64IZHINX:       # %bb.0:
+; RV64IZHINX-NEXT:    lui a1, %hi(.LCPI13_0)
+; RV64IZHINX-NEXT:    lh a1, %lo(.LCPI13_0)(a1)
+; RV64IZHINX-NEXT:    fabs.h a2, a0
+; RV64IZHINX-NEXT:    flt.h a1, a2, a1
+; RV64IZHINX-NEXT:    beqz a1, .LBB13_2
+; RV64IZHINX-NEXT:  # %bb.1:
+; RV64IZHINX-NEXT:    fcvt.w.h a1, a0, rmm
+; RV64IZHINX-NEXT:    fcvt.h.w a1, a1, rmm
+; RV64IZHINX-NEXT:    fsgnj.h a0, a1, a0
+; RV64IZHINX-NEXT:  .LBB13_2:
+; RV64IZHINX-NEXT:    fcvt.l.h a1, a0, rtz
+; RV64IZHINX-NEXT:    feq.h a0, a0, a0
+; RV64IZHINX-NEXT:    seqz a0, a0
+; RV64IZHINX-NEXT:    addi a0, a0, -1
+; RV64IZHINX-NEXT:    and a0, a0, a1
+; RV64IZHINX-NEXT:    ret
+;
 ; RV32IZFHMIN-LABEL: test_round_si64:
 ; RV32IZFHMIN:       # %bb.0:
 ; RV32IZFHMIN-NEXT:    fcvt.s.h fa5, fa0
 ; RV32IZFHMIN-NEXT:    lui a0, 307200
 ; RV32IZFHMIN-NEXT:    fmv.w.x fa4, a0
 ; RV32IZFHMIN-NEXT:    fabs.s fa3, fa5
 ; RV32IZFHMIN-NEXT:    flt.s a0, fa3, fa4
 ; RV32IZFHMIN-NEXT:    beqz a0, .LBB13_2

 ; RV64IZFHMIN-NEXT:    fcvt.h.s fa5, fa5
 ; RV64IZFHMIN-NEXT:    fcvt.s.h fa5, fa5
 ; RV64IZFHMIN-NEXT:    fcvt.l.s a0, fa5, rtz
 ; RV64IZFHMIN-NEXT:    feq.s a1, fa5, fa5
 ; RV64IZFHMIN-NEXT:    seqz a1, a1
 ; RV64IZFHMIN-NEXT:    addi a1, a1, -1
 ; RV64IZFHMIN-NEXT:    and a0, a1, a0
 ; RV64IZFHMIN-NEXT:    ret
+;
+; RV32IZHINXMIN-LABEL: test_round_si64:
+; RV32IZHINXMIN:       # %bb.0:
+; RV32IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV32IZHINXMIN-NEXT:    lui a1, 307200
+; RV32IZHINXMIN-NEXT:    fabs.s a2, a0
+; RV32IZHINXMIN-NEXT:    flt.s a1, a2, a1
+; RV32IZHINXMIN-NEXT:    beqz a1, .LBB13_2
+; RV32IZHINXMIN-NEXT:  # %bb.1:
+; RV32IZHINXMIN-NEXT:    fcvt.w.s a1, a0, rmm
+; RV32IZHINXMIN-NEXT:    fcvt.s.w a1, a1, rmm
+; RV32IZHINXMIN-NEXT:    fsgnj.s a0, a1, a0
+; RV32IZHINXMIN-NEXT:  .LBB13_2:
+; RV32IZHINXMIN-NEXT:    addi sp, sp, -16
+; RV32IZHINXMIN-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZHINXMIN-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
+; RV32IZHINXMIN-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
+; RV32IZHINXMIN-NEXT:    sw s2, 0(sp) # 4-byte Folded Spill
+; RV32IZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; RV32IZHINXMIN-NEXT:    fcvt.s.h s0, a0
+; RV32IZHINXMIN-NEXT:    lui a0, 913408
+; RV32IZHINXMIN-NEXT:    fle.s s1, a0, s0
+; RV32IZHINXMIN-NEXT:    neg s2, s1
+; RV32IZHINXMIN-NEXT:    mv a0, s0
+; RV32IZHINXMIN-NEXT:    call __fixsfdi@plt
+; RV32IZHINXMIN-NEXT:    lui a2, %hi(.LCPI13_0)
+; RV32IZHINXMIN-NEXT:    lw a2, %lo(.LCPI13_0)(a2)
+; RV32IZHINXMIN-NEXT:    and a0, s2, a0
+; RV32IZHINXMIN-NEXT:    flt.s a4, a2, s0
+; RV32IZHINXMIN-NEXT:    neg a2, a4
+; RV32IZHINXMIN-NEXT:    or a0, a2, a0
+; RV32IZHINXMIN-NEXT:    feq.s a2, s0, s0
+; RV32IZHINXMIN-NEXT:    neg a2, a2
+; RV32IZHINXMIN-NEXT:    lui a5, 524288
+; RV32IZHINXMIN-NEXT:    lui a3, 524288
+; RV32IZHINXMIN-NEXT:    beqz s1, .LBB13_4
+; RV32IZHINXMIN-NEXT:  # %bb.3:
+; RV32IZHINXMIN-NEXT:    mv a3, a1
+; RV32IZHINXMIN-NEXT:  .LBB13_4:
+; RV32IZHINXMIN-NEXT:    and a0, a2, a0
+; RV32IZHINXMIN-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZHINXMIN-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
+; RV32IZHINXMIN-NEXT:    lw s1, 4(sp) # 4-byte Folded Reload
+; RV32IZHINXMIN-NEXT:    lw s2, 0(sp) # 4-byte Folded Reload
+; RV32IZHINXMIN-NEXT:    addi sp, sp, 16
+; RV32IZHINXMIN-NEXT:    beqz a4, .LBB13_6
+; RV32IZHINXMIN-NEXT:  # %bb.5:
+; RV32IZHINXMIN-NEXT:    addi a3, a5, -1
+; RV32IZHINXMIN-NEXT:  .LBB13_6:
+; RV32IZHINXMIN-NEXT:    and a1, a2, a3
+; RV32IZHINXMIN-NEXT:    ret
+;
+; RV64IZHINXMIN-LABEL: test_round_si64:
+; RV64IZHINXMIN:       # %bb.0:
+; RV64IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV64IZHINXMIN-NEXT:    lui a1, 307200
+; RV64IZHINXMIN-NEXT:    fabs.s a2, a0
+; RV64IZHINXMIN-NEXT:    flt.s a1, a2, a1
+; RV64IZHINXMIN-NEXT:    beqz a1, .LBB13_2
+; RV64IZHINXMIN-NEXT:  # %bb.1:
+; RV64IZHINXMIN-NEXT:    fcvt.w.s a1, a0, rmm
+; RV64IZHINXMIN-NEXT:    fcvt.s.w a1, a1, rmm
+; RV64IZHINXMIN-NEXT:    fsgnj.s a0, a1, a0
+; RV64IZHINXMIN-NEXT:  .LBB13_2:
+; RV64IZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; RV64IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV64IZHINXMIN-NEXT:    fcvt.l.s a1, a0, rtz
+; RV64IZHINXMIN-NEXT:    feq.s a0, a0, a0
+; RV64IZHINXMIN-NEXT:    seqz a0, a0
+; RV64IZHINXMIN-NEXT:    addi a0, a0, -1
+; RV64IZHINXMIN-NEXT:    and a0, a0, a1
+; RV64IZHINXMIN-NEXT:    ret
   %a = call half @llvm.round.f16(half %x)
   %b = call i64 @llvm.fptosi.sat.i64.f16(half %a)
   ret i64 %b
 }
 
 define signext i32 @test_round_ui32(half %x) {
 ; CHECKIZFH-LABEL: test_round_ui32:
 ; CHECKIZFH:       # %bb.0:
 ; CHECKIZFH-NEXT:    fcvt.wu.h a0, fa0, rmm
 ; CHECKIZFH-NEXT:    feq.h a1, fa0, fa0
 ; CHECKIZFH-NEXT:    seqz a1, a1
 ; CHECKIZFH-NEXT:    addi a1, a1, -1
 ; CHECKIZFH-NEXT:    and a0, a1, a0
 ; CHECKIZFH-NEXT:    ret
 ;
+; RV32IZHINX-LABEL: test_round_ui32:
+; RV32IZHINX:       # %bb.0:
+; RV32IZHINX-NEXT:    lui a1, %hi(.LCPI14_0)
+; RV32IZHINX-NEXT:    lh a1, %lo(.LCPI14_0)(a1)
+; RV32IZHINX-NEXT:    fabs.h a2, a0
+; RV32IZHINX-NEXT:    flt.h a1, a2, a1
+; RV32IZHINX-NEXT:    beqz a1, .LBB14_2
+; RV32IZHINX-NEXT:  # %bb.1:
+; RV32IZHINX-NEXT:    fcvt.w.h a1, a0, rmm
+; RV32IZHINX-NEXT:    fcvt.h.w a1, a1, rmm
+; RV32IZHINX-NEXT:    fsgnj.h a0, a1, a0
+; RV32IZHINX-NEXT:  .LBB14_2:
+; RV32IZHINX-NEXT:    fcvt.wu.h a1, a0, rtz
+; RV32IZHINX-NEXT:    feq.h a0, a0, a0
+; RV32IZHINX-NEXT:    seqz a0, a0
+; RV32IZHINX-NEXT:    addi a0, a0, -1
+; RV32IZHINX-NEXT:    and a0, a0, a1
+; RV32IZHINX-NEXT:    ret
+;
+; RV64IZHINX-LABEL: test_round_ui32:
+; RV64IZHINX:       # %bb.0:
+; RV64IZHINX-NEXT:    lui a1, %hi(.LCPI14_0)
+; RV64IZHINX-NEXT:    lh a1, %lo(.LCPI14_0)(a1)
+; RV64IZHINX-NEXT:    fabs.h a2, a0
+; RV64IZHINX-NEXT:    flt.h a1, a2, a1
+; RV64IZHINX-NEXT:    beqz a1, .LBB14_2
+; RV64IZHINX-NEXT:  # %bb.1:
+; RV64IZHINX-NEXT:    fcvt.w.h a1, a0, rmm
+; RV64IZHINX-NEXT:    fcvt.h.w a1, a1, rmm
+; RV64IZHINX-NEXT:    fsgnj.h a0, a1, a0
+; RV64IZHINX-NEXT:  .LBB14_2:
+; RV64IZHINX-NEXT:    fcvt.wu.h a1, a0, rtz
+; RV64IZHINX-NEXT:    feq.h a0, a0, a0
+; RV64IZHINX-NEXT:    seqz a0, a0
+; RV64IZHINX-NEXT:    addi a0, a0, -1
+; RV64IZHINX-NEXT:    and a0, a1, a0
+; RV64IZHINX-NEXT:    ret
+;
 ; RV32IZFHMIN-LABEL: test_round_ui32:
 ; RV32IZFHMIN:       # %bb.0:
 ; RV32IZFHMIN-NEXT:    fcvt.s.h fa5, fa0
 ; RV32IZFHMIN-NEXT:    lui a0, 307200
 ; RV32IZFHMIN-NEXT:    fmv.w.x fa4, a0
 ; RV32IZFHMIN-NEXT:    fabs.s fa3, fa5
 ; RV32IZFHMIN-NEXT:    flt.s a0, fa3, fa4
 ; RV32IZFHMIN-NEXT:    beqz a0, .LBB14_2

 ; RV64IZFHMIN-NEXT:    fcvt.h.s fa5, fa5
 ; RV64IZFHMIN-NEXT:    fcvt.s.h fa5, fa5
 ; RV64IZFHMIN-NEXT:    fcvt.wu.s a0, fa5, rtz
 ; RV64IZFHMIN-NEXT:    feq.s a1, fa5, fa5
 ; RV64IZFHMIN-NEXT:    seqz a1, a1
 ; RV64IZFHMIN-NEXT:    addi a1, a1, -1
 ; RV64IZFHMIN-NEXT:    and a0, a0, a1
 ; RV64IZFHMIN-NEXT:    ret
+;
+; RV32IZHINXMIN-LABEL: test_round_ui32:
+; RV32IZHINXMIN:       # %bb.0:
+; RV32IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV32IZHINXMIN-NEXT:    lui a1, 307200
+; RV32IZHINXMIN-NEXT:    fabs.s a2, a0
+; RV32IZHINXMIN-NEXT:    flt.s a1, a2, a1
+; RV32IZHINXMIN-NEXT:    beqz a1, .LBB14_2
+; RV32IZHINXMIN-NEXT:  # %bb.1:
+; RV32IZHINXMIN-NEXT:    fcvt.w.s a1, a0, rmm
+; RV32IZHINXMIN-NEXT:    fcvt.s.w a1, a1, rmm
+; RV32IZHINXMIN-NEXT:    fsgnj.s a0, a1, a0
+; RV32IZHINXMIN-NEXT:  .LBB14_2:
+; RV32IZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; RV32IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV32IZHINXMIN-NEXT:    fcvt.wu.s a1, a0, rtz
+; RV32IZHINXMIN-NEXT:    feq.s a0, a0, a0
+; RV32IZHINXMIN-NEXT:    seqz a0, a0
+; RV32IZHINXMIN-NEXT:    addi a0, a0, -1
+; RV32IZHINXMIN-NEXT:    and a0, a0, a1
+; RV32IZHINXMIN-NEXT:    ret
+;
+; RV64IZHINXMIN-LABEL: test_round_ui32:
+; RV64IZHINXMIN:       # %bb.0:
+; RV64IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV64IZHINXMIN-NEXT:    lui a1, 307200
+; RV64IZHINXMIN-NEXT:    fabs.s a2, a0
+; RV64IZHINXMIN-NEXT:    flt.s a1, a2, a1
+; RV64IZHINXMIN-NEXT:    beqz a1, .LBB14_2
+; RV64IZHINXMIN-NEXT:  # %bb.1:
+; RV64IZHINXMIN-NEXT:    fcvt.w.s a1, a0, rmm
+; RV64IZHINXMIN-NEXT:    fcvt.s.w a1, a1, rmm
+; RV64IZHINXMIN-NEXT:    fsgnj.s a0, a1, a0
+; RV64IZHINXMIN-NEXT:  .LBB14_2:
+; RV64IZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; RV64IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV64IZHINXMIN-NEXT:    fcvt.wu.s a1, a0, rtz
+; RV64IZHINXMIN-NEXT:    feq.s a0, a0, a0
+; RV64IZHINXMIN-NEXT:    seqz a0, a0
+; RV64IZHINXMIN-NEXT:    addi a0, a0, -1
+; RV64IZHINXMIN-NEXT:    and a0, a1, a0
+; RV64IZHINXMIN-NEXT:    ret
   %a = call half @llvm.round.f16(half %x)
   %b = call i32 @llvm.fptoui.sat.i32.f16(half %a)
   ret i32 %b
 }
 
 define i64 @test_round_ui64(half %x) nounwind {
 ; RV32IZFH-LABEL: test_round_ui64:
 ; RV32IZFH:       # %bb.0:

 ; RV64IZFH:       # %bb.0:
 ; RV64IZFH-NEXT:    fcvt.lu.h a0, fa0, rmm
 ; RV64IZFH-NEXT:    feq.h a1, fa0, fa0
 ; RV64IZFH-NEXT:    seqz a1, a1
 ; RV64IZFH-NEXT:    addi a1, a1, -1
 ; RV64IZFH-NEXT:    and a0, a1, a0
 ; RV64IZFH-NEXT:    ret
 ;
+; RV32IZHINX-LABEL: test_round_ui64:
+; RV32IZHINX:       # %bb.0:
+; RV32IZHINX-NEXT:    addi sp, sp, -16
+; RV32IZHINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZHINX-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
+; RV32IZHINX-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
+; RV32IZHINX-NEXT:    lui a1, %hi(.LCPI15_0)
+; RV32IZHINX-NEXT:    lh a1, %lo(.LCPI15_0)(a1)
+; RV32IZHINX-NEXT:    fabs.h a2, a0
+; RV32IZHINX-NEXT:    flt.h a1, a2, a1
+; RV32IZHINX-NEXT:    beqz a1, .LBB15_2
+; RV32IZHINX-NEXT:  # %bb.1:
+; RV32IZHINX-NEXT:    fcvt.w.h a1, a0, rmm
+; RV32IZHINX-NEXT:    fcvt.h.w a1, a1, rmm
+; RV32IZHINX-NEXT:    fsgnj.h a0, a1, a0
+; RV32IZHINX-NEXT:  .LBB15_2:
+; RV32IZHINX-NEXT:    fcvt.s.h s0, a0
+; RV32IZHINX-NEXT:    fle.s a0, zero, s0
+; RV32IZHINX-NEXT:    neg s1, a0
+; RV32IZHINX-NEXT:    mv a0, s0
+; RV32IZHINX-NEXT:    call __fixunssfdi@plt
+; RV32IZHINX-NEXT:    lui a2, %hi(.LCPI15_1)
+; RV32IZHINX-NEXT:    lw a2, %lo(.LCPI15_1)(a2)
+; RV32IZHINX-NEXT:    and a0, s1, a0
+; RV32IZHINX-NEXT:    flt.s a2, a2, s0
+; RV32IZHINX-NEXT:    neg a2, a2
+; RV32IZHINX-NEXT:    or a0, a2, a0
+; RV32IZHINX-NEXT:    and a1, s1, a1
+; RV32IZHINX-NEXT:    or a1, a2, a1
+; RV32IZHINX-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZHINX-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
+; RV32IZHINX-NEXT:    lw s1, 4(sp) # 4-byte Folded Reload
+; RV32IZHINX-NEXT:    addi sp, sp, 16
+; RV32IZHINX-NEXT:    ret
+;
+; RV64IZHINX-LABEL: test_round_ui64:
+; RV64IZHINX:       # %bb.0:
+; RV64IZHINX-NEXT:    lui a1, %hi(.LCPI15_0)
+; RV64IZHINX-NEXT:    lh a1, %lo(.LCPI15_0)(a1)
+; RV64IZHINX-NEXT:    fabs.h a2, a0
+; RV64IZHINX-NEXT:    flt.h a1, a2, a1
+; RV64IZHINX-NEXT:    beqz a1, .LBB15_2
+; RV64IZHINX-NEXT:  # %bb.1:
+; RV64IZHINX-NEXT:    fcvt.w.h a1, a0, rmm
+; RV64IZHINX-NEXT:    fcvt.h.w a1, a1, rmm
+; RV64IZHINX-NEXT:    fsgnj.h a0, a1, a0
+; RV64IZHINX-NEXT:  .LBB15_2:
+; RV64IZHINX-NEXT:    fcvt.lu.h a1, a0, rtz
+; RV64IZHINX-NEXT:    feq.h a0, a0, a0
+; RV64IZHINX-NEXT:    seqz a0, a0
+; RV64IZHINX-NEXT:    addi a0, a0, -1
+; RV64IZHINX-NEXT:    and a0, a0, a1
+; RV64IZHINX-NEXT:    ret
+;
 ; RV32IZFHMIN-LABEL: test_round_ui64:
 ; RV32IZFHMIN:       # %bb.0:
 ; RV32IZFHMIN-NEXT:    fcvt.s.h fa5, fa0
 ; RV32IZFHMIN-NEXT:    lui a0, 307200
 ; RV32IZFHMIN-NEXT:    fmv.w.x fa4, a0
 ; RV32IZFHMIN-NEXT:    fabs.s fa3, fa5
 ; RV32IZFHMIN-NEXT:    flt.s a0, fa3, fa4
 ; RV32IZFHMIN-NEXT:    beqz a0, .LBB15_2

 ; RV64IZFHMIN-NEXT:    fcvt.h.s fa5, fa5
 ; RV64IZFHMIN-NEXT:    fcvt.s.h fa5, fa5
 ; RV64IZFHMIN-NEXT:    fcvt.lu.s a0, fa5, rtz
 ; RV64IZFHMIN-NEXT:    feq.s a1, fa5, fa5
 ; RV64IZFHMIN-NEXT:    seqz a1, a1
 ; RV64IZFHMIN-NEXT:    addi a1, a1, -1
 ; RV64IZFHMIN-NEXT:    and a0, a1, a0
 ; RV64IZFHMIN-NEXT:    ret
+;
+; RV32IZHINXMIN-LABEL: test_round_ui64:
+; RV32IZHINXMIN:       # %bb.0:
+; RV32IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV32IZHINXMIN-NEXT:    lui a1, 307200
+; RV32IZHINXMIN-NEXT:    fabs.s a2, a0
+; RV32IZHINXMIN-NEXT:    flt.s a1, a2, a1
+; RV32IZHINXMIN-NEXT:    beqz a1, .LBB15_2
+; RV32IZHINXMIN-NEXT:  # %bb.1:
+; RV32IZHINXMIN-NEXT:    fcvt.w.s a1, a0, rmm
+; RV32IZHINXMIN-NEXT:    fcvt.s.w a1, a1, rmm
+; RV32IZHINXMIN-NEXT:    fsgnj.s a0, a1, a0
+; RV32IZHINXMIN-NEXT:  .LBB15_2:
+; RV32IZHINXMIN-NEXT:    addi sp, sp, -16
+; RV32IZHINXMIN-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZHINXMIN-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
+; RV32IZHINXMIN-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
+; RV32IZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; RV32IZHINXMIN-NEXT:    fcvt.s.h s0, a0
+; RV32IZHINXMIN-NEXT:    fle.s a0, zero, s0
+; RV32IZHINXMIN-NEXT:    neg s1, a0
+; RV32IZHINXMIN-NEXT:    mv a0, s0
+; RV32IZHINXMIN-NEXT:    call __fixunssfdi@plt
+; RV32IZHINXMIN-NEXT:    lui a2, %hi(.LCPI15_0)
+; RV32IZHINXMIN-NEXT:    lw a2, %lo(.LCPI15_0)(a2)
+; RV32IZHINXMIN-NEXT:    and a0, s1, a0
+; RV32IZHINXMIN-NEXT:    flt.s a2, a2, s0
+; RV32IZHINXMIN-NEXT:    neg a2, a2
+; RV32IZHINXMIN-NEXT:    or a0, a2, a0
+; RV32IZHINXMIN-NEXT:    and a1, s1, a1
+; RV32IZHINXMIN-NEXT:    or a1, a2, a1
+; RV32IZHINXMIN-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZHINXMIN-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
+; RV32IZHINXMIN-NEXT:    lw s1, 4(sp) # 4-byte Folded Reload
+; RV32IZHINXMIN-NEXT:    addi sp, sp, 16
+; RV32IZHINXMIN-NEXT:    ret
+;
+; RV64IZHINXMIN-LABEL: test_round_ui64:
+; RV64IZHINXMIN:       # %bb.0:
+; RV64IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV64IZHINXMIN-NEXT:    lui a1, 307200
+; RV64IZHINXMIN-NEXT:    fabs.s a2, a0
+; RV64IZHINXMIN-NEXT:    flt.s a1, a2, a1
+; RV64IZHINXMIN-NEXT:    beqz a1, .LBB15_2
+; RV64IZHINXMIN-NEXT:  # %bb.1:
+; RV64IZHINXMIN-NEXT:    fcvt.w.s a1, a0, rmm
+; RV64IZHINXMIN-NEXT:    fcvt.s.w a1, a1, rmm
+; RV64IZHINXMIN-NEXT:    fsgnj.s a0, a1, a0
+; RV64IZHINXMIN-NEXT:  .LBB15_2:
+; RV64IZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; RV64IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV64IZHINXMIN-NEXT:    fcvt.lu.s a1, a0, rtz
+; RV64IZHINXMIN-NEXT:    feq.s a0, a0, a0
+; RV64IZHINXMIN-NEXT:    seqz a0, a0
+; RV64IZHINXMIN-NEXT:    addi a0, a0, -1
+; RV64IZHINXMIN-NEXT:    and a0, a0, a1
+; RV64IZHINXMIN-NEXT:    ret
   %a = call half @llvm.round.f16(half %x)
   %b = call i64 @llvm.fptoui.sat.i64.f16(half %a)
   ret i64 %b
 }
 
 define signext i32 @test_roundeven_si32(half %x) {
 ; CHECKIZFH-LABEL: test_roundeven_si32:
 ; CHECKIZFH:       # %bb.0:
 ; CHECKIZFH-NEXT:    fcvt.w.h a0, fa0, rne
 ; CHECKIZFH-NEXT:    feq.h a1, fa0, fa0
 ; CHECKIZFH-NEXT:    seqz a1, a1
 ; CHECKIZFH-NEXT:    addi a1, a1, -1
 ; CHECKIZFH-NEXT:    and a0, a1, a0
 ; CHECKIZFH-NEXT:    ret
 ;
+; CHECKIZHINX-LABEL: test_roundeven_si32:
+; CHECKIZHINX:       # %bb.0:
+; CHECKIZHINX-NEXT:    lui a1, %hi(.LCPI16_0)
+; CHECKIZHINX-NEXT:    lh a1, %lo(.LCPI16_0)(a1)
+; CHECKIZHINX-NEXT:    fabs.h a2, a0
+; CHECKIZHINX-NEXT:    flt.h a1, a2, a1
+; CHECKIZHINX-NEXT:    beqz a1, .LBB16_2
+; CHECKIZHINX-NEXT:  # %bb.1:
+; CHECKIZHINX-NEXT:    fcvt.w.h a1, a0, rne
+; CHECKIZHINX-NEXT:    fcvt.h.w a1, a1, rne
+; CHECKIZHINX-NEXT:    fsgnj.h a0, a1, a0
+; CHECKIZHINX-NEXT:  .LBB16_2:
+; CHECKIZHINX-NEXT:    fcvt.w.h a1, a0, rtz
+; CHECKIZHINX-NEXT:    feq.h a0, a0, a0
+; CHECKIZHINX-NEXT:    seqz a0, a0
+; CHECKIZHINX-NEXT:    addi a0, a0, -1
+; CHECKIZHINX-NEXT:    and a0, a0, a1
+; CHECKIZHINX-NEXT:    ret
+;
 ; CHECKIZFHMIN-LABEL: test_roundeven_si32:
 ; CHECKIZFHMIN:       # %bb.0:
 ; CHECKIZFHMIN-NEXT:    fcvt.s.h fa5, fa0
 ; CHECKIZFHMIN-NEXT:    lui a0, 307200
 ; CHECKIZFHMIN-NEXT:    fmv.w.x fa4, a0
 ; CHECKIZFHMIN-NEXT:    fabs.s fa3, fa5
 ; CHECKIZFHMIN-NEXT:    flt.s a0, fa3, fa4
 ; CHECKIZFHMIN-NEXT:    beqz a0, .LBB16_2
 ; CHECKIZFHMIN-NEXT:  # %bb.1:
 ; CHECKIZFHMIN-NEXT:    fcvt.w.s a0, fa5, rne
 ; CHECKIZFHMIN-NEXT:    fcvt.s.w fa4, a0, rne
 ; CHECKIZFHMIN-NEXT:    fsgnj.s fa5, fa4, fa5
 ; CHECKIZFHMIN-NEXT:  .LBB16_2:
 ; CHECKIZFHMIN-NEXT:    fcvt.h.s fa5, fa5
 ; CHECKIZFHMIN-NEXT:    fcvt.s.h fa5, fa5
 ; CHECKIZFHMIN-NEXT:    fcvt.w.s a0, fa5, rtz
 ; CHECKIZFHMIN-NEXT:    feq.s a1, fa5, fa5
 ; CHECKIZFHMIN-NEXT:    seqz a1, a1
 ; CHECKIZFHMIN-NEXT:    addi a1, a1, -1
 ; CHECKIZFHMIN-NEXT:    and a0, a1, a0
 ; CHECKIZFHMIN-NEXT:    ret
+;
+; CHECKIZHINXMIN-LABEL: test_roundeven_si32:
+; CHECKIZHINXMIN:       # %bb.0:
+; CHECKIZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECKIZHINXMIN-NEXT:    lui a1, 307200
+; CHECKIZHINXMIN-NEXT:    fabs.s a2, a0
+; CHECKIZHINXMIN-NEXT:    flt.s a1, a2, a1
+; CHECKIZHINXMIN-NEXT:    beqz a1, .LBB16_2
+; CHECKIZHINXMIN-NEXT:  # %bb.1:
+; CHECKIZHINXMIN-NEXT:    fcvt.w.s a1, a0, rne
+; CHECKIZHINXMIN-NEXT:    fcvt.s.w a1, a1, rne
+; CHECKIZHINXMIN-NEXT:    fsgnj.s a0, a1, a0
+; CHECKIZHINXMIN-NEXT:  .LBB16_2:
+; CHECKIZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; CHECKIZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECKIZHINXMIN-NEXT:    fcvt.w.s a1, a0, rtz
+; CHECKIZHINXMIN-NEXT:    feq.s a0, a0, a0
+; CHECKIZHINXMIN-NEXT:    seqz a0, a0
+; CHECKIZHINXMIN-NEXT:    addi a0, a0, -1
+; CHECKIZHINXMIN-NEXT:    and a0, a0, a1
+; CHECKIZHINXMIN-NEXT:    ret
   %a = call half @llvm.roundeven.f16(half %x)
   %b = call i32 @llvm.fptosi.sat.i32.f16(half %a)
   ret i32 %b
 }
 
 define i64 @test_roundeven_si64(half %x) nounwind {
 ; RV32IZFH-LABEL: test_roundeven_si64:
 ; RV32IZFH:       # %bb.0:

 ; RV64IZFH:       # %bb.0:
 ; RV64IZFH-NEXT:    fcvt.l.h a0, fa0, rne
 ; RV64IZFH-NEXT:    feq.h a1, fa0, fa0
 ; RV64IZFH-NEXT:    seqz a1, a1
 ; RV64IZFH-NEXT:    addi a1, a1, -1
 ; RV64IZFH-NEXT:    and a0, a1, a0
 ; RV64IZFH-NEXT:    ret
 ;
+; RV32IZHINX-LABEL: test_roundeven_si64:
+; RV32IZHINX:       # %bb.0:
+; RV32IZHINX-NEXT:    addi sp, sp, -16
+; RV32IZHINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZHINX-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
+; RV32IZHINX-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
+; RV32IZHINX-NEXT:    sw s2, 0(sp) # 4-byte Folded Spill
+; RV32IZHINX-NEXT:    lui a1, %hi(.LCPI17_0)
+; RV32IZHINX-NEXT:    lh a1, %lo(.LCPI17_0)(a1)
+; RV32IZHINX-NEXT:    fabs.h a2, a0
+; RV32IZHINX-NEXT:    flt.h a1, a2, a1
+; RV32IZHINX-NEXT:    beqz a1, .LBB17_2
+; RV32IZHINX-NEXT:  # %bb.1:
+; RV32IZHINX-NEXT:    fcvt.w.h a1, a0, rne
+; RV32IZHINX-NEXT:    fcvt.h.w a1, a1, rne
+; RV32IZHINX-NEXT:    fsgnj.h a0, a1, a0
+; RV32IZHINX-NEXT:  .LBB17_2:
+; RV32IZHINX-NEXT:    fcvt.s.h s0, a0
+; RV32IZHINX-NEXT:    lui a0, 913408
+; RV32IZHINX-NEXT:    fle.s s1, a0, s0
+; RV32IZHINX-NEXT:    neg s2, s1
+; RV32IZHINX-NEXT:    mv a0, s0
+; RV32IZHINX-NEXT:    call __fixsfdi@plt
+; RV32IZHINX-NEXT:    lui a2, %hi(.LCPI17_1)
+; RV32IZHINX-NEXT:    lw a2, %lo(.LCPI17_1)(a2)
+; RV32IZHINX-NEXT:    and a0, s2, a0
+; RV32IZHINX-NEXT:    flt.s a4, a2, s0
+; RV32IZHINX-NEXT:    neg a2, a4
+; RV32IZHINX-NEXT:    or a0, a2, a0
+; RV32IZHINX-NEXT:    feq.s a2, s0, s0
+; RV32IZHINX-NEXT:    neg a2, a2
+; RV32IZHINX-NEXT:    lui a5, 524288
+; RV32IZHINX-NEXT:    lui a3, 524288
+; RV32IZHINX-NEXT:    beqz s1, .LBB17_4
+; RV32IZHINX-NEXT:  # %bb.3:
+; RV32IZHINX-NEXT:    mv a3, a1
+; RV32IZHINX-NEXT:  .LBB17_4:
+; RV32IZHINX-NEXT:    and a0, a2, a0
+; RV32IZHINX-NEXT:    beqz a4, .LBB17_6
+; RV32IZHINX-NEXT:  # %bb.5:
+; RV32IZHINX-NEXT:    addi a3, a5, -1
+; RV32IZHINX-NEXT:  .LBB17_6:
+; RV32IZHINX-NEXT:    and a1, a2, a3
+; RV32IZHINX-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZHINX-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
+; RV32IZHINX-NEXT:    lw s1, 4(sp) # 4-byte Folded Reload
+; RV32IZHINX-NEXT:    lw s2, 0(sp) # 4-byte Folded Reload
+; RV32IZHINX-NEXT:    addi sp, sp, 16
+; RV32IZHINX-NEXT:    ret
+;
+; RV64IZHINX-LABEL: test_roundeven_si64:
+; RV64IZHINX:       # %bb.0:
+; RV64IZHINX-NEXT:    lui a1, %hi(.LCPI17_0)
+; RV64IZHINX-NEXT:    lh a1, %lo(.LCPI17_0)(a1)
+; RV64IZHINX-NEXT:    fabs.h a2, a0
+; RV64IZHINX-NEXT:    flt.h a1, a2, a1
+; RV64IZHINX-NEXT:    beqz a1, .LBB17_2
+; RV64IZHINX-NEXT:  # %bb.1:
+; RV64IZHINX-NEXT:    fcvt.w.h a1, a0, rne
+; RV64IZHINX-NEXT:    fcvt.h.w a1, a1, rne
+; RV64IZHINX-NEXT:    fsgnj.h a0, a1, a0
+; RV64IZHINX-NEXT:  .LBB17_2:
+; RV64IZHINX-NEXT:    fcvt.l.h a1, a0, rtz
+; RV64IZHINX-NEXT:    feq.h a0, a0, a0
+; RV64IZHINX-NEXT:    seqz a0, a0
+; RV64IZHINX-NEXT:    addi a0, a0, -1
+; RV64IZHINX-NEXT:    and a0, a0, a1
+; RV64IZHINX-NEXT:    ret
+;
 ; RV32IZFHMIN-LABEL: test_roundeven_si64:
 ; RV32IZFHMIN:       # %bb.0:
 ; RV32IZFHMIN-NEXT:    fcvt.s.h fa5, fa0
 ; RV32IZFHMIN-NEXT:    lui a0, 307200
 ; RV32IZFHMIN-NEXT:    fmv.w.x fa4, a0
 ; RV32IZFHMIN-NEXT:    fabs.s fa3, fa5
 ; RV32IZFHMIN-NEXT:    flt.s a0, fa3, fa4
 ; RV32IZFHMIN-NEXT:    beqz a0, .LBB17_2

 ; RV64IZFHMIN-NEXT:    fcvt.h.s fa5, fa5
 ; RV64IZFHMIN-NEXT:    fcvt.s.h fa5, fa5
 ; RV64IZFHMIN-NEXT:    fcvt.l.s a0, fa5, rtz
 ; RV64IZFHMIN-NEXT:    feq.s a1, fa5, fa5
 ; RV64IZFHMIN-NEXT:    seqz a1, a1
 ; RV64IZFHMIN-NEXT:    addi a1, a1, -1
 ; RV64IZFHMIN-NEXT:    and a0, a1, a0
 ; RV64IZFHMIN-NEXT:    ret
+;
+; RV32IZHINXMIN-LABEL: test_roundeven_si64:
+; RV32IZHINXMIN:       # %bb.0:
+; RV32IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV32IZHINXMIN-NEXT:    lui a1, 307200
+; RV32IZHINXMIN-NEXT:    fabs.s a2, a0
+; RV32IZHINXMIN-NEXT:    flt.s a1, a2, a1
+; RV32IZHINXMIN-NEXT:    beqz a1, .LBB17_2
+; RV32IZHINXMIN-NEXT:  # %bb.1:
+; RV32IZHINXMIN-NEXT:    fcvt.w.s a1, a0, rne
+; RV32IZHINXMIN-NEXT:    fcvt.s.w a1, a1, rne
+; RV32IZHINXMIN-NEXT:    fsgnj.s a0, a1, a0
+; RV32IZHINXMIN-NEXT:  .LBB17_2:
+; RV32IZHINXMIN-NEXT:    addi sp, sp, -16
+; RV32IZHINXMIN-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZHINXMIN-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
+; RV32IZHINXMIN-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
+; RV32IZHINXMIN-NEXT:    sw s2, 0(sp) # 4-byte Folded Spill
+; RV32IZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; RV32IZHINXMIN-NEXT:    fcvt.s.h s0, a0
+; RV32IZHINXMIN-NEXT:    lui a0, 913408
+; RV32IZHINXMIN-NEXT:    fle.s s1, a0, s0
+; RV32IZHINXMIN-NEXT:    neg s2, s1
+; RV32IZHINXMIN-NEXT:    mv a0, s0
+; RV32IZHINXMIN-NEXT:    call __fixsfdi@plt
+; RV32IZHINXMIN-NEXT:    lui a2, %hi(.LCPI17_0)
+; RV32IZHINXMIN-NEXT:    lw a2, %lo(.LCPI17_0)(a2)
+; RV32IZHINXMIN-NEXT:    and a0, s2, a0
+; RV32IZHINXMIN-NEXT:    flt.s a4, a2, s0
+; RV32IZHINXMIN-NEXT:    neg a2, a4
+; RV32IZHINXMIN-NEXT:    or a0, a2, a0
+; RV32IZHINXMIN-NEXT:    feq.s a2, s0, s0
+; RV32IZHINXMIN-NEXT:    neg a2, a2
+; RV32IZHINXMIN-NEXT:    lui a5, 524288
+; RV32IZHINXMIN-NEXT:    lui a3, 524288
+; RV32IZHINXMIN-NEXT:    beqz s1, .LBB17_4
+; RV32IZHINXMIN-NEXT:  # %bb.3:
+; RV32IZHINXMIN-NEXT:    mv a3, a1
+; RV32IZHINXMIN-NEXT:  .LBB17_4:
+; RV32IZHINXMIN-NEXT:    and a0, a2, a0
+; RV32IZHINXMIN-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZHINXMIN-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
+; RV32IZHINXMIN-NEXT:    lw s1, 4(sp) # 4-byte Folded Reload
+; RV32IZHINXMIN-NEXT:    lw s2, 0(sp) # 4-byte Folded Reload
+; RV32IZHINXMIN-NEXT:    addi sp, sp, 16
+; RV32IZHINXMIN-NEXT:    beqz a4, .LBB17_6
+; RV32IZHINXMIN-NEXT:  # %bb.5:
+; RV32IZHINXMIN-NEXT:    addi a3, a5, -1
+; RV32IZHINXMIN-NEXT:  .LBB17_6:
+; RV32IZHINXMIN-NEXT:    and a1, a2, a3
+; RV32IZHINXMIN-NEXT:    ret
+;
+; RV64IZHINXMIN-LABEL: test_roundeven_si64:
+; RV64IZHINXMIN:       # %bb.0:
+; RV64IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV64IZHINXMIN-NEXT:    lui a1, 307200
+; RV64IZHINXMIN-NEXT:    fabs.s a2, a0
+; RV64IZHINXMIN-NEXT:    flt.s a1, a2, a1
+; RV64IZHINXMIN-NEXT:    beqz a1, .LBB17_2
+; RV64IZHINXMIN-NEXT:  # %bb.1:
+; RV64IZHINXMIN-NEXT:    fcvt.w.s a1, a0, rne
+; RV64IZHINXMIN-NEXT:    fcvt.s.w a1, a1, rne
+; RV64IZHINXMIN-NEXT:    fsgnj.s a0, a1, a0
+; RV64IZHINXMIN-NEXT:  .LBB17_2:
+; RV64IZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; RV64IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV64IZHINXMIN-NEXT:    fcvt.l.s a1, a0, rtz
+; RV64IZHINXMIN-NEXT:    feq.s a0, a0, a0
+; RV64IZHINXMIN-NEXT:    seqz a0, a0
+; RV64IZHINXMIN-NEXT:    addi a0, a0, -1
+; RV64IZHINXMIN-NEXT:    and a0, a0, a1
+; RV64IZHINXMIN-NEXT:    ret
   %a = call half @llvm.roundeven.f16(half %x)
   %b = call i64 @llvm.fptosi.sat.i64.f16(half %a)
   ret i64 %b
 }
 
 define signext i32 @test_roundeven_ui32(half %x) {
 ; CHECKIZFH-LABEL: test_roundeven_ui32:
 ; CHECKIZFH:       # %bb.0:
 ; CHECKIZFH-NEXT:    fcvt.wu.h a0, fa0, rne
 ; CHECKIZFH-NEXT:    feq.h a1, fa0, fa0
 ; CHECKIZFH-NEXT:    seqz a1, a1
 ; CHECKIZFH-NEXT:    addi a1, a1, -1
 ; CHECKIZFH-NEXT:    and a0, a1, a0
 ; CHECKIZFH-NEXT:    ret
 ;
+; RV32IZHINX-LABEL: test_roundeven_ui32:
+; RV32IZHINX:       # %bb.0:
+; RV32IZHINX-NEXT:    lui a1, %hi(.LCPI18_0)
+; RV32IZHINX-NEXT:    lh a1, %lo(.LCPI18_0)(a1)
+; RV32IZHINX-NEXT:    fabs.h a2, a0
+; RV32IZHINX-NEXT:    flt.h a1, a2, a1
+; RV32IZHINX-NEXT:    beqz a1, .LBB18_2
+; RV32IZHINX-NEXT:  # %bb.1:
+; RV32IZHINX-NEXT:    fcvt.w.h a1, a0, rne
+; RV32IZHINX-NEXT:    fcvt.h.w a1, a1, rne
+; RV32IZHINX-NEXT:    fsgnj.h a0, a1, a0
+; RV32IZHINX-NEXT:  .LBB18_2:
+; RV32IZHINX-NEXT:    fcvt.wu.h a1, a0, rtz
+; RV32IZHINX-NEXT:    feq.h a0, a0, a0
+; RV32IZHINX-NEXT:    seqz a0, a0
+; RV32IZHINX-NEXT:    addi a0, a0, -1
+; RV32IZHINX-NEXT:    and a0, a0, a1
+; RV32IZHINX-NEXT:    ret
+;
+; RV64IZHINX-LABEL: test_roundeven_ui32:
+; RV64IZHINX:       # %bb.0:
+; RV64IZHINX-NEXT:    lui a1, %hi(.LCPI18_0)
+; RV64IZHINX-NEXT:    lh a1, %lo(.LCPI18_0)(a1)
+; RV64IZHINX-NEXT:    fabs.h a2, a0
+; RV64IZHINX-NEXT:    flt.h a1, a2, a1
+; RV64IZHINX-NEXT:    beqz a1, .LBB18_2
+; RV64IZHINX-NEXT:  # %bb.1:
+; RV64IZHINX-NEXT:    fcvt.w.h a1, a0, rne
+; RV64IZHINX-NEXT:    fcvt.h.w a1, a1, rne
+; RV64IZHINX-NEXT:    fsgnj.h a0, a1, a0
+; RV64IZHINX-NEXT:  .LBB18_2:
+; RV64IZHINX-NEXT:    fcvt.wu.h a1, a0, rtz
+; RV64IZHINX-NEXT:    feq.h a0, a0, a0
+; RV64IZHINX-NEXT:    seqz a0, a0
+; RV64IZHINX-NEXT:    addi a0, a0, -1
+; RV64IZHINX-NEXT:    and a0, a1, a0
+; RV64IZHINX-NEXT:    ret
+;
 ; RV32IZFHMIN-LABEL: test_roundeven_ui32:
 ; RV32IZFHMIN:       # %bb.0:
 ; RV32IZFHMIN-NEXT:    fcvt.s.h fa5, fa0
 ; RV32IZFHMIN-NEXT:    lui a0, 307200
 ; RV32IZFHMIN-NEXT:    fmv.w.x fa4, a0
 ; RV32IZFHMIN-NEXT:    fabs.s fa3, fa5
 ; RV32IZFHMIN-NEXT:    flt.s a0, fa3, fa4
 ; RV32IZFHMIN-NEXT:    beqz a0, .LBB18_2

 ; RV64IZFHMIN-NEXT:    fcvt.h.s fa5, fa5
 ; RV64IZFHMIN-NEXT:    fcvt.s.h fa5, fa5
 ; RV64IZFHMIN-NEXT:    fcvt.wu.s a0, fa5, rtz
 ; RV64IZFHMIN-NEXT:    feq.s a1, fa5, fa5
 ; RV64IZFHMIN-NEXT:    seqz a1, a1
 ; RV64IZFHMIN-NEXT:    addi a1, a1, -1
 ; RV64IZFHMIN-NEXT:    and a0, a0, a1
 ; RV64IZFHMIN-NEXT:    ret
+;
+; RV32IZHINXMIN-LABEL: test_roundeven_ui32:
+; RV32IZHINXMIN:       # %bb.0:
+; RV32IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV32IZHINXMIN-NEXT:    lui a1, 307200
+; RV32IZHINXMIN-NEXT:    fabs.s a2, a0
+; RV32IZHINXMIN-NEXT:    flt.s a1, a2, a1
+; RV32IZHINXMIN-NEXT:    beqz a1, .LBB18_2
+; RV32IZHINXMIN-NEXT:  # %bb.1:
+; RV32IZHINXMIN-NEXT:    fcvt.w.s a1, a0, rne
+; RV32IZHINXMIN-NEXT:    fcvt.s.w a1, a1, rne
+; RV32IZHINXMIN-NEXT:    fsgnj.s a0, a1, a0
+; RV32IZHINXMIN-NEXT:  .LBB18_2:
+; RV32IZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; RV32IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV32IZHINXMIN-NEXT:    fcvt.wu.s a1, a0, rtz
+; RV32IZHINXMIN-NEXT:    feq.s a0, a0, a0
+; RV32IZHINXMIN-NEXT:    seqz a0, a0
+; RV32IZHINXMIN-NEXT:    addi a0, a0, -1
+; RV32IZHINXMIN-NEXT:    and a0, a0, a1
+; RV32IZHINXMIN-NEXT:    ret
+;
+; RV64IZHINXMIN-LABEL: test_roundeven_ui32:
+; RV64IZHINXMIN:       # %bb.0:
+; RV64IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV64IZHINXMIN-NEXT:    lui a1, 307200
+; RV64IZHINXMIN-NEXT:    fabs.s a2, a0
+; RV64IZHINXMIN-NEXT:    flt.s a1, a2, a1
+; RV64IZHINXMIN-NEXT:    beqz a1, .LBB18_2
+; RV64IZHINXMIN-NEXT:  # %bb.1:
+; RV64IZHINXMIN-NEXT:    fcvt.w.s a1, a0, rne
+; RV64IZHINXMIN-NEXT:    fcvt.s.w a1, a1, rne
+; RV64IZHINXMIN-NEXT:    fsgnj.s a0, a1, a0
+; RV64IZHINXMIN-NEXT:  .LBB18_2:
+; RV64IZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; RV64IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV64IZHINXMIN-NEXT:    fcvt.wu.s a1, a0, rtz
+; RV64IZHINXMIN-NEXT:    feq.s a0, a0, a0
+; RV64IZHINXMIN-NEXT:    seqz a0, a0
+; RV64IZHINXMIN-NEXT:    addi a0, a0, -1
+; RV64IZHINXMIN-NEXT:    and a0, a1, a0
+; RV64IZHINXMIN-NEXT:    ret
   %a = call half @llvm.roundeven.f16(half %x)
   %b = call i32 @llvm.fptoui.sat.i32.f16(half %a)
   ret i32 %b
 }
 
 define i64 @test_roundeven_ui64(half %x) nounwind {
 ; RV32IZFH-LABEL: test_roundeven_ui64:
 ; RV32IZFH:       # %bb.0:

 ; RV64IZFH:       # %bb.0:
 ; RV64IZFH-NEXT:    fcvt.lu.h a0, fa0, rne
 ; RV64IZFH-NEXT:    feq.h a1, fa0, fa0
 ; RV64IZFH-NEXT:    seqz a1, a1
 ; RV64IZFH-NEXT:    addi a1, a1, -1
 ; RV64IZFH-NEXT:    and a0, a1, a0
 ; RV64IZFH-NEXT:    ret
 ;
+; RV32IZHINX-LABEL: test_roundeven_ui64:
+; RV32IZHINX:       # %bb.0:
+; RV32IZHINX-NEXT:    addi sp, sp, -16
+; RV32IZHINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZHINX-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
+; RV32IZHINX-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
+; RV32IZHINX-NEXT:    lui a1, %hi(.LCPI19_0)
+; RV32IZHINX-NEXT:    lh a1, %lo(.LCPI19_0)(a1)
+; RV32IZHINX-NEXT:    fabs.h a2, a0
+; RV32IZHINX-NEXT:    flt.h a1, a2, a1
+; RV32IZHINX-NEXT:    beqz a1, .LBB19_2
+; RV32IZHINX-NEXT:  # %bb.1:
+; RV32IZHINX-NEXT:    fcvt.w.h a1, a0, rne
+; RV32IZHINX-NEXT:    fcvt.h.w a1, a1, rne
+; RV32IZHINX-NEXT:    fsgnj.h a0, a1, a0
+; RV32IZHINX-NEXT:  .LBB19_2:
+; RV32IZHINX-NEXT:    fcvt.s.h s0, a0
+; RV32IZHINX-NEXT:    fle.s a0, zero, s0
+; RV32IZHINX-NEXT:    neg s1, a0
+; RV32IZHINX-NEXT:    mv a0, s0
+; RV32IZHINX-NEXT:    call __fixunssfdi@plt
+; RV32IZHINX-NEXT:    lui a2, %hi(.LCPI19_1)
+; RV32IZHINX-NEXT:    lw a2, %lo(.LCPI19_1)(a2)
+; RV32IZHINX-NEXT:    and a0, s1, a0
+; RV32IZHINX-NEXT:    flt.s a2, a2, s0
+; RV32IZHINX-NEXT:    neg a2, a2
+; RV32IZHINX-NEXT:    or a0, a2, a0
+; RV32IZHINX-NEXT:    and a1, s1, a1
+; RV32IZHINX-NEXT:    or a1, a2, a1
+; RV32IZHINX-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZHINX-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
+; RV32IZHINX-NEXT:    lw s1, 4(sp) # 4-byte Folded Reload
+; RV32IZHINX-NEXT:    addi sp, sp, 16
+; RV32IZHINX-NEXT:    ret
+;
+; RV64IZHINX-LABEL: test_roundeven_ui64:
+; RV64IZHINX:       # %bb.0:
+; RV64IZHINX-NEXT:    lui a1, %hi(.LCPI19_0)
+; RV64IZHINX-NEXT:    lh a1, %lo(.LCPI19_0)(a1)
+; RV64IZHINX-NEXT:    fabs.h a2, a0
+; RV64IZHINX-NEXT:    flt.h a1, a2, a1
+; RV64IZHINX-NEXT:    beqz a1, .LBB19_2
+; RV64IZHINX-NEXT:  # %bb.1:
+; RV64IZHINX-NEXT:    fcvt.w.h a1, a0, rne
+; RV64IZHINX-NEXT:    fcvt.h.w a1, a1, rne
+; RV64IZHINX-NEXT:    fsgnj.h a0, a1, a0
+; RV64IZHINX-NEXT:  .LBB19_2:
+; RV64IZHINX-NEXT:    fcvt.lu.h a1, a0, rtz
+; RV64IZHINX-NEXT:    feq.h a0, a0, a0
+; RV64IZHINX-NEXT:    seqz a0, a0
+; RV64IZHINX-NEXT:    addi a0, a0, -1
+; RV64IZHINX-NEXT:    and a0, a0, a1
+; RV64IZHINX-NEXT:    ret
+;
 ; RV32IZFHMIN-LABEL: test_roundeven_ui64:
 ; RV32IZFHMIN:       # %bb.0:
 ; RV32IZFHMIN-NEXT:    fcvt.s.h fa5, fa0
 ; RV32IZFHMIN-NEXT:    lui a0, 307200
 ; RV32IZFHMIN-NEXT:    fmv.w.x fa4, a0
 ; RV32IZFHMIN-NEXT:    fabs.s fa3, fa5
 ; RV32IZFHMIN-NEXT:    flt.s a0, fa3, fa4
 ; RV32IZFHMIN-NEXT:    beqz a0, .LBB19_2

 ; RV64IZFHMIN-NEXT:    fcvt.h.s fa5, fa5
 ; RV64IZFHMIN-NEXT:    fcvt.s.h fa5, fa5
 ; RV64IZFHMIN-NEXT:    fcvt.lu.s a0, fa5, rtz
 ; RV64IZFHMIN-NEXT:    feq.s a1, fa5, fa5
 ; RV64IZFHMIN-NEXT:    seqz a1, a1
 ; RV64IZFHMIN-NEXT:    addi a1, a1, -1
 ; RV64IZFHMIN-NEXT:    and a0, a1, a0
 ; RV64IZFHMIN-NEXT:    ret
+;
+; RV32IZHINXMIN-LABEL: test_roundeven_ui64:
+; RV32IZHINXMIN:       # %bb.0:
+; RV32IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV32IZHINXMIN-NEXT:    lui a1, 307200
+; RV32IZHINXMIN-NEXT:    fabs.s a2, a0
+; RV32IZHINXMIN-NEXT:    flt.s a1, a2, a1
+; RV32IZHINXMIN-NEXT:    beqz a1, .LBB19_2
+; RV32IZHINXMIN-NEXT:  # %bb.1:
+; RV32IZHINXMIN-NEXT:    fcvt.w.s a1, a0, rne
+; RV32IZHINXMIN-NEXT:    fcvt.s.w a1, a1, rne
+; RV32IZHINXMIN-NEXT:    fsgnj.s a0, a1, a0
+; RV32IZHINXMIN-NEXT:  .LBB19_2:
+; RV32IZHINXMIN-NEXT:    addi sp, sp, -16
+; RV32IZHINXMIN-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZHINXMIN-NEXT:    sw s0, 8(sp) # 4-byte Folded Spill
+; RV32IZHINXMIN-NEXT:    sw s1, 4(sp) # 4-byte Folded Spill
+; RV32IZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; RV32IZHINXMIN-NEXT:    fcvt.s.h s0, a0
+; RV32IZHINXMIN-NEXT:    fle.s a0, zero, s0
+; RV32IZHINXMIN-NEXT:    neg s1, a0
+; RV32IZHINXMIN-NEXT:    mv a0, s0
+; RV32IZHINXMIN-NEXT:    call __fixunssfdi@plt
+; RV32IZHINXMIN-NEXT:    lui a2, %hi(.LCPI19_0)
+; RV32IZHINXMIN-NEXT:    lw a2, %lo(.LCPI19_0)(a2)
+; RV32IZHINXMIN-NEXT:    and a0, s1, a0
+; RV32IZHINXMIN-NEXT:    flt.s a2, a2, s0
+; RV32IZHINXMIN-NEXT:    neg a2, a2
+; RV32IZHINXMIN-NEXT:    or a0, a2, a0
+; RV32IZHINXMIN-NEXT:    and a1, s1, a1
+; RV32IZHINXMIN-NEXT:    or a1, a2, a1
+; RV32IZHINXMIN-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZHINXMIN-NEXT:    lw s0, 8(sp) # 4-byte Folded Reload
+; RV32IZHINXMIN-NEXT:    lw s1, 4(sp) # 4-byte Folded Reload
+; RV32IZHINXMIN-NEXT:    addi sp, sp, 16
+; RV32IZHINXMIN-NEXT:    ret
+;
+; RV64IZHINXMIN-LABEL: test_roundeven_ui64:
+; RV64IZHINXMIN:       # %bb.0:
+; RV64IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV64IZHINXMIN-NEXT:    lui a1, 307200
+; RV64IZHINXMIN-NEXT:    fabs.s a2, a0
+; RV64IZHINXMIN-NEXT:    flt.s a1, a2, a1
+; RV64IZHINXMIN-NEXT:    beqz a1, .LBB19_2
+; RV64IZHINXMIN-NEXT:  # %bb.1:
+; RV64IZHINXMIN-NEXT:    fcvt.w.s a1, a0, rne
+; RV64IZHINXMIN-NEXT:    fcvt.s.w a1, a1, rne
+; RV64IZHINXMIN-NEXT:    fsgnj.s a0, a1, a0
+; RV64IZHINXMIN-NEXT:  .LBB19_2:
+; RV64IZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; RV64IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV64IZHINXMIN-NEXT:    fcvt.lu.s a1, a0, rtz
+; RV64IZHINXMIN-NEXT:    feq.s a0, a0, a0
+; RV64IZHINXMIN-NEXT:    seqz a0, a0
+; RV64IZHINXMIN-NEXT:    addi a0, a0, -1
+; RV64IZHINXMIN-NEXT:    and a0, a0, a1
+; RV64IZHINXMIN-NEXT:    ret
   %a = call half @llvm.roundeven.f16(half %x)
   %b = call i64 @llvm.fptoui.sat.i64.f16(half %a)
   ret i64 %b
 }
 
 declare half @llvm.floor.f16(half)
 declare half @llvm.ceil.f16(half)
 declare half @llvm.trunc.f16(half)
 declare half @llvm.round.f16(half)
 declare half @llvm.roundeven.f16(half)
 declare i32 @llvm.fptosi.sat.i32.f16(half)
 declare i64 @llvm.fptosi.sat.i64.f16(half)
 declare i32 @llvm.fptoui.sat.i32.f16(half)
 declare i64 @llvm.fptoui.sat.i64.f16(half)

llvm/test/CodeGen/RISCV/half-round-conv.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -mattr=+zfh -verify-machineinstrs < %s \
 ; RUN:   -target-abi=ilp32f | FileCheck -check-prefixes=CHECKIZFH,RV32IZFH %s
 ; RUN: llc -mtriple=riscv64 -mattr=+zfh -verify-machineinstrs < %s \
 ; RUN:   -target-abi=lp64f | FileCheck -check-prefixes=CHECKIZFH,RV64IZFH %s
+; RUN: llc -mtriple=riscv32 -mattr=+zhinx -verify-machineinstrs < %s \
+; RUN:   -target-abi=ilp32 | FileCheck -check-prefixes=CHECKIZHINX,RV32IZHINX %s
+; RUN: llc -mtriple=riscv64 -mattr=+zhinx -verify-machineinstrs < %s \
+; RUN:   -target-abi=lp64 | FileCheck -check-prefixes=CHECKIZHINX,RV64IZHINX %s
 ; RUN: llc -mtriple=riscv32 -mattr=+zfhmin -verify-machineinstrs < %s \
 ; RUN:   -target-abi=ilp32f | FileCheck -check-prefixes=CHECKIZFHMIN,RV32IZFHMIN %s
 ; RUN: llc -mtriple=riscv64 -mattr=+zfhmin -verify-machineinstrs < %s \
 ; RUN:   -target-abi=lp64f | FileCheck -check-prefixes=CHECKIZFHMIN,RV64IZFHMIN %s
+; RUN: llc -mtriple=riscv32 -mattr=+zhinxmin -verify-machineinstrs < %s \
+; RUN:   -target-abi=ilp32 | FileCheck -check-prefixes=CHECKIZHINXMIN,RV32IZHINXMIN %s
+; RUN: llc -mtriple=riscv64 -mattr=+zhinxmin -verify-machineinstrs < %s \
+; RUN:   -target-abi=lp64 | FileCheck -check-prefixes=CHECKIZHINXMIN,RV64IZHINXMIN %s
 
 define signext i8 @test_floor_si8(half %x) {
 ; RV32IZFH-LABEL: test_floor_si8:
 ; RV32IZFH:       # %bb.0:
 ; RV32IZFH-NEXT:    fcvt.w.h a0, fa0, rdn
 ; RV32IZFH-NEXT:    ret
 ;
 ; RV64IZFH-LABEL: test_floor_si8:
 ; RV64IZFH:       # %bb.0:
 ; RV64IZFH-NEXT:    fcvt.l.h a0, fa0, rdn
 ; RV64IZFH-NEXT:    ret
 ;
+; RV32IZHINX-LABEL: test_floor_si8:
+; RV32IZHINX:       # %bb.0:
+; RV32IZHINX-NEXT:    lui a1, %hi(.LCPI0_0)
+; RV32IZHINX-NEXT:    lh a1, %lo(.LCPI0_0)(a1)
+; RV32IZHINX-NEXT:    fabs.h a2, a0
+; RV32IZHINX-NEXT:    flt.h a1, a2, a1
+; RV32IZHINX-NEXT:    beqz a1, .LBB0_2
+; RV32IZHINX-NEXT:  # %bb.1:
+; RV32IZHINX-NEXT:    fcvt.w.h a1, a0, rdn
+; RV32IZHINX-NEXT:    fcvt.h.w a1, a1, rdn
+; RV32IZHINX-NEXT:    fsgnj.h a0, a1, a0
+; RV32IZHINX-NEXT:  .LBB0_2:
+; RV32IZHINX-NEXT:    fcvt.w.h a0, a0, rtz
+; RV32IZHINX-NEXT:    ret
+;
+; RV64IZHINX-LABEL: test_floor_si8:
+; RV64IZHINX:       # %bb.0:
+; RV64IZHINX-NEXT:    lui a1, %hi(.LCPI0_0)
+; RV64IZHINX-NEXT:    lh a1, %lo(.LCPI0_0)(a1)
+; RV64IZHINX-NEXT:    fabs.h a2, a0
+; RV64IZHINX-NEXT:    flt.h a1, a2, a1
+; RV64IZHINX-NEXT:    beqz a1, .LBB0_2
+; RV64IZHINX-NEXT:  # %bb.1:
+; RV64IZHINX-NEXT:    fcvt.w.h a1, a0, rdn
+; RV64IZHINX-NEXT:    fcvt.h.w a1, a1, rdn
+; RV64IZHINX-NEXT:    fsgnj.h a0, a1, a0
+; RV64IZHINX-NEXT:  .LBB0_2:
+; RV64IZHINX-NEXT:    fcvt.l.h a0, a0, rtz
+; RV64IZHINX-NEXT:    ret
+;
 ; RV32IZFHMIN-LABEL: test_floor_si8:
 ; RV32IZFHMIN:       # %bb.0:
 ; RV32IZFHMIN-NEXT:    fcvt.s.h fa5, fa0
 ; RV32IZFHMIN-NEXT:    lui a0, 307200
 ; RV32IZFHMIN-NEXT:    fmv.w.x fa4, a0
 ; RV32IZFHMIN-NEXT:    fabs.s fa3, fa5
 ; RV32IZFHMIN-NEXT:    flt.s a0, fa3, fa4
 ; RV32IZFHMIN-NEXT:    beqz a0, .LBB0_2

 ; RV64IZFHMIN-NEXT:    fcvt.w.s a0, fa5, rdn
 ; RV64IZFHMIN-NEXT:    fcvt.s.w fa4, a0, rdn
 ; RV64IZFHMIN-NEXT:    fsgnj.s fa5, fa4, fa5
 ; RV64IZFHMIN-NEXT:  .LBB0_2:
 ; RV64IZFHMIN-NEXT:    fcvt.h.s fa5, fa5
 ; RV64IZFHMIN-NEXT:    fcvt.s.h fa5, fa5
 ; RV64IZFHMIN-NEXT:    fcvt.l.s a0, fa5, rtz
 ; RV64IZFHMIN-NEXT:    ret
+;
+; RV32IZHINXMIN-LABEL: test_floor_si8:
+; RV32IZHINXMIN:       # %bb.0:
+; RV32IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV32IZHINXMIN-NEXT:    lui a1, 307200
+; RV32IZHINXMIN-NEXT:    fabs.s a2, a0
+; RV32IZHINXMIN-NEXT:    flt.s a1, a2, a1
+; RV32IZHINXMIN-NEXT:    beqz a1, .LBB0_2
+; RV32IZHINXMIN-NEXT:  # %bb.1:
+; RV32IZHINXMIN-NEXT:    fcvt.w.s a1, a0, rdn
+; RV32IZHINXMIN-NEXT:    fcvt.s.w a1, a1, rdn
+; RV32IZHINXMIN-NEXT:    fsgnj.s a0, a1, a0
+; RV32IZHINXMIN-NEXT:  .LBB0_2:
+; RV32IZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; RV32IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV32IZHINXMIN-NEXT:    fcvt.w.s a0, a0, rtz
+; RV32IZHINXMIN-NEXT:    ret
+;
+; RV64IZHINXMIN-LABEL: test_floor_si8:
+; RV64IZHINXMIN:       # %bb.0:
+; RV64IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV64IZHINXMIN-NEXT:    lui a1, 307200
+; RV64IZHINXMIN-NEXT:    fabs.s a2, a0
+; RV64IZHINXMIN-NEXT:    flt.s a1, a2, a1
+; RV64IZHINXMIN-NEXT:    beqz a1, .LBB0_2
+; RV64IZHINXMIN-NEXT:  # %bb.1:
+; RV64IZHINXMIN-NEXT:    fcvt.w.s a1, a0, rdn
+; RV64IZHINXMIN-NEXT:    fcvt.s.w a1, a1, rdn
+; RV64IZHINXMIN-NEXT:    fsgnj.s a0, a1, a0
+; RV64IZHINXMIN-NEXT:  .LBB0_2:
+; RV64IZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; RV64IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV64IZHINXMIN-NEXT:    fcvt.l.s a0, a0, rtz
+; RV64IZHINXMIN-NEXT:    ret
   %a = call half @llvm.floor.f16(half %x)
   %b = fptosi half %a to i8
   ret i8 %b
 }
 
 define signext i16 @test_floor_si16(half %x) {
 ; RV32IZFH-LABEL: test_floor_si16:
 ; RV32IZFH:       # %bb.0:
 ; RV32IZFH-NEXT:    fcvt.w.h a0, fa0, rdn
 ; RV32IZFH-NEXT:    ret
 ;
 ; RV64IZFH-LABEL: test_floor_si16:
 ; RV64IZFH:       # %bb.0:
 ; RV64IZFH-NEXT:    fcvt.l.h a0, fa0, rdn
 ; RV64IZFH-NEXT:    ret
 ;
+; RV32IZHINX-LABEL: test_floor_si16:
+; RV32IZHINX:       # %bb.0:
+; RV32IZHINX-NEXT:    lui a1, %hi(.LCPI1_0)
+; RV32IZHINX-NEXT:    lh a1, %lo(.LCPI1_0)(a1)
+; RV32IZHINX-NEXT:    fabs.h a2, a0
+; RV32IZHINX-NEXT:    flt.h a1, a2, a1
+; RV32IZHINX-NEXT:    beqz a1, .LBB1_2
+; RV32IZHINX-NEXT:  # %bb.1:
+; RV32IZHINX-NEXT:    fcvt.w.h a1, a0, rdn
+; RV32IZHINX-NEXT:    fcvt.h.w a1, a1, rdn
+; RV32IZHINX-NEXT:    fsgnj.h a0, a1, a0
+; RV32IZHINX-NEXT:  .LBB1_2:
+; RV32IZHINX-NEXT:    fcvt.w.h a0, a0, rtz
+; RV32IZHINX-NEXT:    ret
+;
+; RV64IZHINX-LABEL: test_floor_si16:
+; RV64IZHINX:       # %bb.0:
+; RV64IZHINX-NEXT:    lui a1, %hi(.LCPI1_0)
+; RV64IZHINX-NEXT:    lh a1, %lo(.LCPI1_0)(a1)
+; RV64IZHINX-NEXT:    fabs.h a2, a0
+; RV64IZHINX-NEXT:    flt.h a1, a2, a1
+; RV64IZHINX-NEXT:    beqz a1, .LBB1_2
+; RV64IZHINX-NEXT:  # %bb.1:
+; RV64IZHINX-NEXT:    fcvt.w.h a1, a0, rdn
+; RV64IZHINX-NEXT:    fcvt.h.w a1, a1, rdn
+; RV64IZHINX-NEXT:    fsgnj.h a0, a1, a0
+; RV64IZHINX-NEXT:  .LBB1_2:
+; RV64IZHINX-NEXT:    fcvt.l.h a0, a0, rtz
+; RV64IZHINX-NEXT:    ret
+;
 ; RV32IZFHMIN-LABEL: test_floor_si16:
 ; RV32IZFHMIN:       # %bb.0:
 ; RV32IZFHMIN-NEXT:    fcvt.s.h fa5, fa0
 ; RV32IZFHMIN-NEXT:    lui a0, 307200
 ; RV32IZFHMIN-NEXT:    fmv.w.x fa4, a0
 ; RV32IZFHMIN-NEXT:    fabs.s fa3, fa5
 ; RV32IZFHMIN-NEXT:    flt.s a0, fa3, fa4
 ; RV32IZFHMIN-NEXT:    beqz a0, .LBB1_2

 ; RV64IZFHMIN-NEXT:    fcvt.w.s a0, fa5, rdn
 ; RV64IZFHMIN-NEXT:    fcvt.s.w fa4, a0, rdn
 ; RV64IZFHMIN-NEXT:    fsgnj.s fa5, fa4, fa5
 ; RV64IZFHMIN-NEXT:  .LBB1_2:
 ; RV64IZFHMIN-NEXT:    fcvt.h.s fa5, fa5
 ; RV64IZFHMIN-NEXT:    fcvt.s.h fa5, fa5
 ; RV64IZFHMIN-NEXT:    fcvt.l.s a0, fa5, rtz
 ; RV64IZFHMIN-NEXT:    ret
+;
+; RV32IZHINXMIN-LABEL: test_floor_si16:
+; RV32IZHINXMIN:       # %bb.0:
+; RV32IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV32IZHINXMIN-NEXT:    lui a1, 307200
+; RV32IZHINXMIN-NEXT:    fabs.s a2, a0
+; RV32IZHINXMIN-NEXT:    flt.s a1, a2, a1
+; RV32IZHINXMIN-NEXT:    beqz a1, .LBB1_2
+; RV32IZHINXMIN-NEXT:  # %bb.1:
+; RV32IZHINXMIN-NEXT:    fcvt.w.s a1, a0, rdn
+; RV32IZHINXMIN-NEXT:    fcvt.s.w a1, a1, rdn
+; RV32IZHINXMIN-NEXT:    fsgnj.s a0, a1, a0
+; RV32IZHINXMIN-NEXT:  .LBB1_2:
+; RV32IZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; RV32IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV32IZHINXMIN-NEXT:    fcvt.w.s a0, a0, rtz
+; RV32IZHINXMIN-NEXT:    ret
+;
+; RV64IZHINXMIN-LABEL: test_floor_si16:
+; RV64IZHINXMIN:       # %bb.0:
+; RV64IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV64IZHINXMIN-NEXT:    lui a1, 307200
+; RV64IZHINXMIN-NEXT:    fabs.s a2, a0
+; RV64IZHINXMIN-NEXT:    flt.s a1, a2, a1
+; RV64IZHINXMIN-NEXT:    beqz a1, .LBB1_2
+; RV64IZHINXMIN-NEXT:  # %bb.1:
+; RV64IZHINXMIN-NEXT:    fcvt.w.s a1, a0, rdn
+; RV64IZHINXMIN-NEXT:    fcvt.s.w a1, a1, rdn
+; RV64IZHINXMIN-NEXT:    fsgnj.s a0, a1, a0
+; RV64IZHINXMIN-NEXT:  .LBB1_2:
+; RV64IZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; RV64IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV64IZHINXMIN-NEXT:    fcvt.l.s a0, a0, rtz
+; RV64IZHINXMIN-NEXT:    ret
   %a = call half @llvm.floor.f16(half %x)
   %b = fptosi half %a to i16
   ret i16 %b
 }
 
 define signext i32 @test_floor_si32(half %x) {
 ; CHECKIZFH-LABEL: test_floor_si32:
 ; CHECKIZFH:       # %bb.0:
 ; CHECKIZFH-NEXT:    fcvt.w.h a0, fa0, rdn
 ; CHECKIZFH-NEXT:    ret
 ;
+; CHECKIZHINX-LABEL: test_floor_si32:
+; CHECKIZHINX:       # %bb.0:
+; CHECKIZHINX-NEXT:    lui a1, %hi(.LCPI2_0)
+; CHECKIZHINX-NEXT:    lh a1, %lo(.LCPI2_0)(a1)
+; CHECKIZHINX-NEXT:    fabs.h a2, a0
+; CHECKIZHINX-NEXT:    flt.h a1, a2, a1
+; CHECKIZHINX-NEXT:    beqz a1, .LBB2_2
+; CHECKIZHINX-NEXT:  # %bb.1:
+; CHECKIZHINX-NEXT:    fcvt.w.h a1, a0, rdn
+; CHECKIZHINX-NEXT:    fcvt.h.w a1, a1, rdn
+; CHECKIZHINX-NEXT:    fsgnj.h a0, a1, a0
+; CHECKIZHINX-NEXT:  .LBB2_2:
+; CHECKIZHINX-NEXT:    fcvt.w.h a0, a0, rtz
+; CHECKIZHINX-NEXT:    ret
+;
 ; CHECKIZFHMIN-LABEL: test_floor_si32:
 ; CHECKIZFHMIN:       # %bb.0:
 ; CHECKIZFHMIN-NEXT:    fcvt.s.h fa5, fa0
 ; CHECKIZFHMIN-NEXT:    lui a0, 307200
 ; CHECKIZFHMIN-NEXT:    fmv.w.x fa4, a0
 ; CHECKIZFHMIN-NEXT:    fabs.s fa3, fa5
 ; CHECKIZFHMIN-NEXT:    flt.s a0, fa3, fa4
 ; CHECKIZFHMIN-NEXT:    beqz a0, .LBB2_2
 ; CHECKIZFHMIN-NEXT:  # %bb.1:
 ; CHECKIZFHMIN-NEXT:    fcvt.w.s a0, fa5, rdn
 ; CHECKIZFHMIN-NEXT:    fcvt.s.w fa4, a0, rdn
 ; CHECKIZFHMIN-NEXT:    fsgnj.s fa5, fa4, fa5
 ; CHECKIZFHMIN-NEXT:  .LBB2_2:
 ; CHECKIZFHMIN-NEXT:    fcvt.h.s fa5, fa5
 ; CHECKIZFHMIN-NEXT:    fcvt.s.h fa5, fa5
 ; CHECKIZFHMIN-NEXT:    fcvt.w.s a0, fa5, rtz
 ; CHECKIZFHMIN-NEXT:    ret
+;
+; CHECKIZHINXMIN-LABEL: test_floor_si32:
+; CHECKIZHINXMIN:       # %bb.0:
+; CHECKIZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECKIZHINXMIN-NEXT:    lui a1, 307200
+; CHECKIZHINXMIN-NEXT:    fabs.s a2, a0
+; CHECKIZHINXMIN-NEXT:    flt.s a1, a2, a1
+; CHECKIZHINXMIN-NEXT:    beqz a1, .LBB2_2
+; CHECKIZHINXMIN-NEXT:  # %bb.1:
+; CHECKIZHINXMIN-NEXT:    fcvt.w.s a1, a0, rdn
+; CHECKIZHINXMIN-NEXT:    fcvt.s.w a1, a1, rdn
+; CHECKIZHINXMIN-NEXT:    fsgnj.s a0, a1, a0
+; CHECKIZHINXMIN-NEXT:  .LBB2_2:
+; CHECKIZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; CHECKIZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECKIZHINXMIN-NEXT:    fcvt.w.s a0, a0, rtz
+; CHECKIZHINXMIN-NEXT:    ret
   %a = call half @llvm.floor.f16(half %x)
   %b = fptosi half %a to i32
   ret i32 %b
 }
 
 define i64 @test_floor_si64(half %x) {
 ; RV32IZFH-LABEL: test_floor_si64:
 ; RV32IZFH:       # %bb.0:

 ; RV32IZFH-NEXT:    addi sp, sp, 16
 ; RV32IZFH-NEXT:    ret
 ;
 ; RV64IZFH-LABEL: test_floor_si64:
 ; RV64IZFH:       # %bb.0:
 ; RV64IZFH-NEXT:    fcvt.l.h a0, fa0, rdn
 ; RV64IZFH-NEXT:    ret
 ;
+; RV32IZHINX-LABEL: test_floor_si64:
+; RV32IZHINX:       # %bb.0:
+; RV32IZHINX-NEXT:    addi sp, sp, -16
+; RV32IZHINX-NEXT:    .cfi_def_cfa_offset 16
+; RV32IZHINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZHINX-NEXT:    .cfi_offset ra, -4
+; RV32IZHINX-NEXT:    lui a1, %hi(.LCPI3_0)
+; RV32IZHINX-NEXT:    lh a1, %lo(.LCPI3_0)(a1)
+; RV32IZHINX-NEXT:    fabs.h a2, a0
+; RV32IZHINX-NEXT:    flt.h a1, a2, a1
+; RV32IZHINX-NEXT:    beqz a1, .LBB3_2
+; RV32IZHINX-NEXT:  # %bb.1:
+; RV32IZHINX-NEXT:    fcvt.w.h a1, a0, rdn
+; RV32IZHINX-NEXT:    fcvt.h.w a1, a1, rdn
+; RV32IZHINX-NEXT:    fsgnj.h a0, a1, a0
+; RV32IZHINX-NEXT:  .LBB3_2:
+; RV32IZHINX-NEXT:    call __fixhfdi@plt
+; RV32IZHINX-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZHINX-NEXT:    addi sp, sp, 16
+; RV32IZHINX-NEXT:    ret
+;
+; RV64IZHINX-LABEL: test_floor_si64:
+; RV64IZHINX:       # %bb.0:
+; RV64IZHINX-NEXT:    lui a1, %hi(.LCPI3_0)
+; RV64IZHINX-NEXT:    lh a1, %lo(.LCPI3_0)(a1)
+; RV64IZHINX-NEXT:    fabs.h a2, a0
+; RV64IZHINX-NEXT:    flt.h a1, a2, a1
+; RV64IZHINX-NEXT:    beqz a1, .LBB3_2
+; RV64IZHINX-NEXT:  # %bb.1:
+; RV64IZHINX-NEXT:    fcvt.w.h a1, a0, rdn
+; RV64IZHINX-NEXT:    fcvt.h.w a1, a1, rdn
+; RV64IZHINX-NEXT:    fsgnj.h a0, a1, a0
+; RV64IZHINX-NEXT:  .LBB3_2:
+; RV64IZHINX-NEXT:    fcvt.l.h a0, a0, rtz
+; RV64IZHINX-NEXT:    ret
+;
 ; RV32IZFHMIN-LABEL: test_floor_si64:
 ; RV32IZFHMIN:       # %bb.0:
 ; RV32IZFHMIN-NEXT:    fcvt.s.h fa5, fa0
 ; RV32IZFHMIN-NEXT:    lui a0, 307200
 ; RV32IZFHMIN-NEXT:    fmv.w.x fa4, a0
 ; RV32IZFHMIN-NEXT:    fabs.s fa3, fa5
 ; RV32IZFHMIN-NEXT:    flt.s a0, fa3, fa4
 ; RV32IZFHMIN-NEXT:    beqz a0, .LBB3_2

 ; RV64IZFHMIN-NEXT:    fcvt.w.s a0, fa5, rdn
 ; RV64IZFHMIN-NEXT:    fcvt.s.w fa4, a0, rdn
 ; RV64IZFHMIN-NEXT:    fsgnj.s fa5, fa4, fa5
 ; RV64IZFHMIN-NEXT:  .LBB3_2:
 ; RV64IZFHMIN-NEXT:    fcvt.h.s fa5, fa5
 ; RV64IZFHMIN-NEXT:    fcvt.s.h fa5, fa5
 ; RV64IZFHMIN-NEXT:    fcvt.l.s a0, fa5, rtz
 ; RV64IZFHMIN-NEXT:    ret
+;
+; RV32IZHINXMIN-LABEL: test_floor_si64:
+; RV32IZHINXMIN:       # %bb.0:
+; RV32IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV32IZHINXMIN-NEXT:    lui a1, 307200
+; RV32IZHINXMIN-NEXT:    fabs.s a2, a0
+; RV32IZHINXMIN-NEXT:    flt.s a1, a2, a1
+; RV32IZHINXMIN-NEXT:    beqz a1, .LBB3_2
+; RV32IZHINXMIN-NEXT:  # %bb.1:
+; RV32IZHINXMIN-NEXT:    fcvt.w.s a1, a0, rdn
+; RV32IZHINXMIN-NEXT:    fcvt.s.w a1, a1, rdn
+; RV32IZHINXMIN-NEXT:    fsgnj.s a0, a1, a0
+; RV32IZHINXMIN-NEXT:  .LBB3_2:
+; RV32IZHINXMIN-NEXT:    addi sp, sp, -16
+; RV32IZHINXMIN-NEXT:    .cfi_def_cfa_offset 16
+; RV32IZHINXMIN-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZHINXMIN-NEXT:    .cfi_offset ra, -4
+; RV32IZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; RV32IZHINXMIN-NEXT:    call __fixhfdi@plt
+; RV32IZHINXMIN-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZHINXMIN-NEXT:    addi sp, sp, 16
+; RV32IZHINXMIN-NEXT:    ret
+;
+; RV64IZHINXMIN-LABEL: test_floor_si64:
+; RV64IZHINXMIN:       # %bb.0:
+; RV64IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV64IZHINXMIN-NEXT:    lui a1, 307200
+; RV64IZHINXMIN-NEXT:    fabs.s a2, a0
+; RV64IZHINXMIN-NEXT:    flt.s a1, a2, a1
+; RV64IZHINXMIN-NEXT:    beqz a1, .LBB3_2
+; RV64IZHINXMIN-NEXT:  # %bb.1:
+; RV64IZHINXMIN-NEXT:    fcvt.w.s a1, a0, rdn
+; RV64IZHINXMIN-NEXT:    fcvt.s.w a1, a1, rdn
+; RV64IZHINXMIN-NEXT:    fsgnj.s a0, a1, a0
+; RV64IZHINXMIN-NEXT:  .LBB3_2:
+; RV64IZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; RV64IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV64IZHINXMIN-NEXT:    fcvt.l.s a0, a0, rtz
+; RV64IZHINXMIN-NEXT:    ret
   %a = call half @llvm.floor.f16(half %x)
   %b = fptosi half %a to i64
   ret i64 %b
 }
 
 define zeroext i8 @test_floor_ui8(half %x) {
 ; RV32IZFH-LABEL: test_floor_ui8:
 ; RV32IZFH:       # %bb.0:
 ; RV32IZFH-NEXT:    fcvt.wu.h a0, fa0, rdn
 ; RV32IZFH-NEXT:    ret
 ;
 ; RV64IZFH-LABEL: test_floor_ui8:
 ; RV64IZFH:       # %bb.0:
 ; RV64IZFH-NEXT:    fcvt.lu.h a0, fa0, rdn
 ; RV64IZFH-NEXT:    ret
 ;
+; RV32IZHINX-LABEL: test_floor_ui8:
+; RV32IZHINX:       # %bb.0:
+; RV32IZHINX-NEXT:    lui a1, %hi(.LCPI4_0)
+; RV32IZHINX-NEXT:    lh a1, %lo(.LCPI4_0)(a1)
+; RV32IZHINX-NEXT:    fabs.h a2, a0
+; RV32IZHINX-NEXT:    flt.h a1, a2, a1
+; RV32IZHINX-NEXT:    beqz a1, .LBB4_2
+; RV32IZHINX-NEXT:  # %bb.1:
+; RV32IZHINX-NEXT:    fcvt.w.h a1, a0, rdn
+; RV32IZHINX-NEXT:    fcvt.h.w a1, a1, rdn
+; RV32IZHINX-NEXT:    fsgnj.h a0, a1, a0
+; RV32IZHINX-NEXT:  .LBB4_2:
+; RV32IZHINX-NEXT:    fcvt.wu.h a0, a0, rtz
+; RV32IZHINX-NEXT:    ret
+;
+; RV64IZHINX-LABEL: test_floor_ui8:
+; RV64IZHINX:       # %bb.0:
+; RV64IZHINX-NEXT:    lui a1, %hi(.LCPI4_0)
+; RV64IZHINX-NEXT:    lh a1, %lo(.LCPI4_0)(a1)
+; RV64IZHINX-NEXT:    fabs.h a2, a0
+; RV64IZHINX-NEXT:    flt.h a1, a2, a1
+; RV64IZHINX-NEXT:    beqz a1, .LBB4_2
+; RV64IZHINX-NEXT:  # %bb.1:
+; RV64IZHINX-NEXT:    fcvt.w.h a1, a0, rdn
+; RV64IZHINX-NEXT:    fcvt.h.w a1, a1, rdn
+; RV64IZHINX-NEXT:    fsgnj.h a0, a1, a0
+; RV64IZHINX-NEXT:  .LBB4_2:
+; RV64IZHINX-NEXT:    fcvt.lu.h a0, a0, rtz
+; RV64IZHINX-NEXT:    ret
+;
 ; RV32IZFHMIN-LABEL: test_floor_ui8:
 ; RV32IZFHMIN:       # %bb.0:
 ; RV32IZFHMIN-NEXT:    fcvt.s.h fa5, fa0
 ; RV32IZFHMIN-NEXT:    lui a0, 307200
 ; RV32IZFHMIN-NEXT:    fmv.w.x fa4, a0
 ; RV32IZFHMIN-NEXT:    fabs.s fa3, fa5
 ; RV32IZFHMIN-NEXT:    flt.s a0, fa3, fa4
 ; RV32IZFHMIN-NEXT:    beqz a0, .LBB4_2

 ; RV64IZFHMIN-NEXT:    fcvt.w.s a0, fa5, rdn
 ; RV64IZFHMIN-NEXT:    fcvt.s.w fa4, a0, rdn
 ; RV64IZFHMIN-NEXT:    fsgnj.s fa5, fa4, fa5
 ; RV64IZFHMIN-NEXT:  .LBB4_2:
 ; RV64IZFHMIN-NEXT:    fcvt.h.s fa5, fa5
 ; RV64IZFHMIN-NEXT:    fcvt.s.h fa5, fa5
 ; RV64IZFHMIN-NEXT:    fcvt.lu.s a0, fa5, rtz
 ; RV64IZFHMIN-NEXT:    ret
+;
+; RV32IZHINXMIN-LABEL: test_floor_ui8:
+; RV32IZHINXMIN:       # %bb.0:
+; RV32IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV32IZHINXMIN-NEXT:    lui a1, 307200
+; RV32IZHINXMIN-NEXT:    fabs.s a2, a0
+; RV32IZHINXMIN-NEXT:    flt.s a1, a2, a1
+; RV32IZHINXMIN-NEXT:    beqz a1, .LBB4_2
+; RV32IZHINXMIN-NEXT:  # %bb.1:
+; RV32IZHINXMIN-NEXT:    fcvt.w.s a1, a0, rdn
+; RV32IZHINXMIN-NEXT:    fcvt.s.w a1, a1, rdn
+; RV32IZHINXMIN-NEXT:    fsgnj.s a0, a1, a0
+; RV32IZHINXMIN-NEXT:  .LBB4_2:
+; RV32IZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; RV32IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV32IZHINXMIN-NEXT:    fcvt.wu.s a0, a0, rtz
+; RV32IZHINXMIN-NEXT:    ret
+;
+; RV64IZHINXMIN-LABEL: test_floor_ui8:
+; RV64IZHINXMIN:       # %bb.0:
+; RV64IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV64IZHINXMIN-NEXT:    lui a1, 307200
+; RV64IZHINXMIN-NEXT:    fabs.s a2, a0
+; RV64IZHINXMIN-NEXT:    flt.s a1, a2, a1
+; RV64IZHINXMIN-NEXT:    beqz a1, .LBB4_2
+; RV64IZHINXMIN-NEXT:  # %bb.1:
+; RV64IZHINXMIN-NEXT:    fcvt.w.s a1, a0, rdn
+; RV64IZHINXMIN-NEXT:    fcvt.s.w a1, a1, rdn
+; RV64IZHINXMIN-NEXT:    fsgnj.s a0, a1, a0
+; RV64IZHINXMIN-NEXT:  .LBB4_2:
+; RV64IZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; RV64IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV64IZHINXMIN-NEXT:    fcvt.lu.s a0, a0, rtz
+; RV64IZHINXMIN-NEXT:    ret
   %a = call half @llvm.floor.f16(half %x)
   %b = fptoui half %a to i8
   ret i8 %b
 }
 
 define zeroext i16 @test_floor_ui16(half %x) {
 ; RV32IZFH-LABEL: test_floor_ui16:
 ; RV32IZFH:       # %bb.0:
 ; RV32IZFH-NEXT:    fcvt.wu.h a0, fa0, rdn
 ; RV32IZFH-NEXT:    ret
 ;
 ; RV64IZFH-LABEL: test_floor_ui16:
 ; RV64IZFH:       # %bb.0:
 ; RV64IZFH-NEXT:    fcvt.lu.h a0, fa0, rdn
 ; RV64IZFH-NEXT:    ret
 ;
+; RV32IZHINX-LABEL: test_floor_ui16:
+; RV32IZHINX:       # %bb.0:
+; RV32IZHINX-NEXT:    lui a1, %hi(.LCPI5_0)
+; RV32IZHINX-NEXT:    lh a1, %lo(.LCPI5_0)(a1)
+; RV32IZHINX-NEXT:    fabs.h a2, a0
+; RV32IZHINX-NEXT:    flt.h a1, a2, a1
+; RV32IZHINX-NEXT:    beqz a1, .LBB5_2
+; RV32IZHINX-NEXT:  # %bb.1:
+; RV32IZHINX-NEXT:    fcvt.w.h a1, a0, rdn
+; RV32IZHINX-NEXT:    fcvt.h.w a1, a1, rdn
+; RV32IZHINX-NEXT:    fsgnj.h a0, a1, a0
+; RV32IZHINX-NEXT:  .LBB5_2:
+; RV32IZHINX-NEXT:    fcvt.wu.h a0, a0, rtz
+; RV32IZHINX-NEXT:    ret
+;
+; RV64IZHINX-LABEL: test_floor_ui16:
+; RV64IZHINX:       # %bb.0:
+; RV64IZHINX-NEXT:    lui a1, %hi(.LCPI5_0)
+; RV64IZHINX-NEXT:    lh a1, %lo(.LCPI5_0)(a1)
+; RV64IZHINX-NEXT:    fabs.h a2, a0
+; RV64IZHINX-NEXT:    flt.h a1, a2, a1
+; RV64IZHINX-NEXT:    beqz a1, .LBB5_2
+; RV64IZHINX-NEXT:  # %bb.1:
+; RV64IZHINX-NEXT:    fcvt.w.h a1, a0, rdn
+; RV64IZHINX-NEXT:    fcvt.h.w a1, a1, rdn
+; RV64IZHINX-NEXT:    fsgnj.h a0, a1, a0
+; RV64IZHINX-NEXT:  .LBB5_2:
+; RV64IZHINX-NEXT:    fcvt.lu.h a0, a0, rtz
+; RV64IZHINX-NEXT:    ret
+;
 ; RV32IZFHMIN-LABEL: test_floor_ui16:
 ; RV32IZFHMIN:       # %bb.0:
 ; RV32IZFHMIN-NEXT:    fcvt.s.h fa5, fa0
 ; RV32IZFHMIN-NEXT:    lui a0, 307200
 ; RV32IZFHMIN-NEXT:    fmv.w.x fa4, a0
 ; RV32IZFHMIN-NEXT:    fabs.s fa3, fa5
 ; RV32IZFHMIN-NEXT:    flt.s a0, fa3, fa4
 ; RV32IZFHMIN-NEXT:    beqz a0, .LBB5_2

 ; RV64IZFHMIN-NEXT:    fcvt.w.s a0, fa5, rdn
 ; RV64IZFHMIN-NEXT:    fcvt.s.w fa4, a0, rdn
 ; RV64IZFHMIN-NEXT:    fsgnj.s fa5, fa4, fa5
 ; RV64IZFHMIN-NEXT:  .LBB5_2:
 ; RV64IZFHMIN-NEXT:    fcvt.h.s fa5, fa5
 ; RV64IZFHMIN-NEXT:    fcvt.s.h fa5, fa5
 ; RV64IZFHMIN-NEXT:    fcvt.lu.s a0, fa5, rtz
 ; RV64IZFHMIN-NEXT:    ret
+;
+; RV32IZHINXMIN-LABEL: test_floor_ui16:
+; RV32IZHINXMIN:       # %bb.0:
+; RV32IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV32IZHINXMIN-NEXT:    lui a1, 307200
+; RV32IZHINXMIN-NEXT:    fabs.s a2, a0
+; RV32IZHINXMIN-NEXT:    flt.s a1, a2, a1
+; RV32IZHINXMIN-NEXT:    beqz a1, .LBB5_2
+; RV32IZHINXMIN-NEXT:  # %bb.1:
+; RV32IZHINXMIN-NEXT:    fcvt.w.s a1, a0, rdn
+; RV32IZHINXMIN-NEXT:    fcvt.s.w a1, a1, rdn
+; RV32IZHINXMIN-NEXT:    fsgnj.s a0, a1, a0
+; RV32IZHINXMIN-NEXT:  .LBB5_2:
+; RV32IZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; RV32IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV32IZHINXMIN-NEXT:    fcvt.wu.s a0, a0, rtz
+; RV32IZHINXMIN-NEXT:    ret
+;
+; RV64IZHINXMIN-LABEL: test_floor_ui16:
+; RV64IZHINXMIN:       # %bb.0:
+; RV64IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV64IZHINXMIN-NEXT:    lui a1, 307200
+; RV64IZHINXMIN-NEXT:    fabs.s a2, a0
+; RV64IZHINXMIN-NEXT:    flt.s a1, a2, a1
+; RV64IZHINXMIN-NEXT:    beqz a1, .LBB5_2
+; RV64IZHINXMIN-NEXT:  # %bb.1:
+; RV64IZHINXMIN-NEXT:    fcvt.w.s a1, a0, rdn
+; RV64IZHINXMIN-NEXT:    fcvt.s.w a1, a1, rdn
+; RV64IZHINXMIN-NEXT:    fsgnj.s a0, a1, a0
+; RV64IZHINXMIN-NEXT:  .LBB5_2:
+; RV64IZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; RV64IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV64IZHINXMIN-NEXT:    fcvt.lu.s a0, a0, rtz
+; RV64IZHINXMIN-NEXT:    ret
   %a = call half @llvm.floor.f16(half %x)
   %b = fptoui half %a to i16
   ret i16 %b
 }
 
 define signext i32 @test_floor_ui32(half %x) {
 ; CHECKIZFH-LABEL: test_floor_ui32:
 ; CHECKIZFH:       # %bb.0:
 ; CHECKIZFH-NEXT:    fcvt.wu.h a0, fa0, rdn
 ; CHECKIZFH-NEXT:    ret
 ;
+; CHECKIZHINX-LABEL: test_floor_ui32:
+; CHECKIZHINX:       # %bb.0:
+; CHECKIZHINX-NEXT:    lui a1, %hi(.LCPI6_0)
+; CHECKIZHINX-NEXT:    lh a1, %lo(.LCPI6_0)(a1)
+; CHECKIZHINX-NEXT:    fabs.h a2, a0
+; CHECKIZHINX-NEXT:    flt.h a1, a2, a1
+; CHECKIZHINX-NEXT:    beqz a1, .LBB6_2
+; CHECKIZHINX-NEXT:  # %bb.1:
+; CHECKIZHINX-NEXT:    fcvt.w.h a1, a0, rdn
+; CHECKIZHINX-NEXT:    fcvt.h.w a1, a1, rdn
+; CHECKIZHINX-NEXT:    fsgnj.h a0, a1, a0
+; CHECKIZHINX-NEXT:  .LBB6_2:
+; CHECKIZHINX-NEXT:    fcvt.wu.h a0, a0, rtz
+; CHECKIZHINX-NEXT:    ret
+;
 ; CHECKIZFHMIN-LABEL: test_floor_ui32:
 ; CHECKIZFHMIN:       # %bb.0:
 ; CHECKIZFHMIN-NEXT:    fcvt.s.h fa5, fa0
 ; CHECKIZFHMIN-NEXT:    lui a0, 307200
 ; CHECKIZFHMIN-NEXT:    fmv.w.x fa4, a0
 ; CHECKIZFHMIN-NEXT:    fabs.s fa3, fa5
 ; CHECKIZFHMIN-NEXT:    flt.s a0, fa3, fa4
 ; CHECKIZFHMIN-NEXT:    beqz a0, .LBB6_2
 ; CHECKIZFHMIN-NEXT:  # %bb.1:
 ; CHECKIZFHMIN-NEXT:    fcvt.w.s a0, fa5, rdn
 ; CHECKIZFHMIN-NEXT:    fcvt.s.w fa4, a0, rdn
 ; CHECKIZFHMIN-NEXT:    fsgnj.s fa5, fa4, fa5
 ; CHECKIZFHMIN-NEXT:  .LBB6_2:
 ; CHECKIZFHMIN-NEXT:    fcvt.h.s fa5, fa5
 ; CHECKIZFHMIN-NEXT:    fcvt.s.h fa5, fa5
 ; CHECKIZFHMIN-NEXT:    fcvt.wu.s a0, fa5, rtz
 ; CHECKIZFHMIN-NEXT:    ret
+;
+; CHECKIZHINXMIN-LABEL: test_floor_ui32:
+; CHECKIZHINXMIN:       # %bb.0:
+; CHECKIZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECKIZHINXMIN-NEXT:    lui a1, 307200
+; CHECKIZHINXMIN-NEXT:    fabs.s a2, a0
+; CHECKIZHINXMIN-NEXT:    flt.s a1, a2, a1
+; CHECKIZHINXMIN-NEXT:    beqz a1, .LBB6_2
+; CHECKIZHINXMIN-NEXT:  # %bb.1:
+; CHECKIZHINXMIN-NEXT:    fcvt.w.s a1, a0, rdn
+; CHECKIZHINXMIN-NEXT:    fcvt.s.w a1, a1, rdn
+; CHECKIZHINXMIN-NEXT:    fsgnj.s a0, a1, a0
+; CHECKIZHINXMIN-NEXT:  .LBB6_2:
+; CHECKIZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; CHECKIZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECKIZHINXMIN-NEXT:    fcvt.wu.s a0, a0, rtz
+; CHECKIZHINXMIN-NEXT:    ret
   %a = call half @llvm.floor.f16(half %x)
   %b = fptoui half %a to i32
   ret i32 %b
 }
 
 define i64 @test_floor_ui64(half %x) {
 ; RV32IZFH-LABEL: test_floor_ui64:
 ; RV32IZFH:       # %bb.0:

 ; RV32IZFH-NEXT:    addi sp, sp, 16
 ; RV32IZFH-NEXT:    ret
 ;
 ; RV64IZFH-LABEL: test_floor_ui64:
 ; RV64IZFH:       # %bb.0:
 ; RV64IZFH-NEXT:    fcvt.lu.h a0, fa0, rdn
 ; RV64IZFH-NEXT:    ret
 ;
+; RV32IZHINX-LABEL: test_floor_ui64:
+; RV32IZHINX:       # %bb.0:
+; RV32IZHINX-NEXT:    addi sp, sp, -16
+; RV32IZHINX-NEXT:    .cfi_def_cfa_offset 16
+; RV32IZHINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZHINX-NEXT:    .cfi_offset ra, -4
+; RV32IZHINX-NEXT:    lui a1, %hi(.LCPI7_0)
+; RV32IZHINX-NEXT:    lh a1, %lo(.LCPI7_0)(a1)
+; RV32IZHINX-NEXT:    fabs.h a2, a0
+; RV32IZHINX-NEXT:    flt.h a1, a2, a1
+; RV32IZHINX-NEXT:    beqz a1, .LBB7_2
+; RV32IZHINX-NEXT:  # %bb.1:
+; RV32IZHINX-NEXT:    fcvt.w.h a1, a0, rdn
+; RV32IZHINX-NEXT:    fcvt.h.w a1, a1, rdn
+; RV32IZHINX-NEXT:    fsgnj.h a0, a1, a0
+; RV32IZHINX-NEXT:  .LBB7_2:
+; RV32IZHINX-NEXT:    call __fixunshfdi@plt
+; RV32IZHINX-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZHINX-NEXT:    addi sp, sp, 16
+; RV32IZHINX-NEXT:    ret
+;
+; RV64IZHINX-LABEL: test_floor_ui64:
+; RV64IZHINX:       # %bb.0:
+; RV64IZHINX-NEXT:    lui a1, %hi(.LCPI7_0)
+; RV64IZHINX-NEXT:    lh a1, %lo(.LCPI7_0)(a1)
+; RV64IZHINX-NEXT:    fabs.h a2, a0
+; RV64IZHINX-NEXT:    flt.h a1, a2, a1
+; RV64IZHINX-NEXT:    beqz a1, .LBB7_2
+; RV64IZHINX-NEXT:  # %bb.1:
+; RV64IZHINX-NEXT:    fcvt.w.h a1, a0, rdn
+; RV64IZHINX-NEXT:    fcvt.h.w a1, a1, rdn
+; RV64IZHINX-NEXT:    fsgnj.h a0, a1, a0
+; RV64IZHINX-NEXT:  .LBB7_2:
+; RV64IZHINX-NEXT:    fcvt.lu.h a0, a0, rtz
+; RV64IZHINX-NEXT:    ret
+;
 ; RV32IZFHMIN-LABEL: test_floor_ui64:
 ; RV32IZFHMIN:       # %bb.0:
 ; RV32IZFHMIN-NEXT:    fcvt.s.h fa5, fa0
 ; RV32IZFHMIN-NEXT:    lui a0, 307200
 ; RV32IZFHMIN-NEXT:    fmv.w.x fa4, a0
 ; RV32IZFHMIN-NEXT:    fabs.s fa3, fa5
 ; RV32IZFHMIN-NEXT:    flt.s a0, fa3, fa4
 ; RV32IZFHMIN-NEXT:    beqz a0, .LBB7_2

 ; RV64IZFHMIN-NEXT:    fcvt.w.s a0, fa5, rdn
 ; RV64IZFHMIN-NEXT:    fcvt.s.w fa4, a0, rdn
 ; RV64IZFHMIN-NEXT:    fsgnj.s fa5, fa4, fa5
 ; RV64IZFHMIN-NEXT:  .LBB7_2:
 ; RV64IZFHMIN-NEXT:    fcvt.h.s fa5, fa5
 ; RV64IZFHMIN-NEXT:    fcvt.s.h fa5, fa5
 ; RV64IZFHMIN-NEXT:    fcvt.lu.s a0, fa5, rtz
 ; RV64IZFHMIN-NEXT:    ret
+;
+; RV32IZHINXMIN-LABEL: test_floor_ui64:
+; RV32IZHINXMIN:       # %bb.0:
+; RV32IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV32IZHINXMIN-NEXT:    lui a1, 307200
+; RV32IZHINXMIN-NEXT:    fabs.s a2, a0
+; RV32IZHINXMIN-NEXT:    flt.s a1, a2, a1
+; RV32IZHINXMIN-NEXT:    beqz a1, .LBB7_2
+; RV32IZHINXMIN-NEXT:  # %bb.1:
+; RV32IZHINXMIN-NEXT:    fcvt.w.s a1, a0, rdn
+; RV32IZHINXMIN-NEXT:    fcvt.s.w a1, a1, rdn
+; RV32IZHINXMIN-NEXT:    fsgnj.s a0, a1, a0
+; RV32IZHINXMIN-NEXT:  .LBB7_2:
+; RV32IZHINXMIN-NEXT:    addi sp, sp, -16
+; RV32IZHINXMIN-NEXT:    .cfi_def_cfa_offset 16
+; RV32IZHINXMIN-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZHINXMIN-NEXT:    .cfi_offset ra, -4
+; RV32IZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; RV32IZHINXMIN-NEXT:    call __fixunshfdi@plt
+; RV32IZHINXMIN-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZHINXMIN-NEXT:    addi sp, sp, 16
+; RV32IZHINXMIN-NEXT:    ret
+;
+; RV64IZHINXMIN-LABEL: test_floor_ui64:
+; RV64IZHINXMIN:       # %bb.0:
+; RV64IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV64IZHINXMIN-NEXT:    lui a1, 307200
+; RV64IZHINXMIN-NEXT:    fabs.s a2, a0
+; RV64IZHINXMIN-NEXT:    flt.s a1, a2, a1
+; RV64IZHINXMIN-NEXT:    beqz a1, .LBB7_2
+; RV64IZHINXMIN-NEXT:  # %bb.1:
+; RV64IZHINXMIN-NEXT:    fcvt.w.s a1, a0, rdn
+; RV64IZHINXMIN-NEXT:    fcvt.s.w a1, a1, rdn
+; RV64IZHINXMIN-NEXT:    fsgnj.s a0, a1, a0
+; RV64IZHINXMIN-NEXT:  .LBB7_2:
+; RV64IZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; RV64IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV64IZHINXMIN-NEXT:    fcvt.lu.s a0, a0, rtz
+; RV64IZHINXMIN-NEXT:    ret
   %a = call half @llvm.floor.f16(half %x)
   %b = fptoui half %a to i64
   ret i64 %b
 }
 
 define signext i8 @test_ceil_si8(half %x) {
 ; RV32IZFH-LABEL: test_ceil_si8:
 ; RV32IZFH:       # %bb.0:
 ; RV32IZFH-NEXT:    fcvt.w.h a0, fa0, rup
 ; RV32IZFH-NEXT:    ret
 ;
 ; RV64IZFH-LABEL: test_ceil_si8:
 ; RV64IZFH:       # %bb.0:
 ; RV64IZFH-NEXT:    fcvt.l.h a0, fa0, rup
 ; RV64IZFH-NEXT:    ret
 ;
+; RV32IZHINX-LABEL: test_ceil_si8:
+; RV32IZHINX:       # %bb.0:
+; RV32IZHINX-NEXT:    lui a1, %hi(.LCPI8_0)
+; RV32IZHINX-NEXT:    lh a1, %lo(.LCPI8_0)(a1)
+; RV32IZHINX-NEXT:    fabs.h a2, a0
+; RV32IZHINX-NEXT:    flt.h a1, a2, a1
+; RV32IZHINX-NEXT:    beqz a1, .LBB8_2
+; RV32IZHINX-NEXT:  # %bb.1:
+; RV32IZHINX-NEXT:    fcvt.w.h a1, a0, rup
+; RV32IZHINX-NEXT:    fcvt.h.w a1, a1, rup
+; RV32IZHINX-NEXT:    fsgnj.h a0, a1, a0
+; RV32IZHINX-NEXT:  .LBB8_2:
+; RV32IZHINX-NEXT:    fcvt.w.h a0, a0, rtz
+; RV32IZHINX-NEXT:    ret
+;
+; RV64IZHINX-LABEL: test_ceil_si8:
+; RV64IZHINX:       # %bb.0:
+; RV64IZHINX-NEXT:    lui a1, %hi(.LCPI8_0)
+; RV64IZHINX-NEXT:    lh a1, %lo(.LCPI8_0)(a1)
+; RV64IZHINX-NEXT:    fabs.h a2, a0
+; RV64IZHINX-NEXT:    flt.h a1, a2, a1
+; RV64IZHINX-NEXT:    beqz a1, .LBB8_2
+; RV64IZHINX-NEXT:  # %bb.1:
+; RV64IZHINX-NEXT:    fcvt.w.h a1, a0, rup
+; RV64IZHINX-NEXT:    fcvt.h.w a1, a1, rup
+; RV64IZHINX-NEXT:    fsgnj.h a0, a1, a0
+; RV64IZHINX-NEXT:  .LBB8_2:
+; RV64IZHINX-NEXT:    fcvt.l.h a0, a0, rtz
+; RV64IZHINX-NEXT:    ret
+;
 ; RV32IZFHMIN-LABEL: test_ceil_si8:
 ; RV32IZFHMIN:       # %bb.0:
 ; RV32IZFHMIN-NEXT:    fcvt.s.h fa5, fa0
 ; RV32IZFHMIN-NEXT:    lui a0, 307200
 ; RV32IZFHMIN-NEXT:    fmv.w.x fa4, a0
 ; RV32IZFHMIN-NEXT:    fabs.s fa3, fa5
 ; RV32IZFHMIN-NEXT:    flt.s a0, fa3, fa4
 ; RV32IZFHMIN-NEXT:    beqz a0, .LBB8_2

 ; RV64IZFHMIN-NEXT:    fcvt.w.s a0, fa5, rup
 ; RV64IZFHMIN-NEXT:    fcvt.s.w fa4, a0, rup
 ; RV64IZFHMIN-NEXT:    fsgnj.s fa5, fa4, fa5
 ; RV64IZFHMIN-NEXT:  .LBB8_2:
 ; RV64IZFHMIN-NEXT:    fcvt.h.s fa5, fa5
 ; RV64IZFHMIN-NEXT:    fcvt.s.h fa5, fa5
 ; RV64IZFHMIN-NEXT:    fcvt.l.s a0, fa5, rtz
 ; RV64IZFHMIN-NEXT:    ret
+;
+; RV32IZHINXMIN-LABEL: test_ceil_si8:
+; RV32IZHINXMIN:       # %bb.0:
+; RV32IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV32IZHINXMIN-NEXT:    lui a1, 307200
+; RV32IZHINXMIN-NEXT:    fabs.s a2, a0
+; RV32IZHINXMIN-NEXT:    flt.s a1, a2, a1
+; RV32IZHINXMIN-NEXT:    beqz a1, .LBB8_2
+; RV32IZHINXMIN-NEXT:  # %bb.1:
+; RV32IZHINXMIN-NEXT:    fcvt.w.s a1, a0, rup
+; RV32IZHINXMIN-NEXT:    fcvt.s.w a1, a1, rup
+; RV32IZHINXMIN-NEXT:    fsgnj.s a0, a1, a0
+; RV32IZHINXMIN-NEXT:  .LBB8_2:
+; RV32IZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; RV32IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV32IZHINXMIN-NEXT:    fcvt.w.s a0, a0, rtz
+; RV32IZHINXMIN-NEXT:    ret
+;
+; RV64IZHINXMIN-LABEL: test_ceil_si8:
+; RV64IZHINXMIN:       # %bb.0:
+; RV64IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV64IZHINXMIN-NEXT:    lui a1, 307200
+; RV64IZHINXMIN-NEXT:    fabs.s a2, a0
+; RV64IZHINXMIN-NEXT:    flt.s a1, a2, a1
+; RV64IZHINXMIN-NEXT:    beqz a1, .LBB8_2
+; RV64IZHINXMIN-NEXT:  # %bb.1:
+; RV64IZHINXMIN-NEXT:    fcvt.w.s a1, a0, rup
+; RV64IZHINXMIN-NEXT:    fcvt.s.w a1, a1, rup
+; RV64IZHINXMIN-NEXT:    fsgnj.s a0, a1, a0
+; RV64IZHINXMIN-NEXT:  .LBB8_2:
+; RV64IZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; RV64IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV64IZHINXMIN-NEXT:    fcvt.l.s a0, a0, rtz
+; RV64IZHINXMIN-NEXT:    ret
   %a = call half @llvm.ceil.f16(half %x)
   %b = fptosi half %a to i8
   ret i8 %b
 }
 
 define signext i16 @test_ceil_si16(half %x) {
 ; RV32IZFH-LABEL: test_ceil_si16:
 ; RV32IZFH:       # %bb.0:
 ; RV32IZFH-NEXT:    fcvt.w.h a0, fa0, rup
 ; RV32IZFH-NEXT:    ret
 ;
 ; RV64IZFH-LABEL: test_ceil_si16:
 ; RV64IZFH:       # %bb.0:
 ; RV64IZFH-NEXT:    fcvt.l.h a0, fa0, rup
 ; RV64IZFH-NEXT:    ret
 ;
+; RV32IZHINX-LABEL: test_ceil_si16:
+; RV32IZHINX:       # %bb.0:
+; RV32IZHINX-NEXT:    lui a1, %hi(.LCPI9_0)
+; RV32IZHINX-NEXT:    lh a1, %lo(.LCPI9_0)(a1)
+; RV32IZHINX-NEXT:    fabs.h a2, a0
+; RV32IZHINX-NEXT:    flt.h a1, a2, a1
+; RV32IZHINX-NEXT:    beqz a1, .LBB9_2
+; RV32IZHINX-NEXT:  # %bb.1:
+; RV32IZHINX-NEXT:    fcvt.w.h a1, a0, rup
+; RV32IZHINX-NEXT:    fcvt.h.w a1, a1, rup
+; RV32IZHINX-NEXT:    fsgnj.h a0, a1, a0
+; RV32IZHINX-NEXT:  .LBB9_2:
+; RV32IZHINX-NEXT:    fcvt.w.h a0, a0, rtz
+; RV32IZHINX-NEXT:    ret
+;
+; RV64IZHINX-LABEL: test_ceil_si16:
+; RV64IZHINX:       # %bb.0:
+; RV64IZHINX-NEXT:    lui a1, %hi(.LCPI9_0)
+; RV64IZHINX-NEXT:    lh a1, %lo(.LCPI9_0)(a1)
+; RV64IZHINX-NEXT:    fabs.h a2, a0
+; RV64IZHINX-NEXT:    flt.h a1, a2, a1
+; RV64IZHINX-NEXT:    beqz a1, .LBB9_2
+; RV64IZHINX-NEXT:  # %bb.1:
+; RV64IZHINX-NEXT:    fcvt.w.h a1, a0, rup
+; RV64IZHINX-NEXT:    fcvt.h.w a1, a1, rup
+; RV64IZHINX-NEXT:    fsgnj.h a0, a1, a0
+; RV64IZHINX-NEXT:  .LBB9_2:
+; RV64IZHINX-NEXT:    fcvt.l.h a0, a0, rtz
+; RV64IZHINX-NEXT:    ret
+;
 ; RV32IZFHMIN-LABEL: test_ceil_si16:
 ; RV32IZFHMIN:       # %bb.0:
 ; RV32IZFHMIN-NEXT:    fcvt.s.h fa5, fa0
 ; RV32IZFHMIN-NEXT:    lui a0, 307200
 ; RV32IZFHMIN-NEXT:    fmv.w.x fa4, a0
 ; RV32IZFHMIN-NEXT:    fabs.s fa3, fa5
 ; RV32IZFHMIN-NEXT:    flt.s a0, fa3, fa4
 ; RV32IZFHMIN-NEXT:    beqz a0, .LBB9_2

 ; RV64IZFHMIN-NEXT:    fcvt.w.s a0, fa5, rup
 ; RV64IZFHMIN-NEXT:    fcvt.s.w fa4, a0, rup
 ; RV64IZFHMIN-NEXT:    fsgnj.s fa5, fa4, fa5
 ; RV64IZFHMIN-NEXT:  .LBB9_2:
 ; RV64IZFHMIN-NEXT:    fcvt.h.s fa5, fa5
 ; RV64IZFHMIN-NEXT:    fcvt.s.h fa5, fa5
 ; RV64IZFHMIN-NEXT:    fcvt.l.s a0, fa5, rtz
 ; RV64IZFHMIN-NEXT:    ret
+;
+; RV32IZHINXMIN-LABEL: test_ceil_si16:
+; RV32IZHINXMIN:       # %bb.0:
+; RV32IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV32IZHINXMIN-NEXT:    lui a1, 307200
+; RV32IZHINXMIN-NEXT:    fabs.s a2, a0
+; RV32IZHINXMIN-NEXT:    flt.s a1, a2, a1
+; RV32IZHINXMIN-NEXT:    beqz a1, .LBB9_2
+; RV32IZHINXMIN-NEXT:  # %bb.1:
+; RV32IZHINXMIN-NEXT:    fcvt.w.s a1, a0, rup
+; RV32IZHINXMIN-NEXT:    fcvt.s.w a1, a1, rup
+; RV32IZHINXMIN-NEXT:    fsgnj.s a0, a1, a0
+; RV32IZHINXMIN-NEXT:  .LBB9_2:
+; RV32IZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; RV32IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV32IZHINXMIN-NEXT:    fcvt.w.s a0, a0, rtz
+; RV32IZHINXMIN-NEXT:    ret
+;
+; RV64IZHINXMIN-LABEL: test_ceil_si16:
+; RV64IZHINXMIN:       # %bb.0:
+; RV64IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV64IZHINXMIN-NEXT:    lui a1, 307200
+; RV64IZHINXMIN-NEXT:    fabs.s a2, a0
+; RV64IZHINXMIN-NEXT:    flt.s a1, a2, a1
+; RV64IZHINXMIN-NEXT:    beqz a1, .LBB9_2
+; RV64IZHINXMIN-NEXT:  # %bb.1:
+; RV64IZHINXMIN-NEXT:    fcvt.w.s a1, a0, rup
+; RV64IZHINXMIN-NEXT:    fcvt.s.w a1, a1, rup
+; RV64IZHINXMIN-NEXT:    fsgnj.s a0, a1, a0
+; RV64IZHINXMIN-NEXT:  .LBB9_2:
+; RV64IZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; RV64IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV64IZHINXMIN-NEXT:    fcvt.l.s a0, a0, rtz
+; RV64IZHINXMIN-NEXT:    ret
   %a = call half @llvm.ceil.f16(half %x)
   %b = fptosi half %a to i16
   ret i16 %b
 }
 
 define signext i32 @test_ceil_si32(half %x) {
 ; CHECKIZFH-LABEL: test_ceil_si32:
 ; CHECKIZFH:       # %bb.0:
 ; CHECKIZFH-NEXT:    fcvt.w.h a0, fa0, rup
 ; CHECKIZFH-NEXT:    ret
 ;
+; CHECKIZHINX-LABEL: test_ceil_si32:
+; CHECKIZHINX:       # %bb.0:
+; CHECKIZHINX-NEXT:    lui a1, %hi(.LCPI10_0)
+; CHECKIZHINX-NEXT:    lh a1, %lo(.LCPI10_0)(a1)
+; CHECKIZHINX-NEXT:    fabs.h a2, a0
+; CHECKIZHINX-NEXT:    flt.h a1, a2, a1
+; CHECKIZHINX-NEXT:    beqz a1, .LBB10_2
+; CHECKIZHINX-NEXT:  # %bb.1:
+; CHECKIZHINX-NEXT:    fcvt.w.h a1, a0, rup
+; CHECKIZHINX-NEXT:    fcvt.h.w a1, a1, rup
+; CHECKIZHINX-NEXT:    fsgnj.h a0, a1, a0
+; CHECKIZHINX-NEXT:  .LBB10_2:
+; CHECKIZHINX-NEXT:    fcvt.w.h a0, a0, rtz
+; CHECKIZHINX-NEXT:    ret
+;
 ; CHECKIZFHMIN-LABEL: test_ceil_si32:
 ; CHECKIZFHMIN:       # %bb.0:
 ; CHECKIZFHMIN-NEXT:    fcvt.s.h fa5, fa0
 ; CHECKIZFHMIN-NEXT:    lui a0, 307200
 ; CHECKIZFHMIN-NEXT:    fmv.w.x fa4, a0
 ; CHECKIZFHMIN-NEXT:    fabs.s fa3, fa5
 ; CHECKIZFHMIN-NEXT:    flt.s a0, fa3, fa4
 ; CHECKIZFHMIN-NEXT:    beqz a0, .LBB10_2
 ; CHECKIZFHMIN-NEXT:  # %bb.1:
 ; CHECKIZFHMIN-NEXT:    fcvt.w.s a0, fa5, rup
 ; CHECKIZFHMIN-NEXT:    fcvt.s.w fa4, a0, rup
 ; CHECKIZFHMIN-NEXT:    fsgnj.s fa5, fa4, fa5
 ; CHECKIZFHMIN-NEXT:  .LBB10_2:
 ; CHECKIZFHMIN-NEXT:    fcvt.h.s fa5, fa5
 ; CHECKIZFHMIN-NEXT:    fcvt.s.h fa5, fa5
 ; CHECKIZFHMIN-NEXT:    fcvt.w.s a0, fa5, rtz
 ; CHECKIZFHMIN-NEXT:    ret
+;
+; CHECKIZHINXMIN-LABEL: test_ceil_si32:
+; CHECKIZHINXMIN:       # %bb.0:
+; CHECKIZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECKIZHINXMIN-NEXT:    lui a1, 307200
+; CHECKIZHINXMIN-NEXT:    fabs.s a2, a0
+; CHECKIZHINXMIN-NEXT:    flt.s a1, a2, a1
+; CHECKIZHINXMIN-NEXT:    beqz a1, .LBB10_2
+; CHECKIZHINXMIN-NEXT:  # %bb.1:
+; CHECKIZHINXMIN-NEXT:    fcvt.w.s a1, a0, rup
+; CHECKIZHINXMIN-NEXT:    fcvt.s.w a1, a1, rup
+; CHECKIZHINXMIN-NEXT:    fsgnj.s a0, a1, a0
+; CHECKIZHINXMIN-NEXT:  .LBB10_2:
+; CHECKIZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; CHECKIZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECKIZHINXMIN-NEXT:    fcvt.w.s a0, a0, rtz
+; CHECKIZHINXMIN-NEXT:    ret
   %a = call half @llvm.ceil.f16(half %x)
   %b = fptosi half %a to i32
   ret i32 %b
 }
 
 define i64 @test_ceil_si64(half %x) {
 ; RV32IZFH-LABEL: test_ceil_si64:
 ; RV32IZFH:       # %bb.0:

 ; RV32IZFH-NEXT:    addi sp, sp, 16
 ; RV32IZFH-NEXT:    ret
 ;
 ; RV64IZFH-LABEL: test_ceil_si64:
 ; RV64IZFH:       # %bb.0:
 ; RV64IZFH-NEXT:    fcvt.l.h a0, fa0, rup
 ; RV64IZFH-NEXT:    ret
 ;
+; RV32IZHINX-LABEL: test_ceil_si64:
+; RV32IZHINX:       # %bb.0:
+; RV32IZHINX-NEXT:    addi sp, sp, -16
+; RV32IZHINX-NEXT:    .cfi_def_cfa_offset 16
+; RV32IZHINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZHINX-NEXT:    .cfi_offset ra, -4
+; RV32IZHINX-NEXT:    lui a1, %hi(.LCPI11_0)
+; RV32IZHINX-NEXT:    lh a1, %lo(.LCPI11_0)(a1)
+; RV32IZHINX-NEXT:    fabs.h a2, a0
+; RV32IZHINX-NEXT:    flt.h a1, a2, a1
+; RV32IZHINX-NEXT:    beqz a1, .LBB11_2
+; RV32IZHINX-NEXT:  # %bb.1:
+; RV32IZHINX-NEXT:    fcvt.w.h a1, a0, rup
+; RV32IZHINX-NEXT:    fcvt.h.w a1, a1, rup
+; RV32IZHINX-NEXT:    fsgnj.h a0, a1, a0
+; RV32IZHINX-NEXT:  .LBB11_2:
+; RV32IZHINX-NEXT:    call __fixhfdi@plt
+; RV32IZHINX-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZHINX-NEXT:    addi sp, sp, 16
+; RV32IZHINX-NEXT:    ret
+;
+; RV64IZHINX-LABEL: test_ceil_si64:
+; RV64IZHINX:       # %bb.0:
+; RV64IZHINX-NEXT:    lui a1, %hi(.LCPI11_0)
+; RV64IZHINX-NEXT:    lh a1, %lo(.LCPI11_0)(a1)
+; RV64IZHINX-NEXT:    fabs.h a2, a0
+; RV64IZHINX-NEXT:    flt.h a1, a2, a1
+; RV64IZHINX-NEXT:    beqz a1, .LBB11_2
+; RV64IZHINX-NEXT:  # %bb.1:
+; RV64IZHINX-NEXT:    fcvt.w.h a1, a0, rup
+; RV64IZHINX-NEXT:    fcvt.h.w a1, a1, rup
+; RV64IZHINX-NEXT:    fsgnj.h a0, a1, a0
+; RV64IZHINX-NEXT:  .LBB11_2:
+; RV64IZHINX-NEXT:    fcvt.l.h a0, a0, rtz
+; RV64IZHINX-NEXT:    ret
+;
 ; RV32IZFHMIN-LABEL: test_ceil_si64:
 ; RV32IZFHMIN:       # %bb.0:
 ; RV32IZFHMIN-NEXT:    fcvt.s.h fa5, fa0
 ; RV32IZFHMIN-NEXT:    lui a0, 307200
 ; RV32IZFHMIN-NEXT:    fmv.w.x fa4, a0
 ; RV32IZFHMIN-NEXT:    fabs.s fa3, fa5
 ; RV32IZFHMIN-NEXT:    flt.s a0, fa3, fa4
 ; RV32IZFHMIN-NEXT:    beqz a0, .LBB11_2

 ; RV64IZFHMIN-NEXT:    fcvt.w.s a0, fa5, rup
 ; RV64IZFHMIN-NEXT:    fcvt.s.w fa4, a0, rup
 ; RV64IZFHMIN-NEXT:    fsgnj.s fa5, fa4, fa5
 ; RV64IZFHMIN-NEXT:  .LBB11_2:
 ; RV64IZFHMIN-NEXT:    fcvt.h.s fa5, fa5
 ; RV64IZFHMIN-NEXT:    fcvt.s.h fa5, fa5
 ; RV64IZFHMIN-NEXT:    fcvt.l.s a0, fa5, rtz
 ; RV64IZFHMIN-NEXT:    ret
+;
+; RV32IZHINXMIN-LABEL: test_ceil_si64:
+; RV32IZHINXMIN:       # %bb.0:
+; RV32IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV32IZHINXMIN-NEXT:    lui a1, 307200
+; RV32IZHINXMIN-NEXT:    fabs.s a2, a0
+; RV32IZHINXMIN-NEXT:    flt.s a1, a2, a1
+; RV32IZHINXMIN-NEXT:    beqz a1, .LBB11_2
+; RV32IZHINXMIN-NEXT:  # %bb.1:
+; RV32IZHINXMIN-NEXT:    fcvt.w.s a1, a0, rup
+; RV32IZHINXMIN-NEXT:    fcvt.s.w a1, a1, rup
+; RV32IZHINXMIN-NEXT:    fsgnj.s a0, a1, a0
+; RV32IZHINXMIN-NEXT:  .LBB11_2:
+; RV32IZHINXMIN-NEXT:    addi sp, sp, -16
+; RV32IZHINXMIN-NEXT:    .cfi_def_cfa_offset 16
+; RV32IZHINXMIN-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZHINXMIN-NEXT:    .cfi_offset ra, -4
+; RV32IZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; RV32IZHINXMIN-NEXT:    call __fixhfdi@plt
+; RV32IZHINXMIN-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZHINXMIN-NEXT:    addi sp, sp, 16
+; RV32IZHINXMIN-NEXT:    ret
+;
+; RV64IZHINXMIN-LABEL: test_ceil_si64:
+; RV64IZHINXMIN:       # %bb.0:
+; RV64IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV64IZHINXMIN-NEXT:    lui a1, 307200
+; RV64IZHINXMIN-NEXT:    fabs.s a2, a0
+; RV64IZHINXMIN-NEXT:    flt.s a1, a2, a1
+; RV64IZHINXMIN-NEXT:    beqz a1, .LBB11_2
+; RV64IZHINXMIN-NEXT:  # %bb.1:
+; RV64IZHINXMIN-NEXT:    fcvt.w.s a1, a0, rup
+; RV64IZHINXMIN-NEXT:    fcvt.s.w a1, a1, rup
+; RV64IZHINXMIN-NEXT:    fsgnj.s a0, a1, a0
+; RV64IZHINXMIN-NEXT:  .LBB11_2:
+; RV64IZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; RV64IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV64IZHINXMIN-NEXT:    fcvt.l.s a0, a0, rtz
+; RV64IZHINXMIN-NEXT:    ret
   %a = call half @llvm.ceil.f16(half %x)
   %b = fptosi half %a to i64
   ret i64 %b
 }
 
 define zeroext i8 @test_ceil_ui8(half %x) {
 ; RV32IZFH-LABEL: test_ceil_ui8:
 ; RV32IZFH:       # %bb.0:
 ; RV32IZFH-NEXT:    fcvt.wu.h a0, fa0, rup
 ; RV32IZFH-NEXT:    ret
 ;
 ; RV64IZFH-LABEL: test_ceil_ui8:
 ; RV64IZFH:       # %bb.0:
 ; RV64IZFH-NEXT:    fcvt.lu.h a0, fa0, rup
 ; RV64IZFH-NEXT:    ret
 ;
+; RV32IZHINX-LABEL: test_ceil_ui8:
+; RV32IZHINX:       # %bb.0:
+; RV32IZHINX-NEXT:    lui a1, %hi(.LCPI12_0)
+; RV32IZHINX-NEXT:    lh a1, %lo(.LCPI12_0)(a1)
+; RV32IZHINX-NEXT:    fabs.h a2, a0
+; RV32IZHINX-NEXT:    flt.h a1, a2, a1
+; RV32IZHINX-NEXT:    beqz a1, .LBB12_2
+; RV32IZHINX-NEXT:  # %bb.1:
+; RV32IZHINX-NEXT:    fcvt.w.h a1, a0, rup
+; RV32IZHINX-NEXT:    fcvt.h.w a1, a1, rup
+; RV32IZHINX-NEXT:    fsgnj.h a0, a1, a0
+; RV32IZHINX-NEXT:  .LBB12_2:
+; RV32IZHINX-NEXT:    fcvt.wu.h a0, a0, rtz
+; RV32IZHINX-NEXT:    ret
+;
+; RV64IZHINX-LABEL: test_ceil_ui8:
+; RV64IZHINX:       # %bb.0:
+; RV64IZHINX-NEXT:    lui a1, %hi(.LCPI12_0)
+; RV64IZHINX-NEXT:    lh a1, %lo(.LCPI12_0)(a1)
+; RV64IZHINX-NEXT:    fabs.h a2, a0
+; RV64IZHINX-NEXT:    flt.h a1, a2, a1
+; RV64IZHINX-NEXT:    beqz a1, .LBB12_2
+; RV64IZHINX-NEXT:  # %bb.1:
+; RV64IZHINX-NEXT:    fcvt.w.h a1, a0, rup
+; RV64IZHINX-NEXT:    fcvt.h.w a1, a1, rup
+; RV64IZHINX-NEXT:    fsgnj.h a0, a1, a0
+; RV64IZHINX-NEXT:  .LBB12_2:
+; RV64IZHINX-NEXT:    fcvt.lu.h a0, a0, rtz
+; RV64IZHINX-NEXT:    ret
+;
 ; RV32IZFHMIN-LABEL: test_ceil_ui8:
 ; RV32IZFHMIN:       # %bb.0:
 ; RV32IZFHMIN-NEXT:    fcvt.s.h fa5, fa0
 ; RV32IZFHMIN-NEXT:    lui a0, 307200
 ; RV32IZFHMIN-NEXT:    fmv.w.x fa4, a0
 ; RV32IZFHMIN-NEXT:    fabs.s fa3, fa5
 ; RV32IZFHMIN-NEXT:    flt.s a0, fa3, fa4
 ; RV32IZFHMIN-NEXT:    beqz a0, .LBB12_2

 ; RV64IZFHMIN-NEXT:    fcvt.w.s a0, fa5, rup
 ; RV64IZFHMIN-NEXT:    fcvt.s.w fa4, a0, rup
 ; RV64IZFHMIN-NEXT:    fsgnj.s fa5, fa4, fa5
 ; RV64IZFHMIN-NEXT:  .LBB12_2:
 ; RV64IZFHMIN-NEXT:    fcvt.h.s fa5, fa5
 ; RV64IZFHMIN-NEXT:    fcvt.s.h fa5, fa5
 ; RV64IZFHMIN-NEXT:    fcvt.lu.s a0, fa5, rtz
 ; RV64IZFHMIN-NEXT:    ret
+;
+; RV32IZHINXMIN-LABEL: test_ceil_ui8:
+; RV32IZHINXMIN:       # %bb.0:
+; RV32IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV32IZHINXMIN-NEXT:    lui a1, 307200
+; RV32IZHINXMIN-NEXT:    fabs.s a2, a0
+; RV32IZHINXMIN-NEXT:    flt.s a1, a2, a1
+; RV32IZHINXMIN-NEXT:    beqz a1, .LBB12_2
+; RV32IZHINXMIN-NEXT:  # %bb.1:
+; RV32IZHINXMIN-NEXT:    fcvt.w.s a1, a0, rup
+; RV32IZHINXMIN-NEXT:    fcvt.s.w a1, a1, rup
+; RV32IZHINXMIN-NEXT:    fsgnj.s a0, a1, a0
+; RV32IZHINXMIN-NEXT:  .LBB12_2:
+; RV32IZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; RV32IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV32IZHINXMIN-NEXT:    fcvt.wu.s a0, a0, rtz
+; RV32IZHINXMIN-NEXT:    ret
+;
+; RV64IZHINXMIN-LABEL: test_ceil_ui8:
+; RV64IZHINXMIN:       # %bb.0:
+; RV64IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV64IZHINXMIN-NEXT:    lui a1, 307200
+; RV64IZHINXMIN-NEXT:    fabs.s a2, a0
+; RV64IZHINXMIN-NEXT:    flt.s a1, a2, a1
+; RV64IZHINXMIN-NEXT:    beqz a1, .LBB12_2
+; RV64IZHINXMIN-NEXT:  # %bb.1:
+; RV64IZHINXMIN-NEXT:    fcvt.w.s a1, a0, rup
+; RV64IZHINXMIN-NEXT:    fcvt.s.w a1, a1, rup
+; RV64IZHINXMIN-NEXT:    fsgnj.s a0, a1, a0
+; RV64IZHINXMIN-NEXT:  .LBB12_2:
+; RV64IZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; RV64IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV64IZHINXMIN-NEXT:    fcvt.lu.s a0, a0, rtz
+; RV64IZHINXMIN-NEXT:    ret
   %a = call half @llvm.ceil.f16(half %x)
   %b = fptoui half %a to i8
   ret i8 %b
 }
 
 define zeroext i16 @test_ceil_ui16(half %x) {
 ; RV32IZFH-LABEL: test_ceil_ui16:
 ; RV32IZFH:       # %bb.0:
 ; RV32IZFH-NEXT:    fcvt.wu.h a0, fa0, rup
 ; RV32IZFH-NEXT:    ret
 ;
 ; RV64IZFH-LABEL: test_ceil_ui16:
 ; RV64IZFH:       # %bb.0:
 ; RV64IZFH-NEXT:    fcvt.lu.h a0, fa0, rup
 ; RV64IZFH-NEXT:    ret
 ;
+; RV32IZHINX-LABEL: test_ceil_ui16:
+; RV32IZHINX:       # %bb.0:
+; RV32IZHINX-NEXT:    lui a1, %hi(.LCPI13_0)
+; RV32IZHINX-NEXT:    lh a1, %lo(.LCPI13_0)(a1)
+; RV32IZHINX-NEXT:    fabs.h a2, a0
+; RV32IZHINX-NEXT:    flt.h a1, a2, a1
+; RV32IZHINX-NEXT:    beqz a1, .LBB13_2
+; RV32IZHINX-NEXT:  # %bb.1:
+; RV32IZHINX-NEXT:    fcvt.w.h a1, a0, rup
+; RV32IZHINX-NEXT:    fcvt.h.w a1, a1, rup
+; RV32IZHINX-NEXT:    fsgnj.h a0, a1, a0
+; RV32IZHINX-NEXT:  .LBB13_2:
+; RV32IZHINX-NEXT:    fcvt.wu.h a0, a0, rtz
+; RV32IZHINX-NEXT:    ret
+;
+; RV64IZHINX-LABEL: test_ceil_ui16:
+; RV64IZHINX:       # %bb.0:
+; RV64IZHINX-NEXT:    lui a1, %hi(.LCPI13_0)
+; RV64IZHINX-NEXT:    lh a1, %lo(.LCPI13_0)(a1)
+; RV64IZHINX-NEXT:    fabs.h a2, a0
+; RV64IZHINX-NEXT:    flt.h a1, a2, a1
+; RV64IZHINX-NEXT:    beqz a1, .LBB13_2
+; RV64IZHINX-NEXT:  # %bb.1:
+; RV64IZHINX-NEXT:    fcvt.w.h a1, a0, rup
+; RV64IZHINX-NEXT:    fcvt.h.w a1, a1, rup
+; RV64IZHINX-NEXT:    fsgnj.h a0, a1, a0
+; RV64IZHINX-NEXT:  .LBB13_2:
+; RV64IZHINX-NEXT:    fcvt.lu.h a0, a0, rtz
+; RV64IZHINX-NEXT:    ret
+;
 ; RV32IZFHMIN-LABEL: test_ceil_ui16:
 ; RV32IZFHMIN:       # %bb.0:
 ; RV32IZFHMIN-NEXT:    fcvt.s.h fa5, fa0
 ; RV32IZFHMIN-NEXT:    lui a0, 307200
 ; RV32IZFHMIN-NEXT:    fmv.w.x fa4, a0
 ; RV32IZFHMIN-NEXT:    fabs.s fa3, fa5
 ; RV32IZFHMIN-NEXT:    flt.s a0, fa3, fa4
 ; RV32IZFHMIN-NEXT:    beqz a0, .LBB13_2

 ; RV64IZFHMIN-NEXT:    fcvt.w.s a0, fa5, rup
 ; RV64IZFHMIN-NEXT:    fcvt.s.w fa4, a0, rup
 ; RV64IZFHMIN-NEXT:    fsgnj.s fa5, fa4, fa5
 ; RV64IZFHMIN-NEXT:  .LBB13_2:
 ; RV64IZFHMIN-NEXT:    fcvt.h.s fa5, fa5
 ; RV64IZFHMIN-NEXT:    fcvt.s.h fa5, fa5
 ; RV64IZFHMIN-NEXT:    fcvt.lu.s a0, fa5, rtz
 ; RV64IZFHMIN-NEXT:    ret
+;
+; RV32IZHINXMIN-LABEL: test_ceil_ui16:
+; RV32IZHINXMIN:       # %bb.0:
+; RV32IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV32IZHINXMIN-NEXT:    lui a1, 307200
+; RV32IZHINXMIN-NEXT:    fabs.s a2, a0
+; RV32IZHINXMIN-NEXT:    flt.s a1, a2, a1
+; RV32IZHINXMIN-NEXT:    beqz a1, .LBB13_2
+; RV32IZHINXMIN-NEXT:  # %bb.1:
+; RV32IZHINXMIN-NEXT:    fcvt.w.s a1, a0, rup
+; RV32IZHINXMIN-NEXT:    fcvt.s.w a1, a1, rup
+; RV32IZHINXMIN-NEXT:    fsgnj.s a0, a1, a0
+; RV32IZHINXMIN-NEXT:  .LBB13_2:
+; RV32IZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; RV32IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV32IZHINXMIN-NEXT:    fcvt.wu.s a0, a0, rtz
+; RV32IZHINXMIN-NEXT:    ret
+;
+; RV64IZHINXMIN-LABEL: test_ceil_ui16:
+; RV64IZHINXMIN:       # %bb.0:
+; RV64IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV64IZHINXMIN-NEXT:    lui a1, 307200
+; RV64IZHINXMIN-NEXT:    fabs.s a2, a0
+; RV64IZHINXMIN-NEXT:    flt.s a1, a2, a1
+; RV64IZHINXMIN-NEXT:    beqz a1, .LBB13_2
+; RV64IZHINXMIN-NEXT:  # %bb.1:
+; RV64IZHINXMIN-NEXT:    fcvt.w.s a1, a0, rup
+; RV64IZHINXMIN-NEXT:    fcvt.s.w a1, a1, rup
+; RV64IZHINXMIN-NEXT:    fsgnj.s a0, a1, a0
+; RV64IZHINXMIN-NEXT:  .LBB13_2:
+; RV64IZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; RV64IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV64IZHINXMIN-NEXT:    fcvt.lu.s a0, a0, rtz
+; RV64IZHINXMIN-NEXT:    ret
   %a = call half @llvm.ceil.f16(half %x)
   %b = fptoui half %a to i16
   ret i16 %b
 }
 
 define signext i32 @test_ceil_ui32(half %x) {
 ; CHECKIZFH-LABEL: test_ceil_ui32:
 ; CHECKIZFH:       # %bb.0:
 ; CHECKIZFH-NEXT:    fcvt.wu.h a0, fa0, rup
 ; CHECKIZFH-NEXT:    ret
 ;
+; CHECKIZHINX-LABEL: test_ceil_ui32:
+; CHECKIZHINX:       # %bb.0:
+; CHECKIZHINX-NEXT:    lui a1, %hi(.LCPI14_0)
+; CHECKIZHINX-NEXT:    lh a1, %lo(.LCPI14_0)(a1)
+; CHECKIZHINX-NEXT:    fabs.h a2, a0
+; CHECKIZHINX-NEXT:    flt.h a1, a2, a1
+; CHECKIZHINX-NEXT:    beqz a1, .LBB14_2
+; CHECKIZHINX-NEXT:  # %bb.1:
+; CHECKIZHINX-NEXT:    fcvt.w.h a1, a0, rup
+; CHECKIZHINX-NEXT:    fcvt.h.w a1, a1, rup
+; CHECKIZHINX-NEXT:    fsgnj.h a0, a1, a0
+; CHECKIZHINX-NEXT:  .LBB14_2:
+; CHECKIZHINX-NEXT:    fcvt.wu.h a0, a0, rtz
+; CHECKIZHINX-NEXT:    ret
+;
 ; CHECKIZFHMIN-LABEL: test_ceil_ui32:
 ; CHECKIZFHMIN:       # %bb.0:
 ; CHECKIZFHMIN-NEXT:    fcvt.s.h fa5, fa0
 ; CHECKIZFHMIN-NEXT:    lui a0, 307200
 ; CHECKIZFHMIN-NEXT:    fmv.w.x fa4, a0
 ; CHECKIZFHMIN-NEXT:    fabs.s fa3, fa5
 ; CHECKIZFHMIN-NEXT:    flt.s a0, fa3, fa4
 ; CHECKIZFHMIN-NEXT:    beqz a0, .LBB14_2
 ; CHECKIZFHMIN-NEXT:  # %bb.1:
 ; CHECKIZFHMIN-NEXT:    fcvt.w.s a0, fa5, rup
 ; CHECKIZFHMIN-NEXT:    fcvt.s.w fa4, a0, rup
 ; CHECKIZFHMIN-NEXT:    fsgnj.s fa5, fa4, fa5
 ; CHECKIZFHMIN-NEXT:  .LBB14_2:
 ; CHECKIZFHMIN-NEXT:    fcvt.h.s fa5, fa5
 ; CHECKIZFHMIN-NEXT:    fcvt.s.h fa5, fa5
 ; CHECKIZFHMIN-NEXT:    fcvt.wu.s a0, fa5, rtz
 ; CHECKIZFHMIN-NEXT:    ret
+;
+; CHECKIZHINXMIN-LABEL: test_ceil_ui32:
+; CHECKIZHINXMIN:       # %bb.0:
+; CHECKIZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECKIZHINXMIN-NEXT:    lui a1, 307200
+; CHECKIZHINXMIN-NEXT:    fabs.s a2, a0
+; CHECKIZHINXMIN-NEXT:    flt.s a1, a2, a1
+; CHECKIZHINXMIN-NEXT:    beqz a1, .LBB14_2
+; CHECKIZHINXMIN-NEXT:  # %bb.1:
+; CHECKIZHINXMIN-NEXT:    fcvt.w.s a1, a0, rup
+; CHECKIZHINXMIN-NEXT:    fcvt.s.w a1, a1, rup
+; CHECKIZHINXMIN-NEXT:    fsgnj.s a0, a1, a0
+; CHECKIZHINXMIN-NEXT:  .LBB14_2:
+; CHECKIZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; CHECKIZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECKIZHINXMIN-NEXT:    fcvt.wu.s a0, a0, rtz
+; CHECKIZHINXMIN-NEXT:    ret
   %a = call half @llvm.ceil.f16(half %x)
   %b = fptoui half %a to i32
   ret i32 %b
 }
 
 define i64 @test_ceil_ui64(half %x) {
 ; RV32IZFH-LABEL: test_ceil_ui64:
 ; RV32IZFH:       # %bb.0:

 ; RV32IZFH-NEXT:    addi sp, sp, 16
 ; RV32IZFH-NEXT:    ret
 ;
 ; RV64IZFH-LABEL: test_ceil_ui64:
 ; RV64IZFH:       # %bb.0:
 ; RV64IZFH-NEXT:    fcvt.lu.h a0, fa0, rup
 ; RV64IZFH-NEXT:    ret
 ;
+; RV32IZHINX-LABEL: test_ceil_ui64:
+; RV32IZHINX:       # %bb.0:
+; RV32IZHINX-NEXT:    addi sp, sp, -16
+; RV32IZHINX-NEXT:    .cfi_def_cfa_offset 16
+; RV32IZHINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZHINX-NEXT:    .cfi_offset ra, -4
+; RV32IZHINX-NEXT:    lui a1, %hi(.LCPI15_0)
+; RV32IZHINX-NEXT:    lh a1, %lo(.LCPI15_0)(a1)
+; RV32IZHINX-NEXT:    fabs.h a2, a0
+; RV32IZHINX-NEXT:    flt.h a1, a2, a1
+; RV32IZHINX-NEXT:    beqz a1, .LBB15_2
+; RV32IZHINX-NEXT:  # %bb.1:
+; RV32IZHINX-NEXT:    fcvt.w.h a1, a0, rup
+; RV32IZHINX-NEXT:    fcvt.h.w a1, a1, rup
+; RV32IZHINX-NEXT:    fsgnj.h a0, a1, a0
+; RV32IZHINX-NEXT:  .LBB15_2:
+; RV32IZHINX-NEXT:    call __fixunshfdi@plt
+; RV32IZHINX-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZHINX-NEXT:    addi sp, sp, 16
+; RV32IZHINX-NEXT:    ret
+;
+; RV64IZHINX-LABEL: test_ceil_ui64:
+; RV64IZHINX:       # %bb.0:
+; RV64IZHINX-NEXT:    lui a1, %hi(.LCPI15_0)
+; RV64IZHINX-NEXT:    lh a1, %lo(.LCPI15_0)(a1)
+; RV64IZHINX-NEXT:    fabs.h a2, a0
+; RV64IZHINX-NEXT:    flt.h a1, a2, a1
+; RV64IZHINX-NEXT:    beqz a1, .LBB15_2
+; RV64IZHINX-NEXT:  # %bb.1:
+; RV64IZHINX-NEXT:    fcvt.w.h a1, a0, rup
+; RV64IZHINX-NEXT:    fcvt.h.w a1, a1, rup
+; RV64IZHINX-NEXT:    fsgnj.h a0, a1, a0
+; RV64IZHINX-NEXT:  .LBB15_2:
+; RV64IZHINX-NEXT:    fcvt.lu.h a0, a0, rtz
+; RV64IZHINX-NEXT:    ret
+;
 ; RV32IZFHMIN-LABEL: test_ceil_ui64:
 ; RV32IZFHMIN:       # %bb.0:
 ; RV32IZFHMIN-NEXT:    fcvt.s.h fa5, fa0
 ; RV32IZFHMIN-NEXT:    lui a0, 307200
 ; RV32IZFHMIN-NEXT:    fmv.w.x fa4, a0
 ; RV32IZFHMIN-NEXT:    fabs.s fa3, fa5
 ; RV32IZFHMIN-NEXT:    flt.s a0, fa3, fa4
 ; RV32IZFHMIN-NEXT:    beqz a0, .LBB15_2

 ; RV64IZFHMIN-NEXT:    fcvt.w.s a0, fa5, rup
 ; RV64IZFHMIN-NEXT:    fcvt.s.w fa4, a0, rup
 ; RV64IZFHMIN-NEXT:    fsgnj.s fa5, fa4, fa5
 ; RV64IZFHMIN-NEXT:  .LBB15_2:
 ; RV64IZFHMIN-NEXT:    fcvt.h.s fa5, fa5
 ; RV64IZFHMIN-NEXT:    fcvt.s.h fa5, fa5
 ; RV64IZFHMIN-NEXT:    fcvt.lu.s a0, fa5, rtz
 ; RV64IZFHMIN-NEXT:    ret
+;
+; RV32IZHINXMIN-LABEL: test_ceil_ui64:
+; RV32IZHINXMIN:       # %bb.0:
+; RV32IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV32IZHINXMIN-NEXT:    lui a1, 307200
+; RV32IZHINXMIN-NEXT:    fabs.s a2, a0
+; RV32IZHINXMIN-NEXT:    flt.s a1, a2, a1
+; RV32IZHINXMIN-NEXT:    beqz a1, .LBB15_2
+; RV32IZHINXMIN-NEXT:  # %bb.1:
+; RV32IZHINXMIN-NEXT:    fcvt.w.s a1, a0, rup
+; RV32IZHINXMIN-NEXT:    fcvt.s.w a1, a1, rup
+; RV32IZHINXMIN-NEXT:    fsgnj.s a0, a1, a0
+; RV32IZHINXMIN-NEXT:  .LBB15_2:
+; RV32IZHINXMIN-NEXT:    addi sp, sp, -16
+; RV32IZHINXMIN-NEXT:    .cfi_def_cfa_offset 16
+; RV32IZHINXMIN-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZHINXMIN-NEXT:    .cfi_offset ra, -4
+; RV32IZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; RV32IZHINXMIN-NEXT:    call __fixunshfdi@plt
+; RV32IZHINXMIN-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZHINXMIN-NEXT:    addi sp, sp, 16
+; RV32IZHINXMIN-NEXT:    ret
+;
+; RV64IZHINXMIN-LABEL: test_ceil_ui64:
+; RV64IZHINXMIN:       # %bb.0:
+; RV64IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV64IZHINXMIN-NEXT:    lui a1, 307200
+; RV64IZHINXMIN-NEXT:    fabs.s a2, a0
+; RV64IZHINXMIN-NEXT:    flt.s a1, a2, a1
+; RV64IZHINXMIN-NEXT:    beqz a1, .LBB15_2
+; RV64IZHINXMIN-NEXT:  # %bb.1:
+; RV64IZHINXMIN-NEXT:    fcvt.w.s a1, a0, rup
+; RV64IZHINXMIN-NEXT:    fcvt.s.w a1, a1, rup
+; RV64IZHINXMIN-NEXT:    fsgnj.s a0, a1, a0
+; RV64IZHINXMIN-NEXT:  .LBB15_2:
+; RV64IZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; RV64IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV64IZHINXMIN-NEXT:    fcvt.lu.s a0, a0, rtz
+; RV64IZHINXMIN-NEXT:    ret
   %a = call half @llvm.ceil.f16(half %x)
   %b = fptoui half %a to i64
   ret i64 %b
 }
 
 define signext i8 @test_trunc_si8(half %x) {
 ; RV32IZFH-LABEL: test_trunc_si8:
 ; RV32IZFH:       # %bb.0:
 ; RV32IZFH-NEXT:    fcvt.w.h a0, fa0, rtz
 ; RV32IZFH-NEXT:    ret
 ;
 ; RV64IZFH-LABEL: test_trunc_si8:
 ; RV64IZFH:       # %bb.0:
 ; RV64IZFH-NEXT:    fcvt.l.h a0, fa0, rtz
 ; RV64IZFH-NEXT:    ret
 ;
+; RV32IZHINX-LABEL: test_trunc_si8:
+; RV32IZHINX:       # %bb.0:
+; RV32IZHINX-NEXT:    lui a1, %hi(.LCPI16_0)
+; RV32IZHINX-NEXT:    lh a1, %lo(.LCPI16_0)(a1)
+; RV32IZHINX-NEXT:    fabs.h a2, a0
+; RV32IZHINX-NEXT:    flt.h a1, a2, a1
+; RV32IZHINX-NEXT:    beqz a1, .LBB16_2
+; RV32IZHINX-NEXT:  # %bb.1:
+; RV32IZHINX-NEXT:    fcvt.w.h a1, a0, rtz
+; RV32IZHINX-NEXT:    fcvt.h.w a1, a1, rtz
+; RV32IZHINX-NEXT:    fsgnj.h a0, a1, a0
+; RV32IZHINX-NEXT:  .LBB16_2:
+; RV32IZHINX-NEXT:    fcvt.w.h a0, a0, rtz
+; RV32IZHINX-NEXT:    ret
+;
+; RV64IZHINX-LABEL: test_trunc_si8:
+; RV64IZHINX:       # %bb.0:
+; RV64IZHINX-NEXT:    lui a1, %hi(.LCPI16_0)
+; RV64IZHINX-NEXT:    lh a1, %lo(.LCPI16_0)(a1)
+; RV64IZHINX-NEXT:    fabs.h a2, a0
+; RV64IZHINX-NEXT:    flt.h a1, a2, a1
+; RV64IZHINX-NEXT:    beqz a1, .LBB16_2
+; RV64IZHINX-NEXT:  # %bb.1:
+; RV64IZHINX-NEXT:    fcvt.w.h a1, a0, rtz
+; RV64IZHINX-NEXT:    fcvt.h.w a1, a1, rtz
+; RV64IZHINX-NEXT:    fsgnj.h a0, a1, a0
+; RV64IZHINX-NEXT:  .LBB16_2:
+; RV64IZHINX-NEXT:    fcvt.l.h a0, a0, rtz
+; RV64IZHINX-NEXT:    ret
+;
 ; RV32IZFHMIN-LABEL: test_trunc_si8:
 ; RV32IZFHMIN:       # %bb.0:
 ; RV32IZFHMIN-NEXT:    fcvt.s.h fa5, fa0
 ; RV32IZFHMIN-NEXT:    lui a0, 307200
 ; RV32IZFHMIN-NEXT:    fmv.w.x fa4, a0
 ; RV32IZFHMIN-NEXT:    fabs.s fa3, fa5
 ; RV32IZFHMIN-NEXT:    flt.s a0, fa3, fa4
 ; RV32IZFHMIN-NEXT:    beqz a0, .LBB16_2

 ; RV64IZFHMIN-NEXT:    fcvt.w.s a0, fa5, rtz
 ; RV64IZFHMIN-NEXT:    fcvt.s.w fa4, a0, rtz
 ; RV64IZFHMIN-NEXT:    fsgnj.s fa5, fa4, fa5
 ; RV64IZFHMIN-NEXT:  .LBB16_2:
 ; RV64IZFHMIN-NEXT:    fcvt.h.s fa5, fa5
 ; RV64IZFHMIN-NEXT:    fcvt.s.h fa5, fa5
 ; RV64IZFHMIN-NEXT:    fcvt.l.s a0, fa5, rtz
 ; RV64IZFHMIN-NEXT:    ret
+;
+; RV32IZHINXMIN-LABEL: test_trunc_si8:
+; RV32IZHINXMIN:       # %bb.0:
+; RV32IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV32IZHINXMIN-NEXT:    lui a1, 307200
+; RV32IZHINXMIN-NEXT:    fabs.s a2, a0
+; RV32IZHINXMIN-NEXT:    flt.s a1, a2, a1
+; RV32IZHINXMIN-NEXT:    beqz a1, .LBB16_2
+; RV32IZHINXMIN-NEXT:  # %bb.1:
+; RV32IZHINXMIN-NEXT:    fcvt.w.s a1, a0, rtz
+; RV32IZHINXMIN-NEXT:    fcvt.s.w a1, a1, rtz
+; RV32IZHINXMIN-NEXT:    fsgnj.s a0, a1, a0
+; RV32IZHINXMIN-NEXT:  .LBB16_2:
+; RV32IZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; RV32IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV32IZHINXMIN-NEXT:    fcvt.w.s a0, a0, rtz
+; RV32IZHINXMIN-NEXT:    ret
+;
+; RV64IZHINXMIN-LABEL: test_trunc_si8:
+; RV64IZHINXMIN:       # %bb.0:
+; RV64IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV64IZHINXMIN-NEXT:    lui a1, 307200
+; RV64IZHINXMIN-NEXT:    fabs.s a2, a0
+; RV64IZHINXMIN-NEXT:    flt.s a1, a2, a1
+; RV64IZHINXMIN-NEXT:    beqz a1, .LBB16_2
+; RV64IZHINXMIN-NEXT:  # %bb.1:
+; RV64IZHINXMIN-NEXT:    fcvt.w.s a1, a0, rtz
+; RV64IZHINXMIN-NEXT:    fcvt.s.w a1, a1, rtz
+; RV64IZHINXMIN-NEXT:    fsgnj.s a0, a1, a0
+; RV64IZHINXMIN-NEXT:  .LBB16_2:
+; RV64IZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; RV64IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV64IZHINXMIN-NEXT:    fcvt.l.s a0, a0, rtz
+; RV64IZHINXMIN-NEXT:    ret
   %a = call half @llvm.trunc.f16(half %x)
   %b = fptosi half %a to i8
   ret i8 %b
 }
 
 define signext i16 @test_trunc_si16(half %x) {
 ; RV32IZFH-LABEL: test_trunc_si16:
 ; RV32IZFH:       # %bb.0:
 ; RV32IZFH-NEXT:    fcvt.w.h a0, fa0, rtz
 ; RV32IZFH-NEXT:    ret
 ;
 ; RV64IZFH-LABEL: test_trunc_si16:
 ; RV64IZFH:       # %bb.0:
 ; RV64IZFH-NEXT:    fcvt.l.h a0, fa0, rtz
 ; RV64IZFH-NEXT:    ret
 ;
+; RV32IZHINX-LABEL: test_trunc_si16:
+; RV32IZHINX:       # %bb.0:
+; RV32IZHINX-NEXT:    lui a1, %hi(.LCPI17_0)
+; RV32IZHINX-NEXT:    lh a1, %lo(.LCPI17_0)(a1)
+; RV32IZHINX-NEXT:    fabs.h a2, a0
+; RV32IZHINX-NEXT:    flt.h a1, a2, a1
+; RV32IZHINX-NEXT:    beqz a1, .LBB17_2
+; RV32IZHINX-NEXT:  # %bb.1:
+; RV32IZHINX-NEXT:    fcvt.w.h a1, a0, rtz
+; RV32IZHINX-NEXT:    fcvt.h.w a1, a1, rtz
+; RV32IZHINX-NEXT:    fsgnj.h a0, a1, a0
+; RV32IZHINX-NEXT:  .LBB17_2:
+; RV32IZHINX-NEXT:    fcvt.w.h a0, a0, rtz
+; RV32IZHINX-NEXT:    ret
+;
+; RV64IZHINX-LABEL: test_trunc_si16:
+; RV64IZHINX:       # %bb.0:
+; RV64IZHINX-NEXT:    lui a1, %hi(.LCPI17_0)
+; RV64IZHINX-NEXT:    lh a1, %lo(.LCPI17_0)(a1)
+; RV64IZHINX-NEXT:    fabs.h a2, a0
+; RV64IZHINX-NEXT:    flt.h a1, a2, a1
+; RV64IZHINX-NEXT:    beqz a1, .LBB17_2
+; RV64IZHINX-NEXT:  # %bb.1:
+; RV64IZHINX-NEXT:    fcvt.w.h a1, a0, rtz
+; RV64IZHINX-NEXT:    fcvt.h.w a1, a1, rtz
+; RV64IZHINX-NEXT:    fsgnj.h a0, a1, a0
+; RV64IZHINX-NEXT:  .LBB17_2:
+; RV64IZHINX-NEXT:    fcvt.l.h a0, a0, rtz
+; RV64IZHINX-NEXT:    ret
+;
 ; RV32IZFHMIN-LABEL: test_trunc_si16:
 ; RV32IZFHMIN:       # %bb.0:
 ; RV32IZFHMIN-NEXT:    fcvt.s.h fa5, fa0
 ; RV32IZFHMIN-NEXT:    lui a0, 307200
 ; RV32IZFHMIN-NEXT:    fmv.w.x fa4, a0
 ; RV32IZFHMIN-NEXT:    fabs.s fa3, fa5
 ; RV32IZFHMIN-NEXT:    flt.s a0, fa3, fa4
 ; RV32IZFHMIN-NEXT:    beqz a0, .LBB17_2

 ; RV64IZFHMIN-NEXT:    fcvt.w.s a0, fa5, rtz
 ; RV64IZFHMIN-NEXT:    fcvt.s.w fa4, a0, rtz
 ; RV64IZFHMIN-NEXT:    fsgnj.s fa5, fa4, fa5
 ; RV64IZFHMIN-NEXT:  .LBB17_2:
 ; RV64IZFHMIN-NEXT:    fcvt.h.s fa5, fa5
 ; RV64IZFHMIN-NEXT:    fcvt.s.h fa5, fa5
 ; RV64IZFHMIN-NEXT:    fcvt.l.s a0, fa5, rtz
 ; RV64IZFHMIN-NEXT:    ret
+;
+; RV32IZHINXMIN-LABEL: test_trunc_si16:
+; RV32IZHINXMIN:       # %bb.0:
+; RV32IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV32IZHINXMIN-NEXT:    lui a1, 307200
+; RV32IZHINXMIN-NEXT:    fabs.s a2, a0
+; RV32IZHINXMIN-NEXT:    flt.s a1, a2, a1
+; RV32IZHINXMIN-NEXT:    beqz a1, .LBB17_2
+; RV32IZHINXMIN-NEXT:  # %bb.1:
+; RV32IZHINXMIN-NEXT:    fcvt.w.s a1, a0, rtz
+; RV32IZHINXMIN-NEXT:    fcvt.s.w a1, a1, rtz
+; RV32IZHINXMIN-NEXT:    fsgnj.s a0, a1, a0
+; RV32IZHINXMIN-NEXT:  .LBB17_2:
+; RV32IZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; RV32IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV32IZHINXMIN-NEXT:    fcvt.w.s a0, a0, rtz
+; RV32IZHINXMIN-NEXT:    ret
+;
+; RV64IZHINXMIN-LABEL: test_trunc_si16:
+; RV64IZHINXMIN:       # %bb.0:
+; RV64IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV64IZHINXMIN-NEXT:    lui a1, 307200
+; RV64IZHINXMIN-NEXT:    fabs.s a2, a0
+; RV64IZHINXMIN-NEXT:    flt.s a1, a2, a1
+; RV64IZHINXMIN-NEXT:    beqz a1, .LBB17_2
+; RV64IZHINXMIN-NEXT:  # %bb.1:
+; RV64IZHINXMIN-NEXT:    fcvt.w.s a1, a0, rtz
+; RV64IZHINXMIN-NEXT:    fcvt.s.w a1, a1, rtz
+; RV64IZHINXMIN-NEXT:    fsgnj.s a0, a1, a0
+; RV64IZHINXMIN-NEXT:  .LBB17_2:
+; RV64IZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; RV64IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV64IZHINXMIN-NEXT:    fcvt.l.s a0, a0, rtz
+; RV64IZHINXMIN-NEXT:    ret
   %a = call half @llvm.trunc.f16(half %x)
   %b = fptosi half %a to i16
   ret i16 %b
 }
 
 define signext i32 @test_trunc_si32(half %x) {
 ; CHECKIZFH-LABEL: test_trunc_si32:
 ; CHECKIZFH:       # %bb.0:
 ; CHECKIZFH-NEXT:    fcvt.w.h a0, fa0, rtz
 ; CHECKIZFH-NEXT:    ret
 ;
+; CHECKIZHINX-LABEL: test_trunc_si32:
+; CHECKIZHINX:       # %bb.0:
+; CHECKIZHINX-NEXT:    lui a1, %hi(.LCPI18_0)
+; CHECKIZHINX-NEXT:    lh a1, %lo(.LCPI18_0)(a1)
+; CHECKIZHINX-NEXT:    fabs.h a2, a0
+; CHECKIZHINX-NEXT:    flt.h a1, a2, a1
+; CHECKIZHINX-NEXT:    beqz a1, .LBB18_2
+; CHECKIZHINX-NEXT:  # %bb.1:
+; CHECKIZHINX-NEXT:    fcvt.w.h a1, a0, rtz
+; CHECKIZHINX-NEXT:    fcvt.h.w a1, a1, rtz
+; CHECKIZHINX-NEXT:    fsgnj.h a0, a1, a0
+; CHECKIZHINX-NEXT:  .LBB18_2:
+; CHECKIZHINX-NEXT:    fcvt.w.h a0, a0, rtz
+; CHECKIZHINX-NEXT:    ret
+;
 ; CHECKIZFHMIN-LABEL: test_trunc_si32:
 ; CHECKIZFHMIN:       # %bb.0:
 ; CHECKIZFHMIN-NEXT:    fcvt.s.h fa5, fa0
 ; CHECKIZFHMIN-NEXT:    lui a0, 307200
 ; CHECKIZFHMIN-NEXT:    fmv.w.x fa4, a0
 ; CHECKIZFHMIN-NEXT:    fabs.s fa3, fa5
 ; CHECKIZFHMIN-NEXT:    flt.s a0, fa3, fa4
 ; CHECKIZFHMIN-NEXT:    beqz a0, .LBB18_2
 ; CHECKIZFHMIN-NEXT:  # %bb.1:
 ; CHECKIZFHMIN-NEXT:    fcvt.w.s a0, fa5, rtz
 ; CHECKIZFHMIN-NEXT:    fcvt.s.w fa4, a0, rtz
 ; CHECKIZFHMIN-NEXT:    fsgnj.s fa5, fa4, fa5
 ; CHECKIZFHMIN-NEXT:  .LBB18_2:
 ; CHECKIZFHMIN-NEXT:    fcvt.h.s fa5, fa5
 ; CHECKIZFHMIN-NEXT:    fcvt.s.h fa5, fa5
 ; CHECKIZFHMIN-NEXT:    fcvt.w.s a0, fa5, rtz
 ; CHECKIZFHMIN-NEXT:    ret
+;
+; CHECKIZHINXMIN-LABEL: test_trunc_si32:
+; CHECKIZHINXMIN:       # %bb.0:
+; CHECKIZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECKIZHINXMIN-NEXT:    lui a1, 307200
+; CHECKIZHINXMIN-NEXT:    fabs.s a2, a0
+; CHECKIZHINXMIN-NEXT:    flt.s a1, a2, a1
+; CHECKIZHINXMIN-NEXT:    beqz a1, .LBB18_2
+; CHECKIZHINXMIN-NEXT:  # %bb.1:
+; CHECKIZHINXMIN-NEXT:    fcvt.w.s a1, a0, rtz
+; CHECKIZHINXMIN-NEXT:    fcvt.s.w a1, a1, rtz
+; CHECKIZHINXMIN-NEXT:    fsgnj.s a0, a1, a0
+; CHECKIZHINXMIN-NEXT:  .LBB18_2:
+; CHECKIZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; CHECKIZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECKIZHINXMIN-NEXT:    fcvt.w.s a0, a0, rtz
+; CHECKIZHINXMIN-NEXT:    ret
   %a = call half @llvm.trunc.f16(half %x)
   %b = fptosi half %a to i32
   ret i32 %b
 }
 
 define i64 @test_trunc_si64(half %x) {
 ; RV32IZFH-LABEL: test_trunc_si64:
 ; RV32IZFH:       # %bb.0:

 ; RV32IZFH-NEXT:    addi sp, sp, 16
 ; RV32IZFH-NEXT:    ret
 ;
 ; RV64IZFH-LABEL: test_trunc_si64:
 ; RV64IZFH:       # %bb.0:
 ; RV64IZFH-NEXT:    fcvt.l.h a0, fa0, rtz
 ; RV64IZFH-NEXT:    ret
 ;
+; RV32IZHINX-LABEL: test_trunc_si64:
+; RV32IZHINX:       # %bb.0:
+; RV32IZHINX-NEXT:    addi sp, sp, -16
+; RV32IZHINX-NEXT:    .cfi_def_cfa_offset 16
+; RV32IZHINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZHINX-NEXT:    .cfi_offset ra, -4
+; RV32IZHINX-NEXT:    lui a1, %hi(.LCPI19_0)
+; RV32IZHINX-NEXT:    lh a1, %lo(.LCPI19_0)(a1)
+; RV32IZHINX-NEXT:    fabs.h a2, a0
+; RV32IZHINX-NEXT:    flt.h a1, a2, a1
+; RV32IZHINX-NEXT:    beqz a1, .LBB19_2
+; RV32IZHINX-NEXT:  # %bb.1:
+; RV32IZHINX-NEXT:    fcvt.w.h a1, a0, rtz
+; RV32IZHINX-NEXT:    fcvt.h.w a1, a1, rtz
+; RV32IZHINX-NEXT:    fsgnj.h a0, a1, a0
+; RV32IZHINX-NEXT:  .LBB19_2:
+; RV32IZHINX-NEXT:    call __fixhfdi@plt
+; RV32IZHINX-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZHINX-NEXT:    addi sp, sp, 16
+; RV32IZHINX-NEXT:    ret
+;
+; RV64IZHINX-LABEL: test_trunc_si64:
+; RV64IZHINX:       # %bb.0:
+; RV64IZHINX-NEXT:    lui a1, %hi(.LCPI19_0)
+; RV64IZHINX-NEXT:    lh a1, %lo(.LCPI19_0)(a1)
+; RV64IZHINX-NEXT:    fabs.h a2, a0
+; RV64IZHINX-NEXT:    flt.h a1, a2, a1
+; RV64IZHINX-NEXT:    beqz a1, .LBB19_2
+; RV64IZHINX-NEXT:  # %bb.1:
+; RV64IZHINX-NEXT:    fcvt.w.h a1, a0, rtz
+; RV64IZHINX-NEXT:    fcvt.h.w a1, a1, rtz
+; RV64IZHINX-NEXT:    fsgnj.h a0, a1, a0
+; RV64IZHINX-NEXT:  .LBB19_2:
+; RV64IZHINX-NEXT:    fcvt.l.h a0, a0, rtz
+; RV64IZHINX-NEXT:    ret
+;
 ; RV32IZFHMIN-LABEL: test_trunc_si64:
 ; RV32IZFHMIN:       # %bb.0:
 ; RV32IZFHMIN-NEXT:    fcvt.s.h fa5, fa0
 ; RV32IZFHMIN-NEXT:    lui a0, 307200
 ; RV32IZFHMIN-NEXT:    fmv.w.x fa4, a0
 ; RV32IZFHMIN-NEXT:    fabs.s fa3, fa5
 ; RV32IZFHMIN-NEXT:    flt.s a0, fa3, fa4
 ; RV32IZFHMIN-NEXT:    beqz a0, .LBB19_2

 ; RV64IZFHMIN-NEXT:    fcvt.w.s a0, fa5, rtz
 ; RV64IZFHMIN-NEXT:    fcvt.s.w fa4, a0, rtz
 ; RV64IZFHMIN-NEXT:    fsgnj.s fa5, fa4, fa5
 ; RV64IZFHMIN-NEXT:  .LBB19_2:
 ; RV64IZFHMIN-NEXT:    fcvt.h.s fa5, fa5
 ; RV64IZFHMIN-NEXT:    fcvt.s.h fa5, fa5
 ; RV64IZFHMIN-NEXT:    fcvt.l.s a0, fa5, rtz
 ; RV64IZFHMIN-NEXT:    ret
+;
+; RV32IZHINXMIN-LABEL: test_trunc_si64:
+; RV32IZHINXMIN:       # %bb.0:
+; RV32IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV32IZHINXMIN-NEXT:    lui a1, 307200
+; RV32IZHINXMIN-NEXT:    fabs.s a2, a0
+; RV32IZHINXMIN-NEXT:    flt.s a1, a2, a1
+; RV32IZHINXMIN-NEXT:    beqz a1, .LBB19_2
+; RV32IZHINXMIN-NEXT:  # %bb.1:
+; RV32IZHINXMIN-NEXT:    fcvt.w.s a1, a0, rtz
+; RV32IZHINXMIN-NEXT:    fcvt.s.w a1, a1, rtz
+; RV32IZHINXMIN-NEXT:    fsgnj.s a0, a1, a0
+; RV32IZHINXMIN-NEXT:  .LBB19_2:
+; RV32IZHINXMIN-NEXT:    addi sp, sp, -16
+; RV32IZHINXMIN-NEXT:    .cfi_def_cfa_offset 16
+; RV32IZHINXMIN-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZHINXMIN-NEXT:    .cfi_offset ra, -4
+; RV32IZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; RV32IZHINXMIN-NEXT:    call __fixhfdi@plt
+; RV32IZHINXMIN-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZHINXMIN-NEXT:    addi sp, sp, 16
+; RV32IZHINXMIN-NEXT:    ret
+;
+; RV64IZHINXMIN-LABEL: test_trunc_si64:
+; RV64IZHINXMIN:       # %bb.0:
+; RV64IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV64IZHINXMIN-NEXT:    lui a1, 307200
+; RV64IZHINXMIN-NEXT:    fabs.s a2, a0
+; RV64IZHINXMIN-NEXT:    flt.s a1, a2, a1
+; RV64IZHINXMIN-NEXT:    beqz a1, .LBB19_2
+; RV64IZHINXMIN-NEXT:  # %bb.1:
+; RV64IZHINXMIN-NEXT:    fcvt.w.s a1, a0, rtz
+; RV64IZHINXMIN-NEXT:    fcvt.s.w a1, a1, rtz
+; RV64IZHINXMIN-NEXT:    fsgnj.s a0, a1, a0
+; RV64IZHINXMIN-NEXT:  .LBB19_2:
+; RV64IZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; RV64IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV64IZHINXMIN-NEXT:    fcvt.l.s a0, a0, rtz
+; RV64IZHINXMIN-NEXT:    ret
   %a = call half @llvm.trunc.f16(half %x)
   %b = fptosi half %a to i64
   ret i64 %b
 }
 
 define zeroext i8 @test_trunc_ui8(half %x) {
 ; RV32IZFH-LABEL: test_trunc_ui8:
 ; RV32IZFH:       # %bb.0:
 ; RV32IZFH-NEXT:    fcvt.wu.h a0, fa0, rtz
 ; RV32IZFH-NEXT:    ret
 ;
 ; RV64IZFH-LABEL: test_trunc_ui8:
 ; RV64IZFH:       # %bb.0:
 ; RV64IZFH-NEXT:    fcvt.lu.h a0, fa0, rtz
 ; RV64IZFH-NEXT:    ret
 ;
+; RV32IZHINX-LABEL: test_trunc_ui8:
+; RV32IZHINX:       # %bb.0:
+; RV32IZHINX-NEXT:    lui a1, %hi(.LCPI20_0)
+; RV32IZHINX-NEXT:    lh a1, %lo(.LCPI20_0)(a1)
+; RV32IZHINX-NEXT:    fabs.h a2, a0
+; RV32IZHINX-NEXT:    flt.h a1, a2, a1
+; RV32IZHINX-NEXT:    beqz a1, .LBB20_2
+; RV32IZHINX-NEXT:  # %bb.1:
+; RV32IZHINX-NEXT:    fcvt.w.h a1, a0, rtz
+; RV32IZHINX-NEXT:    fcvt.h.w a1, a1, rtz
+; RV32IZHINX-NEXT:    fsgnj.h a0, a1, a0
+; RV32IZHINX-NEXT:  .LBB20_2:
+; RV32IZHINX-NEXT:    fcvt.wu.h a0, a0, rtz
+; RV32IZHINX-NEXT:    ret
+;
+; RV64IZHINX-LABEL: test_trunc_ui8:
+; RV64IZHINX:       # %bb.0:
+; RV64IZHINX-NEXT:    lui a1, %hi(.LCPI20_0)
+; RV64IZHINX-NEXT:    lh a1, %lo(.LCPI20_0)(a1)
+; RV64IZHINX-NEXT:    fabs.h a2, a0
+; RV64IZHINX-NEXT:    flt.h a1, a2, a1
+; RV64IZHINX-NEXT:    beqz a1, .LBB20_2
+; RV64IZHINX-NEXT:  # %bb.1:
+; RV64IZHINX-NEXT:    fcvt.w.h a1, a0, rtz
+; RV64IZHINX-NEXT:    fcvt.h.w a1, a1, rtz
+; RV64IZHINX-NEXT:    fsgnj.h a0, a1, a0
+; RV64IZHINX-NEXT:  .LBB20_2:
+; RV64IZHINX-NEXT:    fcvt.lu.h a0, a0, rtz
+; RV64IZHINX-NEXT:    ret
+;
 ; RV32IZFHMIN-LABEL: test_trunc_ui8:
 ; RV32IZFHMIN:       # %bb.0:
 ; RV32IZFHMIN-NEXT:    fcvt.s.h fa5, fa0
 ; RV32IZFHMIN-NEXT:    lui a0, 307200
 ; RV32IZFHMIN-NEXT:    fmv.w.x fa4, a0
 ; RV32IZFHMIN-NEXT:    fabs.s fa3, fa5
 ; RV32IZFHMIN-NEXT:    flt.s a0, fa3, fa4
 ; RV32IZFHMIN-NEXT:    beqz a0, .LBB20_2

 ; RV64IZFHMIN-NEXT:    fcvt.w.s a0, fa5, rtz
 ; RV64IZFHMIN-NEXT:    fcvt.s.w fa4, a0, rtz
 ; RV64IZFHMIN-NEXT:    fsgnj.s fa5, fa4, fa5
 ; RV64IZFHMIN-NEXT:  .LBB20_2:
 ; RV64IZFHMIN-NEXT:    fcvt.h.s fa5, fa5
 ; RV64IZFHMIN-NEXT:    fcvt.s.h fa5, fa5
 ; RV64IZFHMIN-NEXT:    fcvt.lu.s a0, fa5, rtz
 ; RV64IZFHMIN-NEXT:    ret
+;
+; RV32IZHINXMIN-LABEL: test_trunc_ui8:
+; RV32IZHINXMIN:       # %bb.0:
+; RV32IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV32IZHINXMIN-NEXT:    lui a1, 307200
+; RV32IZHINXMIN-NEXT:    fabs.s a2, a0
+; RV32IZHINXMIN-NEXT:    flt.s a1, a2, a1
+; RV32IZHINXMIN-NEXT:    beqz a1, .LBB20_2
+; RV32IZHINXMIN-NEXT:  # %bb.1:
+; RV32IZHINXMIN-NEXT:    fcvt.w.s a1, a0, rtz
+; RV32IZHINXMIN-NEXT:    fcvt.s.w a1, a1, rtz
+; RV32IZHINXMIN-NEXT:    fsgnj.s a0, a1, a0
+; RV32IZHINXMIN-NEXT:  .LBB20_2:
+; RV32IZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; RV32IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV32IZHINXMIN-NEXT:    fcvt.wu.s a0, a0, rtz
+; RV32IZHINXMIN-NEXT:    ret
+;
+; RV64IZHINXMIN-LABEL: test_trunc_ui8:
+; RV64IZHINXMIN:       # %bb.0:
+; RV64IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV64IZHINXMIN-NEXT:    lui a1, 307200
+; RV64IZHINXMIN-NEXT:    fabs.s a2, a0
+; RV64IZHINXMIN-NEXT:    flt.s a1, a2, a1
+; RV64IZHINXMIN-NEXT:    beqz a1, .LBB20_2
+; RV64IZHINXMIN-NEXT:  # %bb.1:
+; RV64IZHINXMIN-NEXT:    fcvt.w.s a1, a0, rtz
+; RV64IZHINXMIN-NEXT:    fcvt.s.w a1, a1, rtz
+; RV64IZHINXMIN-NEXT:    fsgnj.s a0, a1, a0
+; RV64IZHINXMIN-NEXT:  .LBB20_2:
+; RV64IZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; RV64IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV64IZHINXMIN-NEXT:    fcvt.lu.s a0, a0, rtz
+; RV64IZHINXMIN-NEXT:    ret
   %a = call half @llvm.trunc.f16(half %x)
   %b = fptoui half %a to i8
   ret i8 %b
 }
 
 define zeroext i16 @test_trunc_ui16(half %x) {
 ; RV32IZFH-LABEL: test_trunc_ui16:
 ; RV32IZFH:       # %bb.0:
 ; RV32IZFH-NEXT:    fcvt.wu.h a0, fa0, rtz
 ; RV32IZFH-NEXT:    ret
 ;
 ; RV64IZFH-LABEL: test_trunc_ui16:
 ; RV64IZFH:       # %bb.0:
 ; RV64IZFH-NEXT:    fcvt.lu.h a0, fa0, rtz
 ; RV64IZFH-NEXT:    ret
 ;
+; RV32IZHINX-LABEL: test_trunc_ui16:
+; RV32IZHINX:       # %bb.0:
+; RV32IZHINX-NEXT:    lui a1, %hi(.LCPI21_0)
+; RV32IZHINX-NEXT:    lh a1, %lo(.LCPI21_0)(a1)
+; RV32IZHINX-NEXT:    fabs.h a2, a0
+; RV32IZHINX-NEXT:    flt.h a1, a2, a1
+; RV32IZHINX-NEXT:    beqz a1, .LBB21_2
+; RV32IZHINX-NEXT:  # %bb.1:
+; RV32IZHINX-NEXT:    fcvt.w.h a1, a0, rtz
+; RV32IZHINX-NEXT:    fcvt.h.w a1, a1, rtz
+; RV32IZHINX-NEXT:    fsgnj.h a0, a1, a0
+; RV32IZHINX-NEXT:  .LBB21_2:
+; RV32IZHINX-NEXT:    fcvt.wu.h a0, a0, rtz
+; RV32IZHINX-NEXT:    ret
+;
+; RV64IZHINX-LABEL: test_trunc_ui16:
+; RV64IZHINX:       # %bb.0:
+; RV64IZHINX-NEXT:    lui a1, %hi(.LCPI21_0)
+; RV64IZHINX-NEXT:    lh a1, %lo(.LCPI21_0)(a1)
+; RV64IZHINX-NEXT:    fabs.h a2, a0
+; RV64IZHINX-NEXT:    flt.h a1, a2, a1
+; RV64IZHINX-NEXT:    beqz a1, .LBB21_2
+; RV64IZHINX-NEXT:  # %bb.1:
+; RV64IZHINX-NEXT:    fcvt.w.h a1, a0, rtz
+; RV64IZHINX-NEXT:    fcvt.h.w a1, a1, rtz
+; RV64IZHINX-NEXT:    fsgnj.h a0, a1, a0
+; RV64IZHINX-NEXT:  .LBB21_2:
+; RV64IZHINX-NEXT:    fcvt.lu.h a0, a0, rtz
+; RV64IZHINX-NEXT:    ret
+;
 ; RV32IZFHMIN-LABEL: test_trunc_ui16:
 ; RV32IZFHMIN:       # %bb.0:
 ; RV32IZFHMIN-NEXT:    fcvt.s.h fa5, fa0
 ; RV32IZFHMIN-NEXT:    lui a0, 307200
 ; RV32IZFHMIN-NEXT:    fmv.w.x fa4, a0
 ; RV32IZFHMIN-NEXT:    fabs.s fa3, fa5
 ; RV32IZFHMIN-NEXT:    flt.s a0, fa3, fa4
 ; RV32IZFHMIN-NEXT:    beqz a0, .LBB21_2

 ; RV64IZFHMIN-NEXT:    fcvt.w.s a0, fa5, rtz
 ; RV64IZFHMIN-NEXT:    fcvt.s.w fa4, a0, rtz
 ; RV64IZFHMIN-NEXT:    fsgnj.s fa5, fa4, fa5
 ; RV64IZFHMIN-NEXT:  .LBB21_2:
 ; RV64IZFHMIN-NEXT:    fcvt.h.s fa5, fa5
 ; RV64IZFHMIN-NEXT:    fcvt.s.h fa5, fa5
 ; RV64IZFHMIN-NEXT:    fcvt.lu.s a0, fa5, rtz
 ; RV64IZFHMIN-NEXT:    ret
+;
+; RV32IZHINXMIN-LABEL: test_trunc_ui16:
+; RV32IZHINXMIN:       # %bb.0:
+; RV32IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV32IZHINXMIN-NEXT:    lui a1, 307200
+; RV32IZHINXMIN-NEXT:    fabs.s a2, a0
+; RV32IZHINXMIN-NEXT:    flt.s a1, a2, a1
+; RV32IZHINXMIN-NEXT:    beqz a1, .LBB21_2
+; RV32IZHINXMIN-NEXT:  # %bb.1:
+; RV32IZHINXMIN-NEXT:    fcvt.w.s a1, a0, rtz
+; RV32IZHINXMIN-NEXT:    fcvt.s.w a1, a1, rtz
+; RV32IZHINXMIN-NEXT:    fsgnj.s a0, a1, a0
+; RV32IZHINXMIN-NEXT:  .LBB21_2:
+; RV32IZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; RV32IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV32IZHINXMIN-NEXT:    fcvt.wu.s a0, a0, rtz
+; RV32IZHINXMIN-NEXT:    ret
+;
+; RV64IZHINXMIN-LABEL: test_trunc_ui16:
+; RV64IZHINXMIN:       # %bb.0:
+; RV64IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV64IZHINXMIN-NEXT:    lui a1, 307200
+; RV64IZHINXMIN-NEXT:    fabs.s a2, a0
+; RV64IZHINXMIN-NEXT:    flt.s a1, a2, a1
+; RV64IZHINXMIN-NEXT:    beqz a1, .LBB21_2
+; RV64IZHINXMIN-NEXT:  # %bb.1:
+; RV64IZHINXMIN-NEXT:    fcvt.w.s a1, a0, rtz
+; RV64IZHINXMIN-NEXT:    fcvt.s.w a1, a1, rtz
+; RV64IZHINXMIN-NEXT:    fsgnj.s a0, a1, a0
+; RV64IZHINXMIN-NEXT:  .LBB21_2:
+; RV64IZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; RV64IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV64IZHINXMIN-NEXT:    fcvt.lu.s a0, a0, rtz
+; RV64IZHINXMIN-NEXT:    ret
   %a = call half @llvm.trunc.f16(half %x)
   %b = fptoui half %a to i16
   ret i16 %b
 }
 
 define signext i32 @test_trunc_ui32(half %x) {
 ; CHECKIZFH-LABEL: test_trunc_ui32:
 ; CHECKIZFH:       # %bb.0:
 ; CHECKIZFH-NEXT:    fcvt.wu.h a0, fa0, rtz
 ; CHECKIZFH-NEXT:    ret
 ;
+; CHECKIZHINX-LABEL: test_trunc_ui32:
+; CHECKIZHINX:       # %bb.0:
+; CHECKIZHINX-NEXT:    lui a1, %hi(.LCPI22_0)
+; CHECKIZHINX-NEXT:    lh a1, %lo(.LCPI22_0)(a1)
+; CHECKIZHINX-NEXT:    fabs.h a2, a0
+; CHECKIZHINX-NEXT:    flt.h a1, a2, a1
+; CHECKIZHINX-NEXT:    beqz a1, .LBB22_2
+; CHECKIZHINX-NEXT:  # %bb.1:
+; CHECKIZHINX-NEXT:    fcvt.w.h a1, a0, rtz
+; CHECKIZHINX-NEXT:    fcvt.h.w a1, a1, rtz
+; CHECKIZHINX-NEXT:    fsgnj.h a0, a1, a0
+; CHECKIZHINX-NEXT:  .LBB22_2:
+; CHECKIZHINX-NEXT:    fcvt.wu.h a0, a0, rtz
+; CHECKIZHINX-NEXT:    ret
+;
 ; CHECKIZFHMIN-LABEL: test_trunc_ui32:
 ; CHECKIZFHMIN:       # %bb.0:
 ; CHECKIZFHMIN-NEXT:    fcvt.s.h fa5, fa0
 ; CHECKIZFHMIN-NEXT:    lui a0, 307200
 ; CHECKIZFHMIN-NEXT:    fmv.w.x fa4, a0
 ; CHECKIZFHMIN-NEXT:    fabs.s fa3, fa5
 ; CHECKIZFHMIN-NEXT:    flt.s a0, fa3, fa4
 ; CHECKIZFHMIN-NEXT:    beqz a0, .LBB22_2
 ; CHECKIZFHMIN-NEXT:  # %bb.1:
 ; CHECKIZFHMIN-NEXT:    fcvt.w.s a0, fa5, rtz
 ; CHECKIZFHMIN-NEXT:    fcvt.s.w fa4, a0, rtz
 ; CHECKIZFHMIN-NEXT:    fsgnj.s fa5, fa4, fa5
 ; CHECKIZFHMIN-NEXT:  .LBB22_2:
 ; CHECKIZFHMIN-NEXT:    fcvt.h.s fa5, fa5
 ; CHECKIZFHMIN-NEXT:    fcvt.s.h fa5, fa5
 ; CHECKIZFHMIN-NEXT:    fcvt.wu.s a0, fa5, rtz
 ; CHECKIZFHMIN-NEXT:    ret
+;
+; CHECKIZHINXMIN-LABEL: test_trunc_ui32:
+; CHECKIZHINXMIN:       # %bb.0:
+; CHECKIZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECKIZHINXMIN-NEXT:    lui a1, 307200
+; CHECKIZHINXMIN-NEXT:    fabs.s a2, a0
+; CHECKIZHINXMIN-NEXT:    flt.s a1, a2, a1
+; CHECKIZHINXMIN-NEXT:    beqz a1, .LBB22_2
+; CHECKIZHINXMIN-NEXT:  # %bb.1:
+; CHECKIZHINXMIN-NEXT:    fcvt.w.s a1, a0, rtz
+; CHECKIZHINXMIN-NEXT:    fcvt.s.w a1, a1, rtz
+; CHECKIZHINXMIN-NEXT:    fsgnj.s a0, a1, a0
+; CHECKIZHINXMIN-NEXT:  .LBB22_2:
+; CHECKIZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; CHECKIZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECKIZHINXMIN-NEXT:    fcvt.wu.s a0, a0, rtz
+; CHECKIZHINXMIN-NEXT:    ret
   %a = call half @llvm.trunc.f16(half %x)
   %b = fptoui half %a to i32
   ret i32 %b
 }
 
 define i64 @test_trunc_ui64(half %x) {
 ; RV32IZFH-LABEL: test_trunc_ui64:
 ; RV32IZFH:       # %bb.0:

 ; RV32IZFH-NEXT:    addi sp, sp, 16
 ; RV32IZFH-NEXT:    ret
 ;
 ; RV64IZFH-LABEL: test_trunc_ui64:
 ; RV64IZFH:       # %bb.0:
 ; RV64IZFH-NEXT:    fcvt.lu.h a0, fa0, rtz
 ; RV64IZFH-NEXT:    ret
 ;
+; RV32IZHINX-LABEL: test_trunc_ui64:
+; RV32IZHINX:       # %bb.0:
+; RV32IZHINX-NEXT:    addi sp, sp, -16
+; RV32IZHINX-NEXT:    .cfi_def_cfa_offset 16
+; RV32IZHINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZHINX-NEXT:    .cfi_offset ra, -4
+; RV32IZHINX-NEXT:    lui a1, %hi(.LCPI23_0)
+; RV32IZHINX-NEXT:    lh a1, %lo(.LCPI23_0)(a1)
+; RV32IZHINX-NEXT:    fabs.h a2, a0
+; RV32IZHINX-NEXT:    flt.h a1, a2, a1
+; RV32IZHINX-NEXT:    beqz a1, .LBB23_2
+; RV32IZHINX-NEXT:  # %bb.1:
+; RV32IZHINX-NEXT:    fcvt.w.h a1, a0, rtz
+; RV32IZHINX-NEXT:    fcvt.h.w a1, a1, rtz
+; RV32IZHINX-NEXT:    fsgnj.h a0, a1, a0
+; RV32IZHINX-NEXT:  .LBB23_2:
+; RV32IZHINX-NEXT:    call __fixunshfdi@plt
+; RV32IZHINX-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZHINX-NEXT:    addi sp, sp, 16
+; RV32IZHINX-NEXT:    ret
+;
+; RV64IZHINX-LABEL: test_trunc_ui64:
+; RV64IZHINX:       # %bb.0:
+; RV64IZHINX-NEXT:    lui a1, %hi(.LCPI23_0)
+; RV64IZHINX-NEXT:    lh a1, %lo(.LCPI23_0)(a1)
+; RV64IZHINX-NEXT:    fabs.h a2, a0
+; RV64IZHINX-NEXT:    flt.h a1, a2, a1
+; RV64IZHINX-NEXT:    beqz a1, .LBB23_2
+; RV64IZHINX-NEXT:  # %bb.1:
+; RV64IZHINX-NEXT:    fcvt.w.h a1, a0, rtz
+; RV64IZHINX-NEXT:    fcvt.h.w a1, a1, rtz
+; RV64IZHINX-NEXT:    fsgnj.h a0, a1, a0
+; RV64IZHINX-NEXT:  .LBB23_2:
+; RV64IZHINX-NEXT:    fcvt.lu.h a0, a0, rtz
+; RV64IZHINX-NEXT:    ret
+;
 ; RV32IZFHMIN-LABEL: test_trunc_ui64:
 ; RV32IZFHMIN:       # %bb.0:
 ; RV32IZFHMIN-NEXT:    fcvt.s.h fa5, fa0
 ; RV32IZFHMIN-NEXT:    lui a0, 307200
 ; RV32IZFHMIN-NEXT:    fmv.w.x fa4, a0
 ; RV32IZFHMIN-NEXT:    fabs.s fa3, fa5
 ; RV32IZFHMIN-NEXT:    flt.s a0, fa3, fa4
 ; RV32IZFHMIN-NEXT:    beqz a0, .LBB23_2

 ; RV64IZFHMIN-NEXT:    fcvt.w.s a0, fa5, rtz
 ; RV64IZFHMIN-NEXT:    fcvt.s.w fa4, a0, rtz
 ; RV64IZFHMIN-NEXT:    fsgnj.s fa5, fa4, fa5
 ; RV64IZFHMIN-NEXT:  .LBB23_2:
 ; RV64IZFHMIN-NEXT:    fcvt.h.s fa5, fa5
 ; RV64IZFHMIN-NEXT:    fcvt.s.h fa5, fa5
 ; RV64IZFHMIN-NEXT:    fcvt.lu.s a0, fa5, rtz
 ; RV64IZFHMIN-NEXT:    ret
+;
+; RV32IZHINXMIN-LABEL: test_trunc_ui64:
+; RV32IZHINXMIN:       # %bb.0:
+; RV32IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV32IZHINXMIN-NEXT:    lui a1, 307200
+; RV32IZHINXMIN-NEXT:    fabs.s a2, a0
+; RV32IZHINXMIN-NEXT:    flt.s a1, a2, a1
+; RV32IZHINXMIN-NEXT:    beqz a1, .LBB23_2
+; RV32IZHINXMIN-NEXT:  # %bb.1:
+; RV32IZHINXMIN-NEXT:    fcvt.w.s a1, a0, rtz
+; RV32IZHINXMIN-NEXT:    fcvt.s.w a1, a1, rtz
+; RV32IZHINXMIN-NEXT:    fsgnj.s a0, a1, a0
+; RV32IZHINXMIN-NEXT:  .LBB23_2:
+; RV32IZHINXMIN-NEXT:    addi sp, sp, -16
+; RV32IZHINXMIN-NEXT:    .cfi_def_cfa_offset 16
+; RV32IZHINXMIN-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZHINXMIN-NEXT:    .cfi_offset ra, -4
+; RV32IZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; RV32IZHINXMIN-NEXT:    call __fixunshfdi@plt
+; RV32IZHINXMIN-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZHINXMIN-NEXT:    addi sp, sp, 16
+; RV32IZHINXMIN-NEXT:    ret
+;
+; RV64IZHINXMIN-LABEL: test_trunc_ui64:
+; RV64IZHINXMIN:       # %bb.0:
+; RV64IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV64IZHINXMIN-NEXT:    lui a1, 307200
+; RV64IZHINXMIN-NEXT:    fabs.s a2, a0
+; RV64IZHINXMIN-NEXT:    flt.s a1, a2, a1
+; RV64IZHINXMIN-NEXT:    beqz a1, .LBB23_2
+; RV64IZHINXMIN-NEXT:  # %bb.1:
+; RV64IZHINXMIN-NEXT:    fcvt.w.s a1, a0, rtz
+; RV64IZHINXMIN-NEXT:    fcvt.s.w a1, a1, rtz
+; RV64IZHINXMIN-NEXT:    fsgnj.s a0, a1, a0
+; RV64IZHINXMIN-NEXT:  .LBB23_2:
+; RV64IZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; RV64IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV64IZHINXMIN-NEXT:    fcvt.lu.s a0, a0, rtz
+; RV64IZHINXMIN-NEXT:    ret
   %a = call half @llvm.trunc.f16(half %x)
   %b = fptoui half %a to i64
   ret i64 %b
 }
 
 define signext i8 @test_round_si8(half %x) {
 ; RV32IZFH-LABEL: test_round_si8:
 ; RV32IZFH:       # %bb.0:
 ; RV32IZFH-NEXT:    fcvt.w.h a0, fa0, rmm
 ; RV32IZFH-NEXT:    ret
 ;
 ; RV64IZFH-LABEL: test_round_si8:
 ; RV64IZFH:       # %bb.0:
 ; RV64IZFH-NEXT:    fcvt.l.h a0, fa0, rmm
 ; RV64IZFH-NEXT:    ret
 ;
+; RV32IZHINX-LABEL: test_round_si8:
+; RV32IZHINX:       # %bb.0:
+; RV32IZHINX-NEXT:    lui a1, %hi(.LCPI24_0)
+; RV32IZHINX-NEXT:    lh a1, %lo(.LCPI24_0)(a1)
+; RV32IZHINX-NEXT:    fabs.h a2, a0
+; RV32IZHINX-NEXT:    flt.h a1, a2, a1
+; RV32IZHINX-NEXT:    beqz a1, .LBB24_2
+; RV32IZHINX-NEXT:  # %bb.1:
+; RV32IZHINX-NEXT:    fcvt.w.h a1, a0, rmm
+; RV32IZHINX-NEXT:    fcvt.h.w a1, a1, rmm
+; RV32IZHINX-NEXT:    fsgnj.h a0, a1, a0
+; RV32IZHINX-NEXT:  .LBB24_2:
+; RV32IZHINX-NEXT:    fcvt.w.h a0, a0, rtz
+; RV32IZHINX-NEXT:    ret
+;
+; RV64IZHINX-LABEL: test_round_si8:
+; RV64IZHINX:       # %bb.0:
+; RV64IZHINX-NEXT:    lui a1, %hi(.LCPI24_0)
+; RV64IZHINX-NEXT:    lh a1, %lo(.LCPI24_0)(a1)
+; RV64IZHINX-NEXT:    fabs.h a2, a0
+; RV64IZHINX-NEXT:    flt.h a1, a2, a1
+; RV64IZHINX-NEXT:    beqz a1, .LBB24_2
+; RV64IZHINX-NEXT:  # %bb.1:
+; RV64IZHINX-NEXT:    fcvt.w.h a1, a0, rmm
+; RV64IZHINX-NEXT:    fcvt.h.w a1, a1, rmm
+; RV64IZHINX-NEXT:    fsgnj.h a0, a1, a0
+; RV64IZHINX-NEXT:  .LBB24_2:
+; RV64IZHINX-NEXT:    fcvt.l.h a0, a0, rtz
+; RV64IZHINX-NEXT:    ret
+;
 ; RV32IZFHMIN-LABEL: test_round_si8:
 ; RV32IZFHMIN:       # %bb.0:
 ; RV32IZFHMIN-NEXT:    fcvt.s.h fa5, fa0
 ; RV32IZFHMIN-NEXT:    lui a0, 307200
 ; RV32IZFHMIN-NEXT:    fmv.w.x fa4, a0
 ; RV32IZFHMIN-NEXT:    fabs.s fa3, fa5
 ; RV32IZFHMIN-NEXT:    flt.s a0, fa3, fa4
 ; RV32IZFHMIN-NEXT:    beqz a0, .LBB24_2

 ; RV64IZFHMIN-NEXT:    fcvt.w.s a0, fa5, rmm
 ; RV64IZFHMIN-NEXT:    fcvt.s.w fa4, a0, rmm
 ; RV64IZFHMIN-NEXT:    fsgnj.s fa5, fa4, fa5
 ; RV64IZFHMIN-NEXT:  .LBB24_2:
 ; RV64IZFHMIN-NEXT:    fcvt.h.s fa5, fa5
 ; RV64IZFHMIN-NEXT:    fcvt.s.h fa5, fa5
 ; RV64IZFHMIN-NEXT:    fcvt.l.s a0, fa5, rtz
 ; RV64IZFHMIN-NEXT:    ret
+;
+; RV32IZHINXMIN-LABEL: test_round_si8:
+; RV32IZHINXMIN:       # %bb.0:
+; RV32IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV32IZHINXMIN-NEXT:    lui a1, 307200
+; RV32IZHINXMIN-NEXT:    fabs.s a2, a0
+; RV32IZHINXMIN-NEXT:    flt.s a1, a2, a1
+; RV32IZHINXMIN-NEXT:    beqz a1, .LBB24_2
+; RV32IZHINXMIN-NEXT:  # %bb.1:
+; RV32IZHINXMIN-NEXT:    fcvt.w.s a1, a0, rmm
+; RV32IZHINXMIN-NEXT:    fcvt.s.w a1, a1, rmm
+; RV32IZHINXMIN-NEXT:    fsgnj.s a0, a1, a0
+; RV32IZHINXMIN-NEXT:  .LBB24_2:
+; RV32IZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; RV32IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV32IZHINXMIN-NEXT:    fcvt.w.s a0, a0, rtz
+; RV32IZHINXMIN-NEXT:    ret
+;
+; RV64IZHINXMIN-LABEL: test_round_si8:
+; RV64IZHINXMIN:       # %bb.0:
+; RV64IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV64IZHINXMIN-NEXT:    lui a1, 307200
+; RV64IZHINXMIN-NEXT:    fabs.s a2, a0
+; RV64IZHINXMIN-NEXT:    flt.s a1, a2, a1
+; RV64IZHINXMIN-NEXT:    beqz a1, .LBB24_2
+; RV64IZHINXMIN-NEXT:  # %bb.1:
+; RV64IZHINXMIN-NEXT:    fcvt.w.s a1, a0, rmm
+; RV64IZHINXMIN-NEXT:    fcvt.s.w a1, a1, rmm
+; RV64IZHINXMIN-NEXT:    fsgnj.s a0, a1, a0
+; RV64IZHINXMIN-NEXT:  .LBB24_2:
+; RV64IZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; RV64IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV64IZHINXMIN-NEXT:    fcvt.l.s a0, a0, rtz
+; RV64IZHINXMIN-NEXT:    ret
   %a = call half @llvm.round.f16(half %x)
   %b = fptosi half %a to i8
   ret i8 %b
 }
 
 define signext i16 @test_round_si16(half %x) {
 ; RV32IZFH-LABEL: test_round_si16:
 ; RV32IZFH:       # %bb.0:
 ; RV32IZFH-NEXT:    fcvt.w.h a0, fa0, rmm
 ; RV32IZFH-NEXT:    ret
 ;
 ; RV64IZFH-LABEL: test_round_si16:
 ; RV64IZFH:       # %bb.0:
 ; RV64IZFH-NEXT:    fcvt.l.h a0, fa0, rmm
 ; RV64IZFH-NEXT:    ret
 ;
+; RV32IZHINX-LABEL: test_round_si16:
+; RV32IZHINX:       # %bb.0:
+; RV32IZHINX-NEXT:    lui a1, %hi(.LCPI25_0)
+; RV32IZHINX-NEXT:    lh a1, %lo(.LCPI25_0)(a1)
+; RV32IZHINX-NEXT:    fabs.h a2, a0
+; RV32IZHINX-NEXT:    flt.h a1, a2, a1
+; RV32IZHINX-NEXT:    beqz a1, .LBB25_2
+; RV32IZHINX-NEXT:  # %bb.1:
+; RV32IZHINX-NEXT:    fcvt.w.h a1, a0, rmm
+; RV32IZHINX-NEXT:    fcvt.h.w a1, a1, rmm
+; RV32IZHINX-NEXT:    fsgnj.h a0, a1, a0
+; RV32IZHINX-NEXT:  .LBB25_2:
+; RV32IZHINX-NEXT:    fcvt.w.h a0, a0, rtz
+; RV32IZHINX-NEXT:    ret
+;
+; RV64IZHINX-LABEL: test_round_si16:
+; RV64IZHINX:       # %bb.0:
+; RV64IZHINX-NEXT:    lui a1, %hi(.LCPI25_0)
+; RV64IZHINX-NEXT:    lh a1, %lo(.LCPI25_0)(a1)
+; RV64IZHINX-NEXT:    fabs.h a2, a0
+; RV64IZHINX-NEXT:    flt.h a1, a2, a1
+; RV64IZHINX-NEXT:    beqz a1, .LBB25_2
+; RV64IZHINX-NEXT:  # %bb.1:
+; RV64IZHINX-NEXT:    fcvt.w.h a1, a0, rmm
+; RV64IZHINX-NEXT:    fcvt.h.w a1, a1, rmm
+; RV64IZHINX-NEXT:    fsgnj.h a0, a1, a0
+; RV64IZHINX-NEXT:  .LBB25_2:
+; RV64IZHINX-NEXT:    fcvt.l.h a0, a0, rtz
+; RV64IZHINX-NEXT:    ret
+;
 ; RV32IZFHMIN-LABEL: test_round_si16:
 ; RV32IZFHMIN:       # %bb.0:
 ; RV32IZFHMIN-NEXT:    fcvt.s.h fa5, fa0
 ; RV32IZFHMIN-NEXT:    lui a0, 307200
 ; RV32IZFHMIN-NEXT:    fmv.w.x fa4, a0
 ; RV32IZFHMIN-NEXT:    fabs.s fa3, fa5
 ; RV32IZFHMIN-NEXT:    flt.s a0, fa3, fa4
 ; RV32IZFHMIN-NEXT:    beqz a0, .LBB25_2

 ; RV64IZFHMIN-NEXT:    fcvt.w.s a0, fa5, rmm
 ; RV64IZFHMIN-NEXT:    fcvt.s.w fa4, a0, rmm
 ; RV64IZFHMIN-NEXT:    fsgnj.s fa5, fa4, fa5
 ; RV64IZFHMIN-NEXT:  .LBB25_2:
 ; RV64IZFHMIN-NEXT:    fcvt.h.s fa5, fa5
 ; RV64IZFHMIN-NEXT:    fcvt.s.h fa5, fa5
 ; RV64IZFHMIN-NEXT:    fcvt.l.s a0, fa5, rtz
 ; RV64IZFHMIN-NEXT:    ret
+;
+; RV32IZHINXMIN-LABEL: test_round_si16:
+; RV32IZHINXMIN:       # %bb.0:
+; RV32IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV32IZHINXMIN-NEXT:    lui a1, 307200
+; RV32IZHINXMIN-NEXT:    fabs.s a2, a0
+; RV32IZHINXMIN-NEXT:    flt.s a1, a2, a1
+; RV32IZHINXMIN-NEXT:    beqz a1, .LBB25_2
+; RV32IZHINXMIN-NEXT:  # %bb.1:
+; RV32IZHINXMIN-NEXT:    fcvt.w.s a1, a0, rmm
+; RV32IZHINXMIN-NEXT:    fcvt.s.w a1, a1, rmm
+; RV32IZHINXMIN-NEXT:    fsgnj.s a0, a1, a0
+; RV32IZHINXMIN-NEXT:  .LBB25_2:
+; RV32IZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; RV32IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV32IZHINXMIN-NEXT:    fcvt.w.s a0, a0, rtz
+; RV32IZHINXMIN-NEXT:    ret
+;
+; RV64IZHINXMIN-LABEL: test_round_si16:
+; RV64IZHINXMIN:       # %bb.0:
+; RV64IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV64IZHINXMIN-NEXT:    lui a1, 307200
+; RV64IZHINXMIN-NEXT:    fabs.s a2, a0
+; RV64IZHINXMIN-NEXT:    flt.s a1, a2, a1
+; RV64IZHINXMIN-NEXT:    beqz a1, .LBB25_2
+; RV64IZHINXMIN-NEXT:  # %bb.1:
+; RV64IZHINXMIN-NEXT:    fcvt.w.s a1, a0, rmm
+; RV64IZHINXMIN-NEXT:    fcvt.s.w a1, a1, rmm
+; RV64IZHINXMIN-NEXT:    fsgnj.s a0, a1, a0
+; RV64IZHINXMIN-NEXT:  .LBB25_2:
+; RV64IZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; RV64IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV64IZHINXMIN-NEXT:    fcvt.l.s a0, a0, rtz
+; RV64IZHINXMIN-NEXT:    ret
   %a = call half @llvm.round.f16(half %x)
   %b = fptosi half %a to i16
   ret i16 %b
 }
 
 define signext i32 @test_round_si32(half %x) {
 ; CHECKIZFH-LABEL: test_round_si32:
 ; CHECKIZFH:       # %bb.0:
 ; CHECKIZFH-NEXT:    fcvt.w.h a0, fa0, rmm
 ; CHECKIZFH-NEXT:    ret
 ;
+; CHECKIZHINX-LABEL: test_round_si32:
+; CHECKIZHINX:       # %bb.0:
+; CHECKIZHINX-NEXT:    lui a1, %hi(.LCPI26_0)
+; CHECKIZHINX-NEXT:    lh a1, %lo(.LCPI26_0)(a1)
+; CHECKIZHINX-NEXT:    fabs.h a2, a0
+; CHECKIZHINX-NEXT:    flt.h a1, a2, a1
+; CHECKIZHINX-NEXT:    beqz a1, .LBB26_2
+; CHECKIZHINX-NEXT:  # %bb.1:
+; CHECKIZHINX-NEXT:    fcvt.w.h a1, a0, rmm
+; CHECKIZHINX-NEXT:    fcvt.h.w a1, a1, rmm
+; CHECKIZHINX-NEXT:    fsgnj.h a0, a1, a0
+; CHECKIZHINX-NEXT:  .LBB26_2:
+; CHECKIZHINX-NEXT:    fcvt.w.h a0, a0, rtz
+; CHECKIZHINX-NEXT:    ret
+;
 ; CHECKIZFHMIN-LABEL: test_round_si32:
 ; CHECKIZFHMIN:       # %bb.0:
 ; CHECKIZFHMIN-NEXT:    fcvt.s.h fa5, fa0
 ; CHECKIZFHMIN-NEXT:    lui a0, 307200
 ; CHECKIZFHMIN-NEXT:    fmv.w.x fa4, a0
 ; CHECKIZFHMIN-NEXT:    fabs.s fa3, fa5
 ; CHECKIZFHMIN-NEXT:    flt.s a0, fa3, fa4
 ; CHECKIZFHMIN-NEXT:    beqz a0, .LBB26_2
 ; CHECKIZFHMIN-NEXT:  # %bb.1:
 ; CHECKIZFHMIN-NEXT:    fcvt.w.s a0, fa5, rmm
 ; CHECKIZFHMIN-NEXT:    fcvt.s.w fa4, a0, rmm
 ; CHECKIZFHMIN-NEXT:    fsgnj.s fa5, fa4, fa5
 ; CHECKIZFHMIN-NEXT:  .LBB26_2:
 ; CHECKIZFHMIN-NEXT:    fcvt.h.s fa5, fa5
 ; CHECKIZFHMIN-NEXT:    fcvt.s.h fa5, fa5
 ; CHECKIZFHMIN-NEXT:    fcvt.w.s a0, fa5, rtz
 ; CHECKIZFHMIN-NEXT:    ret
+;
+; CHECKIZHINXMIN-LABEL: test_round_si32:
+; CHECKIZHINXMIN:       # %bb.0:
+; CHECKIZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECKIZHINXMIN-NEXT:    lui a1, 307200
+; CHECKIZHINXMIN-NEXT:    fabs.s a2, a0
+; CHECKIZHINXMIN-NEXT:    flt.s a1, a2, a1
+; CHECKIZHINXMIN-NEXT:    beqz a1, .LBB26_2
+; CHECKIZHINXMIN-NEXT:  # %bb.1:
+; CHECKIZHINXMIN-NEXT:    fcvt.w.s a1, a0, rmm
+; CHECKIZHINXMIN-NEXT:    fcvt.s.w a1, a1, rmm
+; CHECKIZHINXMIN-NEXT:    fsgnj.s a0, a1, a0
+; CHECKIZHINXMIN-NEXT:  .LBB26_2:
+; CHECKIZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; CHECKIZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECKIZHINXMIN-NEXT:    fcvt.w.s a0, a0, rtz
+; CHECKIZHINXMIN-NEXT:    ret
   %a = call half @llvm.round.f16(half %x)
   %b = fptosi half %a to i32
   ret i32 %b
 }
 
 define i64 @test_round_si64(half %x) {
 ; RV32IZFH-LABEL: test_round_si64:
 ; RV32IZFH:       # %bb.0:

 ; RV32IZFH-NEXT:    addi sp, sp, 16
 ; RV32IZFH-NEXT:    ret
 ;
 ; RV64IZFH-LABEL: test_round_si64:
 ; RV64IZFH:       # %bb.0:
 ; RV64IZFH-NEXT:    fcvt.l.h a0, fa0, rmm
 ; RV64IZFH-NEXT:    ret
 ;
+; RV32IZHINX-LABEL: test_round_si64:
+; RV32IZHINX:       # %bb.0:
+; RV32IZHINX-NEXT:    addi sp, sp, -16
+; RV32IZHINX-NEXT:    .cfi_def_cfa_offset 16
+; RV32IZHINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZHINX-NEXT:    .cfi_offset ra, -4
+; RV32IZHINX-NEXT:    lui a1, %hi(.LCPI27_0)
+; RV32IZHINX-NEXT:    lh a1, %lo(.LCPI27_0)(a1)
+; RV32IZHINX-NEXT:    fabs.h a2, a0
+; RV32IZHINX-NEXT:    flt.h a1, a2, a1
+; RV32IZHINX-NEXT:    beqz a1, .LBB27_2
+; RV32IZHINX-NEXT:  # %bb.1:
+; RV32IZHINX-NEXT:    fcvt.w.h a1, a0, rmm
+; RV32IZHINX-NEXT:    fcvt.h.w a1, a1, rmm
+; RV32IZHINX-NEXT:    fsgnj.h a0, a1, a0
+; RV32IZHINX-NEXT:  .LBB27_2:
+; RV32IZHINX-NEXT:    call __fixhfdi@plt
+; RV32IZHINX-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZHINX-NEXT:    addi sp, sp, 16
+; RV32IZHINX-NEXT:    ret
+;
+; RV64IZHINX-LABEL: test_round_si64:
+; RV64IZHINX:       # %bb.0:
+; RV64IZHINX-NEXT:    lui a1, %hi(.LCPI27_0)
+; RV64IZHINX-NEXT:    lh a1, %lo(.LCPI27_0)(a1)
+; RV64IZHINX-NEXT:    fabs.h a2, a0
+; RV64IZHINX-NEXT:    flt.h a1, a2, a1
+; RV64IZHINX-NEXT:    beqz a1, .LBB27_2
+; RV64IZHINX-NEXT:  # %bb.1:
+; RV64IZHINX-NEXT:    fcvt.w.h a1, a0, rmm
+; RV64IZHINX-NEXT:    fcvt.h.w a1, a1, rmm
+; RV64IZHINX-NEXT:    fsgnj.h a0, a1, a0
+; RV64IZHINX-NEXT:  .LBB27_2:
+; RV64IZHINX-NEXT:    fcvt.l.h a0, a0, rtz
+; RV64IZHINX-NEXT:    ret
+;
 ; RV32IZFHMIN-LABEL: test_round_si64:
 ; RV32IZFHMIN:       # %bb.0:
 ; RV32IZFHMIN-NEXT:    fcvt.s.h fa5, fa0
 ; RV32IZFHMIN-NEXT:    lui a0, 307200
 ; RV32IZFHMIN-NEXT:    fmv.w.x fa4, a0
 ; RV32IZFHMIN-NEXT:    fabs.s fa3, fa5
 ; RV32IZFHMIN-NEXT:    flt.s a0, fa3, fa4
 ; RV32IZFHMIN-NEXT:    beqz a0, .LBB27_2

 ; RV64IZFHMIN-NEXT:    fcvt.w.s a0, fa5, rmm
 ; RV64IZFHMIN-NEXT:    fcvt.s.w fa4, a0, rmm
 ; RV64IZFHMIN-NEXT:    fsgnj.s fa5, fa4, fa5
 ; RV64IZFHMIN-NEXT:  .LBB27_2:
 ; RV64IZFHMIN-NEXT:    fcvt.h.s fa5, fa5
 ; RV64IZFHMIN-NEXT:    fcvt.s.h fa5, fa5
 ; RV64IZFHMIN-NEXT:    fcvt.l.s a0, fa5, rtz
 ; RV64IZFHMIN-NEXT:    ret
+;
+; RV32IZHINXMIN-LABEL: test_round_si64:
+; RV32IZHINXMIN:       # %bb.0:
+; RV32IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV32IZHINXMIN-NEXT:    lui a1, 307200
+; RV32IZHINXMIN-NEXT:    fabs.s a2, a0
+; RV32IZHINXMIN-NEXT:    flt.s a1, a2, a1
+; RV32IZHINXMIN-NEXT:    beqz a1, .LBB27_2
+; RV32IZHINXMIN-NEXT:  # %bb.1:
+; RV32IZHINXMIN-NEXT:    fcvt.w.s a1, a0, rmm
+; RV32IZHINXMIN-NEXT:    fcvt.s.w a1, a1, rmm
+; RV32IZHINXMIN-NEXT:    fsgnj.s a0, a1, a0
+; RV32IZHINXMIN-NEXT:  .LBB27_2:
+; RV32IZHINXMIN-NEXT:    addi sp, sp, -16
+; RV32IZHINXMIN-NEXT:    .cfi_def_cfa_offset 16
+; RV32IZHINXMIN-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZHINXMIN-NEXT:    .cfi_offset ra, -4
+; RV32IZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; RV32IZHINXMIN-NEXT:    call __fixhfdi@plt
+; RV32IZHINXMIN-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZHINXMIN-NEXT:    addi sp, sp, 16
+; RV32IZHINXMIN-NEXT:    ret
+;
+; RV64IZHINXMIN-LABEL: test_round_si64:
+; RV64IZHINXMIN:       # %bb.0:
+; RV64IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV64IZHINXMIN-NEXT:    lui a1, 307200
+; RV64IZHINXMIN-NEXT:    fabs.s a2, a0
+; RV64IZHINXMIN-NEXT:    flt.s a1, a2, a1
+; RV64IZHINXMIN-NEXT:    beqz a1, .LBB27_2
+; RV64IZHINXMIN-NEXT:  # %bb.1:
+; RV64IZHINXMIN-NEXT:    fcvt.w.s a1, a0, rmm
+; RV64IZHINXMIN-NEXT:    fcvt.s.w a1, a1, rmm
+; RV64IZHINXMIN-NEXT:    fsgnj.s a0, a1, a0
+; RV64IZHINXMIN-NEXT:  .LBB27_2:
+; RV64IZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; RV64IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV64IZHINXMIN-NEXT:    fcvt.l.s a0, a0, rtz
+; RV64IZHINXMIN-NEXT:    ret
   %a = call half @llvm.round.f16(half %x)
   %b = fptosi half %a to i64
   ret i64 %b
 }
 
 define zeroext i8 @test_round_ui8(half %x) {
 ; RV32IZFH-LABEL: test_round_ui8:
 ; RV32IZFH:       # %bb.0:
 ; RV32IZFH-NEXT:    fcvt.wu.h a0, fa0, rmm
 ; RV32IZFH-NEXT:    ret
 ;
 ; RV64IZFH-LABEL: test_round_ui8:
 ; RV64IZFH:       # %bb.0:
 ; RV64IZFH-NEXT:    fcvt.lu.h a0, fa0, rmm
 ; RV64IZFH-NEXT:    ret
 ;
+; RV32IZHINX-LABEL: test_round_ui8:
+; RV32IZHINX:       # %bb.0:
+; RV32IZHINX-NEXT:    lui a1, %hi(.LCPI28_0)
+; RV32IZHINX-NEXT:    lh a1, %lo(.LCPI28_0)(a1)
+; RV32IZHINX-NEXT:    fabs.h a2, a0
+; RV32IZHINX-NEXT:    flt.h a1, a2, a1
+; RV32IZHINX-NEXT:    beqz a1, .LBB28_2
+; RV32IZHINX-NEXT:  # %bb.1:
+; RV32IZHINX-NEXT:    fcvt.w.h a1, a0, rmm
+; RV32IZHINX-NEXT:    fcvt.h.w a1, a1, rmm
+; RV32IZHINX-NEXT:    fsgnj.h a0, a1, a0
+; RV32IZHINX-NEXT:  .LBB28_2:
+; RV32IZHINX-NEXT:    fcvt.wu.h a0, a0, rtz
+; RV32IZHINX-NEXT:    ret
+;
+; RV64IZHINX-LABEL: test_round_ui8:
+; RV64IZHINX:       # %bb.0:
+; RV64IZHINX-NEXT:    lui a1, %hi(.LCPI28_0)
+; RV64IZHINX-NEXT:    lh a1, %lo(.LCPI28_0)(a1)
+; RV64IZHINX-NEXT:    fabs.h a2, a0
+; RV64IZHINX-NEXT:    flt.h a1, a2, a1
+; RV64IZHINX-NEXT:    beqz a1, .LBB28_2
+; RV64IZHINX-NEXT:  # %bb.1:
+; RV64IZHINX-NEXT:    fcvt.w.h a1, a0, rmm
+; RV64IZHINX-NEXT:    fcvt.h.w a1, a1, rmm
+; RV64IZHINX-NEXT:    fsgnj.h a0, a1, a0
+; RV64IZHINX-NEXT:  .LBB28_2:
+; RV64IZHINX-NEXT:    fcvt.lu.h a0, a0, rtz
+; RV64IZHINX-NEXT:    ret
+;
 ; RV32IZFHMIN-LABEL: test_round_ui8:
 ; RV32IZFHMIN:       # %bb.0:
 ; RV32IZFHMIN-NEXT:    fcvt.s.h fa5, fa0
 ; RV32IZFHMIN-NEXT:    lui a0, 307200
 ; RV32IZFHMIN-NEXT:    fmv.w.x fa4, a0
 ; RV32IZFHMIN-NEXT:    fabs.s fa3, fa5
 ; RV32IZFHMIN-NEXT:    flt.s a0, fa3, fa4
 ; RV32IZFHMIN-NEXT:    beqz a0, .LBB28_2

 ; RV64IZFHMIN-NEXT:    fcvt.w.s a0, fa5, rmm
 ; RV64IZFHMIN-NEXT:    fcvt.s.w fa4, a0, rmm
 ; RV64IZFHMIN-NEXT:    fsgnj.s fa5, fa4, fa5
 ; RV64IZFHMIN-NEXT:  .LBB28_2:
 ; RV64IZFHMIN-NEXT:    fcvt.h.s fa5, fa5
 ; RV64IZFHMIN-NEXT:    fcvt.s.h fa5, fa5
 ; RV64IZFHMIN-NEXT:    fcvt.lu.s a0, fa5, rtz
 ; RV64IZFHMIN-NEXT:    ret
+;
+; RV32IZHINXMIN-LABEL: test_round_ui8:
+; RV32IZHINXMIN:       # %bb.0:
+; RV32IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV32IZHINXMIN-NEXT:    lui a1, 307200
+; RV32IZHINXMIN-NEXT:    fabs.s a2, a0
+; RV32IZHINXMIN-NEXT:    flt.s a1, a2, a1
+; RV32IZHINXMIN-NEXT:    beqz a1, .LBB28_2
+; RV32IZHINXMIN-NEXT:  # %bb.1:
+; RV32IZHINXMIN-NEXT:    fcvt.w.s a1, a0, rmm
+; RV32IZHINXMIN-NEXT:    fcvt.s.w a1, a1, rmm
+; RV32IZHINXMIN-NEXT:    fsgnj.s a0, a1, a0
+; RV32IZHINXMIN-NEXT:  .LBB28_2:
+; RV32IZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; RV32IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV32IZHINXMIN-NEXT:    fcvt.wu.s a0, a0, rtz
+; RV32IZHINXMIN-NEXT:    ret
+;
+; RV64IZHINXMIN-LABEL: test_round_ui8:
+; RV64IZHINXMIN:       # %bb.0:
+; RV64IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV64IZHINXMIN-NEXT:    lui a1, 307200
+; RV64IZHINXMIN-NEXT:    fabs.s a2, a0
+; RV64IZHINXMIN-NEXT:    flt.s a1, a2, a1
+; RV64IZHINXMIN-NEXT:    beqz a1, .LBB28_2
+; RV64IZHINXMIN-NEXT:  # %bb.1:
+; RV64IZHINXMIN-NEXT:    fcvt.w.s a1, a0, rmm
+; RV64IZHINXMIN-NEXT:    fcvt.s.w a1, a1, rmm
+; RV64IZHINXMIN-NEXT:    fsgnj.s a0, a1, a0
+; RV64IZHINXMIN-NEXT:  .LBB28_2:
+; RV64IZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; RV64IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV64IZHINXMIN-NEXT:    fcvt.lu.s a0, a0, rtz
+; RV64IZHINXMIN-NEXT:    ret
   %a = call half @llvm.round.f16(half %x)
   %b = fptoui half %a to i8
   ret i8 %b
 }
 
 define zeroext i16 @test_round_ui16(half %x) {
 ; RV32IZFH-LABEL: test_round_ui16:
 ; RV32IZFH:       # %bb.0:
 ; RV32IZFH-NEXT:    fcvt.wu.h a0, fa0, rmm
 ; RV32IZFH-NEXT:    ret
 ;
 ; RV64IZFH-LABEL: test_round_ui16:
 ; RV64IZFH:       # %bb.0:
 ; RV64IZFH-NEXT:    fcvt.lu.h a0, fa0, rmm
 ; RV64IZFH-NEXT:    ret
 ;
+; RV32IZHINX-LABEL: test_round_ui16:
+; RV32IZHINX:       # %bb.0:
+; RV32IZHINX-NEXT:    lui a1, %hi(.LCPI29_0)
+; RV32IZHINX-NEXT:    lh a1, %lo(.LCPI29_0)(a1)
+; RV32IZHINX-NEXT:    fabs.h a2, a0
+; RV32IZHINX-NEXT:    flt.h a1, a2, a1
+; RV32IZHINX-NEXT:    beqz a1, .LBB29_2
+; RV32IZHINX-NEXT:  # %bb.1:
+; RV32IZHINX-NEXT:    fcvt.w.h a1, a0, rmm
+; RV32IZHINX-NEXT:    fcvt.h.w a1, a1, rmm
+; RV32IZHINX-NEXT:    fsgnj.h a0, a1, a0
+; RV32IZHINX-NEXT:  .LBB29_2:
+; RV32IZHINX-NEXT:    fcvt.wu.h a0, a0, rtz
+; RV32IZHINX-NEXT:    ret
+;
+; RV64IZHINX-LABEL: test_round_ui16:
+; RV64IZHINX:       # %bb.0:
+; RV64IZHINX-NEXT:    lui a1, %hi(.LCPI29_0)
+; RV64IZHINX-NEXT:    lh a1, %lo(.LCPI29_0)(a1)
+; RV64IZHINX-NEXT:    fabs.h a2, a0
+; RV64IZHINX-NEXT:    flt.h a1, a2, a1
+; RV64IZHINX-NEXT:    beqz a1, .LBB29_2
+; RV64IZHINX-NEXT:  # %bb.1:
+; RV64IZHINX-NEXT:    fcvt.w.h a1, a0, rmm
+; RV64IZHINX-NEXT:    fcvt.h.w a1, a1, rmm
+; RV64IZHINX-NEXT:    fsgnj.h a0, a1, a0
+; RV64IZHINX-NEXT:  .LBB29_2:
+; RV64IZHINX-NEXT:    fcvt.lu.h a0, a0, rtz
+; RV64IZHINX-NEXT:    ret
+;
 ; RV32IZFHMIN-LABEL: test_round_ui16:
 ; RV32IZFHMIN:       # %bb.0:
 ; RV32IZFHMIN-NEXT:    fcvt.s.h fa5, fa0
 ; RV32IZFHMIN-NEXT:    lui a0, 307200
 ; RV32IZFHMIN-NEXT:    fmv.w.x fa4, a0
 ; RV32IZFHMIN-NEXT:    fabs.s fa3, fa5
 ; RV32IZFHMIN-NEXT:    flt.s a0, fa3, fa4
 ; RV32IZFHMIN-NEXT:    beqz a0, .LBB29_2

 ; RV64IZFHMIN-NEXT:    fcvt.w.s a0, fa5, rmm
 ; RV64IZFHMIN-NEXT:    fcvt.s.w fa4, a0, rmm
 ; RV64IZFHMIN-NEXT:    fsgnj.s fa5, fa4, fa5
 ; RV64IZFHMIN-NEXT:  .LBB29_2:
 ; RV64IZFHMIN-NEXT:    fcvt.h.s fa5, fa5
 ; RV64IZFHMIN-NEXT:    fcvt.s.h fa5, fa5
 ; RV64IZFHMIN-NEXT:    fcvt.lu.s a0, fa5, rtz
 ; RV64IZFHMIN-NEXT:    ret
+;
+; RV32IZHINXMIN-LABEL: test_round_ui16:
+; RV32IZHINXMIN:       # %bb.0:
+; RV32IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV32IZHINXMIN-NEXT:    lui a1, 307200
+; RV32IZHINXMIN-NEXT:    fabs.s a2, a0
+; RV32IZHINXMIN-NEXT:    flt.s a1, a2, a1
+; RV32IZHINXMIN-NEXT:    beqz a1, .LBB29_2
+; RV32IZHINXMIN-NEXT:  # %bb.1:
+; RV32IZHINXMIN-NEXT:    fcvt.w.s a1, a0, rmm
+; RV32IZHINXMIN-NEXT:    fcvt.s.w a1, a1, rmm
+; RV32IZHINXMIN-NEXT:    fsgnj.s a0, a1, a0
+; RV32IZHINXMIN-NEXT:  .LBB29_2:
+; RV32IZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; RV32IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV32IZHINXMIN-NEXT:    fcvt.wu.s a0, a0, rtz
+; RV32IZHINXMIN-NEXT:    ret
+;
+; RV64IZHINXMIN-LABEL: test_round_ui16:
+; RV64IZHINXMIN:       # %bb.0:
+; RV64IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV64IZHINXMIN-NEXT:    lui a1, 307200
+; RV64IZHINXMIN-NEXT:    fabs.s a2, a0
+; RV64IZHINXMIN-NEXT:    flt.s a1, a2, a1
+; RV64IZHINXMIN-NEXT:    beqz a1, .LBB29_2
+; RV64IZHINXMIN-NEXT:  # %bb.1:
+; RV64IZHINXMIN-NEXT:    fcvt.w.s a1, a0, rmm
+; RV64IZHINXMIN-NEXT:    fcvt.s.w a1, a1, rmm
+; RV64IZHINXMIN-NEXT:    fsgnj.s a0, a1, a0
+; RV64IZHINXMIN-NEXT:  .LBB29_2:
+; RV64IZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; RV64IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV64IZHINXMIN-NEXT:    fcvt.lu.s a0, a0, rtz
+; RV64IZHINXMIN-NEXT:    ret
   %a = call half @llvm.round.f16(half %x)
   %b = fptoui half %a to i16
   ret i16 %b
 }
 
 define signext i32 @test_round_ui32(half %x) {
 ; CHECKIZFH-LABEL: test_round_ui32:
 ; CHECKIZFH:       # %bb.0:
 ; CHECKIZFH-NEXT:    fcvt.wu.h a0, fa0, rmm
 ; CHECKIZFH-NEXT:    ret
 ;
+; CHECKIZHINX-LABEL: test_round_ui32:
+; CHECKIZHINX:       # %bb.0:
+; CHECKIZHINX-NEXT:    lui a1, %hi(.LCPI30_0)
+; CHECKIZHINX-NEXT:    lh a1, %lo(.LCPI30_0)(a1)
+; CHECKIZHINX-NEXT:    fabs.h a2, a0
+; CHECKIZHINX-NEXT:    flt.h a1, a2, a1
+; CHECKIZHINX-NEXT:    beqz a1, .LBB30_2
+; CHECKIZHINX-NEXT:  # %bb.1:
+; CHECKIZHINX-NEXT:    fcvt.w.h a1, a0, rmm
+; CHECKIZHINX-NEXT:    fcvt.h.w a1, a1, rmm
+; CHECKIZHINX-NEXT:    fsgnj.h a0, a1, a0
+; CHECKIZHINX-NEXT:  .LBB30_2:
+; CHECKIZHINX-NEXT:    fcvt.wu.h a0, a0, rtz
+; CHECKIZHINX-NEXT:    ret
+;
 ; CHECKIZFHMIN-LABEL: test_round_ui32:
 ; CHECKIZFHMIN:       # %bb.0:
 ; CHECKIZFHMIN-NEXT:    fcvt.s.h fa5, fa0
 ; CHECKIZFHMIN-NEXT:    lui a0, 307200
 ; CHECKIZFHMIN-NEXT:    fmv.w.x fa4, a0
 ; CHECKIZFHMIN-NEXT:    fabs.s fa3, fa5
 ; CHECKIZFHMIN-NEXT:    flt.s a0, fa3, fa4
 ; CHECKIZFHMIN-NEXT:    beqz a0, .LBB30_2
 ; CHECKIZFHMIN-NEXT:  # %bb.1:
 ; CHECKIZFHMIN-NEXT:    fcvt.w.s a0, fa5, rmm
 ; CHECKIZFHMIN-NEXT:    fcvt.s.w fa4, a0, rmm
 ; CHECKIZFHMIN-NEXT:    fsgnj.s fa5, fa4, fa5
 ; CHECKIZFHMIN-NEXT:  .LBB30_2:
 ; CHECKIZFHMIN-NEXT:    fcvt.h.s fa5, fa5
 ; CHECKIZFHMIN-NEXT:    fcvt.s.h fa5, fa5
 ; CHECKIZFHMIN-NEXT:    fcvt.wu.s a0, fa5, rtz
 ; CHECKIZFHMIN-NEXT:    ret
+;
+; CHECKIZHINXMIN-LABEL: test_round_ui32:
+; CHECKIZHINXMIN:       # %bb.0:
+; CHECKIZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECKIZHINXMIN-NEXT:    lui a1, 307200
+; CHECKIZHINXMIN-NEXT:    fabs.s a2, a0
+; CHECKIZHINXMIN-NEXT:    flt.s a1, a2, a1
+; CHECKIZHINXMIN-NEXT:    beqz a1, .LBB30_2
+; CHECKIZHINXMIN-NEXT:  # %bb.1:
+; CHECKIZHINXMIN-NEXT:    fcvt.w.s a1, a0, rmm
+; CHECKIZHINXMIN-NEXT:    fcvt.s.w a1, a1, rmm
+; CHECKIZHINXMIN-NEXT:    fsgnj.s a0, a1, a0
+; CHECKIZHINXMIN-NEXT:  .LBB30_2:
+; CHECKIZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; CHECKIZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECKIZHINXMIN-NEXT:    fcvt.wu.s a0, a0, rtz
+; CHECKIZHINXMIN-NEXT:    ret
   %a = call half @llvm.round.f16(half %x)
   %b = fptoui half %a to i32
   ret i32 %b
 }
 
 define i64 @test_round_ui64(half %x) {
 ; RV32IZFH-LABEL: test_round_ui64:
 ; RV32IZFH:       # %bb.0:

 ; RV32IZFH-NEXT:    addi sp, sp, 16
 ; RV32IZFH-NEXT:    ret
 ;
 ; RV64IZFH-LABEL: test_round_ui64:
 ; RV64IZFH:       # %bb.0:
 ; RV64IZFH-NEXT:    fcvt.lu.h a0, fa0, rmm
 ; RV64IZFH-NEXT:    ret
 ;
+; RV32IZHINX-LABEL: test_round_ui64:
+; RV32IZHINX:       # %bb.0:
+; RV32IZHINX-NEXT:    addi sp, sp, -16
+; RV32IZHINX-NEXT:    .cfi_def_cfa_offset 16
+; RV32IZHINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZHINX-NEXT:    .cfi_offset ra, -4
+; RV32IZHINX-NEXT:    lui a1, %hi(.LCPI31_0)
+; RV32IZHINX-NEXT:    lh a1, %lo(.LCPI31_0)(a1)
+; RV32IZHINX-NEXT:    fabs.h a2, a0
+; RV32IZHINX-NEXT:    flt.h a1, a2, a1
+; RV32IZHINX-NEXT:    beqz a1, .LBB31_2
+; RV32IZHINX-NEXT:  # %bb.1:
+; RV32IZHINX-NEXT:    fcvt.w.h a1, a0, rmm
+; RV32IZHINX-NEXT:    fcvt.h.w a1, a1, rmm
+; RV32IZHINX-NEXT:    fsgnj.h a0, a1, a0
+; RV32IZHINX-NEXT:  .LBB31_2:
+; RV32IZHINX-NEXT:    call __fixunshfdi@plt
+; RV32IZHINX-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZHINX-NEXT:    addi sp, sp, 16
+; RV32IZHINX-NEXT:    ret
+;
+; RV64IZHINX-LABEL: test_round_ui64:
+; RV64IZHINX:       # %bb.0:
+; RV64IZHINX-NEXT:    lui a1, %hi(.LCPI31_0)
+; RV64IZHINX-NEXT:    lh a1, %lo(.LCPI31_0)(a1)
+; RV64IZHINX-NEXT:    fabs.h a2, a0
+; RV64IZHINX-NEXT:    flt.h a1, a2, a1
+; RV64IZHINX-NEXT:    beqz a1, .LBB31_2
+; RV64IZHINX-NEXT:  # %bb.1:
+; RV64IZHINX-NEXT:    fcvt.w.h a1, a0, rmm
+; RV64IZHINX-NEXT:    fcvt.h.w a1, a1, rmm
+; RV64IZHINX-NEXT:    fsgnj.h a0, a1, a0
+; RV64IZHINX-NEXT:  .LBB31_2:
+; RV64IZHINX-NEXT:    fcvt.lu.h a0, a0, rtz
+; RV64IZHINX-NEXT:    ret
+;
 ; RV32IZFHMIN-LABEL: test_round_ui64:
 ; RV32IZFHMIN:       # %bb.0:
 ; RV32IZFHMIN-NEXT:    fcvt.s.h fa5, fa0
 ; RV32IZFHMIN-NEXT:    lui a0, 307200
 ; RV32IZFHMIN-NEXT:    fmv.w.x fa4, a0
 ; RV32IZFHMIN-NEXT:    fabs.s fa3, fa5
 ; RV32IZFHMIN-NEXT:    flt.s a0, fa3, fa4
 ; RV32IZFHMIN-NEXT:    beqz a0, .LBB31_2

 ; RV64IZFHMIN-NEXT:    fcvt.w.s a0, fa5, rmm
 ; RV64IZFHMIN-NEXT:    fcvt.s.w fa4, a0, rmm
 ; RV64IZFHMIN-NEXT:    fsgnj.s fa5, fa4, fa5
 ; RV64IZFHMIN-NEXT:  .LBB31_2:
 ; RV64IZFHMIN-NEXT:    fcvt.h.s fa5, fa5
 ; RV64IZFHMIN-NEXT:    fcvt.s.h fa5, fa5
 ; RV64IZFHMIN-NEXT:    fcvt.lu.s a0, fa5, rtz
 ; RV64IZFHMIN-NEXT:    ret
+;
+; RV32IZHINXMIN-LABEL: test_round_ui64:
+; RV32IZHINXMIN:       # %bb.0:
+; RV32IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV32IZHINXMIN-NEXT:    lui a1, 307200
+; RV32IZHINXMIN-NEXT:    fabs.s a2, a0
+; RV32IZHINXMIN-NEXT:    flt.s a1, a2, a1
+; RV32IZHINXMIN-NEXT:    beqz a1, .LBB31_2
+; RV32IZHINXMIN-NEXT:  # %bb.1:
+; RV32IZHINXMIN-NEXT:    fcvt.w.s a1, a0, rmm
+; RV32IZHINXMIN-NEXT:    fcvt.s.w a1, a1, rmm
+; RV32IZHINXMIN-NEXT:    fsgnj.s a0, a1, a0
+; RV32IZHINXMIN-NEXT:  .LBB31_2:
+; RV32IZHINXMIN-NEXT:    addi sp, sp, -16
+; RV32IZHINXMIN-NEXT:    .cfi_def_cfa_offset 16
+; RV32IZHINXMIN-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZHINXMIN-NEXT:    .cfi_offset ra, -4
+; RV32IZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; RV32IZHINXMIN-NEXT:    call __fixunshfdi@plt
+; RV32IZHINXMIN-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZHINXMIN-NEXT:    addi sp, sp, 16
+; RV32IZHINXMIN-NEXT:    ret
+;
+; RV64IZHINXMIN-LABEL: test_round_ui64:
+; RV64IZHINXMIN:       # %bb.0:
+; RV64IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV64IZHINXMIN-NEXT:    lui a1, 307200
+; RV64IZHINXMIN-NEXT:    fabs.s a2, a0
+; RV64IZHINXMIN-NEXT:    flt.s a1, a2, a1
+; RV64IZHINXMIN-NEXT:    beqz a1, .LBB31_2
+; RV64IZHINXMIN-NEXT:  # %bb.1:
+; RV64IZHINXMIN-NEXT:    fcvt.w.s a1, a0, rmm
+; RV64IZHINXMIN-NEXT:    fcvt.s.w a1, a1, rmm
+; RV64IZHINXMIN-NEXT:    fsgnj.s a0, a1, a0
+; RV64IZHINXMIN-NEXT:  .LBB31_2:
+; RV64IZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; RV64IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV64IZHINXMIN-NEXT:    fcvt.lu.s a0, a0, rtz
+; RV64IZHINXMIN-NEXT:    ret
   %a = call half @llvm.round.f16(half %x)
   %b = fptoui half %a to i64
   ret i64 %b
 }
 
 define signext i8 @test_roundeven_si8(half %x) {
 ; RV32IZFH-LABEL: test_roundeven_si8:
 ; RV32IZFH:       # %bb.0:
 ; RV32IZFH-NEXT:    fcvt.w.h a0, fa0, rne
 ; RV32IZFH-NEXT:    ret
 ;
 ; RV64IZFH-LABEL: test_roundeven_si8:
 ; RV64IZFH:       # %bb.0:
 ; RV64IZFH-NEXT:    fcvt.l.h a0, fa0, rne
 ; RV64IZFH-NEXT:    ret
 ;
+; RV32IZHINX-LABEL: test_roundeven_si8:
+; RV32IZHINX:       # %bb.0:
+; RV32IZHINX-NEXT:    lui a1, %hi(.LCPI32_0)
+; RV32IZHINX-NEXT:    lh a1, %lo(.LCPI32_0)(a1)
+; RV32IZHINX-NEXT:    fabs.h a2, a0
+; RV32IZHINX-NEXT:    flt.h a1, a2, a1
+; RV32IZHINX-NEXT:    beqz a1, .LBB32_2
+; RV32IZHINX-NEXT:  # %bb.1:
+; RV32IZHINX-NEXT:    fcvt.w.h a1, a0, rne
+; RV32IZHINX-NEXT:    fcvt.h.w a1, a1, rne
+; RV32IZHINX-NEXT:    fsgnj.h a0, a1, a0
+; RV32IZHINX-NEXT:  .LBB32_2:
+; RV32IZHINX-NEXT:    fcvt.w.h a0, a0, rtz
+; RV32IZHINX-NEXT:    ret
+;
+; RV64IZHINX-LABEL: test_roundeven_si8:
+; RV64IZHINX:       # %bb.0:
+; RV64IZHINX-NEXT:    lui a1, %hi(.LCPI32_0)
+; RV64IZHINX-NEXT:    lh a1, %lo(.LCPI32_0)(a1)
+; RV64IZHINX-NEXT:    fabs.h a2, a0
+; RV64IZHINX-NEXT:    flt.h a1, a2, a1
+; RV64IZHINX-NEXT:    beqz a1, .LBB32_2
+; RV64IZHINX-NEXT:  # %bb.1:
+; RV64IZHINX-NEXT:    fcvt.w.h a1, a0, rne
+; RV64IZHINX-NEXT:    fcvt.h.w a1, a1, rne
+; RV64IZHINX-NEXT:    fsgnj.h a0, a1, a0
+; RV64IZHINX-NEXT:  .LBB32_2:
+; RV64IZHINX-NEXT:    fcvt.l.h a0, a0, rtz
+; RV64IZHINX-NEXT:    ret
+;
 ; RV32IZFHMIN-LABEL: test_roundeven_si8:
 ; RV32IZFHMIN:       # %bb.0:
 ; RV32IZFHMIN-NEXT:    fcvt.s.h fa5, fa0
 ; RV32IZFHMIN-NEXT:    lui a0, 307200
 ; RV32IZFHMIN-NEXT:    fmv.w.x fa4, a0
 ; RV32IZFHMIN-NEXT:    fabs.s fa3, fa5
 ; RV32IZFHMIN-NEXT:    flt.s a0, fa3, fa4
 ; RV32IZFHMIN-NEXT:    beqz a0, .LBB32_2

 ; RV64IZFHMIN-NEXT:    fcvt.w.s a0, fa5, rne
 ; RV64IZFHMIN-NEXT:    fcvt.s.w fa4, a0, rne
 ; RV64IZFHMIN-NEXT:    fsgnj.s fa5, fa4, fa5
 ; RV64IZFHMIN-NEXT:  .LBB32_2:
 ; RV64IZFHMIN-NEXT:    fcvt.h.s fa5, fa5
 ; RV64IZFHMIN-NEXT:    fcvt.s.h fa5, fa5
 ; RV64IZFHMIN-NEXT:    fcvt.l.s a0, fa5, rtz
 ; RV64IZFHMIN-NEXT:    ret
+;
+; RV32IZHINXMIN-LABEL: test_roundeven_si8:
+; RV32IZHINXMIN:       # %bb.0:
+; RV32IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV32IZHINXMIN-NEXT:    lui a1, 307200
+; RV32IZHINXMIN-NEXT:    fabs.s a2, a0
+; RV32IZHINXMIN-NEXT:    flt.s a1, a2, a1
+; RV32IZHINXMIN-NEXT:    beqz a1, .LBB32_2
+; RV32IZHINXMIN-NEXT:  # %bb.1:
+; RV32IZHINXMIN-NEXT:    fcvt.w.s a1, a0, rne
+; RV32IZHINXMIN-NEXT:    fcvt.s.w a1, a1, rne
+; RV32IZHINXMIN-NEXT:    fsgnj.s a0, a1, a0
+; RV32IZHINXMIN-NEXT:  .LBB32_2:
+; RV32IZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; RV32IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV32IZHINXMIN-NEXT:    fcvt.w.s a0, a0, rtz
+; RV32IZHINXMIN-NEXT:    ret
+;
+; RV64IZHINXMIN-LABEL: test_roundeven_si8:
+; RV64IZHINXMIN:       # %bb.0:
+; RV64IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV64IZHINXMIN-NEXT:    lui a1, 307200
+; RV64IZHINXMIN-NEXT:    fabs.s a2, a0
+; RV64IZHINXMIN-NEXT:    flt.s a1, a2, a1
+; RV64IZHINXMIN-NEXT:    beqz a1, .LBB32_2
+; RV64IZHINXMIN-NEXT:  # %bb.1:
+; RV64IZHINXMIN-NEXT:    fcvt.w.s a1, a0, rne
+; RV64IZHINXMIN-NEXT:    fcvt.s.w a1, a1, rne
+; RV64IZHINXMIN-NEXT:    fsgnj.s a0, a1, a0
+; RV64IZHINXMIN-NEXT:  .LBB32_2:
+; RV64IZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; RV64IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV64IZHINXMIN-NEXT:    fcvt.l.s a0, a0, rtz
+; RV64IZHINXMIN-NEXT:    ret
   %a = call half @llvm.roundeven.f16(half %x)
   %b = fptosi half %a to i8
   ret i8 %b
 }
 
 define signext i16 @test_roundeven_si16(half %x) {
 ; RV32IZFH-LABEL: test_roundeven_si16:
 ; RV32IZFH:       # %bb.0:
 ; RV32IZFH-NEXT:    fcvt.w.h a0, fa0, rne
 ; RV32IZFH-NEXT:    ret
 ;
 ; RV64IZFH-LABEL: test_roundeven_si16:
 ; RV64IZFH:       # %bb.0:
 ; RV64IZFH-NEXT:    fcvt.l.h a0, fa0, rne
 ; RV64IZFH-NEXT:    ret
 ;
+; RV32IZHINX-LABEL: test_roundeven_si16:
+; RV32IZHINX:       # %bb.0:
+; RV32IZHINX-NEXT:    lui a1, %hi(.LCPI33_0)
+; RV32IZHINX-NEXT:    lh a1, %lo(.LCPI33_0)(a1)
+; RV32IZHINX-NEXT:    fabs.h a2, a0
+; RV32IZHINX-NEXT:    flt.h a1, a2, a1
+; RV32IZHINX-NEXT:    beqz a1, .LBB33_2
+; RV32IZHINX-NEXT:  # %bb.1:
+; RV32IZHINX-NEXT:    fcvt.w.h a1, a0, rne
+; RV32IZHINX-NEXT:    fcvt.h.w a1, a1, rne
+; RV32IZHINX-NEXT:    fsgnj.h a0, a1, a0
+; RV32IZHINX-NEXT:  .LBB33_2:
+; RV32IZHINX-NEXT:    fcvt.w.h a0, a0, rtz
+; RV32IZHINX-NEXT:    ret
+;
+; RV64IZHINX-LABEL: test_roundeven_si16:
+; RV64IZHINX:       # %bb.0:
+; RV64IZHINX-NEXT:    lui a1, %hi(.LCPI33_0)
+; RV64IZHINX-NEXT:    lh a1, %lo(.LCPI33_0)(a1)
+; RV64IZHINX-NEXT:    fabs.h a2, a0
+; RV64IZHINX-NEXT:    flt.h a1, a2, a1
+; RV64IZHINX-NEXT:    beqz a1, .LBB33_2
+; RV64IZHINX-NEXT:  # %bb.1:
+; RV64IZHINX-NEXT:    fcvt.w.h a1, a0, rne
+; RV64IZHINX-NEXT:    fcvt.h.w a1, a1, rne
+; RV64IZHINX-NEXT:    fsgnj.h a0, a1, a0
+; RV64IZHINX-NEXT:  .LBB33_2:
+; RV64IZHINX-NEXT:    fcvt.l.h a0, a0, rtz
+; RV64IZHINX-NEXT:    ret
+;
 ; RV32IZFHMIN-LABEL: test_roundeven_si16:
 ; RV32IZFHMIN:       # %bb.0:
 ; RV32IZFHMIN-NEXT:    fcvt.s.h fa5, fa0
 ; RV32IZFHMIN-NEXT:    lui a0, 307200
 ; RV32IZFHMIN-NEXT:    fmv.w.x fa4, a0
 ; RV32IZFHMIN-NEXT:    fabs.s fa3, fa5
 ; RV32IZFHMIN-NEXT:    flt.s a0, fa3, fa4
 ; RV32IZFHMIN-NEXT:    beqz a0, .LBB33_2

 ; RV64IZFHMIN-NEXT:    fcvt.w.s a0, fa5, rne
 ; RV64IZFHMIN-NEXT:    fcvt.s.w fa4, a0, rne
 ; RV64IZFHMIN-NEXT:    fsgnj.s fa5, fa4, fa5
 ; RV64IZFHMIN-NEXT:  .LBB33_2:
 ; RV64IZFHMIN-NEXT:    fcvt.h.s fa5, fa5
 ; RV64IZFHMIN-NEXT:    fcvt.s.h fa5, fa5
 ; RV64IZFHMIN-NEXT:    fcvt.l.s a0, fa5, rtz
 ; RV64IZFHMIN-NEXT:    ret
+;
+; RV32IZHINXMIN-LABEL: test_roundeven_si16:
+; RV32IZHINXMIN:       # %bb.0:
+; RV32IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV32IZHINXMIN-NEXT:    lui a1, 307200
+; RV32IZHINXMIN-NEXT:    fabs.s a2, a0
+; RV32IZHINXMIN-NEXT:    flt.s a1, a2, a1
+; RV32IZHINXMIN-NEXT:    beqz a1, .LBB33_2
+; RV32IZHINXMIN-NEXT:  # %bb.1:
+; RV32IZHINXMIN-NEXT:    fcvt.w.s a1, a0, rne
+; RV32IZHINXMIN-NEXT:    fcvt.s.w a1, a1, rne
+; RV32IZHINXMIN-NEXT:    fsgnj.s a0, a1, a0
+; RV32IZHINXMIN-NEXT:  .LBB33_2:
+; RV32IZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; RV32IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV32IZHINXMIN-NEXT:    fcvt.w.s a0, a0, rtz
+; RV32IZHINXMIN-NEXT:    ret
+;
+; RV64IZHINXMIN-LABEL: test_roundeven_si16:
+; RV64IZHINXMIN:       # %bb.0:
+; RV64IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV64IZHINXMIN-NEXT:    lui a1, 307200
+; RV64IZHINXMIN-NEXT:    fabs.s a2, a0
+; RV64IZHINXMIN-NEXT:    flt.s a1, a2, a1
+; RV64IZHINXMIN-NEXT:    beqz a1, .LBB33_2
+; RV64IZHINXMIN-NEXT:  # %bb.1:
+; RV64IZHINXMIN-NEXT:    fcvt.w.s a1, a0, rne
+; RV64IZHINXMIN-NEXT:    fcvt.s.w a1, a1, rne
+; RV64IZHINXMIN-NEXT:    fsgnj.s a0, a1, a0
+; RV64IZHINXMIN-NEXT:  .LBB33_2:
+; RV64IZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; RV64IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV64IZHINXMIN-NEXT:    fcvt.l.s a0, a0, rtz
+; RV64IZHINXMIN-NEXT:    ret
   %a = call half @llvm.roundeven.f16(half %x)
   %b = fptosi half %a to i16
   ret i16 %b
 }
 
 define signext i32 @test_roundeven_si32(half %x) {
 ; CHECKIZFH-LABEL: test_roundeven_si32:
 ; CHECKIZFH:       # %bb.0:
 ; CHECKIZFH-NEXT:    fcvt.w.h a0, fa0, rne
 ; CHECKIZFH-NEXT:    ret
 ;
+; CHECKIZHINX-LABEL: test_roundeven_si32:
+; CHECKIZHINX:       # %bb.0:
+; CHECKIZHINX-NEXT:    lui a1, %hi(.LCPI34_0)
+; CHECKIZHINX-NEXT:    lh a1, %lo(.LCPI34_0)(a1)
+; CHECKIZHINX-NEXT:    fabs.h a2, a0
+; CHECKIZHINX-NEXT:    flt.h a1, a2, a1
+; CHECKIZHINX-NEXT:    beqz a1, .LBB34_2
+; CHECKIZHINX-NEXT:  # %bb.1:
+; CHECKIZHINX-NEXT:    fcvt.w.h a1, a0, rne
+; CHECKIZHINX-NEXT:    fcvt.h.w a1, a1, rne
+; CHECKIZHINX-NEXT:    fsgnj.h a0, a1, a0
+; CHECKIZHINX-NEXT:  .LBB34_2:
+; CHECKIZHINX-NEXT:    fcvt.w.h a0, a0, rtz
+; CHECKIZHINX-NEXT:    ret
+;
 ; CHECKIZFHMIN-LABEL: test_roundeven_si32:
 ; CHECKIZFHMIN:       # %bb.0:
 ; CHECKIZFHMIN-NEXT:    fcvt.s.h fa5, fa0
 ; CHECKIZFHMIN-NEXT:    lui a0, 307200
 ; CHECKIZFHMIN-NEXT:    fmv.w.x fa4, a0
 ; CHECKIZFHMIN-NEXT:    fabs.s fa3, fa5
 ; CHECKIZFHMIN-NEXT:    flt.s a0, fa3, fa4
 ; CHECKIZFHMIN-NEXT:    beqz a0, .LBB34_2
 ; CHECKIZFHMIN-NEXT:  # %bb.1:
 ; CHECKIZFHMIN-NEXT:    fcvt.w.s a0, fa5, rne
 ; CHECKIZFHMIN-NEXT:    fcvt.s.w fa4, a0, rne
 ; CHECKIZFHMIN-NEXT:    fsgnj.s fa5, fa4, fa5
 ; CHECKIZFHMIN-NEXT:  .LBB34_2:
 ; CHECKIZFHMIN-NEXT:    fcvt.h.s fa5, fa5
 ; CHECKIZFHMIN-NEXT:    fcvt.s.h fa5, fa5
 ; CHECKIZFHMIN-NEXT:    fcvt.w.s a0, fa5, rtz
 ; CHECKIZFHMIN-NEXT:    ret
+;
+; CHECKIZHINXMIN-LABEL: test_roundeven_si32:
+; CHECKIZHINXMIN:       # %bb.0:
+; CHECKIZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECKIZHINXMIN-NEXT:    lui a1, 307200
+; CHECKIZHINXMIN-NEXT:    fabs.s a2, a0
+; CHECKIZHINXMIN-NEXT:    flt.s a1, a2, a1
+; CHECKIZHINXMIN-NEXT:    beqz a1, .LBB34_2
+; CHECKIZHINXMIN-NEXT:  # %bb.1:
+; CHECKIZHINXMIN-NEXT:    fcvt.w.s a1, a0, rne
+; CHECKIZHINXMIN-NEXT:    fcvt.s.w a1, a1, rne
+; CHECKIZHINXMIN-NEXT:    fsgnj.s a0, a1, a0
+; CHECKIZHINXMIN-NEXT:  .LBB34_2:
+; CHECKIZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; CHECKIZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECKIZHINXMIN-NEXT:    fcvt.w.s a0, a0, rtz
+; CHECKIZHINXMIN-NEXT:    ret
   %a = call half @llvm.roundeven.f16(half %x)
   %b = fptosi half %a to i32
   ret i32 %b
 }
 
 define i64 @test_roundeven_si64(half %x) {
 ; RV32IZFH-LABEL: test_roundeven_si64:
 ; RV32IZFH:       # %bb.0:

 ; RV32IZFH-NEXT:    addi sp, sp, 16
 ; RV32IZFH-NEXT:    ret
 ;
 ; RV64IZFH-LABEL: test_roundeven_si64:
 ; RV64IZFH:       # %bb.0:
 ; RV64IZFH-NEXT:    fcvt.l.h a0, fa0, rne
 ; RV64IZFH-NEXT:    ret
 ;
+; RV32IZHINX-LABEL: test_roundeven_si64:
+; RV32IZHINX:       # %bb.0:
+; RV32IZHINX-NEXT:    addi sp, sp, -16
+; RV32IZHINX-NEXT:    .cfi_def_cfa_offset 16
+; RV32IZHINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZHINX-NEXT:    .cfi_offset ra, -4
+; RV32IZHINX-NEXT:    lui a1, %hi(.LCPI35_0)
+; RV32IZHINX-NEXT:    lh a1, %lo(.LCPI35_0)(a1)
+; RV32IZHINX-NEXT:    fabs.h a2, a0
+; RV32IZHINX-NEXT:    flt.h a1, a2, a1
+; RV32IZHINX-NEXT:    beqz a1, .LBB35_2
+; RV32IZHINX-NEXT:  # %bb.1:
+; RV32IZHINX-NEXT:    fcvt.w.h a1, a0, rne
+; RV32IZHINX-NEXT:    fcvt.h.w a1, a1, rne
+; RV32IZHINX-NEXT:    fsgnj.h a0, a1, a0
+; RV32IZHINX-NEXT:  .LBB35_2:
+; RV32IZHINX-NEXT:    call __fixhfdi@plt
+; RV32IZHINX-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZHINX-NEXT:    addi sp, sp, 16
+; RV32IZHINX-NEXT:    ret
+;
+; RV64IZHINX-LABEL: test_roundeven_si64:
+; RV64IZHINX:       # %bb.0:
+; RV64IZHINX-NEXT:    lui a1, %hi(.LCPI35_0)
+; RV64IZHINX-NEXT:    lh a1, %lo(.LCPI35_0)(a1)
+; RV64IZHINX-NEXT:    fabs.h a2, a0
+; RV64IZHINX-NEXT:    flt.h a1, a2, a1
+; RV64IZHINX-NEXT:    beqz a1, .LBB35_2
+; RV64IZHINX-NEXT:  # %bb.1:
+; RV64IZHINX-NEXT:    fcvt.w.h a1, a0, rne
+; RV64IZHINX-NEXT:    fcvt.h.w a1, a1, rne
+; RV64IZHINX-NEXT:    fsgnj.h a0, a1, a0
+; RV64IZHINX-NEXT:  .LBB35_2:
+; RV64IZHINX-NEXT:    fcvt.l.h a0, a0, rtz
+; RV64IZHINX-NEXT:    ret
+;
 ; RV32IZFHMIN-LABEL: test_roundeven_si64:
 ; RV32IZFHMIN:       # %bb.0:
 ; RV32IZFHMIN-NEXT:    fcvt.s.h fa5, fa0
 ; RV32IZFHMIN-NEXT:    lui a0, 307200
 ; RV32IZFHMIN-NEXT:    fmv.w.x fa4, a0
 ; RV32IZFHMIN-NEXT:    fabs.s fa3, fa5
 ; RV32IZFHMIN-NEXT:    flt.s a0, fa3, fa4
 ; RV32IZFHMIN-NEXT:    beqz a0, .LBB35_2

 ; RV64IZFHMIN-NEXT:    fcvt.w.s a0, fa5, rne
 ; RV64IZFHMIN-NEXT:    fcvt.s.w fa4, a0, rne
 ; RV64IZFHMIN-NEXT:    fsgnj.s fa5, fa4, fa5
 ; RV64IZFHMIN-NEXT:  .LBB35_2:
 ; RV64IZFHMIN-NEXT:    fcvt.h.s fa5, fa5
 ; RV64IZFHMIN-NEXT:    fcvt.s.h fa5, fa5
 ; RV64IZFHMIN-NEXT:    fcvt.l.s a0, fa5, rtz
 ; RV64IZFHMIN-NEXT:    ret
+;
+; RV32IZHINXMIN-LABEL: test_roundeven_si64:
+; RV32IZHINXMIN:       # %bb.0:
+; RV32IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV32IZHINXMIN-NEXT:    lui a1, 307200
+; RV32IZHINXMIN-NEXT:    fabs.s a2, a0
+; RV32IZHINXMIN-NEXT:    flt.s a1, a2, a1
+; RV32IZHINXMIN-NEXT:    beqz a1, .LBB35_2
+; RV32IZHINXMIN-NEXT:  # %bb.1:
+; RV32IZHINXMIN-NEXT:    fcvt.w.s a1, a0, rne
+; RV32IZHINXMIN-NEXT:    fcvt.s.w a1, a1, rne
+; RV32IZHINXMIN-NEXT:    fsgnj.s a0, a1, a0
+; RV32IZHINXMIN-NEXT:  .LBB35_2:
+; RV32IZHINXMIN-NEXT:    addi sp, sp, -16
+; RV32IZHINXMIN-NEXT:    .cfi_def_cfa_offset 16
+; RV32IZHINXMIN-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZHINXMIN-NEXT:    .cfi_offset ra, -4
+; RV32IZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; RV32IZHINXMIN-NEXT:    call __fixhfdi@plt
+; RV32IZHINXMIN-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZHINXMIN-NEXT:    addi sp, sp, 16
+; RV32IZHINXMIN-NEXT:    ret
+;
+; RV64IZHINXMIN-LABEL: test_roundeven_si64:
+; RV64IZHINXMIN:       # %bb.0:
+; RV64IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV64IZHINXMIN-NEXT:    lui a1, 307200
+; RV64IZHINXMIN-NEXT:    fabs.s a2, a0
+; RV64IZHINXMIN-NEXT:    flt.s a1, a2, a1
+; RV64IZHINXMIN-NEXT:    beqz a1, .LBB35_2
+; RV64IZHINXMIN-NEXT:  # %bb.1:
+; RV64IZHINXMIN-NEXT:    fcvt.w.s a1, a0, rne
+; RV64IZHINXMIN-NEXT:    fcvt.s.w a1, a1, rne
+; RV64IZHINXMIN-NEXT:    fsgnj.s a0, a1, a0
+; RV64IZHINXMIN-NEXT:  .LBB35_2:
+; RV64IZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; RV64IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV64IZHINXMIN-NEXT:    fcvt.l.s a0, a0, rtz
+; RV64IZHINXMIN-NEXT:    ret
   %a = call half @llvm.roundeven.f16(half %x)
   %b = fptosi half %a to i64
   ret i64 %b
 }
 
 define zeroext i8 @test_roundeven_ui8(half %x) {
 ; RV32IZFH-LABEL: test_roundeven_ui8:
 ; RV32IZFH:       # %bb.0:
 ; RV32IZFH-NEXT:    fcvt.wu.h a0, fa0, rne
 ; RV32IZFH-NEXT:    ret
 ;
 ; RV64IZFH-LABEL: test_roundeven_ui8:
 ; RV64IZFH:       # %bb.0:
 ; RV64IZFH-NEXT:    fcvt.lu.h a0, fa0, rne
 ; RV64IZFH-NEXT:    ret
 ;
+; RV32IZHINX-LABEL: test_roundeven_ui8:
+; RV32IZHINX:       # %bb.0:
+; RV32IZHINX-NEXT:    lui a1, %hi(.LCPI36_0)
+; RV32IZHINX-NEXT:    lh a1, %lo(.LCPI36_0)(a1)
+; RV32IZHINX-NEXT:    fabs.h a2, a0
+; RV32IZHINX-NEXT:    flt.h a1, a2, a1
+; RV32IZHINX-NEXT:    beqz a1, .LBB36_2
+; RV32IZHINX-NEXT:  # %bb.1:
+; RV32IZHINX-NEXT:    fcvt.w.h a1, a0, rne
+; RV32IZHINX-NEXT:    fcvt.h.w a1, a1, rne
+; RV32IZHINX-NEXT:    fsgnj.h a0, a1, a0
+; RV32IZHINX-NEXT:  .LBB36_2:
+; RV32IZHINX-NEXT:    fcvt.wu.h a0, a0, rtz
+; RV32IZHINX-NEXT:    ret
+;
+; RV64IZHINX-LABEL: test_roundeven_ui8:
+; RV64IZHINX:       # %bb.0:
+; RV64IZHINX-NEXT:    lui a1, %hi(.LCPI36_0)
+; RV64IZHINX-NEXT:    lh a1, %lo(.LCPI36_0)(a1)
+; RV64IZHINX-NEXT:    fabs.h a2, a0
+; RV64IZHINX-NEXT:    flt.h a1, a2, a1
+; RV64IZHINX-NEXT:    beqz a1, .LBB36_2
+; RV64IZHINX-NEXT:  # %bb.1:
+; RV64IZHINX-NEXT:    fcvt.w.h a1, a0, rne
+; RV64IZHINX-NEXT:    fcvt.h.w a1, a1, rne
+; RV64IZHINX-NEXT:    fsgnj.h a0, a1, a0
+; RV64IZHINX-NEXT:  .LBB36_2:
+; RV64IZHINX-NEXT:    fcvt.lu.h a0, a0, rtz
+; RV64IZHINX-NEXT:    ret
+;
 ; RV32IZFHMIN-LABEL: test_roundeven_ui8:
 ; RV32IZFHMIN:       # %bb.0:
 ; RV32IZFHMIN-NEXT:    fcvt.s.h fa5, fa0
 ; RV32IZFHMIN-NEXT:    lui a0, 307200
 ; RV32IZFHMIN-NEXT:    fmv.w.x fa4, a0
 ; RV32IZFHMIN-NEXT:    fabs.s fa3, fa5
 ; RV32IZFHMIN-NEXT:    flt.s a0, fa3, fa4
 ; RV32IZFHMIN-NEXT:    beqz a0, .LBB36_2

 ; RV64IZFHMIN-NEXT:    fcvt.w.s a0, fa5, rne
 ; RV64IZFHMIN-NEXT:    fcvt.s.w fa4, a0, rne
 ; RV64IZFHMIN-NEXT:    fsgnj.s fa5, fa4, fa5
 ; RV64IZFHMIN-NEXT:  .LBB36_2:
 ; RV64IZFHMIN-NEXT:    fcvt.h.s fa5, fa5
 ; RV64IZFHMIN-NEXT:    fcvt.s.h fa5, fa5
 ; RV64IZFHMIN-NEXT:    fcvt.lu.s a0, fa5, rtz
 ; RV64IZFHMIN-NEXT:    ret
+;
+; RV32IZHINXMIN-LABEL: test_roundeven_ui8:
+; RV32IZHINXMIN:       # %bb.0:
+; RV32IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV32IZHINXMIN-NEXT:    lui a1, 307200
+; RV32IZHINXMIN-NEXT:    fabs.s a2, a0
+; RV32IZHINXMIN-NEXT:    flt.s a1, a2, a1
+; RV32IZHINXMIN-NEXT:    beqz a1, .LBB36_2
+; RV32IZHINXMIN-NEXT:  # %bb.1:
+; RV32IZHINXMIN-NEXT:    fcvt.w.s a1, a0, rne
+; RV32IZHINXMIN-NEXT:    fcvt.s.w a1, a1, rne
+; RV32IZHINXMIN-NEXT:    fsgnj.s a0, a1, a0
+; RV32IZHINXMIN-NEXT:  .LBB36_2:
+; RV32IZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; RV32IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV32IZHINXMIN-NEXT:    fcvt.wu.s a0, a0, rtz
+; RV32IZHINXMIN-NEXT:    ret
+;
+; RV64IZHINXMIN-LABEL: test_roundeven_ui8:
+; RV64IZHINXMIN:       # %bb.0:
+; RV64IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV64IZHINXMIN-NEXT:    lui a1, 307200
+; RV64IZHINXMIN-NEXT:    fabs.s a2, a0
+; RV64IZHINXMIN-NEXT:    flt.s a1, a2, a1
+; RV64IZHINXMIN-NEXT:    beqz a1, .LBB36_2
+; RV64IZHINXMIN-NEXT:  # %bb.1:
+; RV64IZHINXMIN-NEXT:    fcvt.w.s a1, a0, rne
+; RV64IZHINXMIN-NEXT:    fcvt.s.w a1, a1, rne
+; RV64IZHINXMIN-NEXT:    fsgnj.s a0, a1, a0
+; RV64IZHINXMIN-NEXT:  .LBB36_2:
+; RV64IZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; RV64IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV64IZHINXMIN-NEXT:    fcvt.lu.s a0, a0, rtz
+; RV64IZHINXMIN-NEXT:    ret
   %a = call half @llvm.roundeven.f16(half %x)
   %b = fptoui half %a to i8
   ret i8 %b
 }
 
 define zeroext i16 @test_roundeven_ui16(half %x) {
 ; RV32IZFH-LABEL: test_roundeven_ui16:
 ; RV32IZFH:       # %bb.0:
 ; RV32IZFH-NEXT:    fcvt.wu.h a0, fa0, rne
 ; RV32IZFH-NEXT:    ret
 ;
 ; RV64IZFH-LABEL: test_roundeven_ui16:
 ; RV64IZFH:       # %bb.0:
 ; RV64IZFH-NEXT:    fcvt.lu.h a0, fa0, rne
 ; RV64IZFH-NEXT:    ret
 ;
+; RV32IZHINX-LABEL: test_roundeven_ui16:
+; RV32IZHINX:       # %bb.0:
+; RV32IZHINX-NEXT:    lui a1, %hi(.LCPI37_0)
+; RV32IZHINX-NEXT:    lh a1, %lo(.LCPI37_0)(a1)
+; RV32IZHINX-NEXT:    fabs.h a2, a0
+; RV32IZHINX-NEXT:    flt.h a1, a2, a1
+; RV32IZHINX-NEXT:    beqz a1, .LBB37_2
+; RV32IZHINX-NEXT:  # %bb.1:
+; RV32IZHINX-NEXT:    fcvt.w.h a1, a0, rne
+; RV32IZHINX-NEXT:    fcvt.h.w a1, a1, rne
+; RV32IZHINX-NEXT:    fsgnj.h a0, a1, a0
+; RV32IZHINX-NEXT:  .LBB37_2:
+; RV32IZHINX-NEXT:    fcvt.wu.h a0, a0, rtz
+; RV32IZHINX-NEXT:    ret
+;
+; RV64IZHINX-LABEL: test_roundeven_ui16:
+; RV64IZHINX:       # %bb.0:
+; RV64IZHINX-NEXT:    lui a1, %hi(.LCPI37_0)
+; RV64IZHINX-NEXT:    lh a1, %lo(.LCPI37_0)(a1)
+; RV64IZHINX-NEXT:    fabs.h a2, a0
+; RV64IZHINX-NEXT:    flt.h a1, a2, a1
+; RV64IZHINX-NEXT:    beqz a1, .LBB37_2
+; RV64IZHINX-NEXT:  # %bb.1:
+; RV64IZHINX-NEXT:    fcvt.w.h a1, a0, rne
+; RV64IZHINX-NEXT:    fcvt.h.w a1, a1, rne
+; RV64IZHINX-NEXT:    fsgnj.h a0, a1, a0
+; RV64IZHINX-NEXT:  .LBB37_2:
+; RV64IZHINX-NEXT:    fcvt.lu.h a0, a0, rtz
+; RV64IZHINX-NEXT:    ret
+;
 ; RV32IZFHMIN-LABEL: test_roundeven_ui16:
 ; RV32IZFHMIN:       # %bb.0:
 ; RV32IZFHMIN-NEXT:    fcvt.s.h fa5, fa0
 ; RV32IZFHMIN-NEXT:    lui a0, 307200
 ; RV32IZFHMIN-NEXT:    fmv.w.x fa4, a0
 ; RV32IZFHMIN-NEXT:    fabs.s fa3, fa5
 ; RV32IZFHMIN-NEXT:    flt.s a0, fa3, fa4
 ; RV32IZFHMIN-NEXT:    beqz a0, .LBB37_2

 ; RV64IZFHMIN-NEXT:    fcvt.w.s a0, fa5, rne
 ; RV64IZFHMIN-NEXT:    fcvt.s.w fa4, a0, rne
 ; RV64IZFHMIN-NEXT:    fsgnj.s fa5, fa4, fa5
 ; RV64IZFHMIN-NEXT:  .LBB37_2:
 ; RV64IZFHMIN-NEXT:    fcvt.h.s fa5, fa5
 ; RV64IZFHMIN-NEXT:    fcvt.s.h fa5, fa5
 ; RV64IZFHMIN-NEXT:    fcvt.lu.s a0, fa5, rtz
 ; RV64IZFHMIN-NEXT:    ret
+;
+; RV32IZHINXMIN-LABEL: test_roundeven_ui16:
+; RV32IZHINXMIN:       # %bb.0:
+; RV32IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV32IZHINXMIN-NEXT:    lui a1, 307200
+; RV32IZHINXMIN-NEXT:    fabs.s a2, a0
+; RV32IZHINXMIN-NEXT:    flt.s a1, a2, a1
+; RV32IZHINXMIN-NEXT:    beqz a1, .LBB37_2
+; RV32IZHINXMIN-NEXT:  # %bb.1:
+; RV32IZHINXMIN-NEXT:    fcvt.w.s a1, a0, rne
+; RV32IZHINXMIN-NEXT:    fcvt.s.w a1, a1, rne
+; RV32IZHINXMIN-NEXT:    fsgnj.s a0, a1, a0
+; RV32IZHINXMIN-NEXT:  .LBB37_2:
+; RV32IZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; RV32IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV32IZHINXMIN-NEXT:    fcvt.wu.s a0, a0, rtz
+; RV32IZHINXMIN-NEXT:    ret
+;
+; RV64IZHINXMIN-LABEL: test_roundeven_ui16:
+; RV64IZHINXMIN:       # %bb.0:
+; RV64IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV64IZHINXMIN-NEXT:    lui a1, 307200
+; RV64IZHINXMIN-NEXT:    fabs.s a2, a0
+; RV64IZHINXMIN-NEXT:    flt.s a1, a2, a1
+; RV64IZHINXMIN-NEXT:    beqz a1, .LBB37_2
+; RV64IZHINXMIN-NEXT:  # %bb.1:
+; RV64IZHINXMIN-NEXT:    fcvt.w.s a1, a0, rne
+; RV64IZHINXMIN-NEXT:    fcvt.s.w a1, a1, rne
+; RV64IZHINXMIN-NEXT:    fsgnj.s a0, a1, a0
+; RV64IZHINXMIN-NEXT:  .LBB37_2:
+; RV64IZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; RV64IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV64IZHINXMIN-NEXT:    fcvt.lu.s a0, a0, rtz
+; RV64IZHINXMIN-NEXT:    ret
   %a = call half @llvm.roundeven.f16(half %x)
   %b = fptoui half %a to i16
   ret i16 %b
 }
 
 define signext i32 @test_roundeven_ui32(half %x) {
 ; CHECKIZFH-LABEL: test_roundeven_ui32:
 ; CHECKIZFH:       # %bb.0:
 ; CHECKIZFH-NEXT:    fcvt.wu.h a0, fa0, rne
 ; CHECKIZFH-NEXT:    ret
 ;
+; CHECKIZHINX-LABEL: test_roundeven_ui32:
+; CHECKIZHINX:       # %bb.0:
+; CHECKIZHINX-NEXT:    lui a1, %hi(.LCPI38_0)
+; CHECKIZHINX-NEXT:    lh a1, %lo(.LCPI38_0)(a1)
+; CHECKIZHINX-NEXT:    fabs.h a2, a0
+; CHECKIZHINX-NEXT:    flt.h a1, a2, a1
+; CHECKIZHINX-NEXT:    beqz a1, .LBB38_2
+; CHECKIZHINX-NEXT:  # %bb.1:
+; CHECKIZHINX-NEXT:    fcvt.w.h a1, a0, rne
+; CHECKIZHINX-NEXT:    fcvt.h.w a1, a1, rne
+; CHECKIZHINX-NEXT:    fsgnj.h a0, a1, a0
+; CHECKIZHINX-NEXT:  .LBB38_2:
+; CHECKIZHINX-NEXT:    fcvt.wu.h a0, a0, rtz
+; CHECKIZHINX-NEXT:    ret
+;
 ; CHECKIZFHMIN-LABEL: test_roundeven_ui32:
 ; CHECKIZFHMIN:       # %bb.0:
 ; CHECKIZFHMIN-NEXT:    fcvt.s.h fa5, fa0
 ; CHECKIZFHMIN-NEXT:    lui a0, 307200
 ; CHECKIZFHMIN-NEXT:    fmv.w.x fa4, a0
 ; CHECKIZFHMIN-NEXT:    fabs.s fa3, fa5
 ; CHECKIZFHMIN-NEXT:    flt.s a0, fa3, fa4
 ; CHECKIZFHMIN-NEXT:    beqz a0, .LBB38_2
 ; CHECKIZFHMIN-NEXT:  # %bb.1:
 ; CHECKIZFHMIN-NEXT:    fcvt.w.s a0, fa5, rne
 ; CHECKIZFHMIN-NEXT:    fcvt.s.w fa4, a0, rne
 ; CHECKIZFHMIN-NEXT:    fsgnj.s fa5, fa4, fa5
 ; CHECKIZFHMIN-NEXT:  .LBB38_2:
 ; CHECKIZFHMIN-NEXT:    fcvt.h.s fa5, fa5
 ; CHECKIZFHMIN-NEXT:    fcvt.s.h fa5, fa5
 ; CHECKIZFHMIN-NEXT:    fcvt.wu.s a0, fa5, rtz
 ; CHECKIZFHMIN-NEXT:    ret
+;
+; CHECKIZHINXMIN-LABEL: test_roundeven_ui32:
+; CHECKIZHINXMIN:       # %bb.0:
+; CHECKIZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECKIZHINXMIN-NEXT:    lui a1, 307200
+; CHECKIZHINXMIN-NEXT:    fabs.s a2, a0
+; CHECKIZHINXMIN-NEXT:    flt.s a1, a2, a1
+; CHECKIZHINXMIN-NEXT:    beqz a1, .LBB38_2
+; CHECKIZHINXMIN-NEXT:  # %bb.1:
+; CHECKIZHINXMIN-NEXT:    fcvt.w.s a1, a0, rne
+; CHECKIZHINXMIN-NEXT:    fcvt.s.w a1, a1, rne
+; CHECKIZHINXMIN-NEXT:    fsgnj.s a0, a1, a0
+; CHECKIZHINXMIN-NEXT:  .LBB38_2:
+; CHECKIZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; CHECKIZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECKIZHINXMIN-NEXT:    fcvt.wu.s a0, a0, rtz
+; CHECKIZHINXMIN-NEXT:    ret
   %a = call half @llvm.roundeven.f16(half %x)
   %b = fptoui half %a to i32
   ret i32 %b
 }
 
 define i64 @test_roundeven_ui64(half %x) {
 ; RV32IZFH-LABEL: test_roundeven_ui64:
 ; RV32IZFH:       # %bb.0:

 ; RV32IZFH-NEXT:    addi sp, sp, 16
 ; RV32IZFH-NEXT:    ret
 ;
 ; RV64IZFH-LABEL: test_roundeven_ui64:
 ; RV64IZFH:       # %bb.0:
 ; RV64IZFH-NEXT:    fcvt.lu.h a0, fa0, rne
 ; RV64IZFH-NEXT:    ret
 ;
+; RV32IZHINX-LABEL: test_roundeven_ui64:
+; RV32IZHINX:       # %bb.0:
+; RV32IZHINX-NEXT:    addi sp, sp, -16
+; RV32IZHINX-NEXT:    .cfi_def_cfa_offset 16
+; RV32IZHINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZHINX-NEXT:    .cfi_offset ra, -4
+; RV32IZHINX-NEXT:    lui a1, %hi(.LCPI39_0)
+; RV32IZHINX-NEXT:    lh a1, %lo(.LCPI39_0)(a1)
+; RV32IZHINX-NEXT:    fabs.h a2, a0
+; RV32IZHINX-NEXT:    flt.h a1, a2, a1
+; RV32IZHINX-NEXT:    beqz a1, .LBB39_2
+; RV32IZHINX-NEXT:  # %bb.1:
+; RV32IZHINX-NEXT:    fcvt.w.h a1, a0, rne
+; RV32IZHINX-NEXT:    fcvt.h.w a1, a1, rne
+; RV32IZHINX-NEXT:    fsgnj.h a0, a1, a0
+; RV32IZHINX-NEXT:  .LBB39_2:
+; RV32IZHINX-NEXT:    call __fixunshfdi@plt
+; RV32IZHINX-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZHINX-NEXT:    addi sp, sp, 16
+; RV32IZHINX-NEXT:    ret
+;
+; RV64IZHINX-LABEL: test_roundeven_ui64:
+; RV64IZHINX:       # %bb.0:
+; RV64IZHINX-NEXT:    lui a1, %hi(.LCPI39_0)
+; RV64IZHINX-NEXT:    lh a1, %lo(.LCPI39_0)(a1)
+; RV64IZHINX-NEXT:    fabs.h a2, a0
+; RV64IZHINX-NEXT:    flt.h a1, a2, a1
+; RV64IZHINX-NEXT:    beqz a1, .LBB39_2
+; RV64IZHINX-NEXT:  # %bb.1:
+; RV64IZHINX-NEXT:    fcvt.w.h a1, a0, rne
+; RV64IZHINX-NEXT:    fcvt.h.w a1, a1, rne
+; RV64IZHINX-NEXT:    fsgnj.h a0, a1, a0
+; RV64IZHINX-NEXT:  .LBB39_2:
+; RV64IZHINX-NEXT:    fcvt.lu.h a0, a0, rtz
+; RV64IZHINX-NEXT:    ret
+;
 ; RV32IZFHMIN-LABEL: test_roundeven_ui64:
 ; RV32IZFHMIN:       # %bb.0:
 ; RV32IZFHMIN-NEXT:    fcvt.s.h fa5, fa0
 ; RV32IZFHMIN-NEXT:    lui a0, 307200
 ; RV32IZFHMIN-NEXT:    fmv.w.x fa4, a0
 ; RV32IZFHMIN-NEXT:    fabs.s fa3, fa5
 ; RV32IZFHMIN-NEXT:    flt.s a0, fa3, fa4
 ; RV32IZFHMIN-NEXT:    beqz a0, .LBB39_2

 ; RV64IZFHMIN-NEXT:    fcvt.w.s a0, fa5, rne
 ; RV64IZFHMIN-NEXT:    fcvt.s.w fa4, a0, rne
 ; RV64IZFHMIN-NEXT:    fsgnj.s fa5, fa4, fa5
 ; RV64IZFHMIN-NEXT:  .LBB39_2:
 ; RV64IZFHMIN-NEXT:    fcvt.h.s fa5, fa5
 ; RV64IZFHMIN-NEXT:    fcvt.s.h fa5, fa5
 ; RV64IZFHMIN-NEXT:    fcvt.lu.s a0, fa5, rtz
 ; RV64IZFHMIN-NEXT:    ret
+;
+; RV32IZHINXMIN-LABEL: test_roundeven_ui64:
+; RV32IZHINXMIN:       # %bb.0:
+; RV32IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV32IZHINXMIN-NEXT:    lui a1, 307200
+; RV32IZHINXMIN-NEXT:    fabs.s a2, a0
+; RV32IZHINXMIN-NEXT:    flt.s a1, a2, a1
+; RV32IZHINXMIN-NEXT:    beqz a1, .LBB39_2
+; RV32IZHINXMIN-NEXT:  # %bb.1:
+; RV32IZHINXMIN-NEXT:    fcvt.w.s a1, a0, rne
+; RV32IZHINXMIN-NEXT:    fcvt.s.w a1, a1, rne
+; RV32IZHINXMIN-NEXT:    fsgnj.s a0, a1, a0
+; RV32IZHINXMIN-NEXT:  .LBB39_2:
+; RV32IZHINXMIN-NEXT:    addi sp, sp, -16
+; RV32IZHINXMIN-NEXT:    .cfi_def_cfa_offset 16
+; RV32IZHINXMIN-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZHINXMIN-NEXT:    .cfi_offset ra, -4
+; RV32IZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; RV32IZHINXMIN-NEXT:    call __fixunshfdi@plt
+; RV32IZHINXMIN-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZHINXMIN-NEXT:    addi sp, sp, 16
+; RV32IZHINXMIN-NEXT:    ret
+;
+; RV64IZHINXMIN-LABEL: test_roundeven_ui64:
+; RV64IZHINXMIN:       # %bb.0:
+; RV64IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV64IZHINXMIN-NEXT:    lui a1, 307200
+; RV64IZHINXMIN-NEXT:    fabs.s a2, a0
+; RV64IZHINXMIN-NEXT:    flt.s a1, a2, a1
+; RV64IZHINXMIN-NEXT:    beqz a1, .LBB39_2
+; RV64IZHINXMIN-NEXT:  # %bb.1:
+; RV64IZHINXMIN-NEXT:    fcvt.w.s a1, a0, rne
+; RV64IZHINXMIN-NEXT:    fcvt.s.w a1, a1, rne
+; RV64IZHINXMIN-NEXT:    fsgnj.s a0, a1, a0
+; RV64IZHINXMIN-NEXT:  .LBB39_2:
+; RV64IZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; RV64IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV64IZHINXMIN-NEXT:    fcvt.lu.s a0, a0, rtz
+; RV64IZHINXMIN-NEXT:    ret
   %a = call half @llvm.roundeven.f16(half %x)
   %b = fptoui half %a to i64
   ret i64 %b
 }
 
 define half @test_floor_half(half %x) {
 ; RV32IFD-LABEL: test_floor_half:
 ; RV32IFD:       # %bb.0:

 ; CHECKIZFH-NEXT:    beqz a0, .LBB40_2
 ; CHECKIZFH-NEXT:  # %bb.1:
 ; CHECKIZFH-NEXT:    fcvt.w.h a0, fa0, rdn
 ; CHECKIZFH-NEXT:    fcvt.h.w fa5, a0, rdn
 ; CHECKIZFH-NEXT:    fsgnj.h fa0, fa5, fa0
 ; CHECKIZFH-NEXT:  .LBB40_2:
 ; CHECKIZFH-NEXT:    ret
 ;
+; CHECKIZHINX-LABEL: test_floor_half:
+; CHECKIZHINX:       # %bb.0:
+; CHECKIZHINX-NEXT:    lui a1, %hi(.LCPI40_0)
+; CHECKIZHINX-NEXT:    lh a1, %lo(.LCPI40_0)(a1)
+; CHECKIZHINX-NEXT:    fabs.h a2, a0
+; CHECKIZHINX-NEXT:    flt.h a1, a2, a1
+; CHECKIZHINX-NEXT:    beqz a1, .LBB40_2
+; CHECKIZHINX-NEXT:  # %bb.1:
+; CHECKIZHINX-NEXT:    fcvt.w.h a1, a0, rdn
+; CHECKIZHINX-NEXT:    fcvt.h.w a1, a1, rdn
+; CHECKIZHINX-NEXT:    fsgnj.h a0, a1, a0
+; CHECKIZHINX-NEXT:  .LBB40_2:
+; CHECKIZHINX-NEXT:    ret
+;
 ; CHECKIZFHMIN-LABEL: test_floor_half:
 ; CHECKIZFHMIN:       # %bb.0:
 ; CHECKIZFHMIN-NEXT:    fcvt.s.h fa5, fa0
 ; CHECKIZFHMIN-NEXT:    lui a0, 307200
 ; CHECKIZFHMIN-NEXT:    fmv.w.x fa4, a0
 ; CHECKIZFHMIN-NEXT:    fabs.s fa3, fa5
 ; CHECKIZFHMIN-NEXT:    flt.s a0, fa3, fa4
 ; CHECKIZFHMIN-NEXT:    beqz a0, .LBB40_2
 ; CHECKIZFHMIN-NEXT:  # %bb.1:
 ; CHECKIZFHMIN-NEXT:    fcvt.w.s a0, fa5, rdn
 ; CHECKIZFHMIN-NEXT:    fcvt.s.w fa4, a0, rdn
 ; CHECKIZFHMIN-NEXT:    fsgnj.s fa5, fa4, fa5
 ; CHECKIZFHMIN-NEXT:  .LBB40_2:
 ; CHECKIZFHMIN-NEXT:    fcvt.h.s fa0, fa5
 ; CHECKIZFHMIN-NEXT:    ret
+;
+; CHECKIZHINXMIN-LABEL: test_floor_half:
+; CHECKIZHINXMIN:       # %bb.0:
+; CHECKIZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECKIZHINXMIN-NEXT:    lui a1, 307200
+; CHECKIZHINXMIN-NEXT:    fabs.s a2, a0
+; CHECKIZHINXMIN-NEXT:    flt.s a1, a2, a1
+; CHECKIZHINXMIN-NEXT:    beqz a1, .LBB40_2
+; CHECKIZHINXMIN-NEXT:  # %bb.1:
+; CHECKIZHINXMIN-NEXT:    fcvt.w.s a1, a0, rdn
+; CHECKIZHINXMIN-NEXT:    fcvt.s.w a1, a1, rdn
+; CHECKIZHINXMIN-NEXT:    fsgnj.s a0, a1, a0
+; CHECKIZHINXMIN-NEXT:  .LBB40_2:
+; CHECKIZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; CHECKIZHINXMIN-NEXT:    ret
   %a = call half @llvm.floor.f16(half %x)
   ret half %a
 }
 
 define half @test_ceil_half(half %x) {
 ; RV32IFD-LABEL: test_ceil_half:
 ; RV32IFD:       # %bb.0:
 ; RV32IFD-NEXT:    addi sp, sp, -16

 ; CHECKIZFH-NEXT:    beqz a0, .LBB41_2
 ; CHECKIZFH-NEXT:  # %bb.1:
 ; CHECKIZFH-NEXT:    fcvt.w.h a0, fa0, rup
 ; CHECKIZFH-NEXT:    fcvt.h.w fa5, a0, rup
 ; CHECKIZFH-NEXT:    fsgnj.h fa0, fa5, fa0
 ; CHECKIZFH-NEXT:  .LBB41_2:
 ; CHECKIZFH-NEXT:    ret
 ;
+; CHECKIZHINX-LABEL: test_ceil_half:
+; CHECKIZHINX:       # %bb.0:
+; CHECKIZHINX-NEXT:    lui a1, %hi(.LCPI41_0)
+; CHECKIZHINX-NEXT:    lh a1, %lo(.LCPI41_0)(a1)
+; CHECKIZHINX-NEXT:    fabs.h a2, a0
+; CHECKIZHINX-NEXT:    flt.h a1, a2, a1
+; CHECKIZHINX-NEXT:    beqz a1, .LBB41_2
+; CHECKIZHINX-NEXT:  # %bb.1:
+; CHECKIZHINX-NEXT:    fcvt.w.h a1, a0, rup
+; CHECKIZHINX-NEXT:    fcvt.h.w a1, a1, rup
+; CHECKIZHINX-NEXT:    fsgnj.h a0, a1, a0
+; CHECKIZHINX-NEXT:  .LBB41_2:
+; CHECKIZHINX-NEXT:    ret
+;
 ; CHECKIZFHMIN-LABEL: test_ceil_half:
 ; CHECKIZFHMIN:       # %bb.0:
 ; CHECKIZFHMIN-NEXT:    fcvt.s.h fa5, fa0
 ; CHECKIZFHMIN-NEXT:    lui a0, 307200
 ; CHECKIZFHMIN-NEXT:    fmv.w.x fa4, a0
 ; CHECKIZFHMIN-NEXT:    fabs.s fa3, fa5
 ; CHECKIZFHMIN-NEXT:    flt.s a0, fa3, fa4
 ; CHECKIZFHMIN-NEXT:    beqz a0, .LBB41_2
 ; CHECKIZFHMIN-NEXT:  # %bb.1:
 ; CHECKIZFHMIN-NEXT:    fcvt.w.s a0, fa5, rup
 ; CHECKIZFHMIN-NEXT:    fcvt.s.w fa4, a0, rup
 ; CHECKIZFHMIN-NEXT:    fsgnj.s fa5, fa4, fa5
 ; CHECKIZFHMIN-NEXT:  .LBB41_2:
 ; CHECKIZFHMIN-NEXT:    fcvt.h.s fa0, fa5
 ; CHECKIZFHMIN-NEXT:    ret
+;
+; CHECKIZHINXMIN-LABEL: test_ceil_half:
+; CHECKIZHINXMIN:       # %bb.0:
+; CHECKIZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECKIZHINXMIN-NEXT:    lui a1, 307200
+; CHECKIZHINXMIN-NEXT:    fabs.s a2, a0
+; CHECKIZHINXMIN-NEXT:    flt.s a1, a2, a1
+; CHECKIZHINXMIN-NEXT:    beqz a1, .LBB41_2
+; CHECKIZHINXMIN-NEXT:  # %bb.1:
+; CHECKIZHINXMIN-NEXT:    fcvt.w.s a1, a0, rup
+; CHECKIZHINXMIN-NEXT:    fcvt.s.w a1, a1, rup
+; CHECKIZHINXMIN-NEXT:    fsgnj.s a0, a1, a0
+; CHECKIZHINXMIN-NEXT:  .LBB41_2:
+; CHECKIZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; CHECKIZHINXMIN-NEXT:    ret
   %a = call half @llvm.ceil.f16(half %x)
   ret half %a
 }
 
 define half @test_trunc_half(half %x) {
 ; RV32IFD-LABEL: test_trunc_half:
 ; RV32IFD:       # %bb.0:
 ; RV32IFD-NEXT:    addi sp, sp, -16

 ; CHECKIZFH-NEXT:    beqz a0, .LBB42_2
 ; CHECKIZFH-NEXT:  # %bb.1:
 ; CHECKIZFH-NEXT:    fcvt.w.h a0, fa0, rtz
 ; CHECKIZFH-NEXT:    fcvt.h.w fa5, a0, rtz
 ; CHECKIZFH-NEXT:    fsgnj.h fa0, fa5, fa0
 ; CHECKIZFH-NEXT:  .LBB42_2:
 ; CHECKIZFH-NEXT:    ret
 ;
+; CHECKIZHINX-LABEL: test_trunc_half:
+; CHECKIZHINX:       # %bb.0:
+; CHECKIZHINX-NEXT:    lui a1, %hi(.LCPI42_0)
+; CHECKIZHINX-NEXT:    lh a1, %lo(.LCPI42_0)(a1)
+; CHECKIZHINX-NEXT:    fabs.h a2, a0
+; CHECKIZHINX-NEXT:    flt.h a1, a2, a1
+; CHECKIZHINX-NEXT:    beqz a1, .LBB42_2
+; CHECKIZHINX-NEXT:  # %bb.1:
+; CHECKIZHINX-NEXT:    fcvt.w.h a1, a0, rtz
+; CHECKIZHINX-NEXT:    fcvt.h.w a1, a1, rtz
+; CHECKIZHINX-NEXT:    fsgnj.h a0, a1, a0
+; CHECKIZHINX-NEXT:  .LBB42_2:
+; CHECKIZHINX-NEXT:    ret
+;
 ; CHECKIZFHMIN-LABEL: test_trunc_half:
 ; CHECKIZFHMIN:       # %bb.0:
 ; CHECKIZFHMIN-NEXT:    fcvt.s.h fa5, fa0
 ; CHECKIZFHMIN-NEXT:    lui a0, 307200
 ; CHECKIZFHMIN-NEXT:    fmv.w.x fa4, a0
 ; CHECKIZFHMIN-NEXT:    fabs.s fa3, fa5
 ; CHECKIZFHMIN-NEXT:    flt.s a0, fa3, fa4
 ; CHECKIZFHMIN-NEXT:    beqz a0, .LBB42_2
 ; CHECKIZFHMIN-NEXT:  # %bb.1:
 ; CHECKIZFHMIN-NEXT:    fcvt.w.s a0, fa5, rtz
 ; CHECKIZFHMIN-NEXT:    fcvt.s.w fa4, a0, rtz
 ; CHECKIZFHMIN-NEXT:    fsgnj.s fa5, fa4, fa5
 ; CHECKIZFHMIN-NEXT:  .LBB42_2:
 ; CHECKIZFHMIN-NEXT:    fcvt.h.s fa0, fa5
 ; CHECKIZFHMIN-NEXT:    ret
+;
+; CHECKIZHINXMIN-LABEL: test_trunc_half:
+; CHECKIZHINXMIN:       # %bb.0:
+; CHECKIZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECKIZHINXMIN-NEXT:    lui a1, 307200
+; CHECKIZHINXMIN-NEXT:    fabs.s a2, a0
+; CHECKIZHINXMIN-NEXT:    flt.s a1, a2, a1
+; CHECKIZHINXMIN-NEXT:    beqz a1, .LBB42_2
+; CHECKIZHINXMIN-NEXT:  # %bb.1:
+; CHECKIZHINXMIN-NEXT:    fcvt.w.s a1, a0, rtz
+; CHECKIZHINXMIN-NEXT:    fcvt.s.w a1, a1, rtz
+; CHECKIZHINXMIN-NEXT:    fsgnj.s a0, a1, a0
+; CHECKIZHINXMIN-NEXT:  .LBB42_2:
+; CHECKIZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; CHECKIZHINXMIN-NEXT:    ret
   %a = call half @llvm.trunc.f16(half %x)
   ret half %a
 }
 
 define half @test_round_half(half %x) {
 ; RV32IFD-LABEL: test_round_half:
 ; RV32IFD:       # %bb.0:
 ; RV32IFD-NEXT:    addi sp, sp, -16

 ; CHECKIZFH-NEXT:    beqz a0, .LBB43_2
 ; CHECKIZFH-NEXT:  # %bb.1:
 ; CHECKIZFH-NEXT:    fcvt.w.h a0, fa0, rmm
 ; CHECKIZFH-NEXT:    fcvt.h.w fa5, a0, rmm
 ; CHECKIZFH-NEXT:    fsgnj.h fa0, fa5, fa0
 ; CHECKIZFH-NEXT:  .LBB43_2:
 ; CHECKIZFH-NEXT:    ret
 ;
+; CHECKIZHINX-LABEL: test_round_half:
+; CHECKIZHINX:       # %bb.0:
+; CHECKIZHINX-NEXT:    lui a1, %hi(.LCPI43_0)
+; CHECKIZHINX-NEXT:    lh a1, %lo(.LCPI43_0)(a1)
+; CHECKIZHINX-NEXT:    fabs.h a2, a0
+; CHECKIZHINX-NEXT:    flt.h a1, a2, a1
+; CHECKIZHINX-NEXT:    beqz a1, .LBB43_2
+; CHECKIZHINX-NEXT:  # %bb.1:
+; CHECKIZHINX-NEXT:    fcvt.w.h a1, a0, rmm
+; CHECKIZHINX-NEXT:    fcvt.h.w a1, a1, rmm
+; CHECKIZHINX-NEXT:    fsgnj.h a0, a1, a0
+; CHECKIZHINX-NEXT:  .LBB43_2:
+; CHECKIZHINX-NEXT:    ret
+;
 ; CHECKIZFHMIN-LABEL: test_round_half:
 ; CHECKIZFHMIN:       # %bb.0:
 ; CHECKIZFHMIN-NEXT:    fcvt.s.h fa5, fa0
 ; CHECKIZFHMIN-NEXT:    lui a0, 307200
 ; CHECKIZFHMIN-NEXT:    fmv.w.x fa4, a0
 ; CHECKIZFHMIN-NEXT:    fabs.s fa3, fa5
 ; CHECKIZFHMIN-NEXT:    flt.s a0, fa3, fa4
 ; CHECKIZFHMIN-NEXT:    beqz a0, .LBB43_2
 ; CHECKIZFHMIN-NEXT:  # %bb.1:
 ; CHECKIZFHMIN-NEXT:    fcvt.w.s a0, fa5, rmm
 ; CHECKIZFHMIN-NEXT:    fcvt.s.w fa4, a0, rmm
 ; CHECKIZFHMIN-NEXT:    fsgnj.s fa5, fa4, fa5
 ; CHECKIZFHMIN-NEXT:  .LBB43_2:
 ; CHECKIZFHMIN-NEXT:    fcvt.h.s fa0, fa5
 ; CHECKIZFHMIN-NEXT:    ret
+;
+; CHECKIZHINXMIN-LABEL: test_round_half:
+; CHECKIZHINXMIN:       # %bb.0:
+; CHECKIZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECKIZHINXMIN-NEXT:    lui a1, 307200
+; CHECKIZHINXMIN-NEXT:    fabs.s a2, a0
+; CHECKIZHINXMIN-NEXT:    flt.s a1, a2, a1
+; CHECKIZHINXMIN-NEXT:    beqz a1, .LBB43_2
+; CHECKIZHINXMIN-NEXT:  # %bb.1:
+; CHECKIZHINXMIN-NEXT:    fcvt.w.s a1, a0, rmm
+; CHECKIZHINXMIN-NEXT:    fcvt.s.w a1, a1, rmm
+; CHECKIZHINXMIN-NEXT:    fsgnj.s a0, a1, a0
+; CHECKIZHINXMIN-NEXT:  .LBB43_2:
+; CHECKIZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; CHECKIZHINXMIN-NEXT:    ret
   %a = call half @llvm.round.f16(half %x)
   ret half %a
 }
 
 define half @test_roundeven_half(half %x) {
 ; RV32IFD-LABEL: test_roundeven_half:
 ; RV32IFD:       # %bb.0:
 ; RV32IFD-NEXT:    addi sp, sp, -16

 ; CHECKIZFH-NEXT:    beqz a0, .LBB44_2
 ; CHECKIZFH-NEXT:  # %bb.1:
 ; CHECKIZFH-NEXT:    fcvt.w.h a0, fa0, rne
 ; CHECKIZFH-NEXT:    fcvt.h.w fa5, a0, rne
 ; CHECKIZFH-NEXT:    fsgnj.h fa0, fa5, fa0
 ; CHECKIZFH-NEXT:  .LBB44_2:
 ; CHECKIZFH-NEXT:    ret
 ;
+; CHECKIZHINX-LABEL: test_roundeven_half:
+; CHECKIZHINX:       # %bb.0:
+; CHECKIZHINX-NEXT:    lui a1, %hi(.LCPI44_0)
+; CHECKIZHINX-NEXT:    lh a1, %lo(.LCPI44_0)(a1)
+; CHECKIZHINX-NEXT:    fabs.h a2, a0
+; CHECKIZHINX-NEXT:    flt.h a1, a2, a1
+; CHECKIZHINX-NEXT:    beqz a1, .LBB44_2
+; CHECKIZHINX-NEXT:  # %bb.1:
+; CHECKIZHINX-NEXT:    fcvt.w.h a1, a0, rne
+; CHECKIZHINX-NEXT:    fcvt.h.w a1, a1, rne
+; CHECKIZHINX-NEXT:    fsgnj.h a0, a1, a0
+; CHECKIZHINX-NEXT:  .LBB44_2:
+; CHECKIZHINX-NEXT:    ret
+;
 ; CHECKIZFHMIN-LABEL: test_roundeven_half:
 ; CHECKIZFHMIN:       # %bb.0:
 ; CHECKIZFHMIN-NEXT:    fcvt.s.h fa5, fa0
 ; CHECKIZFHMIN-NEXT:    lui a0, 307200
 ; CHECKIZFHMIN-NEXT:    fmv.w.x fa4, a0
 ; CHECKIZFHMIN-NEXT:    fabs.s fa3, fa5
 ; CHECKIZFHMIN-NEXT:    flt.s a0, fa3, fa4
 ; CHECKIZFHMIN-NEXT:    beqz a0, .LBB44_2
 ; CHECKIZFHMIN-NEXT:  # %bb.1:
 ; CHECKIZFHMIN-NEXT:    fcvt.w.s a0, fa5, rne
 ; CHECKIZFHMIN-NEXT:    fcvt.s.w fa4, a0, rne
 ; CHECKIZFHMIN-NEXT:    fsgnj.s fa5, fa4, fa5
 ; CHECKIZFHMIN-NEXT:  .LBB44_2:
 ; CHECKIZFHMIN-NEXT:    fcvt.h.s fa0, fa5
 ; CHECKIZFHMIN-NEXT:    ret
+;
+; CHECKIZHINXMIN-LABEL: test_roundeven_half:
+; CHECKIZHINXMIN:       # %bb.0:
+; CHECKIZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECKIZHINXMIN-NEXT:    lui a1, 307200
+; CHECKIZHINXMIN-NEXT:    fabs.s a2, a0
+; CHECKIZHINXMIN-NEXT:    flt.s a1, a2, a1
+; CHECKIZHINXMIN-NEXT:    beqz a1, .LBB44_2
+; CHECKIZHINXMIN-NEXT:  # %bb.1:
+; CHECKIZHINXMIN-NEXT:    fcvt.w.s a1, a0, rne
+; CHECKIZHINXMIN-NEXT:    fcvt.s.w a1, a1, rne
+; CHECKIZHINXMIN-NEXT:    fsgnj.s a0, a1, a0
+; CHECKIZHINXMIN-NEXT:  .LBB44_2:
+; CHECKIZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; CHECKIZHINXMIN-NEXT:    ret
   %a = call half @llvm.roundeven.f16(half %x)
   ret half %a
 }
 
 declare half @llvm.floor.f16(half)
 declare half @llvm.ceil.f16(half)
 declare half @llvm.trunc.f16(half)
 declare half @llvm.round.f16(half)
 declare half @llvm.roundeven.f16(half)

llvm/test/CodeGen/RISCV/half-select-fcmp.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -mattr=+zfh -verify-machineinstrs \
 ; RUN:   -target-abi ilp32f < %s | FileCheck %s
 ; RUN: llc -mtriple=riscv64 -mattr=+zfh -verify-machineinstrs \
 ; RUN:   -target-abi lp64f < %s | FileCheck %s
+; RUN: llc -mtriple=riscv32 -mattr=+zhinx -verify-machineinstrs \
+; RUN:   -target-abi ilp32 < %s | FileCheck -check-prefix=CHECKIZHINX %s
+; RUN: llc -mtriple=riscv64 -mattr=+zhinx -verify-machineinstrs \
+; RUN:   -target-abi lp64 < %s | FileCheck -check-prefix=CHECKIZHINX %s
 ; RUN: llc -mtriple=riscv32 -mattr=+zfhmin -verify-machineinstrs < %s \
 ; RUN:   -target-abi=ilp32f | FileCheck -check-prefix=CHECKIZFHMIN %s
 ; RUN: llc -mtriple=riscv64 -mattr=+zfhmin -verify-machineinstrs < %s \
 ; RUN:   -target-abi=lp64f | FileCheck -check-prefix=CHECKIZFHMIN %s
+; RUN: llc -mtriple=riscv32 -mattr=+zhinxmin -verify-machineinstrs < %s \
+; RUN:   -target-abi=ilp32 | FileCheck -check-prefix=CHECKIZFHMIN %s
+; RUN: llc -mtriple=riscv64 -mattr=+zhinxmin -verify-machineinstrs < %s \
+; RUN:   -target-abi=lp64 | FileCheck -check-prefix=CHECKIZFHMIN %s
 
 define half @select_fcmp_false(half %a, half %b) nounwind {
 ; CHECK-LABEL: select_fcmp_false:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    fmv.h fa0, fa1
 ; CHECK-NEXT:    ret
 ;
-; CHECKIZFHMIN-LABEL: select_fcmp_false:
-; CHECKIZFHMIN:       # %bb.0:
-; CHECKIZFHMIN-NEXT:    fmv.s fa0, fa1
-; CHECKIZFHMIN-NEXT:    ret
+; CHECKIZHINX-LABEL: select_fcmp_false:
+; CHECKIZHINX:       # %bb.0:
+; CHECKIZHINX-NEXT:    mv a0, a1
+; CHECKIZHINX-NEXT:    ret
   %1 = fcmp false half %a, %b
   %2 = select i1 %1, half %a, half %b
   ret half %2
 }
 
 define half @select_fcmp_oeq(half %a, half %b) nounwind {
 ; CHECK-LABEL: select_fcmp_oeq:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    feq.h a0, fa0, fa1
 ; CHECK-NEXT:    bnez a0, .LBB1_2
 ; CHECK-NEXT:  # %bb.1:
 ; CHECK-NEXT:    fmv.h fa0, fa1
 ; CHECK-NEXT:  .LBB1_2:
 ; CHECK-NEXT:    ret
 ;
-; CHECKIZFHMIN-LABEL: select_fcmp_oeq:
-; CHECKIZFHMIN:       # %bb.0:
-; CHECKIZFHMIN-NEXT:    fcvt.s.h fa4, fa1
-; CHECKIZFHMIN-NEXT:    fcvt.s.h fa5, fa0
-; CHECKIZFHMIN-NEXT:    feq.s a0, fa5, fa4
-; CHECKIZFHMIN-NEXT:    bnez a0, .LBB1_2
-; CHECKIZFHMIN-NEXT:  # %bb.1:
-; CHECKIZFHMIN-NEXT:    fmv.s fa5, fa4
-; CHECKIZFHMIN-NEXT:  .LBB1_2:
-; CHECKIZFHMIN-NEXT:    fcvt.h.s fa0, fa5
-; CHECKIZFHMIN-NEXT:    ret
+; CHECKIZHINX-LABEL: select_fcmp_oeq:
+; CHECKIZHINX:       # %bb.0:
+; CHECKIZHINX-NEXT:    feq.h a2, a0, a1
+; CHECKIZHINX-NEXT:    bnez a2, .LBB1_2
+; CHECKIZHINX-NEXT:  # %bb.1:
+; CHECKIZHINX-NEXT:    mv a0, a1
+; CHECKIZHINX-NEXT:  .LBB1_2:
+; CHECKIZHINX-NEXT:    ret
   %1 = fcmp oeq half %a, %b
   %2 = select i1 %1, half %a, half %b
   ret half %2
 }
 
 define half @select_fcmp_ogt(half %a, half %b) nounwind {
 ; CHECK-LABEL: select_fcmp_ogt:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    flt.h a0, fa1, fa0
 ; CHECK-NEXT:    bnez a0, .LBB2_2
 ; CHECK-NEXT:  # %bb.1:
 ; CHECK-NEXT:    fmv.h fa0, fa1
 ; CHECK-NEXT:  .LBB2_2:
 ; CHECK-NEXT:    ret
 ;
-; CHECKIZFHMIN-LABEL: select_fcmp_ogt:
-; CHECKIZFHMIN:       # %bb.0:
-; CHECKIZFHMIN-NEXT:    fcvt.s.h fa5, fa0
-; CHECKIZFHMIN-NEXT:    fcvt.s.h fa4, fa1
-; CHECKIZFHMIN-NEXT:    flt.s a0, fa4, fa5
-; CHECKIZFHMIN-NEXT:    bnez a0, .LBB2_2
-; CHECKIZFHMIN-NEXT:  # %bb.1:
-; CHECKIZFHMIN-NEXT:    fmv.s fa5, fa4
-; CHECKIZFHMIN-NEXT:  .LBB2_2:
-; CHECKIZFHMIN-NEXT:    fcvt.h.s fa0, fa5
-; CHECKIZFHMIN-NEXT:    ret
+; CHECKIZHINX-LABEL: select_fcmp_ogt:
+; CHECKIZHINX:       # %bb.0:
+; CHECKIZHINX-NEXT:    flt.h a2, a1, a0
+; CHECKIZHINX-NEXT:    bnez a2, .LBB2_2
+; CHECKIZHINX-NEXT:  # %bb.1:
+; CHECKIZHINX-NEXT:    mv a0, a1
+; CHECKIZHINX-NEXT:  .LBB2_2:
+; CHECKIZHINX-NEXT:    ret
   %1 = fcmp ogt half %a, %b
   %2 = select i1 %1, half %a, half %b
   ret half %2
 }
 
 define half @select_fcmp_oge(half %a, half %b) nounwind {
 ; CHECK-LABEL: select_fcmp_oge:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    fle.h a0, fa1, fa0
 ; CHECK-NEXT:    bnez a0, .LBB3_2
 ; CHECK-NEXT:  # %bb.1:
 ; CHECK-NEXT:    fmv.h fa0, fa1
 ; CHECK-NEXT:  .LBB3_2:
 ; CHECK-NEXT:    ret
 ;
-; CHECKIZFHMIN-LABEL: select_fcmp_oge:
-; CHECKIZFHMIN:       # %bb.0:
-; CHECKIZFHMIN-NEXT:    fcvt.s.h fa5, fa0
-; CHECKIZFHMIN-NEXT:    fcvt.s.h fa4, fa1
-; CHECKIZFHMIN-NEXT:    fle.s a0, fa4, fa5
-; CHECKIZFHMIN-NEXT:    bnez a0, .LBB3_2
-; CHECKIZFHMIN-NEXT:  # %bb.1:
-; CHECKIZFHMIN-NEXT:    fmv.s fa5, fa4
-; CHECKIZFHMIN-NEXT:  .LBB3_2:
-; CHECKIZFHMIN-NEXT:    fcvt.h.s fa0, fa5
-; CHECKIZFHMIN-NEXT:    ret
+; CHECKIZHINX-LABEL: select_fcmp_oge:
+; CHECKIZHINX:       # %bb.0:
+; CHECKIZHINX-NEXT:    fle.h a2, a1, a0
+; CHECKIZHINX-NEXT:    bnez a2, .LBB3_2
+; CHECKIZHINX-NEXT:  # %bb.1:
+; CHECKIZHINX-NEXT:    mv a0, a1
+; CHECKIZHINX-NEXT:  .LBB3_2:
+; CHECKIZHINX-NEXT:    ret
   %1 = fcmp oge half %a, %b
   %2 = select i1 %1, half %a, half %b
   ret half %2
 }
 
 define half @select_fcmp_olt(half %a, half %b) nounwind {
 ; CHECK-LABEL: select_fcmp_olt:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    flt.h a0, fa0, fa1
 ; CHECK-NEXT:    bnez a0, .LBB4_2
 ; CHECK-NEXT:  # %bb.1:
 ; CHECK-NEXT:    fmv.h fa0, fa1
 ; CHECK-NEXT:  .LBB4_2:
 ; CHECK-NEXT:    ret
 ;
-; CHECKIZFHMIN-LABEL: select_fcmp_olt:
-; CHECKIZFHMIN:       # %bb.0:
-; CHECKIZFHMIN-NEXT:    fcvt.s.h fa4, fa1
-; CHECKIZFHMIN-NEXT:    fcvt.s.h fa5, fa0
-; CHECKIZFHMIN-NEXT:    flt.s a0, fa5, fa4
-; CHECKIZFHMIN-NEXT:    bnez a0, .LBB4_2
-; CHECKIZFHMIN-NEXT:  # %bb.1:
-; CHECKIZFHMIN-NEXT:    fmv.s fa5, fa4
-; CHECKIZFHMIN-NEXT:  .LBB4_2:
-; CHECKIZFHMIN-NEXT:    fcvt.h.s fa0, fa5
-; CHECKIZFHMIN-NEXT:    ret
+; CHECKIZHINX-LABEL: select_fcmp_olt:
+; CHECKIZHINX:       # %bb.0:
+; CHECKIZHINX-NEXT:    flt.h a2, a0, a1
+; CHECKIZHINX-NEXT:    bnez a2, .LBB4_2
+; CHECKIZHINX-NEXT:  # %bb.1:
+; CHECKIZHINX-NEXT:    mv a0, a1
+; CHECKIZHINX-NEXT:  .LBB4_2:
+; CHECKIZHINX-NEXT:    ret
   %1 = fcmp olt half %a, %b
   %2 = select i1 %1, half %a, half %b
   ret half %2
 }
 
 define half @select_fcmp_ole(half %a, half %b) nounwind {
 ; CHECK-LABEL: select_fcmp_ole:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    fle.h a0, fa0, fa1
 ; CHECK-NEXT:    bnez a0, .LBB5_2
 ; CHECK-NEXT:  # %bb.1:
 ; CHECK-NEXT:    fmv.h fa0, fa1
 ; CHECK-NEXT:  .LBB5_2:
 ; CHECK-NEXT:    ret
 ;
-; CHECKIZFHMIN-LABEL: select_fcmp_ole:
-; CHECKIZFHMIN:       # %bb.0:
-; CHECKIZFHMIN-NEXT:    fcvt.s.h fa4, fa1
-; CHECKIZFHMIN-NEXT:    fcvt.s.h fa5, fa0
-; CHECKIZFHMIN-NEXT:    fle.s a0, fa5, fa4
-; CHECKIZFHMIN-NEXT:    bnez a0, .LBB5_2
-; CHECKIZFHMIN-NEXT:  # %bb.1:
-; CHECKIZFHMIN-NEXT:    fmv.s fa5, fa4
-; CHECKIZFHMIN-NEXT:  .LBB5_2:
-; CHECKIZFHMIN-NEXT:    fcvt.h.s fa0, fa5
-; CHECKIZFHMIN-NEXT:    ret
+; CHECKIZHINX-LABEL: select_fcmp_ole:
+; CHECKIZHINX:       # %bb.0:
+; CHECKIZHINX-NEXT:    fle.h a2, a0, a1
+; CHECKIZHINX-NEXT:    bnez a2, .LBB5_2
+; CHECKIZHINX-NEXT:  # %bb.1:
+; CHECKIZHINX-NEXT:    mv a0, a1
+; CHECKIZHINX-NEXT:  .LBB5_2:
+; CHECKIZHINX-NEXT:    ret
   %1 = fcmp ole half %a, %b
   %2 = select i1 %1, half %a, half %b
   ret half %2
 }
 
 define half @select_fcmp_one(half %a, half %b) nounwind {
 ; CHECK-LABEL: select_fcmp_one:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    flt.h a0, fa0, fa1
 ; CHECK-NEXT:    flt.h a1, fa1, fa0
 ; CHECK-NEXT:    or a0, a1, a0
 ; CHECK-NEXT:    bnez a0, .LBB6_2
 ; CHECK-NEXT:  # %bb.1:
 ; CHECK-NEXT:    fmv.h fa0, fa1
 ; CHECK-NEXT:  .LBB6_2:
 ; CHECK-NEXT:    ret
 ;
-; CHECKIZFHMIN-LABEL: select_fcmp_one:
-; CHECKIZFHMIN:       # %bb.0:
-; CHECKIZFHMIN-NEXT:    fcvt.s.h fa4, fa1
-; CHECKIZFHMIN-NEXT:    fcvt.s.h fa5, fa0
-; CHECKIZFHMIN-NEXT:    flt.s a0, fa5, fa4
-; CHECKIZFHMIN-NEXT:    flt.s a1, fa4, fa5
-; CHECKIZFHMIN-NEXT:    or a0, a1, a0
-; CHECKIZFHMIN-NEXT:    bnez a0, .LBB6_2
-; CHECKIZFHMIN-NEXT:  # %bb.1:
-; CHECKIZFHMIN-NEXT:    fmv.s fa5, fa4
-; CHECKIZFHMIN-NEXT:  .LBB6_2:
-; CHECKIZFHMIN-NEXT:    fcvt.h.s fa0, fa5
-; CHECKIZFHMIN-NEXT:    ret
+; CHECKIZHINX-LABEL: select_fcmp_one:
+; CHECKIZHINX:       # %bb.0:
+; CHECKIZHINX-NEXT:    flt.h a2, a0, a1
+; CHECKIZHINX-NEXT:    flt.h a3, a1, a0
+; CHECKIZHINX-NEXT:    or a2, a3, a2
+; CHECKIZHINX-NEXT:    bnez a2, .LBB6_2
+; CHECKIZHINX-NEXT:  # %bb.1:
+; CHECKIZHINX-NEXT:    mv a0, a1
+; CHECKIZHINX-NEXT:  .LBB6_2:
+; CHECKIZHINX-NEXT:    ret
   %1 = fcmp one half %a, %b
   %2 = select i1 %1, half %a, half %b
   ret half %2
 }
 
 define half @select_fcmp_ord(half %a, half %b) nounwind {
 ; CHECK-LABEL: select_fcmp_ord:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    feq.h a0, fa1, fa1
 ; CHECK-NEXT:    feq.h a1, fa0, fa0
 ; CHECK-NEXT:    and a0, a1, a0
 ; CHECK-NEXT:    bnez a0, .LBB7_2
 ; CHECK-NEXT:  # %bb.1:
 ; CHECK-NEXT:    fmv.h fa0, fa1
 ; CHECK-NEXT:  .LBB7_2:
 ; CHECK-NEXT:    ret
 ;
-; CHECKIZFHMIN-LABEL: select_fcmp_ord:
-; CHECKIZFHMIN:       # %bb.0:
-; CHECKIZFHMIN-NEXT:    fcvt.s.h fa5, fa1
-; CHECKIZFHMIN-NEXT:    feq.s a0, fa5, fa5
-; CHECKIZFHMIN-NEXT:    fcvt.s.h fa4, fa0
-; CHECKIZFHMIN-NEXT:    feq.s a1, fa4, fa4
-; CHECKIZFHMIN-NEXT:    and a0, a1, a0
-; CHECKIZFHMIN-NEXT:    bnez a0, .LBB7_2
-; CHECKIZFHMIN-NEXT:  # %bb.1:
-; CHECKIZFHMIN-NEXT:    fmv.s fa4, fa5
-; CHECKIZFHMIN-NEXT:  .LBB7_2:
-; CHECKIZFHMIN-NEXT:    fcvt.h.s fa0, fa4
-; CHECKIZFHMIN-NEXT:    ret
+; CHECKIZHINX-LABEL: select_fcmp_ord:
+; CHECKIZHINX:       # %bb.0:
+; CHECKIZHINX-NEXT:    feq.h a2, a1, a1
+; CHECKIZHINX-NEXT:    feq.h a3, a0, a0
+; CHECKIZHINX-NEXT:    and a2, a3, a2
+; CHECKIZHINX-NEXT:    bnez a2, .LBB7_2
+; CHECKIZHINX-NEXT:  # %bb.1:
+; CHECKIZHINX-NEXT:    mv a0, a1
+; CHECKIZHINX-NEXT:  .LBB7_2:
+; CHECKIZHINX-NEXT:    ret
   %1 = fcmp ord half %a, %b
   %2 = select i1 %1, half %a, half %b
   ret half %2
 }
 
 define half @select_fcmp_ueq(half %a, half %b) nounwind {
 ; CHECK-LABEL: select_fcmp_ueq:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    flt.h a0, fa0, fa1
 ; CHECK-NEXT:    flt.h a1, fa1, fa0
 ; CHECK-NEXT:    or a0, a1, a0
 ; CHECK-NEXT:    beqz a0, .LBB8_2
 ; CHECK-NEXT:  # %bb.1:
 ; CHECK-NEXT:    fmv.h fa0, fa1
 ; CHECK-NEXT:  .LBB8_2:
 ; CHECK-NEXT:    ret
 ;
-; CHECKIZFHMIN-LABEL: select_fcmp_ueq:
-; CHECKIZFHMIN:       # %bb.0:
-; CHECKIZFHMIN-NEXT:    fcvt.s.h fa4, fa1
-; CHECKIZFHMIN-NEXT:    fcvt.s.h fa5, fa0
-; CHECKIZFHMIN-NEXT:    flt.s a0, fa5, fa4
-; CHECKIZFHMIN-NEXT:    flt.s a1, fa4, fa5
-; CHECKIZFHMIN-NEXT:    or a0, a1, a0
-; CHECKIZFHMIN-NEXT:    beqz a0, .LBB8_2
-; CHECKIZFHMIN-NEXT:  # %bb.1:
-; CHECKIZFHMIN-NEXT:    fmv.s fa5, fa4
-; CHECKIZFHMIN-NEXT:  .LBB8_2:
-; CHECKIZFHMIN-NEXT:    fcvt.h.s fa0, fa5
-; CHECKIZFHMIN-NEXT:    ret
+; CHECKIZHINX-LABEL: select_fcmp_ueq:
+; CHECKIZHINX:       # %bb.0:
+; CHECKIZHINX-NEXT:    flt.h a2, a0, a1
+; CHECKIZHINX-NEXT:    flt.h a3, a1, a0
+; CHECKIZHINX-NEXT:    or a2, a3, a2
+; CHECKIZHINX-NEXT:    beqz a2, .LBB8_2
+; CHECKIZHINX-NEXT:  # %bb.1:
+; CHECKIZHINX-NEXT:    mv a0, a1
+; CHECKIZHINX-NEXT:  .LBB8_2:
+; CHECKIZHINX-NEXT:    ret
   %1 = fcmp ueq half %a, %b
   %2 = select i1 %1, half %a, half %b
   ret half %2
 }
 
 define half @select_fcmp_ugt(half %a, half %b) nounwind {
 ; CHECK-LABEL: select_fcmp_ugt:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    fle.h a0, fa0, fa1
 ; CHECK-NEXT:    beqz a0, .LBB9_2
 ; CHECK-NEXT:  # %bb.1:
 ; CHECK-NEXT:    fmv.h fa0, fa1
 ; CHECK-NEXT:  .LBB9_2:
 ; CHECK-NEXT:    ret
 ;
-; CHECKIZFHMIN-LABEL: select_fcmp_ugt:
-; CHECKIZFHMIN:       # %bb.0:
-; CHECKIZFHMIN-NEXT:    fcvt.s.h fa4, fa1
-; CHECKIZFHMIN-NEXT:    fcvt.s.h fa5, fa0
-; CHECKIZFHMIN-NEXT:    fle.s a0, fa5, fa4
-; CHECKIZFHMIN-NEXT:    beqz a0, .LBB9_2
-; CHECKIZFHMIN-NEXT:  # %bb.1:
-; CHECKIZFHMIN-NEXT:    fmv.s fa5, fa4
-; CHECKIZFHMIN-NEXT:  .LBB9_2:
-; CHECKIZFHMIN-NEXT:    fcvt.h.s fa0, fa5
-; CHECKIZFHMIN-NEXT:    ret
+; CHECKIZHINX-LABEL: select_fcmp_ugt:
+; CHECKIZHINX:       # %bb.0:
+; CHECKIZHINX-NEXT:    fle.h a2, a0, a1
+; CHECKIZHINX-NEXT:    beqz a2, .LBB9_2
+; CHECKIZHINX-NEXT:  # %bb.1:
+; CHECKIZHINX-NEXT:    mv a0, a1
+; CHECKIZHINX-NEXT:  .LBB9_2:
+; CHECKIZHINX-NEXT:    ret
   %1 = fcmp ugt half %a, %b
   %2 = select i1 %1, half %a, half %b
   ret half %2
 }
 
 define half @select_fcmp_uge(half %a, half %b) nounwind {
 ; CHECK-LABEL: select_fcmp_uge:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    flt.h a0, fa0, fa1
 ; CHECK-NEXT:    beqz a0, .LBB10_2
 ; CHECK-NEXT:  # %bb.1:
 ; CHECK-NEXT:    fmv.h fa0, fa1
 ; CHECK-NEXT:  .LBB10_2:
 ; CHECK-NEXT:    ret
 ;
-; CHECKIZFHMIN-LABEL: select_fcmp_uge:
-; CHECKIZFHMIN:       # %bb.0:
-; CHECKIZFHMIN-NEXT:    fcvt.s.h fa4, fa1
-; CHECKIZFHMIN-NEXT:    fcvt.s.h fa5, fa0
-; CHECKIZFHMIN-NEXT:    flt.s a0, fa5, fa4
-; CHECKIZFHMIN-NEXT:    beqz a0, .LBB10_2
-; CHECKIZFHMIN-NEXT:  # %bb.1:
-; CHECKIZFHMIN-NEXT:    fmv.s fa5, fa4
-; CHECKIZFHMIN-NEXT:  .LBB10_2:
-; CHECKIZFHMIN-NEXT:    fcvt.h.s fa0, fa5
-; CHECKIZFHMIN-NEXT:    ret
+; CHECKIZHINX-LABEL: select_fcmp_uge:
+; CHECKIZHINX:       # %bb.0:
+; CHECKIZHINX-NEXT:    flt.h a2, a0, a1
+; CHECKIZHINX-NEXT:    beqz a2, .LBB10_2
+; CHECKIZHINX-NEXT:  # %bb.1:
+; CHECKIZHINX-NEXT:    mv a0, a1
+; CHECKIZHINX-NEXT:  .LBB10_2:
+; CHECKIZHINX-NEXT:    ret
   %1 = fcmp uge half %a, %b
   %2 = select i1 %1, half %a, half %b
   ret half %2
 }
 
 define half @select_fcmp_ult(half %a, half %b) nounwind {
 ; CHECK-LABEL: select_fcmp_ult:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    fle.h a0, fa1, fa0
 ; CHECK-NEXT:    beqz a0, .LBB11_2
 ; CHECK-NEXT:  # %bb.1:
 ; CHECK-NEXT:    fmv.h fa0, fa1
 ; CHECK-NEXT:  .LBB11_2:
 ; CHECK-NEXT:    ret
 ;
-; CHECKIZFHMIN-LABEL: select_fcmp_ult:
-; CHECKIZFHMIN:       # %bb.0:
-; CHECKIZFHMIN-NEXT:    fcvt.s.h fa5, fa0
-; CHECKIZFHMIN-NEXT:    fcvt.s.h fa4, fa1
-; CHECKIZFHMIN-NEXT:    fle.s a0, fa4, fa5
-; CHECKIZFHMIN-NEXT:    beqz a0, .LBB11_2
-; CHECKIZFHMIN-NEXT:  # %bb.1:
-; CHECKIZFHMIN-NEXT:    fmv.s fa5, fa4
-; CHECKIZFHMIN-NEXT:  .LBB11_2:
-; CHECKIZFHMIN-NEXT:    fcvt.h.s fa0, fa5
-; CHECKIZFHMIN-NEXT:    ret
+; CHECKIZHINX-LABEL: select_fcmp_ult:
+; CHECKIZHINX:       # %bb.0:
+; CHECKIZHINX-NEXT:    fle.h a2, a1, a0
+; CHECKIZHINX-NEXT:    beqz a2, .LBB11_2
+; CHECKIZHINX-NEXT:  # %bb.1:
+; CHECKIZHINX-NEXT:    mv a0, a1
+; CHECKIZHINX-NEXT:  .LBB11_2:
+; CHECKIZHINX-NEXT:    ret
   %1 = fcmp ult half %a, %b
   %2 = select i1 %1, half %a, half %b
   ret half %2
 }
 
 define half @select_fcmp_ule(half %a, half %b) nounwind {
 ; CHECK-LABEL: select_fcmp_ule:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    flt.h a0, fa1, fa0
 ; CHECK-NEXT:    beqz a0, .LBB12_2
 ; CHECK-NEXT:  # %bb.1:
 ; CHECK-NEXT:    fmv.h fa0, fa1
 ; CHECK-NEXT:  .LBB12_2:
 ; CHECK-NEXT:    ret
 ;
-; CHECKIZFHMIN-LABEL: select_fcmp_ule:
-; CHECKIZFHMIN:       # %bb.0:
-; CHECKIZFHMIN-NEXT:    fcvt.s.h fa5, fa0
-; CHECKIZFHMIN-NEXT:    fcvt.s.h fa4, fa1
-; CHECKIZFHMIN-NEXT:    flt.s a0, fa4, fa5
-; CHECKIZFHMIN-NEXT:    beqz a0, .LBB12_2
-; CHECKIZFHMIN-NEXT:  # %bb.1:
-; CHECKIZFHMIN-NEXT:    fmv.s fa5, fa4
-; CHECKIZFHMIN-NEXT:  .LBB12_2:
-; CHECKIZFHMIN-NEXT:    fcvt.h.s fa0, fa5
-; CHECKIZFHMIN-NEXT:    ret
+; CHECKIZHINX-LABEL: select_fcmp_ule:
+; CHECKIZHINX:       # %bb.0:
+; CHECKIZHINX-NEXT:    flt.h a2, a1, a0
+; CHECKIZHINX-NEXT:    beqz a2, .LBB12_2
+; CHECKIZHINX-NEXT:  # %bb.1:
+; CHECKIZHINX-NEXT:    mv a0, a1
+; CHECKIZHINX-NEXT:  .LBB12_2:
+; CHECKIZHINX-NEXT:    ret
   %1 = fcmp ule half %a, %b
   %2 = select i1 %1, half %a, half %b
   ret half %2
 }
 
 define half @select_fcmp_une(half %a, half %b) nounwind {
 ; CHECK-LABEL: select_fcmp_une:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    feq.h a0, fa0, fa1
 ; CHECK-NEXT:    beqz a0, .LBB13_2
 ; CHECK-NEXT:  # %bb.1:
 ; CHECK-NEXT:    fmv.h fa0, fa1
 ; CHECK-NEXT:  .LBB13_2:
 ; CHECK-NEXT:    ret
 ;
-; CHECKIZFHMIN-LABEL: select_fcmp_une:
-; CHECKIZFHMIN:       # %bb.0:
-; CHECKIZFHMIN-NEXT:    fcvt.s.h fa4, fa1
-; CHECKIZFHMIN-NEXT:    fcvt.s.h fa5, fa0
-; CHECKIZFHMIN-NEXT:    feq.s a0, fa5, fa4
-; CHECKIZFHMIN-NEXT:    beqz a0, .LBB13_2
-; CHECKIZFHMIN-NEXT:  # %bb.1:
-; CHECKIZFHMIN-NEXT:    fmv.s fa5, fa4
-; CHECKIZFHMIN-NEXT:  .LBB13_2:
-; CHECKIZFHMIN-NEXT:    fcvt.h.s fa0, fa5
-; CHECKIZFHMIN-NEXT:    ret
+; CHECKIZHINX-LABEL: select_fcmp_une:
+; CHECKIZHINX:       # %bb.0:
+; CHECKIZHINX-NEXT:    feq.h a2, a0, a1
+; CHECKIZHINX-NEXT:    beqz a2, .LBB13_2
+; CHECKIZHINX-NEXT:  # %bb.1:
+; CHECKIZHINX-NEXT:    mv a0, a1
+; CHECKIZHINX-NEXT:  .LBB13_2:
+; CHECKIZHINX-NEXT:    ret
   %1 = fcmp une half %a, %b
   %2 = select i1 %1, half %a, half %b
   ret half %2
 }
 
 define half @select_fcmp_uno(half %a, half %b) nounwind {
 ; CHECK-LABEL: select_fcmp_uno:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    feq.h a0, fa1, fa1
 ; CHECK-NEXT:    feq.h a1, fa0, fa0
 ; CHECK-NEXT:    and a0, a1, a0
 ; CHECK-NEXT:    beqz a0, .LBB14_2
 ; CHECK-NEXT:  # %bb.1:
 ; CHECK-NEXT:    fmv.h fa0, fa1
 ; CHECK-NEXT:  .LBB14_2:
 ; CHECK-NEXT:    ret
 ;
-; CHECKIZFHMIN-LABEL: select_fcmp_uno:
-; CHECKIZFHMIN:       # %bb.0:
-; CHECKIZFHMIN-NEXT:    fcvt.s.h fa5, fa1
-; CHECKIZFHMIN-NEXT:    feq.s a0, fa5, fa5
-; CHECKIZFHMIN-NEXT:    fcvt.s.h fa4, fa0
-; CHECKIZFHMIN-NEXT:    feq.s a1, fa4, fa4
-; CHECKIZFHMIN-NEXT:    and a0, a1, a0
-; CHECKIZFHMIN-NEXT:    beqz a0, .LBB14_2
-; CHECKIZFHMIN-NEXT:  # %bb.1:
-; CHECKIZFHMIN-NEXT:    fmv.s fa4, fa5
-; CHECKIZFHMIN-NEXT:  .LBB14_2:
-; CHECKIZFHMIN-NEXT:    fcvt.h.s fa0, fa4
-; CHECKIZFHMIN-NEXT:    ret
+; CHECKIZHINX-LABEL: select_fcmp_uno:
+; CHECKIZHINX:       # %bb.0:
+; CHECKIZHINX-NEXT:    feq.h a2, a1, a1
+; CHECKIZHINX-NEXT:    feq.h a3, a0, a0
+; CHECKIZHINX-NEXT:    and a2, a3, a2
+; CHECKIZHINX-NEXT:    beqz a2, .LBB14_2
+; CHECKIZHINX-NEXT:  # %bb.1:
+; CHECKIZHINX-NEXT:    mv a0, a1
+; CHECKIZHINX-NEXT:  .LBB14_2:
+; CHECKIZHINX-NEXT:    ret
   %1 = fcmp uno half %a, %b
   %2 = select i1 %1, half %a, half %b
   ret half %2
 }
 
 define half @select_fcmp_true(half %a, half %b) nounwind {
 ; CHECK-LABEL: select_fcmp_true:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    ret
 ;
+; CHECKIZHINX-LABEL: select_fcmp_true:
+; CHECKIZHINX:       # %bb.0:
+; CHECKIZHINX-NEXT:    ret
+;
 ; CHECKIZFHMIN-LABEL: select_fcmp_true:
 ; CHECKIZFHMIN:       # %bb.0:
 ; CHECKIZFHMIN-NEXT:    ret
   %1 = fcmp true half %a, %b
   %2 = select i1 %1, half %a, half %b
   ret half %2
 }
 
 ; Ensure that ISel succeeds for a select+fcmp that has an i32 result type.
 define i32 @i32_select_fcmp_oeq(half %a, half %b, i32 %c, i32 %d) nounwind {
 ; CHECK-LABEL: i32_select_fcmp_oeq:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    feq.h a2, fa0, fa1
 ; CHECK-NEXT:    bnez a2, .LBB16_2
 ; CHECK-NEXT:  # %bb.1:
 ; CHECK-NEXT:    mv a0, a1
 ; CHECK-NEXT:  .LBB16_2:
 ; CHECK-NEXT:    ret
 ;
-; CHECKIZFHMIN-LABEL: i32_select_fcmp_oeq:
-; CHECKIZFHMIN:       # %bb.0:
-; CHECKIZFHMIN-NEXT:    fcvt.s.h fa5, fa1
-; CHECKIZFHMIN-NEXT:    fcvt.s.h fa4, fa0
-; CHECKIZFHMIN-NEXT:    feq.s a2, fa4, fa5
-; CHECKIZFHMIN-NEXT:    bnez a2, .LBB16_2
-; CHECKIZFHMIN-NEXT:  # %bb.1:
-; CHECKIZFHMIN-NEXT:    mv a0, a1
-; CHECKIZFHMIN-NEXT:  .LBB16_2:
-; CHECKIZFHMIN-NEXT:    ret
+; CHECKIZHINX-LABEL: i32_select_fcmp_oeq:
+; CHECKIZHINX:       # %bb.0:
+; CHECKIZHINX-NEXT:    feq.h a1, a0, a1
+; CHECKIZHINX-NEXT:    mv a0, a2
+; CHECKIZHINX-NEXT:    bnez a1, .LBB16_2
+; CHECKIZHINX-NEXT:  # %bb.1:
+; CHECKIZHINX-NEXT:    mv a0, a3
+; CHECKIZHINX-NEXT:  .LBB16_2:
+; CHECKIZHINX-NEXT:    ret
   %1 = fcmp oeq half %a, %b
   %2 = select i1 %1, i32 %c, i32 %d
   ret i32 %2
 }
 
 define i32 @select_fcmp_oeq_1_2(half %a, half %b) {
 ; CHECK-LABEL: select_fcmp_oeq_1_2:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    feq.h a0, fa0, fa1
 ; CHECK-NEXT:    li a1, 2
 ; CHECK-NEXT:    sub a0, a1, a0
 ; CHECK-NEXT:    ret
 ;
-; CHECKIZFHMIN-LABEL: select_fcmp_oeq_1_2:
-; CHECKIZFHMIN:       # %bb.0:
-; CHECKIZFHMIN-NEXT:    fcvt.s.h fa5, fa1
-; CHECKIZFHMIN-NEXT:    fcvt.s.h fa4, fa0
-; CHECKIZFHMIN-NEXT:    feq.s a0, fa4, fa5
-; CHECKIZFHMIN-NEXT:    li a1, 2
-; CHECKIZFHMIN-NEXT:    sub a0, a1, a0
-; CHECKIZFHMIN-NEXT:    ret
+; CHECKIZHINX-LABEL: select_fcmp_oeq_1_2:
+; CHECKIZHINX:       # %bb.0:
+; CHECKIZHINX-NEXT:    feq.h a0, a0, a1
+; CHECKIZHINX-NEXT:    li a1, 2
+; CHECKIZHINX-NEXT:    sub a0, a1, a0
+; CHECKIZHINX-NEXT:    ret
   %1 = fcmp fast oeq half %a, %b
   %2 = select i1 %1, i32 1, i32 2
   ret i32 %2
 }
 
 define signext i32 @select_fcmp_uge_negone_zero(half %a, half %b) nounwind {
 ; CHECK-LABEL: select_fcmp_uge_negone_zero:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    fle.h a0, fa0, fa1
 ; CHECK-NEXT:    addi a0, a0, -1
 ; CHECK-NEXT:    ret
 ;
-; CHECKIZFHMIN-LABEL: select_fcmp_uge_negone_zero:
-; CHECKIZFHMIN:       # %bb.0:
-; CHECKIZFHMIN-NEXT:    fcvt.s.h fa5, fa1
-; CHECKIZFHMIN-NEXT:    fcvt.s.h fa4, fa0
-; CHECKIZFHMIN-NEXT:    fle.s a0, fa4, fa5
-; CHECKIZFHMIN-NEXT:    addi a0, a0, -1
-; CHECKIZFHMIN-NEXT:    ret
+; CHECKIZHINX-LABEL: select_fcmp_uge_negone_zero:
+; CHECKIZHINX:       # %bb.0:
+; CHECKIZHINX-NEXT:    fle.h a0, a0, a1
+; CHECKIZHINX-NEXT:    addi a0, a0, -1
+; CHECKIZHINX-NEXT:    ret
   %1 = fcmp ugt half %a, %b
   %2 = select i1 %1, i32 -1, i32 0
   ret i32 %2
 }
 
 define signext i32 @select_fcmp_uge_1_2(half %a, half %b) nounwind {
 ; CHECK-LABEL: select_fcmp_uge_1_2:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    fle.h a0, fa0, fa1
 ; CHECK-NEXT:    addi a0, a0, 1
 ; CHECK-NEXT:    ret
 ;
-; CHECKIZFHMIN-LABEL: select_fcmp_uge_1_2:
-; CHECKIZFHMIN:       # %bb.0:
-; CHECKIZFHMIN-NEXT:    fcvt.s.h fa5, fa1
-; CHECKIZFHMIN-NEXT:    fcvt.s.h fa4, fa0
-; CHECKIZFHMIN-NEXT:    fle.s a0, fa4, fa5
-; CHECKIZFHMIN-NEXT:    addi a0, a0, 1
-; CHECKIZFHMIN-NEXT:    ret
+; CHECKIZHINX-LABEL: select_fcmp_uge_1_2:
+; CHECKIZHINX:       # %bb.0:
+; CHECKIZHINX-NEXT:    fle.h a0, a0, a1
+; CHECKIZHINX-NEXT:    addi a0, a0, 1
+; CHECKIZHINX-NEXT:    ret
   %1 = fcmp ugt half %a, %b
   %2 = select i1 %1, i32 1, i32 2
   ret i32 %2
 }

llvm/test/CodeGen/RISCV/half-select-icmp.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -mattr=+zfh -verify-machineinstrs \
 ; RUN:   -target-abi ilp32f < %s | FileCheck %s
 ; RUN: llc -mtriple=riscv64 -mattr=+zfh -verify-machineinstrs \
 ; RUN:   -target-abi lp64f < %s | FileCheck %s
+; RUN: llc -mtriple=riscv32 -mattr=+zhinx -verify-machineinstrs \
+; RUN:   -target-abi ilp32 < %s | FileCheck -check-prefix=CHECKIZHINX %s
+; RUN: llc -mtriple=riscv64 -mattr=+zhinx -verify-machineinstrs \
+; RUN:   -target-abi lp64 < %s | FileCheck -check-prefix=CHECKIZHINX %s
 ; RUN: llc -mtriple=riscv32 -mattr=+zfhmin -verify-machineinstrs < %s \
 ; RUN:   -target-abi=ilp32f | FileCheck -check-prefix=CHECKIZFHMIN %s
 ; RUN: llc -mtriple=riscv64 -mattr=+zfhmin -verify-machineinstrs < %s \
 ; RUN:   -target-abi=lp64f | FileCheck -check-prefix=CHECKIZFHMIN %s
+; RUN: llc -mtriple=riscv32 -mattr=+zhinxmin -verify-machineinstrs < %s \
+; RUN:   -target-abi=ilp32 | FileCheck -check-prefix=CHECKIZHINXMIN %s
+; RUN: llc -mtriple=riscv64 -mattr=+zhinxmin -verify-machineinstrs < %s \
+; RUN:   -target-abi=lp64 | FileCheck -check-prefix=CHECKIZHINXMIN %s
 
 define half @select_icmp_eq(i32 signext %a, i32 signext %b, half %c, half %d) {
 ; CHECK-LABEL: select_icmp_eq:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    beq a0, a1, .LBB0_2
 ; CHECK-NEXT:  # %bb.1:
 ; CHECK-NEXT:    fmv.h fa0, fa1
 ; CHECK-NEXT:  .LBB0_2:
 ; CHECK-NEXT:    ret
 ;
+; CHECKIZHINX-LABEL: select_icmp_eq:
+; CHECKIZHINX:       # %bb.0:
+; CHECKIZHINX-NEXT:    beq a0, a1, .LBB0_2
+; CHECKIZHINX-NEXT:  # %bb.1:
+; CHECKIZHINX-NEXT:    mv a2, a3
+; CHECKIZHINX-NEXT:  .LBB0_2:
+; CHECKIZHINX-NEXT:    mv a0, a2
+; CHECKIZHINX-NEXT:    ret
+;
 ; CHECKIZFHMIN-LABEL: select_icmp_eq:
 ; CHECKIZFHMIN:       # %bb.0:
 ; CHECKIZFHMIN-NEXT:    beq a0, a1, .LBB0_2
 ; CHECKIZFHMIN-NEXT:  # %bb.1:
 ; CHECKIZFHMIN-NEXT:    fcvt.s.h fa5, fa1
 ; CHECKIZFHMIN-NEXT:    fcvt.h.s fa0, fa5
 ; CHECKIZFHMIN-NEXT:    ret
 ; CHECKIZFHMIN-NEXT:  .LBB0_2:
 ; CHECKIZFHMIN-NEXT:    fcvt.s.h fa5, fa0
 ; CHECKIZFHMIN-NEXT:    fcvt.h.s fa0, fa5
 ; CHECKIZFHMIN-NEXT:    ret
+;
+; CHECKIZHINXMIN-LABEL: select_icmp_eq:
+; CHECKIZHINXMIN:       # %bb.0:
+; CHECKIZHINXMIN-NEXT:    beq a0, a1, .LBB0_2
+; CHECKIZHINXMIN-NEXT:  # %bb.1:
+; CHECKIZHINXMIN-NEXT:    fcvt.s.h a0, a3
+; CHECKIZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; CHECKIZHINXMIN-NEXT:    ret
+; CHECKIZHINXMIN-NEXT:  .LBB0_2:
+; CHECKIZHINXMIN-NEXT:    fcvt.s.h a0, a2
+; CHECKIZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; CHECKIZHINXMIN-NEXT:    ret
   %1 = icmp eq i32 %a, %b
   %2 = select i1 %1, half %c, half %d
   ret half %2
 }
 
 define half @select_icmp_ne(i32 signext %a, i32 signext %b, half %c, half %d) {
 ; CHECK-LABEL: select_icmp_ne:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    bne a0, a1, .LBB1_2
 ; CHECK-NEXT:  # %bb.1:
 ; CHECK-NEXT:    fmv.h fa0, fa1
 ; CHECK-NEXT:  .LBB1_2:
 ; CHECK-NEXT:    ret
 ;
+; CHECKIZHINX-LABEL: select_icmp_ne:
+; CHECKIZHINX:       # %bb.0:
+; CHECKIZHINX-NEXT:    bne a0, a1, .LBB1_2
+; CHECKIZHINX-NEXT:  # %bb.1:
+; CHECKIZHINX-NEXT:    mv a2, a3
+; CHECKIZHINX-NEXT:  .LBB1_2:
+; CHECKIZHINX-NEXT:    mv a0, a2
+; CHECKIZHINX-NEXT:    ret
+;
 ; CHECKIZFHMIN-LABEL: select_icmp_ne:
 ; CHECKIZFHMIN:       # %bb.0:
 ; CHECKIZFHMIN-NEXT:    bne a0, a1, .LBB1_2
 ; CHECKIZFHMIN-NEXT:  # %bb.1:
 ; CHECKIZFHMIN-NEXT:    fcvt.s.h fa5, fa1
 ; CHECKIZFHMIN-NEXT:    fcvt.h.s fa0, fa5
 ; CHECKIZFHMIN-NEXT:    ret
 ; CHECKIZFHMIN-NEXT:  .LBB1_2:
 ; CHECKIZFHMIN-NEXT:    fcvt.s.h fa5, fa0
 ; CHECKIZFHMIN-NEXT:    fcvt.h.s fa0, fa5
 ; CHECKIZFHMIN-NEXT:    ret
+;
+; CHECKIZHINXMIN-LABEL: select_icmp_ne:
+; CHECKIZHINXMIN:       # %bb.0:
+; CHECKIZHINXMIN-NEXT:    bne a0, a1, .LBB1_2
+; CHECKIZHINXMIN-NEXT:  # %bb.1:
+; CHECKIZHINXMIN-NEXT:    fcvt.s.h a0, a3
+; CHECKIZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; CHECKIZHINXMIN-NEXT:    ret
+; CHECKIZHINXMIN-NEXT:  .LBB1_2:
+; CHECKIZHINXMIN-NEXT:    fcvt.s.h a0, a2
+; CHECKIZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; CHECKIZHINXMIN-NEXT:    ret
   %1 = icmp ne i32 %a, %b
   %2 = select i1 %1, half %c, half %d
   ret half %2
 }
 
 define half @select_icmp_ugt(i32 signext %a, i32 signext %b, half %c, half %d) {
 ; CHECK-LABEL: select_icmp_ugt:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    bltu a1, a0, .LBB2_2
 ; CHECK-NEXT:  # %bb.1:
 ; CHECK-NEXT:    fmv.h fa0, fa1
 ; CHECK-NEXT:  .LBB2_2:
 ; CHECK-NEXT:    ret
 ;
+; CHECKIZHINX-LABEL: select_icmp_ugt:
+; CHECKIZHINX:       # %bb.0:
+; CHECKIZHINX-NEXT:    bltu a1, a0, .LBB2_2
+; CHECKIZHINX-NEXT:  # %bb.1:
+; CHECKIZHINX-NEXT:    mv a2, a3
+; CHECKIZHINX-NEXT:  .LBB2_2:
+; CHECKIZHINX-NEXT:    mv a0, a2
+; CHECKIZHINX-NEXT:    ret
+;
 ; CHECKIZFHMIN-LABEL: select_icmp_ugt:
 ; CHECKIZFHMIN:       # %bb.0:
 ; CHECKIZFHMIN-NEXT:    bltu a1, a0, .LBB2_2
 ; CHECKIZFHMIN-NEXT:  # %bb.1:
 ; CHECKIZFHMIN-NEXT:    fcvt.s.h fa5, fa1
 ; CHECKIZFHMIN-NEXT:    fcvt.h.s fa0, fa5
 ; CHECKIZFHMIN-NEXT:    ret
 ; CHECKIZFHMIN-NEXT:  .LBB2_2:
 ; CHECKIZFHMIN-NEXT:    fcvt.s.h fa5, fa0
 ; CHECKIZFHMIN-NEXT:    fcvt.h.s fa0, fa5
 ; CHECKIZFHMIN-NEXT:    ret
+;
+; CHECKIZHINXMIN-LABEL: select_icmp_ugt:
+; CHECKIZHINXMIN:       # %bb.0:
+; CHECKIZHINXMIN-NEXT:    bltu a1, a0, .LBB2_2
+; CHECKIZHINXMIN-NEXT:  # %bb.1:
+; CHECKIZHINXMIN-NEXT:    fcvt.s.h a0, a3
+; CHECKIZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; CHECKIZHINXMIN-NEXT:    ret
+; CHECKIZHINXMIN-NEXT:  .LBB2_2:
+; CHECKIZHINXMIN-NEXT:    fcvt.s.h a0, a2
+; CHECKIZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; CHECKIZHINXMIN-NEXT:    ret
   %1 = icmp ugt i32 %a, %b
   %2 = select i1 %1, half %c, half %d
   ret half %2
 }
 
 define half @select_icmp_uge(i32 signext %a, i32 signext %b, half %c, half %d) {
 ; CHECK-LABEL: select_icmp_uge:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    bgeu a0, a1, .LBB3_2
 ; CHECK-NEXT:  # %bb.1:
 ; CHECK-NEXT:    fmv.h fa0, fa1
 ; CHECK-NEXT:  .LBB3_2:
 ; CHECK-NEXT:    ret
 ;
+; CHECKIZHINX-LABEL: select_icmp_uge:
+; CHECKIZHINX:       # %bb.0:
+; CHECKIZHINX-NEXT:    bgeu a0, a1, .LBB3_2
+; CHECKIZHINX-NEXT:  # %bb.1:
+; CHECKIZHINX-NEXT:    mv a2, a3
+; CHECKIZHINX-NEXT:  .LBB3_2:
+; CHECKIZHINX-NEXT:    mv a0, a2
+; CHECKIZHINX-NEXT:    ret
+;
 ; CHECKIZFHMIN-LABEL: select_icmp_uge:
 ; CHECKIZFHMIN:       # %bb.0:
 ; CHECKIZFHMIN-NEXT:    bgeu a0, a1, .LBB3_2
 ; CHECKIZFHMIN-NEXT:  # %bb.1:
 ; CHECKIZFHMIN-NEXT:    fcvt.s.h fa5, fa1
 ; CHECKIZFHMIN-NEXT:    fcvt.h.s fa0, fa5
 ; CHECKIZFHMIN-NEXT:    ret
 ; CHECKIZFHMIN-NEXT:  .LBB3_2:
 ; CHECKIZFHMIN-NEXT:    fcvt.s.h fa5, fa0
 ; CHECKIZFHMIN-NEXT:    fcvt.h.s fa0, fa5
 ; CHECKIZFHMIN-NEXT:    ret
+;
+; CHECKIZHINXMIN-LABEL: select_icmp_uge:
+; CHECKIZHINXMIN:       # %bb.0:
+; CHECKIZHINXMIN-NEXT:    bgeu a0, a1, .LBB3_2
+; CHECKIZHINXMIN-NEXT:  # %bb.1:
+; CHECKIZHINXMIN-NEXT:    fcvt.s.h a0, a3
+; CHECKIZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; CHECKIZHINXMIN-NEXT:    ret
+; CHECKIZHINXMIN-NEXT:  .LBB3_2:
+; CHECKIZHINXMIN-NEXT:    fcvt.s.h a0, a2
+; CHECKIZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; CHECKIZHINXMIN-NEXT:    ret
   %1 = icmp uge i32 %a, %b
   %2 = select i1 %1, half %c, half %d
   ret half %2
 }
 
 define half @select_icmp_ult(i32 signext %a, i32 signext %b, half %c, half %d) {
 ; CHECK-LABEL: select_icmp_ult:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    bltu a0, a1, .LBB4_2
 ; CHECK-NEXT:  # %bb.1:
 ; CHECK-NEXT:    fmv.h fa0, fa1
 ; CHECK-NEXT:  .LBB4_2:
 ; CHECK-NEXT:    ret
 ;
+; CHECKIZHINX-LABEL: select_icmp_ult:
+; CHECKIZHINX:       # %bb.0:
+; CHECKIZHINX-NEXT:    bltu a0, a1, .LBB4_2
+; CHECKIZHINX-NEXT:  # %bb.1:
+; CHECKIZHINX-NEXT:    mv a2, a3
+; CHECKIZHINX-NEXT:  .LBB4_2:
+; CHECKIZHINX-NEXT:    mv a0, a2
+; CHECKIZHINX-NEXT:    ret
+;
 ; CHECKIZFHMIN-LABEL: select_icmp_ult:
 ; CHECKIZFHMIN:       # %bb.0:
 ; CHECKIZFHMIN-NEXT:    bltu a0, a1, .LBB4_2
 ; CHECKIZFHMIN-NEXT:  # %bb.1:
 ; CHECKIZFHMIN-NEXT:    fcvt.s.h fa5, fa1
 ; CHECKIZFHMIN-NEXT:    fcvt.h.s fa0, fa5
 ; CHECKIZFHMIN-NEXT:    ret
 ; CHECKIZFHMIN-NEXT:  .LBB4_2:
 ; CHECKIZFHMIN-NEXT:    fcvt.s.h fa5, fa0
 ; CHECKIZFHMIN-NEXT:    fcvt.h.s fa0, fa5
 ; CHECKIZFHMIN-NEXT:    ret
+;
+; CHECKIZHINXMIN-LABEL: select_icmp_ult:
+; CHECKIZHINXMIN:       # %bb.0:
+; CHECKIZHINXMIN-NEXT:    bltu a0, a1, .LBB4_2
+; CHECKIZHINXMIN-NEXT:  # %bb.1:
+; CHECKIZHINXMIN-NEXT:    fcvt.s.h a0, a3
+; CHECKIZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; CHECKIZHINXMIN-NEXT:    ret
+; CHECKIZHINXMIN-NEXT:  .LBB4_2:
+; CHECKIZHINXMIN-NEXT:    fcvt.s.h a0, a2
+; CHECKIZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; CHECKIZHINXMIN-NEXT:    ret
   %1 = icmp ult i32 %a, %b
   %2 = select i1 %1, half %c, half %d
   ret half %2
 }
 
 define half @select_icmp_ule(i32 signext %a, i32 signext %b, half %c, half %d) {
 ; CHECK-LABEL: select_icmp_ule:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    bgeu a1, a0, .LBB5_2
 ; CHECK-NEXT:  # %bb.1:
 ; CHECK-NEXT:    fmv.h fa0, fa1
 ; CHECK-NEXT:  .LBB5_2:
 ; CHECK-NEXT:    ret
 ;
+; CHECKIZHINX-LABEL: select_icmp_ule:
+; CHECKIZHINX:       # %bb.0:
+; CHECKIZHINX-NEXT:    bgeu a1, a0, .LBB5_2
+; CHECKIZHINX-NEXT:  # %bb.1:
+; CHECKIZHINX-NEXT:    mv a2, a3
+; CHECKIZHINX-NEXT:  .LBB5_2:
+; CHECKIZHINX-NEXT:    mv a0, a2
+; CHECKIZHINX-NEXT:    ret
+;
 ; CHECKIZFHMIN-LABEL: select_icmp_ule:
 ; CHECKIZFHMIN:       # %bb.0:
 ; CHECKIZFHMIN-NEXT:    bgeu a1, a0, .LBB5_2
 ; CHECKIZFHMIN-NEXT:  # %bb.1:
 ; CHECKIZFHMIN-NEXT:    fcvt.s.h fa5, fa1
 ; CHECKIZFHMIN-NEXT:    fcvt.h.s fa0, fa5
 ; CHECKIZFHMIN-NEXT:    ret
 ; CHECKIZFHMIN-NEXT:  .LBB5_2:
 ; CHECKIZFHMIN-NEXT:    fcvt.s.h fa5, fa0
 ; CHECKIZFHMIN-NEXT:    fcvt.h.s fa0, fa5
 ; CHECKIZFHMIN-NEXT:    ret
+;
+; CHECKIZHINXMIN-LABEL: select_icmp_ule:
+; CHECKIZHINXMIN:       # %bb.0:
+; CHECKIZHINXMIN-NEXT:    bgeu a1, a0, .LBB5_2
+; CHECKIZHINXMIN-NEXT:  # %bb.1:
+; CHECKIZHINXMIN-NEXT:    fcvt.s.h a0, a3
+; CHECKIZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; CHECKIZHINXMIN-NEXT:    ret
+; CHECKIZHINXMIN-NEXT:  .LBB5_2:
+; CHECKIZHINXMIN-NEXT:    fcvt.s.h a0, a2
+; CHECKIZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; CHECKIZHINXMIN-NEXT:    ret
   %1 = icmp ule i32 %a, %b
   %2 = select i1 %1, half %c, half %d
   ret half %2
 }
 
 define half @select_icmp_sgt(i32 signext %a, i32 signext %b, half %c, half %d) {
 ; CHECK-LABEL: select_icmp_sgt:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    blt a1, a0, .LBB6_2
 ; CHECK-NEXT:  # %bb.1:
 ; CHECK-NEXT:    fmv.h fa0, fa1
 ; CHECK-NEXT:  .LBB6_2:
 ; CHECK-NEXT:    ret
 ;
+; CHECKIZHINX-LABEL: select_icmp_sgt:
+; CHECKIZHINX:       # %bb.0:
+; CHECKIZHINX-NEXT:    blt a1, a0, .LBB6_2
+; CHECKIZHINX-NEXT:  # %bb.1:
+; CHECKIZHINX-NEXT:    mv a2, a3
+; CHECKIZHINX-NEXT:  .LBB6_2:
+; CHECKIZHINX-NEXT:    mv a0, a2
+; CHECKIZHINX-NEXT:    ret
+;
 ; CHECKIZFHMIN-LABEL: select_icmp_sgt:
 ; CHECKIZFHMIN:       # %bb.0:
 ; CHECKIZFHMIN-NEXT:    blt a1, a0, .LBB6_2
 ; CHECKIZFHMIN-NEXT:  # %bb.1:
 ; CHECKIZFHMIN-NEXT:    fcvt.s.h fa5, fa1
 ; CHECKIZFHMIN-NEXT:    fcvt.h.s fa0, fa5
 ; CHECKIZFHMIN-NEXT:    ret
 ; CHECKIZFHMIN-NEXT:  .LBB6_2:
 ; CHECKIZFHMIN-NEXT:    fcvt.s.h fa5, fa0
 ; CHECKIZFHMIN-NEXT:    fcvt.h.s fa0, fa5
 ; CHECKIZFHMIN-NEXT:    ret
+;
+; CHECKIZHINXMIN-LABEL: select_icmp_sgt:
+; CHECKIZHINXMIN:       # %bb.0:
+; CHECKIZHINXMIN-NEXT:    blt a1, a0, .LBB6_2
+; CHECKIZHINXMIN-NEXT:  # %bb.1:
+; CHECKIZHINXMIN-NEXT:    fcvt.s.h a0, a3
+; CHECKIZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; CHECKIZHINXMIN-NEXT:    ret
+; CHECKIZHINXMIN-NEXT:  .LBB6_2:
+; CHECKIZHINXMIN-NEXT:    fcvt.s.h a0, a2
+; CHECKIZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; CHECKIZHINXMIN-NEXT:    ret
   %1 = icmp sgt i32 %a, %b
   %2 = select i1 %1, half %c, half %d
   ret half %2
 }
 
 define half @select_icmp_sge(i32 signext %a, i32 signext %b, half %c, half %d) {
 ; CHECK-LABEL: select_icmp_sge:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    bge a0, a1, .LBB7_2
 ; CHECK-NEXT:  # %bb.1:
 ; CHECK-NEXT:    fmv.h fa0, fa1
 ; CHECK-NEXT:  .LBB7_2:
 ; CHECK-NEXT:    ret
 ;
+; CHECKIZHINX-LABEL: select_icmp_sge:
+; CHECKIZHINX:       # %bb.0:
+; CHECKIZHINX-NEXT:    bge a0, a1, .LBB7_2
+; CHECKIZHINX-NEXT:  # %bb.1:
+; CHECKIZHINX-NEXT:    mv a2, a3
+; CHECKIZHINX-NEXT:  .LBB7_2:
+; CHECKIZHINX-NEXT:    mv a0, a2
+; CHECKIZHINX-NEXT:    ret
+;
 ; CHECKIZFHMIN-LABEL: select_icmp_sge:
 ; CHECKIZFHMIN:       # %bb.0:
 ; CHECKIZFHMIN-NEXT:    bge a0, a1, .LBB7_2
 ; CHECKIZFHMIN-NEXT:  # %bb.1:
 ; CHECKIZFHMIN-NEXT:    fcvt.s.h fa5, fa1
 ; CHECKIZFHMIN-NEXT:    fcvt.h.s fa0, fa5
 ; CHECKIZFHMIN-NEXT:    ret
 ; CHECKIZFHMIN-NEXT:  .LBB7_2:
 ; CHECKIZFHMIN-NEXT:    fcvt.s.h fa5, fa0
 ; CHECKIZFHMIN-NEXT:    fcvt.h.s fa0, fa5
 ; CHECKIZFHMIN-NEXT:    ret
+;
+; CHECKIZHINXMIN-LABEL: select_icmp_sge:
+; CHECKIZHINXMIN:       # %bb.0:
+; CHECKIZHINXMIN-NEXT:    bge a0, a1, .LBB7_2
+; CHECKIZHINXMIN-NEXT:  # %bb.1:
+; CHECKIZHINXMIN-NEXT:    fcvt.s.h a0, a3
+; CHECKIZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; CHECKIZHINXMIN-NEXT:    ret
+; CHECKIZHINXMIN-NEXT:  .LBB7_2:
+; CHECKIZHINXMIN-NEXT:    fcvt.s.h a0, a2
+; CHECKIZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; CHECKIZHINXMIN-NEXT:    ret
   %1 = icmp sge i32 %a, %b
   %2 = select i1 %1, half %c, half %d
   ret half %2
 }
 
 define half @select_icmp_slt(i32 signext %a, i32 signext %b, half %c, half %d) {
 ; CHECK-LABEL: select_icmp_slt:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    blt a0, a1, .LBB8_2
 ; CHECK-NEXT:  # %bb.1:
 ; CHECK-NEXT:    fmv.h fa0, fa1
 ; CHECK-NEXT:  .LBB8_2:
 ; CHECK-NEXT:    ret
 ;
+; CHECKIZHINX-LABEL: select_icmp_slt:
+; CHECKIZHINX:       # %bb.0:
+; CHECKIZHINX-NEXT:    blt a0, a1, .LBB8_2
+; CHECKIZHINX-NEXT:  # %bb.1:
+; CHECKIZHINX-NEXT:    mv a2, a3
+; CHECKIZHINX-NEXT:  .LBB8_2:
+; CHECKIZHINX-NEXT:    mv a0, a2
+; CHECKIZHINX-NEXT:    ret
+;
 ; CHECKIZFHMIN-LABEL: select_icmp_slt:
 ; CHECKIZFHMIN:       # %bb.0:
 ; CHECKIZFHMIN-NEXT:    blt a0, a1, .LBB8_2
 ; CHECKIZFHMIN-NEXT:  # %bb.1:
 ; CHECKIZFHMIN-NEXT:    fcvt.s.h fa5, fa1
 ; CHECKIZFHMIN-NEXT:    fcvt.h.s fa0, fa5
 ; CHECKIZFHMIN-NEXT:    ret
 ; CHECKIZFHMIN-NEXT:  .LBB8_2:
 ; CHECKIZFHMIN-NEXT:    fcvt.s.h fa5, fa0
 ; CHECKIZFHMIN-NEXT:    fcvt.h.s fa0, fa5
 ; CHECKIZFHMIN-NEXT:    ret
+;
+; CHECKIZHINXMIN-LABEL: select_icmp_slt:
+; CHECKIZHINXMIN:       # %bb.0:
+; CHECKIZHINXMIN-NEXT:    blt a0, a1, .LBB8_2
+; CHECKIZHINXMIN-NEXT:  # %bb.1:
+; CHECKIZHINXMIN-NEXT:    fcvt.s.h a0, a3
+; CHECKIZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; CHECKIZHINXMIN-NEXT:    ret
+; CHECKIZHINXMIN-NEXT:  .LBB8_2:
+; CHECKIZHINXMIN-NEXT:    fcvt.s.h a0, a2
+; CHECKIZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; CHECKIZHINXMIN-NEXT:    ret
   %1 = icmp slt i32 %a, %b
   %2 = select i1 %1, half %c, half %d
   ret half %2
 }
 
 define half @select_icmp_sle(i32 signext %a, i32 signext %b, half %c, half %d) {
 ; CHECK-LABEL: select_icmp_sle:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    bge a1, a0, .LBB9_2
 ; CHECK-NEXT:  # %bb.1:
 ; CHECK-NEXT:    fmv.h fa0, fa1
 ; CHECK-NEXT:  .LBB9_2:
 ; CHECK-NEXT:    ret
 ;
+; CHECKIZHINX-LABEL: select_icmp_sle:
+; CHECKIZHINX:       # %bb.0:
+; CHECKIZHINX-NEXT:    bge a1, a0, .LBB9_2
+; CHECKIZHINX-NEXT:  # %bb.1:
+; CHECKIZHINX-NEXT:    mv a2, a3
+; CHECKIZHINX-NEXT:  .LBB9_2:
+; CHECKIZHINX-NEXT:    mv a0, a2
+; CHECKIZHINX-NEXT:    ret
+;
 ; CHECKIZFHMIN-LABEL: select_icmp_sle:
 ; CHECKIZFHMIN:       # %bb.0:
 ; CHECKIZFHMIN-NEXT:    bge a1, a0, .LBB9_2
 ; CHECKIZFHMIN-NEXT:  # %bb.1:
 ; CHECKIZFHMIN-NEXT:    fcvt.s.h fa5, fa1
 ; CHECKIZFHMIN-NEXT:    fcvt.h.s fa0, fa5
 ; CHECKIZFHMIN-NEXT:    ret
 ; CHECKIZFHMIN-NEXT:  .LBB9_2:
 ; CHECKIZFHMIN-NEXT:    fcvt.s.h fa5, fa0
 ; CHECKIZFHMIN-NEXT:    fcvt.h.s fa0, fa5
 ; CHECKIZFHMIN-NEXT:    ret
+;
+; CHECKIZHINXMIN-LABEL: select_icmp_sle:
+; CHECKIZHINXMIN:       # %bb.0:
+; CHECKIZHINXMIN-NEXT:    bge a1, a0, .LBB9_2
+; CHECKIZHINXMIN-NEXT:  # %bb.1:
+; CHECKIZHINXMIN-NEXT:    fcvt.s.h a0, a3
+; CHECKIZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; CHECKIZHINXMIN-NEXT:    ret
+; CHECKIZHINXMIN-NEXT:  .LBB9_2:
+; CHECKIZHINXMIN-NEXT:    fcvt.s.h a0, a2
+; CHECKIZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; CHECKIZHINXMIN-NEXT:    ret
   %1 = icmp sle i32 %a, %b
   %2 = select i1 %1, half %c, half %d
   ret half %2
 }

llvm/test/CodeGen/RISCV/rv64zfh-half-convert-strict.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv64 -mattr=+zfh -verify-machineinstrs \
 ; RUN:   -target-abi lp64f -disable-strictnode-mutation < %s | \
 ; RUN:   FileCheck %s -check-prefix=RV64IZFH
+; RUN: llc -mtriple=riscv64 -mattr=+zhinx -verify-machineinstrs \
+; RUN:   -target-abi lp64 -disable-strictnode-mutation < %s | \
+; RUN:   FileCheck %s -check-prefix=RV64IZHINX
 
 ; This file exhaustively checks half<->i32 conversions. In general,
 ; fcvt.l[u].h can be selected instead of fcvt.w[u].h because poison is
 ; generated for an fpto[s|u]i conversion if the result doesn't fit in the
 ; target type.
 
 define i32 @aext_fptosi(half %a) nounwind {
 ; RV64IZFH-LABEL: aext_fptosi:
 ; RV64IZFH:       # %bb.0:
 ; RV64IZFH-NEXT:    fcvt.w.h a0, fa0, rtz
 ; RV64IZFH-NEXT:    ret
+;
+; RV64IZHINX-LABEL: aext_fptosi:
+; RV64IZHINX:       # %bb.0:
+; RV64IZHINX-NEXT:    fcvt.w.h a0, a0, rtz
+; RV64IZHINX-NEXT:    ret
   %1 = call i32 @llvm.experimental.constrained.fptosi.i32.f16(half %a, metadata !"fpexcept.strict") strictfp
   ret i32 %1
 }
 declare i32 @llvm.experimental.constrained.fptosi.i32.f16(half, metadata)
 
 define signext i32 @sext_fptosi(half %a) nounwind {
 ; RV64IZFH-LABEL: sext_fptosi:
 ; RV64IZFH:       # %bb.0:
 ; RV64IZFH-NEXT:    fcvt.w.h a0, fa0, rtz
 ; RV64IZFH-NEXT:    ret
+;
+; RV64IZHINX-LABEL: sext_fptosi:
+; RV64IZHINX:       # %bb.0:
+; RV64IZHINX-NEXT:    fcvt.w.h a0, a0, rtz
+; RV64IZHINX-NEXT:    ret
   %1 = call i32 @llvm.experimental.constrained.fptosi.i32.f16(half %a, metadata !"fpexcept.strict") strictfp
   ret i32 %1
 }
 
 define zeroext i32 @zext_fptosi(half %a) nounwind {
 ; RV64IZFH-LABEL: zext_fptosi:
 ; RV64IZFH:       # %bb.0:
 ; RV64IZFH-NEXT:    fcvt.w.h a0, fa0, rtz
 ; RV64IZFH-NEXT:    slli a0, a0, 32
 ; RV64IZFH-NEXT:    srli a0, a0, 32
 ; RV64IZFH-NEXT:    ret
+;
+; RV64IZHINX-LABEL: zext_fptosi:
+; RV64IZHINX:       # %bb.0:
+; RV64IZHINX-NEXT:    fcvt.w.h a0, a0, rtz
+; RV64IZHINX-NEXT:    slli a0, a0, 32
+; RV64IZHINX-NEXT:    srli a0, a0, 32
+; RV64IZHINX-NEXT:    ret
   %1 = call i32 @llvm.experimental.constrained.fptosi.i32.f16(half %a, metadata !"fpexcept.strict") strictfp
   ret i32 %1
 }
 
 define i32 @aext_fptoui(half %a) nounwind {
 ; RV64IZFH-LABEL: aext_fptoui:
 ; RV64IZFH:       # %bb.0:
 ; RV64IZFH-NEXT:    fcvt.wu.h a0, fa0, rtz
 ; RV64IZFH-NEXT:    ret
+;
+; RV64IZHINX-LABEL: aext_fptoui:
+; RV64IZHINX:       # %bb.0:
+; RV64IZHINX-NEXT:    fcvt.wu.h a0, a0, rtz
+; RV64IZHINX-NEXT:    ret
   %1 = call i32 @llvm.experimental.constrained.fptoui.i32.f16(half %a, metadata !"fpexcept.strict") strictfp
   ret i32 %1
 }
 declare i32 @llvm.experimental.constrained.fptoui.i32.f16(half, metadata)
 
 define signext i32 @sext_fptoui(half %a) nounwind {
 ; RV64IZFH-LABEL: sext_fptoui:
 ; RV64IZFH:       # %bb.0:
 ; RV64IZFH-NEXT:    fcvt.wu.h a0, fa0, rtz
 ; RV64IZFH-NEXT:    ret
+;
+; RV64IZHINX-LABEL: sext_fptoui:
+; RV64IZHINX:       # %bb.0:
+; RV64IZHINX-NEXT:    fcvt.wu.h a0, a0, rtz
+; RV64IZHINX-NEXT:    ret
   %1 = call i32 @llvm.experimental.constrained.fptoui.i32.f16(half %a, metadata !"fpexcept.strict") strictfp
   ret i32 %1
 }
 
 define zeroext i32 @zext_fptoui(half %a) nounwind {
 ; RV64IZFH-LABEL: zext_fptoui:
 ; RV64IZFH:       # %bb.0:
 ; RV64IZFH-NEXT:    fcvt.lu.h a0, fa0, rtz
 ; RV64IZFH-NEXT:    ret
+;
+; RV64IZHINX-LABEL: zext_fptoui:
+; RV64IZHINX:       # %bb.0:
+; RV64IZHINX-NEXT:    fcvt.lu.h a0, a0, rtz
+; RV64IZHINX-NEXT:    ret
   %1 = call i32 @llvm.experimental.constrained.fptoui.i32.f16(half %a, metadata !"fpexcept.strict") strictfp
   ret i32 %1
 }
 
 define half @uitofp_aext_i32_to_f16(i32 %a) nounwind {
 ; RV64IZFH-LABEL: uitofp_aext_i32_to_f16:
 ; RV64IZFH:       # %bb.0:
 ; RV64IZFH-NEXT:    fcvt.h.wu fa0, a0
 ; RV64IZFH-NEXT:    ret
+;
+; RV64IZHINX-LABEL: uitofp_aext_i32_to_f16:
+; RV64IZHINX:       # %bb.0:
+; RV64IZHINX-NEXT:    fcvt.h.wu a0, a0
+; RV64IZHINX-NEXT:    ret
   %1 = call half @llvm.experimental.constrained.uitofp.f16.i32(i32 %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
   ret half %1
 }
 declare half @llvm.experimental.constrained.uitofp.f16.i32(i32 %a, metadata, metadata)
 
 define half @uitofp_sext_i32_to_f16(i32 signext %a) nounwind {
 ; RV64IZFH-LABEL: uitofp_sext_i32_to_f16:
 ; RV64IZFH:       # %bb.0:
 ; RV64IZFH-NEXT:    fcvt.h.wu fa0, a0
 ; RV64IZFH-NEXT:    ret
+;
+; RV64IZHINX-LABEL: uitofp_sext_i32_to_f16:
+; RV64IZHINX:       # %bb.0:
+; RV64IZHINX-NEXT:    fcvt.h.wu a0, a0
+; RV64IZHINX-NEXT:    ret
   %1 = call half @llvm.experimental.constrained.uitofp.f16.i32(i32 %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
   ret half %1
 }
 
 define half @uitofp_zext_i32_to_f16(i32 zeroext %a) nounwind {
 ; RV64IZFH-LABEL: uitofp_zext_i32_to_f16:
 ; RV64IZFH:       # %bb.0:
 ; RV64IZFH-NEXT:    fcvt.h.wu fa0, a0
 ; RV64IZFH-NEXT:    ret
+;
+; RV64IZHINX-LABEL: uitofp_zext_i32_to_f16:
+; RV64IZHINX:       # %bb.0:
+; RV64IZHINX-NEXT:    fcvt.h.wu a0, a0
+; RV64IZHINX-NEXT:    ret
   %1 = call half @llvm.experimental.constrained.uitofp.f16.i32(i32 %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
   ret half %1
 }
 
 define half @sitofp_aext_i32_to_f16(i32 %a) nounwind {
 ; RV64IZFH-LABEL: sitofp_aext_i32_to_f16:
 ; RV64IZFH:       # %bb.0:
 ; RV64IZFH-NEXT:    fcvt.h.w fa0, a0
 ; RV64IZFH-NEXT:    ret
+;
+; RV64IZHINX-LABEL: sitofp_aext_i32_to_f16:
+; RV64IZHINX:       # %bb.0:
+; RV64IZHINX-NEXT:    fcvt.h.w a0, a0
+; RV64IZHINX-NEXT:    ret
   %1 = call half @llvm.experimental.constrained.sitofp.f16.i32(i32 %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
   ret half %1
 }
 declare half @llvm.experimental.constrained.sitofp.f16.i32(i32 %a, metadata, metadata)
 
 define half @sitofp_sext_i32_to_f16(i32 signext %a) nounwind {
 ; RV64IZFH-LABEL: sitofp_sext_i32_to_f16:
 ; RV64IZFH:       # %bb.0:
 ; RV64IZFH-NEXT:    fcvt.h.w fa0, a0
 ; RV64IZFH-NEXT:    ret
+;
+; RV64IZHINX-LABEL: sitofp_sext_i32_to_f16:
+; RV64IZHINX:       # %bb.0:
+; RV64IZHINX-NEXT:    fcvt.h.w a0, a0
+; RV64IZHINX-NEXT:    ret
   %1 = call half @llvm.experimental.constrained.sitofp.f16.i32(i32 %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
   ret half %1
 }
 
 define half @sitofp_zext_i32_to_f16(i32 zeroext %a) nounwind {
 ; RV64IZFH-LABEL: sitofp_zext_i32_to_f16:
 ; RV64IZFH:       # %bb.0:
 ; RV64IZFH-NEXT:    fcvt.h.w fa0, a0
 ; RV64IZFH-NEXT:    ret
+;
+; RV64IZHINX-LABEL: sitofp_zext_i32_to_f16:
+; RV64IZHINX:       # %bb.0:
+; RV64IZHINX-NEXT:    fcvt.h.w a0, a0
+; RV64IZHINX-NEXT:    ret
   %1 = call half @llvm.experimental.constrained.sitofp.f16.i32(i32 %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
   ret half %1
 }

llvm/test/CodeGen/RISCV/rv64zfh-half-convert.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv64 -mattr=+zfh -verify-machineinstrs \
 ; RUN:   -target-abi lp64f < %s | FileCheck %s -check-prefix=RV64IZFH
+; RUN: llc -mtriple=riscv64 -mattr=+zhinx -verify-machineinstrs \
+; RUN:   -target-abi lp64 < %s | FileCheck %s -check-prefix=RV64IZHINX
 
 ; This file exhaustively checks half<->i32 conversions. In general,
 ; fcvt.l[u].h can be selected instead of fcvt.w[u].h because poison is
 ; generated for an fpto[s|u]i conversion if the result doesn't fit in the
 ; target type.
 
 define i32 @aext_fptosi(half %a) nounwind {
 ; RV64IZFH-LABEL: aext_fptosi:
 ; RV64IZFH:       # %bb.0:
 ; RV64IZFH-NEXT:    fcvt.w.h a0, fa0, rtz
 ; RV64IZFH-NEXT:    ret
+;
+; RV64IZHINX-LABEL: aext_fptosi:
+; RV64IZHINX:       # %bb.0:
+; RV64IZHINX-NEXT:    fcvt.w.h a0, a0, rtz
+; RV64IZHINX-NEXT:    ret
   %1 = fptosi half %a to i32
   ret i32 %1
 }
 
 define signext i32 @sext_fptosi(half %a) nounwind {
 ; RV64IZFH-LABEL: sext_fptosi:
 ; RV64IZFH:       # %bb.0:
 ; RV64IZFH-NEXT:    fcvt.w.h a0, fa0, rtz
 ; RV64IZFH-NEXT:    ret
+;
+; RV64IZHINX-LABEL: sext_fptosi:
+; RV64IZHINX:       # %bb.0:
+; RV64IZHINX-NEXT:    fcvt.w.h a0, a0, rtz
+; RV64IZHINX-NEXT:    ret
   %1 = fptosi half %a to i32
   ret i32 %1
 }
 
 define zeroext i32 @zext_fptosi(half %a) nounwind {
 ; RV64IZFH-LABEL: zext_fptosi:
 ; RV64IZFH:       # %bb.0:
 ; RV64IZFH-NEXT:    fcvt.w.h a0, fa0, rtz
 ; RV64IZFH-NEXT:    slli a0, a0, 32
 ; RV64IZFH-NEXT:    srli a0, a0, 32
 ; RV64IZFH-NEXT:    ret
+;
+; RV64IZHINX-LABEL: zext_fptosi:
+; RV64IZHINX:       # %bb.0:
+; RV64IZHINX-NEXT:    fcvt.w.h a0, a0, rtz
+; RV64IZHINX-NEXT:    slli a0, a0, 32
+; RV64IZHINX-NEXT:    srli a0, a0, 32
+; RV64IZHINX-NEXT:    ret
   %1 = fptosi half %a to i32
   ret i32 %1
 }
 
 define i32 @aext_fptoui(half %a) nounwind {
 ; RV64IZFH-LABEL: aext_fptoui:
 ; RV64IZFH:       # %bb.0:
 ; RV64IZFH-NEXT:    fcvt.wu.h a0, fa0, rtz
 ; RV64IZFH-NEXT:    ret
+;
+; RV64IZHINX-LABEL: aext_fptoui:
+; RV64IZHINX:       # %bb.0:
+; RV64IZHINX-NEXT:    fcvt.wu.h a0, a0, rtz
+; RV64IZHINX-NEXT:    ret
   %1 = fptoui half %a to i32
   ret i32 %1
 }
 
 define signext i32 @sext_fptoui(half %a) nounwind {
 ; RV64IZFH-LABEL: sext_fptoui:
 ; RV64IZFH:       # %bb.0:
 ; RV64IZFH-NEXT:    fcvt.wu.h a0, fa0, rtz
 ; RV64IZFH-NEXT:    ret
+;
+; RV64IZHINX-LABEL: sext_fptoui:
+; RV64IZHINX:       # %bb.0:
+; RV64IZHINX-NEXT:    fcvt.wu.h a0, a0, rtz
+; RV64IZHINX-NEXT:    ret
   %1 = fptoui half %a to i32
   ret i32 %1
 }
 
 define zeroext i32 @zext_fptoui(half %a) nounwind {
 ; RV64IZFH-LABEL: zext_fptoui:
 ; RV64IZFH:       # %bb.0:
 ; RV64IZFH-NEXT:    fcvt.lu.h a0, fa0, rtz
 ; RV64IZFH-NEXT:    ret
+;
+; RV64IZHINX-LABEL: zext_fptoui:
+; RV64IZHINX:       # %bb.0:
+; RV64IZHINX-NEXT:    fcvt.lu.h a0, a0, rtz
+; RV64IZHINX-NEXT:    ret
   %1 = fptoui half %a to i32
   ret i32 %1
 }
 
 define i16 @bcvt_f16_to_aext_i16(half %a, half %b) nounwind {
 ; RV64IZFH-LABEL: bcvt_f16_to_aext_i16:
 ; RV64IZFH:       # %bb.0:
 ; RV64IZFH-NEXT:    fadd.h fa5, fa0, fa1
 ; RV64IZFH-NEXT:    fmv.x.h a0, fa5
 ; RV64IZFH-NEXT:    ret
+;
+; RV64IZHINX-LABEL: bcvt_f16_to_aext_i16:
+; RV64IZHINX:       # %bb.0:
+; RV64IZHINX-NEXT:    fadd.h a0, a0, a1
+; RV64IZHINX-NEXT:    ret
   %1 = fadd half %a, %b
   %2 = bitcast half %1 to i16
   ret i16 %2
 }
 
 define signext i16 @bcvt_f16_to_sext_i16(half %a, half %b) nounwind {
 ; RV64IZFH-LABEL: bcvt_f16_to_sext_i16:
 ; RV64IZFH:       # %bb.0:
 ; RV64IZFH-NEXT:    fadd.h fa5, fa0, fa1
 ; RV64IZFH-NEXT:    fmv.x.h a0, fa5
 ; RV64IZFH-NEXT:    ret
+;
+; RV64IZHINX-LABEL: bcvt_f16_to_sext_i16:
+; RV64IZHINX:       # %bb.0:
+; RV64IZHINX-NEXT:    fadd.h a0, a0, a1
+; RV64IZHINX-NEXT:    ret
   %1 = fadd half %a, %b
   %2 = bitcast half %1 to i16
   ret i16 %2
 }
 
 define zeroext i16 @bcvt_f16_to_zext_i16(half %a, half %b) nounwind {
 ; RV64IZFH-LABEL: bcvt_f16_to_zext_i16:
 ; RV64IZFH:       # %bb.0:
 ; RV64IZFH-NEXT:    fadd.h fa5, fa0, fa1
 ; RV64IZFH-NEXT:    fmv.x.h a0, fa5
 ; RV64IZFH-NEXT:    slli a0, a0, 48
 ; RV64IZFH-NEXT:    srli a0, a0, 48
 ; RV64IZFH-NEXT:    ret
+;
+; RV64IZHINX-LABEL: bcvt_f16_to_zext_i16:
+; RV64IZHINX:       # %bb.0:
+; RV64IZHINX-NEXT:    fadd.h a0, a0, a1
+; RV64IZHINX-NEXT:    slli a0, a0, 48
+; RV64IZHINX-NEXT:    srli a0, a0, 48
+; RV64IZHINX-NEXT:    ret
   %1 = fadd half %a, %b
   %2 = bitcast half %1 to i16
   ret i16 %2
 }
 
 define half @bcvt_i64_to_f16_via_i16(i64 %a, i64 %b) nounwind {
 ; RV64IZFH-LABEL: bcvt_i64_to_f16_via_i16:
 ; RV64IZFH:       # %bb.0:
 ; RV64IZFH-NEXT:    fmv.h.x fa5, a0
 ; RV64IZFH-NEXT:    fmv.h.x fa4, a1
 ; RV64IZFH-NEXT:    fadd.h fa0, fa5, fa4
 ; RV64IZFH-NEXT:    ret
+;
+; RV64IZHINX-LABEL: bcvt_i64_to_f16_via_i16:
+; RV64IZHINX:       # %bb.0:
+; RV64IZHINX-NEXT:    fadd.h a0, a0, a1
+; RV64IZHINX-NEXT:    ret
   %1 = trunc i64 %a to i16
   %2 = trunc i64 %b to i16
   %3 = bitcast i16 %1 to half
   %4 = bitcast i16 %2 to half
   %5 = fadd half %3, %4
   ret half %5
 }
 
 define half @uitofp_aext_i32_to_f16(i32 %a) nounwind {
 ; RV64IZFH-LABEL: uitofp_aext_i32_to_f16:
 ; RV64IZFH:       # %bb.0:
 ; RV64IZFH-NEXT:    fcvt.h.wu fa0, a0
 ; RV64IZFH-NEXT:    ret
+;
+; RV64IZHINX-LABEL: uitofp_aext_i32_to_f16:
+; RV64IZHINX:       # %bb.0:
+; RV64IZHINX-NEXT:    fcvt.h.wu a0, a0
+; RV64IZHINX-NEXT:    ret
   %1 = uitofp i32 %a to half
   ret half %1
 }
 
 define half @uitofp_sext_i32_to_f16(i32 signext %a) nounwind {
 ; RV64IZFH-LABEL: uitofp_sext_i32_to_f16:
 ; RV64IZFH:       # %bb.0:
 ; RV64IZFH-NEXT:    fcvt.h.wu fa0, a0
 ; RV64IZFH-NEXT:    ret
+;
+; RV64IZHINX-LABEL: uitofp_sext_i32_to_f16:
+; RV64IZHINX:       # %bb.0:
+; RV64IZHINX-NEXT:    fcvt.h.wu a0, a0
+; RV64IZHINX-NEXT:    ret
   %1 = uitofp i32 %a to half
   ret half %1
 }
 
 define half @uitofp_zext_i32_to_f16(i32 zeroext %a) nounwind {
 ; RV64IZFH-LABEL: uitofp_zext_i32_to_f16:
 ; RV64IZFH:       # %bb.0:
 ; RV64IZFH-NEXT:    fcvt.h.wu fa0, a0
 ; RV64IZFH-NEXT:    ret
+;
+; RV64IZHINX-LABEL: uitofp_zext_i32_to_f16:
+; RV64IZHINX:       # %bb.0:
+; RV64IZHINX-NEXT:    fcvt.h.wu a0, a0
+; RV64IZHINX-NEXT:    ret
   %1 = uitofp i32 %a to half
   ret half %1
 }
 
 define half @sitofp_aext_i32_to_f16(i32 %a) nounwind {
 ; RV64IZFH-LABEL: sitofp_aext_i32_to_f16:
 ; RV64IZFH:       # %bb.0:
 ; RV64IZFH-NEXT:    fcvt.h.w fa0, a0
 ; RV64IZFH-NEXT:    ret
+;
+; RV64IZHINX-LABEL: sitofp_aext_i32_to_f16:
+; RV64IZHINX:       # %bb.0:
+; RV64IZHINX-NEXT:    fcvt.h.w a0, a0
+; RV64IZHINX-NEXT:    ret
   %1 = sitofp i32 %a to half
   ret half %1
 }
 
 define half @sitofp_sext_i32_to_f16(i32 signext %a) nounwind {
 ; RV64IZFH-LABEL: sitofp_sext_i32_to_f16:
 ; RV64IZFH:       # %bb.0:
 ; RV64IZFH-NEXT:    fcvt.h.w fa0, a0
 ; RV64IZFH-NEXT:    ret
+;
+; RV64IZHINX-LABEL: sitofp_sext_i32_to_f16:
+; RV64IZHINX:       # %bb.0:
+; RV64IZHINX-NEXT:    fcvt.h.w a0, a0
+; RV64IZHINX-NEXT:    ret
   %1 = sitofp i32 %a to half
   ret half %1
 }
 
 define half @sitofp_zext_i32_to_f16(i32 zeroext %a) nounwind {
 ; RV64IZFH-LABEL: sitofp_zext_i32_to_f16:
 ; RV64IZFH:       # %bb.0:
 ; RV64IZFH-NEXT:    fcvt.h.w fa0, a0
 ; RV64IZFH-NEXT:    ret
+;
+; RV64IZHINX-LABEL: sitofp_zext_i32_to_f16:
+; RV64IZHINX:       # %bb.0:
+; RV64IZHINX-NEXT:    fcvt.h.w a0, a0
+; RV64IZHINX-NEXT:    ret
   %1 = sitofp i32 %a to half
   ret half %1
 }

llvm/test/CodeGen/RISCV/rv64zfh-half-intrinsics.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=riscv64 -mattr=+zfh \
 ; RUN:   -verify-machineinstrs -target-abi lp64f | \
 ; RUN:   FileCheck -check-prefix=RV64IZFH %s
 ; RUN: llc < %s -mtriple=riscv64 -mattr=+d \
 ; RUN:   -mattr=+zfh -verify-machineinstrs -target-abi lp64d | \
 ; RUN:   FileCheck -check-prefix=RV64IDZFH %s
+; RUN: llc < %s -mtriple=riscv64 -mattr=+zhinx \
+; RUN:   -verify-machineinstrs -target-abi lp64 | \
+; RUN:   FileCheck -check-prefix=RV64IZHINX %s
+; RUN: llc < %s -mtriple=riscv64 -mattr=+zdinx \
+; RUN:   -mattr=+zhinx -verify-machineinstrs -target-abi lp64 | \
+; RUN:   FileCheck -check-prefix=RV64IZDINXZHINX %s
 
 ; These intrinsics require half and i64 to be legal types.
 
 declare i64 @llvm.llrint.i64.f16(half)
 
 define i64 @llrint_f16(half %a) nounwind {
 ; RV64IZFH-LABEL: llrint_f16:
 ; RV64IZFH:       # %bb.0:
 ; RV64IZFH-NEXT:    fcvt.l.h a0, fa0
 ; RV64IZFH-NEXT:    ret
 ;
 ; RV64IDZFH-LABEL: llrint_f16:
 ; RV64IDZFH:       # %bb.0:
 ; RV64IDZFH-NEXT:    fcvt.l.h a0, fa0
 ; RV64IDZFH-NEXT:    ret
+;
+; RV64IZHINX-LABEL: llrint_f16:
+; RV64IZHINX:       # %bb.0:
+; RV64IZHINX-NEXT:    fcvt.l.h a0, a0
+; RV64IZHINX-NEXT:    ret
+;
+; RV64IZDINXZHINX-LABEL: llrint_f16:
+; RV64IZDINXZHINX:       # %bb.0:
+; RV64IZDINXZHINX-NEXT:    fcvt.l.h a0, a0
+; RV64IZDINXZHINX-NEXT:    ret
   %1 = call i64 @llvm.llrint.i64.f16(half %a)
   ret i64 %1
 }
 
 declare i64 @llvm.llround.i64.f16(half)
 
 define i64 @llround_f16(half %a) nounwind {
 ; RV64IZFH-LABEL: llround_f16:
 ; RV64IZFH:       # %bb.0:
 ; RV64IZFH-NEXT:    fcvt.l.h a0, fa0, rmm
 ; RV64IZFH-NEXT:    ret
 ;
 ; RV64IDZFH-LABEL: llround_f16:
 ; RV64IDZFH:       # %bb.0:
 ; RV64IDZFH-NEXT:    fcvt.l.h a0, fa0, rmm
 ; RV64IDZFH-NEXT:    ret
+;
+; RV64IZHINX-LABEL: llround_f16:
+; RV64IZHINX:       # %bb.0:
+; RV64IZHINX-NEXT:    fcvt.l.h a0, a0, rmm
+; RV64IZHINX-NEXT:    ret
+;
+; RV64IZDINXZHINX-LABEL: llround_f16:
+; RV64IZDINXZHINX:       # %bb.0:
+; RV64IZDINXZHINX-NEXT:    fcvt.l.h a0, a0, rmm
+; RV64IZDINXZHINX-NEXT:    ret
   %1 = call i64 @llvm.llround.i64.f16(half %a)
   ret i64 %1
 }

llvm/test/CodeGen/RISCV/rv64zfhmin-half-convert-strict.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv64 -mattr=+zfhmin -verify-machineinstrs \
 ; RUN:   -target-abi lp64f -disable-strictnode-mutation < %s | \
 ; RUN:   FileCheck %s -check-prefix=RV64IZFHMIN
+; RUN: llc -mtriple=riscv64 -mattr=+zhinxmin -verify-machineinstrs \
+; RUN:   -target-abi lp64 -disable-strictnode-mutation < %s | \
+; RUN:   FileCheck %s -check-prefix=RV64IZHINXMIN
 
 ; This file exhaustively checks half<->i32 conversions.
 
 define i32 @aext_fptosi(half %a) nounwind {
 ; RV64IZFHMIN-LABEL: aext_fptosi:
 ; RV64IZFHMIN:       # %bb.0:
 ; RV64IZFHMIN-NEXT:    fcvt.s.h fa5, fa0
 ; RV64IZFHMIN-NEXT:    fcvt.w.s a0, fa5, rtz
 ; RV64IZFHMIN-NEXT:    ret
+;
+; RV64IZHINXMIN-LABEL: aext_fptosi:
+; RV64IZHINXMIN:       # %bb.0:
+; RV64IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV64IZHINXMIN-NEXT:    fcvt.w.s a0, a0, rtz
+; RV64IZHINXMIN-NEXT:    ret
   %1 = call i32 @llvm.experimental.constrained.fptosi.i32.f16(half %a, metadata !"fpexcept.strict") strictfp
   ret i32 %1
 }
 declare i32 @llvm.experimental.constrained.fptosi.i32.f16(half, metadata)
 
 define signext i32 @sext_fptosi(half %a) nounwind {
 ; RV64IZFHMIN-LABEL: sext_fptosi:
 ; RV64IZFHMIN:       # %bb.0:
 ; RV64IZFHMIN-NEXT:    fcvt.s.h fa5, fa0
 ; RV64IZFHMIN-NEXT:    fcvt.w.s a0, fa5, rtz
 ; RV64IZFHMIN-NEXT:    ret
+;
+; RV64IZHINXMIN-LABEL: sext_fptosi:
+; RV64IZHINXMIN:       # %bb.0:
+; RV64IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV64IZHINXMIN-NEXT:    fcvt.w.s a0, a0, rtz
+; RV64IZHINXMIN-NEXT:    ret
   %1 = call i32 @llvm.experimental.constrained.fptosi.i32.f16(half %a, metadata !"fpexcept.strict") strictfp
   ret i32 %1
 }
 
 define zeroext i32 @zext_fptosi(half %a) nounwind {
 ; RV64IZFHMIN-LABEL: zext_fptosi:
 ; RV64IZFHMIN:       # %bb.0:
 ; RV64IZFHMIN-NEXT:    fcvt.s.h fa5, fa0
 ; RV64IZFHMIN-NEXT:    fcvt.w.s a0, fa5, rtz
 ; RV64IZFHMIN-NEXT:    slli a0, a0, 32
 ; RV64IZFHMIN-NEXT:    srli a0, a0, 32
 ; RV64IZFHMIN-NEXT:    ret
+;
+; RV64IZHINXMIN-LABEL: zext_fptosi:
+; RV64IZHINXMIN:       # %bb.0:
+; RV64IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV64IZHINXMIN-NEXT:    fcvt.w.s a0, a0, rtz
+; RV64IZHINXMIN-NEXT:    slli a0, a0, 32
+; RV64IZHINXMIN-NEXT:    srli a0, a0, 32
+; RV64IZHINXMIN-NEXT:    ret
   %1 = call i32 @llvm.experimental.constrained.fptosi.i32.f16(half %a, metadata !"fpexcept.strict") strictfp
   ret i32 %1
 }
 
 define i32 @aext_fptoui(half %a) nounwind {
 ; RV64IZFHMIN-LABEL: aext_fptoui:
 ; RV64IZFHMIN:       # %bb.0:
 ; RV64IZFHMIN-NEXT:    fcvt.s.h fa5, fa0
 ; RV64IZFHMIN-NEXT:    fcvt.wu.s a0, fa5, rtz
 ; RV64IZFHMIN-NEXT:    ret
+;
+; RV64IZHINXMIN-LABEL: aext_fptoui:
+; RV64IZHINXMIN:       # %bb.0:
+; RV64IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV64IZHINXMIN-NEXT:    fcvt.wu.s a0, a0, rtz
+; RV64IZHINXMIN-NEXT:    ret
   %1 = call i32 @llvm.experimental.constrained.fptoui.i32.f16(half %a, metadata !"fpexcept.strict") strictfp
   ret i32 %1
 }
 declare i32 @llvm.experimental.constrained.fptoui.i32.f16(half, metadata)
 
 define signext i32 @sext_fptoui(half %a) nounwind {
 ; RV64IZFHMIN-LABEL: sext_fptoui:
 ; RV64IZFHMIN:       # %bb.0:
 ; RV64IZFHMIN-NEXT:    fcvt.s.h fa5, fa0
 ; RV64IZFHMIN-NEXT:    fcvt.wu.s a0, fa5, rtz
 ; RV64IZFHMIN-NEXT:    ret
+;
+; RV64IZHINXMIN-LABEL: sext_fptoui:
+; RV64IZHINXMIN:       # %bb.0:
+; RV64IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV64IZHINXMIN-NEXT:    fcvt.wu.s a0, a0, rtz
+; RV64IZHINXMIN-NEXT:    ret
   %1 = call i32 @llvm.experimental.constrained.fptoui.i32.f16(half %a, metadata !"fpexcept.strict") strictfp
   ret i32 %1
 }
 
 define zeroext i32 @zext_fptoui(half %a) nounwind {
 ; RV64IZFHMIN-LABEL: zext_fptoui:
 ; RV64IZFHMIN:       # %bb.0:
 ; RV64IZFHMIN-NEXT:    fcvt.s.h fa5, fa0
 ; RV64IZFHMIN-NEXT:    fcvt.lu.s a0, fa5, rtz
 ; RV64IZFHMIN-NEXT:    ret
+;
+; RV64IZHINXMIN-LABEL: zext_fptoui:
+; RV64IZHINXMIN:       # %bb.0:
+; RV64IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV64IZHINXMIN-NEXT:    fcvt.lu.s a0, a0, rtz
+; RV64IZHINXMIN-NEXT:    ret
   %1 = call i32 @llvm.experimental.constrained.fptoui.i32.f16(half %a, metadata !"fpexcept.strict") strictfp
   ret i32 %1
 }
 
 define half @uitofp_aext_i32_to_f16(i32 %a) nounwind {
 ; RV64IZFHMIN-LABEL: uitofp_aext_i32_to_f16:
 ; RV64IZFHMIN:       # %bb.0:
 ; RV64IZFHMIN-NEXT:    slli a0, a0, 32
 ; RV64IZFHMIN-NEXT:    srli a0, a0, 32
 ; RV64IZFHMIN-NEXT:    fcvt.s.lu fa5, a0
 ; RV64IZFHMIN-NEXT:    fcvt.h.s fa0, fa5
 ; RV64IZFHMIN-NEXT:    ret
+;
+; RV64IZHINXMIN-LABEL: uitofp_aext_i32_to_f16:
+; RV64IZHINXMIN:       # %bb.0:
+; RV64IZHINXMIN-NEXT:    slli a0, a0, 32
+; RV64IZHINXMIN-NEXT:    srli a0, a0, 32
+; RV64IZHINXMIN-NEXT:    fcvt.s.lu a0, a0
+; RV64IZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; RV64IZHINXMIN-NEXT:    ret
   %1 = call half @llvm.experimental.constrained.uitofp.f16.i32(i32 %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
   ret half %1
 }
 declare half @llvm.experimental.constrained.uitofp.f16.i32(i32 %a, metadata, metadata)
 
 define half @uitofp_sext_i32_to_f16(i32 signext %a) nounwind {
 ; RV64IZFHMIN-LABEL: uitofp_sext_i32_to_f16:
 ; RV64IZFHMIN:       # %bb.0:
 ; RV64IZFHMIN-NEXT:    slli a0, a0, 32
 ; RV64IZFHMIN-NEXT:    srli a0, a0, 32
 ; RV64IZFHMIN-NEXT:    fcvt.s.lu fa5, a0
 ; RV64IZFHMIN-NEXT:    fcvt.h.s fa0, fa5
 ; RV64IZFHMIN-NEXT:    ret
+;
+; RV64IZHINXMIN-LABEL: uitofp_sext_i32_to_f16:
+; RV64IZHINXMIN:       # %bb.0:
+; RV64IZHINXMIN-NEXT:    slli a0, a0, 32
+; RV64IZHINXMIN-NEXT:    srli a0, a0, 32
+; RV64IZHINXMIN-NEXT:    fcvt.s.lu a0, a0
+; RV64IZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; RV64IZHINXMIN-NEXT:    ret
   %1 = call half @llvm.experimental.constrained.uitofp.f16.i32(i32 %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
   ret half %1
 }
 
 define half @uitofp_zext_i32_to_f16(i32 zeroext %a) nounwind {
 ; RV64IZFHMIN-LABEL: uitofp_zext_i32_to_f16:
 ; RV64IZFHMIN:       # %bb.0:
 ; RV64IZFHMIN-NEXT:    fcvt.s.lu fa5, a0
 ; RV64IZFHMIN-NEXT:    fcvt.h.s fa0, fa5
 ; RV64IZFHMIN-NEXT:    ret
+;
+; RV64IZHINXMIN-LABEL: uitofp_zext_i32_to_f16:
+; RV64IZHINXMIN:       # %bb.0:
+; RV64IZHINXMIN-NEXT:    fcvt.s.lu a0, a0
+; RV64IZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; RV64IZHINXMIN-NEXT:    ret
   %1 = call half @llvm.experimental.constrained.uitofp.f16.i32(i32 %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
   ret half %1
 }
 
 define half @sitofp_aext_i32_to_f16(i32 %a) nounwind {
 ; RV64IZFHMIN-LABEL: sitofp_aext_i32_to_f16:
 ; RV64IZFHMIN:       # %bb.0:
 ; RV64IZFHMIN-NEXT:    sext.w a0, a0
 ; RV64IZFHMIN-NEXT:    fcvt.s.l fa5, a0
 ; RV64IZFHMIN-NEXT:    fcvt.h.s fa0, fa5
 ; RV64IZFHMIN-NEXT:    ret
+;
+; RV64IZHINXMIN-LABEL: sitofp_aext_i32_to_f16:
+; RV64IZHINXMIN:       # %bb.0:
+; RV64IZHINXMIN-NEXT:    sext.w a0, a0
+; RV64IZHINXMIN-NEXT:    fcvt.s.l a0, a0
+; RV64IZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; RV64IZHINXMIN-NEXT:    ret
   %1 = call half @llvm.experimental.constrained.sitofp.f16.i32(i32 %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
   ret half %1
 }
 declare half @llvm.experimental.constrained.sitofp.f16.i32(i32 %a, metadata, metadata)
 
 define half @sitofp_sext_i32_to_f16(i32 signext %a) nounwind {
 ; RV64IZFHMIN-LABEL: sitofp_sext_i32_to_f16:
 ; RV64IZFHMIN:       # %bb.0:
 ; RV64IZFHMIN-NEXT:    fcvt.s.l fa5, a0
 ; RV64IZFHMIN-NEXT:    fcvt.h.s fa0, fa5
 ; RV64IZFHMIN-NEXT:    ret
+;
+; RV64IZHINXMIN-LABEL: sitofp_sext_i32_to_f16:
+; RV64IZHINXMIN:       # %bb.0:
+; RV64IZHINXMIN-NEXT:    fcvt.s.l a0, a0
+; RV64IZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; RV64IZHINXMIN-NEXT:    ret
   %1 = call half @llvm.experimental.constrained.sitofp.f16.i32(i32 %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
   ret half %1
 }
 
 define half @sitofp_zext_i32_to_f16(i32 zeroext %a) nounwind {
 ; RV64IZFHMIN-LABEL: sitofp_zext_i32_to_f16:
 ; RV64IZFHMIN:       # %bb.0:
 ; RV64IZFHMIN-NEXT:    sext.w a0, a0
 ; RV64IZFHMIN-NEXT:    fcvt.s.l fa5, a0
 ; RV64IZFHMIN-NEXT:    fcvt.h.s fa0, fa5
 ; RV64IZFHMIN-NEXT:    ret
+;
+; RV64IZHINXMIN-LABEL: sitofp_zext_i32_to_f16:
+; RV64IZHINXMIN:       # %bb.0:
+; RV64IZHINXMIN-NEXT:    sext.w a0, a0
+; RV64IZHINXMIN-NEXT:    fcvt.s.l a0, a0
+; RV64IZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; RV64IZHINXMIN-NEXT:    ret
   %1 = call half @llvm.experimental.constrained.sitofp.f16.i32(i32 %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
   ret half %1
 }

llvm/test/CodeGen/RISCV/rv64zfhmin-half-convert.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv64 -mattr=+zfhmin -verify-machineinstrs \
 ; RUN:   -target-abi lp64f < %s | FileCheck %s -check-prefix=RV64IZFHMIN
+; RUN: llc -mtriple=riscv64 -mattr=+zhinxmin -verify-machineinstrs \
+; RUN:   -target-abi lp64 < %s | FileCheck %s -check-prefix=RV64IZHINXMIN
 
 ; This file exhaustively checks half<->i32 conversions.
 
 define i32 @aext_fptosi(half %a) nounwind {
 ; RV64IZFHMIN-LABEL: aext_fptosi:
 ; RV64IZFHMIN:       # %bb.0:
 ; RV64IZFHMIN-NEXT:    fcvt.s.h fa5, fa0
 ; RV64IZFHMIN-NEXT:    fcvt.w.s a0, fa5, rtz
 ; RV64IZFHMIN-NEXT:    ret
+;
+; RV64IZHINXMIN-LABEL: aext_fptosi:
+; RV64IZHINXMIN:       # %bb.0:
+; RV64IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV64IZHINXMIN-NEXT:    fcvt.w.s a0, a0, rtz
+; RV64IZHINXMIN-NEXT:    ret
   %1 = fptosi half %a to i32
   ret i32 %1
 }
 
 define signext i32 @sext_fptosi(half %a) nounwind {
 ; RV64IZFHMIN-LABEL: sext_fptosi:
 ; RV64IZFHMIN:       # %bb.0:
 ; RV64IZFHMIN-NEXT:    fcvt.s.h fa5, fa0
 ; RV64IZFHMIN-NEXT:    fcvt.w.s a0, fa5, rtz
 ; RV64IZFHMIN-NEXT:    ret
+;
+; RV64IZHINXMIN-LABEL: sext_fptosi:
+; RV64IZHINXMIN:       # %bb.0:
+; RV64IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV64IZHINXMIN-NEXT:    fcvt.w.s a0, a0, rtz
+; RV64IZHINXMIN-NEXT:    ret
   %1 = fptosi half %a to i32
   ret i32 %1
 }
 
 define zeroext i32 @zext_fptosi(half %a) nounwind {
 ; RV64IZFHMIN-LABEL: zext_fptosi:
 ; RV64IZFHMIN:       # %bb.0:
 ; RV64IZFHMIN-NEXT:    fcvt.s.h fa5, fa0
 ; RV64IZFHMIN-NEXT:    fcvt.w.s a0, fa5, rtz
 ; RV64IZFHMIN-NEXT:    slli a0, a0, 32
 ; RV64IZFHMIN-NEXT:    srli a0, a0, 32
 ; RV64IZFHMIN-NEXT:    ret
+;
+; RV64IZHINXMIN-LABEL: zext_fptosi:
+; RV64IZHINXMIN:       # %bb.0:
+; RV64IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV64IZHINXMIN-NEXT:    fcvt.w.s a0, a0, rtz
+; RV64IZHINXMIN-NEXT:    slli a0, a0, 32
+; RV64IZHINXMIN-NEXT:    srli a0, a0, 32
+; RV64IZHINXMIN-NEXT:    ret
   %1 = fptosi half %a to i32
   ret i32 %1
 }
 
 define i32 @aext_fptoui(half %a) nounwind {
 ; RV64IZFHMIN-LABEL: aext_fptoui:
 ; RV64IZFHMIN:       # %bb.0:
 ; RV64IZFHMIN-NEXT:    fcvt.s.h fa5, fa0
 ; RV64IZFHMIN-NEXT:    fcvt.wu.s a0, fa5, rtz
 ; RV64IZFHMIN-NEXT:    ret
+;
+; RV64IZHINXMIN-LABEL: aext_fptoui:
+; RV64IZHINXMIN:       # %bb.0:
+; RV64IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV64IZHINXMIN-NEXT:    fcvt.wu.s a0, a0, rtz
+; RV64IZHINXMIN-NEXT:    ret
   %1 = fptoui half %a to i32
   ret i32 %1
 }
 
 define signext i32 @sext_fptoui(half %a) nounwind {
 ; RV64IZFHMIN-LABEL: sext_fptoui:
 ; RV64IZFHMIN:       # %bb.0:
 ; RV64IZFHMIN-NEXT:    fcvt.s.h fa5, fa0
 ; RV64IZFHMIN-NEXT:    fcvt.wu.s a0, fa5, rtz
 ; RV64IZFHMIN-NEXT:    ret
+;
+; RV64IZHINXMIN-LABEL: sext_fptoui:
+; RV64IZHINXMIN:       # %bb.0:
+; RV64IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV64IZHINXMIN-NEXT:    fcvt.wu.s a0, a0, rtz
+; RV64IZHINXMIN-NEXT:    ret
   %1 = fptoui half %a to i32
   ret i32 %1
 }
 
 define zeroext i32 @zext_fptoui(half %a) nounwind {
 ; RV64IZFHMIN-LABEL: zext_fptoui:
 ; RV64IZFHMIN:       # %bb.0:
 ; RV64IZFHMIN-NEXT:    fcvt.s.h fa5, fa0
 ; RV64IZFHMIN-NEXT:    fcvt.lu.s a0, fa5, rtz
 ; RV64IZFHMIN-NEXT:    ret
+;
+; RV64IZHINXMIN-LABEL: zext_fptoui:
+; RV64IZHINXMIN:       # %bb.0:
+; RV64IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV64IZHINXMIN-NEXT:    fcvt.lu.s a0, a0, rtz
+; RV64IZHINXMIN-NEXT:    ret
   %1 = fptoui half %a to i32
   ret i32 %1
 }
 
 define i16 @bcvt_f16_to_aext_i16(half %a, half %b) nounwind {
 ; RV64IZFHMIN-LABEL: bcvt_f16_to_aext_i16:
 ; RV64IZFHMIN:       # %bb.0:
 ; RV64IZFHMIN-NEXT:    fcvt.s.h fa5, fa1
 ; RV64IZFHMIN-NEXT:    fcvt.s.h fa4, fa0
 ; RV64IZFHMIN-NEXT:    fadd.s fa5, fa4, fa5
 ; RV64IZFHMIN-NEXT:    fcvt.h.s fa5, fa5
 ; RV64IZFHMIN-NEXT:    fmv.x.h a0, fa5
 ; RV64IZFHMIN-NEXT:    ret
+;
+; RV64IZHINXMIN-LABEL: bcvt_f16_to_aext_i16:
+; RV64IZHINXMIN:       # %bb.0:
+; RV64IZHINXMIN-NEXT:    fcvt.s.h a1, a1
+; RV64IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV64IZHINXMIN-NEXT:    fadd.s a0, a0, a1
+; RV64IZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; RV64IZHINXMIN-NEXT:    ret
   %1 = fadd half %a, %b
   %2 = bitcast half %1 to i16
   ret i16 %2
 }
 
 define signext i16 @bcvt_f16_to_sext_i16(half %a, half %b) nounwind {
 ; RV64IZFHMIN-LABEL: bcvt_f16_to_sext_i16:
 ; RV64IZFHMIN:       # %bb.0:
 ; RV64IZFHMIN-NEXT:    fcvt.s.h fa5, fa1
 ; RV64IZFHMIN-NEXT:    fcvt.s.h fa4, fa0
 ; RV64IZFHMIN-NEXT:    fadd.s fa5, fa4, fa5
 ; RV64IZFHMIN-NEXT:    fcvt.h.s fa5, fa5
 ; RV64IZFHMIN-NEXT:    fmv.x.h a0, fa5
 ; RV64IZFHMIN-NEXT:    ret
+;
+; RV64IZHINXMIN-LABEL: bcvt_f16_to_sext_i16:
+; RV64IZHINXMIN:       # %bb.0:
+; RV64IZHINXMIN-NEXT:    fcvt.s.h a1, a1
+; RV64IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV64IZHINXMIN-NEXT:    fadd.s a0, a0, a1
+; RV64IZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; RV64IZHINXMIN-NEXT:    ret
   %1 = fadd half %a, %b
   %2 = bitcast half %1 to i16
   ret i16 %2
 }
 
 define zeroext i16 @bcvt_f16_to_zext_i16(half %a, half %b) nounwind {
 ; RV64IZFHMIN-LABEL: bcvt_f16_to_zext_i16:
 ; RV64IZFHMIN:       # %bb.0:
 ; RV64IZFHMIN-NEXT:    fcvt.s.h fa5, fa1
 ; RV64IZFHMIN-NEXT:    fcvt.s.h fa4, fa0
 ; RV64IZFHMIN-NEXT:    fadd.s fa5, fa4, fa5
 ; RV64IZFHMIN-NEXT:    fcvt.h.s fa5, fa5
 ; RV64IZFHMIN-NEXT:    fmv.x.h a0, fa5
 ; RV64IZFHMIN-NEXT:    slli a0, a0, 48
 ; RV64IZFHMIN-NEXT:    srli a0, a0, 48
 ; RV64IZFHMIN-NEXT:    ret
+;
+; RV64IZHINXMIN-LABEL: bcvt_f16_to_zext_i16:
+; RV64IZHINXMIN:       # %bb.0:
+; RV64IZHINXMIN-NEXT:    fcvt.s.h a1, a1
+; RV64IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV64IZHINXMIN-NEXT:    fadd.s a0, a0, a1
+; RV64IZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; RV64IZHINXMIN-NEXT:    slli a0, a0, 48
+; RV64IZHINXMIN-NEXT:    srli a0, a0, 48
+; RV64IZHINXMIN-NEXT:    ret
   %1 = fadd half %a, %b
   %2 = bitcast half %1 to i16
   ret i16 %2
 }
 
 define half @bcvt_i64_to_f16_via_i16(i64 %a, i64 %b) nounwind {
 ; RV64IZFHMIN-LABEL: bcvt_i64_to_f16_via_i16:
 ; RV64IZFHMIN:       # %bb.0:
 ; RV64IZFHMIN-NEXT:    fmv.h.x fa5, a0
 ; RV64IZFHMIN-NEXT:    fmv.h.x fa4, a1
 ; RV64IZFHMIN-NEXT:    fcvt.s.h fa4, fa4
 ; RV64IZFHMIN-NEXT:    fcvt.s.h fa5, fa5
 ; RV64IZFHMIN-NEXT:    fadd.s fa5, fa5, fa4
 ; RV64IZFHMIN-NEXT:    fcvt.h.s fa0, fa5
 ; RV64IZFHMIN-NEXT:    ret
+;
+; RV64IZHINXMIN-LABEL: bcvt_i64_to_f16_via_i16:
+; RV64IZHINXMIN:       # %bb.0:
+; RV64IZHINXMIN-NEXT:    fcvt.s.h a1, a1
+; RV64IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV64IZHINXMIN-NEXT:    fadd.s a0, a0, a1
+; RV64IZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; RV64IZHINXMIN-NEXT:    ret
   %1 = trunc i64 %a to i16
   %2 = trunc i64 %b to i16
   %3 = bitcast i16 %1 to half
   %4 = bitcast i16 %2 to half
   %5 = fadd half %3, %4
   ret half %5
 }
 
 define half @uitofp_aext_i32_to_f16(i32 %a) nounwind {
 ; RV64IZFHMIN-LABEL: uitofp_aext_i32_to_f16:
 ; RV64IZFHMIN:       # %bb.0:
 ; RV64IZFHMIN-NEXT:    slli a0, a0, 32
 ; RV64IZFHMIN-NEXT:    srli a0, a0, 32
 ; RV64IZFHMIN-NEXT:    fcvt.s.lu fa5, a0
 ; RV64IZFHMIN-NEXT:    fcvt.h.s fa0, fa5
 ; RV64IZFHMIN-NEXT:    ret
+;
+; RV64IZHINXMIN-LABEL: uitofp_aext_i32_to_f16:
+; RV64IZHINXMIN:       # %bb.0:
+; RV64IZHINXMIN-NEXT:    slli a0, a0, 32
+; RV64IZHINXMIN-NEXT:    srli a0, a0, 32
+; RV64IZHINXMIN-NEXT:    fcvt.s.lu a0, a0
+; RV64IZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; RV64IZHINXMIN-NEXT:    ret
   %1 = uitofp i32 %a to half
   ret half %1
 }
 
 define half @uitofp_sext_i32_to_f16(i32 signext %a) nounwind {
 ; RV64IZFHMIN-LABEL: uitofp_sext_i32_to_f16:
 ; RV64IZFHMIN:       # %bb.0:
 ; RV64IZFHMIN-NEXT:    slli a0, a0, 32
 ; RV64IZFHMIN-NEXT:    srli a0, a0, 32
 ; RV64IZFHMIN-NEXT:    fcvt.s.lu fa5, a0
 ; RV64IZFHMIN-NEXT:    fcvt.h.s fa0, fa5
 ; RV64IZFHMIN-NEXT:    ret
+;
+; RV64IZHINXMIN-LABEL: uitofp_sext_i32_to_f16:
+; RV64IZHINXMIN:       # %bb.0:
+; RV64IZHINXMIN-NEXT:    slli a0, a0, 32
+; RV64IZHINXMIN-NEXT:    srli a0, a0, 32
+; RV64IZHINXMIN-NEXT:    fcvt.s.lu a0, a0
+; RV64IZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; RV64IZHINXMIN-NEXT:    ret
   %1 = uitofp i32 %a to half
   ret half %1
 }
 
 define half @uitofp_zext_i32_to_f16(i32 zeroext %a) nounwind {
 ; RV64IZFHMIN-LABEL: uitofp_zext_i32_to_f16:
 ; RV64IZFHMIN:       # %bb.0:
 ; RV64IZFHMIN-NEXT:    fcvt.s.lu fa5, a0
 ; RV64IZFHMIN-NEXT:    fcvt.h.s fa0, fa5
 ; RV64IZFHMIN-NEXT:    ret
+;
+; RV64IZHINXMIN-LABEL: uitofp_zext_i32_to_f16:
+; RV64IZHINXMIN:       # %bb.0:
+; RV64IZHINXMIN-NEXT:    fcvt.s.lu a0, a0
+; RV64IZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; RV64IZHINXMIN-NEXT:    ret
   %1 = uitofp i32 %a to half
   ret half %1
 }
 
 define half @sitofp_aext_i32_to_f16(i32 %a) nounwind {
 ; RV64IZFHMIN-LABEL: sitofp_aext_i32_to_f16:
 ; RV64IZFHMIN:       # %bb.0:
 ; RV64IZFHMIN-NEXT:    sext.w a0, a0
 ; RV64IZFHMIN-NEXT:    fcvt.s.l fa5, a0
 ; RV64IZFHMIN-NEXT:    fcvt.h.s fa0, fa5
 ; RV64IZFHMIN-NEXT:    ret
+;
+; RV64IZHINXMIN-LABEL: sitofp_aext_i32_to_f16:
+; RV64IZHINXMIN:       # %bb.0:
+; RV64IZHINXMIN-NEXT:    sext.w a0, a0
+; RV64IZHINXMIN-NEXT:    fcvt.s.l a0, a0
+; RV64IZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; RV64IZHINXMIN-NEXT:    ret
   %1 = sitofp i32 %a to half
   ret half %1
 }
 
 define half @sitofp_sext_i32_to_f16(i32 signext %a) nounwind {
 ; RV64IZFHMIN-LABEL: sitofp_sext_i32_to_f16:
 ; RV64IZFHMIN:       # %bb.0:
 ; RV64IZFHMIN-NEXT:    fcvt.s.l fa5, a0
 ; RV64IZFHMIN-NEXT:    fcvt.h.s fa0, fa5
 ; RV64IZFHMIN-NEXT:    ret
+;
+; RV64IZHINXMIN-LABEL: sitofp_sext_i32_to_f16:
+; RV64IZHINXMIN:       # %bb.0:
+; RV64IZHINXMIN-NEXT:    fcvt.s.l a0, a0
+; RV64IZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; RV64IZHINXMIN-NEXT:    ret
   %1 = sitofp i32 %a to half
   ret half %1
 }
 
 define half @sitofp_zext_i32_to_f16(i32 zeroext %a) nounwind {
 ; RV64IZFHMIN-LABEL: sitofp_zext_i32_to_f16:
 ; RV64IZFHMIN:       # %bb.0:
 ; RV64IZFHMIN-NEXT:    sext.w a0, a0
 ; RV64IZFHMIN-NEXT:    fcvt.s.l fa5, a0
 ; RV64IZFHMIN-NEXT:    fcvt.h.s fa0, fa5
 ; RV64IZFHMIN-NEXT:    ret
+;
+; RV64IZHINXMIN-LABEL: sitofp_zext_i32_to_f16:
+; RV64IZHINXMIN:       # %bb.0:
+; RV64IZHINXMIN-NEXT:    sext.w a0, a0
+; RV64IZHINXMIN-NEXT:    fcvt.s.l a0, a0
+; RV64IZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; RV64IZHINXMIN-NEXT:    ret
   %1 = sitofp i32 %a to half
   ret half %1
 }

llvm/test/CodeGen/RISCV/rv64zfhmin-half-intrinsics.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=riscv64 -mattr=+zfhmin \
 ; RUN:   -verify-machineinstrs -target-abi lp64f | \
 ; RUN:   FileCheck -check-prefix=CHECKIZFHMIN %s
 ; RUN: llc < %s -mtriple=riscv64 -mattr=+d \
 ; RUN:   -mattr=+zfhmin -verify-machineinstrs -target-abi lp64d | \
 ; RUN:   FileCheck -check-prefix=CHECKIZFHMIN %s
+; RUN: llc < %s -mtriple=riscv64 -mattr=+zhinxmin \
+; RUN:   -verify-machineinstrs -target-abi lp64 | \
+; RUN:   FileCheck -check-prefix=CHECKIZHINXMIN %s
+; RUN: llc < %s -mtriple=riscv64 -mattr=+zdinx \
+; RUN:   -mattr=+zhinxmin -verify-machineinstrs -target-abi lp64 | \
+; RUN:   FileCheck -check-prefix=CHECKIZHINXMIN %s
 
 ; These intrinsics require half and i64 to be legal types.
 
 declare i64 @llvm.llrint.i64.f16(half)
 
 define i64 @llrint_f16(half %a) nounwind {
 ; CHECKIZFHMIN-LABEL: llrint_f16:
 ; CHECKIZFHMIN:       # %bb.0:
 ; CHECKIZFHMIN-NEXT:    fcvt.s.h fa5, fa0
 ; CHECKIZFHMIN-NEXT:    fcvt.l.s a0, fa5
 ; CHECKIZFHMIN-NEXT:    ret
+;
+; CHECKIZHINXMIN-LABEL: llrint_f16:
+; CHECKIZHINXMIN:       # %bb.0:
+; CHECKIZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECKIZHINXMIN-NEXT:    fcvt.l.s a0, a0
+; CHECKIZHINXMIN-NEXT:    ret
   %1 = call i64 @llvm.llrint.i64.f16(half %a)
   ret i64 %1
 }
 
 declare i64 @llvm.llround.i64.f16(half)
 
 define i64 @llround_f16(half %a) nounwind {
 ; CHECKIZFHMIN-LABEL: llround_f16:
 ; CHECKIZFHMIN:       # %bb.0:
 ; CHECKIZFHMIN-NEXT:    fcvt.s.h fa5, fa0
 ; CHECKIZFHMIN-NEXT:    fcvt.l.s a0, fa5, rmm
 ; CHECKIZFHMIN-NEXT:    ret
+;
+; CHECKIZHINXMIN-LABEL: llround_f16:
+; CHECKIZHINXMIN:       # %bb.0:
+; CHECKIZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; CHECKIZHINXMIN-NEXT:    fcvt.l.s a0, a0, rmm
+; CHECKIZHINXMIN-NEXT:    ret
   %1 = call i64 @llvm.llround.i64.f16(half %a)
   ret i64 %1
 }

llvm/test/CodeGen/RISCV/zfh-half-intrinsics-strict.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+zfh \
 ; RUN:   -verify-machineinstrs -target-abi ilp32f -disable-strictnode-mutation \
 ; RUN:   | FileCheck -check-prefix=RV32IZFH %s
 ; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+zfh \
 ; RUN:   -verify-machineinstrs -target-abi lp64f -disable-strictnode-mutation \
 ; RUN:   | FileCheck -check-prefix=RV64IZFH %s
 ; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+d \
 ; RUN:   -mattr=+zfh -verify-machineinstrs -target-abi ilp32d \
 ; RUN:   -disable-strictnode-mutation | FileCheck -check-prefix=RV32IZFH %s
 ; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+d \
 ; RUN:   -mattr=+zfh -verify-machineinstrs -target-abi lp64d \
 ; RUN:   -disable-strictnode-mutation | FileCheck -check-prefix=RV64IZFH %s
+; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+zhinx \
+; RUN:   -verify-machineinstrs -target-abi ilp32 -disable-strictnode-mutation \
+; RUN:   | FileCheck -check-prefix=RV32IZHINX %s
+; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+zhinx \
+; RUN:   -verify-machineinstrs -target-abi lp64 -disable-strictnode-mutation \
+; RUN:   | FileCheck -check-prefix=RV64IZHINX %s
+; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+zdinx \
+; RUN:   -mattr=+zhinx -verify-machineinstrs -target-abi ilp32 | \
+; RUN:   FileCheck -check-prefix=RV32IZDINXZHINX %s
+; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+zdinx \
+; RUN:   -mattr=+zhinx -verify-machineinstrs -target-abi lp64 | \
+; RUN:   FileCheck -check-prefix=RV64IZDINXZHINX %s
 
 declare half @llvm.experimental.constrained.sqrt.f16(half, metadata, metadata)
 
 define half @sqrt_f16(half %a) nounwind strictfp {
 ; RV32IZFH-LABEL: sqrt_f16:
 ; RV32IZFH:       # %bb.0:
 ; RV32IZFH-NEXT:    fsqrt.h fa0, fa0
 ; RV32IZFH-NEXT:    ret
 ;
 ; RV64IZFH-LABEL: sqrt_f16:
 ; RV64IZFH:       # %bb.0:
 ; RV64IZFH-NEXT:    fsqrt.h fa0, fa0
 ; RV64IZFH-NEXT:    ret
+;
+; RV32IZHINX-LABEL: sqrt_f16:
+; RV32IZHINX:       # %bb.0:
+; RV32IZHINX-NEXT:    fsqrt.h a0, a0
+; RV32IZHINX-NEXT:    ret
+;
+; RV64IZHINX-LABEL: sqrt_f16:
+; RV64IZHINX:       # %bb.0:
+; RV64IZHINX-NEXT:    fsqrt.h a0, a0
+; RV64IZHINX-NEXT:    ret
+;
+; RV32IZDINXZHINX-LABEL: sqrt_f16:
+; RV32IZDINXZHINX:       # %bb.0:
+; RV32IZDINXZHINX-NEXT:    fsqrt.h a0, a0
+; RV32IZDINXZHINX-NEXT:    ret
+;
+; RV64IZDINXZHINX-LABEL: sqrt_f16:
+; RV64IZDINXZHINX:       # %bb.0:
+; RV64IZDINXZHINX-NEXT:    fsqrt.h a0, a0
+; RV64IZDINXZHINX-NEXT:    ret
   %1 = call half @llvm.experimental.constrained.sqrt.f16(half %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
   ret half %1
 }
 
 declare half @llvm.experimental.constrained.floor.f16(half, metadata)
 
 define half @floor_f16(half %a) nounwind strictfp {
 ; RV32IZFH-LABEL: floor_f16:

 ; RV64IZFH-NEXT:    addi sp, sp, -16
 ; RV64IZFH-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64IZFH-NEXT:    fcvt.s.h fa0, fa0
 ; RV64IZFH-NEXT:    call floorf@plt
 ; RV64IZFH-NEXT:    fcvt.h.s fa0, fa0
 ; RV64IZFH-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64IZFH-NEXT:    addi sp, sp, 16
 ; RV64IZFH-NEXT:    ret
+;
+; RV32IZHINX-LABEL: floor_f16:
+; RV32IZHINX:       # %bb.0:
+; RV32IZHINX-NEXT:    addi sp, sp, -16
+; RV32IZHINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZHINX-NEXT:    fcvt.s.h a0, a0
+; RV32IZHINX-NEXT:    call floorf@plt
+; RV32IZHINX-NEXT:    fcvt.h.s a0, a0
+; RV32IZHINX-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZHINX-NEXT:    addi sp, sp, 16
+; RV32IZHINX-NEXT:    ret
+;
+; RV64IZHINX-LABEL: floor_f16:
+; RV64IZHINX:       # %bb.0:
+; RV64IZHINX-NEXT:    addi sp, sp, -16
+; RV64IZHINX-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IZHINX-NEXT:    fcvt.s.h a0, a0
+; RV64IZHINX-NEXT:    call floorf@plt
+; RV64IZHINX-NEXT:    fcvt.h.s a0, a0
+; RV64IZHINX-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
+; RV64IZHINX-NEXT:    addi sp, sp, 16
+; RV64IZHINX-NEXT:    ret
+;
+; RV32IZDINXZHINX-LABEL: floor_f16:
+; RV32IZDINXZHINX:       # %bb.0:
+; RV32IZDINXZHINX-NEXT:    addi sp, sp, -16
+; RV32IZDINXZHINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZDINXZHINX-NEXT:    fcvt.s.h a0, a0
+; RV32IZDINXZHINX-NEXT:    call floorf@plt
+; RV32IZDINXZHINX-NEXT:    fcvt.h.s a0, a0
+; RV32IZDINXZHINX-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZDINXZHINX-NEXT:    addi sp, sp, 16
+; RV32IZDINXZHINX-NEXT:    ret
+;
+; RV64IZDINXZHINX-LABEL: floor_f16:
+; RV64IZDINXZHINX:       # %bb.0:
+; RV64IZDINXZHINX-NEXT:    addi sp, sp, -16
+; RV64IZDINXZHINX-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IZDINXZHINX-NEXT:    fcvt.s.h a0, a0
+; RV64IZDINXZHINX-NEXT:    call floorf@plt
+; RV64IZDINXZHINX-NEXT:    fcvt.h.s a0, a0
+; RV64IZDINXZHINX-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
+; RV64IZDINXZHINX-NEXT:    addi sp, sp, 16
+; RV64IZDINXZHINX-NEXT:    ret
   %1 = call half @llvm.experimental.constrained.floor.f16(half %a, metadata !"fpexcept.strict") strictfp
   ret half %1
 }
 
 declare half @llvm.experimental.constrained.ceil.f16(half, metadata)
 
 define half @ceil_f16(half %a) nounwind strictfp {
 ; RV32IZFH-LABEL: ceil_f16:

 ; RV64IZFH-NEXT:    addi sp, sp, -16
 ; RV64IZFH-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64IZFH-NEXT:    fcvt.s.h fa0, fa0
 ; RV64IZFH-NEXT:    call ceilf@plt
 ; RV64IZFH-NEXT:    fcvt.h.s fa0, fa0
 ; RV64IZFH-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64IZFH-NEXT:    addi sp, sp, 16
 ; RV64IZFH-NEXT:    ret
+;
+; RV32IZHINX-LABEL: ceil_f16:
+; RV32IZHINX:       # %bb.0:
+; RV32IZHINX-NEXT:    addi sp, sp, -16
+; RV32IZHINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZHINX-NEXT:    fcvt.s.h a0, a0
+; RV32IZHINX-NEXT:    call ceilf@plt
+; RV32IZHINX-NEXT:    fcvt.h.s a0, a0
+; RV32IZHINX-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZHINX-NEXT:    addi sp, sp, 16
+; RV32IZHINX-NEXT:    ret
+;
+; RV64IZHINX-LABEL: ceil_f16:
+; RV64IZHINX:       # %bb.0:
+; RV64IZHINX-NEXT:    addi sp, sp, -16
+; RV64IZHINX-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IZHINX-NEXT:    fcvt.s.h a0, a0
+; RV64IZHINX-NEXT:    call ceilf@plt
+; RV64IZHINX-NEXT:    fcvt.h.s a0, a0
+; RV64IZHINX-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
+; RV64IZHINX-NEXT:    addi sp, sp, 16
+; RV64IZHINX-NEXT:    ret
+;
+; RV32IZDINXZHINX-LABEL: ceil_f16:
+; RV32IZDINXZHINX:       # %bb.0:
+; RV32IZDINXZHINX-NEXT:    addi sp, sp, -16
+; RV32IZDINXZHINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZDINXZHINX-NEXT:    fcvt.s.h a0, a0
+; RV32IZDINXZHINX-NEXT:    call ceilf@plt
+; RV32IZDINXZHINX-NEXT:    fcvt.h.s a0, a0
+; RV32IZDINXZHINX-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZDINXZHINX-NEXT:    addi sp, sp, 16
+; RV32IZDINXZHINX-NEXT:    ret
+;
+; RV64IZDINXZHINX-LABEL: ceil_f16:
+; RV64IZDINXZHINX:       # %bb.0:
+; RV64IZDINXZHINX-NEXT:    addi sp, sp, -16
+; RV64IZDINXZHINX-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IZDINXZHINX-NEXT:    fcvt.s.h a0, a0
+; RV64IZDINXZHINX-NEXT:    call ceilf@plt
+; RV64IZDINXZHINX-NEXT:    fcvt.h.s a0, a0
+; RV64IZDINXZHINX-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
+; RV64IZDINXZHINX-NEXT:    addi sp, sp, 16
+; RV64IZDINXZHINX-NEXT:    ret
   %1 = call half @llvm.experimental.constrained.ceil.f16(half %a, metadata !"fpexcept.strict") strictfp
   ret half %1
 }
 
 declare half @llvm.experimental.constrained.trunc.f16(half, metadata)
 
 define half @trunc_f16(half %a) nounwind strictfp {
 ; RV32IZFH-LABEL: trunc_f16:

 ; RV64IZFH-NEXT:    addi sp, sp, -16
 ; RV64IZFH-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64IZFH-NEXT:    fcvt.s.h fa0, fa0
 ; RV64IZFH-NEXT:    call truncf@plt
 ; RV64IZFH-NEXT:    fcvt.h.s fa0, fa0
 ; RV64IZFH-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64IZFH-NEXT:    addi sp, sp, 16
 ; RV64IZFH-NEXT:    ret
+;
+; RV32IZHINX-LABEL: trunc_f16:
+; RV32IZHINX:       # %bb.0:
+; RV32IZHINX-NEXT:    addi sp, sp, -16
+; RV32IZHINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZHINX-NEXT:    fcvt.s.h a0, a0
+; RV32IZHINX-NEXT:    call truncf@plt
+; RV32IZHINX-NEXT:    fcvt.h.s a0, a0
+; RV32IZHINX-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZHINX-NEXT:    addi sp, sp, 16
+; RV32IZHINX-NEXT:    ret
+;
+; RV64IZHINX-LABEL: trunc_f16:
+; RV64IZHINX:       # %bb.0:
+; RV64IZHINX-NEXT:    addi sp, sp, -16
+; RV64IZHINX-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IZHINX-NEXT:    fcvt.s.h a0, a0
+; RV64IZHINX-NEXT:    call truncf@plt
+; RV64IZHINX-NEXT:    fcvt.h.s a0, a0
+; RV64IZHINX-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
+; RV64IZHINX-NEXT:    addi sp, sp, 16
+; RV64IZHINX-NEXT:    ret
+;
+; RV32IZDINXZHINX-LABEL: trunc_f16:
+; RV32IZDINXZHINX:       # %bb.0:
+; RV32IZDINXZHINX-NEXT:    addi sp, sp, -16
+; RV32IZDINXZHINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZDINXZHINX-NEXT:    fcvt.s.h a0, a0
+; RV32IZDINXZHINX-NEXT:    call truncf@plt
+; RV32IZDINXZHINX-NEXT:    fcvt.h.s a0, a0
+; RV32IZDINXZHINX-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZDINXZHINX-NEXT:    addi sp, sp, 16
+; RV32IZDINXZHINX-NEXT:    ret
+;
+; RV64IZDINXZHINX-LABEL: trunc_f16:
+; RV64IZDINXZHINX:       # %bb.0:
+; RV64IZDINXZHINX-NEXT:    addi sp, sp, -16
+; RV64IZDINXZHINX-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IZDINXZHINX-NEXT:    fcvt.s.h a0, a0
+; RV64IZDINXZHINX-NEXT:    call truncf@plt
+; RV64IZDINXZHINX-NEXT:    fcvt.h.s a0, a0
+; RV64IZDINXZHINX-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
+; RV64IZDINXZHINX-NEXT:    addi sp, sp, 16
+; RV64IZDINXZHINX-NEXT:    ret
   %1 = call half @llvm.experimental.constrained.trunc.f16(half %a, metadata !"fpexcept.strict") strictfp
   ret half %1
 }
 
 declare half @llvm.experimental.constrained.rint.f16(half, metadata, metadata)
 
 define half @rint_f16(half %a) nounwind strictfp {
 ; RV32IZFH-LABEL: rint_f16:

 ; RV64IZFH-NEXT:    addi sp, sp, -16
 ; RV64IZFH-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64IZFH-NEXT:    fcvt.s.h fa0, fa0
 ; RV64IZFH-NEXT:    call rintf@plt
 ; RV64IZFH-NEXT:    fcvt.h.s fa0, fa0
 ; RV64IZFH-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64IZFH-NEXT:    addi sp, sp, 16
 ; RV64IZFH-NEXT:    ret
+;
+; RV32IZHINX-LABEL: rint_f16:
+; RV32IZHINX:       # %bb.0:
+; RV32IZHINX-NEXT:    addi sp, sp, -16
+; RV32IZHINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZHINX-NEXT:    fcvt.s.h a0, a0
+; RV32IZHINX-NEXT:    call rintf@plt
+; RV32IZHINX-NEXT:    fcvt.h.s a0, a0
+; RV32IZHINX-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZHINX-NEXT:    addi sp, sp, 16
+; RV32IZHINX-NEXT:    ret
+;
+; RV64IZHINX-LABEL: rint_f16:
+; RV64IZHINX:       # %bb.0:
+; RV64IZHINX-NEXT:    addi sp, sp, -16
+; RV64IZHINX-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IZHINX-NEXT:    fcvt.s.h a0, a0
+; RV64IZHINX-NEXT:    call rintf@plt
+; RV64IZHINX-NEXT:    fcvt.h.s a0, a0
+; RV64IZHINX-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
+; RV64IZHINX-NEXT:    addi sp, sp, 16
+; RV64IZHINX-NEXT:    ret
+;
+; RV32IZDINXZHINX-LABEL: rint_f16:
+; RV32IZDINXZHINX:       # %bb.0:
+; RV32IZDINXZHINX-NEXT:    addi sp, sp, -16
+; RV32IZDINXZHINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZDINXZHINX-NEXT:    fcvt.s.h a0, a0
+; RV32IZDINXZHINX-NEXT:    call rintf@plt
+; RV32IZDINXZHINX-NEXT:    fcvt.h.s a0, a0
+; RV32IZDINXZHINX-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZDINXZHINX-NEXT:    addi sp, sp, 16
+; RV32IZDINXZHINX-NEXT:    ret
+;
+; RV64IZDINXZHINX-LABEL: rint_f16:
+; RV64IZDINXZHINX:       # %bb.0:
+; RV64IZDINXZHINX-NEXT:    addi sp, sp, -16
+; RV64IZDINXZHINX-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IZDINXZHINX-NEXT:    fcvt.s.h a0, a0
+; RV64IZDINXZHINX-NEXT:    call rintf@plt
+; RV64IZDINXZHINX-NEXT:    fcvt.h.s a0, a0
+; RV64IZDINXZHINX-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
+; RV64IZDINXZHINX-NEXT:    addi sp, sp, 16
+; RV64IZDINXZHINX-NEXT:    ret
   %1 = call half @llvm.experimental.constrained.rint.f16(half %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
   ret half %1
 }
 
 declare half @llvm.experimental.constrained.nearbyint.f16(half, metadata, metadata)
 
 define half @nearbyint_f16(half %a) nounwind strictfp {
 ; RV32IZFH-LABEL: nearbyint_f16:

 ; RV64IZFH-NEXT:    addi sp, sp, -16
 ; RV64IZFH-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64IZFH-NEXT:    fcvt.s.h fa0, fa0
 ; RV64IZFH-NEXT:    call nearbyintf@plt
 ; RV64IZFH-NEXT:    fcvt.h.s fa0, fa0
 ; RV64IZFH-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64IZFH-NEXT:    addi sp, sp, 16
 ; RV64IZFH-NEXT:    ret
+;
+; RV32IZHINX-LABEL: nearbyint_f16:
+; RV32IZHINX:       # %bb.0:
+; RV32IZHINX-NEXT:    addi sp, sp, -16
+; RV32IZHINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZHINX-NEXT:    fcvt.s.h a0, a0
+; RV32IZHINX-NEXT:    call nearbyintf@plt
+; RV32IZHINX-NEXT:    fcvt.h.s a0, a0
+; RV32IZHINX-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZHINX-NEXT:    addi sp, sp, 16
+; RV32IZHINX-NEXT:    ret
+;
+; RV64IZHINX-LABEL: nearbyint_f16:
+; RV64IZHINX:       # %bb.0:
+; RV64IZHINX-NEXT:    addi sp, sp, -16
+; RV64IZHINX-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IZHINX-NEXT:    fcvt.s.h a0, a0
+; RV64IZHINX-NEXT:    call nearbyintf@plt
+; RV64IZHINX-NEXT:    fcvt.h.s a0, a0
+; RV64IZHINX-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
+; RV64IZHINX-NEXT:    addi sp, sp, 16
+; RV64IZHINX-NEXT:    ret
+;
+; RV32IZDINXZHINX-LABEL: nearbyint_f16:
+; RV32IZDINXZHINX:       # %bb.0:
+; RV32IZDINXZHINX-NEXT:    addi sp, sp, -16
+; RV32IZDINXZHINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZDINXZHINX-NEXT:    fcvt.s.h a0, a0
+; RV32IZDINXZHINX-NEXT:    call nearbyintf@plt
+; RV32IZDINXZHINX-NEXT:    fcvt.h.s a0, a0
+; RV32IZDINXZHINX-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZDINXZHINX-NEXT:    addi sp, sp, 16
+; RV32IZDINXZHINX-NEXT:    ret
+;
+; RV64IZDINXZHINX-LABEL: nearbyint_f16:
+; RV64IZDINXZHINX:       # %bb.0:
+; RV64IZDINXZHINX-NEXT:    addi sp, sp, -16
+; RV64IZDINXZHINX-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IZDINXZHINX-NEXT:    fcvt.s.h a0, a0
+; RV64IZDINXZHINX-NEXT:    call nearbyintf@plt
+; RV64IZDINXZHINX-NEXT:    fcvt.h.s a0, a0
+; RV64IZDINXZHINX-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
+; RV64IZDINXZHINX-NEXT:    addi sp, sp, 16
+; RV64IZDINXZHINX-NEXT:    ret
   %1 = call half @llvm.experimental.constrained.nearbyint.f16(half %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
   ret half %1
 }
 
 declare half @llvm.experimental.constrained.round.f16(half, metadata)
 
 define half @round_f16(half %a) nounwind strictfp {
 ; RV32IZFH-LABEL: round_f16:

 ; RV64IZFH-NEXT:    addi sp, sp, -16
 ; RV64IZFH-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64IZFH-NEXT:    fcvt.s.h fa0, fa0
 ; RV64IZFH-NEXT:    call roundf@plt
 ; RV64IZFH-NEXT:    fcvt.h.s fa0, fa0
 ; RV64IZFH-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64IZFH-NEXT:    addi sp, sp, 16
 ; RV64IZFH-NEXT:    ret
+;
+; RV32IZHINX-LABEL: round_f16:
+; RV32IZHINX:       # %bb.0:
+; RV32IZHINX-NEXT:    addi sp, sp, -16
+; RV32IZHINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZHINX-NEXT:    fcvt.s.h a0, a0
+; RV32IZHINX-NEXT:    call roundf@plt
+; RV32IZHINX-NEXT:    fcvt.h.s a0, a0
+; RV32IZHINX-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZHINX-NEXT:    addi sp, sp, 16
+; RV32IZHINX-NEXT:    ret
+;
+; RV64IZHINX-LABEL: round_f16:
+; RV64IZHINX:       # %bb.0:
+; RV64IZHINX-NEXT:    addi sp, sp, -16
+; RV64IZHINX-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IZHINX-NEXT:    fcvt.s.h a0, a0
+; RV64IZHINX-NEXT:    call roundf@plt
+; RV64IZHINX-NEXT:    fcvt.h.s a0, a0
+; RV64IZHINX-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
+; RV64IZHINX-NEXT:    addi sp, sp, 16
+; RV64IZHINX-NEXT:    ret
+;
+; RV32IZDINXZHINX-LABEL: round_f16:
+; RV32IZDINXZHINX:       # %bb.0:
+; RV32IZDINXZHINX-NEXT:    addi sp, sp, -16
+; RV32IZDINXZHINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZDINXZHINX-NEXT:    fcvt.s.h a0, a0
+; RV32IZDINXZHINX-NEXT:    call roundf@plt
+; RV32IZDINXZHINX-NEXT:    fcvt.h.s a0, a0
+; RV32IZDINXZHINX-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZDINXZHINX-NEXT:    addi sp, sp, 16
+; RV32IZDINXZHINX-NEXT:    ret
+;
+; RV64IZDINXZHINX-LABEL: round_f16:
+; RV64IZDINXZHINX:       # %bb.0:
+; RV64IZDINXZHINX-NEXT:    addi sp, sp, -16
+; RV64IZDINXZHINX-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IZDINXZHINX-NEXT:    fcvt.s.h a0, a0
+; RV64IZDINXZHINX-NEXT:    call roundf@plt
+; RV64IZDINXZHINX-NEXT:    fcvt.h.s a0, a0
+; RV64IZDINXZHINX-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
+; RV64IZDINXZHINX-NEXT:    addi sp, sp, 16
+; RV64IZDINXZHINX-NEXT:    ret
   %1 = call half @llvm.experimental.constrained.round.f16(half %a, metadata !"fpexcept.strict") strictfp
   ret half %1
 }
 
 declare half @llvm.experimental.constrained.roundeven.f16(half, metadata)
 
 define half @roundeven_f16(half %a) nounwind strictfp {
 ; RV32IZFH-LABEL: roundeven_f16:

 ; RV64IZFH-NEXT:    addi sp, sp, -16
 ; RV64IZFH-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64IZFH-NEXT:    fcvt.s.h fa0, fa0
 ; RV64IZFH-NEXT:    call roundevenf@plt
 ; RV64IZFH-NEXT:    fcvt.h.s fa0, fa0
 ; RV64IZFH-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64IZFH-NEXT:    addi sp, sp, 16
 ; RV64IZFH-NEXT:    ret
+;
+; RV32IZHINX-LABEL: roundeven_f16:
+; RV32IZHINX:       # %bb.0:
+; RV32IZHINX-NEXT:    addi sp, sp, -16
+; RV32IZHINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZHINX-NEXT:    fcvt.s.h a0, a0
+; RV32IZHINX-NEXT:    call roundevenf@plt
+; RV32IZHINX-NEXT:    fcvt.h.s a0, a0
+; RV32IZHINX-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZHINX-NEXT:    addi sp, sp, 16
+; RV32IZHINX-NEXT:    ret
+;
+; RV64IZHINX-LABEL: roundeven_f16:
+; RV64IZHINX:       # %bb.0:
+; RV64IZHINX-NEXT:    addi sp, sp, -16
+; RV64IZHINX-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IZHINX-NEXT:    fcvt.s.h a0, a0
+; RV64IZHINX-NEXT:    call roundevenf@plt
+; RV64IZHINX-NEXT:    fcvt.h.s a0, a0
+; RV64IZHINX-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
+; RV64IZHINX-NEXT:    addi sp, sp, 16
+; RV64IZHINX-NEXT:    ret
+;
+; RV32IZDINXZHINX-LABEL: roundeven_f16:
+; RV32IZDINXZHINX:       # %bb.0:
+; RV32IZDINXZHINX-NEXT:    addi sp, sp, -16
+; RV32IZDINXZHINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZDINXZHINX-NEXT:    fcvt.s.h a0, a0
+; RV32IZDINXZHINX-NEXT:    call roundevenf@plt
+; RV32IZDINXZHINX-NEXT:    fcvt.h.s a0, a0
+; RV32IZDINXZHINX-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZDINXZHINX-NEXT:    addi sp, sp, 16
+; RV32IZDINXZHINX-NEXT:    ret
+;
+; RV64IZDINXZHINX-LABEL: roundeven_f16:
+; RV64IZDINXZHINX:       # %bb.0:
+; RV64IZDINXZHINX-NEXT:    addi sp, sp, -16
+; RV64IZDINXZHINX-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IZDINXZHINX-NEXT:    fcvt.s.h a0, a0
+; RV64IZDINXZHINX-NEXT:    call roundevenf@plt
+; RV64IZDINXZHINX-NEXT:    fcvt.h.s a0, a0
+; RV64IZDINXZHINX-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
+; RV64IZDINXZHINX-NEXT:    addi sp, sp, 16
+; RV64IZDINXZHINX-NEXT:    ret
   %1 = call half @llvm.experimental.constrained.roundeven.f16(half %a, metadata !"fpexcept.strict") strictfp
   ret half %1
 }
 
 declare iXLen @llvm.experimental.constrained.lrint.iXLen.f16(half, metadata, metadata)
 
 define iXLen @lrint_f16(half %a) nounwind strictfp {
 ; RV32IZFH-LABEL: lrint_f16:
 ; RV32IZFH:       # %bb.0:
 ; RV32IZFH-NEXT:    fcvt.w.h a0, fa0
 ; RV32IZFH-NEXT:    ret
 ;
 ; RV64IZFH-LABEL: lrint_f16:
 ; RV64IZFH:       # %bb.0:
 ; RV64IZFH-NEXT:    fcvt.l.h a0, fa0
 ; RV64IZFH-NEXT:    ret
+;
+; RV32IZHINX-LABEL: lrint_f16:
+; RV32IZHINX:       # %bb.0:
+; RV32IZHINX-NEXT:    fcvt.w.h a0, a0
+; RV32IZHINX-NEXT:    ret
+;
+; RV64IZHINX-LABEL: lrint_f16:
+; RV64IZHINX:       # %bb.0:
+; RV64IZHINX-NEXT:    fcvt.l.h a0, a0
+; RV64IZHINX-NEXT:    ret
+;
+; RV32IZDINXZHINX-LABEL: lrint_f16:
+; RV32IZDINXZHINX:       # %bb.0:
+; RV32IZDINXZHINX-NEXT:    fcvt.w.h a0, a0
+; RV32IZDINXZHINX-NEXT:    ret
+;
+; RV64IZDINXZHINX-LABEL: lrint_f16:
+; RV64IZDINXZHINX:       # %bb.0:
+; RV64IZDINXZHINX-NEXT:    fcvt.l.h a0, a0
+; RV64IZDINXZHINX-NEXT:    ret
   %1 = call iXLen @llvm.experimental.constrained.lrint.iXLen.f16(half %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
   ret iXLen %1
 }
 
 declare iXLen @llvm.experimental.constrained.lround.iXLen.f16(half, metadata)
 
 define iXLen @lround_f16(half %a) nounwind strictfp {
 ; RV32IZFH-LABEL: lround_f16:
 ; RV32IZFH:       # %bb.0:
 ; RV32IZFH-NEXT:    fcvt.w.h a0, fa0, rmm
 ; RV32IZFH-NEXT:    ret
 ;
 ; RV64IZFH-LABEL: lround_f16:
 ; RV64IZFH:       # %bb.0:
 ; RV64IZFH-NEXT:    fcvt.l.h a0, fa0, rmm
 ; RV64IZFH-NEXT:    ret
+;
+; RV32IZHINX-LABEL: lround_f16:
+; RV32IZHINX:       # %bb.0:
+; RV32IZHINX-NEXT:    fcvt.w.h a0, a0, rmm
+; RV32IZHINX-NEXT:    ret
+;
+; RV64IZHINX-LABEL: lround_f16:
+; RV64IZHINX:       # %bb.0:
+; RV64IZHINX-NEXT:    fcvt.l.h a0, a0, rmm
+; RV64IZHINX-NEXT:    ret
+;
+; RV32IZDINXZHINX-LABEL: lround_f16:
+; RV32IZDINXZHINX:       # %bb.0:
+; RV32IZDINXZHINX-NEXT:    fcvt.w.h a0, a0, rmm
+; RV32IZDINXZHINX-NEXT:    ret
+;
+; RV64IZDINXZHINX-LABEL: lround_f16:
+; RV64IZDINXZHINX:       # %bb.0:
+; RV64IZDINXZHINX-NEXT:    fcvt.l.h a0, a0, rmm
+; RV64IZDINXZHINX-NEXT:    ret
   %1 = call iXLen @llvm.experimental.constrained.lround.iXLen.f16(half %a, metadata !"fpexcept.strict") strictfp
   ret iXLen %1
 }
 
 declare i64 @llvm.experimental.constrained.llrint.i64.f16(half, metadata, metadata)
 
 define i64 @llrint_f16(half %a) nounwind strictfp {
 ; RV32IZFH-LABEL: llrint_f16:
 ; RV32IZFH:       # %bb.0:
 ; RV32IZFH-NEXT:    addi sp, sp, -16
 ; RV32IZFH-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32IZFH-NEXT:    fcvt.s.h fa0, fa0
 ; RV32IZFH-NEXT:    call llrintf@plt
 ; RV32IZFH-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32IZFH-NEXT:    addi sp, sp, 16
 ; RV32IZFH-NEXT:    ret
 ;
 ; RV64IZFH-LABEL: llrint_f16:
 ; RV64IZFH:       # %bb.0:
 ; RV64IZFH-NEXT:    fcvt.l.h a0, fa0
 ; RV64IZFH-NEXT:    ret
+;
+; RV32IZHINX-LABEL: llrint_f16:
+; RV32IZHINX:       # %bb.0:
+; RV32IZHINX-NEXT:    addi sp, sp, -16
+; RV32IZHINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZHINX-NEXT:    fcvt.s.h a0, a0
+; RV32IZHINX-NEXT:    call llrintf@plt
+; RV32IZHINX-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZHINX-NEXT:    addi sp, sp, 16
+; RV32IZHINX-NEXT:    ret
+;
+; RV64IZHINX-LABEL: llrint_f16:
+; RV64IZHINX:       # %bb.0:
+; RV64IZHINX-NEXT:    fcvt.l.h a0, a0
+; RV64IZHINX-NEXT:    ret
+;
+; RV32IZDINXZHINX-LABEL: llrint_f16:
+; RV32IZDINXZHINX:       # %bb.0:
+; RV32IZDINXZHINX-NEXT:    addi sp, sp, -16
+; RV32IZDINXZHINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZDINXZHINX-NEXT:    fcvt.s.h a0, a0
+; RV32IZDINXZHINX-NEXT:    call llrintf@plt
+; RV32IZDINXZHINX-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZDINXZHINX-NEXT:    addi sp, sp, 16
+; RV32IZDINXZHINX-NEXT:    ret
+;
+; RV64IZDINXZHINX-LABEL: llrint_f16:
+; RV64IZDINXZHINX:       # %bb.0:
+; RV64IZDINXZHINX-NEXT:    fcvt.l.h a0, a0
+; RV64IZDINXZHINX-NEXT:    ret
   %1 = call i64 @llvm.experimental.constrained.llrint.i64.f16(half %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
   ret i64 %1
 }
 
 declare i64 @llvm.experimental.constrained.llround.i64.f16(half, metadata)
 
 define i64 @llround_f16(half %a) nounwind strictfp {
 ; RV32IZFH-LABEL: llround_f16:
 ; RV32IZFH:       # %bb.0:
 ; RV32IZFH-NEXT:    addi sp, sp, -16
 ; RV32IZFH-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32IZFH-NEXT:    fcvt.s.h fa0, fa0
 ; RV32IZFH-NEXT:    call llroundf@plt
 ; RV32IZFH-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32IZFH-NEXT:    addi sp, sp, 16
 ; RV32IZFH-NEXT:    ret
 ;
 ; RV64IZFH-LABEL: llround_f16:
 ; RV64IZFH:       # %bb.0:
 ; RV64IZFH-NEXT:    fcvt.l.h a0, fa0, rmm
 ; RV64IZFH-NEXT:    ret
+;
+; RV32IZHINX-LABEL: llround_f16:
+; RV32IZHINX:       # %bb.0:
+; RV32IZHINX-NEXT:    addi sp, sp, -16
+; RV32IZHINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZHINX-NEXT:    fcvt.s.h a0, a0
+; RV32IZHINX-NEXT:    call llroundf@plt
+; RV32IZHINX-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZHINX-NEXT:    addi sp, sp, 16
+; RV32IZHINX-NEXT:    ret
+;
+; RV64IZHINX-LABEL: llround_f16:
+; RV64IZHINX:       # %bb.0:
+; RV64IZHINX-NEXT:    fcvt.l.h a0, a0, rmm
+; RV64IZHINX-NEXT:    ret
+;
+; RV32IZDINXZHINX-LABEL: llround_f16:
+; RV32IZDINXZHINX:       # %bb.0:
+; RV32IZDINXZHINX-NEXT:    addi sp, sp, -16
+; RV32IZDINXZHINX-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZDINXZHINX-NEXT:    fcvt.s.h a0, a0
+; RV32IZDINXZHINX-NEXT:    call llroundf@plt
+; RV32IZDINXZHINX-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZDINXZHINX-NEXT:    addi sp, sp, 16
+; RV32IZDINXZHINX-NEXT:    ret
+;
+; RV64IZDINXZHINX-LABEL: llround_f16:
+; RV64IZDINXZHINX:       # %bb.0:
+; RV64IZDINXZHINX-NEXT:    fcvt.l.h a0, a0, rmm
+; RV64IZDINXZHINX-NEXT:    ret
   %1 = call i64 @llvm.experimental.constrained.llround.i64.f16(half %a, metadata !"fpexcept.strict") strictfp
   ret i64 %1
 }

llvm/test/CodeGen/RISCV/zfh-half-intrinsics.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+zfh \
 ; RUN:   -verify-machineinstrs -target-abi ilp32f | \
 ; RUN:   FileCheck -check-prefix=RV32IZFH %s
 ; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+zfh \
 ; RUN:   -verify-machineinstrs -target-abi lp64f | \
 ; RUN:   FileCheck -check-prefix=RV64IZFH %s
+; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=zhinx \
+; RUN:   -verify-machineinstrs -target-abi ilp32 | \
+; RUN:   FileCheck -check-prefix=RV32IZHINX %s
+; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=zhinx \
+; RUN:   -verify-machineinstrs -target-abi lp64 | \
+; RUN:   FileCheck -check-prefix=RV64IZHINX %s
 ; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+d \
 ; RUN:   -mattr=+zfh -verify-machineinstrs -target-abi ilp32d | \
 ; RUN:   FileCheck -check-prefix=RV32IDZFH %s
 ; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+d \
 ; RUN:   -mattr=+zfh -verify-machineinstrs -target-abi lp64d | \
 ; RUN:   FileCheck -check-prefix=RV64IDZFH %s
+; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+zdinx \
+; RUN:   -mattr=+zhinx -verify-machineinstrs -target-abi ilp32 | \
+; RUN:   FileCheck -check-prefix=RV32IZDINXZHINX %s
+; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+zdinx \
+; RUN:   -mattr=+zhinx -verify-machineinstrs -target-abi lp64 | \
+; RUN:   FileCheck -check-prefix=RV64IZDINXZHINX %s
 
 ; These intrinsics require half to be a legal type.
 
 declare iXLen @llvm.lrint.iXLen.f16(half)
 
 define iXLen @lrint_f16(half %a) nounwind {
 ; RV32IZFH-LABEL: lrint_f16:
 ; RV32IZFH:       # %bb.0:
 ; RV32IZFH-NEXT:    fcvt.w.h a0, fa0
 ; RV32IZFH-NEXT:    ret
 ;
 ; RV64IZFH-LABEL: lrint_f16:
 ; RV64IZFH:       # %bb.0:
 ; RV64IZFH-NEXT:    fcvt.l.h a0, fa0
 ; RV64IZFH-NEXT:    ret
 ;
+; RV32IZHINX-LABEL: lrint_f16:
+; RV32IZHINX:       # %bb.0:
+; RV32IZHINX-NEXT:    fcvt.w.h a0, a0
+; RV32IZHINX-NEXT:    ret
+;
+; RV64IZHINX-LABEL: lrint_f16:
+; RV64IZHINX:       # %bb.0:
+; RV64IZHINX-NEXT:    fcvt.l.h a0, a0
+; RV64IZHINX-NEXT:    ret
+;
 ; RV32IDZFH-LABEL: lrint_f16:
 ; RV32IDZFH:       # %bb.0:
 ; RV32IDZFH-NEXT:    fcvt.w.h a0, fa0
 ; RV32IDZFH-NEXT:    ret
 ;
 ; RV64IDZFH-LABEL: lrint_f16:
 ; RV64IDZFH:       # %bb.0:
 ; RV64IDZFH-NEXT:    fcvt.l.h a0, fa0
 ; RV64IDZFH-NEXT:    ret
+;
+; RV32IZDINXZHINX-LABEL: lrint_f16:
+; RV32IZDINXZHINX:       # %bb.0:
+; RV32IZDINXZHINX-NEXT:    fcvt.w.h a0, a0
+; RV32IZDINXZHINX-NEXT:    ret
+;
+; RV64IZDINXZHINX-LABEL: lrint_f16:
+; RV64IZDINXZHINX:       # %bb.0:
+; RV64IZDINXZHINX-NEXT:    fcvt.l.h a0, a0
+; RV64IZDINXZHINX-NEXT:    ret
   %1 = call iXLen @llvm.lrint.iXLen.f16(half %a)
   ret iXLen %1
 }
 
 declare i32 @llvm.lround.i32.f16(half)
 declare i64 @llvm.lround.i64.f16(half)
 
 define iXLen @lround_f16(half %a) nounwind {
 ; RV32IZFH-LABEL: lround_f16:
 ; RV32IZFH:       # %bb.0:
 ; RV32IZFH-NEXT:    fcvt.w.h a0, fa0, rmm
 ; RV32IZFH-NEXT:    ret
 ;
 ; RV64IZFH-LABEL: lround_f16:
 ; RV64IZFH:       # %bb.0:
 ; RV64IZFH-NEXT:    fcvt.l.h a0, fa0, rmm
 ; RV64IZFH-NEXT:    ret
 ;
+; RV32IZHINX-LABEL: lround_f16:
+; RV32IZHINX:       # %bb.0:
+; RV32IZHINX-NEXT:    fcvt.w.h a0, a0, rmm
+; RV32IZHINX-NEXT:    ret
+;
+; RV64IZHINX-LABEL: lround_f16:
+; RV64IZHINX:       # %bb.0:
+; RV64IZHINX-NEXT:    fcvt.l.h a0, a0, rmm
+; RV64IZHINX-NEXT:    ret
+;
 ; RV32IDZFH-LABEL: lround_f16:
 ; RV32IDZFH:       # %bb.0:
 ; RV32IDZFH-NEXT:    fcvt.w.h a0, fa0, rmm
 ; RV32IDZFH-NEXT:    ret
 ;
 ; RV64IDZFH-LABEL: lround_f16:
 ; RV64IDZFH:       # %bb.0:
 ; RV64IDZFH-NEXT:    fcvt.l.h a0, fa0, rmm
 ; RV64IDZFH-NEXT:    ret
+;
+; RV32IZDINXZHINX-LABEL: lround_f16:
+; RV32IZDINXZHINX:       # %bb.0:
+; RV32IZDINXZHINX-NEXT:    fcvt.w.h a0, a0, rmm
+; RV32IZDINXZHINX-NEXT:    ret
+;
+; RV64IZDINXZHINX-LABEL: lround_f16:
+; RV64IZDINXZHINX:       # %bb.0:
+; RV64IZDINXZHINX-NEXT:    fcvt.l.h a0, a0, rmm
+; RV64IZDINXZHINX-NEXT:    ret
   %1 = call iXLen @llvm.lround.iXLen.f16(half %a)
   ret iXLen %1
 }
 
 define i32 @lround_i32_f16(half %a) nounwind {
 ; RV32IZFH-LABEL: lround_i32_f16:
 ; RV32IZFH:       # %bb.0:
 ; RV32IZFH-NEXT:    fcvt.w.h a0, fa0, rmm
 ; RV32IZFH-NEXT:    ret
 ;
 ; RV64IZFH-LABEL: lround_i32_f16:
 ; RV64IZFH:       # %bb.0:
 ; RV64IZFH-NEXT:    fcvt.w.h a0, fa0, rmm
 ; RV64IZFH-NEXT:    ret
 ;
+; RV32IZHINX-LABEL: lround_i32_f16:
+; RV32IZHINX:       # %bb.0:
+; RV32IZHINX-NEXT:    fcvt.w.h a0, a0, rmm
+; RV32IZHINX-NEXT:    ret
+;
+; RV64IZHINX-LABEL: lround_i32_f16:
+; RV64IZHINX:       # %bb.0:
+; RV64IZHINX-NEXT:    fcvt.w.h a0, a0, rmm
+; RV64IZHINX-NEXT:    ret
+;
 ; RV32IDZFH-LABEL: lround_i32_f16:
 ; RV32IDZFH:       # %bb.0:
 ; RV32IDZFH-NEXT:    fcvt.w.h a0, fa0, rmm
 ; RV32IDZFH-NEXT:    ret
 ;
 ; RV64IDZFH-LABEL: lround_i32_f16:
 ; RV64IDZFH:       # %bb.0:
 ; RV64IDZFH-NEXT:    fcvt.w.h a0, fa0, rmm
 ; RV64IDZFH-NEXT:    ret
+;
+; RV32IZDINXZHINX-LABEL: lround_i32_f16:
+; RV32IZDINXZHINX:       # %bb.0:
+; RV32IZDINXZHINX-NEXT:    fcvt.w.h a0, a0, rmm
+; RV32IZDINXZHINX-NEXT:    ret
+;
+; RV64IZDINXZHINX-LABEL: lround_i32_f16:
+; RV64IZDINXZHINX:       # %bb.0:
+; RV64IZDINXZHINX-NEXT:    fcvt.w.h a0, a0, rmm
+; RV64IZDINXZHINX-NEXT:    ret
   %1 = call i32 @llvm.lround.i32.f16(half %a)
   ret i32 %1
 }

llvm/test/CodeGen/RISCV/zfh-imm.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -target-abi ilp32f -mattr=+zfh < %s \
 ; RUN:     | FileCheck --check-prefix=RV32IZFH %s
 ; RUN: llc -mtriple=riscv32 -target-abi ilp32d -mattr=+zfh,+d < %s \
 ; RUN:     | FileCheck --check-prefix=RV32IDZFH %s
 ; RUN: llc -mtriple=riscv64 -target-abi lp64f -mattr=+zfh < %s \
 ; RUN:     | FileCheck --check-prefix=RV64IZFH %s
 ; RUN: llc -mtriple=riscv64 -target-abi lp64d -mattr=+zfh,+d < %s \
 ; RUN:     | FileCheck --check-prefix=RV64IDZFH %s
+; RUN: llc -mtriple=riscv32 -target-abi ilp32 -mattr=+zhinx < %s \
+; RUN:     | FileCheck --check-prefix=RV32IZHINX %s
+; RUN: llc -mtriple=riscv32 -target-abi ilp32 -mattr=+zhinx,+zdinx < %s \
+; RUN:     | FileCheck --check-prefix=RV32IZDINXZHINX %s
+; RUN: llc -mtriple=riscv64 -target-abi lp64 -mattr=+zhinx < %s \
+; RUN:     | FileCheck --check-prefix=RV64IZHINX %s
+; RUN: llc -mtriple=riscv64 -target-abi lp64 -mattr=+zhinx,+zdinx < %s \
+; RUN:     | FileCheck --check-prefix=RV64IZDINXZHINX %s
 
 define half @f16_positive_zero(ptr %pf) nounwind {
 ; RV32IZFH-LABEL: f16_positive_zero:
 ; RV32IZFH:       # %bb.0:
 ; RV32IZFH-NEXT:    fmv.h.x fa0, zero
 ; RV32IZFH-NEXT:    ret
 ;
 ; RV32IDZFH-LABEL: f16_positive_zero:
 ; RV32IDZFH:       # %bb.0:
 ; RV32IDZFH-NEXT:    fmv.h.x fa0, zero
 ; RV32IDZFH-NEXT:    ret
 ;
 ; RV64IZFH-LABEL: f16_positive_zero:
 ; RV64IZFH:       # %bb.0:
 ; RV64IZFH-NEXT:    fmv.h.x fa0, zero
 ; RV64IZFH-NEXT:    ret
 ;
 ; RV64IDZFH-LABEL: f16_positive_zero:
 ; RV64IDZFH:       # %bb.0:
 ; RV64IDZFH-NEXT:    fmv.h.x fa0, zero
 ; RV64IDZFH-NEXT:    ret
+;
+; RV32IZHINX-LABEL: f16_positive_zero:
+; RV32IZHINX:       # %bb.0:
+; RV32IZHINX-NEXT:    li a0, 0
+; RV32IZHINX-NEXT:    ret
+;
+; RV32IZDINXZHINX-LABEL: f16_positive_zero:
+; RV32IZDINXZHINX:       # %bb.0:
+; RV32IZDINXZHINX-NEXT:    li a0, 0
+; RV32IZDINXZHINX-NEXT:    ret
+;
+; RV64IZHINX-LABEL: f16_positive_zero:
+; RV64IZHINX:       # %bb.0:
+; RV64IZHINX-NEXT:    li a0, 0
+; RV64IZHINX-NEXT:    ret
+;
+; RV64IZDINXZHINX-LABEL: f16_positive_zero:
+; RV64IZDINXZHINX:       # %bb.0:
+; RV64IZDINXZHINX-NEXT:    li a0, 0
+; RV64IZDINXZHINX-NEXT:    ret
   ret half 0.0
 }
 
 define half @f16_negative_zero(ptr %pf) nounwind {
 ; RV32IZFH-LABEL: f16_negative_zero:
 ; RV32IZFH:       # %bb.0:
 ; RV32IZFH-NEXT:    lui a0, 1048568
 ; RV32IZFH-NEXT:    fmv.h.x fa0, a0

 ; RV64IZFH-NEXT:    fmv.h.x fa0, a0
 ; RV64IZFH-NEXT:    ret
 ;
 ; RV64IDZFH-LABEL: f16_negative_zero:
 ; RV64IDZFH:       # %bb.0:
 ; RV64IDZFH-NEXT:    lui a0, 1048568
 ; RV64IDZFH-NEXT:    fmv.h.x fa0, a0
 ; RV64IDZFH-NEXT:    ret
+;
+; RV32IZHINX-LABEL: f16_negative_zero:
+; RV32IZHINX:       # %bb.0:
+; RV32IZHINX-NEXT:    lui a0, 1048568
+; RV32IZHINX-NEXT:    ret
+;
+; RV32IZDINXZHINX-LABEL: f16_negative_zero:
+; RV32IZDINXZHINX:       # %bb.0:
+; RV32IZDINXZHINX-NEXT:    lui a0, 1048568
+; RV32IZDINXZHINX-NEXT:    ret
+;
+; RV64IZHINX-LABEL: f16_negative_zero:
+; RV64IZHINX:       # %bb.0:
+; RV64IZHINX-NEXT:    lui a0, 1048568
+; RV64IZHINX-NEXT:    ret
+;
+; RV64IZDINXZHINX-LABEL: f16_negative_zero:
+; RV64IZDINXZHINX:       # %bb.0:
+; RV64IZDINXZHINX-NEXT:    lui a0, 1048568
+; RV64IZDINXZHINX-NEXT:    ret
   ret half -0.0
 }

llvm/test/CodeGen/RISCV/zfhmin-half-intrinsics-strict.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+zfhmin \
 ; RUN:   -verify-machineinstrs -target-abi ilp32f -disable-strictnode-mutation \
 ; RUN:   | FileCheck -check-prefix=RV32IZFHMIN %s
 ; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+zfhmin \
 ; RUN:   -verify-machineinstrs -target-abi lp64f -disable-strictnode-mutation \
 ; RUN:   | FileCheck -check-prefix=RV64IZFHMIN %s
 ; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+d \
 ; RUN:   -mattr=+zfhmin -verify-machineinstrs -target-abi ilp32d \
 ; RUN:   -disable-strictnode-mutation | FileCheck -check-prefix=RV32IZFHMIN %s
 ; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+d \
 ; RUN:   -mattr=+zfhmin -verify-machineinstrs -target-abi lp64d \
 ; RUN:   -disable-strictnode-mutation | FileCheck -check-prefix=RV64IZFHMIN %s
+; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+zhinxmin \
+; RUN:   -verify-machineinstrs -target-abi ilp32 -disable-strictnode-mutation \
+; RUN:   | FileCheck -check-prefix=RV32IZHINXMIN-STRICT %s
+; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+zhinxmin \
+; RUN:   -verify-machineinstrs -target-abi lp64 -disable-strictnode-mutation \
+; RUN:   | FileCheck -check-prefix=RV64IZHINXMIN-STRICT %s
+; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+zdinx \
+; RUN:   -mattr=+zhinxmin -verify-machineinstrs -target-abi ilp32 | \
+; RUN:   FileCheck -check-prefix=RV32IZDINXZHINXMIN %s
+; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+zdinx \
+; RUN:   -mattr=+zhinxmin -verify-machineinstrs -target-abi lp64 | \
+; RUN:   FileCheck -check-prefix=RV64IZDINXZHINXMIN %s
 
 declare half @llvm.experimental.constrained.sqrt.f16(half, metadata, metadata)
 
 define half @sqrt_f16(half %a) nounwind strictfp {
 ; RV32IZFHMIN-LABEL: sqrt_f16:
 ; RV32IZFHMIN:       # %bb.0:
 ; RV32IZFHMIN-NEXT:    fcvt.s.h fa5, fa0
 ; RV32IZFHMIN-NEXT:    fsqrt.s fa5, fa5
 ; RV32IZFHMIN-NEXT:    fcvt.h.s fa0, fa5
 ; RV32IZFHMIN-NEXT:    ret
 ;
 ; RV64IZFHMIN-LABEL: sqrt_f16:
 ; RV64IZFHMIN:       # %bb.0:
 ; RV64IZFHMIN-NEXT:    fcvt.s.h fa5, fa0
 ; RV64IZFHMIN-NEXT:    fsqrt.s fa5, fa5
 ; RV64IZFHMIN-NEXT:    fcvt.h.s fa0, fa5
 ; RV64IZFHMIN-NEXT:    ret
+;
+; RV32IZHINXMIN-STRICT-LABEL: sqrt_f16:
+; RV32IZHINXMIN-STRICT:       # %bb.0:
+; RV32IZHINXMIN-STRICT-NEXT:    fcvt.s.h a0, a0
+; RV32IZHINXMIN-STRICT-NEXT:    fsqrt.s a0, a0
+; RV32IZHINXMIN-STRICT-NEXT:    fcvt.h.s a0, a0
+; RV32IZHINXMIN-STRICT-NEXT:    ret
+;
+; RV64IZHINXMIN-STRICT-LABEL: sqrt_f16:
+; RV64IZHINXMIN-STRICT:       # %bb.0:
+; RV64IZHINXMIN-STRICT-NEXT:    fcvt.s.h a0, a0
+; RV64IZHINXMIN-STRICT-NEXT:    fsqrt.s a0, a0
+; RV64IZHINXMIN-STRICT-NEXT:    fcvt.h.s a0, a0
+; RV64IZHINXMIN-STRICT-NEXT:    ret
+;
+; RV32IZDINXZHINXMIN-LABEL: sqrt_f16:
+; RV32IZDINXZHINXMIN:       # %bb.0:
+; RV32IZDINXZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV32IZDINXZHINXMIN-NEXT:    fsqrt.s a0, a0
+; RV32IZDINXZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; RV32IZDINXZHINXMIN-NEXT:    ret
+;
+; RV64IZDINXZHINXMIN-LABEL: sqrt_f16:
+; RV64IZDINXZHINXMIN:       # %bb.0:
+; RV64IZDINXZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV64IZDINXZHINXMIN-NEXT:    fsqrt.s a0, a0
+; RV64IZDINXZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; RV64IZDINXZHINXMIN-NEXT:    ret
   %1 = call half @llvm.experimental.constrained.sqrt.f16(half %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
   ret half %1
 }
 
 declare half @llvm.experimental.constrained.floor.f16(half, metadata)
 
 define half @floor_f16(half %a) nounwind strictfp {
 ; RV32IZFHMIN-LABEL: floor_f16:

 ; RV64IZFHMIN-NEXT:    addi sp, sp, -16
 ; RV64IZFHMIN-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64IZFHMIN-NEXT:    fcvt.s.h fa0, fa0
 ; RV64IZFHMIN-NEXT:    call floorf@plt
 ; RV64IZFHMIN-NEXT:    fcvt.h.s fa0, fa0
 ; RV64IZFHMIN-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64IZFHMIN-NEXT:    addi sp, sp, 16
 ; RV64IZFHMIN-NEXT:    ret
+;
+; RV32IZHINXMIN-STRICT-LABEL: floor_f16:
+; RV32IZHINXMIN-STRICT:       # %bb.0:
+; RV32IZHINXMIN-STRICT-NEXT:    addi sp, sp, -16
+; RV32IZHINXMIN-STRICT-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZHINXMIN-STRICT-NEXT:    fcvt.s.h a0, a0
+; RV32IZHINXMIN-STRICT-NEXT:    call floorf@plt
+; RV32IZHINXMIN-STRICT-NEXT:    fcvt.h.s a0, a0
+; RV32IZHINXMIN-STRICT-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZHINXMIN-STRICT-NEXT:    addi sp, sp, 16
+; RV32IZHINXMIN-STRICT-NEXT:    ret
+;
+; RV64IZHINXMIN-STRICT-LABEL: floor_f16:
+; RV64IZHINXMIN-STRICT:       # %bb.0:
+; RV64IZHINXMIN-STRICT-NEXT:    addi sp, sp, -16
+; RV64IZHINXMIN-STRICT-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IZHINXMIN-STRICT-NEXT:    fcvt.s.h a0, a0
+; RV64IZHINXMIN-STRICT-NEXT:    call floorf@plt
+; RV64IZHINXMIN-STRICT-NEXT:    fcvt.h.s a0, a0
+; RV64IZHINXMIN-STRICT-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
+; RV64IZHINXMIN-STRICT-NEXT:    addi sp, sp, 16
+; RV64IZHINXMIN-STRICT-NEXT:    ret
+;
+; RV32IZDINXZHINXMIN-LABEL: floor_f16:
+; RV32IZDINXZHINXMIN:       # %bb.0:
+; RV32IZDINXZHINXMIN-NEXT:    addi sp, sp, -16
+; RV32IZDINXZHINXMIN-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZDINXZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV32IZDINXZHINXMIN-NEXT:    call floorf@plt
+; RV32IZDINXZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; RV32IZDINXZHINXMIN-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZDINXZHINXMIN-NEXT:    addi sp, sp, 16
+; RV32IZDINXZHINXMIN-NEXT:    ret
+;
+; RV64IZDINXZHINXMIN-LABEL: floor_f16:
+; RV64IZDINXZHINXMIN:       # %bb.0:
+; RV64IZDINXZHINXMIN-NEXT:    addi sp, sp, -16
+; RV64IZDINXZHINXMIN-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IZDINXZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV64IZDINXZHINXMIN-NEXT:    call floorf@plt
+; RV64IZDINXZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; RV64IZDINXZHINXMIN-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
+; RV64IZDINXZHINXMIN-NEXT:    addi sp, sp, 16
+; RV64IZDINXZHINXMIN-NEXT:    ret
   %1 = call half @llvm.experimental.constrained.floor.f16(half %a, metadata !"fpexcept.strict") strictfp
   ret half %1
 }
 
 declare half @llvm.experimental.constrained.ceil.f16(half, metadata)
 
 define half @ceil_f16(half %a) nounwind strictfp {
 ; RV32IZFHMIN-LABEL: ceil_f16:

 ; RV64IZFHMIN-NEXT:    addi sp, sp, -16
 ; RV64IZFHMIN-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64IZFHMIN-NEXT:    fcvt.s.h fa0, fa0
 ; RV64IZFHMIN-NEXT:    call ceilf@plt
 ; RV64IZFHMIN-NEXT:    fcvt.h.s fa0, fa0
 ; RV64IZFHMIN-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64IZFHMIN-NEXT:    addi sp, sp, 16
 ; RV64IZFHMIN-NEXT:    ret
+;
+; RV32IZHINXMIN-STRICT-LABEL: ceil_f16:
+; RV32IZHINXMIN-STRICT:       # %bb.0:
+; RV32IZHINXMIN-STRICT-NEXT:    addi sp, sp, -16
+; RV32IZHINXMIN-STRICT-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZHINXMIN-STRICT-NEXT:    fcvt.s.h a0, a0
+; RV32IZHINXMIN-STRICT-NEXT:    call ceilf@plt
+; RV32IZHINXMIN-STRICT-NEXT:    fcvt.h.s a0, a0
+; RV32IZHINXMIN-STRICT-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZHINXMIN-STRICT-NEXT:    addi sp, sp, 16
+; RV32IZHINXMIN-STRICT-NEXT:    ret
+;
+; RV64IZHINXMIN-STRICT-LABEL: ceil_f16:
+; RV64IZHINXMIN-STRICT:       # %bb.0:
+; RV64IZHINXMIN-STRICT-NEXT:    addi sp, sp, -16
+; RV64IZHINXMIN-STRICT-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IZHINXMIN-STRICT-NEXT:    fcvt.s.h a0, a0
+; RV64IZHINXMIN-STRICT-NEXT:    call ceilf@plt
+; RV64IZHINXMIN-STRICT-NEXT:    fcvt.h.s a0, a0
+; RV64IZHINXMIN-STRICT-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
+; RV64IZHINXMIN-STRICT-NEXT:    addi sp, sp, 16
+; RV64IZHINXMIN-STRICT-NEXT:    ret
+;
+; RV32IZDINXZHINXMIN-LABEL: ceil_f16:
+; RV32IZDINXZHINXMIN:       # %bb.0:
+; RV32IZDINXZHINXMIN-NEXT:    addi sp, sp, -16
+; RV32IZDINXZHINXMIN-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZDINXZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV32IZDINXZHINXMIN-NEXT:    call ceilf@plt
+; RV32IZDINXZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; RV32IZDINXZHINXMIN-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZDINXZHINXMIN-NEXT:    addi sp, sp, 16
+; RV32IZDINXZHINXMIN-NEXT:    ret
+;
+; RV64IZDINXZHINXMIN-LABEL: ceil_f16:
+; RV64IZDINXZHINXMIN:       # %bb.0:
+; RV64IZDINXZHINXMIN-NEXT:    addi sp, sp, -16
+; RV64IZDINXZHINXMIN-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IZDINXZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV64IZDINXZHINXMIN-NEXT:    call ceilf@plt
+; RV64IZDINXZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; RV64IZDINXZHINXMIN-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
+; RV64IZDINXZHINXMIN-NEXT:    addi sp, sp, 16
+; RV64IZDINXZHINXMIN-NEXT:    ret
   %1 = call half @llvm.experimental.constrained.ceil.f16(half %a, metadata !"fpexcept.strict") strictfp
   ret half %1
 }
 
 declare half @llvm.experimental.constrained.trunc.f16(half, metadata)
 
 define half @trunc_f16(half %a) nounwind strictfp {
 ; RV32IZFHMIN-LABEL: trunc_f16:

 ; RV64IZFHMIN-NEXT:    addi sp, sp, -16
 ; RV64IZFHMIN-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64IZFHMIN-NEXT:    fcvt.s.h fa0, fa0
 ; RV64IZFHMIN-NEXT:    call truncf@plt
 ; RV64IZFHMIN-NEXT:    fcvt.h.s fa0, fa0
 ; RV64IZFHMIN-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64IZFHMIN-NEXT:    addi sp, sp, 16
 ; RV64IZFHMIN-NEXT:    ret
+;
+; RV32IZHINXMIN-STRICT-LABEL: trunc_f16:
+; RV32IZHINXMIN-STRICT:       # %bb.0:
+; RV32IZHINXMIN-STRICT-NEXT:    addi sp, sp, -16
+; RV32IZHINXMIN-STRICT-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZHINXMIN-STRICT-NEXT:    fcvt.s.h a0, a0
+; RV32IZHINXMIN-STRICT-NEXT:    call truncf@plt
+; RV32IZHINXMIN-STRICT-NEXT:    fcvt.h.s a0, a0
+; RV32IZHINXMIN-STRICT-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZHINXMIN-STRICT-NEXT:    addi sp, sp, 16
+; RV32IZHINXMIN-STRICT-NEXT:    ret
+;
+; RV64IZHINXMIN-STRICT-LABEL: trunc_f16:
+; RV64IZHINXMIN-STRICT:       # %bb.0:
+; RV64IZHINXMIN-STRICT-NEXT:    addi sp, sp, -16
+; RV64IZHINXMIN-STRICT-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IZHINXMIN-STRICT-NEXT:    fcvt.s.h a0, a0
+; RV64IZHINXMIN-STRICT-NEXT:    call truncf@plt
+; RV64IZHINXMIN-STRICT-NEXT:    fcvt.h.s a0, a0
+; RV64IZHINXMIN-STRICT-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
+; RV64IZHINXMIN-STRICT-NEXT:    addi sp, sp, 16
+; RV64IZHINXMIN-STRICT-NEXT:    ret
+;
+; RV32IZDINXZHINXMIN-LABEL: trunc_f16:
+; RV32IZDINXZHINXMIN:       # %bb.0:
+; RV32IZDINXZHINXMIN-NEXT:    addi sp, sp, -16
+; RV32IZDINXZHINXMIN-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZDINXZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV32IZDINXZHINXMIN-NEXT:    call truncf@plt
+; RV32IZDINXZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; RV32IZDINXZHINXMIN-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZDINXZHINXMIN-NEXT:    addi sp, sp, 16
+; RV32IZDINXZHINXMIN-NEXT:    ret
+;
+; RV64IZDINXZHINXMIN-LABEL: trunc_f16:
+; RV64IZDINXZHINXMIN:       # %bb.0:
+; RV64IZDINXZHINXMIN-NEXT:    addi sp, sp, -16
+; RV64IZDINXZHINXMIN-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IZDINXZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV64IZDINXZHINXMIN-NEXT:    call truncf@plt
+; RV64IZDINXZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; RV64IZDINXZHINXMIN-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
+; RV64IZDINXZHINXMIN-NEXT:    addi sp, sp, 16
+; RV64IZDINXZHINXMIN-NEXT:    ret
   %1 = call half @llvm.experimental.constrained.trunc.f16(half %a, metadata !"fpexcept.strict") strictfp
   ret half %1
 }
 
 declare half @llvm.experimental.constrained.rint.f16(half, metadata, metadata)
 
 define half @rint_f16(half %a) nounwind strictfp {
 ; RV32IZFHMIN-LABEL: rint_f16:

 ; RV64IZFHMIN-NEXT:    addi sp, sp, -16
 ; RV64IZFHMIN-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64IZFHMIN-NEXT:    fcvt.s.h fa0, fa0
 ; RV64IZFHMIN-NEXT:    call rintf@plt
 ; RV64IZFHMIN-NEXT:    fcvt.h.s fa0, fa0
 ; RV64IZFHMIN-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64IZFHMIN-NEXT:    addi sp, sp, 16
 ; RV64IZFHMIN-NEXT:    ret
+;
+; RV32IZHINXMIN-STRICT-LABEL: rint_f16:
+; RV32IZHINXMIN-STRICT:       # %bb.0:
+; RV32IZHINXMIN-STRICT-NEXT:    addi sp, sp, -16
+; RV32IZHINXMIN-STRICT-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZHINXMIN-STRICT-NEXT:    fcvt.s.h a0, a0
+; RV32IZHINXMIN-STRICT-NEXT:    call rintf@plt
+; RV32IZHINXMIN-STRICT-NEXT:    fcvt.h.s a0, a0
+; RV32IZHINXMIN-STRICT-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZHINXMIN-STRICT-NEXT:    addi sp, sp, 16
+; RV32IZHINXMIN-STRICT-NEXT:    ret
+;
+; RV64IZHINXMIN-STRICT-LABEL: rint_f16:
+; RV64IZHINXMIN-STRICT:       # %bb.0:
+; RV64IZHINXMIN-STRICT-NEXT:    addi sp, sp, -16
+; RV64IZHINXMIN-STRICT-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IZHINXMIN-STRICT-NEXT:    fcvt.s.h a0, a0
+; RV64IZHINXMIN-STRICT-NEXT:    call rintf@plt
+; RV64IZHINXMIN-STRICT-NEXT:    fcvt.h.s a0, a0
+; RV64IZHINXMIN-STRICT-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
+; RV64IZHINXMIN-STRICT-NEXT:    addi sp, sp, 16
+; RV64IZHINXMIN-STRICT-NEXT:    ret
+;
+; RV32IZDINXZHINXMIN-LABEL: rint_f16:
+; RV32IZDINXZHINXMIN:       # %bb.0:
+; RV32IZDINXZHINXMIN-NEXT:    addi sp, sp, -16
+; RV32IZDINXZHINXMIN-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZDINXZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV32IZDINXZHINXMIN-NEXT:    call rintf@plt
+; RV32IZDINXZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; RV32IZDINXZHINXMIN-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZDINXZHINXMIN-NEXT:    addi sp, sp, 16
+; RV32IZDINXZHINXMIN-NEXT:    ret
+;
+; RV64IZDINXZHINXMIN-LABEL: rint_f16:
+; RV64IZDINXZHINXMIN:       # %bb.0:
+; RV64IZDINXZHINXMIN-NEXT:    addi sp, sp, -16
+; RV64IZDINXZHINXMIN-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IZDINXZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV64IZDINXZHINXMIN-NEXT:    call rintf@plt
+; RV64IZDINXZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; RV64IZDINXZHINXMIN-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
+; RV64IZDINXZHINXMIN-NEXT:    addi sp, sp, 16
+; RV64IZDINXZHINXMIN-NEXT:    ret
   %1 = call half @llvm.experimental.constrained.rint.f16(half %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
   ret half %1
 }
 
 declare half @llvm.experimental.constrained.nearbyint.f16(half, metadata, metadata)
 
 define half @nearbyint_f16(half %a) nounwind strictfp {
 ; RV32IZFHMIN-LABEL: nearbyint_f16:

 ; RV64IZFHMIN-NEXT:    addi sp, sp, -16
 ; RV64IZFHMIN-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64IZFHMIN-NEXT:    fcvt.s.h fa0, fa0
 ; RV64IZFHMIN-NEXT:    call nearbyintf@plt
 ; RV64IZFHMIN-NEXT:    fcvt.h.s fa0, fa0
 ; RV64IZFHMIN-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64IZFHMIN-NEXT:    addi sp, sp, 16
 ; RV64IZFHMIN-NEXT:    ret
+;
+; RV32IZHINXMIN-STRICT-LABEL: nearbyint_f16:
+; RV32IZHINXMIN-STRICT:       # %bb.0:
+; RV32IZHINXMIN-STRICT-NEXT:    addi sp, sp, -16
+; RV32IZHINXMIN-STRICT-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZHINXMIN-STRICT-NEXT:    fcvt.s.h a0, a0
+; RV32IZHINXMIN-STRICT-NEXT:    call nearbyintf@plt
+; RV32IZHINXMIN-STRICT-NEXT:    fcvt.h.s a0, a0
+; RV32IZHINXMIN-STRICT-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZHINXMIN-STRICT-NEXT:    addi sp, sp, 16
+; RV32IZHINXMIN-STRICT-NEXT:    ret
+;
+; RV64IZHINXMIN-STRICT-LABEL: nearbyint_f16:
+; RV64IZHINXMIN-STRICT:       # %bb.0:
+; RV64IZHINXMIN-STRICT-NEXT:    addi sp, sp, -16
+; RV64IZHINXMIN-STRICT-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IZHINXMIN-STRICT-NEXT:    fcvt.s.h a0, a0
+; RV64IZHINXMIN-STRICT-NEXT:    call nearbyintf@plt
+; RV64IZHINXMIN-STRICT-NEXT:    fcvt.h.s a0, a0
+; RV64IZHINXMIN-STRICT-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
+; RV64IZHINXMIN-STRICT-NEXT:    addi sp, sp, 16
+; RV64IZHINXMIN-STRICT-NEXT:    ret
+;
+; RV32IZDINXZHINXMIN-LABEL: nearbyint_f16:
+; RV32IZDINXZHINXMIN:       # %bb.0:
+; RV32IZDINXZHINXMIN-NEXT:    addi sp, sp, -16
+; RV32IZDINXZHINXMIN-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZDINXZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV32IZDINXZHINXMIN-NEXT:    call nearbyintf@plt
+; RV32IZDINXZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; RV32IZDINXZHINXMIN-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZDINXZHINXMIN-NEXT:    addi sp, sp, 16
+; RV32IZDINXZHINXMIN-NEXT:    ret
+;
+; RV64IZDINXZHINXMIN-LABEL: nearbyint_f16:
+; RV64IZDINXZHINXMIN:       # %bb.0:
+; RV64IZDINXZHINXMIN-NEXT:    addi sp, sp, -16
+; RV64IZDINXZHINXMIN-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IZDINXZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV64IZDINXZHINXMIN-NEXT:    call nearbyintf@plt
+; RV64IZDINXZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; RV64IZDINXZHINXMIN-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
+; RV64IZDINXZHINXMIN-NEXT:    addi sp, sp, 16
+; RV64IZDINXZHINXMIN-NEXT:    ret
   %1 = call half @llvm.experimental.constrained.nearbyint.f16(half %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
   ret half %1
 }
 
 declare half @llvm.experimental.constrained.round.f16(half, metadata)
 
 define half @round_f16(half %a) nounwind strictfp {
 ; RV32IZFHMIN-LABEL: round_f16:

 ; RV64IZFHMIN-NEXT:    addi sp, sp, -16
 ; RV64IZFHMIN-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64IZFHMIN-NEXT:    fcvt.s.h fa0, fa0
 ; RV64IZFHMIN-NEXT:    call roundf@plt
 ; RV64IZFHMIN-NEXT:    fcvt.h.s fa0, fa0
 ; RV64IZFHMIN-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64IZFHMIN-NEXT:    addi sp, sp, 16
 ; RV64IZFHMIN-NEXT:    ret
+;
+; RV32IZHINXMIN-STRICT-LABEL: round_f16:
+; RV32IZHINXMIN-STRICT:       # %bb.0:
+; RV32IZHINXMIN-STRICT-NEXT:    addi sp, sp, -16
+; RV32IZHINXMIN-STRICT-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZHINXMIN-STRICT-NEXT:    fcvt.s.h a0, a0
+; RV32IZHINXMIN-STRICT-NEXT:    call roundf@plt
+; RV32IZHINXMIN-STRICT-NEXT:    fcvt.h.s a0, a0
+; RV32IZHINXMIN-STRICT-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZHINXMIN-STRICT-NEXT:    addi sp, sp, 16
+; RV32IZHINXMIN-STRICT-NEXT:    ret
+;
+; RV64IZHINXMIN-STRICT-LABEL: round_f16:
+; RV64IZHINXMIN-STRICT:       # %bb.0:
+; RV64IZHINXMIN-STRICT-NEXT:    addi sp, sp, -16
+; RV64IZHINXMIN-STRICT-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IZHINXMIN-STRICT-NEXT:    fcvt.s.h a0, a0
+; RV64IZHINXMIN-STRICT-NEXT:    call roundf@plt
+; RV64IZHINXMIN-STRICT-NEXT:    fcvt.h.s a0, a0
+; RV64IZHINXMIN-STRICT-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
+; RV64IZHINXMIN-STRICT-NEXT:    addi sp, sp, 16
+; RV64IZHINXMIN-STRICT-NEXT:    ret
+;
+; RV32IZDINXZHINXMIN-LABEL: round_f16:
+; RV32IZDINXZHINXMIN:       # %bb.0:
+; RV32IZDINXZHINXMIN-NEXT:    addi sp, sp, -16
+; RV32IZDINXZHINXMIN-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZDINXZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV32IZDINXZHINXMIN-NEXT:    call roundf@plt
+; RV32IZDINXZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; RV32IZDINXZHINXMIN-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZDINXZHINXMIN-NEXT:    addi sp, sp, 16
+; RV32IZDINXZHINXMIN-NEXT:    ret
+;
+; RV64IZDINXZHINXMIN-LABEL: round_f16:
+; RV64IZDINXZHINXMIN:       # %bb.0:
+; RV64IZDINXZHINXMIN-NEXT:    addi sp, sp, -16
+; RV64IZDINXZHINXMIN-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IZDINXZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV64IZDINXZHINXMIN-NEXT:    call roundf@plt
+; RV64IZDINXZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; RV64IZDINXZHINXMIN-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
+; RV64IZDINXZHINXMIN-NEXT:    addi sp, sp, 16
+; RV64IZDINXZHINXMIN-NEXT:    ret
   %1 = call half @llvm.experimental.constrained.round.f16(half %a, metadata !"fpexcept.strict") strictfp
   ret half %1
 }
 
 declare half @llvm.experimental.constrained.roundeven.f16(half, metadata)
 
 define half @roundeven_f16(half %a) nounwind strictfp {
 ; RV32IZFHMIN-LABEL: roundeven_f16:

 ; RV64IZFHMIN-NEXT:    addi sp, sp, -16
 ; RV64IZFHMIN-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
 ; RV64IZFHMIN-NEXT:    fcvt.s.h fa0, fa0
 ; RV64IZFHMIN-NEXT:    call roundevenf@plt
 ; RV64IZFHMIN-NEXT:    fcvt.h.s fa0, fa0
 ; RV64IZFHMIN-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
 ; RV64IZFHMIN-NEXT:    addi sp, sp, 16
 ; RV64IZFHMIN-NEXT:    ret
+;
+; RV32IZHINXMIN-STRICT-LABEL: roundeven_f16:
+; RV32IZHINXMIN-STRICT:       # %bb.0:
+; RV32IZHINXMIN-STRICT-NEXT:    addi sp, sp, -16
+; RV32IZHINXMIN-STRICT-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZHINXMIN-STRICT-NEXT:    fcvt.s.h a0, a0
+; RV32IZHINXMIN-STRICT-NEXT:    call roundevenf@plt
+; RV32IZHINXMIN-STRICT-NEXT:    fcvt.h.s a0, a0
+; RV32IZHINXMIN-STRICT-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZHINXMIN-STRICT-NEXT:    addi sp, sp, 16
+; RV32IZHINXMIN-STRICT-NEXT:    ret
+;
+; RV64IZHINXMIN-STRICT-LABEL: roundeven_f16:
+; RV64IZHINXMIN-STRICT:       # %bb.0:
+; RV64IZHINXMIN-STRICT-NEXT:    addi sp, sp, -16
+; RV64IZHINXMIN-STRICT-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IZHINXMIN-STRICT-NEXT:    fcvt.s.h a0, a0
+; RV64IZHINXMIN-STRICT-NEXT:    call roundevenf@plt
+; RV64IZHINXMIN-STRICT-NEXT:    fcvt.h.s a0, a0
+; RV64IZHINXMIN-STRICT-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
+; RV64IZHINXMIN-STRICT-NEXT:    addi sp, sp, 16
+; RV64IZHINXMIN-STRICT-NEXT:    ret
+;
+; RV32IZDINXZHINXMIN-LABEL: roundeven_f16:
+; RV32IZDINXZHINXMIN:       # %bb.0:
+; RV32IZDINXZHINXMIN-NEXT:    addi sp, sp, -16
+; RV32IZDINXZHINXMIN-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZDINXZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV32IZDINXZHINXMIN-NEXT:    call roundevenf@plt
+; RV32IZDINXZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; RV32IZDINXZHINXMIN-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZDINXZHINXMIN-NEXT:    addi sp, sp, 16
+; RV32IZDINXZHINXMIN-NEXT:    ret
+;
+; RV64IZDINXZHINXMIN-LABEL: roundeven_f16:
+; RV64IZDINXZHINXMIN:       # %bb.0:
+; RV64IZDINXZHINXMIN-NEXT:    addi sp, sp, -16
+; RV64IZDINXZHINXMIN-NEXT:    sd ra, 8(sp) # 8-byte Folded Spill
+; RV64IZDINXZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV64IZDINXZHINXMIN-NEXT:    call roundevenf@plt
+; RV64IZDINXZHINXMIN-NEXT:    fcvt.h.s a0, a0
+; RV64IZDINXZHINXMIN-NEXT:    ld ra, 8(sp) # 8-byte Folded Reload
+; RV64IZDINXZHINXMIN-NEXT:    addi sp, sp, 16
+; RV64IZDINXZHINXMIN-NEXT:    ret
   %1 = call half @llvm.experimental.constrained.roundeven.f16(half %a, metadata !"fpexcept.strict") strictfp
   ret half %1
 }
 
 declare iXLen @llvm.experimental.constrained.lrint.iXLen.f16(half, metadata, metadata)
 
 define iXLen @lrint_f16(half %a) nounwind strictfp {
 ; RV32IZFHMIN-LABEL: lrint_f16:
 ; RV32IZFHMIN:       # %bb.0:
 ; RV32IZFHMIN-NEXT:    fcvt.s.h fa5, fa0
 ; RV32IZFHMIN-NEXT:    fcvt.w.s a0, fa5
 ; RV32IZFHMIN-NEXT:    ret
 ;
 ; RV64IZFHMIN-LABEL: lrint_f16:
 ; RV64IZFHMIN:       # %bb.0:
 ; RV64IZFHMIN-NEXT:    fcvt.s.h fa5, fa0
 ; RV64IZFHMIN-NEXT:    fcvt.l.s a0, fa5
 ; RV64IZFHMIN-NEXT:    ret
+;
+; RV32IZHINXMIN-STRICT-LABEL: lrint_f16:
+; RV32IZHINXMIN-STRICT:       # %bb.0:
+; RV32IZHINXMIN-STRICT-NEXT:    fcvt.s.h a0, a0
+; RV32IZHINXMIN-STRICT-NEXT:    fcvt.w.s a0, a0
+; RV32IZHINXMIN-STRICT-NEXT:    ret
+;
+; RV64IZHINXMIN-STRICT-LABEL: lrint_f16:
+; RV64IZHINXMIN-STRICT:       # %bb.0:
+; RV64IZHINXMIN-STRICT-NEXT:    fcvt.s.h a0, a0
+; RV64IZHINXMIN-STRICT-NEXT:    fcvt.l.s a0, a0
+; RV64IZHINXMIN-STRICT-NEXT:    ret
+;
+; RV32IZDINXZHINXMIN-LABEL: lrint_f16:
+; RV32IZDINXZHINXMIN:       # %bb.0:
+; RV32IZDINXZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV32IZDINXZHINXMIN-NEXT:    fcvt.w.s a0, a0
+; RV32IZDINXZHINXMIN-NEXT:    ret
+;
+; RV64IZDINXZHINXMIN-LABEL: lrint_f16:
+; RV64IZDINXZHINXMIN:       # %bb.0:
+; RV64IZDINXZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV64IZDINXZHINXMIN-NEXT:    fcvt.l.s a0, a0
+; RV64IZDINXZHINXMIN-NEXT:    ret
   %1 = call iXLen @llvm.experimental.constrained.lrint.iXLen.f16(half %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
   ret iXLen %1
 }
 
 declare iXLen @llvm.experimental.constrained.lround.iXLen.f16(half, metadata)
 
 define iXLen @lround_f16(half %a) nounwind strictfp {
 ; RV32IZFHMIN-LABEL: lround_f16:
 ; RV32IZFHMIN:       # %bb.0:
 ; RV32IZFHMIN-NEXT:    fcvt.s.h fa5, fa0
 ; RV32IZFHMIN-NEXT:    fcvt.w.s a0, fa5, rmm
 ; RV32IZFHMIN-NEXT:    ret
 ;
 ; RV64IZFHMIN-LABEL: lround_f16:
 ; RV64IZFHMIN:       # %bb.0:
 ; RV64IZFHMIN-NEXT:    fcvt.s.h fa5, fa0
 ; RV64IZFHMIN-NEXT:    fcvt.l.s a0, fa5, rmm
 ; RV64IZFHMIN-NEXT:    ret
+;
+; RV32IZHINXMIN-STRICT-LABEL: lround_f16:
+; RV32IZHINXMIN-STRICT:       # %bb.0:
+; RV32IZHINXMIN-STRICT-NEXT:    fcvt.s.h a0, a0
+; RV32IZHINXMIN-STRICT-NEXT:    fcvt.w.s a0, a0, rmm
+; RV32IZHINXMIN-STRICT-NEXT:    ret
+;
+; RV64IZHINXMIN-STRICT-LABEL: lround_f16:
+; RV64IZHINXMIN-STRICT:       # %bb.0:
+; RV64IZHINXMIN-STRICT-NEXT:    fcvt.s.h a0, a0
+; RV64IZHINXMIN-STRICT-NEXT:    fcvt.l.s a0, a0, rmm
+; RV64IZHINXMIN-STRICT-NEXT:    ret
+;
+; RV32IZDINXZHINXMIN-LABEL: lround_f16:
+; RV32IZDINXZHINXMIN:       # %bb.0:
+; RV32IZDINXZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV32IZDINXZHINXMIN-NEXT:    fcvt.w.s a0, a0, rmm
+; RV32IZDINXZHINXMIN-NEXT:    ret
+;
+; RV64IZDINXZHINXMIN-LABEL: lround_f16:
+; RV64IZDINXZHINXMIN:       # %bb.0:
+; RV64IZDINXZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV64IZDINXZHINXMIN-NEXT:    fcvt.l.s a0, a0, rmm
+; RV64IZDINXZHINXMIN-NEXT:    ret
   %1 = call iXLen @llvm.experimental.constrained.lround.iXLen.f16(half %a, metadata !"fpexcept.strict") strictfp
   ret iXLen %1
 }
 
 declare i64 @llvm.experimental.constrained.llrint.i64.f16(half, metadata, metadata)
 
 define i64 @llrint_f16(half %a) nounwind strictfp {
 ; RV32IZFHMIN-LABEL: llrint_f16:
 ; RV32IZFHMIN:       # %bb.0:
 ; RV32IZFHMIN-NEXT:    addi sp, sp, -16
 ; RV32IZFHMIN-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32IZFHMIN-NEXT:    fcvt.s.h fa0, fa0
 ; RV32IZFHMIN-NEXT:    call llrintf@plt
 ; RV32IZFHMIN-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32IZFHMIN-NEXT:    addi sp, sp, 16
 ; RV32IZFHMIN-NEXT:    ret
 ;
 ; RV64IZFHMIN-LABEL: llrint_f16:
 ; RV64IZFHMIN:       # %bb.0:
 ; RV64IZFHMIN-NEXT:    fcvt.s.h fa5, fa0
 ; RV64IZFHMIN-NEXT:    fcvt.l.s a0, fa5
 ; RV64IZFHMIN-NEXT:    ret
+;
+; RV32IZHINXMIN-STRICT-LABEL: llrint_f16:
+; RV32IZHINXMIN-STRICT:       # %bb.0:
+; RV32IZHINXMIN-STRICT-NEXT:    addi sp, sp, -16
+; RV32IZHINXMIN-STRICT-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZHINXMIN-STRICT-NEXT:    fcvt.s.h a0, a0
+; RV32IZHINXMIN-STRICT-NEXT:    call llrintf@plt
+; RV32IZHINXMIN-STRICT-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZHINXMIN-STRICT-NEXT:    addi sp, sp, 16
+; RV32IZHINXMIN-STRICT-NEXT:    ret
+;
+; RV64IZHINXMIN-STRICT-LABEL: llrint_f16:
+; RV64IZHINXMIN-STRICT:       # %bb.0:
+; RV64IZHINXMIN-STRICT-NEXT:    fcvt.s.h a0, a0
+; RV64IZHINXMIN-STRICT-NEXT:    fcvt.l.s a0, a0
+; RV64IZHINXMIN-STRICT-NEXT:    ret
+;
+; RV32IZDINXZHINXMIN-LABEL: llrint_f16:
+; RV32IZDINXZHINXMIN:       # %bb.0:
+; RV32IZDINXZHINXMIN-NEXT:    addi sp, sp, -16
+; RV32IZDINXZHINXMIN-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZDINXZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV32IZDINXZHINXMIN-NEXT:    call llrintf@plt
+; RV32IZDINXZHINXMIN-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZDINXZHINXMIN-NEXT:    addi sp, sp, 16
+; RV32IZDINXZHINXMIN-NEXT:    ret
+;
+; RV64IZDINXZHINXMIN-LABEL: llrint_f16:
+; RV64IZDINXZHINXMIN:       # %bb.0:
+; RV64IZDINXZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV64IZDINXZHINXMIN-NEXT:    fcvt.l.s a0, a0
+; RV64IZDINXZHINXMIN-NEXT:    ret
   %1 = call i64 @llvm.experimental.constrained.llrint.i64.f16(half %a, metadata !"round.dynamic", metadata !"fpexcept.strict") strictfp
   ret i64 %1
 }
 
 declare i64 @llvm.experimental.constrained.llround.i64.f16(half, metadata)
 
 define i64 @llround_f16(half %a) nounwind strictfp {
 ; RV32IZFHMIN-LABEL: llround_f16:
 ; RV32IZFHMIN:       # %bb.0:
 ; RV32IZFHMIN-NEXT:    addi sp, sp, -16
 ; RV32IZFHMIN-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
 ; RV32IZFHMIN-NEXT:    fcvt.s.h fa0, fa0
 ; RV32IZFHMIN-NEXT:    call llroundf@plt
 ; RV32IZFHMIN-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
 ; RV32IZFHMIN-NEXT:    addi sp, sp, 16
 ; RV32IZFHMIN-NEXT:    ret
 ;
 ; RV64IZFHMIN-LABEL: llround_f16:
 ; RV64IZFHMIN:       # %bb.0:
 ; RV64IZFHMIN-NEXT:    fcvt.s.h fa5, fa0
 ; RV64IZFHMIN-NEXT:    fcvt.l.s a0, fa5, rmm
 ; RV64IZFHMIN-NEXT:    ret
+;
+; RV32IZHINXMIN-STRICT-LABEL: llround_f16:
+; RV32IZHINXMIN-STRICT:       # %bb.0:
+; RV32IZHINXMIN-STRICT-NEXT:    addi sp, sp, -16
+; RV32IZHINXMIN-STRICT-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZHINXMIN-STRICT-NEXT:    fcvt.s.h a0, a0
+; RV32IZHINXMIN-STRICT-NEXT:    call llroundf@plt
+; RV32IZHINXMIN-STRICT-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZHINXMIN-STRICT-NEXT:    addi sp, sp, 16
+; RV32IZHINXMIN-STRICT-NEXT:    ret
+;
+; RV64IZHINXMIN-STRICT-LABEL: llround_f16:
+; RV64IZHINXMIN-STRICT:       # %bb.0:
+; RV64IZHINXMIN-STRICT-NEXT:    fcvt.s.h a0, a0
+; RV64IZHINXMIN-STRICT-NEXT:    fcvt.l.s a0, a0, rmm
+; RV64IZHINXMIN-STRICT-NEXT:    ret
+;
+; RV32IZDINXZHINXMIN-LABEL: llround_f16:
+; RV32IZDINXZHINXMIN:       # %bb.0:
+; RV32IZDINXZHINXMIN-NEXT:    addi sp, sp, -16
+; RV32IZDINXZHINXMIN-NEXT:    sw ra, 12(sp) # 4-byte Folded Spill
+; RV32IZDINXZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV32IZDINXZHINXMIN-NEXT:    call llroundf@plt
+; RV32IZDINXZHINXMIN-NEXT:    lw ra, 12(sp) # 4-byte Folded Reload
+; RV32IZDINXZHINXMIN-NEXT:    addi sp, sp, 16
+; RV32IZDINXZHINXMIN-NEXT:    ret
+;
+; RV64IZDINXZHINXMIN-LABEL: llround_f16:
+; RV64IZDINXZHINXMIN:       # %bb.0:
+; RV64IZDINXZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV64IZDINXZHINXMIN-NEXT:    fcvt.l.s a0, a0, rmm
+; RV64IZDINXZHINXMIN-NEXT:    ret
   %1 = call i64 @llvm.experimental.constrained.llround.i64.f16(half %a, metadata !"fpexcept.strict") strictfp
   ret i64 %1
 }

llvm/test/CodeGen/RISCV/zfhmin-half-intrinsics.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+zfhmin \
 ; RUN:   -verify-machineinstrs -target-abi ilp32f | \
 ; RUN:   FileCheck -check-prefix=RV32IZFHMIN %s
 ; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+zfhmin \
 ; RUN:   -verify-machineinstrs -target-abi lp64f | \
 ; RUN:   FileCheck -check-prefix=RV64IZFHMIN %s
 ; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+d \
 ; RUN:   -mattr=+zfhmin -verify-machineinstrs -target-abi ilp32d | \
 ; RUN:   FileCheck -check-prefix=RV32IDZFHMIN %s
 ; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+d \
 ; RUN:   -mattr=+zfhmin -verify-machineinstrs -target-abi lp64d | \
 ; RUN:   FileCheck -check-prefix=RV64IDZFHMIN %s
+; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+zhinxmin \
+; RUN:   -verify-machineinstrs -target-abi ilp32 | \
+; RUN:   FileCheck -check-prefix=RV32IZHINXMIN %s
+; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+zhinxmin \
+; RUN:   -verify-machineinstrs -target-abi lp64 | \
+; RUN:   FileCheck -check-prefix=RV64IZHINXMIN %s
+; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+zdinx \
+; RUN:   -mattr=+zhinxmin -verify-machineinstrs -target-abi ilp32 | \
+; RUN:   FileCheck -check-prefix=RV32IZDINXZHINXMIN %s
+; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+zdinx \
+; RUN:   -mattr=+zhinxmin -verify-machineinstrs -target-abi lp64 | \
+; RUN:   FileCheck -check-prefix=RV64IZDINXZHINXMIN %s
 
 ; These intrinsics require half to be a legal type.
 
 declare iXLen @llvm.lrint.iXLen.f16(half)
 
 define iXLen @lrint_f16(half %a) nounwind {
 ; RV32IZFHMIN-LABEL: lrint_f16:
 ; RV32IZFHMIN:       # %bb.0:

 ; RV32IDZFHMIN-NEXT:    fcvt.w.s a0, fa5
 ; RV32IDZFHMIN-NEXT:    ret
 ;
 ; RV64IDZFHMIN-LABEL: lrint_f16:
 ; RV64IDZFHMIN:       # %bb.0:
 ; RV64IDZFHMIN-NEXT:    fcvt.s.h fa5, fa0
 ; RV64IDZFHMIN-NEXT:    fcvt.l.s a0, fa5
 ; RV64IDZFHMIN-NEXT:    ret
+;
+; RV32IZHINXMIN-LABEL: lrint_f16:
+; RV32IZHINXMIN:       # %bb.0:
+; RV32IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV32IZHINXMIN-NEXT:    fcvt.w.s a0, a0
+; RV32IZHINXMIN-NEXT:    ret
+;
+; RV64IZHINXMIN-LABEL: lrint_f16:
+; RV64IZHINXMIN:       # %bb.0:
+; RV64IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV64IZHINXMIN-NEXT:    fcvt.l.s a0, a0
+; RV64IZHINXMIN-NEXT:    ret
+;
+; RV32IZDINXZHINXMIN-LABEL: lrint_f16:
+; RV32IZDINXZHINXMIN:       # %bb.0:
+; RV32IZDINXZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV32IZDINXZHINXMIN-NEXT:    fcvt.w.s a0, a0
+; RV32IZDINXZHINXMIN-NEXT:    ret
+;
+; RV64IZDINXZHINXMIN-LABEL: lrint_f16:
+; RV64IZDINXZHINXMIN:       # %bb.0:
+; RV64IZDINXZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV64IZDINXZHINXMIN-NEXT:    fcvt.l.s a0, a0
+; RV64IZDINXZHINXMIN-NEXT:    ret
   %1 = call iXLen @llvm.lrint.iXLen.f16(half %a)
   ret iXLen %1
 }
 
 declare iXLen @llvm.lround.iXLen.f16(half)
 
 define iXLen @lround_f16(half %a) nounwind {
 ; RV32IZFHMIN-LABEL: lround_f16:

 ; RV32IDZFHMIN-NEXT:    fcvt.w.s a0, fa5, rmm
 ; RV32IDZFHMIN-NEXT:    ret
 ;
 ; RV64IDZFHMIN-LABEL: lround_f16:
 ; RV64IDZFHMIN:       # %bb.0:
 ; RV64IDZFHMIN-NEXT:    fcvt.s.h fa5, fa0
 ; RV64IDZFHMIN-NEXT:    fcvt.l.s a0, fa5, rmm
 ; RV64IDZFHMIN-NEXT:    ret
+;
+; RV32IZHINXMIN-LABEL: lround_f16:
+; RV32IZHINXMIN:       # %bb.0:
+; RV32IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV32IZHINXMIN-NEXT:    fcvt.w.s a0, a0, rmm
+; RV32IZHINXMIN-NEXT:    ret
+;
+; RV64IZHINXMIN-LABEL: lround_f16:
+; RV64IZHINXMIN:       # %bb.0:
+; RV64IZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV64IZHINXMIN-NEXT:    fcvt.l.s a0, a0, rmm
+; RV64IZHINXMIN-NEXT:    ret
+;
+; RV32IZDINXZHINXMIN-LABEL: lround_f16:
+; RV32IZDINXZHINXMIN:       # %bb.0:
+; RV32IZDINXZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV32IZDINXZHINXMIN-NEXT:    fcvt.w.s a0, a0, rmm
+; RV32IZDINXZHINXMIN-NEXT:    ret
+;
+; RV64IZDINXZHINXMIN-LABEL: lround_f16:
+; RV64IZDINXZHINXMIN:       # %bb.0:
+; RV64IZDINXZHINXMIN-NEXT:    fcvt.s.h a0, a0
+; RV64IZDINXZHINXMIN-NEXT:    fcvt.l.s a0, a0, rmm
+; RV64IZDINXZHINXMIN-NEXT:    ret
   %1 = call iXLen @llvm.lround.iXLen.f16(half %a)
   ret iXLen %1
 }

llvm/test/CodeGen/RISCV/zfhmin-imm.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -mtriple=riscv32 -target-abi ilp32f -mattr=+zfhmin < %s \
 ; RUN:     | FileCheck --check-prefix=RV32IZFHMIN %s
 ; RUN: llc -mtriple=riscv32 -target-abi ilp32d -mattr=+zfhmin,+d < %s \
 ; RUN:     | FileCheck --check-prefix=RV32IDZFHMIN %s
+; RUN: llc -mtriple=riscv32 -target-abi ilp32 -mattr=+zhinxmin < %s \
+; RUN:     | FileCheck --check-prefix=RV32IZHINXMIN %s
+; RUN: llc -mtriple=riscv32 -target-abi ilp32 -mattr=+zhinxmin,+zdinx < %s \
+; RUN:     | FileCheck --check-prefix=RV32IZDINXZHINXMIN %s
 ; RUN: llc -mtriple=riscv64 -target-abi lp64f -mattr=+zfhmin < %s \
 ; RUN:     | FileCheck --check-prefix=RV64IZFHMIN %s
 ; RUN: llc -mtriple=riscv64 -target-abi lp64d -mattr=+zfhmin,+d < %s \
 ; RUN:     | FileCheck --check-prefix=RV64IDZFHMIN %s
+; RUN: llc -mtriple=riscv64 -target-abi lp64 -mattr=+zhinxmin < %s \
+; RUN:     | FileCheck --check-prefix=RV64IZHINXMIN %s
+; RUN: llc -mtriple=riscv64 -target-abi lp64 -mattr=+zhinxmin,+zdinx < %s \
+; RUN:     | FileCheck --check-prefix=RV64IZDINXZHINXMIN %s
 
 define half @f16_positive_zero(ptr %pf) nounwind {
 ; RV32IZFHMIN-LABEL: f16_positive_zero:
 ; RV32IZFHMIN:       # %bb.0:
 ; RV32IZFHMIN-NEXT:    fmv.h.x fa0, zero
 ; RV32IZFHMIN-NEXT:    ret
 ;
 ; RV32IDZFHMIN-LABEL: f16_positive_zero:
 ; RV32IDZFHMIN:       # %bb.0:
 ; RV32IDZFHMIN-NEXT:    fmv.h.x fa0, zero
 ; RV32IDZFHMIN-NEXT:    ret
 ;
+; RV32IZHINXMIN-LABEL: f16_positive_zero:
+; RV32IZHINXMIN:       # %bb.0:
+; RV32IZHINXMIN-NEXT:    li a0, 0
+; RV32IZHINXMIN-NEXT:    ret
+;
+; RV32IZDINXZHINXMIN-LABEL: f16_positive_zero:
+; RV32IZDINXZHINXMIN:       # %bb.0:
+; RV32IZDINXZHINXMIN-NEXT:    li a0, 0
+; RV32IZDINXZHINXMIN-NEXT:    ret
+;
 ; RV64IZFHMIN-LABEL: f16_positive_zero:
 ; RV64IZFHMIN:       # %bb.0:
 ; RV64IZFHMIN-NEXT:    fmv.h.x fa0, zero
 ; RV64IZFHMIN-NEXT:    ret
 ;
 ; RV64IDZFHMIN-LABEL: f16_positive_zero:
 ; RV64IDZFHMIN:       # %bb.0:
 ; RV64IDZFHMIN-NEXT:    fmv.h.x fa0, zero
 ; RV64IDZFHMIN-NEXT:    ret
+;
+; RV64IZHINXMIN-LABEL: f16_positive_zero:
+; RV64IZHINXMIN:       # %bb.0:
+; RV64IZHINXMIN-NEXT:    li a0, 0
+; RV64IZHINXMIN-NEXT:    ret
+;
+; RV64IZDINXZHINXMIN-LABEL: f16_positive_zero:
+; RV64IZDINXZHINXMIN:       # %bb.0:
+; RV64IZDINXZHINXMIN-NEXT:    li a0, 0
+; RV64IZDINXZHINXMIN-NEXT:    ret
   ret half 0.0
 }
 
 define half @f16_negative_zero(ptr %pf) nounwind {
 ; RV32IZFHMIN-LABEL: f16_negative_zero:
 ; RV32IZFHMIN:       # %bb.0:
 ; RV32IZFHMIN-NEXT:    lui a0, 1048568
 ; RV32IZFHMIN-NEXT:    fmv.h.x fa0, a0
 ; RV32IZFHMIN-NEXT:    ret
 ;
 ; RV32IDZFHMIN-LABEL: f16_negative_zero:
 ; RV32IDZFHMIN:       # %bb.0:
 ; RV32IDZFHMIN-NEXT:    lui a0, 1048568
 ; RV32IDZFHMIN-NEXT:    fmv.h.x fa0, a0
 ; RV32IDZFHMIN-NEXT:    ret
 ;
+; RV32IZHINXMIN-LABEL: f16_negative_zero:
+; RV32IZHINXMIN:       # %bb.0:
+; RV32IZHINXMIN-NEXT:    lui a0, 1048568
+; RV32IZHINXMIN-NEXT:    ret
+;
+; RV32IZDINXZHINXMIN-LABEL: f16_negative_zero:
+; RV32IZDINXZHINXMIN:       # %bb.0:
+; RV32IZDINXZHINXMIN-NEXT:    lui a0, 1048568
+; RV32IZDINXZHINXMIN-NEXT:    ret
+;
 ; RV64IZFHMIN-LABEL: f16_negative_zero:
 ; RV64IZFHMIN:       # %bb.0:
 ; RV64IZFHMIN-NEXT:    lui a0, 1048568
 ; RV64IZFHMIN-NEXT:    fmv.h.x fa0, a0
 ; RV64IZFHMIN-NEXT:    ret
 ;
 ; RV64IDZFHMIN-LABEL: f16_negative_zero:
 ; RV64IDZFHMIN:       # %bb.0:
 ; RV64IDZFHMIN-NEXT:    lui a0, 1048568
 ; RV64IDZFHMIN-NEXT:    fmv.h.x fa0, a0
 ; RV64IDZFHMIN-NEXT:    ret
+;
+; RV64IZHINXMIN-LABEL: f16_negative_zero:
+; RV64IZHINXMIN:       # %bb.0:
+; RV64IZHINXMIN-NEXT:    lui a0, 1048568
+; RV64IZHINXMIN-NEXT:    ret
+;
+; RV64IZDINXZHINXMIN-LABEL: f16_negative_zero:
+; RV64IZDINXZHINXMIN:       # %bb.0:
+; RV64IZDINXZHINXMIN-NEXT:    lui a0, 1048568
+; RV64IZDINXZHINXMIN-NEXT:    ret
   ret half -0.0
 }