[RISCV][RISCV][clang] Split out SiFive VCIX C intrinsics from riscv_vector.td

[4vtomat]

Summary

Since we don't always need the vendor extension to be in riscv_vector.td,
so it's better to make it be in separated header.

Depends on D148223

[kito-cheng]

clang/include/clang/Basic/riscv_vector.td

15

This should be separated NFC patch.

2152

Do that on https://reviews.llvm.org/D148223

clang/lib/Headers/sifive_vector.h

15

sifive_vcix -> sifive_vector since it might not only contain VCIX in future, and also the file named sifive_vector.h

[4vtomat]

Resolved Kito's comments.

[kito-cheng]

LGTM, thanks!

clang/include/clang/Basic/BuiltinsRISCVVector.def

 //
 //===----------------------------------------------------------------------===//
 
 #if defined(BUILTIN) && !defined(TARGET_BUILTIN)
 #   define TARGET_BUILTIN(ID, TYPE, ATTRS, FEATURE) BUILTIN(ID, TYPE, ATTRS)
 #endif
 
 #include "clang/Basic/riscv_vector_builtins.inc"
+#include "clang/Basic/riscv_sifive_vector_builtins.inc"
 
 #undef BUILTIN
 #undef TARGET_BUILTIN

clang/include/clang/Basic/CMakeLists.txt

clang_tablegen(riscv_vector_builtins.inc -gen-riscv-vector-builtins
   SOURCE riscv_vector.td
   TARGET ClangRISCVVectorBuiltins)
 clang_tablegen(riscv_vector_builtin_cg.inc -gen-riscv-vector-builtin-codegen
   SOURCE riscv_vector.td
   TARGET ClangRISCVVectorBuiltinCG)
 clang_tablegen(riscv_vector_builtin_sema.inc -gen-riscv-vector-builtin-sema
   SOURCE riscv_vector.td
   TARGET ClangRISCVVectorBuiltinSema)
+clang_tablegen(riscv_sifive_vector_builtins.inc -gen-riscv-sifive-vector-builtins
+  SOURCE riscv_sifive_vector.td
+  TARGET ClangRISCVSiFiveVectorBuiltins)
+clang_tablegen(riscv_sifive_vector_builtin_cg.inc -gen-riscv-sifive-vector-builtin-codegen
+  SOURCE riscv_sifive_vector.td
+  TARGET ClangRISCVSiFiveVectorBuiltinCG)
+clang_tablegen(riscv_sifive_vector_builtin_sema.inc -gen-riscv-sifive-vector-builtin-sema
+  SOURCE riscv_sifive_vector.td
+  TARGET ClangRISCVSiFiveVectorBuiltinSema)

clang/include/clang/Basic/riscv_sifive_vector.td

 //==--- riscv_sifive_vector.td - RISC-V SiFive VCIX function list ---------===//
 //
 //  Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 //  See https://llvm.org/LICENSE.txt for license information.
 //  SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
 // This file defines the builtins for RISC-V SiFive VCIX. See:
 //
 //     https://sifive.cdn.prismic.io/sifive/c3829e36-8552-41f0-a841-79945784241b_vcix-spec-software.pdf
 //
 //===----------------------------------------------------------------------===//
 
+include "riscv_vector_common.td"
+
 //===----------------------------------------------------------------------===//
 // Instruction definitions
 //===----------------------------------------------------------------------===//
 
 class VCIXSuffix<string range> {
   list<string> suffix = !cond(!eq(range, "c"): ["8mf8", "8mf4", "8mf2", "8m1", "8m2", "8m4", "8m8"],
                               !eq(range, "s"): ["16mf4", "16mf2", "16m1", "16m2", "16m4", "16m8"],
                               !eq(range, "i"): ["32mf2", "32m1", "32m2", "32m4", "32m8"],

clang/include/clang/Basic/riscv_vector.td

 //==--- riscv_vector.td - RISC-V V-ext Builtin function list --------------===//
 //
 //  Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 //  See https://llvm.org/LICENSE.txt for license information.
 //  SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
 // This file defines the builtins for RISC-V V-extension. See:
 //
 //     https://github.com/riscv/rvv-intrinsic-doc
 //
 //===----------------------------------------------------------------------===//
 
 include "riscv_vector_common.td"
 
 //===----------------------------------------------------------------------===//
 // Basic classes with automatic codegen.
 //===----------------------------------------------------------------------===//
 
 class RVVOutBuiltin<string suffix, string prototype, string type_range>
     : RVVBuiltin<suffix, prototype, type_range> {
   let IntrinsicTypes = [-1];
let Name = "vset_v", Log2LMUL = [0, 1, 2], MaskedPolicyScheme = NonePolicy,
       }
       }] in {
     foreach dst_lmul = ["(LFixedLog2LMUL:1)", "(LFixedLog2LMUL:2)", "(LFixedLog2LMUL:3)"] in {
       def : RVVBuiltin<"v" # dst_lmul # "v", dst_lmul # "v" # dst_lmul # "vKzv", "csilxfd">;
       def : RVVBuiltin<"Uv" # dst_lmul # "Uv", dst_lmul # "Uv" # dst_lmul #"UvKzUv", "csil">;
     }
   }
 }
-
-include "riscv_sifive_vector.td"

clang/include/clang/Sema/RISCVIntrinsicManager.h

 namespace clang {
 class LookupResult;
 class IdentifierInfo;
 class Preprocessor;
 
 namespace sema {
 class RISCVIntrinsicManager {
 public:
+  enum class IntrinsicKind : uint8_t { RVV, SIFIVE_VECTOR };
+
   virtual ~RISCVIntrinsicManager() = default;
 
   // Create RISC-V intrinsic and insert into symbol table and return true if
   // found, otherwise return false.
   virtual bool CreateIntrinsicIfFound(LookupResult &LR, IdentifierInfo *II,
                                       Preprocessor &PP) = 0;
 };
 } // end namespace sema
 } // end namespace clang
 
 #endif

clang/include/clang/Sema/Sema.h

   /// Increment when we find a reference; decrement when we find an ignored
   /// assignment.  Ultimately the value is 0 if every reference is an ignored
   /// assignment.
   llvm::DenseMap<const VarDecl *, int> RefsMinusAssignments;
 
   /// Indicate RISC-V vector builtin functions enabled or not.
   bool DeclareRISCVVBuiltins = false;
 
+  /// Indicate RISC-V Sifive vector builtin functions enabled or not.
+  bool DeclareRISCVVectorBuiltins = false;
+
 private:
   std::unique_ptr<sema::RISCVIntrinsicManager> RVIntrinsicManager;
 
   std::optional<std::unique_ptr<DarwinSDKInfo>> CachedDarwinSDKInfo;
 
   bool WarnedDarwinSDKInfoMissing = false;
 
 public:

clang/lib/CodeGen/CGBuiltin.cpp

case RISCV::BI__builtin_riscv_ntl_store: {
     Store->setMetadata(CGM.getModule().getMDKindID("riscv-nontemporal-domain"),
                        RISCVDomainNode);
 
     return Store;
   }
 
   // Vector builtins are handled from here.
 #include "clang/Basic/riscv_vector_builtin_cg.inc"
+  // SiFive Vector builtins are handled from here.
+#include "clang/Basic/riscv_sifive_vector_builtin_cg.inc"
   }
 
   assert(ID != Intrinsic::not_intrinsic);
 
   llvm::Function *F = CGM.getIntrinsic(ID, IntrinsicTypes);
   return Builder.CreateCall(F, Ops, "");
 }
 

clang/lib/Headers/CMakeLists.txt

set(ppc_htm_files
   htmintrin.h
   htmxlintrin.h
   )
 
 set(riscv_files
   riscv_ntlh.h
   )
 
+set(sifive_files
+  sifive_vector.h
+  )
+
 set(systemz_files
   s390intrin.h
   vecintrin.h
   )
 
 set(ve_files
   velintrin.h
   velintrin_gen.h
set(files
   ${hexagon_files}
   ${hip_files}
   ${loongarch_files}
   ${mips_msa_files}
   ${opencl_files}
   ${ppc_files}
   ${ppc_htm_files}
   ${riscv_files}
+  ${sifive_files}
   ${systemz_files}
   ${ve_files}
   ${x86_files}
   ${webassembly_files}
   ${windows_only_files}
   ${utility_files}
   )
 

clang/lib/Headers/sifive_vector.h

+//===----- sifive_vector.h - SiFive Vector definitions --------------------===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef _SIFIVE_VECTOR_H_
+#define _SIFIVE_VECTOR_H_
+
+#include "riscv_vector.h"
+
+#pragma clang riscv intrinsic sifive_vector
+
+#endif //_SIFIVE_VECTOR_H_

clang/lib/Parse/ParsePragma.cpp

PP.Diag(Tok.getLocation(), diag::warn_pragma_extra_tokens_at_eol)
         << "clang max_tokens_total";
     return;
   }
 
   PP.overrideMaxTokens(MaxTokens, Loc);
 }
 
 // Handle '#pragma clang riscv intrinsic vector'.
+//        '#pragma clang riscv intrinsic sifive_vector'.
 void PragmaRISCVHandler::HandlePragma(Preprocessor &PP,
                                       PragmaIntroducer Introducer,
                                       Token &FirstToken) {
   Token Tok;
   PP.Lex(Tok);
   IdentifierInfo *II = Tok.getIdentifierInfo();
 
   if (!II || !II->isStr("intrinsic")) {
     PP.Diag(Tok.getLocation(), diag::warn_pragma_invalid_argument)
         << PP.getSpelling(Tok) << "riscv" << /*Expected=*/true << "'intrinsic'";
     return;
   }
 
   PP.Lex(Tok);
   II = Tok.getIdentifierInfo();
-  if (!II || !II->isStr("vector")) {
+  StringRef IntrinsicClass = II->getName();
+  if (!II || !(II->isStr("vector") || II->isStr("sifive_vector"))) {
     PP.Diag(Tok.getLocation(), diag::warn_pragma_invalid_argument)
-        << PP.getSpelling(Tok) << "riscv" << /*Expected=*/true << "'vector'";
+        << PP.getSpelling(Tok) << "riscv" << /*Expected=*/true
+        << "'vector' or 'sifive_vector'";
     return;
   }
 
   PP.Lex(Tok);
   if (Tok.isNot(tok::eod)) {
     PP.Diag(Tok.getLocation(), diag::warn_pragma_extra_tokens_at_eol)
         << "clang riscv intrinsic";
     return;
   }
 
+  if (IntrinsicClass == "vector")
     Actions.DeclareRISCVVBuiltins = true;
+  else if (IntrinsicClass == "sifive_vector")
+    Actions.DeclareRISCVVectorBuiltins = true;
 }

clang/lib/Sema/SemaLookup.cpp

if (II) {
         auto Index = isOpenCLBuiltin(II->getName());
         if (Index.first) {
           InsertOCLBuiltinDeclarationsFromTable(*this, R, II, Index.first - 1,
                                                 Index.second);
           return true;
         }
       }
 
-      if (DeclareRISCVVBuiltins) {
+      if (DeclareRISCVVBuiltins || DeclareRISCVVectorBuiltins) {
         if (!RVIntrinsicManager)
           RVIntrinsicManager = CreateRISCVIntrinsicManager(*this);
 
         if (RVIntrinsicManager->CreateIntrinsicIfFound(R, II, PP))
           return true;
       }
 
       // If this is a builtin on this (or all) targets, create the decl.

clang/lib/Sema/SemaRISCVVectorLookup.cpp

 #include <optional>
 #include <string>
 #include <vector>
 
 using namespace llvm;
 using namespace clang;
 using namespace clang::RISCV;
 
+using IntrinsicKind = sema::RISCVIntrinsicManager::IntrinsicKind;
+
 namespace {
 
 // Function definition of a RVV intrinsic.
 struct RVVIntrinsicDef {
   /// Full function name with suffix, e.g. vadd_vv_i32m1.
   std::string Name;
 
   /// Overloaded function name, e.g. vadd.

 } // namespace
 
 static const PrototypeDescriptor RVVSignatureTable[] = {
 #define DECL_SIGNATURE_TABLE
 #include "clang/Basic/riscv_vector_builtin_sema.inc"
 #undef DECL_SIGNATURE_TABLE
 };
 
+static const PrototypeDescriptor RVSiFiveVectorSignatureTable[] = {
+#define DECL_SIGNATURE_TABLE
+#include "clang/Basic/riscv_sifive_vector_builtin_sema.inc"
+#undef DECL_SIGNATURE_TABLE
+};
+
 static const RVVIntrinsicRecord RVVIntrinsicRecords[] = {
 #define DECL_INTRINSIC_RECORDS
 #include "clang/Basic/riscv_vector_builtin_sema.inc"
 #undef DECL_INTRINSIC_RECORDS
 };
 
+static const RVVIntrinsicRecord RVSiFiveVectorIntrinsicRecords[] = {
+#define DECL_INTRINSIC_RECORDS
+#include "clang/Basic/riscv_sifive_vector_builtin_sema.inc"
+#undef DECL_INTRINSIC_RECORDS
+};
+
 // Get subsequence of signature table.
-static ArrayRef<PrototypeDescriptor> ProtoSeq2ArrayRef(uint16_t Index,
-                                                       uint8_t Length) {
+static ArrayRef<PrototypeDescriptor>
+ProtoSeq2ArrayRef(IntrinsicKind K, uint16_t Index, uint8_t Length) {
+  switch (K) {
+  default:
+    llvm_unreachable("Unsupported intrinsic kind.");
+  case IntrinsicKind::RVV:
     return ArrayRef(&RVVSignatureTable[Index], Length);
+  case IntrinsicKind::SIFIVE_VECTOR:
+    return ArrayRef(&RVSiFiveVectorSignatureTable[Index], Length);
+  }
 }
 
 static QualType RVVType2Qual(ASTContext &Context, const RVVType *Type) {
   QualType QT;
   switch (Type->getScalarType()) {
   case ScalarTypeKind::Void:
     QT = Context.VoidTy;
     break;

 };
 } // namespace
 
 void RISCVIntrinsicManagerImpl::InitIntrinsicList() {
   const TargetInfo &TI = Context.getTargetInfo();
   bool HasRV64 = TI.hasFeature("64bit");
   bool HasFullMultiply = TI.hasFeature("v");
 
+  auto ConstructRVVIntrinsics = [&](ArrayRef<RVVIntrinsicRecord> Recs,
+                                    IntrinsicKind K) {
     // Construction of RVVIntrinsicRecords need to sync with createRVVIntrinsics
     // in RISCVVEmitter.cpp.
-  for (auto &Record : RVVIntrinsicRecords) {
+    for (auto &Record : Recs) {
       // Create Intrinsics for each type and LMUL.
       BasicType BaseType = BasicType::Unknown;
       ArrayRef<PrototypeDescriptor> BasicProtoSeq =
-        ProtoSeq2ArrayRef(Record.PrototypeIndex, Record.PrototypeLength);
+          ProtoSeq2ArrayRef(K, Record.PrototypeIndex, Record.PrototypeLength);
       ArrayRef<PrototypeDescriptor> SuffixProto =
-        ProtoSeq2ArrayRef(Record.SuffixIndex, Record.SuffixLength);
+          ProtoSeq2ArrayRef(K, Record.SuffixIndex, Record.SuffixLength);
       ArrayRef<PrototypeDescriptor> OverloadedSuffixProto = ProtoSeq2ArrayRef(
-        Record.OverloadedSuffixIndex, Record.OverloadedSuffixSize);
+          K, Record.OverloadedSuffixIndex, Record.OverloadedSuffixSize);
 
       PolicyScheme UnMaskedPolicyScheme =
           static_cast<PolicyScheme>(Record.UnMaskedPolicyScheme);
       PolicyScheme MaskedPolicyScheme =
           static_cast<PolicyScheme>(Record.MaskedPolicyScheme);
 
       const Policy DefaultPolicy;
 
       llvm::SmallVector<PrototypeDescriptor> ProtoSeq =
           RVVIntrinsic::computeBuiltinTypes(BasicProtoSeq, /*IsMasked=*/false,
                                             /*HasMaskedOffOperand=*/false,
                                             Record.HasVL, Record.NF,
                                             UnMaskedPolicyScheme, DefaultPolicy);
 
       llvm::SmallVector<PrototypeDescriptor> ProtoMaskSeq =
           RVVIntrinsic::computeBuiltinTypes(
               BasicProtoSeq, /*IsMasked=*/true, Record.HasMaskedOffOperand,
               Record.HasVL, Record.NF, MaskedPolicyScheme, DefaultPolicy);
 
       bool UnMaskedHasPolicy = UnMaskedPolicyScheme != PolicyScheme::SchemeNone;
       bool MaskedHasPolicy = MaskedPolicyScheme != PolicyScheme::SchemeNone;
       SmallVector<Policy> SupportedUnMaskedPolicies =
           RVVIntrinsic::getSupportedUnMaskedPolicies();
       SmallVector<Policy> SupportedMaskedPolicies =
           RVVIntrinsic::getSupportedMaskedPolicies(Record.HasTailPolicy,
                                                    Record.HasMaskPolicy);
 
       for (unsigned int TypeRangeMaskShift = 0;
            TypeRangeMaskShift <= static_cast<unsigned int>(BasicType::MaxOffset);
            ++TypeRangeMaskShift) {
         unsigned int BaseTypeI = 1 << TypeRangeMaskShift;
         BaseType = static_cast<BasicType>(BaseTypeI);
 
         if ((BaseTypeI & Record.TypeRangeMask) != BaseTypeI)
           continue;
 
         // Check requirement.
         if (((Record.RequiredExtensions & RVV_REQ_RV64) == RVV_REQ_RV64) &&
             !HasRV64)
           continue;
 
         if ((BaseType == BasicType::Int64) &&
             ((Record.RequiredExtensions & RVV_REQ_FullMultiply) ==
              RVV_REQ_FullMultiply) &&
             !HasFullMultiply)
           continue;
 
         // Expanded with different LMUL.
         for (int Log2LMUL = -3; Log2LMUL <= 3; Log2LMUL++) {
           if (!(Record.Log2LMULMask & (1 << (Log2LMUL + 3))))
             continue;
 
           std::optional<RVVTypes> Types =
               TypeCache.computeTypes(BaseType, Log2LMUL, Record.NF, ProtoSeq);
 
           // Ignored to create new intrinsic if there are any illegal types.
           if (!Types.has_value())
             continue;
 
           std::string SuffixStr = RVVIntrinsic::getSuffixStr(
               TypeCache, BaseType, Log2LMUL, SuffixProto);
           std::string OverloadedSuffixStr = RVVIntrinsic::getSuffixStr(
               TypeCache, BaseType, Log2LMUL, OverloadedSuffixProto);
 
           // Create non-masked intrinsic.
           InitRVVIntrinsic(Record, SuffixStr, OverloadedSuffixStr, false, *Types,
                            UnMaskedHasPolicy, DefaultPolicy);
 
           // Create non-masked policy intrinsic.
           if (Record.UnMaskedPolicyScheme != PolicyScheme::SchemeNone) {
-          for (const auto &P : SupportedUnMaskedPolicies) {
+            for (auto P : SupportedUnMaskedPolicies) {
               llvm::SmallVector<PrototypeDescriptor> PolicyPrototype =
                   RVVIntrinsic::computeBuiltinTypes(
                       BasicProtoSeq, /*IsMasked=*/false,
                       /*HasMaskedOffOperand=*/false, Record.HasVL, Record.NF,
                       UnMaskedPolicyScheme, P);
               std::optional<RVVTypes> PolicyTypes = TypeCache.computeTypes(
                   BaseType, Log2LMUL, Record.NF, PolicyPrototype);
               InitRVVIntrinsic(Record, SuffixStr, OverloadedSuffixStr,
                                /*IsMask=*/false, *PolicyTypes, UnMaskedHasPolicy,
                                P);
             }
           }
           if (!Record.HasMasked)
             continue;
           // Create masked intrinsic.
           std::optional<RVVTypes> MaskTypes =
               TypeCache.computeTypes(BaseType, Log2LMUL, Record.NF, ProtoMaskSeq);
           InitRVVIntrinsic(Record, SuffixStr, OverloadedSuffixStr, true,
                            *MaskTypes, MaskedHasPolicy, DefaultPolicy);
           if (Record.MaskedPolicyScheme == PolicyScheme::SchemeNone)
             continue;
           // Create masked policy intrinsic.
           for (auto P : SupportedMaskedPolicies) {
             llvm::SmallVector<PrototypeDescriptor> PolicyPrototype =
                 RVVIntrinsic::computeBuiltinTypes(
                     BasicProtoSeq, /*IsMasked=*/true, Record.HasMaskedOffOperand,
                     Record.HasVL, Record.NF, MaskedPolicyScheme, P);
             std::optional<RVVTypes> PolicyTypes = TypeCache.computeTypes(
                 BaseType, Log2LMUL, Record.NF, PolicyPrototype);
             InitRVVIntrinsic(Record, SuffixStr, OverloadedSuffixStr,
                              /*IsMask=*/true, *PolicyTypes, MaskedHasPolicy, P);
           }
         } // End for different LMUL
       } // End for different TypeRange
     }
+  };
+  if (S.DeclareRISCVVBuiltins)
+    ConstructRVVIntrinsics(RVVIntrinsicRecords,
+                           IntrinsicKind::RVV);
+  if (S.DeclareRISCVVectorBuiltins)
+    ConstructRVVIntrinsics(RVSiFiveVectorIntrinsicRecords,
+                           IntrinsicKind::SIFIVE_VECTOR);
 }
 
 // Compute name and signatures for intrinsic with practical types.
 void RISCVIntrinsicManagerImpl::InitRVVIntrinsic(
     const RVVIntrinsicRecord &Record, StringRef SuffixStr,
     StringRef OverloadedSuffixStr, bool IsMasked, RVVTypes &Signature,
     bool HasPolicy, Policy PolicyAttrs) {
   // Function name, e.g. vadd_vv_i32m1.

clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/xsfvcp-x-rv64.c

 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
 // RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +xsfvcp -disable-O0-optnone -emit-llvm %s -o - | opt -S -passes=mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
 
-#include <riscv_vector.h>
+#include <sifive_vector.h>
 
 #define p27_26 (0b11)
 #define p24_20 (0b11111)
 #define p11_7  (0b11111)
 
 // CHECK-RV64-LABEL: @test_sf_vc_x_se_u64m1(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    call void @llvm.riscv.sf.vc.x.se.e64m1.i64.i64.i64(i64 3, i64 31, i64 31, i64 [[RS1:%.*]], i64 [[VL:%.*]])

clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/xsfvcp-x.c

 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
 // RUN: %clang_cc1 -triple riscv32 -target-feature +v -target-feature +xsfvcp -disable-O0-optnone -emit-llvm %s -o - | opt -S -passes=mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
 // RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +xsfvcp -disable-O0-optnone -emit-llvm %s -o - | opt -S -passes=mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
 
-#include <riscv_vector.h>
+#include <sifive_vector.h>
 
 #define p27_26 (0b11)
 #define p24_20 (0b11111)
 #define p11_7  (0b11111)
 #define simm5  (10)
 
 // CHECK-RV32-LABEL: @test_sf_vc_x_se_u8mf8(
 // CHECK-RV32-NEXT:  entry:

clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/xsfvcp-xv-rv64.c

 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
 // REQUIRES: riscv-registered-target
 // RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +xsfvcp -disable-O0-optnone -emit-llvm %s -o - | opt -S -passes=mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
 
-#include <riscv_vector.h>
+#include <sifive_vector.h>
 
 #define p27_26 (0b11)
 #define p11_7  (0b11111)
 
 // CHECK-RV64-LABEL: @test_sf_vc_xv_se_u64m1(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    call void @llvm.riscv.sf.vc.xv.se.i64.nxv1i64.i64.i64(i64 3, i64 31, <vscale x 1 x i64> [[VS2:%.*]], i64 [[RS1:%.*]], i64 [[VL:%.*]])
 // CHECK-RV64-NEXT:    ret void

clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/xsfvcp-xv.c

 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
 // RUN: %clang_cc1 -triple riscv32 -target-feature +v -target-feature +zfh -target-feature +xsfvcp -disable-O0-optnone -emit-llvm %s -o - | opt -S -passes=mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
 // RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +xsfvcp -disable-O0-optnone -emit-llvm %s -o - | opt -S -passes=mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
 
-#include <riscv_vector.h>
+#include <sifive_vector.h>
 
 #define p27_26 (0b11)
 #define p26    (0b1)
 #define p11_7  (0b11111)
 #define simm5  (10)
 
 // CHECK-RV32-LABEL: @test_sf_vc_vv_se_u8mf8(
 // CHECK-RV32-NEXT:  entry:

clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/xsfvcp-xvv-rv64.c

 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
 // REQUIRES: riscv-registered-target
 // RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +xsfvcp -disable-O0-optnone -emit-llvm %s -o - | opt -S -passes=mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
 
-#include <riscv_vector.h>
+#include <sifive_vector.h>
 
 #define p27_26 (0b11)
 
 // CHECK-RV64-LABEL: @test_sf_vc_xvv_se_u64m1(
 // CHECK-RV64-NEXT:  entry:
 // CHECK-RV64-NEXT:    call void @llvm.riscv.sf.vc.xvv.se.i64.nxv1i64.i64.i64(i64 3, <vscale x 1 x i64> [[VD:%.*]], <vscale x 1 x i64> [[VS2:%.*]], i64 [[RS1:%.*]], i64 [[VL:%.*]])
 // CHECK-RV64-NEXT:    ret void
 //

clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/xsfvcp-xvv.c

 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
 // RUN: %clang_cc1 -triple riscv32 -target-feature +v -target-feature +zfh -target-feature +xsfvcp -disable-O0-optnone -emit-llvm %s -o - | opt -S -passes=mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
 // RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +xsfvcp -disable-O0-optnone -emit-llvm %s -o - | opt -S -passes=mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
 
-#include <riscv_vector.h>
+#include <sifive_vector.h>
 
 #define p27_26 (0b11)
 #define p26    (0b1)
 #define simm5  (10)
 
 // CHECK-RV32-LABEL: @test_sf_vc_vvv_se_u8mf8(
 // CHECK-RV32-NEXT:  entry:
 // CHECK-RV32-NEXT:    call void @llvm.riscv.sf.vc.vvv.se.i32.nxv1i8.nxv1i8.i32(i32 3, <vscale x 1 x i8> [[VD:%.*]], <vscale x 1 x i8> [[VS2:%.*]], <vscale x 1 x i8> [[VS1:%.*]], i32 [[VL:%.*]])

clang/test/CodeGen/RISCV/rvv-intrinsics-autogenerated/non-policy/non-overloaded/xsfvcp-xvw.c

 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
 // RUN: %clang_cc1 -triple riscv32 -target-feature +v -target-feature +zfh -target-feature +xsfvcp -disable-O0-optnone -emit-llvm %s -o - | opt -S -passes=mem2reg | FileCheck --check-prefix=CHECK-RV32 %s
 // RUN: %clang_cc1 -triple riscv64 -target-feature +v -target-feature +zfh -target-feature +xsfvcp -disable-O0-optnone -emit-llvm %s -o - | opt -S -passes=mem2reg | FileCheck --check-prefix=CHECK-RV64 %s
 
-#include <riscv_vector.h>
+#include <sifive_vector.h>
 
 #define p27_26 (0b11)
 #define p26    (0b1)
 #define simm5  (10)
 
 // CHECK-RV32-LABEL: @test_sf_vc_vvw_se_u8mf8(
 // CHECK-RV32-NEXT:  entry:
 // CHECK-RV32-NEXT:    call void @llvm.riscv.sf.vc.vvw.se.i32.nxv1i16.nxv1i8.nxv1i8.i32(i32 3, <vscale x 1 x i16> [[VD:%.*]], <vscale x 1 x i8> [[VS2:%.*]], <vscale x 1 x i8> [[VS1:%.*]], i32 [[VL:%.*]])

clang/test/CodeGen/RISCV/rvv-intrinsics-handcrafted/xsfvcp-index-out-of-range.c

 // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
 // REQUIRES: riscv-registered-target
 // RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \
 // RUN:   -target-feature +v -target-feature +zfh -target-feature +experimental-zvfh \
 // RUN:   -target-feature +xsfvcp \
 // RUN:   -fsyntax-only -verify %s
 
-#include <riscv_vector.h>
+#include <sifive_vector.h>
 
 #define p27_26 (0b11)
 #define p26    (0b1)
 #define p24_20 (0b11111)
 #define p11_7  (0b11111)
 #define simm5  (15)
 
 #define p27_26_overflow (0b100)

clang/test/Sema/riscv-bad-intrinsic-pragma.c

 // RUN: %clang_cc1 -triple riscv64 -target-feature +v %s -emit-llvm -o - \
 // RUN:            2>&1 | FileCheck %s
 
 #pragma clang riscv intrinsic vvvv
-// CHECK:      warning: unexpected argument 'vvvv' to '#pragma riscv'; expected 'vector' [-Wignored-pragmas]
+// CHECK:      warning: unexpected argument 'vvvv' to '#pragma riscv'; expected 'vector' or 'sifive_vector' [-Wignored-pragmas]
 
 #pragma clang riscv what + 3241
 // CHECK:      warning: unexpected argument 'what' to '#pragma riscv'; expected 'intrinsic' [-Wignored-pragmas]
 #pragma clang riscv int i = 12;
 // CHECK:      warning: unexpected argument 'int' to '#pragma riscv'; expected 'intrinsic' [-Wignored-pragmas]
 #pragma clang riscv intrinsic vector bar
 // CHECK:     warning: extra tokens at end of '#pragma clang riscv intrinsic' - ignored [-Wignored-pragmas]
 

clang/utils/TableGen/TableGen.cpp

enum ActionType {
   GenArmCdeBuiltinDef,
   GenArmCdeBuiltinSema,
   GenArmCdeBuiltinCG,
   GenArmCdeBuiltinAliases,
   GenRISCVVectorHeader,
   GenRISCVVectorBuiltins,
   GenRISCVVectorBuiltinCG,
   GenRISCVVectorBuiltinSema,
+  GenRISCVSiFiveVectorBuiltins,
+  GenRISCVSiFiveVectorBuiltinCG,
+  GenRISCVSiFiveVectorBuiltinSema,
   GenAttrDocs,
   GenDiagDocs,
   GenOptDocs,
   GenDataCollectors,
   GenTestPragmaAttributeSupportedAttributes
 };
 
 namespace {
cl::values(
         clEnumValN(GenRISCVVectorHeader, "gen-riscv-vector-header",
                    "Generate riscv_vector.h for clang"),
         clEnumValN(GenRISCVVectorBuiltins, "gen-riscv-vector-builtins",
                    "Generate riscv_vector_builtins.inc for clang"),
         clEnumValN(GenRISCVVectorBuiltinCG, "gen-riscv-vector-builtin-codegen",
                    "Generate riscv_vector_builtin_cg.inc for clang"),
         clEnumValN(GenRISCVVectorBuiltinSema, "gen-riscv-vector-builtin-sema",
                    "Generate riscv_vector_builtin_sema.inc for clang"),
+        clEnumValN(GenRISCVSiFiveVectorBuiltins, "gen-riscv-sifive-vector-builtins",
+                   "Generate riscv_sifive_vector_builtins.inc for clang"),
+        clEnumValN(GenRISCVSiFiveVectorBuiltinCG, "gen-riscv-sifive-vector-builtin-codegen",
+                   "Generate riscv_sifive_vector_builtin_cg.inc for clang"),
+        clEnumValN(GenRISCVSiFiveVectorBuiltinSema, "gen-riscv-sifive-vector-builtin-sema",
+                   "Generate riscv_sifive_vector_builtin_sema.inc for clang"),
         clEnumValN(GenAttrDocs, "gen-attr-docs",
                    "Generate attribute documentation"),
         clEnumValN(GenDiagDocs, "gen-diag-docs",
                    "Generate diagnostic documentation"),
         clEnumValN(GenOptDocs, "gen-opt-docs", "Generate option documentation"),
         clEnumValN(GenDataCollectors, "gen-clang-data-collectors",
                    "Generate data collectors for AST nodes"),
         clEnumValN(GenTestPragmaAttributeSupportedAttributes,
case GenRISCVVectorBuiltins:
     EmitRVVBuiltins(Records, OS);
     break;
   case GenRISCVVectorBuiltinCG:
     EmitRVVBuiltinCG(Records, OS);
     break;
   case GenRISCVVectorBuiltinSema:
     EmitRVVBuiltinSema(Records, OS);
     break;
+  case GenRISCVSiFiveVectorBuiltins:
+    EmitRVVBuiltins(Records, OS);
+    break;
+  case GenRISCVSiFiveVectorBuiltinCG:
+    EmitRVVBuiltinCG(Records, OS);
+    break;
+  case GenRISCVSiFiveVectorBuiltinSema:
+    EmitRVVBuiltinSema(Records, OS);
+    break;
   case GenAttrDocs:
     EmitClangAttrDocs(Records, OS);
     break;
   case GenDiagDocs:
     EmitClangDiagDocs(Records, OS);
     break;
   case GenOptDocs:
     EmitClangOptDocs(Records, OS);

llvm/docs/CommandGuide/tblgen.rst

 .. option:: -gen-riscv-vector-builtins
 
   Generate ``riscv_vector_builtins.inc`` for Clang.
 
 .. option:: -gen-riscv-vector-builtin-codegen
 
   Generate ``riscv_vector_builtin_cg.inc`` for Clang.
 
+.. option:: -gen-riscv-sifive-vector-builtins
+
+  Generate ``riscv_sifive_vector_builtins.inc`` for Clang.
+
+.. option:: -gen-riscv-sifive-vector-builtin-codegen
+
+  Generate ``riscv_sifive_vector_builtin_cg.inc`` for Clang.
+
 .. option:: -gen-attr-docs
 
   Generate attribute documentation.
 
 .. option:: -gen-diag-docs
 
   Generate diagnostic documentation.