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[RISCV] Support LLVM IR intrinsics for XSfvcp extension.
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Authored by 4vtomat on Apr 10 2023, 6:01 AM.

Details

Summary

This patch aims at supporting LLVM IR for sifive VCIX(XSfvcp).

Note that sf.vc.x and sf.vc.i intrinsics don't have any vector types in the output
and inputs, but the intrinsic spec said that we still need to add vetvli for
them. Therefore, we need to encode the VTYPE to these IR names.

Diff Detail

Event Timeline

4vtomat created this revision.Apr 10 2023, 6:01 AM
Herald added a project: Restricted Project. · View Herald TranscriptApr 10 2023, 6:01 AM
4vtomat requested review of this revision.Apr 10 2023, 6:01 AM
craig.topper added inline comments.Apr 11 2023, 4:25 PM
llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td
492

Indent these since the if created a new scope

507

Indent

llvm/test/CodeGen/RISCV/rvv/xsfvcp-x.ll
240

Why is there no test for the e64 version of this intrinsic?

craig.topper added inline comments.Apr 11 2023, 4:34 PM
llvm/include/llvm/IR/IntrinsicsRISCVXsf.td
18

Aren't we supposed to have ImmArg<ArgIndex<0>>, ImmArg<ArgIndex<1>> for the immediate operands?

craig.topper added inline comments.Apr 11 2023, 4:36 PM
llvm/include/llvm/IR/IntrinsicsRISCVXsf.td
18

That's what is in our downstream. And we use llvm_i32_ty for those operands.

4vtomat updated this revision to Diff 513191.Apr 13 2023, 5:36 AM

Resolved Craig's comments

4vtomat added inline comments.Apr 13 2023, 5:42 AM
llvm/include/llvm/IR/IntrinsicsRISCVXsf.td
18

You are right, we should have these properties, I've added and make them to XLenVT type instead of i32 type, so that we can skip scalar legalization in lowerVectorIntrinsicScalars.

llvm/test/CodeGen/RISCV/rvv/xsfvcp-x.ll
240

I'm not sure what Nelson is concerning at that time, I guess it's because this test contains both 32 bits and 64 bits test, however e64 tests is not available in 32 bits target.

craig.topper added inline comments.Apr 13 2023, 9:17 AM
llvm/include/llvm/IR/IntrinsicsRISCVXsf.td
18

ImmArg automatically skips scalar legalization so that wouldn’t have been an issue.

We can use XLenVT.

craig.topper added inline comments.Apr 13 2023, 7:09 PM
llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td
124

There's a !tolower operator in tablegen.

493

Isn't there already a Scalar and ScalarRegClass field in vti?

craig.topper added inline comments.Apr 13 2023, 7:24 PM
llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td
218

Why do VCIX instruction have HasDummyMask=1? There's no mask operand in the MC instructions is there?

4vtomat added inline comments.Apr 13 2023, 11:41 PM
llvm/include/llvm/IR/IntrinsicsRISCVXsf.td
18

Got it!

llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td
493

We want vector argument to be integer and scalar argument to be float, so that's why we need to convert only scalar to float.

4vtomat updated this revision to Diff 513447.Apr 13 2023, 11:44 PM

Resolved Craig's comments.

craig.topper added inline comments.Apr 13 2023, 11:57 PM
llvm/lib/Target/RISCV/RISCVInstrInfoXSf.td
493

That makes sense. Thanks!

This revision is now accepted and ready to land.Apr 13 2023, 11:59 PM
This revision was landed with ongoing or failed builds.Apr 24 2023, 3:10 AM
This revision was automatically updated to reflect the committed changes.