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- Jan 29 2022, 6:29 AM (87 w, 3 d)
Tue, Sep 19
Mon, Sep 18
Add VRM2, VRM4 and VRM8 to CalleeSaved register list.
Sep 1 2023
Update commit message.
RVVArgDispatcher is the class used to compute and maximize the register usage by using the vector argument information placed in std::vector<RVVArgInfo>, it's both used by frontend and backend.
Currently I'm not sure where is the better file to place this class, so I just place it in RISCVTargetParser.h.
Finish handling vector arguments in backend.
Aug 31 2023
Aug 30 2023
Resolved MaskRay's comments.
Aug 29 2023
Update Craig's comment.
Aug 18 2023
Update test cases.
Aug 17 2023
Address Craig's comments.
Aug 16 2023
Update llvm/docs/RISCVUsage.rst.
Aug 15 2023
Update commit message.
Add an option to deduce vector cc(default off).
Aug 14 2023
- Apply clang-format for this patch
- Replace FileCheck --implicit-check-not=warning: with %clang -Werror
Aug 13 2023
Ping
Aug 11 2023
LGTM, but leave final decision to other reviewers~
LGTM, thanks!
Aug 9 2023
LGTM, thanks~
Rename the function in the test case.
Add test cases.
Aug 8 2023
Aug 3 2023
This update does a few things:
- Update test cases based on rvv-intrinsic-doc.
- Add checks for "zvknh[a|b]" instructions.
- Rename and restructure the function from CheckInvalidEGW to CheckInvalidVLENandLMUL.
Aug 2 2023
Update missing comment.
This update does a few things:
- Update Craig's comments.
- Make LMUL=8 valid(https://github.com/riscv-non-isa/rvv-intrinsic-doc/pull/234#discussion_r1282568330).
- Rebase.
Aug 1 2023
Update Craig's comment.
Resolved Craig's comment.
Jul 31 2023
Resolved Craig's comment.
Jul 30 2023
Updated test case.
Resolved MaskRay's comments.
Resolved Aaron's comments.
Also group some code and refactoring some code to make it much clear.
Rebase
Resolved MaskRay's comments, thanks for reviewing!!
Jul 27 2023
Resolved Craig's comment.
Jul 26 2023
After discusstion in https://github.com/riscv-non-isa/rvv-intrinsic-doc/pull/234,
we will have multiple lmuls for scalar type operands.
Currently the test cases for those instructions are only presented in vaesdf,
all other instructions test cases will be copied from rvv-intrinsic-doc once
they're ready.
Also added test case for sema checking for checking valid lmul.
Resolved Craig's comments.
This update includes:
- Add the constraint: LMUL*VLEN < EGW during lowering instructions.
- Enumerate over all of lmul less or equal to vd type's lmul for those instructions that have scalar operand.
Add a test case for invalid example.