[RISCV][CodeGen] Add codegen pattern for experimental zfa extension (FLI and FCVTMOD not included)

[joshua-arch1]

Summary

This patch implements experimental support for the RISCV Zfa extension except FLI and FCVTMOD instructions as specified here: https://github.com/riscv/riscv-isa-manual/releases/download/draft-20221119-5234c63/riscv-spec.pdf, Ch. 25. This extension has not been ratified. Once ratified, it'll move out of experimental status.

This change adds codegen support.

[jrtc27]

You don’t need to mention FCVTMOD given it does not apply to C/C++.

[joshua-arch1]

In D143982#4125543, @jrtc27 wrote:

You don’t need to mention FCVTMOD given it does not apply to C/C++.

Maybe we can define intrinsics like llvm.fptosi.sat.i32.f64 but without saturating. If feasible, I can have a try.

[craig.topper]

LGTM with that one formatting fix.

llvm/lib/Target/RISCV/RISCVInstrInfoZfa.td

91

This } should line up with the l in let

[asb]

I think function renaming was missed in half-zfa.ll.

Also, most of these tests have the same output for RV32 and RV64, so would benefit from having common CHECK prefixes for them both (e.g. CHECKIZFA), so visual inspection is easier.

llvm/test/CodeGen/RISCV/half-zfa.ll

10

The tests in this file should presumable be e.g. fminm_h rather than e.g. fminm_d (seems to be a repeated mistake elsewhere in this file).

[jrtc27]

In D143982#4125543, @jrtc27 wrote:

You don’t need to mention FCVTMOD given it does not apply to C/C++.

This was not fixed in the committed version, nor was the Differential Revision: link included, nor reviewer information. Please use arc patch/amend appropriately in future, it's annoying when commits don't have this information as it's a hassle to have to go back and find the right revision manually.

[joshua-arch1]

In D143982#4131071, @jrtc27 wrote:

In D143982#4125543, @jrtc27 wrote:

You don’t need to mention FCVTMOD given it does not apply to C/C++.

This was not fixed in the committed version, nor was the Differential Revision: link included, nor reviewer information. Please use arc patch/amend appropriately in future, it's annoying when commits don't have this information as it's a hassle to have to go back and find the right revision manually.

I see. I'll pay attention next time.

[asb]

In D143982#4126556, @asb wrote:

I think function renaming was missed in half-zfa.ll.

It looks like this was addressed in the committed version - thanks!

Also, most of these tests have the same output for RV32 and RV64, so would benefit from having common CHECK prefixes for them both (e.g. CHECKIZFA), so visual inspection is easier.

I think you might have missed my comment here.

llvm/lib/Target/RISCV/RISCVISelLowering.cpp

static const unsigned FPRndMode[] = {
       ISD::FROUNDEVEN};
 
   if (Subtarget.hasStdExtZfhOrZfhmin())
     setOperationAction(ISD::BITCAST, MVT::i16, Custom);
 
   if (Subtarget.hasStdExtZfhOrZfhmin()) {
     if (Subtarget.hasStdExtZfh()) {
       setOperationAction(FPLegalNodeTypes, MVT::f16, Legal);
-      setOperationAction(FPRndMode, MVT::f16, Custom);
+      setOperationAction(FPRndMode, MVT::f16,
+                         Subtarget.hasStdExtZfa() ? Legal : Custom);
       setOperationAction(ISD::SELECT, MVT::f16, Custom);
     } else {
       static const unsigned ZfhminPromoteOps[] = {
           ISD::FMINNUM,      ISD::FMAXNUM,       ISD::FADD,
           ISD::FSUB,         ISD::FMUL,          ISD::FMA,
           ISD::FDIV,         ISD::FSQRT,         ISD::FABS,
           ISD::FNEG,         ISD::STRICT_FMA,    ISD::STRICT_FADD,
           ISD::STRICT_FSUB,  ISD::STRICT_FMUL,   ISD::STRICT_FDIV,
if (Subtarget.hasStdExtZfhOrZfhmin()) {
     }
 
     setOperationAction(ISD::STRICT_FP_ROUND, MVT::f16, Legal);
     setOperationAction(ISD::STRICT_FP_EXTEND, MVT::f32, Legal);
     setCondCodeAction(FPCCToExpand, MVT::f16, Expand);
     setOperationAction(ISD::SELECT_CC, MVT::f16, Expand);
     setOperationAction(ISD::BR_CC, MVT::f16, Expand);
 
-    setOperationAction({ISD::FREM, ISD::FNEARBYINT, ISD::FPOW, ISD::FPOWI,
+    setOperationAction(ISD::FNEARBYINT, MVT::f16,
+                       Subtarget.hasStdExtZfa() ? Legal : Promote);
+    setOperationAction({ISD::FREM, ISD::FPOW, ISD::FPOWI,
                         ISD::FCOS, ISD::FSIN, ISD::FSINCOS, ISD::FEXP,
                         ISD::FEXP2, ISD::FLOG, ISD::FLOG2, ISD::FLOG10},
                        MVT::f16, Promote);
 
     // FIXME: Need to promote f16 STRICT_* to f32 libcalls, but we don't have
     // complete support for all operations in LegalizeDAG.
     setOperationAction({ISD::STRICT_FCEIL, ISD::STRICT_FFLOOR,
                         ISD::STRICT_FNEARBYINT, ISD::STRICT_FRINT,
                         ISD::STRICT_FROUND, ISD::STRICT_FROUNDEVEN,
                         ISD::STRICT_FTRUNC},
                        MVT::f16, Promote);
 
     // We need to custom promote this.
     if (Subtarget.is64Bit())
       setOperationAction(ISD::FPOWI, MVT::i32, Custom);
   }
 
   if (Subtarget.hasStdExtF()) {
     setOperationAction(FPLegalNodeTypes, MVT::f32, Legal);
-    setOperationAction(FPRndMode, MVT::f32, Custom);
+    setOperationAction(FPRndMode, MVT::f32,
+                       Subtarget.hasStdExtZfa() ? Legal : Custom);
     setCondCodeAction(FPCCToExpand, MVT::f32, Expand);
     setOperationAction(ISD::SELECT_CC, MVT::f32, Expand);
     setOperationAction(ISD::SELECT, MVT::f32, Custom);
     setOperationAction(ISD::BR_CC, MVT::f32, Expand);
     setOperationAction(FPOpToExpand, MVT::f32, Expand);
     setLoadExtAction(ISD::EXTLOAD, MVT::f32, MVT::f16, Expand);
     setTruncStoreAction(MVT::f32, MVT::f16, Expand);
+
+    if (Subtarget.hasStdExtZfa())
+      setOperationAction(ISD::FNEARBYINT, MVT::f32, Legal);
   }
 
   if (Subtarget.hasStdExtF() && Subtarget.is64Bit())
     setOperationAction(ISD::BITCAST, MVT::i32, Custom);
 
   if (Subtarget.hasStdExtD()) {
     setOperationAction(FPLegalNodeTypes, MVT::f64, Legal);
-    if (Subtarget.is64Bit()) {
-      setOperationAction(FPRndMode, MVT::f64, Custom);
+
+    if (Subtarget.hasStdExtZfa()) {
+      setOperationAction(FPRndMode, MVT::f64, Legal);
+      setOperationAction(ISD::FNEARBYINT, MVT::f64, Legal);
+      setOperationAction(ISD::BITCAST, MVT::i64, Custom);
+      setOperationAction(ISD::BITCAST, MVT::f64, Custom);
     }
+
+    if (Subtarget.is64Bit())
+      setOperationAction(FPRndMode, MVT::f64,
+                         Subtarget.hasStdExtZfa() ? Legal : Custom);
+
     setOperationAction(ISD::STRICT_FP_ROUND, MVT::f32, Legal);
     setOperationAction(ISD::STRICT_FP_EXTEND, MVT::f64, Legal);
     setCondCodeAction(FPCCToExpand, MVT::f64, Expand);
     setOperationAction(ISD::SELECT_CC, MVT::f64, Expand);
     setOperationAction(ISD::SELECT, MVT::f64, Custom);
     setOperationAction(ISD::BR_CC, MVT::f64, Expand);
     setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f32, Expand);
     setTruncStoreAction(MVT::f64, MVT::f32, Expand);
case ISD::BITCAST: {
     }
     if (VT == MVT::f32 && Op0VT == MVT::i32 && Subtarget.is64Bit() &&
         Subtarget.hasStdExtF()) {
       SDValue NewOp0 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i64, Op0);
       SDValue FPConv =
           DAG.getNode(RISCVISD::FMV_W_X_RV64, DL, MVT::f32, NewOp0);
       return FPConv;
     }
+    if (VT == MVT::f64 && Op0VT == MVT::i64 && XLenVT == MVT::i32 &&
+        Subtarget.hasStdExtZfa()) {
+      SDValue Lo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, Op0,
+                               DAG.getConstant(0, DL, MVT::i32));
+      SDValue Hi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, Op0,
+                               DAG.getConstant(1, DL, MVT::i32));
+      SDValue RetReg =
+          DAG.getNode(RISCVISD::BuildPairF64, DL, MVT::f64, Lo, Hi);
+      return RetReg;
+    }
 
     // Consider other scalar<->scalar casts as legal if the types are legal.
     // Otherwise expand them.
     if (!VT.isVector() && !Op0VT.isVector()) {
       if (isTypeLegal(VT) && isTypeLegal(Op0VT))
         return Op;
       return SDValue();
     }
if (VT == MVT::i16 && Op0VT == MVT::f16 &&
         Subtarget.hasStdExtZfhOrZfhmin()) {
       SDValue FPConv = DAG.getNode(RISCVISD::FMV_X_ANYEXTH, DL, XLenVT, Op0);
       Results.push_back(DAG.getNode(ISD::TRUNCATE, DL, MVT::i16, FPConv));
     } else if (VT == MVT::i32 && Op0VT == MVT::f32 && Subtarget.is64Bit() &&
                Subtarget.hasStdExtF()) {
       SDValue FPConv =
           DAG.getNode(RISCVISD::FMV_X_ANYEXTW_RV64, DL, MVT::i64, Op0);
       Results.push_back(DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, FPConv));
+    } else if (VT == MVT::i64 && Op0VT == MVT::f64 && XLenVT == MVT::i32 &&
+               Subtarget.hasStdExtZfa()) {
+      SDValue NewReg = DAG.getNode(RISCVISD::SplitF64, DL,
+                                   DAG.getVTList(MVT::i32, MVT::i32), Op0);
+      SDValue RetReg = DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64,
+                                   NewReg.getValue(0), NewReg.getValue(1));
+      Results.push_back(RetReg);
     } else if (!VT.isVector() && Op0VT.isFixedLengthVector() &&
                isTypeLegal(Op0VT)) {
       // Custom-legalize bitcasts from fixed-length vector types to illegal
       // scalar types in order to improve codegen. Bitcast the vector to a
       // one-element vector type whose element type is the same as the result
       // type, and extract the first element.
       EVT BVT = EVT::getVectorVT(*DAG.getContext(), VT, 1);
       if (isTypeLegal(BVT)) {
static MachineBasicBlock *emitReadCycleWidePseudo(MachineInstr &MI,
   LoopMBB->addSuccessor(DoneMBB);
 
   MI.eraseFromParent();
 
   return DoneMBB;
 }
 
 static MachineBasicBlock *emitSplitF64Pseudo(MachineInstr &MI,
-                                             MachineBasicBlock *BB) {
+                                             MachineBasicBlock *BB,
+                                             const RISCVSubtarget &Subtarget) {
   assert(MI.getOpcode() == RISCV::SplitF64Pseudo && "Unexpected instruction");
 
   MachineFunction &MF = *BB->getParent();
   DebugLoc DL = MI.getDebugLoc();
   const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
   const TargetRegisterInfo *RI = MF.getSubtarget().getRegisterInfo();
   Register LoReg = MI.getOperand(0).getReg();
   Register HiReg = MI.getOperand(1).getReg();
   Register SrcReg = MI.getOperand(2).getReg();
+  if (Subtarget.hasStdExtD() && Subtarget.hasStdExtZfa() &&
+      !Subtarget.is64Bit()) {
+    BuildMI(*BB, MI, DL, TII.get(RISCV::FMV_X_W_FPR64), LoReg).addReg(SrcReg);
+    BuildMI(*BB, MI, DL, TII.get(RISCV::FMVH_X_D), HiReg).addReg(SrcReg);
+    MI.eraseFromParent(); // The pseudo instruction is gone now.
+    return BB;
+  }
+
   const TargetRegisterClass *SrcRC = &RISCV::FPR64RegClass;
   int FI = MF.getInfo<RISCVMachineFunctionInfo>()->getMoveF64FrameIndex(MF);
 
   TII.storeRegToStackSlot(*BB, MI, SrcReg, MI.getOperand(2).isKill(), FI, SrcRC,
                           RI, Register());
   MachinePointerInfo MPI = MachinePointerInfo::getFixedStack(MF, FI);
   MachineMemOperand *MMOLo =
       MF.getMachineMemOperand(MPI, MachineMemOperand::MOLoad, 4, Align(8));
   MachineMemOperand *MMOHi = MF.getMachineMemOperand(
       MPI.getWithOffset(4), MachineMemOperand::MOLoad, 4, Align(8));
   BuildMI(*BB, MI, DL, TII.get(RISCV::LW), LoReg)
       .addFrameIndex(FI)
       .addImm(0)
       .addMemOperand(MMOLo);
   BuildMI(*BB, MI, DL, TII.get(RISCV::LW), HiReg)
       .addFrameIndex(FI)
       .addImm(4)
       .addMemOperand(MMOHi);
   MI.eraseFromParent(); // The pseudo instruction is gone now.
   return BB;
 }
 
 static MachineBasicBlock *emitBuildPairF64Pseudo(MachineInstr &MI,
-                                                 MachineBasicBlock *BB) {
+                                                 MachineBasicBlock *BB,
+                                                 const RISCVSubtarget &Subtarget) {
   assert(MI.getOpcode() == RISCV::BuildPairF64Pseudo &&
          "Unexpected instruction");
 
   MachineFunction &MF = *BB->getParent();
   DebugLoc DL = MI.getDebugLoc();
   const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
   const TargetRegisterInfo *RI = MF.getSubtarget().getRegisterInfo();
   Register DstReg = MI.getOperand(0).getReg();
   Register LoReg = MI.getOperand(1).getReg();
   Register HiReg = MI.getOperand(2).getReg();
+  if (Subtarget.hasStdExtD() && Subtarget.hasStdExtZfa() &&
+      !Subtarget.is64Bit()) {
+    BuildMI(*BB, MI, DL, TII.get(RISCV::FMVP_D_X), DstReg)
+        .addReg(LoReg)
+        .addReg(HiReg);
+    MI.eraseFromParent();
+    return BB;
+  }
+
   const TargetRegisterClass *DstRC = &RISCV::FPR64RegClass;
   int FI = MF.getInfo<RISCVMachineFunctionInfo>()->getMoveF64FrameIndex(MF);
 
   MachinePointerInfo MPI = MachinePointerInfo::getFixedStack(MF, FI);
   MachineMemOperand *MMOLo =
       MF.getMachineMemOperand(MPI, MachineMemOperand::MOStore, 4, Align(8));
   MachineMemOperand *MMOHi = MF.getMachineMemOperand(
       MPI.getWithOffset(4), MachineMemOperand::MOStore, 4, Align(8));
assert(!Subtarget.is64Bit() &&
            "ReadCycleWrite is only to be used on riscv32");
     return emitReadCycleWidePseudo(MI, BB);
   case RISCV::Select_GPR_Using_CC_GPR:
   case RISCV::Select_FPR16_Using_CC_GPR:
   case RISCV::Select_FPR32_Using_CC_GPR:
   case RISCV::Select_FPR64_Using_CC_GPR:
     return emitSelectPseudo(MI, BB, Subtarget);
   case RISCV::BuildPairF64Pseudo:
-    return emitBuildPairF64Pseudo(MI, BB);
+    return emitBuildPairF64Pseudo(MI, BB, Subtarget);
   case RISCV::SplitF64Pseudo:
-    return emitSplitF64Pseudo(MI, BB);
+    return emitSplitF64Pseudo(MI, BB, Subtarget);
   case RISCV::PseudoQuietFLE_H:
     return emitQuietFCMP(MI, BB, RISCV::FLE_H, RISCV::FEQ_H, Subtarget);
   case RISCV::PseudoQuietFLT_H:
     return emitQuietFCMP(MI, BB, RISCV::FLT_H, RISCV::FEQ_H, Subtarget);
   case RISCV::PseudoQuietFLE_S:
     return emitQuietFCMP(MI, BB, RISCV::FLE_S, RISCV::FEQ_S, Subtarget);
   case RISCV::PseudoQuietFLT_S:
     return emitQuietFCMP(MI, BB, RISCV::FLT_S, RISCV::FEQ_S, Subtarget);

llvm/lib/Target/RISCV/RISCVInstrInfoZfa.td

 def FLEQ_D : FPCmp_rr<0b1010001, 0b100, "fleq.d", FPR64, /*Commutable*/ 1>;
 } // Predicates = [HasStdExtZfa, HasStdExtD]
 
 let Predicates = [HasStdExtZfa, HasStdExtD, IsRV32] in {
 def FMVH_X_D : FPUnaryOp_r<0b1110001, 0b00001, 0b000, GPR, FPR64, "fmvh.x.d">,
                Sched<[WriteFMovF32ToI32, ReadFMovF32ToI32]>;
 def FMVP_D_X : FPBinaryOp_rr<0b1011001, 0b000, FPR64, GPR, "fmvp.d.x">,
                Sched<[WriteFMovI32ToF32, ReadFMovI32ToF32]>;
+let isCodeGenOnly = 1, mayRaiseFPException = 0 in
+def FMV_X_W_FPR64 : FPUnaryOp_r<0b1110000, 0b00000, 0b000, GPR, FPR64,
+                                "fmv.x.w">,
+                    Sched<[WriteFMovF32ToI32, ReadFMovF32ToI32]>;
 } // Predicates = [HasStdExtZfa, HasStdExtD, IsRV32]
 
 let Predicates = [HasStdExtZfa, HasStdExtZfh] in {
 def FMINM_H: FPALU_rr<0b0010110, 0b010, "fminm.h", FPR16, /*Commutable*/ 1>;
 def FMAXM_H: FPALU_rr<0b0010110, 0b011, "fmaxm.h", FPR16, /*Commutable*/ 1>;
 
 def FROUND_H : FPUnaryOp_r_frm<0b0100010, 0b00100, FPR16, FPR16, "fround.h">;
 def FROUNDNX_H : FPUnaryOp_r_frm<0b0100010, 0b00101, FPR16, FPR16, "froundnx.h">;
 
 def FLTQ_H : FPCmp_rr<0b1010010, 0b101, "fltq.h", FPR16, /*Commutable*/ 1>;
 def FLEQ_H : FPCmp_rr<0b1010010, 0b100, "fleq.h", FPR16, /*Commutable*/ 1>;
 } // Predicates = [HasStdExtZfa, HasStdExtZfh]
+
+
+//===----------------------------------------------------------------------===//
+// Codegen patterns
+//===----------------------------------------------------------------------===//
+
+let Predicates = [HasStdExtZfa] in {
+def: PatFprFpr<fminimum, FMINM_S, FPR32>;
+def: PatFprFpr<fmaximum, FMAXM_S, FPR32>;
+
+// frint rounds according to the current rounding mode and detects
+// inexact conditions.
+def: Pat<(any_frint FPR32 : $rs1), (FROUNDNX_S FPR32 : $rs1, 0b111)>;
+
+// fnearbyint is like frint but does not detect inexact conditions.
+def: Pat<(any_fnearbyint FPR32 : $rs1), (FROUND_S FPR32 : $rs1, 0b111)>;
+
+def: Pat<(any_fround FPR32 : $rs1), (FROUND_S FPR32 : $rs1, 0b100)>;
+def: Pat<(any_ffloor FPR32 : $rs1), (FROUND_S FPR32 : $rs1, 0b011)>;
+def: Pat<(any_fceil FPR32 : $rs1), (FROUND_S FPR32 : $rs1, 0b010)>;
+def: Pat<(any_ftrunc FPR32 : $rs1), (FROUND_S FPR32 : $rs1, 0b001)>;
+
+def: PatSetCC<FPR32, strict_fsetcc, SETLT, FLTQ_S>;
+def: PatSetCC<FPR32, strict_fsetcc, SETOLT, FLTQ_S>;
+def: PatSetCC<FPR32, strict_fsetcc, SETLE, FLEQ_S>;
+def: PatSetCC<FPR32, strict_fsetcc, SETOLE, FLEQ_S>;
+} // Predicates = [HasStdExtZfa]
+
+let Predicates = [HasStdExtZfa, HasStdExtD] in {
+def: PatFprFpr<fminimum, FMINM_D, FPR64>;
+def: PatFprFpr<fmaximum, FMAXM_D, FPR64>;
+
+// frint rounds according to the current rounding mode and detects
+// inexact conditions.
+def: Pat<(any_frint FPR64 : $rs1), (FROUNDNX_D FPR64 : $rs1, 0b111)>;
+
+// fnearbyint is like frint but does not detect inexact conditions.
+def: Pat<(any_fnearbyint FPR64 : $rs1), (FROUND_D FPR64 : $rs1, 0b111)>;
+
+def: Pat<(any_fround FPR64 : $rs1), (FROUND_D FPR64 : $rs1, 0b100)>;
+def: Pat<(any_froundeven FPR64 : $rs1), (FROUND_D FPR64 : $rs1, 0b000)>;
+def: Pat<(any_ffloor FPR64 : $rs1), (FROUND_D FPR64 : $rs1, 0b011)>;
+def: Pat<(any_fceil FPR64 : $rs1), (FROUND_D FPR64 : $rs1, 0b010)>;
+def: Pat<(any_ftrunc FPR64 : $rs1), (FROUND_D FPR64 : $rs1, 0b001)>;
+
+def: PatSetCC<FPR64, strict_fsetcc, SETLT, FLTQ_D>;
+def: PatSetCC<FPR64, strict_fsetcc, SETOLT, FLTQ_D>;
+def: PatSetCC<FPR64, strict_fsetcc, SETLE, FLEQ_D>;
+def: PatSetCC<FPR64, strict_fsetcc, SETOLE, FLEQ_D>;
+} // Predicates = [HasStdExtZfa, HasStdExtD]
+
+let Predicates = [HasStdExtZfa, HasStdExtZfh] in {
+def: PatFprFpr<fminimum, FMINM_H, FPR16>;
+def: PatFprFpr<fmaximum, FMAXM_H, FPR16>;
+
+// frint rounds according to the current rounding mode and detects
+// inexact conditions.
+def: Pat<(any_frint FPR16 : $rs1), (FROUNDNX_H FPR16 : $rs1, 0b111)>;
+
+// fnearbyint is like frint but does not detect inexact conditions.
+def: Pat<(any_fnearbyint FPR16 : $rs1), (FROUND_H FPR16 : $rs1, 0b111)>;
+
+def: Pat<(any_fround FPR16 : $rs1), (FROUND_H FPR16 : $rs1, 0b100)>;
+def: Pat<(any_froundeven FPR16 : $rs1), (FROUND_H FPR16 : $rs1, 0b000)>;
+def: Pat<(any_ffloor FPR16 : $rs1), (FROUND_H FPR16 : $rs1, 0b011)>;
+def: Pat<(any_fceil FPR16 : $rs1), (FROUND_H FPR16 : $rs1, 0b010)>;
+def: Pat<(any_ftrunc FPR16 : $rs1), (FROUND_H FPR16 : $rs1, 0b001)>;
+
+def: PatSetCC<FPR16, strict_fsetcc, SETLT, FLTQ_H>;
+def: PatSetCC<FPR16, strict_fsetcc, SETOLT, FLTQ_H>;
+def: PatSetCC<FPR16, strict_fsetcc, SETLE, FLEQ_H>;
+def: PatSetCC<FPR16, strict_fsetcc, SETOLE, FLEQ_H>;
+} // Predicates = [HasStdExtZfa, HasStdExtZfh]

llvm/test/CodeGen/RISCV/double-zfa.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -target-abi ilp32d -mattr=+experimental-zfa,+d < %s \
+; RUN:     | FileCheck --check-prefixes=CHECK,RV32IDZFA %s
+; RUN: llc -mtriple=riscv64 -target-abi lp64d -mattr=+experimental-zfa,+d < %s \
+; RUN:     | FileCheck --check-prefixes=CHECK,RV64DZFA %s
+
+declare double @llvm.minimum.f64(double, double)
+
+define double @fminm_d(double %a, double %b) nounwind {
+; CHECK-LABEL: fminm_d:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fminm.d fa0, fa0, fa1
+; CHECK-NEXT:    ret
+  %1 = call double @llvm.minimum.f64(double %a, double %b)
+  ret double %1
+}
+
+declare double @llvm.maximum.f64(double, double)
+
+define double @fmaxm_d(double %a, double %b) nounwind {
+; CHECK-LABEL: fmaxm_d:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fmaxm.d fa0, fa0, fa1
+; CHECK-NEXT:    ret
+  %1 = call double @llvm.maximum.f64(double %a, double %b)
+  ret double %1
+}
+
+define double @fround_d_1(double %a) nounwind {
+; CHECK-LABEL: fround_d_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fround.d fa0, fa0, rmm
+; CHECK-NEXT:    ret
+  %call = tail call double @round(double %a) nounwind readnone
+  ret double %call
+}
+
+declare double @round(double) nounwind readnone
+
+
+define double @fround_d_2(double %a) nounwind {
+; CHECK-LABEL: fround_d_2:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fround.d fa0, fa0, rup
+; CHECK-NEXT:    ret
+  %call = tail call double @floor(double %a) nounwind readnone
+  ret double %call
+}
+
+declare double @floor(double) nounwind readnone
+
+
+define double @fround_d_3(double %a) nounwind {
+; CHECK-LABEL: fround_d_3:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fround.d fa0, fa0, rdn
+; CHECK-NEXT:    ret
+  %call = tail call double @ceil(double %a) nounwind readnone
+  ret double %call
+}
+
+declare double @ceil(double) nounwind readnone
+
+
+define double @fround_d_4(double %a) nounwind {
+; CHECK-LABEL: fround_d_4:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fround.d fa0, fa0, rtz
+; CHECK-NEXT:    ret
+  %call = tail call double @trunc(double %a) nounwind readnone
+  ret double %call
+}
+
+declare double @trunc(double) nounwind readnone
+
+
+define double @fround_d_5(double %a) nounwind {
+; CHECK-LABEL: fround_d_5:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fround.d fa0, fa0
+; CHECK-NEXT:    ret
+  %call = tail call double @nearbyint(double %a) nounwind readnone
+  ret double %call
+}
+
+declare double @nearbyint(double) nounwind readnone
+
+
+define double @froundnx_d(double %a) nounwind {
+; CHECK-LABEL: froundnx_d:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    froundnx.d fa0, fa0
+; CHECK-NEXT:    ret
+  %call = tail call double @rint(double %a) nounwind readnone
+  ret double %call
+}
+
+declare double @rint(double) nounwind readnone
+
+declare i1 @llvm.experimental.constrained.fcmp.f64(double, double, metadata, metadata)
+
+define i32 @fcmp_olt_q(double %a, double %b) nounwind strictfp {
+; CHECK-LABEL: fcmp_olt_q:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fltq.d a0, fa0, fa1
+; CHECK-NEXT:    ret
+  %1 = call i1 @llvm.experimental.constrained.fcmp.f64(double %a, double %b, metadata !"olt", metadata !"fpexcept.strict") strictfp
+  %2 = zext i1 %1 to i32
+  ret i32 %2
+}
+
+define i32 @fcmp_ole_q(double %a, double %b) nounwind strictfp {
+; CHECK-LABEL: fcmp_ole_q:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fleq.d a0, fa0, fa1
+; CHECK-NEXT:    ret
+  %1 = call i1 @llvm.experimental.constrained.fcmp.f64(double %a, double %b, metadata !"ole", metadata !"fpexcept.strict") strictfp
+  %2 = zext i1 %1 to i32
+  ret i32 %2
+}
+
+define i64 @fmvh_x_d(double %fa) {
+; RV32IDZFA-LABEL: fmvh_x_d:
+; RV32IDZFA:       # %bb.0:
+; RV32IDZFA-NEXT:    fmv.x.w a0, fa0
+; RV32IDZFA-NEXT:    fmvh.x.d a1, fa0
+; RV32IDZFA-NEXT:    ret
+;
+; RV64DZFA-LABEL: fmvh_x_d:
+; RV64DZFA:       # %bb.0:
+; RV64DZFA-NEXT:    fmv.x.d a0, fa0
+; RV64DZFA-NEXT:    ret
+  %i = bitcast double %fa to i64
+  ret i64 %i
+}
+
+define double @fmvp_d_x(i64 %a) {
+; RV32IDZFA-LABEL: fmvp_d_x:
+; RV32IDZFA:       # %bb.0:
+; RV32IDZFA-NEXT:    fmvp.d.x fa0, a0, a1
+; RV32IDZFA-NEXT:    ret
+;
+; RV64DZFA-LABEL: fmvp_d_x:
+; RV64DZFA:       # %bb.0:
+; RV64DZFA-NEXT:    fmv.d.x fa0, a0
+; RV64DZFA-NEXT:    ret
+  %or = bitcast i64 %a to double
+  ret double %or
+}

llvm/test/CodeGen/RISCV/float-zfa.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -target-abi ilp32f -mattr=+experimental-zfa < %s \
+; RUN:     | FileCheck %s
+; RUN: llc -mtriple=riscv64 -target-abi lp64f -mattr=+experimental-zfa < %s \
+; RUN:     | FileCheck %s
+
+declare float @llvm.minimum.f32(float, float)
+
+define float @fminm_s(float %a, float %b) nounwind {
+; CHECK-LABEL: fminm_s:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fminm.s fa0, fa0, fa1
+; CHECK-NEXT:    ret
+  %1 = call float @llvm.minimum.f32(float %a, float %b)
+  ret float %1
+}
+
+declare float @llvm.maximum.f32(float, float)
+
+define float @fmaxm_s(float %a, float %b) nounwind {
+; CHECK-LABEL: fmaxm_s:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fmaxm.s fa0, fa0, fa1
+; CHECK-NEXT:    ret
+  %1 = call float @llvm.maximum.f32(float %a, float %b)
+  ret float %1
+}
+
+
+define float @fround_s_1(float %a) nounwind {
+; CHECK-LABEL: fround_s_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fround.s fa0, fa0, rmm
+; CHECK-NEXT:    ret
+  %call = tail call float @roundf(float %a) nounwind readnone
+  ret float %call
+}
+
+declare float @roundf(float) nounwind readnone
+
+
+define float @fround_s_2(float %a) nounwind {
+; CHECK-LABEL: fround_s_2:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fround.s fa0, fa0, rup
+; CHECK-NEXT:    ret
+  %call = tail call float @floorf(float %a) nounwind readnone
+  ret float %call
+}
+
+declare float @floorf(float) nounwind readnone
+
+
+define float @fround_s_3(float %a) nounwind {
+; CHECK-LABEL: fround_s_3:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fround.s fa0, fa0, rdn
+; CHECK-NEXT:    ret
+  %call = tail call float @ceilf(float %a) nounwind readnone
+  ret float %call
+}
+
+declare float @ceilf(float) nounwind readnone
+
+
+define float @fround_s_4(float %a) nounwind {
+; CHECK-LABEL: fround_s_4:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fround.s fa0, fa0, rtz
+; CHECK-NEXT:    ret
+  %call = tail call float @truncf(float %a) nounwind readnone
+  ret float %call
+}
+
+declare float @truncf(float) nounwind readnone
+
+
+define float @fround_s_5(float %a) nounwind {
+; CHECK-LABEL: fround_s_5:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fround.s fa0, fa0
+; CHECK-NEXT:    ret
+  %call = tail call float @nearbyintf(float %a) nounwind readnone
+  ret float %call
+}
+
+declare float @nearbyintf(float) nounwind readnone
+
+
+define float @froundnx_s(float %a) nounwind {
+; CHECK-LABEL: froundnx_s:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    froundnx.s fa0, fa0
+; CHECK-NEXT:    ret
+  %call = tail call float @rintf(float %a) nounwind readnone
+  ret float %call
+}
+
+declare float @rintf(float) nounwind readnone
+
+declare i1 @llvm.experimental.constrained.fcmp.f32(float, float, metadata, metadata)
+
+define i32 @fcmp_olt_q(float %a, float %b) nounwind strictfp {
+; CHECK-LABEL: fcmp_olt_q:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fltq.s a0, fa0, fa1
+; CHECK-NEXT:    ret
+  %1 = call i1 @llvm.experimental.constrained.fcmp.f32(float %a, float %b, metadata !"olt", metadata !"fpexcept.strict") strictfp
+  %2 = zext i1 %1 to i32
+  ret i32 %2
+}
+
+define i32 @fcmp_ole_q(float %a, float %b) nounwind strictfp {
+; CHECK-LABEL: fcmp_ole_q:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fleq.s a0, fa0, fa1
+; CHECK-NEXT:    ret
+  %1 = call i1 @llvm.experimental.constrained.fcmp.f32(float %a, float %b, metadata !"ole", metadata !"fpexcept.strict") strictfp
+  %2 = zext i1 %1 to i32
+  ret i32 %2
+}

llvm/test/CodeGen/RISCV/half-zfa.ll

+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
+; RUN: llc -mtriple=riscv32 -target-abi ilp32f -mattr=+experimental-zfa,+zfh < %s \
+; RUN:     | FileCheck %s
+; RUN: llc -mtriple=riscv64 -target-abi lp64f -mattr=+experimental-zfa,+zfh < %s \
+; RUN:     | FileCheck %s
+
+declare half @llvm.minimum.f16(half, half)
+
+define half @fminm_h(half %a, half %b) nounwind {
+; CHECK-LABEL: fminm_h:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fminm.h fa0, fa0, fa1
+; CHECK-NEXT:    ret
+  %1 = call half @llvm.minimum.f16(half %a, half %b)
+  ret half %1
+}
+
+declare half @llvm.maximum.f16(half, half)
+
+define half @fmaxm_h(half %a, half %b) nounwind {
+; CHECK-LABEL: fmaxm_h:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fmaxm.h fa0, fa0, fa1
+; CHECK-NEXT:    ret
+  %1 = tail call half @llvm.maximum.f16(half %a, half %b)
+  ret half %1
+}
+
+define half @fround_h_1(half %a) nounwind {
+; CHECK-LABEL: fround_h_1:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fround.h fa0, fa0, rmm
+; CHECK-NEXT:    ret
+  %call = tail call half @llvm.round.f16(half %a) nounwind readnone
+  ret half %call
+}
+
+declare half @llvm.round.f16(half) nounwind readnone
+
+
+define half @fround_h_2(half %a) nounwind {
+; CHECK-LABEL: fround_h_2:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fround.h fa0, fa0, rup
+; CHECK-NEXT:    ret
+  %call = tail call half @llvm.floor.f16(half %a) nounwind readnone
+  ret half %call
+}
+
+declare half @llvm.floor.f16(half) nounwind readnone
+
+
+define half @fround_h_3(half %a) nounwind {
+; CHECK-LABEL: fround_h_3:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fround.h fa0, fa0, rdn
+; CHECK-NEXT:    ret
+  %call = tail call half @llvm.ceil.f16(half %a) nounwind readnone
+  ret half %call
+}
+
+declare half @llvm.ceil.f16(half) nounwind readnone
+
+
+define half @fround_h_4(half %a) nounwind {
+; CHECK-LABEL: fround_h_4:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fround.h fa0, fa0, rtz
+; CHECK-NEXT:    ret
+  %call = tail call half @llvm.trunc.f16(half %a) nounwind readnone
+  ret half %call
+}
+
+declare half @llvm.trunc.f16(half) nounwind readnone
+
+
+define half @fround_h_5(half %a) nounwind {
+; CHECK-LABEL: fround_h_5:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fround.h fa0, fa0
+; CHECK-NEXT:    ret
+  %call = tail call half @llvm.nearbyint.f16(half %a) nounwind readnone
+  ret half %call
+}
+
+declare half @llvm.nearbyint.f16(half) nounwind readnone
+
+
+define half @froundnx_h(half %a) nounwind {
+; CHECK-LABEL: froundnx_h:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    froundnx.h fa0, fa0
+; CHECK-NEXT:    ret
+  %call = tail call half @llvm.rint.f16(half %a) nounwind readnone
+  ret half %call
+}
+
+declare half @llvm.rint.f16(half) nounwind readnone
+
+declare i1 @llvm.experimental.constrained.fcmp.f16(half, half, metadata, metadata)
+
+define i32 @fcmp_olt_q(half %a, half %b) nounwind strictfp {
+; CHECK-LABEL: fcmp_olt_q:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fltq.h a0, fa0, fa1
+; CHECK-NEXT:    ret
+  %1 = call i1 @llvm.experimental.constrained.fcmp.f16(half %a, half %b, metadata !"olt", metadata !"fpexcept.strict") strictfp
+  %2 = zext i1 %1 to i32
+  ret i32 %2
+}
+
+define i32 @fcmp_ole_q(half %a, half %b) nounwind strictfp {
+; CHECK-LABEL: fcmp_ole_q:
+; CHECK:       # %bb.0:
+; CHECK-NEXT:    fleq.h a0, fa0, fa1
+; CHECK-NEXT:    ret
+  %1 = call i1 @llvm.experimental.constrained.fcmp.f16(half %a, half %b, metadata !"ole", metadata !"fpexcept.strict") strictfp
+  %2 = zext i1 %1 to i32
+  ret i32 %2
+}