[RISCV] Add max/min builtins to generate some Zfa instructions from C-code

[joshua-arch1]

Summary

To generate FMINM/FMAXM instructions in https://reviews.llvm.org/D143982, we need to use llvm intrinsics in IR files. Now I custom some corresponding builtins in BuiltinsRISCV.def to make sure these instructions can be generated from C codes.
In this implemention, crash mentioned in https://reviews.llvm.org/D144843 will not occur. These builtins can only work in riscv with specific extension.

[craig.topper]

clang/include/clang/Basic/BuiltinsRISCV.def

83

RISC-V builtins should use RISC-V instruction names

clang/lib/CodeGen/CGBuiltin.cpp

2365

This needs to be in the EmitRISCVBuiltinExpr function.

[craig.topper]

clang/include/clang/Basic/BuiltinsRISCV.def

85

as noted in Builtins.def, the letter for _Float16 is 'x' not 'h'

//  x -> half (_Float16)

[joshua-arch1]

Update builtin names using corresponding RISCV instructions.

[craig.topper]

clang/include/clang/Basic/BuiltinsRISCV.def

84

Should we use _s to match the instruction name, fmaxm.s?

clang/lib/CodeGen/CGBuiltin.cpp

2365

This is still in the wrong place

[joshua-arch1]

Update builtin_riscv_fmaxm_f/builtin_riscv_fminm_f to builtin_riscv_fmaxm_s/builtin_riscv_fminm_s

[craig.topper]

clang/lib/CodeGen/CGBuiltin.cpp

2366

This needs to be in the RISC-V specific function EmitRISCVBuiltinExpr.

clang/include/clang/Basic/BuiltinsRISCV.def

 // Zksed extension
 TARGET_BUILTIN(__builtin_riscv_sm4ed, "LiLiLiIUc", "nc", "zksed")
 TARGET_BUILTIN(__builtin_riscv_sm4ks, "LiLiLiIUc", "nc", "zksed")
 
 // Zksh extension
 TARGET_BUILTIN(__builtin_riscv_sm3p0, "LiLi", "nc", "zksh")
 TARGET_BUILTIN(__builtin_riscv_sm3p1, "LiLi", "nc", "zksh")
 
+// Zfa extension
+TARGET_BUILTIN(__builtin_riscv_fmaxm_d, "ddd", "Fnc", "d,experimental-zfa")
+TARGET_BUILTIN(__builtin_riscv_fmaxm_s, "fff", "Fnc", "experimental-zfa")
+TARGET_BUILTIN(__builtin_riscv_fmaxm_h, "xxx", "Fnc", "zfh,experimental-zfa")
+TARGET_BUILTIN(__builtin_riscv_fminm_d, "ddd", "Fnc", "d,experimental-zfa")
+TARGET_BUILTIN(__builtin_riscv_fminm_s, "fff", "Fnc", "experimental-zfa")
+TARGET_BUILTIN(__builtin_riscv_fminm_h, "xxx", "Fnc", "zfh,experimental-zfa")
+
 #undef BUILTIN
 #undef TARGET_BUILTIN

clang/lib/CodeGen/CGBuiltin.cpp

if (FD->hasAttr<ConstAttr>() ||
     case Builtin::BI__builtin_fminf:
     case Builtin::BI__builtin_fminf16:
     case Builtin::BI__builtin_fminl:
     case Builtin::BI__builtin_fminf128:
       return RValue::get(emitBinaryMaybeConstrainedFPBuiltin(*this, E,
                                    Intrinsic::minnum,
                                    Intrinsic::experimental_constrained_minnum));
 
+    // Zfa
+    case RISCV::BI__builtin_riscv_fmaxm_d:
+    case RISCV::BI__builtin_riscv_fmaxm_s:
+    case RISCV::BI__builtin_riscv_fmaxm_h:
+      return RValue::get(emitBinaryMaybeConstrainedFPBuiltin(*this, E,
+                                   Intrinsic::maximum,
+                                   Intrinsic::experimental_constrained_maximum));
+
+    case RISCV::BI__builtin_riscv_fminm_d:
+    case RISCV::BI__builtin_riscv_fminm_s:
+    case RISCV::BI__builtin_riscv_fminm_h:
+    return RValue::get(emitBinaryMaybeConstrainedFPBuiltin(*this, E,
+                                 Intrinsic::minimum,
+                                 Intrinsic::experimental_constrained_minimum));
+
     // fmod() is a special-case. It maps to the frem instruction rather than an
     // LLVM intrinsic.
     case Builtin::BIfmod:
     case Builtin::BIfmodf:
     case Builtin::BIfmodl:
     case Builtin::BI__builtin_fmod:
     case Builtin::BI__builtin_fmodf:
     case Builtin::BI__builtin_fmodf16:

clang/test/CodeGen/RISCV/zfa-intrinsics.c

+// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
+// RUN: %clang_cc1 -triple riscv64 -target-feature +d -target-feature +zfh -target-feature +experimental-zfa -emit-llvm %s -o - \
+// RUN:     | FileCheck %s  -check-prefix=RV64ZFA
+// RUN: %clang_cc1 -triple riscv32 -target-feature +d -target-feature +zfh -target-feature +experimental-zfa -emit-llvm %s -o - \
+// RUN:     | FileCheck %s  -check-prefix=RV32ZFA
+
+// RV64ZFA-LABEL: @fmaxm_s(
+// RV64ZFA-NEXT:  entry:
+// RV64ZFA-NEXT:    [[A_ADDR:%.*]] = alloca float, align 4
+// RV64ZFA-NEXT:    [[B_ADDR:%.*]] = alloca float, align 4
+// RV64ZFA-NEXT:    store float [[A:%.*]], ptr [[A_ADDR]], align 4
+// RV64ZFA-NEXT:    store float [[B:%.*]], ptr [[B_ADDR]], align 4
+// RV64ZFA-NEXT:    [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
+// RV64ZFA-NEXT:    [[TMP1:%.*]] = load float, ptr [[B_ADDR]], align 4
+// RV64ZFA-NEXT:    [[TMP2:%.*]] = call float @llvm.maximum.f32(float [[TMP0]], float [[TMP1]])
+// RV64ZFA-NEXT:    ret float [[TMP2]]
+//
+// RV32ZFA-LABEL: @fmaxm_s(
+// RV32ZFA-NEXT:  entry:
+// RV32ZFA-NEXT:    [[A_ADDR:%.*]] = alloca float, align 4
+// RV32ZFA-NEXT:    [[B_ADDR:%.*]] = alloca float, align 4
+// RV32ZFA-NEXT:    store float [[A:%.*]], ptr [[A_ADDR]], align 4
+// RV32ZFA-NEXT:    store float [[B:%.*]], ptr [[B_ADDR]], align 4
+// RV32ZFA-NEXT:    [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
+// RV32ZFA-NEXT:    [[TMP1:%.*]] = load float, ptr [[B_ADDR]], align 4
+// RV32ZFA-NEXT:    [[TMP2:%.*]] = call float @llvm.maximum.f32(float [[TMP0]], float [[TMP1]])
+// RV32ZFA-NEXT:    ret float [[TMP2]]
+//
+float fmaxm_s(float a, float b)
+{
+  return __builtin_riscv_fmaxm_s(a, b);
+}
+
+// RV64ZFA-LABEL: @fminm_s(
+// RV64ZFA-NEXT:  entry:
+// RV64ZFA-NEXT:    [[A_ADDR:%.*]] = alloca float, align 4
+// RV64ZFA-NEXT:    [[B_ADDR:%.*]] = alloca float, align 4
+// RV64ZFA-NEXT:    store float [[A:%.*]], ptr [[A_ADDR]], align 4
+// RV64ZFA-NEXT:    store float [[B:%.*]], ptr [[B_ADDR]], align 4
+// RV64ZFA-NEXT:    [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
+// RV64ZFA-NEXT:    [[TMP1:%.*]] = load float, ptr [[B_ADDR]], align 4
+// RV64ZFA-NEXT:    [[TMP2:%.*]] = call float @llvm.minimum.f32(float [[TMP0]], float [[TMP1]])
+// RV64ZFA-NEXT:    ret float [[TMP2]]
+//
+// RV32ZFA-LABEL: @fminm_s(
+// RV32ZFA-NEXT:  entry:
+// RV32ZFA-NEXT:    [[A_ADDR:%.*]] = alloca float, align 4
+// RV32ZFA-NEXT:    [[B_ADDR:%.*]] = alloca float, align 4
+// RV32ZFA-NEXT:    store float [[A:%.*]], ptr [[A_ADDR]], align 4
+// RV32ZFA-NEXT:    store float [[B:%.*]], ptr [[B_ADDR]], align 4
+// RV32ZFA-NEXT:    [[TMP0:%.*]] = load float, ptr [[A_ADDR]], align 4
+// RV32ZFA-NEXT:    [[TMP1:%.*]] = load float, ptr [[B_ADDR]], align 4
+// RV32ZFA-NEXT:    [[TMP2:%.*]] = call float @llvm.minimum.f32(float [[TMP0]], float [[TMP1]])
+// RV32ZFA-NEXT:    ret float [[TMP2]]
+//
+float fminm_s(float a, float b)
+{
+  return __builtin_riscv_fminm_s(a, b);
+}
+
+// RV64ZFA-LABEL: @fmaxm_d(
+// RV64ZFA-NEXT:  entry:
+// RV64ZFA-NEXT:    [[A_ADDR:%.*]] = alloca double, align 8
+// RV64ZFA-NEXT:    [[B_ADDR:%.*]] = alloca double, align 8
+// RV64ZFA-NEXT:    store double [[A:%.*]], ptr [[A_ADDR]], align 8
+// RV64ZFA-NEXT:    store double [[B:%.*]], ptr [[B_ADDR]], align 8
+// RV64ZFA-NEXT:    [[TMP0:%.*]] = load double, ptr [[A_ADDR]], align 8
+// RV64ZFA-NEXT:    [[TMP1:%.*]] = load double, ptr [[B_ADDR]], align 8
+// RV64ZFA-NEXT:    [[TMP2:%.*]] = call double @llvm.maximum.f64(double [[TMP0]], double [[TMP1]])
+// RV64ZFA-NEXT:    ret double [[TMP2]]
+//
+// RV32ZFA-LABEL: @fmaxm_d(
+// RV32ZFA-NEXT:  entry:
+// RV32ZFA-NEXT:    [[A_ADDR:%.*]] = alloca double, align 8
+// RV32ZFA-NEXT:    [[B_ADDR:%.*]] = alloca double, align 8
+// RV32ZFA-NEXT:    store double [[A:%.*]], ptr [[A_ADDR]], align 8
+// RV32ZFA-NEXT:    store double [[B:%.*]], ptr [[B_ADDR]], align 8
+// RV32ZFA-NEXT:    [[TMP0:%.*]] = load double, ptr [[A_ADDR]], align 8
+// RV32ZFA-NEXT:    [[TMP1:%.*]] = load double, ptr [[B_ADDR]], align 8
+// RV32ZFA-NEXT:    [[TMP2:%.*]] = call double @llvm.maximum.f64(double [[TMP0]], double [[TMP1]])
+// RV32ZFA-NEXT:    ret double [[TMP2]]
+//
+double fmaxm_d(double a, double b)
+{
+  return __builtin_riscv_fmaxm_d(a, b);
+}
+
+// RV64ZFA-LABEL: @fminm_d(
+// RV64ZFA-NEXT:  entry:
+// RV64ZFA-NEXT:    [[A_ADDR:%.*]] = alloca double, align 8
+// RV64ZFA-NEXT:    [[B_ADDR:%.*]] = alloca double, align 8
+// RV64ZFA-NEXT:    store double [[A:%.*]], ptr [[A_ADDR]], align 8
+// RV64ZFA-NEXT:    store double [[B:%.*]], ptr [[B_ADDR]], align 8
+// RV64ZFA-NEXT:    [[TMP0:%.*]] = load double, ptr [[A_ADDR]], align 8
+// RV64ZFA-NEXT:    [[TMP1:%.*]] = load double, ptr [[B_ADDR]], align 8
+// RV64ZFA-NEXT:    [[TMP2:%.*]] = call double @llvm.minimum.f64(double [[TMP0]], double [[TMP1]])
+// RV64ZFA-NEXT:    ret double [[TMP2]]
+//
+// RV32ZFA-LABEL: @fminm_d(
+// RV32ZFA-NEXT:  entry:
+// RV32ZFA-NEXT:    [[A_ADDR:%.*]] = alloca double, align 8
+// RV32ZFA-NEXT:    [[B_ADDR:%.*]] = alloca double, align 8
+// RV32ZFA-NEXT:    store double [[A:%.*]], ptr [[A_ADDR]], align 8
+// RV32ZFA-NEXT:    store double [[B:%.*]], ptr [[B_ADDR]], align 8
+// RV32ZFA-NEXT:    [[TMP0:%.*]] = load double, ptr [[A_ADDR]], align 8
+// RV32ZFA-NEXT:    [[TMP1:%.*]] = load double, ptr [[B_ADDR]], align 8
+// RV32ZFA-NEXT:    [[TMP2:%.*]] = call double @llvm.minimum.f64(double [[TMP0]], double [[TMP1]])
+// RV32ZFA-NEXT:    ret double [[TMP2]]
+//
+double fminm_d(double a, double b)
+{
+  return __builtin_riscv_fminm_d(a, b);
+}
+
+// RV64ZFA-LABEL: @fmaxm_h(
+// RV64ZFA-NEXT:  entry:
+// RV64ZFA-NEXT:    [[A_ADDR:%.*]] = alloca half, align 2
+// RV64ZFA-NEXT:    [[B_ADDR:%.*]] = alloca half, align 2
+// RV64ZFA-NEXT:    store half [[A:%.*]], ptr [[A_ADDR]], align 2
+// RV64ZFA-NEXT:    store half [[B:%.*]], ptr [[B_ADDR]], align 2
+// RV64ZFA-NEXT:    [[TMP0:%.*]] = load half, ptr [[A_ADDR]], align 2
+// RV64ZFA-NEXT:    [[TMP1:%.*]] = load half, ptr [[B_ADDR]], align 2
+// RV64ZFA-NEXT:    [[TMP2:%.*]] = call half @llvm.maximum.f16(half [[TMP0]], half [[TMP1]])
+// RV64ZFA-NEXT:    ret half [[TMP2]]
+//
+// RV32ZFA-LABEL: @fmaxm_h(
+// RV32ZFA-NEXT:  entry:
+// RV32ZFA-NEXT:    [[A_ADDR:%.*]] = alloca half, align 2
+// RV32ZFA-NEXT:    [[B_ADDR:%.*]] = alloca half, align 2
+// RV32ZFA-NEXT:    store half [[A:%.*]], ptr [[A_ADDR]], align 2
+// RV32ZFA-NEXT:    store half [[B:%.*]], ptr [[B_ADDR]], align 2
+// RV32ZFA-NEXT:    [[TMP0:%.*]] = load half, ptr [[A_ADDR]], align 2
+// RV32ZFA-NEXT:    [[TMP1:%.*]] = load half, ptr [[B_ADDR]], align 2
+// RV32ZFA-NEXT:    [[TMP2:%.*]] = call half @llvm.maximum.f16(half [[TMP0]], half [[TMP1]])
+// RV32ZFA-NEXT:    ret half [[TMP2]]
+//
+_Float16 fmaxm_h(_Float16 a, _Float16 b)
+{
+  return __builtin_riscv_fmaxm_h(a, b);
+}
+
+// RV64ZFA-LABEL: @fminm_h(
+// RV64ZFA-NEXT:  entry:
+// RV64ZFA-NEXT:    [[A_ADDR:%.*]] = alloca half, align 2
+// RV64ZFA-NEXT:    [[B_ADDR:%.*]] = alloca half, align 2
+// RV64ZFA-NEXT:    store half [[A:%.*]], ptr [[A_ADDR]], align 2
+// RV64ZFA-NEXT:    store half [[B:%.*]], ptr [[B_ADDR]], align 2
+// RV64ZFA-NEXT:    [[TMP0:%.*]] = load half, ptr [[A_ADDR]], align 2
+// RV64ZFA-NEXT:    [[TMP1:%.*]] = load half, ptr [[B_ADDR]], align 2
+// RV64ZFA-NEXT:    [[TMP2:%.*]] = call half @llvm.minimum.f16(half [[TMP0]], half [[TMP1]])
+// RV64ZFA-NEXT:    ret half [[TMP2]]
+//
+// RV32ZFA-LABEL: @fminm_h(
+// RV32ZFA-NEXT:  entry:
+// RV32ZFA-NEXT:    [[A_ADDR:%.*]] = alloca half, align 2
+// RV32ZFA-NEXT:    [[B_ADDR:%.*]] = alloca half, align 2
+// RV32ZFA-NEXT:    store half [[A:%.*]], ptr [[A_ADDR]], align 2
+// RV32ZFA-NEXT:    store half [[B:%.*]], ptr [[B_ADDR]], align 2
+// RV32ZFA-NEXT:    [[TMP0:%.*]] = load half, ptr [[A_ADDR]], align 2
+// RV32ZFA-NEXT:    [[TMP1:%.*]] = load half, ptr [[B_ADDR]], align 2
+// RV32ZFA-NEXT:    [[TMP2:%.*]] = call half @llvm.minimum.f16(half [[TMP0]], half [[TMP1]])
+// RV32ZFA-NEXT:    ret half [[TMP2]]
+//
+_Float16 fminm_h(_Float16 a, _Float16 b)
+{
+  return __builtin_riscv_fminm_h(a, b);
+}