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joshua-arch1 (Jun Sha)
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User Since
Jul 27 2020, 12:27 AM (106 w, 2 d)

Recent Activity

Thu, Aug 4

joshua-arch1 updated the diff for D131230: [RISCV] Setting small data limitation to zero for PIE.
Thu, Aug 4, 7:31 PM · Restricted Project
joshua-arch1 added reviewers for D131230: [RISCV] Setting small data limitation to zero for PIE: shiva0217, apazos.
Thu, Aug 4, 7:15 PM · Restricted Project
joshua-arch1 requested review of D131230: [RISCV] Setting small data limitation to zero for PIE.
Thu, Aug 4, 7:13 PM · Restricted Project

Jun 28 2022

joshua-arch1 added a comment to rG2de4f19ecdb2: [LSan][RISCV] Enable LSan for RISCV64.

It seems that only with this patch, LSAN cannot work for RISCV64.

Jun 28 2022, 6:57 PM

Jun 23 2022

joshua-arch1 added a comment to D87580: [RISCV][ASAN] support code for architecture-specific parts of asan.

There is a range of addresses where the kernel may place the main executable. It has been extended once in the past (ASLR). ASan mapping is a compile-time constant, so it must work with any location within that range. I suspect that for QEMU this range may be different.

Anyway, some architectures use dynamic shadow allocation at runtime. IMHO this is a much better solution, even if it costs some CPU cycles (5% or whatever).

Jun 23 2022, 8:34 PM · Restricted Project, Restricted Project
joshua-arch1 added a comment to D87580: [RISCV][ASAN] support code for architecture-specific parts of asan.

There is a range of addresses where the kernel may place the main executable. It has been extended once in the past (ASLR). ASan mapping is a compile-time constant, so it must work with any location within that range. I suspect that for QEMU this range may be different.

Anyway, some architectures use dynamic shadow allocation at runtime. IMHO this is a much better solution, even if it costs some CPU cycles (5% or whatever).

Jun 23 2022, 8:22 PM · Restricted Project, Restricted Project

Jun 19 2022

joshua-arch1 added a comment to D87580: [RISCV][ASAN] support code for architecture-specific parts of asan.
Jun 19 2022, 11:14 PM · Restricted Project, Restricted Project

Jun 15 2022

joshua-arch1 added a comment to D87580: [RISCV][ASAN] support code for architecture-specific parts of asan.
Jun 15 2022, 7:08 PM · Restricted Project, Restricted Project

Jun 14 2022

joshua-arch1 added a comment to D87580: [RISCV][ASAN] support code for architecture-specific parts of asan.

How is this work going? If you find the commit that led to this failure, maybe I can also help fix it.

I was going to reply earlier but then I ran into reproducibility issues. Long story short, I had reproduced the failure but during the bisection process it stopped reproducing. I'll provide more details when I can.

Jun 14 2022, 11:03 PM · Restricted Project, Restricted Project

Jun 12 2022

joshua-arch1 added a comment to D87580: [RISCV][ASAN] support code for architecture-specific parts of asan.

I have checked the satp register to convince myself that I was just running with sv39. I also spent a few hours debugging the up-to-date sanitizer code, but got nothing. Has anyone encounted with this error before?

Thanks for that work. I think I will be able to look into this around the end of this week or the start of the next one.

I've checked that indeed things are broken in main but they weren't broken with an older commit. I'll bisect and investigate this. My current RV64 setup is slow so the bisection will take a while.

Jun 12 2022, 6:56 PM · Restricted Project, Restricted Project

Jun 8 2022

joshua-arch1 added a comment to D87580: [RISCV][ASAN] support code for architecture-specific parts of asan.
Jun 8 2022, 4:01 AM · Restricted Project, Restricted Project

May 26 2022

joshua-arch1 added a comment to D87580: [RISCV][ASAN] support code for architecture-specific parts of asan.

==265==ERROR: AddressSanitizer: SEGV on unknown address 0x00081ffd1560 (pc 0x0000000108a8 bp 0x003fffe8ab70 sp 0x003fffe8aaf0 T0)
==265==The signal is caused by a READ memory access.

The current (and original) ASan RISC-V implementation assumes sv39. Linux did not support sv48 when the RISC-V ASan port was merged. Check if you are running with sv48 (cat /proc/cpu). If so, that is to be expected. Of course, adding sv48 support is welcome.

May 26 2022, 5:20 AM · Restricted Project, Restricted Project

May 25 2022

joshua-arch1 added a comment to D87580: [RISCV][ASAN] support code for architecture-specific parts of asan.

It seems that even if I run on hardware, ASAN cannot work for riscv64. It says

May 25 2022, 12:26 AM · Restricted Project, Restricted Project

May 9 2022

joshua-arch1 added a comment to D87580: [RISCV][ASAN] support code for architecture-specific parts of asan.

There is a range of addresses where the kernel may place the main executable. It has been extended once in the past (ASLR). ASan mapping is a compile-time constant, so it must work with any location within that range. I suspect that for QEMU this range may be different.

Anyway, some architectures use dynamic shadow allocation at runtime. IMHO this is a much better solution, even if it costs some CPU cycles (5% or whatever).

May 9 2022, 7:43 PM · Restricted Project, Restricted Project

May 8 2022

joshua-arch1 added a comment to D87580: [RISCV][ASAN] support code for architecture-specific parts of asan.

It seems that Asan cannot work correctly for RISC-V now.
When I use '-fsanitize=address' to compile the program and then run on Qemu, I get
AddressSanitizer: CHECK failed: sanitizer_allocator_primary32.h:292 "((res)) < ((kNumPossibleRegions))" (0x40016, 0x40000) (tid=80622)

<empty stack>

From your description, I assume you're running user-mode QEMU. The ASAN address mappings are system-specific. Running the user-mode QEMU is going to call your host machine's kernel, and the address mappings aren't going to be compatible. So I guess that behavior is to be expected. You should instead run a full riscv64-linux-gnu system under qemu-system-riscv64 to use ASAN with RISC-V.

May 8 2022, 11:11 PM · Restricted Project, Restricted Project

May 5 2022

joshua-arch1 added a comment to D87580: [RISCV][ASAN] support code for architecture-specific parts of asan.

The mappings are defined such that the address range where the kernel might place the main executable image do not overlap with the shadow region. This can be different in qemu.

May 5 2022, 8:08 PM · Restricted Project, Restricted Project

Apr 29 2022

joshua-arch1 added a comment to D87580: [RISCV][ASAN] support code for architecture-specific parts of asan.

It seems that Asan cannot work correctly for RISC-V now.
When I use '-fsanitize=address' to compile the program and then run on Qemu, I get
AddressSanitizer: CHECK failed: sanitizer_allocator_primary32.h:292 "((res)) < ((kNumPossibleRegions))" (0x40016, 0x40000) (tid=80622)

<empty stack>

From your description, I assume you're running user-mode QEMU. The ASAN address mappings are system-specific. Running the user-mode QEMU is going to call your host machine's kernel, and the address mappings aren't going to be compatible. So I guess that behavior is to be expected. You should instead run a full riscv64-linux-gnu system under qemu-system-riscv64 to use ASAN with RISC-V.

Apr 29 2022, 2:48 AM · Restricted Project, Restricted Project

Apr 25 2022

joshua-arch1 added a comment to D87580: [RISCV][ASAN] support code for architecture-specific parts of asan.

It seems that Asan cannot work correctly for RISC-V now.
When I use '-fsanitize=address' to compile the program and then run on Qemu, I get
AddressSanitizer: CHECK failed: sanitizer_allocator_primary32.h:292 "((res)) < ((kNumPossibleRegions))" (0x40016, 0x40000) (tid=80622)

<empty stack>

From your description, I assume you're running user-mode QEMU. The ASAN address mappings are system-specific. Running the user-mode QEMU is going to call your host machine's kernel, and the address mappings aren't going to be compatible. So I guess that behavior is to be expected. You should instead run a full riscv64-linux-gnu system under qemu-system-riscv64 to use ASAN with RISC-V.

Apr 25 2022, 8:03 PM · Restricted Project, Restricted Project

Apr 21 2022

Herald added a project to D87580: [RISCV][ASAN] support code for architecture-specific parts of asan: Restricted Project.

It seems that Asan cannot work correctly for RISC-V now.
When I use '-fsanitize=address' to compile the program and then run on Qemu, I get
AddressSanitizer: CHECK failed: sanitizer_allocator_primary32.h:292 "((res)) < ((kNumPossibleRegions))" (0x40016, 0x40000) (tid=80622)

<empty stack>
Apr 21 2022, 8:18 PM · Restricted Project, Restricted Project

Apr 1 2022

joshua-arch1 updated the diff for D116735: [RISCV] Adjust RISCV data layout by using n32:64 in layout string.
Apr 1 2022, 4:22 AM · Restricted Project, Restricted Project
joshua-arch1 updated the diff for D116735: [RISCV] Adjust RISCV data layout by using n32:64 in layout string.
Apr 1 2022, 2:04 AM · Restricted Project, Restricted Project
joshua-arch1 updated the diff for D116735: [RISCV] Adjust RISCV data layout by using n32:64 in layout string.
Apr 1 2022, 12:00 AM · Restricted Project, Restricted Project

Mar 31 2022

joshua-arch1 added a comment to D116735: [RISCV] Adjust RISCV data layout by using n32:64 in layout string.

Reverse ping.

Mar 31 2022, 11:39 PM · Restricted Project, Restricted Project
joshua-arch1 updated the diff for D116735: [RISCV] Adjust RISCV data layout by using n32:64 in layout string.
Mar 31 2022, 11:37 PM · Restricted Project, Restricted Project

Feb 27 2022

joshua-arch1 added a comment to D116735: [RISCV] Adjust RISCV data layout by using n32:64 in layout string.

I think I'm correct in thinking that everyone so far is broadly in favour of this change, but as Craig suggests it likely wants something in AutoUpgrade.cpp to handle the change.

Does anyone feel differently?

Feb 27 2022, 6:07 PM · Restricted Project, Restricted Project

Feb 23 2022

joshua-arch1 added a comment to D116735: [RISCV] Adjust RISCV data layout by using n32:64 in layout string.

Ping.

Feb 23 2022, 10:52 PM · Restricted Project, Restricted Project
joshua-arch1 updated the diff for D116735: [RISCV] Adjust RISCV data layout by using n32:64 in layout string.
Feb 23 2022, 10:45 PM · Restricted Project, Restricted Project
joshua-arch1 updated the diff for D116735: [RISCV] Adjust RISCV data layout by using n32:64 in layout string.
Feb 23 2022, 10:39 PM · Restricted Project, Restricted Project

Feb 8 2022

joshua-arch1 added a comment to D116735: [RISCV] Adjust RISCV data layout by using n32:64 in layout string.

Ping.

Feb 8 2022, 3:59 AM · Restricted Project, Restricted Project

Jan 25 2022

joshua-arch1 added a comment to D116735: [RISCV] Adjust RISCV data layout by using n32:64 in layout string.

For the following benchmark, the performance can improve without degression of other cases (on T-HEAD XuanTie C906 processor with THEAD instruction extension)

Jan 25 2022, 11:02 PM · Restricted Project, Restricted Project

Jan 16 2022

joshua-arch1 added a comment to D116735: [RISCV] Adjust RISCV data layout by using n32:64 in layout string.

I have checked all the benchmarks.
For coremark, spec2006_int-471.omnetpp and eembc_networking_pktflow, the performance can improve by more than 3%, without degression of other cases.

Can you say more about what hardware and ISA extensions were used for that testing?

Jan 16 2022, 7:31 PM · Restricted Project, Restricted Project

Jan 9 2022

joshua-arch1 added a comment to D116735: [RISCV] Adjust RISCV data layout by using n32:64 in layout string.

I have checked all the benchmarks.
For coremark, spec2006_int-471.omnetpp and eembc_networking_pktflow, the performance can improve by more than 3%, without degression of other cases.

Jan 9 2022, 6:01 PM · Restricted Project, Restricted Project

Jan 6 2022

joshua-arch1 updated the diff for D116735: [RISCV] Adjust RISCV data layout by using n32:64 in layout string.
Jan 6 2022, 6:47 PM · Restricted Project, Restricted Project
joshua-arch1 updated the summary of D116735: [RISCV] Adjust RISCV data layout by using n32:64 in layout string.
Jan 6 2022, 3:53 AM · Restricted Project, Restricted Project
joshua-arch1 requested review of D116735: [RISCV] Adjust RISCV data layout by using n32:64 in layout string.
Jan 6 2022, 3:52 AM · Restricted Project, Restricted Project

Sep 14 2020

joshua-arch1 added inline comments to D86195: [RISC-V] Add support for AddressSanitizer on RISC-V GCC.
Sep 14 2020, 11:02 PM

Sep 13 2020

joshua-arch1 updated the summary of D86195: [RISC-V] Add support for AddressSanitizer on RISC-V GCC.
Sep 13 2020, 11:45 PM
joshua-arch1 updated the summary of D86195: [RISC-V] Add support for AddressSanitizer on RISC-V GCC.
Sep 13 2020, 11:44 PM
joshua-arch1 updated the diff for D86195: [RISC-V] Add support for AddressSanitizer on RISC-V GCC.
Sep 13 2020, 11:31 PM
joshua-arch1 added a comment to D86198: llvm enable sanitizer (RISCV64).

There are still issues with compiling and running the sanitizer tests for the added architecture. I think fixing those should be a precondition for this to be considered mergeable.

Have you added the flag "-DLLVM_DEFAULT_TARGET_TRIPLE="riscv64-unknown-linux-gnu"" and "-fsanitize=address" when compiling the sanitizer test?

It's not that I had trouble compiling tests due to an incorrect configuration (I think), it's that when running the entire set of sanitizer tests I encountered things (e.g. #ifdefs) that weren't yet implemented for RISC-V, and so would fail to compile or run. Have you tried running the entire set of (relevant) sanitizer checks?

Sep 13 2020, 6:35 PM

Sep 5 2020

joshua-arch1 added a comment to D86198: llvm enable sanitizer (RISCV64).

I have updated my patch and summary. Are there any new updates with the patch review?

There are still issues with compiling and running the sanitizer tests for the added architecture. I think fixing those should be a precondition for this to be considered mergeable.

Sep 5 2020, 7:19 PM

Aug 27 2020

joshua-arch1 added a comment to D86198: llvm enable sanitizer (RISCV64).

For D84727, I didn't know how to correctly submit an updated patch before. That is why I submitted another patch. For the current stage, you can just abandon D84727.

For D84727 you need to go to the dropdown menu near the bottom that says "Add Action..." and choose "Abandon Revision". To update a patch you use the "Update Diff" link elsewhere on the review page.

Aug 27 2020, 11:33 PM

Aug 23 2020

joshua-arch1 edited reviewers for D86198: llvm enable sanitizer (RISCV64), added: asb; removed: alex.
Aug 23 2020, 7:01 PM
joshua-arch1 edited reviewers for D86195: [RISC-V] Add support for AddressSanitizer on RISC-V GCC, added: asb; removed: alex.
Aug 23 2020, 7:00 PM
joshua-arch1 added a reviewer for D86195: [RISC-V] Add support for AddressSanitizer on RISC-V GCC: alex.
Aug 23 2020, 6:58 PM
joshua-arch1 added a reviewer for D86198: llvm enable sanitizer (RISCV64): alex.
Aug 23 2020, 6:57 PM

Aug 20 2020

joshua-arch1 updated the summary of D86195: [RISC-V] Add support for AddressSanitizer on RISC-V GCC.
Aug 20 2020, 10:53 PM
joshua-arch1 added a reviewer for D86195: [RISC-V] Add support for AddressSanitizer on RISC-V GCC: luismarques.
Aug 20 2020, 10:51 PM
joshua-arch1 added a comment to D86198: llvm enable sanitizer (RISCV64).
Aug 20 2020, 10:49 PM
joshua-arch1 updated the diff for D86198: llvm enable sanitizer (RISCV64).

Remove some unnecessary sanitizers and update the summary

Aug 20 2020, 4:26 AM
joshua-arch1 abandoned D84727: [RISC-V] Add support for AddressSanitizer.
Aug 20 2020, 4:11 AM
joshua-arch1 added a comment to D86195: [RISC-V] Add support for AddressSanitizer on RISC-V GCC.

Hi Jun:

GCC part should review at gcc-patch mailing list instead of here, for other files (sanitizer_platform.h, sanitizer_common.h and sanitizer_symbolizer_libcdep.cpp), it's right place to review, but it should using the diff which generated within LLVM source-tree, and GCC will sync libsanitizer after LLVM is accepted.

What about config/riscv/riscv.c? Should I place it here to review?

For config/riscv/riscv.c, it's part of GCC source tree, so there is wrong place to review :P

Aug 20 2020, 2:51 AM
joshua-arch1 added a comment to D86198: llvm enable sanitizer (RISCV64).

Did you mean D84727? For that patch, no one has given an update feedback so far.

Yes, I meant D84727. I don't see why the lack of additional feedback on that patch lead you to submit another patch that also enabled ASan, among other sanitizers.

Hi I have updated the patch according to your comments.

You didn't actually address point 4. The review summary doesn't accurately list the enabled sanitizers and doesn't provide an explanation or evidence for why enabling them is reasonable. For instance, this patch enables DFSan but there is no actual support for RISC-V, and it won't actually compile as is.

Aug 20 2020, 2:47 AM
joshua-arch1 added a comment to D86198: llvm enable sanitizer (RISCV64).
  1. You need to provide the full context in the patch. See [1], particularly the part about the -U999999.
  2. You need to base your patch on a recent LLVM commit, as this patch doesn't apply cleanly.
  3. This patch repeats changes from D86198. Are you abandoning D86198? If so you need to update the status of that review.
  4. I would expect this review to provide a more detailed summary, including the support status of the various sanitizers for RISC-V, and why it's reasonable to enable them.

[1] https://llvm.org/docs/Phabricator.html#phabricator-request-review-web

Aug 20 2020, 12:40 AM
joshua-arch1 added a comment to D86195: [RISC-V] Add support for AddressSanitizer on RISC-V GCC.

can you generate the diff with full context?

git format-patch -U99999

Aug 20 2020, 12:39 AM
joshua-arch1 updated the diff for D86195: [RISC-V] Add support for AddressSanitizer on RISC-V GCC.
  1. to remove unnecessary definitions
  2. to generate the diff with full context
  3. to generate the diff on LLVM source tree
Aug 20 2020, 12:38 AM
joshua-arch1 updated the summary of D86198: llvm enable sanitizer (RISCV64).
Aug 20 2020, 12:12 AM
joshua-arch1 updated the diff for D86198: llvm enable sanitizer (RISCV64).
  1. to provide the full context in the patch
  2. to base the patch on a recent LLVM commit
Aug 20 2020, 12:12 AM

Aug 19 2020

joshua-arch1 added a comment to D86198: llvm enable sanitizer (RISCV64).
  1. You need to provide the full context in the patch. See [1], particularly the part about the -U999999.
  2. You need to base your patch on a recent LLVM commit, as this patch doesn't apply cleanly.
  3. This patch repeats changes from D86198. Are you abandoning D86198? If so you need to update the status of that review.
  4. I would expect this review to provide a more detailed summary, including the support status of the various sanitizers for RISC-V, and why it's reasonable to enable them.

[1] https://llvm.org/docs/Phabricator.html#phabricator-request-review-web

Aug 19 2020, 6:33 PM
joshua-arch1 added a comment to D86195: [RISC-V] Add support for AddressSanitizer on RISC-V GCC.
Aug 19 2020, 1:06 AM
joshua-arch1 added a reviewer for D86198: llvm enable sanitizer (RISCV64): lenary.
Aug 19 2020, 12:42 AM
joshua-arch1 requested review of D86198: llvm enable sanitizer (RISCV64).
Aug 19 2020, 12:42 AM

Aug 18 2020

joshua-arch1 added a comment to D86195: [RISC-V] Add support for AddressSanitizer on RISC-V GCC.

Hi Jun:

GCC part should review at gcc-patch mailing list instead of here, for other files (sanitizer_platform.h, sanitizer_common.h and sanitizer_symbolizer_libcdep.cpp), it's right place to review, but it should using the diff which generated within LLVM source-tree, and GCC will sync libsanitizer after LLVM is accepted.

Aug 18 2020, 11:45 PM
joshua-arch1 added a reviewer for D86195: [RISC-V] Add support for AddressSanitizer on RISC-V GCC: marxin.
Aug 18 2020, 11:26 PM
joshua-arch1 added a reviewer for D86195: [RISC-V] Add support for AddressSanitizer on RISC-V GCC: jimw.
Aug 18 2020, 11:20 PM
joshua-arch1 added a reviewer for D86195: [RISC-V] Add support for AddressSanitizer on RISC-V GCC: lenary.
Aug 18 2020, 11:18 PM
joshua-arch1 requested review of D86195: [RISC-V] Add support for AddressSanitizer on RISC-V GCC.
Aug 18 2020, 11:17 PM
joshua-arch1 added a comment to D84727: [RISC-V] Add support for AddressSanitizer.

There is only support for 64-bit RISC-V in the sanitizer implementation: rG977205b595c. Until the 32-bit risc-v linux ABI is stable, this should not be landed.

Aug 18 2020, 11:11 PM
joshua-arch1 added a comment to D84727: [RISC-V] Add support for AddressSanitizer.
Aug 18 2020, 11:10 PM

Jul 30 2020

joshua-arch1 updated the diff for D84727: [RISC-V] Add support for AddressSanitizer.

I have removed support for 32-bit RISC-V in Linux sanitizer implementation. Please review it.

Jul 30 2020, 5:24 AM

Jul 28 2020

joshua-arch1 added reviewers for D84727: [RISC-V] Add support for AddressSanitizer: mgorny, fedor.sergeev, simoncook, cryptoad, shiva0217, rogfer01, rkruppe, s.egerton, sameer.abuasal, luismarques.
Jul 28 2020, 5:37 AM

Jul 27 2020

joshua-arch1 added a reviewer for D84727: [RISC-V] Add support for AddressSanitizer: PkmX.
Jul 27 2020, 10:52 PM
joshua-arch1 added reviewers for D84727: [RISC-V] Add support for AddressSanitizer: kito-cheng, Jim.
Jul 27 2020, 10:51 PM
joshua-arch1 requested review of D84727: [RISC-V] Add support for AddressSanitizer.
Jul 27 2020, 10:50 PM