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[AArch64] Support SLC in ACLE prefetch intrinsics

Authored by lenary on Dec 6 2022, 10:36 AM.



This change:

  • Modifies the ACLE code to allow the new SLC value (3) for the prefetch target.
  • Introduces a new intrinsic, @llvm.aarch64.prefetch which matches the PRFM family instructions much more closely, and can represent all values for the PRFM immediate.

    The target-independent @llvm.prefetch intrinsic does not have enough information for us to be able to lower to it from the ACLE intrinsics correctly.
  • Lowers the acle calls to the new intrinsic on aarch64 (the ARM lowering is unchanged).
  • Implements code generation for the new intrinsic in both SelectionDAG and GlobalISel. We specifically choose to continue to support lowering the target-independent @llvm.prefetch intrinsic so that other frontends can continue to use it.

Diff Detail

Event Timeline

lenary created this revision.Dec 6 2022, 10:36 AM
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lenary requested review of this revision.Dec 6 2022, 10:36 AM
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lenary added reviewers: pratlucas, stuij, tmatheson.
lenary added a reviewer: sdesmalen.
lenary added a subscriber: sdesmalen.

@sdesmalen adding you as I've moved around the custom lowering of INTRINSIC_VOID to be its own function, and as we need to handle it for @llvm.arm.prefetch all the time, it's no longer conditional on SME.

tschuett added inline comments.

I believe you also have to turn on GISL: -global-isel.

See test in

lenary added inline comments.Dec 6 2022, 10:47 AM

I'm not sure this is necessary, global isel is enabled at O0 on AArch64, and e.g. RegBankSelect appears in the output of llc -mtriple=aarch64 -mattr=+v8.9a -O0 < llvm/test/CodeGen/AArch64/arm64-prefetch-new.ll -debug-pass=Structure -o arm64-prefetch-new.ll

Would you find it clearer as:

; RUN: llc -mtriple=aarch64 -mattr=+v8.9a --global-isel=0 < %s | FileCheck %s
; RUN: llc -mtriple=aarch64 -mattr=+v8.9a --global-isel=1 --global-isel-abort=1 < %s | FileCheck %s


tschuett added inline comments.Dec 6 2022, 10:50 AM

I didn't know or forgot. I believe --global-isel=1 makes the intent clearer.

lenary updated this revision to Diff 482489.Dec 13 2022, 8:01 AM

Adding Jessica and Amara as this affects GlobalISel for AArch64.

GISel part LGTM

This revision is now accepted and ready to land.Dec 16 2022, 3:34 AM
This revision was landed with ongoing or failed builds.Dec 16 2022, 6:43 AM
This revision was automatically updated to reflect the committed changes.
lenary marked 2 inline comments as done.