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pratlucas (Lucas Prates)
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User Since
Jan 21 2020, 7:29 AM (34 w, 6 d)

Recent Activity

Today

pratlucas committed rG53d238a961d1: [CodeGen] Fixing inconsistent ABI mangling of vlaues in SelectionDAGBuilder (authored by pratlucas).
[CodeGen] Fixing inconsistent ABI mangling of vlaues in SelectionDAGBuilder
Mon, Sep 21, 2:05 AM
pratlucas closed D87844: [CodeGen] Fixing inconsistent ABI mangling of vlaues in SelectionDAGBuilder.
Mon, Sep 21, 2:05 AM · Restricted Project

Fri, Sep 18

pratlucas updated the diff for D87844: [CodeGen] Fixing inconsistent ABI mangling of vlaues in SelectionDAGBuilder.

Cleaning-up test and removing the getABIRegCopyCC function.

Fri, Sep 18, 7:51 AM · Restricted Project
pratlucas added a comment to D87844: [CodeGen] Fixing inconsistent ABI mangling of vlaues in SelectionDAGBuilder.

This seemed weird to me as well, specially as removing it had no impact on any of the regression tests.

Fri, Sep 18, 7:27 AM · Restricted Project

Thu, Sep 17

pratlucas added reviewers for D87844: [CodeGen] Fixing inconsistent ABI mangling of vlaues in SelectionDAGBuilder: eli.friedman, arsenm, hans, sunfish.
Thu, Sep 17, 10:36 AM · Restricted Project
pratlucas requested review of D87844: [CodeGen] Fixing inconsistent ABI mangling of vlaues in SelectionDAGBuilder.
Thu, Sep 17, 10:33 AM · Restricted Project

Thu, Aug 27

pratlucas committed rG3d943bcd223e: [CodeGen] Properly propagating Calling Convention information when lowering… (authored by pratlucas).
[CodeGen] Properly propagating Calling Convention information when lowering…
Thu, Aug 27, 9:01 AM
pratlucas closed D86715: [CodeGen] Properly propagating Calling Convention information when lowering vector arguments.
Thu, Aug 27, 9:01 AM · Restricted Project
pratlucas added inline comments to D86715: [CodeGen] Properly propagating Calling Convention information when lowering vector arguments.
Thu, Aug 27, 7:48 AM · Restricted Project
pratlucas added reviewers for D86715: [CodeGen] Properly propagating Calling Convention information when lowering vector arguments: ostannard, dmgreen, hans, efriedma.
Thu, Aug 27, 7:45 AM · Restricted Project
pratlucas updated the diff for D86715: [CodeGen] Properly propagating Calling Convention information when lowering vector arguments.

Removing unrelated whitespace change.

Thu, Aug 27, 7:42 AM · Restricted Project
pratlucas requested review of D86715: [CodeGen] Properly propagating Calling Convention information when lowering vector arguments.
Thu, Aug 27, 7:40 AM · Restricted Project

Tue, Aug 25

pratlucas added a comment to D75169: [ARM] Supporting lowering of half-precision FP arguments and returns in AArch32's backend.

Hi @hans , I'll have a look at it!

Tue, Aug 25, 8:33 AM · Restricted Project, Restricted Project

Jul 9 2020

pratlucas committed rGfc39a9ca0ef4: [CodeGen] Matching promoted type for 16-bit integer bitcasts from fp16 operand (authored by pratlucas).
[CodeGen] Matching promoted type for 16-bit integer bitcasts from fp16 operand
Jul 9 2020, 1:46 AM
pratlucas closed D82552: [CodeGen] Matching promoted type for 16-bit integer bitcasts from fp16 operand.
Jul 9 2020, 1:46 AM · Restricted Project

Jul 7 2020

pratlucas updated the diff for D82552: [CodeGen] Matching promoted type for 16-bit integer bitcasts from fp16 operand.

Fixing typos.

Jul 7 2020, 2:13 AM · Restricted Project

Jul 2 2020

pratlucas updated the diff for D82552: [CodeGen] Matching promoted type for 16-bit integer bitcasts from fp16 operand.

Moving fix to SelectionDAG::getNode.

Jul 2 2020, 8:37 AM · Restricted Project
pratlucas accepted D82443: [ARM] Narrowing half-precision lowering to supported CCs.

@plotfi This should not interfere D82552.
I believe you can land this, LGTM.

Jul 2 2020, 8:37 AM · Restricted Project
pratlucas added a comment to D81942: [NFC][CodeGen] Refactor: splitting register allocation method in RegAllocFast.

Ping.

Jul 2 2020, 7:31 AM · Restricted Project

Jun 25 2020

pratlucas added a comment to D82552: [CodeGen] Matching promoted type for 16-bit integer bitcasts from fp16 operand.

The issue happens when creating the ISD::FP_TO_FP16 in case the input is a constant.
It tries to generate the new 16-bit constant but the NOutVT type passed to DAG.getNode has 32-bits, which causes the assertion in SelectionDAG.cpp:1307 to fail:

llvm/lib/CodeGen/SelectionDAG/SelectionDAG.cpp:1307: llvm::SDValue llvm::SelectionDAG::getConstant(const llvm::ConstantInt &, const llvm::SDLoc &, llvm::EVT, bool, bool): Assertion `Elt->getBitWidth() == EltVT.getSizeInBits() && "APInt size does not match type size!"' failed.
Jun 25 2020, 10:14 AM · Restricted Project
pratlucas added a comment to D82443: [ARM] Narrowing half-precision lowering to supported CCs.

I've posted D82552 fixing the assertion failure on the type legalization's bitcast handling. Once it lands, it should be ok to include arm_aapcs_fvpcc and swiftcc on this patch.

Jun 25 2020, 8:00 AM · Restricted Project
pratlucas added reviewers for D82552: [CodeGen] Matching promoted type for 16-bit integer bitcasts from fp16 operand: ostannard, efriedma, pirama, jmolloy, plotfi.
Jun 25 2020, 8:00 AM · Restricted Project
pratlucas created D82552: [CodeGen] Matching promoted type for 16-bit integer bitcasts from fp16 operand.
Jun 25 2020, 8:00 AM · Restricted Project

Jun 24 2020

pratlucas added reviewers for D82443: [ARM] Narrowing half-precision lowering to supported CCs: efriedma, ostannard, SjoerdMeijer.
Jun 24 2020, 9:42 AM · Restricted Project
pratlucas added a comment to D82443: [ARM] Narrowing half-precision lowering to supported CCs.

It seems most of the argument lowering convertions get simplifyed on the regular case, when not using fastcc.
When using it, though, type legalization ends up trying to handle a i16 = bitcast ConstantFP:f16<APFloat(0)> node, turning it into an i32 <- f32 operation and getting lost while trying to create the new constant.

Jun 24 2020, 9:42 AM · Restricted Project
pratlucas added a comment to D82443: [ARM] Narrowing half-precision lowering to supported CCs.

Taking a further look to the differences in the DAG, the resulting type is actually the same.
Both result in an f32 value, but get to it in different ways as expected.

Jun 24 2020, 3:44 AM · Restricted Project
pratlucas added a comment to D82443: [ARM] Narrowing half-precision lowering to supported CCs.

I believe simply limiting the calling conventions might be a bit tricky. At this point the method might get a calling convention id that does not reflect the one required for argument lowering (see ARMTargetLowering::getEffectiveCallingConv in ARMISelLowering.cpp).
One option to get around this would be to use that same method to determine the effective calling convention, but it might not be easy to check whether or not the function beeing handled is variadic.

Jun 24 2020, 3:12 AM · Restricted Project

Jun 18 2020

pratlucas committed rGada4c9dc4a63: [ARM][Clang] Removing lowering of half-precision FP arguments and returns from… (authored by pratlucas).
[ARM][Clang] Removing lowering of half-precision FP arguments and returns from…
Jun 18 2020, 5:25 AM
pratlucas committed rG92ad6d57c218: [ARM] Moving CMSE handling of half arguments and return to the backend (authored by pratlucas).
[ARM] Moving CMSE handling of half arguments and return to the backend
Jun 18 2020, 5:25 AM
pratlucas closed D81451: [ARM][Clang] Removing lowering of half-precision FP arguments and returns from Clang's CodeGen.
Jun 18 2020, 5:25 AM · Restricted Project
pratlucas committed rGa255931c4055: [ARM] Supporting lowering of half-precision FP arguments and returns in… (authored by pratlucas).
[ARM] Supporting lowering of half-precision FP arguments and returns in…
Jun 18 2020, 5:25 AM
pratlucas closed D81428: [ARM] Moving CMSE handling of half arguments and return to the backend.
Jun 18 2020, 5:25 AM · Restricted Project, Restricted Project
pratlucas closed D75169: [ARM] Supporting lowering of half-precision FP arguments and returns in AArch32's backend.
Jun 18 2020, 5:24 AM · Restricted Project, Restricted Project

Jun 16 2020

pratlucas added inline comments to D80999: [ARM][CodeGen] Enabling spilling of high registers in RegAllocFast for Thumb1.
Jun 16 2020, 9:21 AM · Restricted Project
pratlucas edited reviewers for D80999: [ARM][CodeGen] Enabling spilling of high registers in RegAllocFast for Thumb1, added: efriedma; removed: eli.friedman.
Jun 16 2020, 9:21 AM · Restricted Project
pratlucas updated the diff for D80999: [ARM][CodeGen] Enabling spilling of high registers in RegAllocFast for Thumb1.

Splitting NFC changes into a separate patch.

Jun 16 2020, 9:21 AM · Restricted Project
pratlucas added reviewers for D81942: [NFC][CodeGen] Refactor: splitting register allocation method in RegAllocFast: efriedma, arsenm.
Jun 16 2020, 9:21 AM · Restricted Project
pratlucas created D81942: [NFC][CodeGen] Refactor: splitting register allocation method in RegAllocFast.
Jun 16 2020, 9:21 AM · Restricted Project

Jun 15 2020

pratlucas added a comment to D81451: [ARM][Clang] Removing lowering of half-precision FP arguments and returns from Clang's CodeGen.

The changes to the backend only handle the half (f16) type itself, not vectors that have it as their base type.

Jun 15 2020, 9:13 AM · Restricted Project
pratlucas added a comment to D80999: [ARM][CodeGen] Enabling spilling of high registers in RegAllocFast for Thumb1.

After taking a deeper look at ARMConstantIslandPass, I believe this patch won't actually cause any issues when interacting with it.

Jun 15 2020, 8:43 AM · Restricted Project

Jun 12 2020

pratlucas added a comment to D75169: [ARM] Supporting lowering of half-precision FP arguments and returns in AArch32's backend.

From @SjoerdMeijer's comment and the links he pointed to, it seems to me that making f16 types legal for all ARM subtargets would be a major undertaking and far from trivial to implement. It's also not clear to me how significant would be the returns of this effort.
My feeling is that we could proceed with the current approach and discuss the possbility of making f16 legal in a separate follow up effort, as mentioned by @dnsampaio.

Jun 12 2020, 6:58 AM · Restricted Project, Restricted Project

Jun 11 2020

pratlucas added inline comments to D81428: [ARM] Moving CMSE handling of half arguments and return to the backend.
Jun 11 2020, 8:48 AM · Restricted Project, Restricted Project
pratlucas updated the diff for D81428: [ARM] Moving CMSE handling of half arguments and return to the backend.

Addressing review comment.

Jun 11 2020, 8:46 AM · Restricted Project, Restricted Project
pratlucas updated the diff for D81428: [ARM] Moving CMSE handling of half arguments and return to the backend.

Rebasing and simplifying function attributes on test.

Jun 11 2020, 8:46 AM · Restricted Project, Restricted Project
pratlucas updated the diff for D75169: [ARM] Supporting lowering of half-precision FP arguments and returns in AArch32's backend.

Fixing failure on CodeGen/ARM/GlobalISel/arm-unsupported.ll and making clang-format happy.

Jun 11 2020, 8:14 AM · Restricted Project, Restricted Project

Jun 10 2020

pratlucas added inline comments to D75169: [ARM] Supporting lowering of half-precision FP arguments and returns in AArch32's backend.
Jun 10 2020, 11:41 AM · Restricted Project, Restricted Project
pratlucas updated the diff for D75169: [ARM] Supporting lowering of half-precision FP arguments and returns in AArch32's backend.

Clean-ups + fixing failure in CodeGen/ARM/half.ll test.

Jun 10 2020, 11:40 AM · Restricted Project, Restricted Project

Jun 9 2020

pratlucas updated the diff for D75169: [ARM] Supporting lowering of half-precision FP arguments and returns in AArch32's backend.

Formatting patch.

Jun 9 2020, 3:15 AM · Restricted Project, Restricted Project
pratlucas retitled D75169: [ARM] Supporting lowering of half-precision FP arguments and returns in AArch32's backend from [ARM] Enforcing calling convention for half-precision FP arguments and returns for big-endian AArch32 to [ARM] Supporting lowering of half-precision FP arguments and returns in AArch32's backend.
Jun 9 2020, 2:42 AM · Restricted Project, Restricted Project
pratlucas added reviewers for D81451: [ARM][Clang] Removing lowering of half-precision FP arguments and returns from Clang's CodeGen: rjmccall, chill, ostannard, dnsampaio.
Jun 9 2020, 2:42 AM · Restricted Project
pratlucas updated the diff for D81428: [ARM] Moving CMSE handling of half arguments and return to the backend.

Moving the clean-up of the Clang-side handling to a separate patch.

Jun 9 2020, 2:42 AM · Restricted Project, Restricted Project
pratlucas updated the diff for D75169: [ARM] Supporting lowering of half-precision FP arguments and returns in AArch32's backend.

Splitting the patch into two parts: one for introducing the half-precision
handling into AArch32's backend and one for removing the existing coercion
of those arguments from Clang.

Jun 9 2020, 2:42 AM · Restricted Project, Restricted Project
pratlucas created D81451: [ARM][Clang] Removing lowering of half-precision FP arguments and returns from Clang's CodeGen.
Jun 9 2020, 2:42 AM · Restricted Project

Jun 8 2020

pratlucas added reviewers for D81428: [ARM] Moving CMSE handling of half arguments and return to the backend: chill, rjmccall, ostannard.
Jun 8 2020, 1:52 PM · Restricted Project, Restricted Project
pratlucas created D81428: [ARM] Moving CMSE handling of half arguments and return to the backend.
Jun 8 2020, 1:52 PM · Restricted Project, Restricted Project
pratlucas updated the diff for D75169: [ARM] Supporting lowering of half-precision FP arguments and returns in AArch32's backend.

Re-writing the handling of fp16 arguments, moving their lowering to be performed
in the backend.

Jun 8 2020, 1:52 PM · Restricted Project, Restricted Project

Jun 4 2020

pratlucas added a comment to D80999: [ARM][CodeGen] Enabling spilling of high registers in RegAllocFast for Thumb1.

This is intentionally not addressing greedy regalloc, I guess.

Jun 4 2020, 9:53 AM · Restricted Project
pratlucas updated the diff for D80999: [ARM][CodeGen] Enabling spilling of high registers in RegAllocFast for Thumb1.

Rebasing on top of rG66251f7e1de7.

Jun 4 2020, 9:20 AM · Restricted Project

Jun 3 2020

pratlucas committed rG8beaba13b8a6: [Clang][AArch64] Capturing proper pointer alignment for Neon vld1 intrinsicts (authored by pratlucas).
[Clang][AArch64] Capturing proper pointer alignment for Neon vld1 intrinsicts
Jun 3 2020, 3:49 AM
pratlucas closed D79721: [Clang][AArch64] Capturing proper pointer alignment for Neon vld1 intrinsicts.
Jun 3 2020, 3:48 AM · Restricted Project

Jun 2 2020

pratlucas added inline comments to D80716: [AArch64]: BFloat Load/Store Intrinsics&CodeGen.
Jun 2 2020, 9:52 AM · Restricted Project, Restricted Project
pratlucas added inline comments to D79721: [Clang][AArch64] Capturing proper pointer alignment for Neon vld1 intrinsicts.
Jun 2 2020, 9:52 AM · Restricted Project
pratlucas updated the diff for D79721: [Clang][AArch64] Capturing proper pointer alignment for Neon vld1 intrinsicts.

Addressing review comments and extending tests.

Jun 2 2020, 9:52 AM · Restricted Project
pratlucas updated the diff for D80999: [ARM][CodeGen] Enabling spilling of high registers in RegAllocFast for Thumb1.

Removing unecessary include and fixing formatting.

Jun 2 2020, 7:08 AM · Restricted Project
pratlucas added reviewers for D80999: [ARM][CodeGen] Enabling spilling of high registers in RegAllocFast for Thumb1: eli.friedman, thopre, qcolombet, abeserminji, MatzeB, arsenm, petpav01.
Jun 2 2020, 6:36 AM · Restricted Project
pratlucas created D80999: [ARM][CodeGen] Enabling spilling of high registers in RegAllocFast for Thumb1.
Jun 2 2020, 6:36 AM · Restricted Project

May 27 2020

pratlucas updated the diff for D79721: [Clang][AArch64] Capturing proper pointer alignment for Neon vld1 intrinsicts.

Hi @efriedma and @plotf,

May 27 2020, 5:55 AM · Restricted Project
pratlucas reopened D79721: [Clang][AArch64] Capturing proper pointer alignment for Neon vld1 intrinsicts.
May 27 2020, 5:55 AM · Restricted Project

May 26 2020

pratlucas committed rG98cad555e291: [Clang][AArch64] Capturing proper pointer alignment for Neon vld1 intrinsicts (authored by pratlucas).
[Clang][AArch64] Capturing proper pointer alignment for Neon vld1 intrinsicts
May 26 2020, 2:40 AM
pratlucas closed D79721: [Clang][AArch64] Capturing proper pointer alignment for Neon vld1 intrinsicts.
May 26 2020, 2:39 AM · Restricted Project

May 20 2020

pratlucas added a comment to D79721: [Clang][AArch64] Capturing proper pointer alignment for Neon vld1 intrinsicts.

Ping.

May 20 2020, 3:12 AM · Restricted Project

May 11 2020

pratlucas added reviewers for D79721: [Clang][AArch64] Capturing proper pointer alignment for Neon vld1 intrinsicts: t.p.northover, ostannard, pcc.
May 11 2020, 9:39 AM · Restricted Project
pratlucas created D79721: [Clang][AArch64] Capturing proper pointer alignment for Neon vld1 intrinsicts.
May 11 2020, 9:39 AM · Restricted Project
pratlucas committed rGfdebc127acff: [Clang][AArch64] Capturing proper pointer alignment for Neon vld1 intrinsicts (authored by pratlucas).
[Clang][AArch64] Capturing proper pointer alignment for Neon vld1 intrinsicts
May 11 2020, 4:15 AM

May 7 2020

pratlucas committed rG9d39df03a984: [Clang][Sema] Capturing section type conflicts between #pragma clang section… (authored by pratlucas).
[Clang][Sema] Capturing section type conflicts between #pragma clang section…
May 7 2020, 3:56 AM
pratlucas committed rG0dac639f285a: [Clang][Sema] Capturing section type conflicts on #pragma clang section (authored by pratlucas).
[Clang][Sema] Capturing section type conflicts on #pragma clang section
May 7 2020, 3:56 AM
pratlucas closed D78573: [Clang][Sema] Capturing section type conflicts between #pragma clang section and section attributes.
May 7 2020, 3:56 AM · Restricted Project
pratlucas closed D78572: [Clang][Sema] Capturing section type conflicts on #pragma clang section.
May 7 2020, 3:56 AM · Restricted Project
pratlucas updated the diff for D78572: [Clang][Sema] Capturing section type conflicts on #pragma clang section.

Addressing review comment.

May 7 2020, 3:55 AM · Restricted Project
pratlucas updated the diff for D78573: [Clang][Sema] Capturing section type conflicts between #pragma clang section and section attributes.

Addressing review comment.

May 7 2020, 3:54 AM · Restricted Project

May 5 2020

pratlucas added a comment to D75169: [ARM] Supporting lowering of half-precision FP arguments and returns in AArch32's backend.

Ping.

May 5 2020, 2:39 AM · Restricted Project, Restricted Project
pratlucas edited reviewers for D75169: [ARM] Supporting lowering of half-precision FP arguments and returns in AArch32's backend, added: asl; removed: lattner, rudkx.
May 5 2020, 2:39 AM · Restricted Project, Restricted Project
pratlucas added a comment to D78573: [Clang][Sema] Capturing section type conflicts between #pragma clang section and section attributes.

Ping.

May 5 2020, 2:39 AM · Restricted Project

Apr 28 2020

pratlucas added inline comments to D78573: [Clang][Sema] Capturing section type conflicts between #pragma clang section and section attributes.
Apr 28 2020, 7:29 AM · Restricted Project
pratlucas updated the diff for D78573: [Clang][Sema] Capturing section type conflicts between #pragma clang section and section attributes.

Updateing test.

Apr 28 2020, 7:29 AM · Restricted Project

Apr 23 2020

pratlucas updated the diff for D78572: [Clang][Sema] Capturing section type conflicts on #pragma clang section.

Rebasing.

Apr 23 2020, 9:11 AM · Restricted Project
pratlucas updated the diff for D78573: [Clang][Sema] Capturing section type conflicts between #pragma clang section and section attributes.

Rebasing.

Apr 23 2020, 9:11 AM · Restricted Project

Apr 22 2020

pratlucas committed rG727e6fb84a3a: [NFC][llvm][X86] Adding missing -mtiple to X86 test. (authored by pratlucas).
[NFC][llvm][X86] Adding missing -mtiple to X86 test.
Apr 22 2020, 4:17 AM

Apr 21 2020

pratlucas added reviewers for D78573: [Clang][Sema] Capturing section type conflicts between #pragma clang section and section attributes: hans, rnk, javed.absar.
Apr 21 2020, 10:47 AM · Restricted Project
pratlucas updated the diff for D78573: [Clang][Sema] Capturing section type conflicts between #pragma clang section and section attributes.

Removing unnecessary function.

Apr 21 2020, 10:47 AM · Restricted Project
pratlucas added reviewers for D78572: [Clang][Sema] Capturing section type conflicts on #pragma clang section: hans, rnk, javed.absar.
Apr 21 2020, 10:47 AM · Restricted Project
pratlucas updated the diff for D78573: [Clang][Sema] Capturing section type conflicts between #pragma clang section and section attributes.

Fixing "mising clang-format" messages.

Apr 21 2020, 10:14 AM · Restricted Project
pratlucas updated the diff for D78572: [Clang][Sema] Capturing section type conflicts on #pragma clang section.

Fixing missing clang-format messages.

Apr 21 2020, 10:14 AM · Restricted Project
pratlucas created D78572: [Clang][Sema] Capturing section type conflicts on #pragma clang section.
Apr 21 2020, 9:42 AM · Restricted Project
pratlucas created D78573: [Clang][Sema] Capturing section type conflicts between #pragma clang section and section attributes.
Apr 21 2020, 9:42 AM · Restricted Project

Apr 20 2020

pratlucas added a comment to D75169: [ARM] Supporting lowering of half-precision FP arguments and returns in AArch32's backend.

Ping.

Apr 20 2020, 1:34 AM · Restricted Project, Restricted Project

Apr 8 2020

pratlucas added a comment to D75169: [ARM] Supporting lowering of half-precision FP arguments and returns in AArch32's backend.

Ping.

Apr 8 2020, 9:14 AM · Restricted Project, Restricted Project

Apr 6 2020

pratlucas added a comment to D75903: [AArch64][CodeGen] Fixing stack alignment of HFA arguments on AArch64 PCS.

From the AAPCS64's Parameter Passing Rules section (https://github.com/ARM-software/abi-aa/blob/master/aapcs64/aapcs64.rst#642parameter-passing-rules), I believe the proposed handling is correct. The HFA related rules described in this section are:

Stage B – Pre-padding and extension of arguments
[...]
B.2 	If the argument type is an HFA or an HVA, then the argument is used unmodified.
[...]
Stage C – Assignment of arguments to registers and stack
[...]
C.2 	If the argument is an HFA or an HVA and there are sufficient unallocated SIMD and Floating-point registers (NSRN + number of members <= 8), then the argument is allocated to SIMD and Floating-point Registers (with one register per member of the HFA or HVA). The NSRN is incremented by the number of registers used. The argument has now been allocated.
C.3 	If the argument is an HFA or an HVA then the NSRN is set to 8 and the size of the argument is rounded up to the nearest multiple of 8 bytes.
C.4 	If the argument is an HFA, an HVA, a Quad-precision Floating-point or Short Vector Type then the NSAA is rounded up to the larger of 8 or the Natural Alignment of the argument’s type.
[...]

As per rule C.4, the argument should be allocated on the stack address rounded to the larger of 8 and its Natural Alignment, which is 32 according to what is specified by the Composite Types rules in sectoin 5.6 of that same document (https://github.com/ARM-software/abi-aa/blob/master/aapcs64/aapcs64.rst#composite-types):

5.6   Composite Types
[...]
- The natural alignment of a composite type is the maximum of each of the member alignments of the 'top-level' members of the composite type i.e. before any alignment adjustment of the entire composite is applied

In regards to the compatibility with other compilers, I'm not sure that following what seems to be an uncompliant behavior would be the best way to proceed. @rnk and @ostannard, what would be your take on this?

Apr 6 2020, 3:45 AM · Restricted Project, Restricted Project

Apr 2 2020

pratlucas committed rGe6cb4b659af9: [Clang][CodeGen] Fixing mismatch between memory layout and const expressions… (authored by pratlucas).
[Clang][CodeGen] Fixing mismatch between memory layout and const expressions…
Apr 2 2020, 4:19 AM
pratlucas closed D77048: [Clang][CodeGen] Fixing mismatch between memory layout and const expressions for oversized bitfields.
Apr 2 2020, 4:19 AM · Restricted Project