[MachineCombiner] Extend reassociation logic to handle inverse instructions

[asi-sc]

Summary

Machine combiner supports generic reassociation only of associative and
commutative instructions, for example (A + X) + Y => (X + Y) + A. However, we
can extend this generic support to handle patterns like
(X + A) - Y => (X - Y) + A), where - is the inverse of +.
This patch adds interface functions to process reassociation patterns of
associative/commutative instructions and their inverse variants with minimal
changes in backends.

[asi-sc]

Some support of add-sub reassociation was added to AArch64 in D124564. This patch generalizes this idea and makes implementation target-independent.

It also introduces one more invariant to machine combiner that is REASSOC_AX/XA_BY/YB patterns must be gathered only with standard mechanism (isAssociativeAndCommutative function, etc. ) if reassociation is performed by default implementation. This sounds reasonable for me: if we have custom pattern matcher, we must be ready to write custom reassociation. All targets except RISCV that use machine-combine do not contradict the new invariant. If this patch gets positive feedback, I'll change RISCV implementation accordingly. It will require a few changes.

There is a big diff for tests, but it is just a change in the order of operands in commutative instructions. This is required to generalize the transformation rules.

[pengfei]

Do we have any benefits in doing this? The diff in tests just show a swap of 2 source operands, which I think might have no impact to the performance.

[asi-sc]

In D136754#3885523, @pengfei wrote:

Do we have any benefits in doing this? The diff in tests just show a swap of 2 source operands, which I think might have no impact to the performance.

This is a general support in machine-combiner that provides functions to be overridden in backends. So, exactly this patch will not show performance changes. But I agree, I definitely must've demonstrated at least some performance measurements. So, if we implement basic support in RISCV and say that fsub is the inverse of fadd, then for Whetstone we have the following results:

N1 +8%
N2 +14%

Baseline

Loop content                  Result              MFLOPS      MOPS   Seconds

N1 floating point     -1.12398255667391900       284.545              0.694
N2 floating point     -1.12187079889295083       224.314              6.162
N3 if then else        1.00000000000000000                5715.791    0.186
N4 fixed point        12.00000000000000000               323977497.600    0.000
N5 sin,cos etc.        0.49902937281518078                  20.796   41.147
N6 floating point      0.99999987890802811       169.611             32.708
N7 assignments         3.00000000000000000                7136.783    0.266
N8 exp,sqrt etc.       0.75100163018453681                  21.396   17.882

MWIPS                                           1038.403             99.046

This patch + RISCV support

Loop content                  Result              MFLOPS      MOPS   Seconds

N1 floating point     -1.12398255667392588       308.002              0.652
N2 floating point     -1.12187079889289487       257.436              5.460
N3 if then else        1.00000000000000000                5714.154    0.189
N4 fixed point        12.00000000000000000               299507735.273    0.000
N5 sin,cos etc.        0.49902937281518078                  20.861   41.714
N6 floating point      0.99999987890802811       170.068             33.173
N7 assignments         3.00000000000000000                7176.013    0.269
N8 exp,sqrt etc.       0.75100163018453681                  21.117   18.425

MWIPS                                           1047.136             99.882

Compilation flags -O3 -funroll-loops -finline-functions -ffast-math -mtune=sifive-u74

[craig.topper]

llvm/include/llvm/CodeGen/TargetInstrInfo.h

1181

I'm not sure we should mention mul/div here. I don't think you can reassociate them the same way.

1183

Can we make getInverseOpcode return an Optional<unsigned> so we can merge hasInverseOpcode and getInverseOpcode?

1195

Can we not figure this out using getInverseOpcode?

llvm/lib/CodeGen/TargetInstrInfo.cpp

835

Incorrectly*

[asi-sc]

llvm/include/llvm/CodeGen/TargetInstrInfo.h

1181

Do you mean division by zero cases, e.g. (A / X) * 0 --> A / (X / 0) ? We must not introduce new divisors and then it will be legal. Am I missing something?
If we don't have any other problems with mul/div, I'll fix reassociation patterns.

1183

Yeah, I'll do that. My original implementation used Optional, but then I decided that two functions were clearer solution for the interface. However, now I see that having Optional is better than these ugly reminders in the comments.

1195

Do you suggest changing isAssociativeAndCommutative to take not only an instruction, but an opcode as well? This seems to spoil the readability of its interface. However, this will simplify the implementation.

llvm/lib/CodeGen/TargetInstrInfo.cpp

857

This is incorrect. Must be Y - (A - X) => (Y + X) - A

[asi-sc]

@craig.topper , may I ask you to take a look at the questions from my previous comment (https://reviews.llvm.org/D136754#3898721) ? It'll help me to resolve original comments properly.

[asi-sc]

Address review comments:

• fix typos
• merge hasInverseOpcode and getInverseOpcode
• drop mentions of mul/div reassociation

[asi-sc]

llvm/include/llvm/CodeGen/TargetInstrInfo.h

1181

Disregard my previous comment. I agree we should not mention mul/div here as we cannot guarantee transformation safety.

1183

Thanks, done.

1195

I left this unchanged for now and uploaded a patch that shows how it looks like in the current design D138660 . If there is still a desire to merge isInverseInstAssociativeAndCommutative with isAssociativeAndCommutative, then we should change the latter to take not only the instruction, but the opcode as well

/// Return true when \P Inst with \P Opcode is both associative and commutative.
virtual bool isAssociativeAndCommutative(const MachineInstr &Inst, unsinged Opcode) const;

which seems to me pretty unclear from the user's point of view of this interface.

[craig.topper]

llvm/include/llvm/CodeGen/TargetInstrInfo.h

1195

Nevermind. My suggestion. I realize now that it requires the instruction to exist with the inverted opcode.

Would it make sense to pass an Invert bool to isAssociativeAndCommutative so we don't need to two interfaces?

[asi-sc]

Address comments: pass bool flag to isAssociativeAndCommutative

[asi-sc]

llvm/include/llvm/CodeGen/TargetInstrInfo.h

1195

Good suggestion, thanks! I've added Invert bool flag. One thing I'd like to mention explicitly is that I've added the default value to Invert argument. In general, it's dangerous in C++ to combine virtual functions and default argument values. However, I can't imagine the situation when a specific target decides to use another default value for the argument as it'll break machine combiner logic. So, exactly in this case I think it's completely safe.

[asi-sc]

Change Optional to std::optional, rebase

[craig.topper]

llvm/include/llvm/CodeGen/TargetInstrInfo.h

1183

std::nullopt?

llvm/lib/CodeGen/TargetInstrInfo.cpp

748

Add /*Invert*/ before true

761

Add /*Invert*/ before true

[asi-sc]

Address review comments

[craig.topper]

LGTM

llvm/include/llvm/CodeGen/TargetInstrInfo.h

public:
 
   /// Return true if the input \P Inst is part of a chain of dependent ops
   /// that are suitable for reassociation, otherwise return false.
   /// If the instruction's operands must be commuted to have a previous
   /// instruction of the same type define the first source operand, \P Commuted
   /// will be set to true.
   bool isReassociationCandidate(const MachineInstr &Inst, bool &Commuted) const;
 
-  /// Return true when \P Inst is both associative and commutative.
-  virtual bool isAssociativeAndCommutative(const MachineInstr &Inst) const {
+  /// Return true when \P Inst is both associative and commutative. If \P Invert
+  /// is true, then the inverse of \P Inst operation must be tested.
+  virtual bool isAssociativeAndCommutative(const MachineInstr &Inst,
+                                           bool Invert = false) const {
     return false;
   }
 
+  /// Return the inverse operation opcode if it exists for \P Opcode (e.g. add
+  /// for sub and vice versa).
+  virtual std::optional<unsigned> getInverseOpcode(unsigned Opcode) const {
+    return std::nullopt;
+  }
+
+  /// Return true when \P Opcode1 or its inversion is equal to \P Opcode2.
+  bool areOpcodesEqualOrInverse(unsigned Opcode1, unsigned Opcode2) const;
+
   /// Return true when \P Inst has reassociable operands in the same \P MBB.
   virtual bool hasReassociableOperands(const MachineInstr &Inst,
                                        const MachineBasicBlock *MBB) const;
 
   /// Return true when \P Inst has reassociable sibling.
   virtual bool hasReassociableSibling(const MachineInstr &Inst,
                                       bool &Commuted) const;
 
   /// When getMachineCombinerPatterns() finds patterns, this function generates
   /// the instructions that could replace the original code sequence. The client
   /// has to decide whether the actual replacement is beneficial or not.
   /// \param Root - Instruction that could be combined with one of its operands
   /// \param Pattern - Combination pattern for Root
   /// \param InsInstrs - Vector of new instructions that implement P
   /// \param DelInstrs - Old instructions, including Root, that could be
public:
   /// Attempt to reassociate \P Root and \P Prev according to \P Pattern to
   /// reduce critical path length.
   void reassociateOps(MachineInstr &Root, MachineInstr &Prev,
                       MachineCombinerPattern Pattern,
                       SmallVectorImpl<MachineInstr *> &InsInstrs,
                       SmallVectorImpl<MachineInstr *> &DelInstrs,
                       DenseMap<unsigned, unsigned> &InstrIdxForVirtReg) const;
 
+  /// Reassociation of some instructions requires inverse operations (e.g.
+  /// (X + A) - Y => (X - Y) + A). This method returns a pair of new opcodes
+  /// (new root opcode, new prev opcode) that must be used to reassociate \P
+  /// Root and \P Prev accoring to \P Pattern.
+  std::pair<unsigned, unsigned>
+  getReassociationOpcodes(MachineCombinerPattern Pattern,
+                          const MachineInstr &Root,
+                          const MachineInstr &Prev) const;
+
   /// The limit on resource length extension we accept in MachineCombiner Pass.
   virtual int getExtendResourceLenLimit() const { return 0; }
 
   /// This is an architecture-specific helper function of reassociateOps.
   /// Set special operand attributes for new instructions after reassociation.
   virtual void setSpecialOperandAttr(MachineInstr &OldMI1, MachineInstr &OldMI2,
                                      MachineInstr &NewMI1,
                                      MachineInstr &NewMI2) const {}

llvm/lib/CodeGen/TargetInstrInfo.cpp

if (Op1.isReg() && Register::isVirtualRegister(Op1.getReg()))
     MI1 = MRI.getUniqueVRegDef(Op1.getReg());
   if (Op2.isReg() && Register::isVirtualRegister(Op2.getReg()))
     MI2 = MRI.getUniqueVRegDef(Op2.getReg());
 
   // And they need to be in the trace (otherwise, they won't have a depth).
   return MI1 && MI2 && MI1->getParent() == MBB && MI2->getParent() == MBB;
 }
 
+bool TargetInstrInfo::areOpcodesEqualOrInverse(unsigned Opcode1,
+                                               unsigned Opcode2) const {
+  return Opcode1 == Opcode2 || getInverseOpcode(Opcode1) == Opcode2;
+}
+
 bool TargetInstrInfo::hasReassociableSibling(const MachineInstr &Inst,
                                              bool &Commuted) const {
   const MachineBasicBlock *MBB = Inst.getParent();
   const MachineRegisterInfo &MRI = MBB->getParent()->getRegInfo();
   MachineInstr *MI1 = MRI.getUniqueVRegDef(Inst.getOperand(1).getReg());
   MachineInstr *MI2 = MRI.getUniqueVRegDef(Inst.getOperand(2).getReg());
-  unsigned AssocOpcode = Inst.getOpcode();
+  unsigned Opcode = Inst.getOpcode();
 
-  // If only one operand has the same opcode and it's the second source operand,
-  // the operands must be commuted.
-  Commuted = MI1->getOpcode() != AssocOpcode && MI2->getOpcode() == AssocOpcode;
+  // If only one operand has the same or inverse opcode and it's the second
+  // source operand, the operands must be commuted.
+  Commuted = !areOpcodesEqualOrInverse(Opcode, MI1->getOpcode()) &&
+             areOpcodesEqualOrInverse(Opcode, MI2->getOpcode());
   if (Commuted)
     std::swap(MI1, MI2);
 
   // 1. The previous instruction must be the same type as Inst.
-  // 2. The previous instruction must also be associative/commutative (this can
-  //    be different even for instructions with the same opcode if traits like
-  //    fast-math-flags are included).
+  // 2. The previous instruction must also be associative/commutative or be the
+  //    inverse of such an operation (this can be different even for
+  //    instructions with the same opcode if traits like fast-math-flags are
+  //    included).
   // 3. The previous instruction must have virtual register definitions for its
   //    operands in the same basic block as Inst.
   // 4. The previous instruction's result must only be used by Inst.
-  return MI1->getOpcode() == AssocOpcode && isAssociativeAndCommutative(*MI1) &&
+  return areOpcodesEqualOrInverse(Opcode, MI1->getOpcode()) &&
+         (isAssociativeAndCommutative(*MI1) ||
+          isAssociativeAndCommutative(*MI1, /* Invert */ true)) &&
          hasReassociableOperands(*MI1, MBB) &&
          MRI.hasOneNonDBGUse(MI1->getOperand(0).getReg());
 }
 
-// 1. The operation must be associative and commutative.
+// 1. The operation must be associative and commutative or be the inverse of
+//    such an operation.
 // 2. The instruction must have virtual register definitions for its
 //    operands in the same basic block.
 // 3. The instruction must have a reassociable sibling.
 bool TargetInstrInfo::isReassociationCandidate(const MachineInstr &Inst,
                                                bool &Commuted) const {
-  return isAssociativeAndCommutative(Inst) &&
+  return (isAssociativeAndCommutative(Inst) ||
+          isAssociativeAndCommutative(Inst, /* Invert */ true)) &&
          hasReassociableOperands(Inst, Inst.getParent()) &&
          hasReassociableSibling(Inst, Commuted);
 }
 
 // The concept of the reassociation pass is that these operations can benefit
 // from this kind of transformation:
 //
 // A = ? op ?

 }
 
 /// Return true when a code sequence can improve loop throughput.
 bool
 TargetInstrInfo::isThroughputPattern(MachineCombinerPattern Pattern) const {
   return false;
 }
 
+std::pair<unsigned, unsigned>
+TargetInstrInfo::getReassociationOpcodes(MachineCombinerPattern Pattern,
+                                         const MachineInstr &Root,
+                                         const MachineInstr &Prev) const {
+  bool AssocCommutRoot = isAssociativeAndCommutative(Root);
+  bool AssocCommutPrev = isAssociativeAndCommutative(Prev);
+
+  // Early exit if both opcodes are associative and commutative. It's a trivial
+  // reassociation when we only change operands order. In this case opcodes are
+  // not required to have inverse versions.
+  if (AssocCommutRoot && AssocCommutPrev) {
+    assert(Root.getOpcode() == Prev.getOpcode() && "Expected to be equal");
+    return std::make_pair(Root.getOpcode(), Root.getOpcode());
+  }
+
+  // At least one instruction is not associative or commutative.
+  // Since we have matched one of the reassociation patterns, we expect that the
+  // instructions' opcodes are equal or one of them is the inversion of the
+  // other.
+  assert(areOpcodesEqualOrInverse(Root.getOpcode(), Prev.getOpcode()) &&
+         "Incorrectly matched pattern");
+  unsigned AssocCommutOpcode = Root.getOpcode();
+  unsigned InverseOpcode = getInverseOpcode(Root.getOpcode()).value();
+  if (!AssocCommutRoot)
+    std::swap(AssocCommutOpcode, InverseOpcode);
+
+  // The transformation rule (`+` is any associative and commutative binary
+  // operation, `-` is the inverse):
+  // REASSOC_AX_BY:
+  //   (A + X) + Y => A + (X + Y)
+  //   (A + X) - Y => A + (X - Y)
+  //   (A - X) + Y => A - (X - Y)
+  //   (A - X) - Y => A - (X + Y)
+  // REASSOC_XA_BY:
+  //   (X + A) + Y => (X + Y) + A
+  //   (X + A) - Y => (X - Y) + A
+  //   (X - A) + Y => (X + Y) - A
+  //   (X - A) - Y => (X - Y) - A
+  // REASSOC_AX_YB:
+  //   Y + (A + X) => (Y + X) + A
+  //   Y - (A + X) => (Y - X) - A
+  //   Y + (A - X) => (Y - X) + A
+  //   Y - (A - X) => (Y + X) - A
+  // REASSOC_XA_YB:
+  //   Y + (X + A) => (Y + X) + A
+  //   Y - (X + A) => (Y - X) - A
+  //   Y + (X - A) => (Y + X) - A
+  //   Y - (X - A) => (Y - X) + A
+  switch (Pattern) {
+  default:
+    llvm_unreachable("Unexpected pattern");
+  case MachineCombinerPattern::REASSOC_AX_BY:
+    if (!AssocCommutRoot && AssocCommutPrev)
+      return {AssocCommutOpcode, InverseOpcode};
+    if (AssocCommutRoot && !AssocCommutPrev)
+      return {InverseOpcode, InverseOpcode};
+    if (!AssocCommutRoot && !AssocCommutPrev)
+      return {InverseOpcode, AssocCommutOpcode};
+    break;
+  case MachineCombinerPattern::REASSOC_XA_BY:
+    if (!AssocCommutRoot && AssocCommutPrev)
+      return {AssocCommutOpcode, InverseOpcode};
+    if (AssocCommutRoot && !AssocCommutPrev)
+      return {InverseOpcode, AssocCommutOpcode};
+    if (!AssocCommutRoot && !AssocCommutPrev)
+      return {InverseOpcode, InverseOpcode};
+    break;
+  case MachineCombinerPattern::REASSOC_AX_YB:
+    if (!AssocCommutRoot && AssocCommutPrev)
+      return {InverseOpcode, InverseOpcode};
+    if (AssocCommutRoot && !AssocCommutPrev)
+      return {AssocCommutOpcode, InverseOpcode};
+    if (!AssocCommutRoot && !AssocCommutPrev)
+      return {InverseOpcode, AssocCommutOpcode};
+    break;
+  case MachineCombinerPattern::REASSOC_XA_YB:
+    if (!AssocCommutRoot && AssocCommutPrev)
+      return {InverseOpcode, InverseOpcode};
+    if (AssocCommutRoot && !AssocCommutPrev)
+      return {InverseOpcode, AssocCommutOpcode};
+    if (!AssocCommutRoot && !AssocCommutPrev)
+      return {AssocCommutOpcode, InverseOpcode};
+    break;
+  }
+  llvm_unreachable("Unhandled combination");
+}
+
+// Return a pair of boolean flags showing if the new root and new prev operands
+// must be swapped. See visual example of the rule in
+// TargetInstrInfo::getReassociationOpcodes.
+static std::pair<bool, bool> mustSwapOperands(MachineCombinerPattern Pattern) {
+  switch (Pattern) {
+  default:
+    llvm_unreachable("Unexpected pattern");
+  case MachineCombinerPattern::REASSOC_AX_BY:
+    return {false, false};
+  case MachineCombinerPattern::REASSOC_XA_BY:
+    return {true, false};
+  case MachineCombinerPattern::REASSOC_AX_YB:
+    return {true, true};
+  case MachineCombinerPattern::REASSOC_XA_YB:
+    return {true, true};
+  }
+}
+
 /// Attempt the reassociation transformation to reduce critical path length.
 /// See the above comments before getMachineCombinerPatterns().
 void TargetInstrInfo::reassociateOps(
     MachineInstr &Root, MachineInstr &Prev,
     MachineCombinerPattern Pattern,
     SmallVectorImpl<MachineInstr *> &InsInstrs,
     SmallVectorImpl<MachineInstr *> &DelInstrs,
     DenseMap<unsigned, unsigned> &InstrIdxForVirtReg) const {
if (Register::isVirtualRegister(RegC))
     MRI.constrainRegClass(RegC, RC);
 
   // Create a new virtual register for the result of (X op Y) instead of
   // recycling RegB because the MachineCombiner's computation of the critical
   // path requires a new register definition rather than an existing one.
   Register NewVR = MRI.createVirtualRegister(RC);
   InstrIdxForVirtReg.insert(std::make_pair(NewVR, 0));
 
-  unsigned Opcode = Root.getOpcode();
+  auto [NewRootOpc, NewPrevOpc] = getReassociationOpcodes(Pattern, Root, Prev);
   bool KillA = OpA.isKill();
   bool KillX = OpX.isKill();
   bool KillY = OpY.isKill();
+  bool KillNewVR = true;
+
+  auto [SwapRootOperands, SwapPrevOperands] = mustSwapOperands(Pattern);
+
+  if (SwapPrevOperands) {
+    std::swap(RegX, RegY);
+    std::swap(KillX, KillY);
+  }
 
   // Create new instructions for insertion.
   MachineInstrBuilder MIB1 =
-      BuildMI(*MF, MIMetadata(Prev), TII->get(Opcode), NewVR)
+      BuildMI(*MF, MIMetadata(Prev), TII->get(NewPrevOpc), NewVR)
           .addReg(RegX, getKillRegState(KillX))
           .addReg(RegY, getKillRegState(KillY))
           .setMIFlags(Prev.getFlags());
+
+  if (SwapRootOperands) {
+    std::swap(RegA, NewVR);
+    std::swap(KillA, KillNewVR);
+  }
+
   MachineInstrBuilder MIB2 =
-      BuildMI(*MF, MIMetadata(Root), TII->get(Opcode), RegC)
+      BuildMI(*MF, MIMetadata(Root), TII->get(NewRootOpc), RegC)
           .addReg(RegA, getKillRegState(KillA))
-          .addReg(NewVR, getKillRegState(true))
+          .addReg(NewVR, getKillRegState(KillNewVR))
           .setMIFlags(Root.getFlags());
 
   setSpecialOperandAttr(Root, Prev, *MIB1, *MIB2);
 
   // Record new instructions for insertion and old instructions for deletion.
   InsInstrs.push_back(MIB1);
   InsInstrs.push_back(MIB2);
   DelInstrs.push_back(&Prev);

llvm/lib/Target/AArch64/AArch64InstrInfo.h

public:
   /// Return true when there is potentially a faster code sequence
   /// for an instruction chain ending in ``Root``. All potential patterns are
   /// listed in the ``Patterns`` array.
   bool
   getMachineCombinerPatterns(MachineInstr &Root,
                              SmallVectorImpl<MachineCombinerPattern> &Patterns,
                              bool DoRegPressureReduce) const override;
   /// Return true when Inst is associative and commutative so that it can be
-  /// reassociated.
-  bool isAssociativeAndCommutative(const MachineInstr &Inst) const override;
+  /// reassociated. If Invert is true, then the inverse of Inst operation must
+  /// be checked.
+  bool isAssociativeAndCommutative(const MachineInstr &Inst,
+                                   bool Invert) const override;
   /// When getMachineCombinerPatterns() finds patterns, this function generates
   /// the instructions that could replace the original code sequence
   void genAlternativeCodeSequence(
       MachineInstr &Root, MachineCombinerPattern Pattern,
       SmallVectorImpl<MachineInstr *> &InsInstrs,
       SmallVectorImpl<MachineInstr *> &DelInstrs,
       DenseMap<unsigned, unsigned> &InstrIdxForVirtReg) const override;
   /// AArch64 supports MachineCombiner.

llvm/lib/Target/AArch64/AArch64InstrInfo.cpp

static bool canCombineWithFMUL(MachineBasicBlock &MBB, MachineOperand &MO,
                                unsigned MulOpc) {
   return canCombine(MBB, MO, MulOpc);
 }
 
 // TODO: There are many more machine instruction opcodes to match:
 //       1. Other data types (integer, vectors)
 //       2. Other math / logic operations (xor, or)
 //       3. Other forms of the same operation (intrinsics and other variants)
-bool AArch64InstrInfo::isAssociativeAndCommutative(
-    const MachineInstr &Inst) const {
+bool AArch64InstrInfo::isAssociativeAndCommutative(const MachineInstr &Inst,
+                                                   bool Invert) const {
+  if (Invert)
+    return false;
   switch (Inst.getOpcode()) {
   case AArch64::FADDDrr:
   case AArch64::FADDSrr:
   case AArch64::FADDv2f32:
   case AArch64::FADDv2f64:
   case AArch64::FADDv4f32:
   case AArch64::FMULDrr:
   case AArch64::FMULSrr:

llvm/lib/Target/PowerPC/PPCInstrInfo.h

bool shouldReduceRegisterPressure(
       const RegisterClassInfo *RegClassInfo) const override;
 
   /// Fixup the placeholders we put in genAlternativeCodeSequence() for
   /// MachineCombiner.
   void
   finalizeInsInstrs(MachineInstr &Root, MachineCombinerPattern &P,
                     SmallVectorImpl<MachineInstr *> &InsInstrs) const override;
 
-  bool isAssociativeAndCommutative(const MachineInstr &Inst) const override;
+  bool isAssociativeAndCommutative(const MachineInstr &Inst,
+                                   bool Invert) const override;
 
   /// On PowerPC, we try to reassociate FMA chain which will increase
   /// instruction size. Set extension resource length limit to 1 for edge case.
   /// Resource Length is calculated by scaled resource usage in getCycles().
   /// Because of the division in getCycles(), it returns different cycles due to
   /// legacy scaled resource usage. So new resource length may be same with
   /// legacy or 1 bigger than legacy.
   /// We need to execlude the 1 bigger case even the resource length is not

llvm/lib/Target/PowerPC/PPCInstrInfo.cpp

void PPCInstrInfo::setSpecialOperandAttr(MachineInstr &MI,
   MI.clearFlag(MachineInstr::MIFlag::IsExact);
 }
 
 // This function does not list all associative and commutative operations, but
 // only those worth feeding through the machine combiner in an attempt to
 // reduce the critical path. Mostly, this means floating-point operations,
 // because they have high latencies(>=5) (compared to other operations, such as
 // and/or, which are also associative and commutative, but have low latencies).
-bool PPCInstrInfo::isAssociativeAndCommutative(const MachineInstr &Inst) const {
+bool PPCInstrInfo::isAssociativeAndCommutative(const MachineInstr &Inst,
+                                               bool Invert) const {
+  if (Invert)
+    return false;
   switch (Inst.getOpcode()) {
   // Floating point:
   // FP Add:
   case PPC::FADD:
   case PPC::FADDS:
   // FP Multiply:
   case PPC::FMUL:
   case PPC::FMULS:

llvm/lib/Target/RISCV/RISCVInstrInfo.h

void genAlternativeCodeSequence(
       MachineInstr &Root, MachineCombinerPattern Pattern,
       SmallVectorImpl<MachineInstr *> &InsInstrs,
       SmallVectorImpl<MachineInstr *> &DelInstrs,
       DenseMap<unsigned, unsigned> &InstrIdxForVirtReg) const override;
 
   bool hasReassociableSibling(const MachineInstr &Inst,
                               bool &Commuted) const override;
 
-  bool isAssociativeAndCommutative(const MachineInstr &Inst) const override;
+  bool isAssociativeAndCommutative(const MachineInstr &Inst,
+                                   bool Invert) const override;
 
 protected:
   const RISCVSubtarget &STI;
 };
 
 namespace RISCV {
 
 // Returns true if this is the sext.w pattern, addiw rd, rs1, 0.

llvm/lib/Target/RISCV/RISCVInstrInfo.cpp

bool RISCVInstrInfo::hasReassociableSibling(const MachineInstr &Inst,
   const MachineRegisterInfo &MRI = Inst.getMF()->getRegInfo();
   unsigned OperandIdx = Commuted ? 2 : 1;
   const MachineInstr &Sibling =
       *MRI.getVRegDef(Inst.getOperand(OperandIdx).getReg());
 
   return RISCV::hasEqualFRM(Inst, Sibling);
 }
 
-bool RISCVInstrInfo::isAssociativeAndCommutative(
-    const MachineInstr &Inst) const {
+bool RISCVInstrInfo::isAssociativeAndCommutative(const MachineInstr &Inst,
+                                                 bool Invert) const {
   unsigned Opc = Inst.getOpcode();
+  if (Invert)
+    return false;
+
   if (isFADD(Opc) || isFMUL(Opc))
     return Inst.getFlag(MachineInstr::MIFlag::FmReassoc) &&
            Inst.getFlag(MachineInstr::MIFlag::FmNsz);
   return false;
 }
 
 static bool canCombineFPFusedMultiply(const MachineInstr &Root,
                                       const MachineOperand &MO,

llvm/lib/Target/X86/X86InstrInfo.h

public:
   bool hasHighOperandLatency(const TargetSchedModel &SchedModel,
                              const MachineRegisterInfo *MRI,
                              const MachineInstr &DefMI, unsigned DefIdx,
                              const MachineInstr &UseMI,
                              unsigned UseIdx) const override;
 
   bool useMachineCombiner() const override { return true; }
 
-  bool isAssociativeAndCommutative(const MachineInstr &Inst) const override;
+  bool isAssociativeAndCommutative(const MachineInstr &Inst,
+                                   bool Invert) const override;
 
   bool hasReassociableOperands(const MachineInstr &Inst,
                                const MachineBasicBlock *MBB) const override;
 
   void setSpecialOperandAttr(MachineInstr &OldMI1, MachineInstr &OldMI2,
                              MachineInstr &NewMI1,
                              MachineInstr &NewMI2) const override;
 

llvm/lib/Target/X86/X86InstrInfo.cpp

bool X86InstrInfo::hasReassociableOperands(const MachineInstr &Inst,
 
   return TargetInstrInfo::hasReassociableOperands(Inst, MBB);
 }
 
 // TODO: There are many more machine instruction opcodes to match:
 //       1. Other data types (integer, vectors)
 //       2. Other math / logic operations (xor, or)
 //       3. Other forms of the same operation (intrinsics and other variants)
-bool X86InstrInfo::isAssociativeAndCommutative(const MachineInstr &Inst) const {
+bool X86InstrInfo::isAssociativeAndCommutative(const MachineInstr &Inst,
+                                               bool Invert) const {
+  if (Invert)
+    return false;
   switch (Inst.getOpcode()) {
   case X86::ADD8rr:
   case X86::ADD16rr:
   case X86::ADD32rr:
   case X86::ADD64rr:
   case X86::AND8rr:
   case X86::AND16rr:
   case X86::AND32rr:

llvm/test/CodeGen/AArch64/GlobalISel/arm64-atomic.ll

 ; CHECK-NOLSE-O1-LABEL: atomic_load_relaxed_8:
 ; CHECK-NOLSE-O1:       ; %bb.0:
 ; CHECK-NOLSE-O1-NEXT:    add x8, x0, #291, lsl #12 ; =1191936
 ; CHECK-NOLSE-O1-NEXT:    ldrb w9, [x0, #4095]
 ; CHECK-NOLSE-O1-NEXT:    ldrb w10, [x0, w1, sxtw]
 ; CHECK-NOLSE-O1-NEXT:    ldurb w11, [x0, #-256]
 ; CHECK-NOLSE-O1-NEXT:    ldrb w8, [x8]
 ; CHECK-NOLSE-O1-NEXT:    add w9, w9, w11
-; CHECK-NOLSE-O1-NEXT:    add w9, w10, w9
+; CHECK-NOLSE-O1-NEXT:    add w9, w9, w10
 ; CHECK-NOLSE-O1-NEXT:    add w0, w9, w8
 ; CHECK-NOLSE-O1-NEXT:    ret
 ;
 ; CHECK-NOLSE-O0-LABEL: atomic_load_relaxed_8:
 ; CHECK-NOLSE-O0:       ; %bb.0:
 ; CHECK-NOLSE-O0-NEXT:    ldrb w9, [x0, #4095]
 ; CHECK-NOLSE-O0-NEXT:    add x8, x0, w1, sxtw
 ; CHECK-NOLSE-O0-NEXT:    ldrb w8, [x8]
 ; CHECK-NOLSE-O0-NEXT:    add w8, w8, w9, uxtb
 ; CHECK-NOLSE-O0-NEXT:    subs x9, x0, #256
 ; CHECK-NOLSE-O0-NEXT:    ldrb w9, [x9]
 ; CHECK-NOLSE-O0-NEXT:    add w8, w8, w9, uxtb
 ; CHECK-NOLSE-O0-NEXT:    add x9, x0, #291, lsl #12 ; =1191936
 ; CHECK-NOLSE-O0-NEXT:    ldrb w9, [x9]
 ; CHECK-NOLSE-O0-NEXT:    add w0, w8, w9, uxtb
 ; CHECK-NOLSE-O0-NEXT:    ret
 ;
 ; CHECK-LSE-O1-LABEL: atomic_load_relaxed_8:
 ; CHECK-LSE-O1:       ; %bb.0:
 ; CHECK-LSE-O1-NEXT:    ldrb w8, [x0, #4095]
 ; CHECK-LSE-O1-NEXT:    ldrb w9, [x0, w1, sxtw]
 ; CHECK-LSE-O1-NEXT:    ldurb w10, [x0, #-256]
 ; CHECK-LSE-O1-NEXT:    add w8, w8, w10
-; CHECK-LSE-O1-NEXT:    add w8, w9, w8
+; CHECK-LSE-O1-NEXT:    add w8, w8, w9
 ; CHECK-LSE-O1-NEXT:    add x9, x0, #291, lsl #12 ; =1191936
 ; CHECK-LSE-O1-NEXT:    ldrb w9, [x9]
 ; CHECK-LSE-O1-NEXT:    add w0, w8, w9
 ; CHECK-LSE-O1-NEXT:    ret
 ;
 ; CHECK-LSE-O0-LABEL: atomic_load_relaxed_8:
 ; CHECK-LSE-O0:       ; %bb.0:
 ; CHECK-LSE-O0-NEXT:    ldrb w9, [x0, #4095]

 ; CHECK-NOLSE-O1-LABEL: atomic_load_relaxed_16:
 ; CHECK-NOLSE-O1:       ; %bb.0:
 ; CHECK-NOLSE-O1-NEXT:    add x8, x0, #291, lsl #12 ; =1191936
 ; CHECK-NOLSE-O1-NEXT:    ldrh w9, [x0, #8190]
 ; CHECK-NOLSE-O1-NEXT:    ldrh w10, [x0, w1, sxtw #1]
 ; CHECK-NOLSE-O1-NEXT:    ldurh w11, [x0, #-256]
 ; CHECK-NOLSE-O1-NEXT:    ldrh w8, [x8]
 ; CHECK-NOLSE-O1-NEXT:    add w9, w9, w11
-; CHECK-NOLSE-O1-NEXT:    add w9, w10, w9
+; CHECK-NOLSE-O1-NEXT:    add w9, w9, w10
 ; CHECK-NOLSE-O1-NEXT:    add w0, w9, w8
 ; CHECK-NOLSE-O1-NEXT:    ret
 ;
 ; CHECK-NOLSE-O0-LABEL: atomic_load_relaxed_16:
 ; CHECK-NOLSE-O0:       ; %bb.0:
 ; CHECK-NOLSE-O0-NEXT:    ldrh w9, [x0, #8190]
 ; CHECK-NOLSE-O0-NEXT:    add x8, x0, w1, sxtw #1
 ; CHECK-NOLSE-O0-NEXT:    ldrh w8, [x8]
 ; CHECK-NOLSE-O0-NEXT:    add w8, w8, w9, uxth
 ; CHECK-NOLSE-O0-NEXT:    subs x9, x0, #256
 ; CHECK-NOLSE-O0-NEXT:    ldrh w9, [x9]
 ; CHECK-NOLSE-O0-NEXT:    add w8, w8, w9, uxth
 ; CHECK-NOLSE-O0-NEXT:    add x9, x0, #291, lsl #12 ; =1191936
 ; CHECK-NOLSE-O0-NEXT:    ldrh w9, [x9]
 ; CHECK-NOLSE-O0-NEXT:    add w0, w8, w9, uxth
 ; CHECK-NOLSE-O0-NEXT:    ret
 ;
 ; CHECK-LSE-O1-LABEL: atomic_load_relaxed_16:
 ; CHECK-LSE-O1:       ; %bb.0:
 ; CHECK-LSE-O1-NEXT:    ldrh w8, [x0, #8190]
 ; CHECK-LSE-O1-NEXT:    ldrh w9, [x0, w1, sxtw #1]
 ; CHECK-LSE-O1-NEXT:    ldurh w10, [x0, #-256]
 ; CHECK-LSE-O1-NEXT:    add w8, w8, w10
-; CHECK-LSE-O1-NEXT:    add w8, w9, w8
+; CHECK-LSE-O1-NEXT:    add w8, w8, w9
 ; CHECK-LSE-O1-NEXT:    add x9, x0, #291, lsl #12 ; =1191936
 ; CHECK-LSE-O1-NEXT:    ldrh w9, [x9]
 ; CHECK-LSE-O1-NEXT:    add w0, w8, w9
 ; CHECK-LSE-O1-NEXT:    ret
 ;
 ; CHECK-LSE-O0-LABEL: atomic_load_relaxed_16:
 ; CHECK-LSE-O0:       ; %bb.0:
 ; CHECK-LSE-O0-NEXT:    ldrh w9, [x0, #8190]

 ; CHECK-NOLSE-O1-LABEL: atomic_load_relaxed_32:
 ; CHECK-NOLSE-O1:       ; %bb.0:
 ; CHECK-NOLSE-O1-NEXT:    add x8, x0, #291, lsl #12 ; =1191936
 ; CHECK-NOLSE-O1-NEXT:    ldr w9, [x0, #16380]
 ; CHECK-NOLSE-O1-NEXT:    ldr w10, [x0, w1, sxtw #2]
 ; CHECK-NOLSE-O1-NEXT:    ldur w11, [x0, #-256]
 ; CHECK-NOLSE-O1-NEXT:    ldr w8, [x8]
 ; CHECK-NOLSE-O1-NEXT:    add w9, w9, w11
-; CHECK-NOLSE-O1-NEXT:    add w9, w10, w9
+; CHECK-NOLSE-O1-NEXT:    add w9, w9, w10
 ; CHECK-NOLSE-O1-NEXT:    add w0, w9, w8
 ; CHECK-NOLSE-O1-NEXT:    ret
 ;
 ; CHECK-NOLSE-O0-LABEL: atomic_load_relaxed_32:
 ; CHECK-NOLSE-O0:       ; %bb.0:
 ; CHECK-NOLSE-O0-NEXT:    ldr w8, [x0, #16380]
 ; CHECK-NOLSE-O0-NEXT:    ldr w9, [x0, w1, sxtw #2]
 ; CHECK-NOLSE-O0-NEXT:    add w8, w8, w9
 ; CHECK-NOLSE-O0-NEXT:    ldur w9, [x0, #-256]
 ; CHECK-NOLSE-O0-NEXT:    add w8, w8, w9
 ; CHECK-NOLSE-O0-NEXT:    add x9, x0, #291, lsl #12 ; =1191936
 ; CHECK-NOLSE-O0-NEXT:    ldr w9, [x9]
 ; CHECK-NOLSE-O0-NEXT:    add w0, w8, w9
 ; CHECK-NOLSE-O0-NEXT:    ret
 ;
 ; CHECK-LSE-O1-LABEL: atomic_load_relaxed_32:
 ; CHECK-LSE-O1:       ; %bb.0:
 ; CHECK-LSE-O1-NEXT:    ldr w8, [x0, #16380]
 ; CHECK-LSE-O1-NEXT:    ldr w9, [x0, w1, sxtw #2]
 ; CHECK-LSE-O1-NEXT:    ldur w10, [x0, #-256]
 ; CHECK-LSE-O1-NEXT:    add w8, w8, w10
-; CHECK-LSE-O1-NEXT:    add w8, w9, w8
+; CHECK-LSE-O1-NEXT:    add w8, w8, w9
 ; CHECK-LSE-O1-NEXT:    add x9, x0, #291, lsl #12 ; =1191936
 ; CHECK-LSE-O1-NEXT:    ldr w9, [x9]
 ; CHECK-LSE-O1-NEXT:    add w0, w8, w9
 ; CHECK-LSE-O1-NEXT:    ret
 ;
 ; CHECK-LSE-O0-LABEL: atomic_load_relaxed_32:
 ; CHECK-LSE-O0:       ; %bb.0:
 ; CHECK-LSE-O0-NEXT:    ldr w8, [x0, #16380]

 ; CHECK-NOLSE-O1-LABEL: atomic_load_relaxed_64:
 ; CHECK-NOLSE-O1:       ; %bb.0:
 ; CHECK-NOLSE-O1-NEXT:    add x8, x0, #291, lsl #12 ; =1191936
 ; CHECK-NOLSE-O1-NEXT:    ldr x9, [x0, #32760]
 ; CHECK-NOLSE-O1-NEXT:    ldr x10, [x0, w1, sxtw #3]
 ; CHECK-NOLSE-O1-NEXT:    ldur x11, [x0, #-256]
 ; CHECK-NOLSE-O1-NEXT:    ldr x8, [x8]
 ; CHECK-NOLSE-O1-NEXT:    add x9, x9, x11
-; CHECK-NOLSE-O1-NEXT:    add x9, x10, x9
+; CHECK-NOLSE-O1-NEXT:    add x9, x9, x10
 ; CHECK-NOLSE-O1-NEXT:    add x0, x9, x8
 ; CHECK-NOLSE-O1-NEXT:    ret
 ;
 ; CHECK-NOLSE-O0-LABEL: atomic_load_relaxed_64:
 ; CHECK-NOLSE-O0:       ; %bb.0:
 ; CHECK-NOLSE-O0-NEXT:    ldr x8, [x0, #32760]
 ; CHECK-NOLSE-O0-NEXT:    ldr x9, [x0, w1, sxtw #3]
 ; CHECK-NOLSE-O0-NEXT:    add x8, x8, x9
 ; CHECK-NOLSE-O0-NEXT:    ldur x9, [x0, #-256]
 ; CHECK-NOLSE-O0-NEXT:    add x8, x8, x9
 ; CHECK-NOLSE-O0-NEXT:    add x9, x0, #291, lsl #12 ; =1191936
 ; CHECK-NOLSE-O0-NEXT:    ldr x9, [x9]
 ; CHECK-NOLSE-O0-NEXT:    add x0, x8, x9
 ; CHECK-NOLSE-O0-NEXT:    ret
 ;
 ; CHECK-LSE-O1-LABEL: atomic_load_relaxed_64:
 ; CHECK-LSE-O1:       ; %bb.0:
 ; CHECK-LSE-O1-NEXT:    ldr x8, [x0, #32760]
 ; CHECK-LSE-O1-NEXT:    ldr x9, [x0, w1, sxtw #3]
 ; CHECK-LSE-O1-NEXT:    ldur x10, [x0, #-256]
 ; CHECK-LSE-O1-NEXT:    add x8, x8, x10
-; CHECK-LSE-O1-NEXT:    add x8, x9, x8
+; CHECK-LSE-O1-NEXT:    add x8, x8, x9
 ; CHECK-LSE-O1-NEXT:    add x9, x0, #291, lsl #12 ; =1191936
 ; CHECK-LSE-O1-NEXT:    ldr x9, [x9]
 ; CHECK-LSE-O1-NEXT:    add x0, x8, x9
 ; CHECK-LSE-O1-NEXT:    ret
 ;
 ; CHECK-LSE-O0-LABEL: atomic_load_relaxed_64:
 ; CHECK-LSE-O0:       ; %bb.0:
 ; CHECK-LSE-O0-NEXT:    ldr x8, [x0, #32760]

llvm/test/CodeGen/AArch64/GlobalISel/arm64-pcsections.ll

define i8 @atomic_load_relaxed_8(ptr %p, i32 %off32) {
   ; CHECK: bb.0 (%ir-block.0):
   ; CHECK-NEXT:   liveins: $w1, $x0
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT:   renamable $x8 = ADDXri renamable $x0, 291, 12
   ; CHECK-NEXT:   renamable $w9 = LDRBBui renamable $x0, 4095, pcsections !0 :: (load monotonic (s8) from %ir.ptr_unsigned)
   ; CHECK-NEXT:   renamable $w10 = LDRBBroW renamable $x0, killed renamable $w1, 1, 0, pcsections !0 :: (load unordered (s8) from %ir.ptr_regoff)
   ; CHECK-NEXT:   renamable $w11 = LDURBBi killed renamable $x0, -256, pcsections !0 :: (load monotonic (s8) from %ir.ptr_unscaled)
   ; CHECK-NEXT:   renamable $w8 = LDRBBui killed renamable $x8, 0, pcsections !0 :: (load unordered (s8) from %ir.ptr_random)
-  ; CHECK-NEXT:   $w9 = ADDWrs killed renamable $w9, killed renamable $w11, 0
-  ; CHECK-NEXT:   $w9 = ADDWrs killed renamable $w10, killed renamable $w9, 0
+  ; CHECK-NEXT:   $w9 = ADDWrs killed renamable $w9, killed renamable $w11, 0, pcsections !0
+  ; CHECK-NEXT:   $w9 = ADDWrs killed renamable $w9, killed renamable $w10, 0, pcsections !0
   ; CHECK-NEXT:   $w0 = ADDWrs killed renamable $w9, killed renamable $w8, 0, pcsections !0
   ; CHECK-NEXT:   RET undef $lr, implicit $w0
   %ptr_unsigned = getelementptr i8, ptr %p, i32 4095
   %val_unsigned = load atomic i8, ptr %ptr_unsigned monotonic, align 1, !pcsections !0
 
   %ptr_regoff = getelementptr i8, ptr %p, i32 %off32
   %val_regoff = load atomic i8, ptr %ptr_regoff unordered, align 1, !pcsections !0
   %tot1 = add i8 %val_unsigned, %val_regoff, !pcsections !0
define i16 @atomic_load_relaxed_16(ptr %p, i32 %off32) {
   ; CHECK: bb.0 (%ir-block.0):
   ; CHECK-NEXT:   liveins: $w1, $x0
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT:   renamable $x8 = ADDXri renamable $x0, 291, 12
   ; CHECK-NEXT:   renamable $w9 = LDRHHui renamable $x0, 4095, pcsections !0 :: (load monotonic (s16) from %ir.ptr_unsigned)
   ; CHECK-NEXT:   renamable $w10 = LDRHHroW renamable $x0, killed renamable $w1, 1, 1, pcsections !0 :: (load unordered (s16) from %ir.ptr_regoff)
   ; CHECK-NEXT:   renamable $w11 = LDURHHi killed renamable $x0, -256, pcsections !0 :: (load monotonic (s16) from %ir.ptr_unscaled)
   ; CHECK-NEXT:   renamable $w8 = LDRHHui killed renamable $x8, 0, pcsections !0 :: (load unordered (s16) from %ir.ptr_random)
-  ; CHECK-NEXT:   $w9 = ADDWrs killed renamable $w9, killed renamable $w11, 0
-  ; CHECK-NEXT:   $w9 = ADDWrs killed renamable $w10, killed renamable $w9, 0
+  ; CHECK-NEXT:   $w9 = ADDWrs killed renamable $w9, killed renamable $w11, 0, pcsections !0
+  ; CHECK-NEXT:   $w9 = ADDWrs killed renamable $w9, killed renamable $w10, 0, pcsections !0
   ; CHECK-NEXT:   $w0 = ADDWrs killed renamable $w9, killed renamable $w8, 0, pcsections !0
   ; CHECK-NEXT:   RET undef $lr, implicit $w0
   %ptr_unsigned = getelementptr i16, ptr %p, i32 4095
   %val_unsigned = load atomic i16, ptr %ptr_unsigned monotonic, align 2, !pcsections !0
 
   %ptr_regoff = getelementptr i16, ptr %p, i32 %off32
   %val_regoff = load atomic i16, ptr %ptr_regoff unordered, align 2, !pcsections !0
   %tot1 = add i16 %val_unsigned, %val_regoff, !pcsections !0
define i32 @atomic_load_relaxed_32(ptr %p, i32 %off32) {
   ; CHECK: bb.0 (%ir-block.0):
   ; CHECK-NEXT:   liveins: $w1, $x0
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT:   renamable $x8 = ADDXri renamable $x0, 291, 12
   ; CHECK-NEXT:   renamable $w9 = LDRWui renamable $x0, 4095, pcsections !0 :: (load monotonic (s32) from %ir.ptr_unsigned)
   ; CHECK-NEXT:   renamable $w10 = LDRWroW renamable $x0, killed renamable $w1, 1, 1, pcsections !0 :: (load unordered (s32) from %ir.ptr_regoff)
   ; CHECK-NEXT:   renamable $w11 = LDURWi killed renamable $x0, -256, pcsections !0 :: (load monotonic (s32) from %ir.ptr_unscaled)
   ; CHECK-NEXT:   renamable $w8 = LDRWui killed renamable $x8, 0, pcsections !0 :: (load unordered (s32) from %ir.ptr_random)
-  ; CHECK-NEXT:   $w9 = ADDWrs killed renamable $w9, killed renamable $w11, 0
-  ; CHECK-NEXT:   $w9 = ADDWrs killed renamable $w10, killed renamable $w9, 0
+  ; CHECK-NEXT:   $w9 = ADDWrs killed renamable $w9, killed renamable $w11, 0, pcsections !0
+  ; CHECK-NEXT:   $w9 = ADDWrs killed renamable $w9, killed renamable $w10, 0, pcsections !0
   ; CHECK-NEXT:   $w0 = ADDWrs killed renamable $w9, killed renamable $w8, 0, pcsections !0
   ; CHECK-NEXT:   RET undef $lr, implicit $w0
   %ptr_unsigned = getelementptr i32, ptr %p, i32 4095
   %val_unsigned = load atomic i32, ptr %ptr_unsigned monotonic, align 4, !pcsections !0
 
   %ptr_regoff = getelementptr i32, ptr %p, i32 %off32
   %val_regoff = load atomic i32, ptr %ptr_regoff unordered, align 4, !pcsections !0
   %tot1 = add i32 %val_unsigned, %val_regoff, !pcsections !0
define i64 @atomic_load_relaxed_64(ptr %p, i32 %off32) {
   ; CHECK: bb.0 (%ir-block.0):
   ; CHECK-NEXT:   liveins: $w1, $x0
   ; CHECK-NEXT: {{  $}}
   ; CHECK-NEXT:   renamable $x8 = ADDXri renamable $x0, 291, 12
   ; CHECK-NEXT:   renamable $x9 = LDRXui renamable $x0, 4095, pcsections !0 :: (load monotonic (s64) from %ir.ptr_unsigned)
   ; CHECK-NEXT:   renamable $x10 = LDRXroW renamable $x0, killed renamable $w1, 1, 1, pcsections !0 :: (load unordered (s64) from %ir.ptr_regoff)
   ; CHECK-NEXT:   renamable $x11 = LDURXi killed renamable $x0, -256, pcsections !0 :: (load monotonic (s64) from %ir.ptr_unscaled)
   ; CHECK-NEXT:   renamable $x8 = LDRXui killed renamable $x8, 0, pcsections !0 :: (load unordered (s64) from %ir.ptr_random)
-  ; CHECK-NEXT:   $x9 = ADDXrs killed renamable $x9, killed renamable $x11, 0
-  ; CHECK-NEXT:   $x9 = ADDXrs killed renamable $x10, killed renamable $x9, 0
+  ; CHECK-NEXT:   $x9 = ADDXrs killed renamable $x9, killed renamable $x11, 0, pcsections !0
+  ; CHECK-NEXT:   $x9 = ADDXrs killed renamable $x9, killed renamable $x10, 0, pcsections !0
   ; CHECK-NEXT:   $x0 = ADDXrs killed renamable $x9, killed renamable $x8, 0, pcsections !0
   ; CHECK-NEXT:   RET undef $lr, implicit $x0
   %ptr_unsigned = getelementptr i64, ptr %p, i32 4095
   %val_unsigned = load atomic i64, ptr %ptr_unsigned monotonic, align 8, !pcsections !0
 
   %ptr_regoff = getelementptr i64, ptr %p, i32 %off32
   %val_regoff = load atomic i64, ptr %ptr_regoff unordered, align 8, !pcsections !0
   %tot1 = add i64 %val_unsigned, %val_regoff, !pcsections !0

llvm/test/CodeGen/AArch64/arm64-rev.ll

 ; GISEL:       // %bb.0: // %entry
 ; GISEL-NEXT:    lsr x8, x0, #8
 ; GISEL-NEXT:    lsl x9, x0, #8
 ; GISEL-NEXT:    and x10, x8, #0xff000000000000
 ; GISEL-NEXT:    and x11, x9, #0xff00000000000000
 ; GISEL-NEXT:    and x12, x8, #0xff00000000
 ; GISEL-NEXT:    and x13, x9, #0xff0000000000
 ; GISEL-NEXT:    orr x10, x11, x10
-; GISEL-NEXT:    orr x11, x12, x13
+; GISEL-NEXT:    orr x11, x13, x12
 ; GISEL-NEXT:    and x12, x8, #0xff0000
 ; GISEL-NEXT:    and x13, x9, #0xff000000
-; GISEL-NEXT:    orr x12, x12, x13
+; GISEL-NEXT:    orr x12, x13, x12
 ; GISEL-NEXT:    and x8, x8, #0xff
-; GISEL-NEXT:    orr x10, x10, x11
-; GISEL-NEXT:    orr x8, x12, x8
-; GISEL-NEXT:    orr x8, x10, x8
+; GISEL-NEXT:    orr x10, x11, x10
+; GISEL-NEXT:    orr x8, x8, x12
+; GISEL-NEXT:    orr x8, x8, x10
 ; GISEL-NEXT:    and x9, x9, #0xff00
 ; GISEL-NEXT:    orr x0, x9, x8
 ; GISEL-NEXT:    ret
 entry:
   %0 = lshr i64 %a, 8
   %1 = and i64 %0, 71776119061217280
   %2 = shl i64 %a, 8
   %3 = and i64 %2, -72057594037927936

llvm/test/CodeGen/AArch64/machine-combiner.ll

 ; CHECK-STD-NEXT:    fadd s0, s2, s0
 ; CHECK-STD-NEXT:    fadd s0, s0, s3
 ; CHECK-STD-NEXT:    ret
 ;
 ; CHECK-UNSAFE-LABEL: reassociate_adds2:
 ; CHECK-UNSAFE:       // %bb.0:
 ; CHECK-UNSAFE-NEXT:    fadd s0, s0, s1
 ; CHECK-UNSAFE-NEXT:    fadd s1, s2, s3
-; CHECK-UNSAFE-NEXT:    fadd s0, s0, s1
+; CHECK-UNSAFE-NEXT:    fadd s0, s1, s0
 ; CHECK-UNSAFE-NEXT:    ret
   %t0 = fadd float %x0, %x1
   %t1 = fadd float %x2, %t0
   %t2 = fadd float %t1, %x3
   ret float %t2
 }
 
 define float @reassociate_adds3(float %x0, float %x1, float %x2, float %x3) {
 ; CHECK-STD-LABEL: reassociate_adds3:
 ; CHECK-STD:       // %bb.0:
 ; CHECK-STD-NEXT:    fadd s0, s0, s1
 ; CHECK-STD-NEXT:    fadd s0, s0, s2
 ; CHECK-STD-NEXT:    fadd s0, s3, s0
 ; CHECK-STD-NEXT:    ret
 ;
 ; CHECK-UNSAFE-LABEL: reassociate_adds3:
 ; CHECK-UNSAFE:       // %bb.0:
 ; CHECK-UNSAFE-NEXT:    fadd s0, s0, s1
-; CHECK-UNSAFE-NEXT:    fadd s1, s2, s3
-; CHECK-UNSAFE-NEXT:    fadd s0, s0, s1
+; CHECK-UNSAFE-NEXT:    fadd s1, s3, s2
+; CHECK-UNSAFE-NEXT:    fadd s0, s1, s0
 ; CHECK-UNSAFE-NEXT:    ret
   %t0 = fadd float %x0, %x1
   %t1 = fadd float %t0, %x2
   %t2 = fadd float %x3, %t1
   ret float %t2
 }
 
 define float @reassociate_adds4(float %x0, float %x1, float %x2, float %x3) {
 ; CHECK-STD-LABEL: reassociate_adds4:
 ; CHECK-STD:       // %bb.0:
 ; CHECK-STD-NEXT:    fadd s0, s0, s1
 ; CHECK-STD-NEXT:    fadd s0, s2, s0
 ; CHECK-STD-NEXT:    fadd s0, s3, s0
 ; CHECK-STD-NEXT:    ret
 ;
 ; CHECK-UNSAFE-LABEL: reassociate_adds4:
 ; CHECK-UNSAFE:       // %bb.0:
 ; CHECK-UNSAFE-NEXT:    fadd s0, s0, s1
-; CHECK-UNSAFE-NEXT:    fadd s1, s2, s3
-; CHECK-UNSAFE-NEXT:    fadd s0, s0, s1
+; CHECK-UNSAFE-NEXT:    fadd s1, s3, s2
+; CHECK-UNSAFE-NEXT:    fadd s0, s1, s0
 ; CHECK-UNSAFE-NEXT:    ret
   %t0 = fadd float %x0, %x1
   %t1 = fadd float %x2, %t0
   %t2 = fadd float %x3, %t1
   ret float %t2
 }
 
 ; Verify that we reassociate some of these ops. The optimal balanced tree of adds is not

 ; CHECK-STD-NEXT:    fdiv s0, s0, s1
 ; CHECK-STD-NEXT:    fadd s0, s2, s0
 ; CHECK-STD-NEXT:    fadd s0, s3, s0
 ; CHECK-STD-NEXT:    ret
 ;
 ; CHECK-UNSAFE-LABEL: reassociate_adds6:
 ; CHECK-UNSAFE:       // %bb.0:
 ; CHECK-UNSAFE-NEXT:    fdiv s0, s0, s1
-; CHECK-UNSAFE-NEXT:    fadd s1, s2, s3
-; CHECK-UNSAFE-NEXT:    fadd s0, s0, s1
+; CHECK-UNSAFE-NEXT:    fadd s1, s3, s2
+; CHECK-UNSAFE-NEXT:    fadd s0, s1, s0
 ; CHECK-UNSAFE-NEXT:    ret
   %t0 = fdiv float %x0, %x1
   %t1 = fadd float %x2, %t0
   %t2 = fadd float %x3, %t1
   ret float %t2
 }
 
 ; Verify that scalar single-precision multiplies are reassociated.
 
 define float @reassociate_muls1(float %x0, float %x1, float %x2, float %x3) {
 ; CHECK-STD-LABEL: reassociate_muls1:
 ; CHECK-STD:       // %bb.0:
 ; CHECK-STD-NEXT:    fdiv s0, s0, s1
 ; CHECK-STD-NEXT:    fmul s1, s2, s0
 ; CHECK-STD-NEXT:    fmul s0, s3, s1
 ; CHECK-STD-NEXT:    ret
 ;
 ; CHECK-UNSAFE-LABEL: reassociate_muls1:
 ; CHECK-UNSAFE:       // %bb.0:
 ; CHECK-UNSAFE-NEXT:    fdiv s0, s0, s1
-; CHECK-UNSAFE-NEXT:    fmul s1, s2, s3
-; CHECK-UNSAFE-NEXT:    fmul s0, s0, s1
+; CHECK-UNSAFE-NEXT:    fmul s1, s3, s2
+; CHECK-UNSAFE-NEXT:    fmul s0, s1, s0
 ; CHECK-UNSAFE-NEXT:    ret
   %t0 = fdiv float %x0, %x1
   %t1 = fmul float %x2, %t0
   %t2 = fmul float %x3, %t1
   ret float %t2
 }
 
 ; Verify that scalar double-precision adds are reassociated.
 
 define double @reassociate_adds_double(double %x0, double %x1, double %x2, double %x3) {
 ; CHECK-STD-LABEL: reassociate_adds_double:
 ; CHECK-STD:       // %bb.0:
 ; CHECK-STD-NEXT:    fdiv d0, d0, d1
 ; CHECK-STD-NEXT:    fadd d0, d2, d0
 ; CHECK-STD-NEXT:    fadd d0, d3, d0
 ; CHECK-STD-NEXT:    ret
 ;
 ; CHECK-UNSAFE-LABEL: reassociate_adds_double:
 ; CHECK-UNSAFE:       // %bb.0:
 ; CHECK-UNSAFE-NEXT:    fdiv d0, d0, d1
-; CHECK-UNSAFE-NEXT:    fadd d1, d2, d3
-; CHECK-UNSAFE-NEXT:    fadd d0, d0, d1
+; CHECK-UNSAFE-NEXT:    fadd d1, d3, d2
+; CHECK-UNSAFE-NEXT:    fadd d0, d1, d0
 ; CHECK-UNSAFE-NEXT:    ret
   %t0 = fdiv double %x0, %x1
   %t1 = fadd double %x2, %t0
   %t2 = fadd double %x3, %t1
   ret double %t2
 }
 
 ; Verify that scalar double-precision multiplies are reassociated.
 
 define double @reassociate_muls_double(double %x0, double %x1, double %x2, double %x3) {
 ; CHECK-STD-LABEL: reassociate_muls_double:
 ; CHECK-STD:       // %bb.0:
 ; CHECK-STD-NEXT:    fdiv d0, d0, d1
 ; CHECK-STD-NEXT:    fmul d1, d2, d0
 ; CHECK-STD-NEXT:    fmul d0, d3, d1
 ; CHECK-STD-NEXT:    ret
 ;
 ; CHECK-UNSAFE-LABEL: reassociate_muls_double:
 ; CHECK-UNSAFE:       // %bb.0:
 ; CHECK-UNSAFE-NEXT:    fdiv d0, d0, d1
-; CHECK-UNSAFE-NEXT:    fmul d1, d2, d3
-; CHECK-UNSAFE-NEXT:    fmul d0, d0, d1
+; CHECK-UNSAFE-NEXT:    fmul d1, d3, d2
+; CHECK-UNSAFE-NEXT:    fmul d0, d1, d0
 ; CHECK-UNSAFE-NEXT:    ret
   %t0 = fdiv double %x0, %x1
   %t1 = fmul double %x2, %t0
   %t2 = fmul double %x3, %t1
   ret double %t2
 }
 
 ; Verify that we reassociate vector instructions too.

 ; CHECK-STD-NEXT:    fadd v0.4s, v2.4s, v0.4s
 ; CHECK-STD-NEXT:    fadd v0.4s, v0.4s, v3.4s
 ; CHECK-STD-NEXT:    ret
 ;
 ; CHECK-UNSAFE-LABEL: vector_reassociate_adds2:
 ; CHECK-UNSAFE:       // %bb.0:
 ; CHECK-UNSAFE-NEXT:    fadd v0.4s, v0.4s, v1.4s
 ; CHECK-UNSAFE-NEXT:    fadd v1.4s, v2.4s, v3.4s
-; CHECK-UNSAFE-NEXT:    fadd v0.4s, v0.4s, v1.4s
+; CHECK-UNSAFE-NEXT:    fadd v0.4s, v1.4s, v0.4s
 ; CHECK-UNSAFE-NEXT:    ret
   %t0 = fadd <4 x float> %x0, %x1
   %t1 = fadd <4 x float> %x2, %t0
   %t2 = fadd <4 x float> %t1, %x3
   ret <4 x float> %t2
 }
 
 define <4 x float> @vector_reassociate_adds3(<4 x float> %x0, <4 x float> %x1, <4 x float> %x2, <4 x float> %x3) {
 ; CHECK-STD-LABEL: vector_reassociate_adds3:
 ; CHECK-STD:       // %bb.0:
 ; CHECK-STD-NEXT:    fadd v0.4s, v0.4s, v1.4s
 ; CHECK-STD-NEXT:    fadd v0.4s, v0.4s, v2.4s
 ; CHECK-STD-NEXT:    fadd v0.4s, v3.4s, v0.4s
 ; CHECK-STD-NEXT:    ret
 ;
 ; CHECK-UNSAFE-LABEL: vector_reassociate_adds3:
 ; CHECK-UNSAFE:       // %bb.0:
 ; CHECK-UNSAFE-NEXT:    fadd v0.4s, v0.4s, v1.4s
-; CHECK-UNSAFE-NEXT:    fadd v1.4s, v2.4s, v3.4s
-; CHECK-UNSAFE-NEXT:    fadd v0.4s, v0.4s, v1.4s
+; CHECK-UNSAFE-NEXT:    fadd v1.4s, v3.4s, v2.4s
+; CHECK-UNSAFE-NEXT:    fadd v0.4s, v1.4s, v0.4s
 ; CHECK-UNSAFE-NEXT:    ret
   %t0 = fadd <4 x float> %x0, %x1
   %t1 = fadd <4 x float> %t0, %x2
   %t2 = fadd <4 x float> %x3, %t1
   ret <4 x float> %t2
 }
 
 define <4 x float> @vector_reassociate_adds4(<4 x float> %x0, <4 x float> %x1, <4 x float> %x2, <4 x float> %x3) {
 ; CHECK-STD-LABEL: vector_reassociate_adds4:
 ; CHECK-STD:       // %bb.0:
 ; CHECK-STD-NEXT:    fadd v0.4s, v0.4s, v1.4s
 ; CHECK-STD-NEXT:    fadd v0.4s, v2.4s, v0.4s
 ; CHECK-STD-NEXT:    fadd v0.4s, v3.4s, v0.4s
 ; CHECK-STD-NEXT:    ret
 ;
 ; CHECK-UNSAFE-LABEL: vector_reassociate_adds4:
 ; CHECK-UNSAFE:       // %bb.0:
 ; CHECK-UNSAFE-NEXT:    fadd v0.4s, v0.4s, v1.4s
-; CHECK-UNSAFE-NEXT:    fadd v1.4s, v2.4s, v3.4s
-; CHECK-UNSAFE-NEXT:    fadd v0.4s, v0.4s, v1.4s
+; CHECK-UNSAFE-NEXT:    fadd v1.4s, v3.4s, v2.4s
+; CHECK-UNSAFE-NEXT:    fadd v0.4s, v1.4s, v0.4s
 ; CHECK-UNSAFE-NEXT:    ret
   %t0 = fadd <4 x float> %x0, %x1
   %t1 = fadd <4 x float> %x2, %t0
   %t2 = fadd <4 x float> %x3, %t1
   ret <4 x float> %t2
 }
 ; Verify that 128-bit vector single-precision multiplies are reassociated.
 
 define <4 x float> @reassociate_muls_v4f32(<4 x float> %x0, <4 x float> %x1, <4 x float> %x2, <4 x float> %x3) {
 ; CHECK-STD-LABEL: reassociate_muls_v4f32:
 ; CHECK-STD:       // %bb.0:
 ; CHECK-STD-NEXT:    fadd v0.4s, v0.4s, v1.4s
 ; CHECK-STD-NEXT:    fmul v0.4s, v2.4s, v0.4s
 ; CHECK-STD-NEXT:    fmul v0.4s, v3.4s, v0.4s
 ; CHECK-STD-NEXT:    ret
 ;
 ; CHECK-UNSAFE-LABEL: reassociate_muls_v4f32:
 ; CHECK-UNSAFE:       // %bb.0:
 ; CHECK-UNSAFE-NEXT:    fadd v0.4s, v0.4s, v1.4s
-; CHECK-UNSAFE-NEXT:    fmul v1.4s, v2.4s, v3.4s
-; CHECK-UNSAFE-NEXT:    fmul v0.4s, v0.4s, v1.4s
+; CHECK-UNSAFE-NEXT:    fmul v1.4s, v3.4s, v2.4s
+; CHECK-UNSAFE-NEXT:    fmul v0.4s, v1.4s, v0.4s
 ; CHECK-UNSAFE-NEXT:    ret
   %t0 = fadd <4 x float> %x0, %x1
   %t1 = fmul <4 x float> %x2, %t0
   %t2 = fmul <4 x float> %x3, %t1
   ret <4 x float> %t2
 }
 
 ; Verify that 128-bit vector double-precision multiplies are reassociated.
 
 define <2 x double> @reassociate_muls_v2f64(<2 x double> %x0, <2 x double> %x1, <2 x double> %x2, <2 x double> %x3) {
 ; CHECK-STD-LABEL: reassociate_muls_v2f64:
 ; CHECK-STD:       // %bb.0:
 ; CHECK-STD-NEXT:    fadd v0.2d, v0.2d, v1.2d
 ; CHECK-STD-NEXT:    fmul v0.2d, v2.2d, v0.2d
 ; CHECK-STD-NEXT:    fmul v0.2d, v3.2d, v0.2d
 ; CHECK-STD-NEXT:    ret
 ;
 ; CHECK-UNSAFE-LABEL: reassociate_muls_v2f64:
 ; CHECK-UNSAFE:       // %bb.0:
 ; CHECK-UNSAFE-NEXT:    fadd v0.2d, v0.2d, v1.2d
-; CHECK-UNSAFE-NEXT:    fmul v1.2d, v2.2d, v3.2d
-; CHECK-UNSAFE-NEXT:    fmul v0.2d, v0.2d, v1.2d
+; CHECK-UNSAFE-NEXT:    fmul v1.2d, v3.2d, v2.2d
+; CHECK-UNSAFE-NEXT:    fmul v0.2d, v1.2d, v0.2d
 ; CHECK-UNSAFE-NEXT:    ret
   %t0 = fadd <2 x double> %x0, %x1
   %t1 = fmul <2 x double> %x2, %t0
   %t2 = fmul <2 x double> %x3, %t1
   ret <2 x double> %t2
 }
 
 ; PR25016: https://llvm.org/bugs/show_bug.cgi?id=25016

llvm/test/CodeGen/AArch64/sqrt-fastmath.ll

 ; CHECK-LABEL: fsqrt:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    frsqrte s1, s0
 ; CHECK-NEXT:    fcmp s0, #0.0
 ; CHECK-NEXT:    fmul s2, s1, s1
 ; CHECK-NEXT:    frsqrts s2, s0, s2
 ; CHECK-NEXT:    fmul s1, s1, s2
 ; CHECK-NEXT:    fmul s2, s1, s1
-; CHECK-NEXT:    fmul s1, s1, s0
+; CHECK-NEXT:    fmul s1, s0, s1
 ; CHECK-NEXT:    frsqrts s2, s0, s2
-; CHECK-NEXT:    fmul s1, s2, s1
+; CHECK-NEXT:    fmul s1, s1, s2
 ; CHECK-NEXT:    fcsel s0, s0, s1, eq
 ; CHECK-NEXT:    ret
   %1 = tail call fast float @llvm.sqrt.f32(float %a)
   ret float %1
 }
 
 define float @fsqrt_ieee_denorms(float %a) #1 {
 ; FAULT-LABEL: fsqrt_ieee_denorms:
 ; FAULT:       // %bb.0:
 ; FAULT-NEXT:    fsqrt s0, s0
 ; FAULT-NEXT:    ret
 ;
 ; CHECK-LABEL: fsqrt_ieee_denorms:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    frsqrte s1, s0
 ; CHECK-NEXT:    fcmp s0, #0.0
 ; CHECK-NEXT:    fmul s2, s1, s1
 ; CHECK-NEXT:    frsqrts s2, s0, s2
 ; CHECK-NEXT:    fmul s1, s1, s2
 ; CHECK-NEXT:    fmul s2, s1, s1
-; CHECK-NEXT:    fmul s1, s1, s0
+; CHECK-NEXT:    fmul s1, s0, s1
 ; CHECK-NEXT:    frsqrts s2, s0, s2
-; CHECK-NEXT:    fmul s1, s2, s1
+; CHECK-NEXT:    fmul s1, s1, s2
 ; CHECK-NEXT:    fcsel s0, s0, s1, eq
 ; CHECK-NEXT:    ret
   %1 = tail call fast float @llvm.sqrt.f32(float %a)
   ret float %1
 }
 
 define <2 x float> @f2sqrt(<2 x float> %a) #0 {
 ; FAULT-LABEL: f2sqrt:
 ; FAULT:       // %bb.0:
 ; FAULT-NEXT:    fsqrt v0.2s, v0.2s
 ; FAULT-NEXT:    ret
 ;
 ; CHECK-LABEL: f2sqrt:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    frsqrte v1.2s, v0.2s
 ; CHECK-NEXT:    fmul v2.2s, v1.2s, v1.2s
 ; CHECK-NEXT:    frsqrts v2.2s, v0.2s, v2.2s
 ; CHECK-NEXT:    fmul v1.2s, v1.2s, v2.2s
 ; CHECK-NEXT:    fmul v2.2s, v1.2s, v1.2s
-; CHECK-NEXT:    fmul v1.2s, v1.2s, v0.2s
+; CHECK-NEXT:    fmul v1.2s, v0.2s, v1.2s
 ; CHECK-NEXT:    frsqrts v2.2s, v0.2s, v2.2s
-; CHECK-NEXT:    fmul v1.2s, v2.2s, v1.2s
+; CHECK-NEXT:    fmul v1.2s, v1.2s, v2.2s
 ; CHECK-NEXT:    fcmeq v2.2s, v0.2s, #0.0
 ; CHECK-NEXT:    bif v0.8b, v1.8b, v2.8b
 ; CHECK-NEXT:    ret
   %1 = tail call fast <2 x float> @llvm.sqrt.v2f32(<2 x float> %a)
   ret <2 x float> %1
 }
 
 define <4 x float> @f4sqrt(<4 x float> %a) #0 {
 ; FAULT-LABEL: f4sqrt:
 ; FAULT:       // %bb.0:
 ; FAULT-NEXT:    fsqrt v0.4s, v0.4s
 ; FAULT-NEXT:    ret
 ;
 ; CHECK-LABEL: f4sqrt:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    frsqrte v1.4s, v0.4s
 ; CHECK-NEXT:    fmul v2.4s, v1.4s, v1.4s
 ; CHECK-NEXT:    frsqrts v2.4s, v0.4s, v2.4s
 ; CHECK-NEXT:    fmul v1.4s, v1.4s, v2.4s
 ; CHECK-NEXT:    fmul v2.4s, v1.4s, v1.4s
-; CHECK-NEXT:    fmul v1.4s, v1.4s, v0.4s
+; CHECK-NEXT:    fmul v1.4s, v0.4s, v1.4s
 ; CHECK-NEXT:    frsqrts v2.4s, v0.4s, v2.4s
-; CHECK-NEXT:    fmul v1.4s, v2.4s, v1.4s
+; CHECK-NEXT:    fmul v1.4s, v1.4s, v2.4s
 ; CHECK-NEXT:    fcmeq v2.4s, v0.4s, #0.0
 ; CHECK-NEXT:    bif v0.16b, v1.16b, v2.16b
 ; CHECK-NEXT:    ret
   %1 = tail call fast <4 x float> @llvm.sqrt.v4f32(<4 x float> %a)
   ret <4 x float> %1
 }
 
 define <8 x float> @f8sqrt(<8 x float> %a) #0 {
 ; FAULT-LABEL: f8sqrt:
 ; FAULT:       // %bb.0:
 ; FAULT-NEXT:    fsqrt v0.4s, v0.4s
 ; FAULT-NEXT:    fsqrt v1.4s, v1.4s
 ; FAULT-NEXT:    ret
 ;
 ; CHECK-LABEL: f8sqrt:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    frsqrte v2.4s, v0.4s
 ; CHECK-NEXT:    frsqrte v3.4s, v1.4s
 ; CHECK-NEXT:    fmul v4.4s, v2.4s, v2.4s
 ; CHECK-NEXT:    frsqrts v4.4s, v0.4s, v4.4s
 ; CHECK-NEXT:    fmul v5.4s, v3.4s, v3.4s
 ; CHECK-NEXT:    frsqrts v5.4s, v1.4s, v5.4s
 ; CHECK-NEXT:    fmul v2.4s, v2.4s, v4.4s
 ; CHECK-NEXT:    fmul v4.4s, v2.4s, v2.4s
-; CHECK-NEXT:    fmul v2.4s, v2.4s, v0.4s
+; CHECK-NEXT:    fmul v2.4s, v0.4s, v2.4s
 ; CHECK-NEXT:    frsqrts v4.4s, v0.4s, v4.4s
 ; CHECK-NEXT:    fmul v3.4s, v3.4s, v5.4s
 ; CHECK-NEXT:    fmul v5.4s, v3.4s, v3.4s
-; CHECK-NEXT:    fmul v3.4s, v3.4s, v1.4s
+; CHECK-NEXT:    fmul v3.4s, v1.4s, v3.4s
 ; CHECK-NEXT:    frsqrts v5.4s, v1.4s, v5.4s
-; CHECK-NEXT:    fmul v2.4s, v4.4s, v2.4s
+; CHECK-NEXT:    fmul v2.4s, v2.4s, v4.4s
 ; CHECK-NEXT:    fcmeq v4.4s, v0.4s, #0.0
 ; CHECK-NEXT:    bif v0.16b, v2.16b, v4.16b
-; CHECK-NEXT:    fmul v3.4s, v5.4s, v3.4s
+; CHECK-NEXT:    fmul v3.4s, v3.4s, v5.4s
 ; CHECK-NEXT:    fcmeq v5.4s, v1.4s, #0.0
 ; CHECK-NEXT:    bif v1.16b, v3.16b, v5.16b
 ; CHECK-NEXT:    ret
   %1 = tail call fast <8 x float> @llvm.sqrt.v8f32(<8 x float> %a)
   ret <8 x float> %1
 }
 
 define double @dsqrt(double %a) #0 {
 ; FAULT-LABEL: dsqrt:
 ; FAULT:       // %bb.0:
 ; FAULT-NEXT:    fsqrt d0, d0
 ; FAULT-NEXT:    ret
 ;
 ; CHECK-LABEL: dsqrt:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    frsqrte d1, d0
 ; CHECK-NEXT:    fcmp d0, #0.0
 ; CHECK-NEXT:    fmul d2, d1, d1
 ; CHECK-NEXT:    frsqrts d2, d0, d2
 ; CHECK-NEXT:    fmul d1, d1, d2
 ; CHECK-NEXT:    fmul d2, d1, d1
 ; CHECK-NEXT:    frsqrts d2, d0, d2
 ; CHECK-NEXT:    fmul d1, d1, d2
 ; CHECK-NEXT:    fmul d2, d1, d1
-; CHECK-NEXT:    fmul d1, d1, d0
+; CHECK-NEXT:    fmul d1, d0, d1
 ; CHECK-NEXT:    frsqrts d2, d0, d2
-; CHECK-NEXT:    fmul d1, d2, d1
+; CHECK-NEXT:    fmul d1, d1, d2
 ; CHECK-NEXT:    fcsel d0, d0, d1, eq
 ; CHECK-NEXT:    ret
   %1 = tail call fast double @llvm.sqrt.f64(double %a)
   ret double %1
 }
 
 define double @dsqrt_ieee_denorms(double %a) #1 {
 ; FAULT-LABEL: dsqrt_ieee_denorms:
 ; FAULT:       // %bb.0:
 ; FAULT-NEXT:    fsqrt d0, d0
 ; FAULT-NEXT:    ret
 ;
 ; CHECK-LABEL: dsqrt_ieee_denorms:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    frsqrte d1, d0
 ; CHECK-NEXT:    fcmp d0, #0.0
 ; CHECK-NEXT:    fmul d2, d1, d1
 ; CHECK-NEXT:    frsqrts d2, d0, d2
 ; CHECK-NEXT:    fmul d1, d1, d2
 ; CHECK-NEXT:    fmul d2, d1, d1
 ; CHECK-NEXT:    frsqrts d2, d0, d2
 ; CHECK-NEXT:    fmul d1, d1, d2
 ; CHECK-NEXT:    fmul d2, d1, d1
-; CHECK-NEXT:    fmul d1, d1, d0
+; CHECK-NEXT:    fmul d1, d0, d1
 ; CHECK-NEXT:    frsqrts d2, d0, d2
-; CHECK-NEXT:    fmul d1, d2, d1
+; CHECK-NEXT:    fmul d1, d1, d2
 ; CHECK-NEXT:    fcsel d0, d0, d1, eq
 ; CHECK-NEXT:    ret
   %1 = tail call fast double @llvm.sqrt.f64(double %a)
   ret double %1
 }
 
 define <2 x double> @d2sqrt(<2 x double> %a) #0 {
 ; FAULT-LABEL: d2sqrt:
 ; FAULT:       // %bb.0:
 ; FAULT-NEXT:    fsqrt v0.2d, v0.2d
 ; FAULT-NEXT:    ret
 ;
 ; CHECK-LABEL: d2sqrt:
 ; CHECK:       // %bb.0:
 ; CHECK-NEXT:    frsqrte v1.2d, v0.2d
 ; CHECK-NEXT:    fmul v2.2d, v1.2d, v1.2d
 ; CHECK-NEXT:    frsqrts v2.2d, v0.2d, v2.2d
 ; CHECK-NEXT:    fmul v1.2d, v1.2d, v2.2d
 ; CHECK-NEXT:    fmul v2.2d, v1.2d, v1.2d
 ; CHECK-NEXT:    frsqrts v2.2d, v0.2d, v2.2d
 ; CHECK-NEXT:    fmul v1.2d, v1.2d, v2.2d
 ; CHECK-NEXT:    fmul v2.2d, v1.2d, v1.2d
-; CHECK-NEXT:    fmul v1.2d, v1.2d, v0.2d
+; CHECK-NEXT:    fmul v1.2d, v0.2d, v1.2d
 ; CHECK-NEXT:    frsqrts v2.2d, v0.2d, v2.2d
-; CHECK-NEXT:    fmul v1.2d, v2.2d, v1.2d
+; CHECK-NEXT:    fmul v1.2d, v1.2d, v2.2d
 ; CHECK-NEXT:    fcmeq v2.2d, v0.2d, #0.0
 ; CHECK-NEXT:    bif v0.16b, v1.16b, v2.16b
 ; CHECK-NEXT:    ret
   %1 = tail call fast <2 x double> @llvm.sqrt.v2f64(<2 x double> %a)
   ret <2 x double> %1
 }
 
 define <4 x double> @d4sqrt(<4 x double> %a) #0 {

 ; CHECK-NEXT:    fmul v2.2d, v2.2d, v4.2d
 ; CHECK-NEXT:    fmul v4.2d, v2.2d, v2.2d
 ; CHECK-NEXT:    frsqrts v4.2d, v0.2d, v4.2d
 ; CHECK-NEXT:    fmul v3.2d, v3.2d, v5.2d
 ; CHECK-NEXT:    fmul v5.2d, v3.2d, v3.2d
 ; CHECK-NEXT:    frsqrts v5.2d, v1.2d, v5.2d
 ; CHECK-NEXT:    fmul v2.2d, v2.2d, v4.2d
 ; CHECK-NEXT:    fmul v4.2d, v2.2d, v2.2d
-; CHECK-NEXT:    fmul v2.2d, v2.2d, v0.2d
+; CHECK-NEXT:    fmul v2.2d, v0.2d, v2.2d
 ; CHECK-NEXT:    frsqrts v4.2d, v0.2d, v4.2d
 ; CHECK-NEXT:    fmul v3.2d, v3.2d, v5.2d
 ; CHECK-NEXT:    fmul v5.2d, v3.2d, v3.2d
-; CHECK-NEXT:    fmul v3.2d, v3.2d, v1.2d
+; CHECK-NEXT:    fmul v3.2d, v1.2d, v3.2d
 ; CHECK-NEXT:    frsqrts v5.2d, v1.2d, v5.2d
-; CHECK-NEXT:    fmul v2.2d, v4.2d, v2.2d
+; CHECK-NEXT:    fmul v2.2d, v2.2d, v4.2d
 ; CHECK-NEXT:    fcmeq v4.2d, v0.2d, #0.0
 ; CHECK-NEXT:    bif v0.16b, v2.16b, v4.16b
-; CHECK-NEXT:    fmul v3.2d, v5.2d, v3.2d
+; CHECK-NEXT:    fmul v3.2d, v3.2d, v5.2d
 ; CHECK-NEXT:    fcmeq v5.2d, v1.2d, #0.0
 ; CHECK-NEXT:    bif v1.16b, v3.16b, v5.16b
 ; CHECK-NEXT:    ret
   %1 = tail call fast <4 x double> @llvm.sqrt.v4f64(<4 x double> %a)
   ret <4 x double> %1
 }
 
 define float @frsqrt(float %a) #0 {

llvm/test/CodeGen/PowerPC/machine-combiner.ll

; CHECK-NEXT:  blr
   ret float %t2
 }
 
 define float @reassociate_adds2(float %x0, float %x1, float %x2, float %x3) {
 ; CHECK-LABEL: reassociate_adds2:
 ; CHECK:       # %bb.0:
 ; CHECK:       fadds [[REG0:[0-9]+]], 1, 2
 ; CHECK:       fadds [[REG1:[0-9]+]], 3, 4
-; CHECK:       fadds 1, [[REG0]], [[REG1]]
+; CHECK:       fadds 1, [[REG1]], [[REG0]]
 ; CHECK-NEXT:  blr
 
   %t0 = fadd reassoc nsz float %x0, %x1
   %t1 = fadd reassoc nsz float %x2, %t0
   %t2 = fadd reassoc nsz float %t1, %x3
   ret float %t2
 }
 
 define float @reassociate_adds3(float %x0, float %x1, float %x2, float %x3) {
 ; CHECK-LABEL: reassociate_adds3:
 ; CHECK:       # %bb.0:
 ; CHECK:       fadds [[REG0:[0-9]+]], 1, 2
-; CHECK:       fadds [[REG1:[0-9]+]], 3, 4
-; CHECK:       fadds 1, [[REG0]], [[REG1]]
+; CHECK:       fadds [[REG1:[0-9]+]], 4, 3
+; CHECK:       fadds 1, [[REG1]], [[REG0]]
 ; CHECK-NEXT:  blr
 
   %t0 = fadd reassoc nsz float %x0, %x1
   %t1 = fadd reassoc nsz float %t0, %x2
   %t2 = fadd reassoc nsz float %x3, %t1
   ret float %t2
 }
 
 define float @reassociate_adds4(float %x0, float %x1, float %x2, float %x3) {
 ; CHECK-LABEL: reassociate_adds4:
 ; CHECK:       # %bb.0:
 ; CHECK:       fadds [[REG0:[0-9]+]], 1, 2
-; CHECK:       fadds [[REG1:[0-9]+]], 3, 4
-; CHECK:       fadds 1, [[REG0]], [[REG1]]
+; CHECK:       fadds [[REG1:[0-9]+]], 4, 3
+; CHECK:       fadds 1, [[REG1]], [[REG0]]
 ; CHECK-NEXT:  blr
 
   %t0 = fadd reassoc nsz float %x0, %x1
   %t1 = fadd reassoc nsz float %x2, %t0
   %t2 = fadd reassoc nsz float %x3, %t1
   ret float %t2
 }
 
; CHECK-NEXT:  blr
   ret <4 x float> %t2
 }
 
 define <4 x float> @vector_reassociate_adds2(<4 x float> %x0, <4 x float> %x1, <4 x float> %x2, <4 x float> %x3) {
 ; CHECK-LABEL: vector_reassociate_adds2:
 ; CHECK:       # %bb.0:
 ; CHECK-PWR:       xvaddsp [[REG0:[0-9]+]], 34, 35
 ; CHECK-PWR:       xvaddsp [[REG1:[0-9]+]], 36, 37
-; CHECK-PWR:       xvaddsp 34, [[REG0]], [[REG1]]
+; CHECK-PWR:       xvaddsp 34, [[REG1]], [[REG0]]
 ; CHECK-NEXT:  blr
 
   %t0 = fadd reassoc nsz <4 x float> %x0, %x1
   %t1 = fadd reassoc nsz <4 x float> %x2, %t0
   %t2 = fadd reassoc nsz <4 x float> %t1, %x3
   ret <4 x float> %t2
 }
 
 define <4 x float> @vector_reassociate_adds3(<4 x float> %x0, <4 x float> %x1, <4 x float> %x2, <4 x float> %x3) {
 ; CHECK-LABEL: vector_reassociate_adds3:
 ; CHECK:       # %bb.0:
 ; CHECK-PWR:       xvaddsp [[REG0:[0-9]+]], 34, 35
-; CHECK-PWR:       xvaddsp [[REG1:[0-9]+]], 36, 37
-; CHECK-PWR:       xvaddsp 34, [[REG0]], [[REG1]]
+; CHECK-PWR:       xvaddsp [[REG1:[0-9]+]], 37, 36
+; CHECK-PWR:       xvaddsp 34, [[REG1]], [[REG0]]
 ; CHECK-NEXT:  blr
 
   %t0 = fadd reassoc nsz <4 x float> %x0, %x1
   %t1 = fadd reassoc nsz <4 x float> %t0, %x2
   %t2 = fadd reassoc nsz <4 x float> %x3, %t1
   ret <4 x float> %t2
 }
 
 define <4 x float> @vector_reassociate_adds4(<4 x float> %x0, <4 x float> %x1, <4 x float> %x2, <4 x float> %x3) {
 ; CHECK-LABEL: vector_reassociate_adds4:
 ; CHECK:       # %bb.0:
 ; CHECK-PWR:       xvaddsp [[REG0:[0-9]+]], 34, 35
-; CHECK-PWR:       xvaddsp [[REG1:[0-9]+]], 36, 37
-; CHECK-PWR:       xvaddsp 34, [[REG0]], [[REG1]]
+; CHECK-PWR:       xvaddsp [[REG1:[0-9]+]], 37, 36
+; CHECK-PWR:       xvaddsp 34, [[REG1]], [[REG0]]
 ; CHECK-NEXT:  blr
 
   %t0 = fadd reassoc nsz <4 x float> %x0, %x1
   %t1 = fadd reassoc nsz <4 x float> %x2, %t0
   %t2 = fadd reassoc nsz <4 x float> %x3, %t1
   ret <4 x float> %t2
 }
 

llvm/test/CodeGen/RISCV/machine-combiner.ll

; CHECK-NEXT:    ret
   ret double %t2
 }
 
 define double @test_reassoc_fadd2(double %a0, double %a1, double %a2, double %a3) {
 ; CHECK-LABEL: test_reassoc_fadd2:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    fadd.d ft0, fa0, fa1
 ; CHECK-NEXT:    fadd.d ft1, fa2, fa3
-; CHECK-NEXT:    fadd.d fa0, ft0, ft1
+; CHECK-NEXT:    fadd.d fa0, ft1, ft0
 ; CHECK-NEXT:    ret
   %t0 = fadd nsz reassoc double %a0, %a1
   %t1 = fadd nsz reassoc double %a2, %t0
   %t2 = fadd nsz reassoc double %t1, %a3
   ret double %t2
 }
 
 define double @test_reassoc_fadd3(double %a0, double %a1, double %a2, double %a3) {
 ; CHECK-LABEL: test_reassoc_fadd3:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    fadd.d ft0, fa0, fa1
-; CHECK-NEXT:    fadd.d ft1, fa2, fa3
-; CHECK-NEXT:    fadd.d fa0, ft0, ft1
+; CHECK-NEXT:    fadd.d ft1, fa3, fa2
+; CHECK-NEXT:    fadd.d fa0, ft1, ft0
 ; CHECK-NEXT:    ret
   %t0 = fadd nsz reassoc double %a0, %a1
   %t1 = fadd nsz reassoc double %t0, %a2
   %t2 = fadd nsz reassoc double %a3, %t1
   ret double %t2
 }
 
 define double @test_reassoc_fadd4(double %a0, double %a1, double %a2, double %a3) {
 ; CHECK-LABEL: test_reassoc_fadd4:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    fadd.d ft0, fa0, fa1
-; CHECK-NEXT:    fadd.d ft1, fa2, fa3
-; CHECK-NEXT:    fadd.d fa0, ft0, ft1
+; CHECK-NEXT:    fadd.d ft1, fa3, fa2
+; CHECK-NEXT:    fadd.d fa0, ft1, ft0
 ; CHECK-NEXT:    ret
   %t0 = fadd nsz reassoc double %a0, %a1
   %t1 = fadd nsz reassoc double %a2, %t0
   %t2 = fadd nsz reassoc double %a3, %t1
   ret double %t2
 }
 
 define double @test_reassoc_fmul1(double %a0, double %a1, double %a2, double %a3) {
; CHECK-NEXT:    ret
   ret double %t2
 }
 
 define double @test_reassoc_fmul2(double %a0, double %a1, double %a2, double %a3) {
 ; CHECK-LABEL: test_reassoc_fmul2:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    fmul.d ft0, fa0, fa1
 ; CHECK-NEXT:    fmul.d ft1, fa2, fa3
-; CHECK-NEXT:    fmul.d fa0, ft0, ft1
+; CHECK-NEXT:    fmul.d fa0, ft1, ft0
 ; CHECK-NEXT:    ret
   %t0 = fmul nsz reassoc double %a0, %a1
   %t1 = fmul nsz reassoc double %a2, %t0
   %t2 = fmul nsz reassoc double %t1, %a3
   ret double %t2
 }
 
 define double @test_reassoc_fmul3(double %a0, double %a1, double %a2, double %a3) {
 ; CHECK-LABEL: test_reassoc_fmul3:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    fmul.d ft0, fa0, fa1
-; CHECK-NEXT:    fmul.d ft1, fa2, fa3
-; CHECK-NEXT:    fmul.d fa0, ft0, ft1
+; CHECK-NEXT:    fmul.d ft1, fa3, fa2
+; CHECK-NEXT:    fmul.d fa0, ft1, ft0
 ; CHECK-NEXT:    ret
   %t0 = fmul nsz reassoc double %a0, %a1
   %t1 = fmul nsz reassoc double %t0, %a2
   %t2 = fmul nsz reassoc double %a3, %t1
   ret double %t2
 }
 
 define double @test_reassoc_fmul4(double %a0, double %a1, double %a2, double %a3) {
 ; CHECK-LABEL: test_reassoc_fmul4:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    fmul.d ft0, fa0, fa1
-; CHECK-NEXT:    fmul.d ft1, fa2, fa3
-; CHECK-NEXT:    fmul.d fa0, ft0, ft1
+; CHECK-NEXT:    fmul.d ft1, fa3, fa2
+; CHECK-NEXT:    fmul.d fa0, ft1, ft0
 ; CHECK-NEXT:    ret
   %t0 = fmul nsz reassoc double %a0, %a1
   %t1 = fmul nsz reassoc double %a2, %t0
   %t2 = fmul nsz reassoc double %a3, %t1
   ret double %t2
 }
 
 define double @test_reassoc_big1(double %a0, double %a1, double %a2, double %a3, double %a4, double %a5, double %a6) {

 ; CHECK-LABEL: test_reassoc_big2:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    fcvt.d.w ft0, a0
 ; CHECK-NEXT:    fcvt.d.w ft1, a1
 ; CHECK-NEXT:    fmul.d ft0, fa2, ft0
 ; CHECK-NEXT:    fmul.d ft1, ft1, fa1
 ; CHECK-NEXT:    fadd.d ft2, fa0, fa1
 ; CHECK-NEXT:    fadd.d ft3, fa2, fa1
-; CHECK-NEXT:    fmul.d ft0, ft0, ft1
+; CHECK-NEXT:    fmul.d ft0, ft1, ft0
 ; CHECK-NEXT:    fadd.d ft1, fa2, ft2
 ; CHECK-NEXT:    fmul.d ft2, fa0, ft3
 ; CHECK-NEXT:    fsub.d ft1, fa3, ft1
 ; CHECK-NEXT:    fmul.d ft0, ft0, ft2
 ; CHECK-NEXT:    fmul.d fa0, ft1, ft0
 ; CHECK-NEXT:    ret
   %cvt1 = sitofp i32 %a2 to double
   %cvt2 = sitofp i32 %a4 to double

llvm/test/CodeGen/X86/avx512-mask-op.ll

 ; X86-NEXT:    kshiftrq $6, %k0, %k1
 ; X86-NEXT:    kshiftlq $6, %k1, %k1
 ; X86-NEXT:    kshiftlq $59, %k0, %k0
 ; X86-NEXT:    kshiftrq $59, %k0, %k0
 ; X86-NEXT:    movb $1, %al
 ; X86-NEXT:    kmovd %eax, %k2
 ; X86-NEXT:    kshiftlq $63, %k2, %k2
 ; X86-NEXT:    kshiftrq $58, %k2, %k2
-; X86-NEXT:    korq %k2, %k1, %k1
-; X86-NEXT:    korq %k1, %k0, %k0
+; X86-NEXT:    korq %k1, %k2, %k1
+; X86-NEXT:    korq %k0, %k1, %k0
 ; X86-NEXT:    vpmovm2b %k0, %zmm0
 ; X86-NEXT:    retl
   %a = bitcast i64 %x to <64 x i1>
   %b = insertelement <64 x i1>%a, i1 true, i32 5
   %c = sext <64 x i1>%b to <64 x i8>
   ret <64 x i8>%c
 }
 

 ; X86-NEXT:    setg %al
 ; X86-NEXT:    kshiftrq $6, %k0, %k1
 ; X86-NEXT:    kshiftlq $6, %k1, %k1
 ; X86-NEXT:    kshiftlq $59, %k0, %k0
 ; X86-NEXT:    kshiftrq $59, %k0, %k0
 ; X86-NEXT:    kmovd %eax, %k2
 ; X86-NEXT:    kshiftlq $63, %k2, %k2
 ; X86-NEXT:    kshiftrq $58, %k2, %k2
-; X86-NEXT:    korq %k2, %k1, %k1
-; X86-NEXT:    korq %k1, %k0, %k0
+; X86-NEXT:    korq %k1, %k2, %k1
+; X86-NEXT:    korq %k0, %k1, %k0
 ; X86-NEXT:    vpmovm2b %k0, %zmm0
 ; X86-NEXT:    retl
   %a = bitcast i64 %x to <64 x i1>
   %b = icmp sgt i32 %y, %z
   %c = insertelement <64 x i1>%a, i1 %b, i32 5
   %d = sext <64 x i1>%c to <64 x i8>
   ret <64 x i8>%d
 }

llvm/test/CodeGen/X86/avx512fp16-intrinsics.ll

 
 define <32 x half> @test_sqrt_ph_512_fast_estimate_attribute_2(<32 x half> %a0, <32 x half> %a1) "reciprocal-estimates"="vec-sqrth:1" {
 ; CHECK-LABEL: test_sqrt_ph_512_fast_estimate_attribute_2:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vrsqrtph %zmm0, %zmm2
 ; CHECK-NEXT:    vmulph %zmm2, %zmm0, %zmm0
 ; CHECK-NEXT:    vfmadd213ph {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to32}, %zmm2, %zmm0
 ; CHECK-NEXT:    vmulph {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to32}, %zmm2, %zmm2
-; CHECK-NEXT:    vmulph %zmm1, %zmm0, %zmm0
-; CHECK-NEXT:    vmulph %zmm0, %zmm2, %zmm0
+; CHECK-NEXT:    vmulph %zmm0, %zmm1, %zmm0
+; CHECK-NEXT:    vmulph %zmm2, %zmm0, %zmm0
 ; CHECK-NEXT:    retq
   %1 = call fast <32 x half> @llvm.sqrt.v32f16(<32 x half> %a0)
   %2 = fdiv fast <32 x half> %a1, %1
   ret <32 x half> %2
 }
 
 define <32 x half> @test_mask_sqrt_ph_512(<32 x half> %a0, <32 x half> %passthru, i32 %mask) {
 ; CHECK-LABEL: test_mask_sqrt_ph_512:

llvm/test/CodeGen/X86/avx512fp16-machine-combiner.ll

; CHECK-NEXT:    retq
   ret half %t2
 }
 
 define half @reassociate_adds2(half %x0, half %x1, half %x2, half %x3) {
 ; CHECK-LABEL: reassociate_adds2:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vaddsh %xmm1, %xmm0, %xmm0
 ; CHECK-NEXT:    vaddsh %xmm3, %xmm2, %xmm1
-; CHECK-NEXT:    vaddsh %xmm1, %xmm0, %xmm0
+; CHECK-NEXT:    vaddsh %xmm0, %xmm1, %xmm0
 ; CHECK-NEXT:    retq
   %t0 = fadd reassoc nsz half %x0, %x1
   %t1 = fadd reassoc nsz half %x2, %t0
   %t2 = fadd reassoc nsz half %t1, %x3
   ret half %t2
 }
 
 define half @reassociate_adds3(half %x0, half %x1, half %x2, half %x3) {
 ; CHECK-LABEL: reassociate_adds3:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vaddsh %xmm1, %xmm0, %xmm0
-; CHECK-NEXT:    vaddsh %xmm3, %xmm2, %xmm1
-; CHECK-NEXT:    vaddsh %xmm1, %xmm0, %xmm0
+; CHECK-NEXT:    vaddsh %xmm2, %xmm3, %xmm1
+; CHECK-NEXT:    vaddsh %xmm0, %xmm1, %xmm0
 ; CHECK-NEXT:    retq
   %t0 = fadd reassoc nsz half %x0, %x1
   %t1 = fadd reassoc nsz half %t0, %x2
   %t2 = fadd reassoc nsz half %x3, %t1
   ret half %t2
 }
 
 define half @reassociate_adds4(half %x0, half %x1, half %x2, half %x3) {
 ; CHECK-LABEL: reassociate_adds4:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vaddsh %xmm1, %xmm0, %xmm0
-; CHECK-NEXT:    vaddsh %xmm3, %xmm2, %xmm1
-; CHECK-NEXT:    vaddsh %xmm1, %xmm0, %xmm0
+; CHECK-NEXT:    vaddsh %xmm2, %xmm3, %xmm1
+; CHECK-NEXT:    vaddsh %xmm0, %xmm1, %xmm0
 ; CHECK-NEXT:    retq
   %t0 = fadd reassoc nsz half %x0, %x1
   %t1 = fadd reassoc nsz half %x2, %t0
   %t2 = fadd reassoc nsz half %x3, %t1
   ret half %t2
 }
 
 ; Verify that we reassociate some of these ops. The optimal balanced tree of adds is not

 ; Also, we should reassociate such that the result of the high latency division
 ; is used by the final 'add' rather than reassociating the %x3 operand with the
 ; division. The latter reassociation would not improve anything.
 
 define half @reassociate_adds6(half %x0, half %x1, half %x2, half %x3) {
 ; CHECK-LABEL: reassociate_adds6:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vdivsh %xmm1, %xmm0, %xmm0
-; CHECK-NEXT:    vaddsh %xmm3, %xmm2, %xmm1
-; CHECK-NEXT:    vaddsh %xmm1, %xmm0, %xmm0
+; CHECK-NEXT:    vaddsh %xmm2, %xmm3, %xmm1
+; CHECK-NEXT:    vaddsh %xmm0, %xmm1, %xmm0
 ; CHECK-NEXT:    retq
   %t0 = fdiv reassoc nsz half %x0, %x1
   %t1 = fadd reassoc nsz half %x2, %t0
   %t2 = fadd reassoc nsz half %x3, %t1
   ret half %t2
 }
 
 ; Verify that SSE and AVX scalar single-precision multiplies are reassociated.
 
 define half @reassociate_muls1(half %x0, half %x1, half %x2, half %x3) {
 ; CHECK-LABEL: reassociate_muls1:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vdivsh %xmm1, %xmm0, %xmm0
-; CHECK-NEXT:    vmulsh %xmm3, %xmm2, %xmm1
-; CHECK-NEXT:    vmulsh %xmm1, %xmm0, %xmm0
+; CHECK-NEXT:    vmulsh %xmm2, %xmm3, %xmm1
+; CHECK-NEXT:    vmulsh %xmm0, %xmm1, %xmm0
 ; CHECK-NEXT:    retq
   %t0 = fdiv reassoc nsz half %x0, %x1
   %t1 = fmul reassoc nsz half %x2, %t0
   %t2 = fmul reassoc nsz half %x3, %t1
   ret half %t2
 }
 
 ; Verify that SSE and AVX 128-bit vector half-precision adds are reassociated.
 
 define <8 x half> @reassociate_adds_v8f16(<8 x half> %x0, <8 x half> %x1, <8 x half> %x2, <8 x half> %x3) {
 ; CHECK-LABEL: reassociate_adds_v8f16:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vdivph %xmm1, %xmm0, %xmm0
-; CHECK-NEXT:    vaddph %xmm3, %xmm2, %xmm1
-; CHECK-NEXT:    vaddph %xmm1, %xmm0, %xmm0
+; CHECK-NEXT:    vaddph %xmm2, %xmm3, %xmm1
+; CHECK-NEXT:    vaddph %xmm0, %xmm1, %xmm0
 ; CHECK-NEXT:    retq
   %t0 = fdiv reassoc nsz <8 x half> %x0, %x1
   %t1 = fadd reassoc nsz <8 x half> %x2, %t0
   %t2 = fadd reassoc nsz <8 x half> %x3, %t1
   ret <8 x half> %t2
 }
 
 ; Verify that SSE and AVX 128-bit vector half-precision multiplies are reassociated.
 
 define <8 x half> @reassociate_muls_v8f16(<8 x half> %x0, <8 x half> %x1, <8 x half> %x2, <8 x half> %x3) {
 ; CHECK-LABEL: reassociate_muls_v8f16:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vaddph %xmm1, %xmm0, %xmm0
-; CHECK-NEXT:    vmulph %xmm3, %xmm2, %xmm1
-; CHECK-NEXT:    vmulph %xmm1, %xmm0, %xmm0
+; CHECK-NEXT:    vmulph %xmm2, %xmm3, %xmm1
+; CHECK-NEXT:    vmulph %xmm0, %xmm1, %xmm0
 ; CHECK-NEXT:    retq
   %t0 = fadd reassoc nsz <8 x half> %x0, %x1
   %t1 = fmul reassoc nsz <8 x half> %x2, %t0
   %t2 = fmul reassoc nsz <8 x half> %x3, %t1
   ret <8 x half> %t2
 }
 
 ; Verify that AVX 256-bit vector half-precision adds are reassociated.
 
 define <16 x half> @reassociate_adds_v16f16(<16 x half> %x0, <16 x half> %x1, <16 x half> %x2, <16 x half> %x3) {
 ; CHECK-LABEL: reassociate_adds_v16f16:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vdivph %ymm1, %ymm0, %ymm0
-; CHECK-NEXT:    vaddph %ymm3, %ymm2, %ymm1
-; CHECK-NEXT:    vaddph %ymm1, %ymm0, %ymm0
+; CHECK-NEXT:    vaddph %ymm2, %ymm3, %ymm1
+; CHECK-NEXT:    vaddph %ymm0, %ymm1, %ymm0
 ; CHECK-NEXT:    retq
   %t0 = fdiv reassoc nsz <16 x half> %x0, %x1
   %t1 = fadd reassoc nsz <16 x half> %x2, %t0
   %t2 = fadd reassoc nsz <16 x half> %x3, %t1
   ret <16 x half> %t2
 }
 
 ; Verify that AVX 256-bit vector half-precision multiplies are reassociated.
 
 define <16 x half> @reassociate_muls_v16f16(<16 x half> %x0, <16 x half> %x1, <16 x half> %x2, <16 x half> %x3) {
 ; CHECK-LABEL: reassociate_muls_v16f16:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vaddph %ymm1, %ymm0, %ymm0
-; CHECK-NEXT:    vmulph %ymm3, %ymm2, %ymm1
-; CHECK-NEXT:    vmulph %ymm1, %ymm0, %ymm0
+; CHECK-NEXT:    vmulph %ymm2, %ymm3, %ymm1
+; CHECK-NEXT:    vmulph %ymm0, %ymm1, %ymm0
 ; CHECK-NEXT:    retq
   %t0 = fadd reassoc nsz <16 x half> %x0, %x1
   %t1 = fmul reassoc nsz <16 x half> %x2, %t0
   %t2 = fmul reassoc nsz <16 x half> %x3, %t1
   ret <16 x half> %t2
 }
 
 ; Verify that AVX512 512-bit vector half-precision adds are reassociated.
 
 define <32 x half> @reassociate_adds_v32f16(<32 x half> %x0, <32 x half> %x1, <32 x half> %x2, <32 x half> %x3) {
 ; CHECK-LABEL: reassociate_adds_v32f16:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vdivph %zmm1, %zmm0, %zmm0
-; CHECK-NEXT:    vaddph %zmm3, %zmm2, %zmm1
-; CHECK-NEXT:    vaddph %zmm1, %zmm0, %zmm0
+; CHECK-NEXT:    vaddph %zmm2, %zmm3, %zmm1
+; CHECK-NEXT:    vaddph %zmm0, %zmm1, %zmm0
 ; CHECK-NEXT:    retq
   %t0 = fdiv reassoc nsz <32 x half> %x0, %x1
   %t1 = fadd reassoc nsz <32 x half> %x2, %t0
   %t2 = fadd reassoc nsz <32 x half> %x3, %t1
   ret <32 x half> %t2
 }
 
 ; Verify that AVX512 512-bit vector half-precision multiplies are reassociated.
 
 define <32 x half> @reassociate_muls_v32f16(<32 x half> %x0, <32 x half> %x1, <32 x half> %x2, <32 x half> %x3) {
 ; CHECK-LABEL: reassociate_muls_v32f16:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vaddph %zmm1, %zmm0, %zmm0
-; CHECK-NEXT:    vmulph %zmm3, %zmm2, %zmm1
-; CHECK-NEXT:    vmulph %zmm1, %zmm0, %zmm0
+; CHECK-NEXT:    vmulph %zmm2, %zmm3, %zmm1
+; CHECK-NEXT:    vmulph %zmm0, %zmm1, %zmm0
 ; CHECK-NEXT:    retq
   %t0 = fadd reassoc nsz <32 x half> %x0, %x1
   %t1 = fmul reassoc nsz <32 x half> %x2, %t0
   %t2 = fmul reassoc nsz <32 x half> %x3, %t1
   ret <32 x half> %t2
 }
 
 ; Verify that SSE and AVX scalar half-precision minimum ops are reassociated.
 
 define half @reassociate_mins_half(half %x0, half %x1, half %x2, half %x3) {
 ; CHECK-LABEL: reassociate_mins_half:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vdivsh %xmm1, %xmm0, %xmm0
-; CHECK-NEXT:    vminsh %xmm3, %xmm2, %xmm1
-; CHECK-NEXT:    vminsh %xmm1, %xmm0, %xmm0
+; CHECK-NEXT:    vminsh %xmm2, %xmm3, %xmm1
+; CHECK-NEXT:    vminsh %xmm0, %xmm1, %xmm0
 ; CHECK-NEXT:    retq
   %t0 = fdiv half %x0, %x1
   %cmp1 = fcmp olt half %x2, %t0
   %sel1 = select i1 %cmp1, half %x2, half %t0
   %cmp2 = fcmp olt half %x3, %sel1
   %sel2 = select i1 %cmp2, half %x3, half %sel1
   ret half %sel2
 }
 
 ; Verify that SSE and AVX scalar half-precision maximum ops are reassociated.
 
 define half @reassociate_maxs_half(half %x0, half %x1, half %x2, half %x3) {
 ; CHECK-LABEL: reassociate_maxs_half:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vdivsh %xmm1, %xmm0, %xmm0
-; CHECK-NEXT:    vmaxsh %xmm3, %xmm2, %xmm1
-; CHECK-NEXT:    vmaxsh %xmm1, %xmm0, %xmm0
+; CHECK-NEXT:    vmaxsh %xmm2, %xmm3, %xmm1
+; CHECK-NEXT:    vmaxsh %xmm0, %xmm1, %xmm0
 ; CHECK-NEXT:    retq
   %t0 = fdiv half %x0, %x1
   %cmp1 = fcmp ogt half %x2, %t0
   %sel1 = select i1 %cmp1, half %x2, half %t0
   %cmp2 = fcmp ogt half %x3, %sel1
   %sel2 = select i1 %cmp2, half %x3, half %sel1
   ret half %sel2
 }
 
 ; Verify that SSE and AVX 128-bit vector half-precision minimum ops are reassociated.
 
 define <8 x half> @reassociate_mins_v8f16(<8 x half> %x0, <8 x half> %x1, <8 x half> %x2, <8 x half> %x3) {
 ; CHECK-LABEL: reassociate_mins_v8f16:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vaddph %xmm1, %xmm0, %xmm0
-; CHECK-NEXT:    vminph %xmm3, %xmm2, %xmm1
-; CHECK-NEXT:    vminph %xmm1, %xmm0, %xmm0
+; CHECK-NEXT:    vminph %xmm2, %xmm3, %xmm1
+; CHECK-NEXT:    vminph %xmm0, %xmm1, %xmm0
 ; CHECK-NEXT:    retq
   %t0 = fadd <8 x half> %x0, %x1
   %cmp1 = fcmp olt <8 x half> %x2, %t0
   %sel1 = select <8 x i1> %cmp1, <8 x half> %x2, <8 x half> %t0
   %cmp2 = fcmp olt <8 x half> %x3, %sel1
   %sel2 = select <8 x i1> %cmp2, <8 x half> %x3, <8 x half> %sel1
   ret <8 x half> %sel2
 }
 
 ; Verify that SSE and AVX 128-bit vector half-precision maximum ops are reassociated.
 
 define <8 x half> @reassociate_maxs_v8f16(<8 x half> %x0, <8 x half> %x1, <8 x half> %x2, <8 x half> %x3) {
 ; CHECK-LABEL: reassociate_maxs_v8f16:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vaddph %xmm1, %xmm0, %xmm0
-; CHECK-NEXT:    vmaxph %xmm3, %xmm2, %xmm1
-; CHECK-NEXT:    vmaxph %xmm1, %xmm0, %xmm0
+; CHECK-NEXT:    vmaxph %xmm2, %xmm3, %xmm1
+; CHECK-NEXT:    vmaxph %xmm0, %xmm1, %xmm0
 ; CHECK-NEXT:    retq
   %t0 = fadd <8 x half> %x0, %x1
   %cmp1 = fcmp ogt <8 x half> %x2, %t0
   %sel1 = select <8 x i1> %cmp1, <8 x half> %x2, <8 x half> %t0
   %cmp2 = fcmp ogt <8 x half> %x3, %sel1
   %sel2 = select <8 x i1> %cmp2, <8 x half> %x3, <8 x half> %sel1
   ret <8 x half> %sel2
 }
 
 ; Verify that AVX 256-bit vector half-precision minimum ops are reassociated.
 
 define <16 x half> @reassociate_mins_v16f16(<16 x half> %x0, <16 x half> %x1, <16 x half> %x2, <16 x half> %x3) {
 ; CHECK-LABEL: reassociate_mins_v16f16:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vaddph %ymm1, %ymm0, %ymm0
-; CHECK-NEXT:    vminph %ymm3, %ymm2, %ymm1
-; CHECK-NEXT:    vminph %ymm1, %ymm0, %ymm0
+; CHECK-NEXT:    vminph %ymm2, %ymm3, %ymm1
+; CHECK-NEXT:    vminph %ymm0, %ymm1, %ymm0
 ; CHECK-NEXT:    retq
   %t0 = fadd <16 x half> %x0, %x1
   %cmp1 = fcmp olt <16 x half> %x2, %t0
   %sel1 = select <16 x i1> %cmp1, <16 x half> %x2, <16 x half> %t0
   %cmp2 = fcmp olt <16 x half> %x3, %sel1
   %sel2 = select <16 x i1> %cmp2, <16 x half> %x3, <16 x half> %sel1
   ret <16 x half> %sel2
 }
 
 ; Verify that AVX 256-bit vector half-precision maximum ops are reassociated.
 
 define <16 x half> @reassociate_maxs_v16f16(<16 x half> %x0, <16 x half> %x1, <16 x half> %x2, <16 x half> %x3) {
 ; CHECK-LABEL: reassociate_maxs_v16f16:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vaddph %ymm1, %ymm0, %ymm0
-; CHECK-NEXT:    vmaxph %ymm3, %ymm2, %ymm1
-; CHECK-NEXT:    vmaxph %ymm1, %ymm0, %ymm0
+; CHECK-NEXT:    vmaxph %ymm2, %ymm3, %ymm1
+; CHECK-NEXT:    vmaxph %ymm0, %ymm1, %ymm0
 ; CHECK-NEXT:    retq
   %t0 = fadd <16 x half> %x0, %x1
   %cmp1 = fcmp ogt <16 x half> %x2, %t0
   %sel1 = select <16 x i1> %cmp1, <16 x half> %x2, <16 x half> %t0
   %cmp2 = fcmp ogt <16 x half> %x3, %sel1
   %sel2 = select <16 x i1> %cmp2, <16 x half> %x3, <16 x half> %sel1
   ret <16 x half> %sel2
 }
 
 ; Verify that AVX512 512-bit vector half-precision minimum ops are reassociated.
 
 define <32 x half> @reassociate_mins_v32f16(<32 x half> %x0, <32 x half> %x1, <32 x half> %x2, <32 x half> %x3) {
 ; CHECK-LABEL: reassociate_mins_v32f16:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vaddph %zmm1, %zmm0, %zmm0
-; CHECK-NEXT:    vminph %zmm3, %zmm2, %zmm1
-; CHECK-NEXT:    vminph %zmm1, %zmm0, %zmm0
+; CHECK-NEXT:    vminph %zmm2, %zmm3, %zmm1
+; CHECK-NEXT:    vminph %zmm0, %zmm1, %zmm0
 ; CHECK-NEXT:    retq
   %t0 = fadd <32 x half> %x0, %x1
   %cmp1 = fcmp olt <32 x half> %x2, %t0
   %sel1 = select <32 x i1> %cmp1, <32 x half> %x2, <32 x half> %t0
   %cmp2 = fcmp olt <32 x half> %x3, %sel1
   %sel2 = select <32 x i1> %cmp2, <32 x half> %x3, <32 x half> %sel1
   ret <32 x half> %sel2
 }
 
 ; Verify that AVX512 512-bit vector half-precision maximum ops are reassociated.
 
 define <32 x half> @reassociate_maxs_v16f32(<32 x half> %x0, <32 x half> %x1, <32 x half> %x2, <32 x half> %x3) {
 ; CHECK-LABEL: reassociate_maxs_v16f32:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vaddph %zmm1, %zmm0, %zmm0
-; CHECK-NEXT:    vmaxph %zmm3, %zmm2, %zmm1
-; CHECK-NEXT:    vmaxph %zmm1, %zmm0, %zmm0
+; CHECK-NEXT:    vmaxph %zmm2, %zmm3, %zmm1
+; CHECK-NEXT:    vmaxph %zmm0, %zmm1, %zmm0
 ; CHECK-NEXT:    retq
   %t0 = fadd <32 x half> %x0, %x1
   %cmp1 = fcmp ogt <32 x half> %x2, %t0
   %sel1 = select <32 x i1> %cmp1, <32 x half> %x2, <32 x half> %t0
   %cmp2 = fcmp ogt <32 x half> %x3, %sel1
   %sel2 = select <32 x i1> %cmp2, <32 x half> %x3, <32 x half> %sel1
   ret <32 x half> %sel2
 }
 

llvm/test/CodeGen/X86/avx512fp16-mscatter.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc < %s -mtriple=x86_64-unkown-unkown -mattr=+avx512bw -mattr=+avx512vl -mattr=+avx512fp16 | FileCheck %s
 
 define void @test_mscatter_v16f16(ptr %base, <16 x i32> %index, <16 x half> %val)
 ; CHECK-LABEL: test_mscatter_v16f16:
 ; CHECK:       # %bb.0:
 ; CHECK-NEXT:    vpbroadcastq %rdi, %zmm3
 ; CHECK-NEXT:    vextracti64x4 $1, %zmm0, %ymm2
 ; CHECK-NEXT:    vpmovsxdq %ymm2, %zmm2
-; CHECK-NEXT:    vpaddq %zmm3, %zmm2, %zmm4
-; CHECK-NEXT:    vpaddq %zmm4, %zmm2, %zmm2
+; CHECK-NEXT:    vpaddq %zmm2, %zmm3, %zmm4
+; CHECK-NEXT:    vpaddq %zmm2, %zmm4, %zmm2
 ; CHECK-NEXT:    vpmovsxdq %ymm0, %zmm0
-; CHECK-NEXT:    vpaddq %zmm3, %zmm0, %zmm3
-; CHECK-NEXT:    vpaddq %zmm3, %zmm0, %zmm0
+; CHECK-NEXT:    vpaddq %zmm0, %zmm3, %zmm3
+; CHECK-NEXT:    vpaddq %zmm0, %zmm3, %zmm0
 ; CHECK-NEXT:    vmovq %xmm0, %rax
 ; CHECK-NEXT:    vmovsh %xmm1, (%rax)
 ; CHECK-NEXT:    vpsrld $16, %xmm1, %xmm3
 ; CHECK-NEXT:    vpextrq $1, %xmm0, %rax
 ; CHECK-NEXT:    vmovsh %xmm3, (%rax)
 ; CHECK-NEXT:    vmovshdup {{.*#+}} xmm3 = xmm1[1,1,3,3]
 ; CHECK-NEXT:    vextracti128 $1, %ymm0, %xmm4
 ; CHECK-NEXT:    vmovq %xmm4, %rax

llvm/test/CodeGen/X86/avx512vl-intrinsics.ll

 define <8 x i16> @test_x86_vcvtps2ph_128(<4 x float> %a0, i8 %mask, <8 x i16> %src) {
 ; X86-LABEL: test_x86_vcvtps2ph_128:
 ; X86:       # %bb.0:
 ; X86-NEXT:    movzbl {{[0-9]+}}(%esp), %eax # encoding: [0x0f,0xb6,0x44,0x24,0x04]
 ; X86-NEXT:    kmovw %eax, %k1 # encoding: [0xc5,0xf8,0x92,0xc8]
 ; X86-NEXT:    vcvtps2ph $2, %xmm0, %xmm2 # EVEX TO VEX Compression encoding: [0xc4,0xe3,0x79,0x1d,0xc2,0x02]
 ; X86-NEXT:    vcvtps2ph $10, %xmm0, %xmm3 {%k1} {z} # encoding: [0x62,0xf3,0x7d,0x89,0x1d,0xc3,0x0a]
 ; X86-NEXT:    vcvtps2ph $11, %xmm0, %xmm1 {%k1} # encoding: [0x62,0xf3,0x7d,0x09,0x1d,0xc1,0x0b]
-; X86-NEXT:    vpaddw %xmm1, %xmm3, %xmm0 # encoding: [0xc5,0xe1,0xfd,0xc1]
-; X86-NEXT:    vpaddw %xmm0, %xmm2, %xmm0 # encoding: [0xc5,0xe9,0xfd,0xc0]
+; X86-NEXT:    vpaddw %xmm3, %xmm1, %xmm0 # encoding: [0xc5,0xf1,0xfd,0xc3]
+; X86-NEXT:    vpaddw %xmm2, %xmm0, %xmm0 # encoding: [0xc5,0xf9,0xfd,0xc2]
 ; X86-NEXT:    retl # encoding: [0xc3]
 ;
 ; X64-LABEL: test_x86_vcvtps2ph_128:
 ; X64:       # %bb.0:
 ; X64-NEXT:    kmovw %edi, %k1 # encoding: [0xc5,0xf8,0x92,0xcf]
 ; X64-NEXT:    vcvtps2ph $2, %xmm0, %xmm2 # EVEX TO VEX Compression encoding: [0xc4,0xe3,0x79,0x1d,0xc2,0x02]
 ; X64-NEXT:    vcvtps2ph $10, %xmm0, %xmm3 {%k1} {z} # encoding: [0x62,0xf3,0x7d,0x89,0x1d,0xc3,0x0a]
 ; X64-NEXT:    vcvtps2ph $11, %xmm0, %xmm1 {%k1} # encoding: [0x62,0xf3,0x7d,0x09,0x1d,0xc1,0x0b]
-; X64-NEXT:    vpaddw %xmm1, %xmm3, %xmm0 # encoding: [0xc5,0xe1,0xfd,0xc1]
-; X64-NEXT:    vpaddw %xmm0, %xmm2, %xmm0 # encoding: [0xc5,0xe9,0xfd,0xc0]
+; X64-NEXT:    vpaddw %xmm3, %xmm1, %xmm0 # encoding: [0xc5,0xf1,0xfd,0xc3]
+; X64-NEXT:    vpaddw %xmm2, %xmm0, %xmm0 # encoding: [0xc5,0xf9,0xfd,0xc2]
 ; X64-NEXT:    retq # encoding: [0xc3]
   %res1 = call <8 x i16> @llvm.x86.avx512.mask.vcvtps2ph.128(<4 x float> %a0, i32 2, <8 x i16> zeroinitializer, i8 -1)
   %res2 = call <8 x i16> @llvm.x86.avx512.mask.vcvtps2ph.128(<4 x float> %a0, i32 10, <8 x i16> zeroinitializer, i8 %mask)
   %res3 = call <8 x i16> @llvm.x86.avx512.mask.vcvtps2ph.128(<4 x float> %a0, i32 11, <8 x i16> %src, i8 %mask)
   %res0 = add <8 x i16> %res1, %res2
   %res = add <8 x i16> %res3, %res0
   ret <8 x i16> %res
 }
 
 declare <8 x i16> @llvm.x86.avx512.mask.vcvtps2ph.128(<4 x float>, i32, <8 x i16>, i8) nounwind readonly
 
 define <8 x i16> @test_x86_vcvtps2ph_256(<8 x float> %a0, i8 %mask, <8 x i16> %src) {
 ; X86-LABEL: test_x86_vcvtps2ph_256:
 ; X86:       # %bb.0:
 ; X86-NEXT:    movzbl {{[0-9]+}}(%esp), %eax # encoding: [0x0f,0xb6,0x44,0x24,0x04]
 ; X86-NEXT:    kmovw %eax, %k1 # encoding: [0xc5,0xf8,0x92,0xc8]
 ; X86-NEXT:    vcvtps2ph $2, %ymm0, %xmm2 # EVEX TO VEX Compression encoding: [0xc4,0xe3,0x7d,0x1d,0xc2,0x02]
 ; X86-NEXT:    vcvtps2ph $11, %ymm0, %xmm3 {%k1} {z} # encoding: [0x62,0xf3,0x7d,0xa9,0x1d,0xc3,0x0b]
 ; X86-NEXT:    vcvtps2ph $12, %ymm0, %xmm1 {%k1} # encoding: [0x62,0xf3,0x7d,0x29,0x1d,0xc1,0x0c]
-; X86-NEXT:    vpaddw %xmm1, %xmm3, %xmm0 # encoding: [0xc5,0xe1,0xfd,0xc1]
-; X86-NEXT:    vpaddw %xmm0, %xmm2, %xmm0 # encoding: [0xc5,0xe9,0xfd,0xc0]
+; X86-NEXT:    vpaddw %xmm3, %xmm1, %xmm0 # encoding: [0xc5,0xf1,0xfd,0xc3]
+; X86-NEXT:    vpaddw %xmm2, %xmm0, %xmm0 # encoding: [0xc5,0xf9,0xfd,0xc2]
 ; X86-NEXT:    vzeroupper # encoding: [0xc5,0xf8,0x77]
 ; X86-NEXT:    retl # encoding: [0xc3]
 ;
 ; X64-LABEL: test_x86_vcvtps2ph_256:
 ; X64:       # %bb.0:
 ; X64-NEXT:    kmovw %edi, %k1 # encoding: [0xc5,0xf8,0x92,0xcf]
 ; X64-NEXT:    vcvtps2ph $2, %ymm0, %xmm2 # EVEX TO VEX Compression encoding: [0xc4,0xe3,0x7d,0x1d,0xc2,0x02]
 ; X64-NEXT:    vcvtps2ph $11, %ymm0, %xmm3 {%k1} {z} # encoding: [0x62,0xf3,0x7d,0xa9,0x1d,0xc3,0x0b]
 ; X64-NEXT:    vcvtps2ph $12, %ymm0, %xmm1 {%k1} # encoding: [0x62,0xf3,0x7d,0x29,0x1d,0xc1,0x0c]
-; X64-NEXT:    vpaddw %xmm1, %xmm3, %xmm0 # encoding: [0xc5,0xe1,0xfd,0xc1]
-; X64-NEXT:    vpaddw %xmm0, %xmm2, %xmm0 # encoding: [0xc5,0xe9,0xfd,0xc0]
+; X64-NEXT:    vpaddw %xmm3, %xmm1, %xmm0 # encoding: [0xc5,0xf1,0xfd,0xc3]
+; X64-NEXT:    vpaddw %xmm2, %xmm0, %xmm0 # encoding: [0xc5,0xf9,0xfd,0xc2]
 ; X64-NEXT:    vzeroupper # encoding: [0xc5,0xf8,0x77]
 ; X64-NEXT:    retq # encoding: [0xc3]
   %res1 = call <8 x i16> @llvm.x86.avx512.mask.vcvtps2ph.256(<8 x float> %a0, i32 2, <8 x i16> zeroinitializer, i8 -1)
   %res2 = call <8 x i16> @llvm.x86.avx512.mask.vcvtps2ph.256(<8 x float> %a0, i32 11, <8 x i16> zeroinitializer, i8 %mask)
   %res3 = call <8 x i16> @llvm.x86.avx512.mask.vcvtps2ph.256(<8 x float> %a0, i32 12, <8 x i16> %src, i8 %mask)
   %res0 = add <8 x i16> %res1, %res2
   %res = add <8 x i16> %res3, %res0
   ret <8 x i16> %res

llvm/test/CodeGen/X86/horizontal-sum.ll

 ; AVX1-SLOW-NEXT:    vpshufd {{.*#+}} xmm1 = xmm1[2,3,2,3]
 ; AVX1-SLOW-NEXT:    vpshufd {{.*#+}} xmm0 = xmm0[3,3,3,3]
 ; AVX1-SLOW-NEXT:    vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3],xmm0[4,5,6,7]
 ; AVX1-SLOW-NEXT:    vpshufd {{.*#+}} xmm1 = xmm2[1,1,1,1]
 ; AVX1-SLOW-NEXT:    vpaddd %xmm2, %xmm1, %xmm1
 ; AVX1-SLOW-NEXT:    vpunpcklqdq {{.*#+}} xmm1 = xmm4[0],xmm1[0]
 ; AVX1-SLOW-NEXT:    vpshufd {{.*#+}} xmm4 = xmm2[3,3,3,3]
 ; AVX1-SLOW-NEXT:    vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm4[0]
-; AVX1-SLOW-NEXT:    vpaddd %xmm0, %xmm1, %xmm0
+; AVX1-SLOW-NEXT:    vpaddd %xmm1, %xmm0, %xmm0
 ; AVX1-SLOW-NEXT:    vpblendw {{.*#+}} xmm1 = xmm5[0,1,2,3],xmm2[4,5,6,7]
-; AVX1-SLOW-NEXT:    vpaddd %xmm0, %xmm1, %xmm0
+; AVX1-SLOW-NEXT:    vpaddd %xmm1, %xmm0, %xmm0
 ; AVX1-SLOW-NEXT:    vpshufd {{.*#+}} xmm1 = xmm3[1,1,1,1]
 ; AVX1-SLOW-NEXT:    vpshufd {{.*#+}} xmm2 = xmm3[0,0,0,0]
 ; AVX1-SLOW-NEXT:    vpshufd {{.*#+}} xmm4 = xmm3[2,2,2,2]
-; AVX1-SLOW-NEXT:    vpaddd %xmm4, %xmm2, %xmm2
-; AVX1-SLOW-NEXT:    vpaddd %xmm3, %xmm2, %xmm2
+; AVX1-SLOW-NEXT:    vpaddd %xmm2, %xmm4, %xmm2
+; AVX1-SLOW-NEXT:    vpaddd %xmm1, %xmm3, %xmm1
 ; AVX1-SLOW-NEXT:    vpaddd %xmm2, %xmm1, %xmm1
 ; AVX1-SLOW-NEXT:    vpblendw {{.*#+}} xmm0 = xmm0[0,1,2,3,4,5],xmm1[6,7]
 ; AVX1-SLOW-NEXT:    retq
 ;
 ; AVX1-FAST-LABEL: sequential_sum_v4i32_v4i32:
 ; AVX1-FAST:       # %bb.0:
 ; AVX1-FAST-NEXT:    vphaddd %xmm1, %xmm0, %xmm4
 ; AVX1-FAST-NEXT:    vpshufd {{.*#+}} xmm4 = xmm4[0,2,2,3]
 ; AVX1-FAST-NEXT:    vpunpckhdq {{.*#+}} xmm5 = xmm0[2],xmm1[2],xmm0[3],xmm1[3]
 ; AVX1-FAST-NEXT:    vpshufd {{.*#+}} xmm1 = xmm1[2,3,2,3]
 ; AVX1-FAST-NEXT:    vpshufd {{.*#+}} xmm0 = xmm0[3,3,3,3]
 ; AVX1-FAST-NEXT:    vpblendw {{.*#+}} xmm0 = xmm0[0,1],xmm1[2,3],xmm0[4,5,6,7]
 ; AVX1-FAST-NEXT:    vphaddd %xmm2, %xmm2, %xmm1
 ; AVX1-FAST-NEXT:    vpunpcklqdq {{.*#+}} xmm1 = xmm4[0],xmm1[0]
 ; AVX1-FAST-NEXT:    vpshufd {{.*#+}} xmm4 = xmm2[3,3,3,3]
 ; AVX1-FAST-NEXT:    vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm4[0]
-; AVX1-FAST-NEXT:    vpaddd %xmm0, %xmm1, %xmm0
+; AVX1-FAST-NEXT:    vpaddd %xmm1, %xmm0, %xmm0
 ; AVX1-FAST-NEXT:    vpblendw {{.*#+}} xmm1 = xmm5[0,1,2,3],xmm2[4,5,6,7]
-; AVX1-FAST-NEXT:    vpaddd %xmm0, %xmm1, %xmm0
+; AVX1-FAST-NEXT:    vpaddd %xmm1, %xmm0, %xmm0
 ; AVX1-FAST-NEXT:    vphaddd %xmm3, %xmm3, %xmm1
 ; AVX1-FAST-NEXT:    vpshufd {{.*#+}} xmm2 = xmm3[2,2,2,2]
 ; AVX1-FAST-NEXT:    vpshufd {{.*#+}} xmm1 = xmm1[0,0,0,0]
-; AVX1-FAST-NEXT:    vpaddd %xmm3, %xmm1, %xmm1
-; AVX1-FAST-NEXT:    vpaddd %xmm1, %xmm2, %xmm1
+; AVX1-FAST-NEXT:    vpaddd %xmm1, %xmm3, %xmm1
+; AVX1-FAST-NEXT:    vpaddd %xmm2, %xmm1, %xmm1
 ; AVX1-FAST-NEXT:    vpblendw {{.*#+}} xmm0 = xmm0[0,1,2,3,4,5],xmm1[6,7]
 ; AVX1-FAST-NEXT:    retq
 ;
 ; AVX2-SLOW-LABEL: sequential_sum_v4i32_v4i32:
 ; AVX2-SLOW:       # %bb.0:
 ; AVX2-SLOW-NEXT:    vphaddd %xmm1, %xmm0, %xmm4
 ; AVX2-SLOW-NEXT:    vpshufd {{.*#+}} xmm4 = xmm4[0,2,2,3]
 ; AVX2-SLOW-NEXT:    vpunpckhdq {{.*#+}} xmm5 = xmm0[2],xmm1[2],xmm0[3],xmm1[3]
 ; AVX2-SLOW-NEXT:    vpshufd {{.*#+}} xmm1 = xmm1[2,3,2,3]
 ; AVX2-SLOW-NEXT:    vpshufd {{.*#+}} xmm0 = xmm0[3,3,3,3]
 ; AVX2-SLOW-NEXT:    vpblendd {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2,3]
 ; AVX2-SLOW-NEXT:    vpshufd {{.*#+}} xmm1 = xmm2[1,1,1,1]
 ; AVX2-SLOW-NEXT:    vpaddd %xmm2, %xmm1, %xmm1
 ; AVX2-SLOW-NEXT:    vpunpcklqdq {{.*#+}} xmm1 = xmm4[0],xmm1[0]
 ; AVX2-SLOW-NEXT:    vpshufd {{.*#+}} xmm4 = xmm2[3,3,3,3]
 ; AVX2-SLOW-NEXT:    vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm4[0]
 ; AVX2-SLOW-NEXT:    vpblendd {{.*#+}} xmm2 = xmm5[0,1],xmm2[2,3]
 ; AVX2-SLOW-NEXT:    vpshufd {{.*#+}} xmm4 = xmm3[1,1,1,1]
 ; AVX2-SLOW-NEXT:    vpbroadcastd %xmm3, %xmm5
 ; AVX2-SLOW-NEXT:    vpaddd %xmm5, %xmm4, %xmm4
 ; AVX2-SLOW-NEXT:    vpblendd {{.*#+}} xmm1 = xmm1[0,1,2],xmm4[3]
 ; AVX2-SLOW-NEXT:    vpshufd {{.*#+}} xmm4 = xmm3[2,2,2,2]
 ; AVX2-SLOW-NEXT:    vpblendd {{.*#+}} xmm2 = xmm2[0,1,2],xmm4[3]
 ; AVX2-SLOW-NEXT:    vpblendd {{.*#+}} xmm0 = xmm0[0,1,2],xmm3[3]
-; AVX2-SLOW-NEXT:    vpaddd %xmm0, %xmm1, %xmm0
-; AVX2-SLOW-NEXT:    vpaddd %xmm0, %xmm2, %xmm0
+; AVX2-SLOW-NEXT:    vpaddd %xmm1, %xmm0, %xmm0
+; AVX2-SLOW-NEXT:    vpaddd %xmm2, %xmm0, %xmm0
 ; AVX2-SLOW-NEXT:    retq
 ;
 ; AVX2-FAST-LABEL: sequential_sum_v4i32_v4i32:
 ; AVX2-FAST:       # %bb.0:
 ; AVX2-FAST-NEXT:    vphaddd %xmm1, %xmm0, %xmm4
 ; AVX2-FAST-NEXT:    vpshufd {{.*#+}} xmm4 = xmm4[0,2,2,3]
 ; AVX2-FAST-NEXT:    vpunpckhdq {{.*#+}} xmm5 = xmm0[2],xmm1[2],xmm0[3],xmm1[3]
 ; AVX2-FAST-NEXT:    vpshufd {{.*#+}} xmm1 = xmm1[2,3,2,3]
 ; AVX2-FAST-NEXT:    vpshufd {{.*#+}} xmm0 = xmm0[3,3,3,3]
 ; AVX2-FAST-NEXT:    vpblendd {{.*#+}} xmm0 = xmm0[0],xmm1[1],xmm0[2,3]
 ; AVX2-FAST-NEXT:    vphaddd %xmm2, %xmm2, %xmm1
 ; AVX2-FAST-NEXT:    vpunpcklqdq {{.*#+}} xmm1 = xmm4[0],xmm1[0]
 ; AVX2-FAST-NEXT:    vpshufd {{.*#+}} xmm4 = xmm2[3,3,3,3]
 ; AVX2-FAST-NEXT:    vpunpcklqdq {{.*#+}} xmm0 = xmm0[0],xmm4[0]
 ; AVX2-FAST-NEXT:    vpblendd {{.*#+}} xmm2 = xmm5[0,1],xmm2[2,3]
 ; AVX2-FAST-NEXT:    vphaddd %xmm3, %xmm3, %xmm4
 ; AVX2-FAST-NEXT:    vpshufd {{.*#+}} xmm5 = xmm3[2,2,2,2]
 ; AVX2-FAST-NEXT:    vpblendd {{.*#+}} xmm2 = xmm2[0,1,2],xmm5[3]
 ; AVX2-FAST-NEXT:    vpbroadcastd %xmm4, %xmm4
 ; AVX2-FAST-NEXT:    vpblendd {{.*#+}} xmm1 = xmm1[0,1,2],xmm4[3]
 ; AVX2-FAST-NEXT:    vpblendd {{.*#+}} xmm0 = xmm0[0,1,2],xmm3[3]
-; AVX2-FAST-NEXT:    vpaddd %xmm0, %xmm1, %xmm0
-; AVX2-FAST-NEXT:    vpaddd %xmm0, %xmm2, %xmm0
+; AVX2-FAST-NEXT:    vpaddd %xmm1, %xmm0, %xmm0
+; AVX2-FAST-NEXT:    vpaddd %xmm2, %xmm0, %xmm0
 ; AVX2-FAST-NEXT:    retq
   %5 = shufflevector <4 x i32> %0, <4 x i32> %1, <2 x i32> <i32 0, i32 4>
   %6 = shufflevector <4 x i32> %0, <4 x i32> %1, <2 x i32> <i32 1, i32 5>
   %7 = add <2 x i32> %5, %6
   %8 = shufflevector <4 x i32> %0, <4 x i32> %1, <2 x i32> <i32 2, i32 6>
   %9 = add <2 x i32> %8, %7
   %10 = shufflevector <4 x i32> %0, <4 x i32> %1, <2 x i32> <i32 3, i32 7>
   %11 = add <2 x i32> %10, %9

llvm/test/CodeGen/X86/machine-combiner-int-vec.ll

 ; SSE-NEXT:    paddd %xmm1, %xmm0
 ; SSE-NEXT:    pand %xmm3, %xmm2
 ; SSE-NEXT:    pand %xmm2, %xmm0
 ; SSE-NEXT:    retq
 ;
 ; AVX2-LABEL: reassociate_and_v4i32:
 ; AVX2:       # %bb.0:
 ; AVX2-NEXT:    vpaddd %xmm1, %xmm0, %xmm0
-; AVX2-NEXT:    vpand %xmm3, %xmm2, %xmm1
-; AVX2-NEXT:    vpand %xmm1, %xmm0, %xmm0
+; AVX2-NEXT:    vpand %xmm2, %xmm3, %xmm1
+; AVX2-NEXT:    vpand %xmm0, %xmm1, %xmm0
 ; AVX2-NEXT:    retq
 ;
 ; AVX512-LABEL: reassociate_and_v4i32:
 ; AVX512:       # %bb.0:
 ; AVX512-NEXT:    vpaddd %xmm1, %xmm0, %xmm0
 ; AVX512-NEXT:    vpternlogd $128, %xmm2, %xmm3, %xmm0
 ; AVX512-NEXT:    retq
 

 ; SSE-NEXT:    paddd %xmm1, %xmm0
 ; SSE-NEXT:    por %xmm3, %xmm2
 ; SSE-NEXT:    por %xmm2, %xmm0
 ; SSE-NEXT:    retq
 ;
 ; AVX2-LABEL: reassociate_or_v4i32:
 ; AVX2:       # %bb.0:
 ; AVX2-NEXT:    vpaddd %xmm1, %xmm0, %xmm0
-; AVX2-NEXT:    vpor %xmm3, %xmm2, %xmm1
-; AVX2-NEXT:    vpor %xmm1, %xmm0, %xmm0
+; AVX2-NEXT:    vpor %xmm2, %xmm3, %xmm1
+; AVX2-NEXT:    vpor %xmm0, %xmm1, %xmm0
 ; AVX2-NEXT:    retq
 ;
 ; AVX512-LABEL: reassociate_or_v4i32:
 ; AVX512:       # %bb.0:
 ; AVX512-NEXT:    vpaddd %xmm1, %xmm0, %xmm0
 ; AVX512-NEXT:    vpternlogd $254, %xmm2, %xmm3, %xmm0
 ; AVX512-NEXT:    retq
 

 ; SSE-NEXT:    paddd %xmm1, %xmm0
 ; SSE-NEXT:    pxor %xmm3, %xmm2
 ; SSE-NEXT:    pxor %xmm2, %xmm0
 ; SSE-NEXT:    retq
 ;
 ; AVX2-LABEL: reassociate_xor_v4i32:
 ; AVX2:       # %bb.0:
 ; AVX2-NEXT:    vpaddd %xmm1, %xmm0, %xmm0
-; AVX2-NEXT:    vpxor %xmm3, %xmm2, %xmm1
-; AVX2-NEXT:    vpxor %xmm1, %xmm0, %xmm0
+; AVX2-NEXT:    vpxor %xmm2, %xmm3, %xmm1
+; AVX2-NEXT:    vpxor %xmm0, %xmm1, %xmm0
 ; AVX2-NEXT:    retq
 ;
 ; AVX512-LABEL: reassociate_xor_v4i32:
 ; AVX512:       # %bb.0:
 ; AVX512-NEXT:    vpaddd %xmm1, %xmm0, %xmm0
 ; AVX512-NEXT:    vpternlogd $150, %xmm2, %xmm3, %xmm0
 ; AVX512-NEXT:    retq
 

 ; SSE-NEXT:    paddd %xmm3, %xmm1
 ; SSE-NEXT:    pand %xmm7, %xmm5
 ; SSE-NEXT:    pand %xmm5, %xmm1
 ; SSE-NEXT:    retq
 ;
 ; AVX2-LABEL: reassociate_and_v8i32:
 ; AVX2:       # %bb.0:
 ; AVX2-NEXT:    vpaddd %ymm1, %ymm0, %ymm0
-; AVX2-NEXT:    vpand %ymm3, %ymm2, %ymm1
-; AVX2-NEXT:    vpand %ymm1, %ymm0, %ymm0
+; AVX2-NEXT:    vpand %ymm2, %ymm3, %ymm1
+; AVX2-NEXT:    vpand %ymm0, %ymm1, %ymm0
 ; AVX2-NEXT:    retq
 ;
 ; AVX512-LABEL: reassociate_and_v8i32:
 ; AVX512:       # %bb.0:
 ; AVX512-NEXT:    vpaddd %ymm1, %ymm0, %ymm0
 ; AVX512-NEXT:    vpternlogd $128, %ymm2, %ymm3, %ymm0
 ; AVX512-NEXT:    retq
 

 ; SSE-NEXT:    paddd %xmm3, %xmm1
 ; SSE-NEXT:    por %xmm7, %xmm5
 ; SSE-NEXT:    por %xmm5, %xmm1
 ; SSE-NEXT:    retq
 ;
 ; AVX2-LABEL: reassociate_or_v8i32:
 ; AVX2:       # %bb.0:
 ; AVX2-NEXT:    vpaddd %ymm1, %ymm0, %ymm0
-; AVX2-NEXT:    vpor %ymm3, %ymm2, %ymm1
-; AVX2-NEXT:    vpor %ymm1, %ymm0, %ymm0
+; AVX2-NEXT:    vpor %ymm2, %ymm3, %ymm1
+; AVX2-NEXT:    vpor %ymm0, %ymm1, %ymm0
 ; AVX2-NEXT:    retq
 ;
 ; AVX512-LABEL: reassociate_or_v8i32:
 ; AVX512:       # %bb.0:
 ; AVX512-NEXT:    vpaddd %ymm1, %ymm0, %ymm0
 ; AVX512-NEXT:    vpternlogd $254, %ymm2, %ymm3, %ymm0
 ; AVX512-NEXT:    retq
 

 ; SSE-NEXT:    paddd %xmm3, %xmm1
 ; SSE-NEXT:    pxor %xmm7, %xmm5
 ; SSE-NEXT:    pxor %xmm5, %xmm1
 ; SSE-NEXT:    retq
 ;
 ; AVX2-LABEL: reassociate_xor_v8i32:
 ; AVX2:       # %bb.0:
 ; AVX2-NEXT:    vpaddd %ymm1, %ymm0, %ymm0
-; AVX2-NEXT:    vpxor %ymm3, %ymm2, %ymm1
-; AVX2-NEXT:    vpxor %ymm1, %ymm0, %ymm0
+; AVX2-NEXT:    vpxor %ymm2, %ymm3, %ymm1
+; AVX2-NEXT:    vpxor %ymm0, %ymm1, %ymm0
 ; AVX2-NEXT:    retq
 ;
 ; AVX512-LABEL: reassociate_xor_v8i32:
 ; AVX512:       # %bb.0:
 ; AVX512-NEXT:    vpaddd %ymm1, %ymm0, %ymm0
 ; AVX512-NEXT:    vpternlogd $150, %ymm2, %ymm3, %ymm0
 ; AVX512-NEXT:    retq
 

 ; SSE-NEXT:    pand {{[0-9]+}}(%rsp), %xmm1
 ; SSE-NEXT:    pand {{[0-9]+}}(%rsp), %xmm2
 ; SSE-NEXT:    pand {{[0-9]+}}(%rsp), %xmm3
 ; SSE-NEXT:    retq
 ;
 ; AVX2-LABEL: reassociate_and_v16i32:
 ; AVX2:       # %bb.0:
 ; AVX2-NEXT:    vpaddd %ymm2, %ymm0, %ymm0
-; AVX2-NEXT:    vpand %ymm6, %ymm4, %ymm2
-; AVX2-NEXT:    vpand %ymm2, %ymm0, %ymm0
+; AVX2-NEXT:    vpand %ymm4, %ymm6, %ymm2
+; AVX2-NEXT:    vpand %ymm0, %ymm2, %ymm0
 ; AVX2-NEXT:    vpaddd %ymm3, %ymm1, %ymm1
-; AVX2-NEXT:    vpand %ymm7, %ymm5, %ymm2
-; AVX2-NEXT:    vpand %ymm2, %ymm1, %ymm1
+; AVX2-NEXT:    vpand %ymm5, %ymm7, %ymm2
+; AVX2-NEXT:    vpand %ymm1, %ymm2, %ymm1
 ; AVX2-NEXT:    retq
 ;
 ; AVX512-LABEL: reassociate_and_v16i32:
 ; AVX512:       # %bb.0:
 ; AVX512-NEXT:    vpaddd %zmm1, %zmm0, %zmm0
 ; AVX512-NEXT:    vpternlogd $128, %zmm2, %zmm3, %zmm0
 ; AVX512-NEXT:    retq
 

 ; SSE-NEXT:    por {{[0-9]+}}(%rsp), %xmm1
 ; SSE-NEXT:    por {{[0-9]+}}(%rsp), %xmm2
 ; SSE-NEXT:    por {{[0-9]+}}(%rsp), %xmm3
 ; SSE-NEXT:    retq
 ;
 ; AVX2-LABEL: reassociate_or_v16i32:
 ; AVX2:       # %bb.0:
 ; AVX2-NEXT:    vpaddd %ymm2, %ymm0, %ymm0
-; AVX2-NEXT:    vpor %ymm6, %ymm4, %ymm2
-; AVX2-NEXT:    vpor %ymm2, %ymm0, %ymm0
+; AVX2-NEXT:    vpor %ymm4, %ymm6, %ymm2
+; AVX2-NEXT:    vpor %ymm0, %ymm2, %ymm0
 ; AVX2-NEXT:    vpaddd %ymm3, %ymm1, %ymm1
-; AVX2-NEXT:    vpor %ymm7, %ymm5, %ymm2
-; AVX2-NEXT:    vpor %ymm2, %ymm1, %ymm1
+; AVX2-NEXT:    vpor %ymm5, %ymm7, %ymm2
+; AVX2-NEXT:    vpor %ymm1, %ymm2, %ymm1
 ; AVX2-NEXT:    retq
 ;
 ; AVX512-LABEL: reassociate_or_v16i32:
 ; AVX512:       # %bb.0:
 ; AVX512-NEXT:    vpaddd %zmm1, %zmm0, %zmm0
 ; AVX512-NEXT:    vpternlogd $254, %zmm2, %zmm3, %zmm0
 ; AVX512-NEXT:    retq
 

 ; SSE-NEXT:    pxor {{[0-9]+}}(%rsp), %xmm1
 ; SSE-NEXT:    pxor {{[0-9]+}}(%rsp), %xmm2
 ; SSE-NEXT:    pxor {{[0-9]+}}(%rsp), %xmm3
 ; SSE-NEXT:    retq
 ;
 ; AVX2-LABEL: reassociate_xor_v16i32:
 ; AVX2:       # %bb.0:
 ; AVX2-NEXT:    vpaddd %ymm2, %ymm0, %ymm0
-; AVX2-NEXT:    vpxor %ymm6, %ymm4, %ymm2
-; AVX2-NEXT:    vpxor %ymm2, %ymm0, %ymm0
+; AVX2-NEXT:    vpxor %ymm4, %ymm6, %ymm2
+; AVX2-NEXT:    vpxor %ymm0, %ymm2, %ymm0
 ; AVX2-NEXT:    vpaddd %ymm3, %ymm1, %ymm1
-; AVX2-NEXT:    vpxor %ymm7, %ymm5, %ymm2
-; AVX2-NEXT:    vpxor %ymm2, %ymm1, %ymm1
+; AVX2-NEXT:    vpxor %ymm5, %ymm7, %ymm2
+; AVX2-NEXT:    vpxor %ymm1, %ymm2, %ymm1
 ; AVX2-NEXT:    retq
 ;
 ; AVX512-LABEL: reassociate_xor_v16i32:
 ; AVX512:       # %bb.0:
 ; AVX512-NEXT:    vpaddd %zmm1, %zmm0, %zmm0
 ; AVX512-NEXT:    vpternlogd $150, %zmm2, %zmm3, %zmm0
 ; AVX512-NEXT:    retq
 

 ; SSE-NEXT:    paddb %xmm1, %xmm0
 ; SSE-NEXT:    pmaxub %xmm3, %xmm2
 ; SSE-NEXT:    pmaxub %xmm2, %xmm0
 ; SSE-NEXT:    retq
 ;
 ; AVX-LABEL: reassociate_umax_v16i8:
 ; AVX:       # %bb.0:
 ; AVX-NEXT:    vpaddb %xmm1, %xmm0, %xmm0
-; AVX-NEXT:    vpmaxub %xmm3, %xmm2, %xmm1
-; AVX-NEXT:    vpmaxub %xmm1, %xmm0, %xmm0
+; AVX-NEXT:    vpmaxub %xmm2, %xmm3, %xmm1
+; AVX-NEXT:    vpmaxub %xmm0, %xmm1, %xmm0
 ; AVX-NEXT:    retq
 
   %t0 = add <16 x i8> %x0, %x1
   %t1 = icmp ugt <16 x i8> %x2, %t0
   %t2 = select <16 x i1> %t1, <16 x i8> %x2, <16 x i8> %t0
   %t3 = icmp ugt <16 x i8> %x3, %t2
   %t4 = select <16 x i1> %t3, <16 x i8> %x3, <16 x i8> %t2
   ret <16 x i8> %t4
 }
 
 define <8 x i16> @reassociate_umax_v8i16(<8 x i16> %x0, <8 x i16> %x1, <8 x i16> %x2, <8 x i16> %x3) {
 ; SSE-LABEL: reassociate_umax_v8i16:
 ; SSE:       # %bb.0:
 ; SSE-NEXT:    paddw %xmm1, %xmm0
 ; SSE-NEXT:    psubusw %xmm2, %xmm0
 ; SSE-NEXT:    paddw %xmm2, %xmm0
 ; SSE-NEXT:    psubusw %xmm3, %xmm0
 ; SSE-NEXT:    paddw %xmm3, %xmm0
 ; SSE-NEXT:    retq
 ;
 ; AVX-LABEL: reassociate_umax_v8i16:
 ; AVX:       # %bb.0:
 ; AVX-NEXT:    vpaddw %xmm1, %xmm0, %xmm0
-; AVX-NEXT:    vpmaxuw %xmm3, %xmm2, %xmm1
-; AVX-NEXT:    vpmaxuw %xmm1, %xmm0, %xmm0
+; AVX-NEXT:    vpmaxuw %xmm2, %xmm3, %xmm1
+; AVX-NEXT:    vpmaxuw %xmm0, %xmm1, %xmm0
 ; AVX-NEXT:    retq
 
   %t0 = add <8 x i16> %x0, %x1
   %t1 = icmp ugt <8 x i16> %x2, %t0
   %t2 = select <8 x i1> %t1, <8 x i16> %x2, <8 x i16> %t0
   %t3 = icmp ugt <8 x i16> %x3, %t2
   %t4 = select <8 x i1> %t3, <8 x i16> %x3, <8 x i16> %t2
   ret <8 x i16> %t4

 ; SSE-NEXT:    pandn %xmm4, %xmm1
 ; SSE-NEXT:    por %xmm3, %xmm1
 ; SSE-NEXT:    movdqa %xmm1, %xmm0
 ; SSE-NEXT:    retq
 ;
 ; AVX-LABEL: reassociate_umax_v4i32:
 ; AVX:       # %bb.0:
 ; AVX-NEXT:    vpaddd %xmm1, %xmm0, %xmm0
-; AVX-NEXT:    vpmaxud %xmm3, %xmm2, %xmm1
-; AVX-NEXT:    vpmaxud %xmm1, %xmm0, %xmm0
+; AVX-NEXT:    vpmaxud %xmm2, %xmm3, %xmm1
+; AVX-NEXT:    vpmaxud %xmm0, %xmm1, %xmm0
 ; AVX-NEXT:    retq
 
   %t0 = add <4 x i32> %x0, %x1
   %t1 = icmp ugt <4 x i32> %x2, %t0
   %t2 = select <4 x i1> %t1, <4 x i32> %x2, <4 x i32> %t0
   %t3 = icmp ugt <4 x i32> %x3, %t2
   %t4 = select <4 x i1> %t3, <4 x i32> %x3, <4 x i32> %t2
   ret <4 x i32> %t4

 ; AVX2-NEXT:    vpxor %xmm1, %xmm3, %xmm1
 ; AVX2-NEXT:    vpcmpgtq %xmm2, %xmm1, %xmm1
 ; AVX2-NEXT:    vblendvpd %xmm1, %xmm3, %xmm0, %xmm0
 ; AVX2-NEXT:    retq
 ;
 ; AVX512-LABEL: reassociate_umax_v2i64:
 ; AVX512:       # %bb.0:
 ; AVX512-NEXT:    vpaddq %xmm1, %xmm0, %xmm0
-; AVX512-NEXT:    vpmaxuq %xmm3, %xmm2, %xmm1
-; AVX512-NEXT:    vpmaxuq %xmm1, %xmm0, %xmm0
+; AVX512-NEXT:    vpmaxuq %xmm2, %xmm3, %xmm1
+; AVX512-NEXT:    vpmaxuq %xmm0, %xmm1, %xmm0
 ; AVX512-NEXT:    retq
 
   %t0 = add <2 x i64> %x0, %x1
   %t1 = icmp ugt <2 x i64> %x2, %t0
   %t2 = select <2 x i1> %t1, <2 x i64> %x2, <2 x i64> %t0
   %t3 = icmp ugt <2 x i64> %x3, %t2
   %t4 = select <2 x i1> %t3, <2 x i64> %x3, <2 x i64> %t2
   ret <2 x i64> %t4

 ; SSE-NEXT:    pand %xmm0, %xmm3
 ; SSE-NEXT:    pandn %xmm1, %xmm0
 ; SSE-NEXT:    por %xmm3, %xmm0
 ; SSE-NEXT:    retq
 ;
 ; AVX-LABEL: reassociate_smax_v16i8:
 ; AVX:       # %bb.0:
 ; AVX-NEXT:    vpaddb %xmm1, %xmm0, %xmm0
-; AVX-NEXT:    vpmaxsb %xmm3, %xmm2, %xmm1
-; AVX-NEXT:    vpmaxsb %xmm1, %xmm0, %xmm0
+; AVX-NEXT:    vpmaxsb %xmm2, %xmm3, %xmm1
+; AVX-NEXT:    vpmaxsb %xmm0, %xmm1, %xmm0
 ; AVX-NEXT:    retq
 
   %t0 = add <16 x i8> %x0, %x1
   %t1 = icmp sgt <16 x i8> %x2, %t0
   %t2 = select <16 x i1> %t1, <16 x i8> %x2, <16 x i8> %t0
   %t3 = icmp sgt <16 x i8> %x3, %t2
   %t4 = select <16 x i1> %t3, <16 x i8> %x3, <16 x i8> %t2
   ret <16 x i8> %t4
 }
 
 define <8 x i16> @reassociate_smax_v8i16(<8 x i16> %x0, <8 x i16> %x1, <8 x i16> %x2, <8 x i16> %x3) {
 ; SSE-LABEL: reassociate_smax_v8i16:
 ; SSE:       # %bb.0:
 ; SSE-NEXT:    paddw %xmm1, %xmm0
 ; SSE-NEXT:    pmaxsw %xmm3, %xmm2
 ; SSE-NEXT:    pmaxsw %xmm2, %xmm0
 ; SSE-NEXT:    retq
 ;
 ; AVX-LABEL: reassociate_smax_v8i16:
 ; AVX:       # %bb.0:
 ; AVX-NEXT:    vpaddw %xmm1, %xmm0, %xmm0
-; AVX-NEXT:    vpmaxsw %xmm3, %xmm2, %xmm1
-; AVX-NEXT:    vpmaxsw %xmm1, %xmm0, %xmm0
+; AVX-NEXT:    vpmaxsw %xmm2, %xmm3, %xmm1
+; AVX-NEXT:    vpmaxsw %xmm0, %xmm1, %xmm0
 ; AVX-NEXT:    retq
 
   %t0 = add <8 x i16> %x0, %x1
   %t1 = icmp sgt <8 x i16> %x2, %t0
   %t2 = select <8 x i1> %t1, <8 x i16> %x2, <8 x i16> %t0
   %t3 = icmp sgt <8 x i16> %x3, %t2
   %t4 = select <8 x i1> %t3, <8 x i16> %x3, <8 x i16> %t2
   ret <8 x i16> %t4

 ; SSE-NEXT:    pand %xmm0, %xmm3
 ; SSE-NEXT:    pandn %xmm1, %xmm0
 ; SSE-NEXT:    por %xmm3, %xmm0
 ; SSE-NEXT:    retq
 ;
 ; AVX-LABEL: reassociate_smax_v4i32:
 ; AVX:       # %bb.0:
 ; AVX-NEXT:    vpaddd %xmm1, %xmm0, %xmm0
-; AVX-NEXT:    vpmaxsd %xmm3, %xmm2, %xmm1
-; AVX-NEXT:    vpmaxsd %xmm1, %xmm0, %xmm0
+; AVX-NEXT:    vpmaxsd %xmm2, %xmm3, %xmm1
+; AVX-NEXT:    vpmaxsd %xmm0, %xmm1, %xmm0
 ; AVX-NEXT:    retq
 
   %t0 = add <4 x i32> %x0, %x1
   %t1 = icmp sgt <4 x i32> %x2, %t0
   %t2 = select <4 x i1> %t1, <4 x i32> %x2, <4 x i32> %t0
   %t3 = icmp sgt <4 x i32> %x3, %t2
   %t4 = select <4 x i1> %t3, <4 x i32> %x3, <4 x i32> %t2
   ret <4 x i32> %t4

 ; AVX2-NEXT:    vblendvpd %xmm1, %xmm2, %xmm0, %xmm0
 ; AVX2-NEXT:    vpcmpgtq %xmm0, %xmm3, %xmm1
 ; AVX2-NEXT:    vblendvpd %xmm1, %xmm3, %xmm0, %xmm0
 ; AVX2-NEXT:    retq
 ;
 ; AVX512-LABEL: reassociate_smax_v2i64:
 ; AVX512:       # %bb.0:
 ; AVX512-NEXT:    vpaddq %xmm1, %xmm0, %xmm0
-; AVX512-NEXT:    vpmaxsq %xmm3, %xmm2, %xmm1
-; AVX512-NEXT:    vpmaxsq %xmm1, %xmm0, %xmm0
+; AVX512-NEXT:    vpmaxsq %xmm2, %xmm3, %xmm1
+; AVX512-NEXT:    vpmaxsq %xmm0, %xmm1, %xmm0
 ; AVX512-NEXT:    retq
 
   %t0 = add <2 x i64> %x0, %x1
   %t1 = icmp sgt <2 x i64> %x2, %t0
   %t2 = select <2 x i1> %t1, <2 x i64> %x2, <2 x i64> %t0
   %t3 = icmp sgt <2 x i64> %x3, %t2
   %t4 = select <2 x i1> %t3, <2 x i64> %x3, <2 x i64> %t2
   ret <2 x i64> %t4
 }
 
 define <16 x i8> @reassociate_umin_v16i8(<16 x i8> %x0, <16 x i8> %x1, <16 x i8> %x2, <16 x i8> %x3) {
 ; SSE-LABEL: reassociate_umin_v16i8:
 ; SSE:       # %bb.0:
 ; SSE-NEXT:    paddb %xmm1, %xmm0
 ; SSE-NEXT:    pminub %xmm3, %xmm2
 ; SSE-NEXT:    pminub %xmm2, %xmm0
 ; SSE-NEXT:    retq
 ;
 ; AVX-LABEL: reassociate_umin_v16i8:
 ; AVX:       # %bb.0:
 ; AVX-NEXT:    vpaddb %xmm1, %xmm0, %xmm0
-; AVX-NEXT:    vpminub %xmm3, %xmm2, %xmm1
-; AVX-NEXT:    vpminub %xmm1, %xmm0, %xmm0
+; AVX-NEXT:    vpminub %xmm2, %xmm3, %xmm1
+; AVX-NEXT:    vpminub %xmm0, %xmm1, %xmm0
 ; AVX-NEXT:    retq
 
   %t0 = add <16 x i8> %x0, %x1
   %t1 = icmp ult <16 x i8> %x2, %t0
   %t2 = select <16 x i1> %t1, <16 x i8> %x2, <16 x i8> %t0
   %t3 = icmp ult <16 x i8> %x3, %t2
   %t4 = select <16 x i1> %t3, <16 x i8> %x3, <16 x i8> %t2
   ret <16 x i8> %t4

 ; SSE-NEXT:    psubusw %xmm2, %xmm0
 ; SSE-NEXT:    psubw %xmm0, %xmm3
 ; SSE-NEXT:    movdqa %xmm3, %xmm0
 ; SSE-NEXT:    retq
 ;
 ; AVX-LABEL: reassociate_umin_v8i16:
 ; AVX:       # %bb.0:
 ; AVX-NEXT:    vpaddw %xmm1, %xmm0, %xmm0
-; AVX-NEXT:    vpminuw %xmm3, %xmm2, %xmm1
-; AVX-NEXT:    vpminuw %xmm1, %xmm0, %xmm0
+; AVX-NEXT:    vpminuw %xmm2, %xmm3, %xmm1
+; AVX-NEXT:    vpminuw %xmm0, %xmm1, %xmm0
 ; AVX-NEXT:    retq
 
   %t0 = add <8 x i16> %x0, %x1
   %t1 = icmp ult <8 x i16> %x2, %t0
   %t2 = select <8 x i1> %t1, <8 x i16> %x2, <8 x i16> %t0
   %t3 = icmp ult <8 x i16> %x3, %t2
   %t4 = select <8 x i1> %t3, <8 x i16> %x3, <8 x i16> %t2
   ret <8 x i16> %t4

 ; SSE-NEXT:    pand %xmm0, %xmm3
 ; SSE-NEXT:    pandn %xmm5, %xmm0
 ; SSE-NEXT:    por %xmm3, %xmm0
 ; SSE-NEXT:    retq
 ;
 ; AVX-LABEL: reassociate_umin_v4i32:
 ; AVX:       # %bb.0:
 ; AVX-NEXT:    vpaddd %xmm1, %xmm0, %xmm0
-; AVX-NEXT:    vpminud %xmm3, %xmm2, %xmm1
-; AVX-NEXT:    vpminud %xmm1, %xmm0, %xmm0
+; AVX-NEXT:    vpminud %xmm2, %xmm3, %xmm1
+; AVX-NEXT:    vpminud %xmm0, %xmm1, %xmm0
 ; AVX-NEXT:    retq
 
   %t0 = add <4 x i32> %x0, %x1
   %t1 = icmp ult <4 x i32> %x2, %t0
   %t2 = select <4 x i1> %t1, <4 x i32> %x2, <4 x i32> %t0
   %t3 = icmp ult <4 x i32> %x3, %t2
   %t4 = select <4 x i1> %t3, <4 x i32> %x3, <4 x i32> %t2
   ret <4 x i32> %t4

 ; AVX2-NEXT:    vpxor %xmm1, %xmm3, %xmm1
 ; AVX2-NEXT:    vpcmpgtq %xmm1, %xmm2, %xmm1
 ; AVX2-NEXT:    vblendvpd %xmm1, %xmm3, %xmm0, %xmm0
 ; AVX2-NEXT:    retq
 ;
 ; AVX512-LABEL: reassociate_umin_v2i64:
 ; AVX512:       # %bb.0:
 ; AVX512-NEXT:    vpaddq %xmm1, %xmm0, %xmm0
-; AVX512-NEXT:    vpminuq %xmm3, %xmm2, %xmm1
-; AVX512-NEXT:    vpminuq %xmm1, %xmm0, %xmm0
+; AVX512-NEXT:    vpminuq %xmm2, %xmm3, %xmm1
+; AVX512-NEXT:    vpminuq %xmm0, %xmm1, %xmm0
 ; AVX512-NEXT:    retq
 
   %t0 = add <2 x i64> %x0, %x1
   %t1 = icmp ult <2 x i64> %x2, %t0
   %t2 = select <2 x i1> %t1, <2 x i64> %x2, <2 x i64> %t0
   %t3 = icmp ult <2 x i64> %x3, %t2
   %t4 = select <2 x i1> %t3, <2 x i64> %x3, <2 x i64> %t2
   ret <2 x i64> %t4

 ; SSE-NEXT:    pand %xmm0, %xmm3
 ; SSE-NEXT:    pandn %xmm1, %xmm0
 ; SSE-NEXT:    por %xmm3, %xmm0
 ; SSE-NEXT:    retq
 ;
 ; AVX-LABEL: reassociate_smin_v16i8:
 ; AVX:       # %bb.0:
 ; AVX-NEXT:    vpaddb %xmm1, %xmm0, %xmm0
-; AVX-NEXT:    vpminsb %xmm3, %xmm2, %xmm1
-; AVX-NEXT:    vpminsb %xmm1, %xmm0, %xmm0
+; AVX-NEXT:    vpminsb %xmm2, %xmm3, %xmm1
+; AVX-NEXT:    vpminsb %xmm0, %xmm1, %xmm0
 ; AVX-NEXT:    retq
 
   %t0 = add <16 x i8> %x0, %x1
   %t1 = icmp slt <16 x i8> %x2, %t0
   %t2 = select <16 x i1> %t1, <16 x i8> %x2, <16 x i8> %t0
   %t3 = icmp slt <16 x i8> %x3, %t2
   %t4 = select <16 x i1> %t3, <16 x i8> %x3, <16 x i8> %t2
   ret <16 x i8> %t4
 }
 
 define <8 x i16> @reassociate_smin_v8i16(<8 x i16> %x0, <8 x i16> %x1, <8 x i16> %x2, <8 x i16> %x3) {
 ; SSE-LABEL: reassociate_smin_v8i16:
 ; SSE:       # %bb.0:
 ; SSE-NEXT:    paddw %xmm1, %xmm0
 ; SSE-NEXT:    pminsw %xmm3, %xmm2
 ; SSE-NEXT:    pminsw %xmm2, %xmm0
 ; SSE-NEXT:    retq
 ;
 ; AVX-LABEL: reassociate_smin_v8i16:
 ; AVX:       # %bb.0:
 ; AVX-NEXT:    vpaddw %xmm1, %xmm0, %xmm0
-; AVX-NEXT:    vpminsw %xmm3, %xmm2, %xmm1
-; AVX-NEXT:    vpminsw %xmm1, %xmm0, %xmm0
+; AVX-NEXT:    vpminsw %xmm2, %xmm3, %xmm1
+; AVX-NEXT:    vpminsw %xmm0, %xmm1, %xmm0
 ; AVX-NEXT:    retq
 
   %t0 = add <8 x i16> %x0, %x1
   %t1 = icmp slt <8 x i16> %x2, %t0
   %t2 = select <8 x i1> %t1, <8 x i16> %x2, <8 x i16> %t0
   %t3 = icmp slt <8 x i16> %x3, %t2
   %t4 = select <8 x i1> %t3, <8 x i16> %x3, <8 x i16> %t2
   ret <8 x i16> %t4

 ; SSE-NEXT:    pand %xmm0, %xmm3
 ; SSE-NEXT:    pandn %xmm1, %xmm0
 ; SSE-NEXT:    por %xmm3, %xmm0
 ; SSE-NEXT:    retq
 ;
 ; AVX-LABEL: reassociate_smin_v4i32:
 ; AVX:       # %bb.0:
 ; AVX-NEXT:    vpaddd %xmm1, %xmm0, %xmm0
-; AVX-NEXT:    vpminsd %xmm3, %xmm2, %xmm1
-; AVX-NEXT:    vpminsd %xmm1, %xmm0, %xmm0
+; AVX-NEXT:    vpminsd %xmm2, %xmm3, %xmm1
+; AVX-NEXT:    vpminsd %xmm0, %xmm1, %xmm0
 ; AVX-NEXT:    retq
 
   %t0 = add <4 x i32> %x0, %x1
   %t1 = icmp slt <4 x i32> %x2, %t0
   %t2 = select <4 x i1> %t1, <4 x i32> %x2, <4 x i32> %t0
   %t3 = icmp slt <4 x i32> %x3, %t2
   %t4 = select <4 x i1> %t3, <4 x i32> %x3, <4 x i32> %t2
   ret <4 x i32> %t4

 ; AVX2-NEXT:    vblendvpd %xmm1, %xmm2, %xmm0, %xmm0
 ; AVX2-NEXT:    vpcmpgtq %xmm3, %xmm0, %xmm1
 ; AVX2-NEXT:    vblendvpd %xmm1, %xmm3, %xmm0, %xmm0
 ; AVX2-NEXT:    retq
 ;
 ; AVX512-LABEL: reassociate_smin_v2i64:
 ; AVX512:       # %bb.0:
 ; AVX512-NEXT:    vpaddq %xmm1, %xmm0, %xmm0
-; AVX512-NEXT:    vpminsq %xmm3, %xmm2, %xmm1
-; AVX512-NEXT:    vpminsq %xmm1, %xmm0, %xmm0
+; AVX512-NEXT:    vpminsq %xmm2, %xmm3, %xmm1
+; AVX512-NEXT:    vpminsq %xmm0, %xmm1, %xmm0
 ; AVX512-NEXT:    retq
 
   %t0 = add <2 x i64> %x0, %x1
   %t1 = icmp slt <2 x i64> %x2, %t0
   %t2 = select <2 x i1> %t1, <2 x i64> %x2, <2 x i64> %t0
   %t3 = icmp slt <2 x i64> %x3, %t2
   %t4 = select <2 x i1> %t3, <2 x i64> %x3, <2 x i64> %t2
   ret <2 x i64> %t4

 ; SSE-NEXT:    pmaxub %xmm4, %xmm0
 ; SSE-NEXT:    pmaxub %xmm7, %xmm5
 ; SSE-NEXT:    pmaxub %xmm5, %xmm1
 ; SSE-NEXT:    retq
 ;
 ; AVX-LABEL: reassociate_umax_v32i8:
 ; AVX:       # %bb.0:
 ; AVX-NEXT:    vpaddb %ymm1, %ymm0, %ymm0
-; AVX-NEXT:    vpmaxub %ymm3, %ymm2, %ymm1
-; AVX-NEXT:    vpmaxub %ymm1, %ymm0, %ymm0
+; AVX-NEXT:    vpmaxub %ymm2, %ymm3, %ymm1
+; AVX-NEXT:    vpmaxub %ymm0, %ymm1, %ymm0
 ; AVX-NEXT:    retq
 
   %t0 = add <32 x i8> %x0, %x1
   %t1 = icmp ugt <32 x i8> %x2, %t0
   %t2 = select <32 x i1> %t1, <32 x i8> %x2, <32 x i8> %t0
   %t3 = icmp ugt <32 x i8> %x3, %t2
   %t4 = select <32 x i1> %t3, <32 x i8> %x3, <32 x i8> %t2
   ret <32 x i8> %t4

 ; SSE-NEXT:    paddw %xmm6, %xmm0
 ; SSE-NEXT:    psubusw %xmm7, %xmm1
 ; SSE-NEXT:    paddw %xmm7, %xmm1
 ; SSE-NEXT:    retq
 ;
 ; AVX-LABEL: reassociate_umax_v16i16:
 ; AVX:       # %bb.0:
 ; AVX-NEXT:    vpaddw %ymm1, %ymm0, %ymm0
-; AVX-NEXT:    vpmaxuw %ymm3, %ymm2, %ymm1
-; AVX-NEXT:    vpmaxuw %ymm1, %ymm0, %ymm0
+; AVX-NEXT:    vpmaxuw %ymm2, %ymm3, %ymm1
+; AVX-NEXT:    vpmaxuw %ymm0, %ymm1, %ymm0
 ; AVX-NEXT:    retq
 
   %t0 = add <16 x i16> %x0, %x1
   %t1 = icmp ugt <16 x i16> %x2, %t0
   %t2 = select <16 x i1> %t1, <16 x i16> %x2, <16 x i16> %t0
   %t3 = icmp ugt <16 x i16> %x3, %t2
   %t4 = select <16 x i1> %t3, <16 x i16> %x3, <16 x i16> %t2
   ret <16 x i16> %t4

 ; SSE-NEXT:    pand %xmm1, %xmm7
 ; SSE-NEXT:    pandn %xmm2, %xmm1
 ; SSE-NEXT:    por %xmm7, %xmm1
 ; SSE-NEXT:    retq
 ;
 ; AVX-LABEL: reassociate_umax_v8i32:
 ; AVX:       # %bb.0:
 ; AVX-NEXT:    vpaddd %ymm1, %ymm0, %ymm0
-; AVX-NEXT:    vpmaxud %ymm3, %ymm2, %ymm1
-; AVX-NEXT:    vpmaxud %ymm1, %ymm0, %ymm0
+; AVX-NEXT:    vpmaxud %ymm2, %ymm3, %ymm1
+; AVX-NEXT:    vpmaxud %ymm0, %ymm1, %ymm0
 ; AVX-NEXT:    retq
 
   %t0 = add <8 x i32> %x0, %x1
   %t1 = icmp ugt <8 x i32> %x2, %t0
   %t2 = select <8 x i1> %t1, <8 x i32> %x2, <8 x i32> %t0
   %t3 = icmp ugt <8 x i32> %x3, %t2
   %t4 = select <8 x i1> %t3, <8 x i32> %x3, <8 x i32> %t2
   ret <8 x i32> %t4

 ; AVX2-NEXT:    vpxor %ymm4, %ymm3, %ymm2
 ; AVX2-NEXT:    vpcmpgtq %ymm1, %ymm2, %ymm1
 ; AVX2-NEXT:    vblendvpd %ymm1, %ymm3, %ymm0, %ymm0
 ; AVX2-NEXT:    retq
 ;
 ; AVX512-LABEL: reassociate_umax_v4i64:
 ; AVX512:       # %bb.0:
 ; AVX512-NEXT:    vpaddq %ymm1, %ymm0, %ymm0
-; AVX512-NEXT:    vpmaxuq %ymm3, %ymm2, %ymm1
-; AVX512-NEXT:    vpmaxuq %ymm1, %ymm0, %ymm0
+; AVX512-NEXT:    vpmaxuq %ymm2, %ymm3, %ymm1
+; AVX512-NEXT:    vpmaxuq %ymm0, %ymm1, %ymm0
 ; AVX512-NEXT:    retq
 
   %t0 = add <4 x i64> %x0, %x1
   %t1 = icmp ugt <4 x i64> %x2, %t0
   %t2 = select <4 x i1> %t1, <4 x i64> %x2, <4 x i64> %t0
   %t3 = icmp ugt <4 x i64> %x3, %t2
   %t4 = select <4 x i1> %t3, <4 x i64> %x3, <4 x i64> %t2
   ret <4 x i64> %t4

 ; SSE-NEXT:    pand %xmm1, %xmm7
 ; SSE-NEXT:    pandn %xmm2, %xmm1
 ; SSE-NEXT:    por %xmm7, %xmm1
 ; SSE-NEXT:    retq
 ;
 ; AVX-LABEL: reassociate_smax_v32i8:
 ; AVX:       # %bb.0:
 ; AVX-NEXT:    vpaddb %ymm1, %ymm0, %ymm0
-; AVX-NEXT:    vpmaxsb %ymm3, %ymm2, %ymm1
-; AVX-NEXT:    vpmaxsb %ymm1, %ymm0, %ymm0
+; AVX-NEXT:    vpmaxsb %ymm2, %ymm3, %ymm1
+; AVX-NEXT:    vpmaxsb %ymm0, %ymm1, %ymm0
 ; AVX-NEXT:    retq
 
   %t0 = add <32 x i8> %x0, %x1
   %t1 = icmp sgt <32 x i8> %x2, %t0
   %t2 = select <32 x i1> %t1, <32 x i8> %x2, <32 x i8> %t0
   %t3 = icmp sgt <32 x i8> %x3, %t2
   %t4 = select <32 x i1> %t3, <32 x i8> %x3, <32 x i8> %t2
   ret <32 x i8> %t4
 }
 
 define <16 x i16> @reassociate_smax_v16i16(<16 x i16> %x0, <16 x i16> %x1, <16 x i16> %x2, <16 x i16> %x3) {
 ; SSE-LABEL: reassociate_smax_v16i16:
 ; SSE:       # %bb.0:
 ; SSE-NEXT:    paddw %xmm2, %xmm0
 ; SSE-NEXT:    paddw %xmm3, %xmm1
 ; SSE-NEXT:    pmaxsw %xmm6, %xmm4
 ; SSE-NEXT:    pmaxsw %xmm4, %xmm0
 ; SSE-NEXT:    pmaxsw %xmm7, %xmm5
 ; SSE-NEXT:    pmaxsw %xmm5, %xmm1
 ; SSE-NEXT:    retq
 ;
 ; AVX-LABEL: reassociate_smax_v16i16:
 ; AVX:       # %bb.0:
 ; AVX-NEXT:    vpaddw %ymm1, %ymm0, %ymm0
-; AVX-NEXT:    vpmaxsw %ymm3, %ymm2, %ymm1
-; AVX-NEXT:    vpmaxsw %ymm1, %ymm0, %ymm0
+; AVX-NEXT:    vpmaxsw %ymm2, %ymm3, %ymm1
+; AVX-NEXT:    vpmaxsw %ymm0, %ymm1, %ymm0
 ; AVX-NEXT:    retq
 
   %t0 = add <16 x i16> %x0, %x1
   %t1 = icmp sgt <16 x i16> %x2, %t0
   %t2 = select <16 x i1> %t1, <16 x i16> %x2, <16 x i16> %t0
   %t3 = icmp sgt <16 x i16> %x3, %t2
   %t4 = select <16 x i1> %t3, <16 x i16> %x3, <16 x i16> %t2
   ret <16 x i16> %t4

 ; SSE-NEXT:    pand %xmm1, %xmm7
 ; SSE-NEXT:    pandn %xmm2, %xmm1
 ; SSE-NEXT:    por %xmm7, %xmm1
 ; SSE-NEXT:    retq
 ;
 ; AVX-LABEL: reassociate_smax_v8i32:
 ; AVX:       # %bb.0:
 ; AVX-NEXT:    vpaddd %ymm1, %ymm0, %ymm0
-; AVX-NEXT:    vpmaxsd %ymm3, %ymm2, %ymm1
-; AVX-NEXT:    vpmaxsd %ymm1, %ymm0, %ymm0
+; AVX-NEXT:    vpmaxsd %ymm2, %ymm3, %ymm1
+; AVX-NEXT:    vpmaxsd %ymm0, %ymm1, %ymm0
 ; AVX-NEXT:    retq
 
   %t0 = add <8 x i32> %x0, %x1
   %t1 = icmp sgt <8 x i32> %x2, %t0
   %t2 = select <8 x i1> %t1, <8 x i32> %x2, <8 x i32> %t0
   %t3 = icmp sgt <8 x i32> %x3, %t2
   %t4 = select <8 x i1> %t3, <8 x i32> %x3, <8 x i32> %t2
   ret <8 x i32> %t4

 ; AVX2-NEXT:    vblendvpd %ymm1, %ymm2, %ymm0, %ymm0
 ; AVX2-NEXT:    vpcmpgtq %ymm0, %ymm3, %ymm1
 ; AVX2-NEXT:    vblendvpd %ymm1, %ymm3, %ymm0, %ymm0
 ; AVX2-NEXT:    retq
 ;
 ; AVX512-LABEL: reassociate_smax_v4i64:
 ; AVX512:       # %bb.0:
 ; AVX512-NEXT:    vpaddq %ymm1, %ymm0, %ymm0
-; AVX512-NEXT:    vpmaxsq %ymm3, %ymm2, %ymm1
-; AVX512-NEXT:    vpmaxsq %ymm1, %ymm0, %ymm0
+; AVX512-NEXT:    vpmaxsq %ymm2, %ymm3, %ymm1
+; AVX512-NEXT:    vpmaxsq %ymm0, %ymm1, %ymm0
 ; AVX512-NEXT:    retq
 
   %t0 = add <4 x i64> %x0, %x1
   %t1 = icmp sgt <4 x i64> %x2, %t0
   %t2 = select <4 x i1> %t1, <4 x i64> %x2, <4 x i64> %t0
   %t3 = icmp sgt <4 x i64> %x3, %t2
   %t4 = select <4 x i1> %t3, <4 x i64> %x3, <4 x i64> %t2
   ret <4 x i64> %t4
 }
 
 define <32 x i8> @reassociate_umin_v32i8(<32 x i8> %x0, <32 x i8> %x1, <32 x i8> %x2, <32 x i8> %x3) {
 ; SSE-LABEL: reassociate_umin_v32i8:
 ; SSE:       # %bb.0:
 ; SSE-NEXT:    paddb %xmm2, %xmm0
 ; SSE-NEXT:    paddb %xmm3, %xmm1
 ; SSE-NEXT:    pminub %xmm6, %xmm4
 ; SSE-NEXT:    pminub %xmm4, %xmm0
 ; SSE-NEXT:    pminub %xmm7, %xmm5
 ; SSE-NEXT:    pminub %xmm5, %xmm1
 ; SSE-NEXT:    retq
 ;
 ; AVX-LABEL: reassociate_umin_v32i8:
 ; AVX:       # %bb.0:
 ; AVX-NEXT:    vpaddb %ymm1, %ymm0, %ymm0
-; AVX-NEXT:    vpminub %ymm3, %ymm2, %ymm1
-; AVX-NEXT:    vpminub %ymm1, %ymm0, %ymm0
+; AVX-NEXT:    vpminub %ymm2, %ymm3, %ymm1
+; AVX-NEXT:    vpminub %ymm0, %ymm1, %ymm0
 ; AVX-NEXT:    retq
 
   %t0 = add <32 x i8> %x0, %x1
   %t1 = icmp ult <32 x i8> %x2, %t0
   %t2 = select <32 x i1> %t1, <32 x i8> %x2, <32 x i8> %t0
   %t3 = icmp ult <32 x i8> %x3, %t2
   %t4 = select <32 x i1> %t3, <32 x i8> %x3, <32 x i8> %t2
   ret <32 x i8> %t4

 ; SSE-NEXT:    psubw %xmm0, %xmm7
 ; SSE-NEXT:    movdqa %xmm6, %xmm0
 ; SSE-NEXT:    movdqa %xmm7, %xmm1
 ; SSE-NEXT:    retq
 ;
 ; AVX-LABEL: reassociate_umin_v16i16:
 ; AVX:       # %bb.0:
 ; AVX-NEXT:    vpaddw %ymm1, %ymm0, %ymm0
-; AVX-NEXT:    vpminuw %ymm3, %ymm2, %ymm1
-; AVX-NEXT:    vpminuw %ymm1, %ymm0, %ymm0
+; AVX-NEXT:    vpminuw %ymm2, %ymm3, %ymm1
+; AVX-NEXT:    vpminuw %ymm0, %ymm1, %ymm0
 ; AVX-NEXT:    retq
 
   %t0 = add <16 x i16> %x0, %x1
   %t1 = icmp ult <16 x i16> %x2, %t0
   %t2 = select <16 x i1> %t1, <16 x i16> %x2, <16 x i16> %t0
   %t3 = icmp ult <16 x i16> %x3, %t2
   %t4 = select <16 x i1> %t3, <16 x i16> %x3, <16 x i16> %t2
   ret <16 x i16> %t4

 ; SSE-NEXT:    pand %xmm1, %xmm7
 ; SSE-NEXT:    pandn %xmm2, %xmm1
 ; SSE-NEXT:    por %xmm7, %xmm1
 ; SSE-NEXT:    retq
 ;
 ; AVX-LABEL: reassociate_umin_v8i32:
 ; AVX:       # %bb.0:
 ; AVX-NEXT:    vpaddd %ymm1, %ymm0, %ymm0
-; AVX-NEXT:    vpminud %ymm3, %ymm2, %ymm1
-; AVX-NEXT:    vpminud %ymm1, %ymm0, %ymm0
+; AVX-NEXT:    vpminud %ymm2, %ymm3, %ymm1
+; AVX-NEXT:    vpminud %ymm0, %ymm1, %ymm0
 ; AVX-NEXT:    retq
 
   %t0 = add <8 x i32> %x0, %x1
   %t1 = icmp ult <8 x i32> %x2, %t0
   %t2 = select <8 x i1> %t1, <8 x i32> %x2, <8 x i32> %t0
   %t3 = icmp ult <8 x i32> %x3, %t2
   %t4 = select <8 x i1> %t3, <8 x i32> %x3, <8 x i32> %t2
   ret <8 x i32> %t4

 ; AVX2-NEXT:    vpxor %ymm4, %ymm3, %ymm2
 ; AVX2-NEXT:    vpcmpgtq %ymm2, %ymm1, %ymm1
 ; AVX2-NEXT:    vblendvpd %ymm1, %ymm3, %ymm0, %ymm0
 ; AVX2-NEXT:    retq
 ;
 ; AVX512-LABEL: reassociate_umin_v4i64:
 ; AVX512:       # %bb.0:
 ; AVX512-NEXT:    vpaddq %ymm1, %ymm0, %ymm0
-; AVX512-NEXT:    vpminuq %ymm3, %ymm2, %ymm1
-; AVX512-NEXT:    vpminuq %ymm1, %ymm0, %ymm0
+; AVX512-NEXT:    vpminuq %ymm2, %ymm3, %ymm1
+; AVX512-NEXT:    vpminuq %ymm0, %ymm1, %ymm0
 ; AVX512-NEXT:    retq
 
   %t0 = add <4 x i64> %x0, %x1
   %t1 = icmp ult <4 x i64> %x2, %t0
   %t2 = select <4 x i1> %t1, <4 x i64> %x2, <4 x i64> %t0
   %t3 = icmp ult <4 x i64> %x3, %t2
   %t4 = select <4 x i1> %t3, <4 x i64> %x3, <4 x i64> %t2
   ret <4 x i64> %t4

 ; SSE-NEXT:    pand %xmm1, %xmm7
 ; SSE-NEXT:    pandn %xmm2, %xmm1
 ; SSE-NEXT:    por %xmm7, %xmm1
 ; SSE-NEXT:    retq
 ;
 ; AVX-LABEL: reassociate_smin_v32i8:
 ; AVX:       # %bb.0:
 ; AVX-NEXT:    vpaddb %ymm1, %ymm0, %ymm0
-; AVX-NEXT:    vpminsb %ymm3, %ymm2, %ymm1
-; AVX-NEXT:    vpminsb %ymm1, %ymm0, %ymm0
+; AVX-NEXT:    vpminsb %ymm2, %ymm3, %ymm1
+; AVX-NEXT:    vpminsb %ymm0, %ymm1, %ymm0
 ; AVX-NEXT:    retq
 
   %t0 = add <32 x i8> %x0, %x1
   %t1 = icmp slt <32 x i8> %x2, %t0
   %t2 = select <32 x i1> %t1, <32 x i8> %x2, <32 x i8> %t0
   %t3 = icmp slt <32 x i8> %x3, %t2
   %t4 = select <32 x i1> %t3, <32 x i8> %x3, <32 x i8> %t2
   ret <32 x i8> %t4
 }
 
 define <16 x i16> @reassociate_smin_v16i16(<16 x i16> %x0, <16 x i16> %x1, <16 x i16> %x2, <16 x i16> %x3) {
 ; SSE-LABEL: reassociate_smin_v16i16:
 ; SSE:       # %bb.0:
 ; SSE-NEXT:    paddw %xmm2, %xmm0
 ; SSE-NEXT:    paddw %xmm3, %xmm1
 ; SSE-NEXT:    pminsw %xmm6, %xmm4
 ; SSE-NEXT:    pminsw %xmm4, %xmm0
 ; SSE-NEXT:    pminsw %xmm7, %xmm5
 ; SSE-NEXT:    pminsw %xmm5, %xmm1
 ; SSE-NEXT:    retq
 ;
 ; AVX-LABEL: reassociate_smin_v16i16:
 ; AVX:       # %bb.0:
 ; AVX-NEXT:    vpaddw %ymm1, %ymm0, %ymm0
-; AVX-NEXT:    vpminsw %ymm3, %ymm2, %ymm1
-; AVX-NEXT:    vpminsw %ymm1, %ymm0, %ymm0
+; AVX-NEXT:    vpminsw %ymm2, %ymm3, %ymm1
+; AVX-NEXT:    vpminsw %ymm0, %ymm1, %ymm0
 ; AVX-NEXT:    retq
 
   %t0 = add <16 x i16> %x0, %x1
   %t1 = icmp slt <16 x i16> %x2, %t0
   %t2 = select <16 x i1> %t1, <16 x i16> %x2, <16 x i16> %t0
   %t3 = icmp slt <16 x i16> %x3, %t2
   %t4 = select <16 x i1> %t3, <16 x i16> %x3, <16 x i16> %t2
   ret <16 x i16> %t4

 ; SSE-NEXT:    pand %xmm1, %xmm7
 ; SSE-NEXT:    pandn %xmm2, %xmm1
 ; SSE-NEXT:    por %xmm7, %xmm1
 ; SSE-NEXT:    retq
 ;
 ; AVX-LABEL: reassociate_smin_v8i32:
 ; AVX:       # %bb.0:
 ; AVX-NEXT:    vpaddd %ymm1, %ymm0, %ymm0
-; AVX-NEXT:    vpminsd %ymm3, %ymm2, %ymm1
-; AVX-NEXT:    vpminsd %ymm1, %ymm0, %ymm0
+; AVX-NEXT:    vpminsd %ymm2, %ymm3, %ymm1
+; AVX-NEXT:    vpminsd %ymm0, %ymm1, %ymm0
 ; AVX-NEXT:    retq
 
   %t0 = add <8 x i32> %x0, %x1
   %t1 = icmp slt <8 x i32> %x2, %t0
   %t2 = select <8 x i1> %t1, <8 x i32> %x2, <8 x i32> %t0
   %t3 = icmp slt <8 x i32> %x3, %t2
   %t4 = select <8 x i1> %t3, <8 x i32> %x3, <8 x i32> %t2
   ret <8 x i32> %t4

 ; AVX2-NEXT:    vblendvpd %ymm1, %ymm2, %ymm0, %ymm0
 ; AVX2-NEXT:    vpcmpgtq %ymm3, %ymm0, %ymm1
 ; AVX2-NEXT:    vblendvpd %ymm1, %ymm3, %ymm0, %ymm0
 ; AVX2-NEXT:    retq
 ;
 ; AVX512-LABEL: reassociate_smin_v4i64:
 ; AVX512:       # %bb.0:
 ; AVX512-NEXT:    vpaddq %ymm1, %ymm0, %ymm0
-; AVX512-NEXT:    vpminsq %ymm3, %ymm2, %ymm1
-; AVX512-NEXT:    vpminsq %ymm1, %ymm0, %ymm0
+; AVX512-NEXT:    vpminsq %ymm2, %ymm3, %ymm1
+; AVX512-NEXT:    vpminsq %ymm0, %ymm1, %ymm0
 ; AVX512-NEXT:    retq
 
   %t0 = add <4 x i64> %x0, %x1
   %t1 = icmp slt <4 x i64> %x2, %t0
   %t2 = select <4 x i1> %t1, <4 x i64> %x2, <4 x i64> %t0
   %t3 = icmp slt <4 x i64> %x3, %t2
   %t4 = select <4 x i1> %t3, <4 x i64> %x3, <4 x i64> %t2
   ret <4 x i64> %t4

 ; SSE-NEXT:    pmaxub {{[0-9]+}}(%rsp), %xmm2
 ; SSE-NEXT:    pmaxub {{[0-9]+}}(%rsp), %xmm3
 ; SSE-NEXT:    retq
 ;
 ; AVX2-LABEL: reassociate_umax_v64i8:
 ; AVX2:       # %bb.0:
 ; AVX2-NEXT:    vpaddb %ymm2, %ymm0, %ymm0
 ; AVX2-NEXT:    vpaddb %ymm3, %ymm1, %ymm1
-; AVX2-NEXT:    vpmaxub %ymm6, %ymm4, %ymm2
-; AVX2-NEXT:    vpmaxub %ymm2, %ymm0, %ymm0
-; AVX2-NEXT:    vpmaxub %ymm7, %ymm5, %ymm2
-; AVX2-NEXT:    vpmaxub %ymm2, %ymm1, %ymm1
+; AVX2-NEXT:    vpmaxub %ymm4, %ymm6, %ymm2
+; AVX2-NEXT:    vpmaxub %ymm0, %ymm2, %ymm0
+; AVX2-NEXT:    vpmaxub %ymm5, %ymm7, %ymm2
+; AVX2-NEXT:    vpmaxub %ymm1, %ymm2, %ymm1
 ; AVX2-NEXT:    retq
 ;
 ; AVX512-LABEL: reassociate_umax_v64i8:
 ; AVX512:       # %bb.0:
 ; AVX512-NEXT:    vpaddb %zmm1, %zmm0, %zmm0
-; AVX512-NEXT:    vpmaxub %zmm3, %zmm2, %zmm1
-; AVX512-NEXT:    vpmaxub %zmm1, %zmm0, %zmm0
+; AVX512-NEXT:    vpmaxub %zmm2, %zmm3, %zmm1
+; AVX512-NEXT:    vpmaxub %zmm0, %zmm1, %zmm0
 ; AVX512-NEXT:    retq
 
   %t0 = add <64 x i8> %x0, %x1
   %t1 = icmp ugt <64 x i8> %x2, %t0
   %t2 = select <64 x i1> %t1, <64 x i8> %x2, <64 x i8> %t0
   %t3 = icmp ugt <64 x i8> %x3, %t2
   %t4 = select <64 x i1> %t3, <64 x i8> %x3, <64 x i8> %t2
   ret <64 x i8> %t4

 ; SSE-NEXT:    psubusw %xmm8, %xmm3
 ; SSE-NEXT:    paddw %xmm8, %xmm3
 ; SSE-NEXT:    retq
 ;
 ; AVX2-LABEL: reassociate_umax_v32i16:
 ; AVX2:       # %bb.0:
 ; AVX2-NEXT:    vpaddw %ymm2, %ymm0, %ymm0
 ; AVX2-NEXT:    vpaddw %ymm3, %ymm1, %ymm1
-; AVX2-NEXT:    vpmaxuw %ymm6, %ymm4, %ymm2
-; AVX2-NEXT:    vpmaxuw %ymm2, %ymm0, %ymm0
-; AVX2-NEXT:    vpmaxuw %ymm7, %ymm5, %ymm2
-; AVX2-NEXT:    vpmaxuw %ymm2, %ymm1, %ymm1
+; AVX2-NEXT:    vpmaxuw %ymm4, %ymm6, %ymm2
+; AVX2-NEXT:    vpmaxuw %ymm0, %ymm2, %ymm0
+; AVX2-NEXT:    vpmaxuw %ymm5, %ymm7, %ymm2
+; AVX2-NEXT:    vpmaxuw %ymm1, %ymm2, %ymm1
 ; AVX2-NEXT:    retq
 ;
 ; AVX512-LABEL: reassociate_umax_v32i16:
 ; AVX512:       # %bb.0:
 ; AVX512-NEXT:    vpaddw %zmm1, %zmm0, %zmm0
-; AVX512-NEXT:    vpmaxuw %zmm3, %zmm2, %zmm1
-; AVX512-NEXT:    vpmaxuw %zmm1, %zmm0, %zmm0
+; AVX512-NEXT:    vpmaxuw %zmm2, %zmm3, %zmm1
+; AVX512-NEXT:    vpmaxuw %zmm0, %zmm1, %zmm0
 ; AVX512-NEXT:    retq
 
   %t0 = add <32 x i16> %x0, %x1
   %t1 = icmp ugt <32 x i16> %x2, %t0
   %t2 = select <32 x i1> %t1, <32 x i16> %x2, <32 x i16> %t0
   %t3 = icmp ugt <32 x i16> %x3, %t2
   %t4 = select <32 x i1> %t3, <32 x i16> %x3, <32 x i16> %t2
   ret <32 x i16> %t4

 ; SSE-NEXT:    pandn %xmm6, %xmm3
 ; SSE-NEXT:    por %xmm5, %xmm3
 ; SSE-NEXT:    retq
 ;
 ; AVX2-LABEL: reassociate_umax_v16i32:
 ; AVX2:       # %bb.0:
 ; AVX2-NEXT:    vpaddd %ymm2, %ymm0, %ymm0
 ; AVX2-NEXT:    vpaddd %ymm3, %ymm1, %ymm1
-; AVX2-NEXT:    vpmaxud %ymm6, %ymm4, %ymm2
-; AVX2-NEXT:    vpmaxud %ymm2, %ymm0, %ymm0
-; AVX2-NEXT:    vpmaxud %ymm7, %ymm5, %ymm2
-; AVX2-NEXT:    vpmaxud %ymm2, %ymm1, %ymm1
+; AVX2-NEXT:    vpmaxud %ymm4, %ymm6, %ymm2
+; AVX2-NEXT:    vpmaxud %ymm0, %ymm2, %ymm0
+; AVX2-NEXT:    vpmaxud %ymm5, %ymm7, %ymm2
+; AVX2-NEXT:    vpmaxud %ymm1, %ymm2, %ymm1
 ; AVX2-NEXT:    retq
 ;
 ; AVX512-LABEL: reassociate_umax_v16i32:
 ; AVX512:       # %bb.0:
 ; AVX512-NEXT:    vpaddd %zmm1, %zmm0, %zmm0
-; AVX512-NEXT:    vpmaxud %zmm3, %zmm2, %zmm1
-; AVX512-NEXT:    vpmaxud %zmm1, %zmm0, %zmm0
+; AVX512-NEXT:    vpmaxud %zmm2, %zmm3, %zmm1
+; AVX512-NEXT:    vpmaxud %zmm0, %zmm1, %zmm0
 ; AVX512-NEXT:    retq
 
   %t0 = add <16 x i32> %x0, %x1
   %t1 = icmp ugt <16 x i32> %x2, %t0
   %t2 = select <16 x i1> %t1, <16 x i32> %x2, <16 x i32> %t0
   %t3 = icmp ugt <16 x i32> %x3, %t2
   %t4 = select <16 x i1> %t3, <16 x i32> %x3, <16 x i32> %t2
   ret <16 x i32> %t4

 ; AVX2-NEXT:    vpxor %ymm2, %ymm7, %ymm2
 ; AVX2-NEXT:    vpcmpgtq %ymm3, %ymm2, %ymm2
 ; AVX2-NEXT:    vblendvpd %ymm2, %ymm7, %ymm1, %ymm1
 ; AVX2-NEXT:    retq
 ;
 ; AVX512-LABEL: reassociate_umax_v8i64:
 ; AVX512:       # %bb.0:
 ; AVX512-NEXT:    vpaddq %zmm1, %zmm0, %zmm0
-; AVX512-NEXT:    vpmaxuq %zmm3, %zmm2, %zmm1
-; AVX512-NEXT:    vpmaxuq %zmm1, %zmm0, %zmm0
+; AVX512-NEXT:    vpmaxuq %zmm2, %zmm3, %zmm1
+; AVX512-NEXT:    vpmaxuq %zmm0, %zmm1, %zmm0
 ; AVX512-NEXT:    retq
 
   %t0 = add <8 x i64> %x0, %x1
   %t1 = icmp ugt <8 x i64> %x2, %t0
   %t2 = select <8 x i1> %t1, <8 x i64> %x2, <8 x i64> %t0
   %t3 = icmp ugt <8 x i64> %x3, %t2
   %t4 = select <8 x i1> %t3, <8 x i64> %x3, <8 x i64> %t2
   ret <8 x i64> %t4

 ; SSE-NEXT:    pandn %xmm4, %xmm3
 ; SSE-NEXT:    por %xmm8, %xmm3
 ; SSE-NEXT:    retq
 ;
 ; AVX2-LABEL: reassociate_smax_v64i8:
 ; AVX2:       # %bb.0:
 ; AVX2-NEXT:    vpaddb %ymm2, %ymm0, %ymm0
 ; AVX2-NEXT:    vpaddb %ymm3, %ymm1, %ymm1
-; AVX2-NEXT:    vpmaxsb %ymm6, %ymm4, %ymm2
-; AVX2-NEXT:    vpmaxsb %ymm2, %ymm0, %ymm0
-; AVX2-NEXT:    vpmaxsb %ymm7, %ymm5, %ymm2
-; AVX2-NEXT:    vpmaxsb %ymm2, %ymm1, %ymm1
+; AVX2-NEXT:    vpmaxsb %ymm4, %ymm6, %ymm2
+; AVX2-NEXT:    vpmaxsb %ymm0, %ymm2, %ymm0
+; AVX2-NEXT:    vpmaxsb %ymm5, %ymm7, %ymm2
+; AVX2-NEXT:    vpmaxsb %ymm1, %ymm2, %ymm1
 ; AVX2-NEXT:    retq
 ;
 ; AVX512-LABEL: reassociate_smax_v64i8:
 ; AVX512:       # %bb.0:
 ; AVX512-NEXT:    vpaddb %zmm1, %zmm0, %zmm0
-; AVX512-NEXT:    vpmaxsb %zmm3, %zmm2, %zmm1
-; AVX512-NEXT:    vpmaxsb %zmm1, %zmm0, %zmm0
+; AVX512-NEXT:    vpmaxsb %zmm2, %zmm3, %zmm1
+; AVX512-NEXT:    vpmaxsb %zmm0, %zmm1, %zmm0
 ; AVX512-NEXT:    retq
 
   %t0 = add <64 x i8> %x0, %x1
   %t1 = icmp sgt <64 x i8> %x2, %t0
   %t2 = select <64 x i1> %t1, <64 x i8> %x2, <64 x i8> %t0
   %t3 = icmp sgt <64 x i8> %x3, %t2
   %t4 = select <64 x i1> %t3, <64 x i8> %x3, <64 x i8> %t2
   ret <64 x i8> %t4

 ; SSE-NEXT:    pmaxsw {{[0-9]+}}(%rsp), %xmm2
 ; SSE-NEXT:    pmaxsw {{[0-9]+}}(%rsp), %xmm3
 ; SSE-NEXT:    retq
 ;
 ; AVX2-LABEL: reassociate_smax_v32i16:
 ; AVX2:       # %bb.0:
 ; AVX2-NEXT:    vpaddw %ymm2, %ymm0, %ymm0
 ; AVX2-NEXT:    vpaddw %ymm3, %ymm1, %ymm1
-; AVX2-NEXT:    vpmaxsw %ymm6, %ymm4, %ymm2
-; AVX2-NEXT:    vpmaxsw %ymm2, %ymm0, %ymm0
-; AVX2-NEXT:    vpmaxsw %ymm7, %ymm5, %ymm2
-; AVX2-NEXT:    vpmaxsw %ymm2, %ymm1, %ymm1
+; AVX2-NEXT:    vpmaxsw %ymm4, %ymm6, %ymm2
+; AVX2-NEXT:    vpmaxsw %ymm0, %ymm2, %ymm0
+; AVX2-NEXT:    vpmaxsw %ymm5, %ymm7, %ymm2
+; AVX2-NEXT:    vpmaxsw %ymm1, %ymm2, %ymm1
 ; AVX2-NEXT:    retq
 ;
 ; AVX512-LABEL: reassociate_smax_v32i16:
 ; AVX512:       # %bb.0:
 ; AVX512-NEXT:    vpaddw %zmm1, %zmm0, %zmm0
-; AVX512-NEXT:    vpmaxsw %zmm3, %zmm2, %zmm1
-; AVX512-NEXT:    vpmaxsw %zmm1, %zmm0, %zmm0
+; AVX512-NEXT:    vpmaxsw %zmm2, %zmm3, %zmm1
+; AVX512-NEXT:    vpmaxsw %zmm0, %zmm1, %zmm0
 ; AVX512-NEXT:    retq
 
   %t0 = add <32 x i16> %x0, %x1
   %t1 = icmp sgt <32 x i16> %x2, %t0
   %t2 = select <32 x i1> %t1, <32 x i16> %x2, <32 x i16> %t0
   %t3 = icmp sgt <32 x i16> %x3, %t2
   %t4 = select <32 x i1> %t3, <32 x i16> %x3, <32 x i16> %t2
   ret <32 x i16> %t4

 ; SSE-NEXT:    pandn %xmm4, %xmm3
 ; SSE-NEXT:    por %xmm8, %xmm3
 ; SSE-NEXT:    retq
 ;
 ; AVX2-LABEL: reassociate_smax_v16i32:
 ; AVX2:       # %bb.0:
 ; AVX2-NEXT:    vpaddd %ymm2, %ymm0, %ymm0
 ; AVX2-NEXT:    vpaddd %ymm3, %ymm1, %ymm1
-; AVX2-NEXT:    vpmaxsd %ymm6, %ymm4, %ymm2
-; AVX2-NEXT:    vpmaxsd %ymm2, %ymm0, %ymm0
-; AVX2-NEXT:    vpmaxsd %ymm7, %ymm5, %ymm2
-; AVX2-NEXT:    vpmaxsd %ymm2, %ymm1, %ymm1
+; AVX2-NEXT:    vpmaxsd %ymm4, %ymm6, %ymm2
+; AVX2-NEXT:    vpmaxsd %ymm0, %ymm2, %ymm0
+; AVX2-NEXT:    vpmaxsd %ymm5, %ymm7, %ymm2
+; AVX2-NEXT:    vpmaxsd %ymm1, %ymm2, %ymm1
 ; AVX2-NEXT:    retq
 ;
 ; AVX512-LABEL: reassociate_smax_v16i32:
 ; AVX512:       # %bb.0:
 ; AVX512-NEXT:    vpaddd %zmm1, %zmm0, %zmm0
-; AVX512-NEXT:    vpmaxsd %zmm3, %zmm2, %zmm1
-; AVX512-NEXT:    vpmaxsd %zmm1, %zmm0, %zmm0
+; AVX512-NEXT:    vpmaxsd %zmm2, %zmm3, %zmm1
+; AVX512-NEXT:    vpmaxsd %zmm0, %zmm1, %zmm0
 ; AVX512-NEXT:    retq
 
   %t0 = add <16 x i32> %x0, %x1
   %t1 = icmp sgt <16 x i32> %x2, %t0
   %t2 = select <16 x i1> %t1, <16 x i32> %x2, <16 x i32> %t0
   %t3 = icmp sgt <16 x i32> %x3, %t2
   %t4 = select <16 x i1> %t3, <16 x i32> %x3, <16 x i32> %t2
   ret <16 x i32> %t4

 ; AVX2-NEXT:    vblendvpd %ymm2, %ymm6, %ymm0, %ymm0
 ; AVX2-NEXT:    vpcmpgtq %ymm1, %ymm7, %ymm2
 ; AVX2-NEXT:    vblendvpd %ymm2, %ymm7, %ymm1, %ymm1
 ; AVX2-NEXT:    retq
 ;
 ; AVX512-LABEL: reassociate_smax_v8i64:
 ; AVX512:       # %bb.0:
 ; AVX512-NEXT:    vpaddq %zmm1, %zmm0, %zmm0
-; AVX512-NEXT:    vpmaxsq %zmm3, %zmm2, %zmm1
-; AVX512-NEXT:    vpmaxsq %zmm1, %zmm0, %zmm0
+; AVX512-NEXT:    vpmaxsq %zmm2, %zmm3, %zmm1
+; AVX512-NEXT:    vpmaxsq %zmm0, %zmm1, %zmm0
 ; AVX512-NEXT:    retq
 
   %t0 = add <8 x i64> %x0, %x1
   %t1 = icmp sgt <8 x i64> %x2, %t0
   %t2 = select <8 x i1> %t1, <8 x i64> %x2, <8 x i64> %t0
   %t3 = icmp sgt <8 x i64> %x3, %t2
   %t4 = select <8 x i1> %t3, <8 x i64> %x3, <8 x i64> %t2
   ret <8 x i64> %t4

 ; SSE-NEXT:    pminub {{[0-9]+}}(%rsp), %xmm2
 ; SSE-NEXT:    pminub {{[0-9]+}}(%rsp), %xmm3
 ; SSE-NEXT:    retq
 ;
 ; AVX2-LABEL: reassociate_umin_v64i8:
 ; AVX2:       # %bb.0:
 ; AVX2-NEXT:    vpaddb %ymm2, %ymm0, %ymm0
 ; AVX2-NEXT:    vpaddb %ymm3, %ymm1, %ymm1
-; AVX2-NEXT:    vpminub %ymm6, %ymm4, %ymm2
-; AVX2-NEXT:    vpminub %ymm2, %ymm0, %ymm0
-; AVX2-NEXT:    vpminub %ymm7, %ymm5, %ymm2
-; AVX2-NEXT:    vpminub %ymm2, %ymm1, %ymm1
+; AVX2-NEXT:    vpminub %ymm4, %ymm6, %ymm2
+; AVX2-NEXT:    vpminub %ymm0, %ymm2, %ymm0
+; AVX2-NEXT:    vpminub %ymm5, %ymm7, %ymm2
+; AVX2-NEXT:    vpminub %ymm1, %ymm2, %ymm1
 ; AVX2-NEXT:    retq
 ;
 ; AVX512-LABEL: reassociate_umin_v64i8:
 ; AVX512:       # %bb.0:
 ; AVX512-NEXT:    vpaddb %zmm1, %zmm0, %zmm0
-; AVX512-NEXT:    vpminub %zmm3, %zmm2, %zmm1
-; AVX512-NEXT:    vpminub %zmm1, %zmm0, %zmm0
+; AVX512-NEXT:    vpminub %zmm2, %zmm3, %zmm1
+; AVX512-NEXT:    vpminub %zmm0, %zmm1, %zmm0
 ; AVX512-NEXT:    retq
 
   %t0 = add <64 x i8> %x0, %x1
   %t1 = icmp ult <64 x i8> %x2, %t0
   %t2 = select <64 x i1> %t1, <64 x i8> %x2, <64 x i8> %t0
   %t3 = icmp ult <64 x i8> %x3, %t2
   %t4 = select <64 x i1> %t3, <64 x i8> %x3, <64 x i8> %t2
   ret <64 x i8> %t4

 ; SSE-NEXT:    psubusw %xmm12, %xmm4
 ; SSE-NEXT:    psubw %xmm4, %xmm3
 ; SSE-NEXT:    retq
 ;
 ; AVX2-LABEL: reassociate_umin_v32i16:
 ; AVX2:       # %bb.0:
 ; AVX2-NEXT:    vpaddw %ymm2, %ymm0, %ymm0
 ; AVX2-NEXT:    vpaddw %ymm3, %ymm1, %ymm1
-; AVX2-NEXT:    vpminuw %ymm6, %ymm4, %ymm2
-; AVX2-NEXT:    vpminuw %ymm2, %ymm0, %ymm0
-; AVX2-NEXT:    vpminuw %ymm7, %ymm5, %ymm2
-; AVX2-NEXT:    vpminuw %ymm2, %ymm1, %ymm1
+; AVX2-NEXT:    vpminuw %ymm4, %ymm6, %ymm2
+; AVX2-NEXT:    vpminuw %ymm0, %ymm2, %ymm0
+; AVX2-NEXT:    vpminuw %ymm5, %ymm7, %ymm2
+; AVX2-NEXT:    vpminuw %ymm1, %ymm2, %ymm1
 ; AVX2-NEXT:    retq
 ;
 ; AVX512-LABEL: reassociate_umin_v32i16:
 ; AVX512:       # %bb.0:
 ; AVX512-NEXT:    vpaddw %zmm1, %zmm0, %zmm0
-; AVX512-NEXT:    vpminuw %zmm3, %zmm2, %zmm1
-; AVX512-NEXT:    vpminuw %zmm1, %zmm0, %zmm0
+; AVX512-NEXT:    vpminuw %zmm2, %zmm3, %zmm1
+; AVX512-NEXT:    vpminuw %zmm0, %zmm1, %zmm0
 ; AVX512-NEXT:    retq
 
   %t0 = add <32 x i16> %x0, %x1
   %t1 = icmp ult <32 x i16> %x2, %t0
   %t2 = select <32 x i1> %t1, <32 x i16> %x2, <32 x i16> %t0
   %t3 = icmp ult <32 x i16> %x3, %t2
   %t4 = select <32 x i1> %t3, <32 x i16> %x3, <32 x i16> %t2
   ret <32 x i16> %t4

 ; SSE-NEXT:    pandn %xmm4, %xmm3
 ; SSE-NEXT:    por %xmm8, %xmm3
 ; SSE-NEXT:    retq
 ;
 ; AVX2-LABEL: reassociate_umin_v16i32:
 ; AVX2:       # %bb.0:
 ; AVX2-NEXT:    vpaddd %ymm2, %ymm0, %ymm0
 ; AVX2-NEXT:    vpaddd %ymm3, %ymm1, %ymm1
-; AVX2-NEXT:    vpminud %ymm6, %ymm4, %ymm2
-; AVX2-NEXT:    vpminud %ymm2, %ymm0, %ymm0
-; AVX2-NEXT:    vpminud %ymm7, %ymm5, %ymm2
-; AVX2-NEXT:    vpminud %ymm2, %ymm1, %ymm1
+; AVX2-NEXT:    vpminud %ymm4, %ymm6, %ymm2
+; AVX2-NEXT:    vpminud %ymm0, %ymm2, %ymm0
+; AVX2-NEXT:    vpminud %ymm5, %ymm7, %ymm2
+; AVX2-NEXT:    vpminud %ymm1, %ymm2, %ymm1
 ; AVX2-NEXT:    retq
 ;
 ; AVX512-LABEL: reassociate_umin_v16i32:
 ; AVX512:       # %bb.0:
 ; AVX512-NEXT:    vpaddd %zmm1, %zmm0, %zmm0
-; AVX512-NEXT:    vpminud %zmm3, %zmm2, %zmm1
-; AVX512-NEXT:    vpminud %zmm1, %zmm0, %zmm0
+; AVX512-NEXT:    vpminud %zmm2, %zmm3, %zmm1
+; AVX512-NEXT:    vpminud %zmm0, %zmm1, %zmm0
 ; AVX512-NEXT:    retq
 
   %t0 = add <16 x i32> %x0, %x1
   %t1 = icmp ult <16 x i32> %x2, %t0
   %t2 = select <16 x i1> %t1, <16 x i32> %x2, <16 x i32> %t0
   %t3 = icmp ult <16 x i32> %x3, %t2
   %t4 = select <16 x i1> %t3, <16 x i32> %x3, <16 x i32> %t2
   ret <16 x i32> %t4

 ; AVX2-NEXT:    vpxor %ymm2, %ymm7, %ymm2
 ; AVX2-NEXT:    vpcmpgtq %ymm2, %ymm3, %ymm2
 ; AVX2-NEXT:    vblendvpd %ymm2, %ymm7, %ymm1, %ymm1
 ; AVX2-NEXT:    retq
 ;
 ; AVX512-LABEL: reassociate_umin_v8i64:
 ; AVX512:       # %bb.0:
 ; AVX512-NEXT:    vpaddq %zmm1, %zmm0, %zmm0
-; AVX512-NEXT:    vpminuq %zmm3, %zmm2, %zmm1
-; AVX512-NEXT:    vpminuq %zmm1, %zmm0, %zmm0
+; AVX512-NEXT:    vpminuq %zmm2, %zmm3, %zmm1
+; AVX512-NEXT:    vpminuq %zmm0, %zmm1, %zmm0
 ; AVX512-NEXT:    retq
 
   %t0 = add <8 x i64> %x0, %x1
   %t1 = icmp ult <8 x i64> %x2, %t0
   %t2 = select <8 x i1> %t1, <8 x i64> %x2, <8 x i64> %t0
   %t3 = icmp ult <8 x i64> %x3, %t2
   %t4 = select <8 x i1> %t3, <8 x i64> %x3, <8 x i64> %t2
   ret <8 x i64> %t4

 ; SSE-NEXT:    pandn %xmm4, %xmm3
 ; SSE-NEXT:    por %xmm8, %xmm3
 ; SSE-NEXT:    retq
 ;
 ; AVX2-LABEL: reassociate_smin_v64i8:
 ; AVX2:       # %bb.0:
 ; AVX2-NEXT:    vpaddb %ymm2, %ymm0, %ymm0
 ; AVX2-NEXT:    vpaddb %ymm3, %ymm1, %ymm1
-; AVX2-NEXT:    vpminsb %ymm6, %ymm4, %ymm2
-; AVX2-NEXT:    vpminsb %ymm2, %ymm0, %ymm0
-; AVX2-NEXT:    vpminsb %ymm7, %ymm5, %ymm2
-; AVX2-NEXT:    vpminsb %ymm2, %ymm1, %ymm1
+; AVX2-NEXT:    vpminsb %ymm4, %ymm6, %ymm2
+; AVX2-NEXT:    vpminsb %ymm0, %ymm2, %ymm0
+; AVX2-NEXT:    vpminsb %ymm5, %ymm7, %ymm2
+; AVX2-NEXT:    vpminsb %ymm1, %ymm2, %ymm1
 ; AVX2-NEXT:    retq
 ;
 ; AVX512-LABEL: reassociate_smin_v64i8:
 ; AVX512:       # %bb.0:
 ; AVX512-NEXT:    vpaddb %zmm1, %zmm0, %zmm0
-; AVX512-NEXT:    vpminsb %zmm3, %zmm2, %zmm1
-; AVX512-NEXT:    vpminsb %zmm1, %zmm0, %zmm0
+; AVX512-NEXT:    vpminsb %zmm2, %zmm3, %zmm1
+; AVX512-NEXT:    vpminsb %zmm0, %zmm1, %zmm0
 ; AVX512-NEXT:    retq
 
   %t0 = add <64 x i8> %x0, %x1
   %t1 = icmp slt <64 x i8> %x2, %t0
   %t2 = select <64 x i1> %t1, <64 x i8> %x2, <64 x i8> %t0
   %t3 = icmp slt <64 x i8> %x3, %t2
   %t4 = select <64 x i1> %t3, <64 x i8> %x3, <64 x i8> %t2
   ret <64 x i8> %t4

 ; SSE-NEXT:    pminsw {{[0-9]+}}(%rsp), %xmm2
 ; SSE-NEXT:    pminsw {{[0-9]+}}(%rsp), %xmm3
 ; SSE-NEXT:    retq
 ;
 ; AVX2-LABEL: reassociate_smin_v32i16:
 ; AVX2:       # %bb.0:
 ; AVX2-NEXT:    vpaddw %ymm2, %ymm0, %ymm0
 ; AVX2-NEXT:    vpaddw %ymm3, %ymm1, %ymm1
-; AVX2-NEXT:    vpminsw %ymm6, %ymm4, %ymm2
-; AVX2-NEXT:    vpminsw %ymm2, %ymm0, %ymm0
-; AVX2-NEXT:    vpminsw %ymm7, %ymm5, %ymm2
-; AVX2-NEXT:    vpminsw %ymm2, %ymm1, %ymm1
+; AVX2-NEXT:    vpminsw %ymm4, %ymm6, %ymm2
+; AVX2-NEXT:    vpminsw %ymm0, %ymm2, %ymm0
+; AVX2-NEXT:    vpminsw %ymm5, %ymm7, %ymm2
+; AVX2-NEXT:    vpminsw %ymm1, %ymm2, %ymm1
 ; AVX2-NEXT:    retq
 ;
 ; AVX512-LABEL: reassociate_smin_v32i16:
 ; AVX512:       # %bb.0:
 ; AVX512-NEXT:    vpaddw %zmm1, %zmm0, %zmm0
-; AVX512-NEXT:    vpminsw %zmm3, %zmm2, %zmm1
-; AVX512-NEXT:    vpminsw %zmm1, %zmm0, %zmm0
+; AVX512-NEXT:    vpminsw %zmm2, %zmm3, %zmm1
+; AVX512-NEXT:    vpminsw %zmm0, %zmm1, %zmm0
 ; AVX512-NEXT:    retq
 
   %t0 = add <32 x i16> %x0, %x1
   %t1 = icmp slt <32 x i16> %x2, %t0
   %t2 = select <32 x i1> %t1, <32 x i16> %x2, <32 x i16> %t0
   %t3 = icmp slt <32 x i16> %x3, %t2
   %t4 = select <32 x i1> %t3, <32 x i16> %x3, <32 x i16> %t2
   ret <32 x i16> %t4

 ; SSE-NEXT:    pandn %xmm4, %xmm3
 ; SSE-NEXT:    por %xmm8, %xmm3
 ; SSE-NEXT:    retq
 ;
 ; AVX2-LABEL: reassociate_smin_v16i32:
 ; AVX2:       # %bb.0:
 ; AVX2-NEXT:    vpaddd %ymm2, %ymm0, %ymm0
 ; AVX2-NEXT:    vpaddd %ymm3, %ymm1, %ymm1
-; AVX2-NEXT:    vpminsd %ymm6, %ymm4, %ymm2
-; AVX2-NEXT:    vpminsd %ymm2, %ymm0, %ymm0
-; AVX2-NEXT:    vpminsd %ymm7, %ymm5, %ymm2
-; AVX2-NEXT:    vpminsd %ymm2, %ymm1, %ymm1
+; AVX2-NEXT:    vpminsd %ymm4, %ymm6, %ymm2
+; AVX2-NEXT:    vpminsd %ymm0, %ymm2, %ymm0
+; AVX2-NEXT:    vpminsd %ymm5, %ymm7, %ymm2
+; AVX2-NEXT:    vpminsd %ymm1, %ymm2, %ymm1
 ; AVX2-NEXT:    retq
 ;
 ; AVX512-LABEL: reassociate_smin_v16i32:
 ; AVX512:       # %bb.0:
 ; AVX512-NEXT:    vpaddd %zmm1, %zmm0, %zmm0
-; AVX512-NEXT:    vpminsd %zmm3, %zmm2, %zmm1
-; AVX512-NEXT:    vpminsd %zmm1, %zmm0, %zmm0
+; AVX512-NEXT:    vpminsd %zmm2, %zmm3, %zmm1
+; AVX512-NEXT:    vpminsd %zmm0, %zmm1, %zmm0
 ; AVX512-NEXT:    retq
 
   %t0 = add <16 x i32> %x0, %x1
   %t1 = icmp slt <16 x i32> %x2, %t0
   %t2 = select <16 x i1> %t1, <16 x i32> %x2, <16 x i32> %t0
   %t3 = icmp slt <16 x i32> %x3, %t2
   %t4 = select <16 x i1> %t3, <16 x i32> %x3, <16 x i32> %t2
   ret <16 x i32> %t4

 ; AVX2-NEXT:    vblendvpd %ymm2, %ymm6, %ymm0, %ymm0
 ; AVX2-NEXT:    vpcmpgtq %ymm7, %ymm1, %ymm2
 ; AVX2-NEXT:    vblendvpd %ymm2, %ymm7, %ymm1, %ymm1
 ; AVX2-NEXT:    retq
 ;
 ; AVX512-LABEL: reassociate_smin_v8i64:
 ; AVX512:       # %bb.0:
 ; AVX512-NEXT:    vpaddq %zmm1, %zmm0, %zmm0
-; AVX512-NEXT:    vpminsq %zmm3, %zmm2, %zmm1
-; AVX512-NEXT:    vpminsq %zmm1, %zmm0, %zmm0
+; AVX512-NEXT:    vpminsq %zmm2, %zmm3, %zmm1
+; AVX512-NEXT:    vpminsq %zmm0, %zmm1, %zmm0
 ; AVX512-NEXT:    retq
 
   %t0 = add <8 x i64> %x0, %x1
   %t1 = icmp slt <8 x i64> %x2, %t0
   %t2 = select <8 x i1> %t1, <8 x i64> %x2, <8 x i64> %t0
   %t3 = icmp slt <8 x i64> %x3, %t2
   %t4 = select <8 x i1> %t3, <8 x i64> %x3, <8 x i64> %t2
   ret <8 x i64> %t4
 }

llvm/test/CodeGen/X86/machine-combiner.ll

 ; SSE-NEXT:    addss %xmm3, %xmm2
 ; SSE-NEXT:    addss %xmm2, %xmm0
 ; SSE-NEXT:    retq
 ;
 ; AVX-LABEL: reassociate_adds2:
 ; AVX:       # %bb.0:
 ; AVX-NEXT:    vaddss %xmm1, %xmm0, %xmm0
 ; AVX-NEXT:    vaddss %xmm3, %xmm2, %xmm1
-; AVX-NEXT:    vaddss %xmm1, %xmm0, %xmm0
+; AVX-NEXT:    vaddss %xmm0, %xmm1, %xmm0
 ; AVX-NEXT:    retq
   %t0 = fadd reassoc nsz float %x0, %x1
   %t1 = fadd reassoc nsz float %x2, %t0
   %t2 = fadd reassoc nsz float %t1, %x3
   ret float %t2
 }
 
 define float @reassociate_adds3(float %x0, float %x1, float %x2, float %x3) {
 ; SSE-LABEL: reassociate_adds3:
 ; SSE:       # %bb.0:
 ; SSE-NEXT:    addss %xmm1, %xmm0
 ; SSE-NEXT:    addss %xmm3, %xmm2
 ; SSE-NEXT:    addss %xmm2, %xmm0
 ; SSE-NEXT:    retq
 ;
 ; AVX-LABEL: reassociate_adds3:
 ; AVX:       # %bb.0:
 ; AVX-NEXT:    vaddss %xmm1, %xmm0, %xmm0
-; AVX-NEXT:    vaddss %xmm3, %xmm2, %xmm1
-; AVX-NEXT:    vaddss %xmm1, %xmm0, %xmm0
+; AVX-NEXT:    vaddss %xmm2, %xmm3, %xmm1
+; AVX-NEXT:    vaddss %xmm0, %xmm1, %xmm0
 ; AVX-NEXT:    retq
   %t0 = fadd reassoc nsz float %x0, %x1
   %t1 = fadd reassoc nsz float %t0, %x2
   %t2 = fadd reassoc nsz float %x3, %t1
   ret float %t2
 }
 
 define float @reassociate_adds4(float %x0, float %x1, float %x2, float %x3) {
 ; SSE-LABEL: reassociate_adds4:
 ; SSE:       # %bb.0:
 ; SSE-NEXT:    addss %xmm1, %xmm0
 ; SSE-NEXT:    addss %xmm3, %xmm2
 ; SSE-NEXT:    addss %xmm2, %xmm0
 ; SSE-NEXT:    retq
 ;
 ; AVX-LABEL: reassociate_adds4:
 ; AVX:       # %bb.0:
 ; AVX-NEXT:    vaddss %xmm1, %xmm0, %xmm0
-; AVX-NEXT:    vaddss %xmm3, %xmm2, %xmm1
-; AVX-NEXT:    vaddss %xmm1, %xmm0, %xmm0
+; AVX-NEXT:    vaddss %xmm2, %xmm3, %xmm1
+; AVX-NEXT:    vaddss %xmm0, %xmm1, %xmm0
 ; AVX-NEXT:    retq
   %t0 = fadd reassoc nsz float %x0, %x1
   %t1 = fadd reassoc nsz float %x2, %t0
   %t2 = fadd reassoc nsz float %x3, %t1
   ret float %t2
 }
 
 ; Verify that we reassociate some of these ops. The optimal balanced tree of adds is not

 ; SSE-NEXT:    divss %xmm1, %xmm0
 ; SSE-NEXT:    addss %xmm3, %xmm2
 ; SSE-NEXT:    addss %xmm2, %xmm0
 ; SSE-NEXT:    retq
 ;
 ; AVX-LABEL: reassociate_adds6:
 ; AVX:       # %bb.0:
 ; AVX-NEXT:    vdivss %xmm1, %xmm0, %xmm0
-; AVX-NEXT:    vaddss %xmm3, %xmm2, %xmm1
-; AVX-NEXT:    vaddss %xmm1, %xmm0, %xmm0
+; AVX-NEXT:    vaddss %xmm2, %xmm3, %xmm1
+; AVX-NEXT:    vaddss %xmm0, %xmm1, %xmm0
 ; AVX-NEXT:    retq
   %t0 = fdiv reassoc nsz float %x0, %x1
   %t1 = fadd reassoc nsz float %x2, %t0
   %t2 = fadd reassoc nsz float %x3, %t1
   ret float %t2
 }
 
 ; Verify that SSE and AVX scalar single-precision multiplies are reassociated.
 
 define float @reassociate_muls1(float %x0, float %x1, float %x2, float %x3) {
 ; SSE-LABEL: reassociate_muls1:
 ; SSE:       # %bb.0:
 ; SSE-NEXT:    divss %xmm1, %xmm0
 ; SSE-NEXT:    mulss %xmm3, %xmm2
 ; SSE-NEXT:    mulss %xmm2, %xmm0
 ; SSE-NEXT:    retq
 ;
 ; AVX-LABEL: reassociate_muls1:
 ; AVX:       # %bb.0:
 ; AVX-NEXT:    vdivss %xmm1, %xmm0, %xmm0
-; AVX-NEXT:    vmulss %xmm3, %xmm2, %xmm1
-; AVX-NEXT:    vmulss %xmm1, %xmm0, %xmm0
+; AVX-NEXT:    vmulss %xmm2, %xmm3, %xmm1
+; AVX-NEXT:    vmulss %xmm0, %xmm1, %xmm0
 ; AVX-NEXT:    retq
   %t0 = fdiv reassoc nsz float %x0, %x1
   %t1 = fmul reassoc nsz float %x2, %t0
   %t2 = fmul reassoc nsz float %x3, %t1
   ret float %t2
 }
 
 ; Verify that SSE and AVX scalar double-precision adds are reassociated.
 
 define double @reassociate_adds_double(double %x0, double %x1, double %x2, double %x3) {
 ; SSE-LABEL: reassociate_adds_double:
 ; SSE:       # %bb.0:
 ; SSE-NEXT:    divsd %xmm1, %xmm0
 ; SSE-NEXT:    addsd %xmm3, %xmm2
 ; SSE-NEXT:    addsd %xmm2, %xmm0
 ; SSE-NEXT:    retq
 ;
 ; AVX-LABEL: reassociate_adds_double:
 ; AVX:       # %bb.0:
 ; AVX-NEXT:    vdivsd %xmm1, %xmm0, %xmm0
-; AVX-NEXT:    vaddsd %xmm3, %xmm2, %xmm1
-; AVX-NEXT:    vaddsd %xmm1, %xmm0, %xmm0
+; AVX-NEXT:    vaddsd %xmm2, %xmm3, %xmm1
+; AVX-NEXT:    vaddsd %xmm0, %xmm1, %xmm0
 ; AVX-NEXT:    retq
   %t0 = fdiv reassoc nsz double %x0, %x1
   %t1 = fadd reassoc nsz double %x2, %t0
   %t2 = fadd reassoc nsz double %x3, %t1
   ret double %t2
 }
 
 ; Verify that SSE and AVX scalar double-precision multiplies are reassociated.
 
 define double @reassociate_muls_double(double %x0, double %x1, double %x2, double %x3) {
 ; SSE-LABEL: reassociate_muls_double:
 ; SSE:       # %bb.0:
 ; SSE-NEXT:    divsd %xmm1, %xmm0
 ; SSE-NEXT:    mulsd %xmm3, %xmm2
 ; SSE-NEXT:    mulsd %xmm2, %xmm0
 ; SSE-NEXT:    retq
 ;
 ; AVX-LABEL: reassociate_muls_double:
 ; AVX:       # %bb.0:
 ; AVX-NEXT:    vdivsd %xmm1, %xmm0, %xmm0
-; AVX-NEXT:    vmulsd %xmm3, %xmm2, %xmm1
-; AVX-NEXT:    vmulsd %xmm1, %xmm0, %xmm0
+; AVX-NEXT:    vmulsd %xmm2, %xmm3, %xmm1
+; AVX-NEXT:    vmulsd %xmm0, %xmm1, %xmm0
 ; AVX-NEXT:    retq
   %t0 = fdiv reassoc nsz double %x0, %x1
   %t1 = fmul reassoc nsz double %x2, %t0
   %t2 = fmul reassoc nsz double %x3, %t1
   ret double %t2
 }
 
 ; Verify that SSE and AVX 128-bit vector single-precision adds are reassociated.
 
 define <4 x float> @reassociate_adds_v4f32(<4 x float> %x0, <4 x float> %x1, <4 x float> %x2, <4 x float> %x3) {
 ; SSE-LABEL: reassociate_adds_v4f32:
 ; SSE:       # %bb.0:
 ; SSE-NEXT:    mulps %xmm1, %xmm0
 ; SSE-NEXT:    addps %xmm3, %xmm2
 ; SSE-NEXT:    addps %xmm2, %xmm0
 ; SSE-NEXT:    retq
 ;
 ; AVX1-LABEL: reassociate_adds_v4f32:
 ; AVX1:       # %bb.0:
 ; AVX1-NEXT:    vmulps %xmm1, %xmm0, %xmm0
-; AVX1-NEXT:    vaddps %xmm3, %xmm2, %xmm1
-; AVX1-NEXT:    vaddps %xmm1, %xmm0, %xmm0
+; AVX1-NEXT:    vaddps %xmm2, %xmm3, %xmm1
+; AVX1-NEXT:    vaddps %xmm0, %xmm1, %xmm0
 ; AVX1-NEXT:    retq
 ;
 ; AVX512-LABEL: reassociate_adds_v4f32:
 ; AVX512:       # %bb.0:
 ; AVX512-NEXT:    vfmadd213ps {{.*#+}} xmm0 = (xmm1 * xmm0) + xmm2
 ; AVX512-NEXT:    vaddps %xmm0, %xmm3, %xmm0
 ; AVX512-NEXT:    retq
   %t0 = fmul contract reassoc nsz <4 x float> %x0, %x1

 ; SSE-NEXT:    mulpd %xmm1, %xmm0
 ; SSE-NEXT:    addpd %xmm3, %xmm2
 ; SSE-NEXT:    addpd %xmm2, %xmm0
 ; SSE-NEXT:    retq
 ;
 ; AVX1-LABEL: reassociate_adds_v2f64:
 ; AVX1:       # %bb.0:
 ; AVX1-NEXT:    vmulpd %xmm1, %xmm0, %xmm0
-; AVX1-NEXT:    vaddpd %xmm3, %xmm2, %xmm1
-; AVX1-NEXT:    vaddpd %xmm1, %xmm0, %xmm0
+; AVX1-NEXT:    vaddpd %xmm2, %xmm3, %xmm1
+; AVX1-NEXT:    vaddpd %xmm0, %xmm1, %xmm0
 ; AVX1-NEXT:    retq
 ;
 ; AVX512-LABEL: reassociate_adds_v2f64:
 ; AVX512:       # %bb.0:
 ; AVX512-NEXT:    vfmadd213pd {{.*#+}} xmm0 = (xmm1 * xmm0) + xmm2
 ; AVX512-NEXT:    vaddpd %xmm0, %xmm3, %xmm0
 ; AVX512-NEXT:    retq
   %t0 = fmul contract reassoc nsz <2 x double> %x0, %x1

 ; SSE-NEXT:    addps %xmm1, %xmm0
 ; SSE-NEXT:    mulps %xmm3, %xmm2
 ; SSE-NEXT:    mulps %xmm2, %xmm0
 ; SSE-NEXT:    retq
 ;
 ; AVX-LABEL: reassociate_muls_v4f32:
 ; AVX:       # %bb.0:
 ; AVX-NEXT:    vaddps %xmm1, %xmm0, %xmm0
-; AVX-NEXT:    vmulps %xmm3, %xmm2, %xmm1
-; AVX-NEXT:    vmulps %xmm1, %xmm0, %xmm0
+; AVX-NEXT:    vmulps %xmm2, %xmm3, %xmm1
+; AVX-NEXT:    vmulps %xmm0, %xmm1, %xmm0
 ; AVX-NEXT:    retq
   %t0 = fadd reassoc nsz <4 x float> %x0, %x1
   %t1 = fmul reassoc nsz <4 x float> %x2, %t0
   %t2 = fmul reassoc nsz <4 x float> %x3, %t1
   ret <4 x float> %t2
 }
 
 ; Verify that SSE and AVX 128-bit vector double-precision multiplies are reassociated.
 
 define <2 x double> @reassociate_muls_v2f64(<2 x double> %x0, <2 x double> %x1, <2 x double> %x2, <2 x double> %x3) {
 ; SSE-LABEL: reassociate_muls_v2f64:
 ; SSE:       # %bb.0:
 ; SSE-NEXT:    addpd %xmm1, %xmm0
 ; SSE-NEXT:    mulpd %xmm3, %xmm2
 ; SSE-NEXT:    mulpd %xmm2, %xmm0
 ; SSE-NEXT:    retq
 ;
 ; AVX-LABEL: reassociate_muls_v2f64:
 ; AVX:       # %bb.0:
 ; AVX-NEXT:    vaddpd %xmm1, %xmm0, %xmm0
-; AVX-NEXT:    vmulpd %xmm3, %xmm2, %xmm1
-; AVX-NEXT:    vmulpd %xmm1, %xmm0, %xmm0
+; AVX-NEXT:    vmulpd %xmm2, %xmm3, %xmm1
+; AVX-NEXT:    vmulpd %xmm0, %xmm1, %xmm0
 ; AVX-NEXT:    retq
   %t0 = fadd reassoc nsz <2 x double> %x0, %x1
   %t1 = fmul reassoc nsz <2 x double> %x2, %t0
   %t2 = fmul reassoc nsz <2 x double> %x3, %t1
   ret <2 x double> %t2
 }
 
 ; Verify that AVX 256-bit vector single-precision adds are reassociated.
 
 define <8 x float> @reassociate_adds_v8f32(<8 x float> %x0, <8 x float> %x1, <8 x float> %x2, <8 x float> %x3) {
 ; SSE-LABEL: reassociate_adds_v8f32:
 ; SSE:       # %bb.0:
 ; SSE-NEXT:    mulps %xmm2, %xmm0
 ; SSE-NEXT:    mulps %xmm3, %xmm1
 ; SSE-NEXT:    addps %xmm6, %xmm4
 ; SSE-NEXT:    addps %xmm4, %xmm0
 ; SSE-NEXT:    addps %xmm7, %xmm5
 ; SSE-NEXT:    addps %xmm5, %xmm1
 ; SSE-NEXT:    retq
 ;
 ; AVX1-LABEL: reassociate_adds_v8f32:
 ; AVX1:       # %bb.0:
 ; AVX1-NEXT:    vmulps %ymm1, %ymm0, %ymm0
-; AVX1-NEXT:    vaddps %ymm3, %ymm2, %ymm1
-; AVX1-NEXT:    vaddps %ymm1, %ymm0, %ymm0
+; AVX1-NEXT:    vaddps %ymm2, %ymm3, %ymm1
+; AVX1-NEXT:    vaddps %ymm0, %ymm1, %ymm0
 ; AVX1-NEXT:    retq
 ;
 ; AVX512-LABEL: reassociate_adds_v8f32:
 ; AVX512:       # %bb.0:
 ; AVX512-NEXT:    vfmadd213ps {{.*#+}} ymm0 = (ymm1 * ymm0) + ymm2
 ; AVX512-NEXT:    vaddps %ymm0, %ymm3, %ymm0
 ; AVX512-NEXT:    retq
   %t0 = fmul contract reassoc nsz <8 x float> %x0, %x1

 ; SSE-NEXT:    addpd %xmm4, %xmm0
 ; SSE-NEXT:    addpd %xmm7, %xmm5
 ; SSE-NEXT:    addpd %xmm5, %xmm1
 ; SSE-NEXT:    retq
 ;
 ; AVX1-LABEL: reassociate_adds_v4f64:
 ; AVX1:       # %bb.0:
 ; AVX1-NEXT:    vmulpd %ymm1, %ymm0, %ymm0
-; AVX1-NEXT:    vaddpd %ymm3, %ymm2, %ymm1
-; AVX1-NEXT:    vaddpd %ymm1, %ymm0, %ymm0
+; AVX1-NEXT:    vaddpd %ymm2, %ymm3, %ymm1
+; AVX1-NEXT:    vaddpd %ymm0, %ymm1, %ymm0
 ; AVX1-NEXT:    retq
 ;
 ; AVX512-LABEL: reassociate_adds_v4f64:
 ; AVX512:       # %bb.0:
 ; AVX512-NEXT:    vfmadd213pd {{.*#+}} ymm0 = (ymm1 * ymm0) + ymm2
 ; AVX512-NEXT:    vaddpd %ymm0, %ymm3, %ymm0
 ; AVX512-NEXT:    retq
   %t0 = fmul contract reassoc nsz <4 x double> %x0, %x1

 ; SSE-NEXT:    mulps %xmm4, %xmm0
 ; SSE-NEXT:    mulps %xmm7, %xmm5
 ; SSE-NEXT:    mulps %xmm5, %xmm1
 ; SSE-NEXT:    retq
 ;
 ; AVX-LABEL: reassociate_muls_v8f32:
 ; AVX:       # %bb.0:
 ; AVX-NEXT:    vaddps %ymm1, %ymm0, %ymm0
-; AVX-NEXT:    vmulps %ymm3, %ymm2, %ymm1
-; AVX-NEXT:    vmulps %ymm1, %ymm0, %ymm0
+; AVX-NEXT:    vmulps %ymm2, %ymm3, %ymm1
+; AVX-NEXT:    vmulps %ymm0, %ymm1, %ymm0
 ; AVX-NEXT:    retq
   %t0 = fadd reassoc nsz <8 x float> %x0, %x1
   %t1 = fmul reassoc nsz <8 x float> %x2, %t0
   %t2 = fmul reassoc nsz <8 x float> %x3, %t1
   ret <8 x float> %t2
 }
 
 ; Verify that AVX 256-bit vector double-precision multiplies are reassociated.
 
 define <4 x double> @reassociate_muls_v4f64(<4 x double> %x0, <4 x double> %x1, <4 x double> %x2, <4 x double> %x3) {
 ; SSE-LABEL: reassociate_muls_v4f64:
 ; SSE:       # %bb.0:
 ; SSE-NEXT:    addpd %xmm2, %xmm0
 ; SSE-NEXT:    addpd %xmm3, %xmm1
 ; SSE-NEXT:    mulpd %xmm6, %xmm4
 ; SSE-NEXT:    mulpd %xmm4, %xmm0
 ; SSE-NEXT:    mulpd %xmm7, %xmm5
 ; SSE-NEXT:    mulpd %xmm5, %xmm1
 ; SSE-NEXT:    retq
 ;
 ; AVX-LABEL: reassociate_muls_v4f64:
 ; AVX:       # %bb.0:
 ; AVX-NEXT:    vaddpd %ymm1, %ymm0, %ymm0
-; AVX-NEXT:    vmulpd %ymm3, %ymm2, %ymm1
-; AVX-NEXT:    vmulpd %ymm1, %ymm0, %ymm0
+; AVX-NEXT:    vmulpd %ymm2, %ymm3, %ymm1
+; AVX-NEXT:    vmulpd %ymm0, %ymm1, %ymm0
 ; AVX-NEXT:    retq
   %t0 = fadd reassoc nsz <4 x double> %x0, %x1
   %t1 = fmul reassoc nsz <4 x double> %x2, %t0
   %t2 = fmul reassoc nsz  <4 x double> %x3, %t1
   ret <4 x double> %t2
 }
 
 ; Verify that AVX512 512-bit vector single-precision adds are reassociated.

 ; SSE-NEXT:    addps {{[0-9]+}}(%rsp), %xmm2
 ; SSE-NEXT:    addps {{[0-9]+}}(%rsp), %xmm3
 ; SSE-NEXT:    retq
 ;
 ; AVX1-LABEL: reassociate_adds_v16f32:
 ; AVX1:       # %bb.0:
 ; AVX1-NEXT:    vmulps %ymm2, %ymm0, %ymm0
 ; AVX1-NEXT:    vmulps %ymm3, %ymm1, %ymm1
-; AVX1-NEXT:    vaddps %ymm6, %ymm4, %ymm2
-; AVX1-NEXT:    vaddps %ymm2, %ymm0, %ymm0
-; AVX1-NEXT:    vaddps %ymm7, %ymm5, %ymm2
-; AVX1-NEXT:    vaddps %ymm2, %ymm1, %ymm1
+; AVX1-NEXT:    vaddps %ymm4, %ymm6, %ymm2
+; AVX1-NEXT:    vaddps %ymm0, %ymm2, %ymm0
+; AVX1-NEXT:    vaddps %ymm5, %ymm7, %ymm2
+; AVX1-NEXT:    vaddps %ymm1, %ymm2, %ymm1
 ; AVX1-NEXT:    retq
 ;
 ; AVX512-LABEL: reassociate_adds_v16f32:
 ; AVX512:       # %bb.0:
 ; AVX512-NEXT:    vfmadd213ps {{.*#+}} zmm0 = (zmm1 * zmm0) + zmm2
 ; AVX512-NEXT:    vaddps %zmm0, %zmm3, %zmm0
 ; AVX512-NEXT:    retq
   %t0 = fmul contract reassoc nsz <16 x float> %x0, %x1

 ; SSE-NEXT:    addpd {{[0-9]+}}(%rsp), %xmm2
 ; SSE-NEXT:    addpd {{[0-9]+}}(%rsp), %xmm3
 ; SSE-NEXT:    retq
 ;
 ; AVX1-LABEL: reassociate_adds_v8f64:
 ; AVX1:       # %bb.0:
 ; AVX1-NEXT:    vmulpd %ymm2, %ymm0, %ymm0
 ; AVX1-NEXT:    vmulpd %ymm3, %ymm1, %ymm1
-; AVX1-NEXT:    vaddpd %ymm6, %ymm4, %ymm2
-; AVX1-NEXT:    vaddpd %ymm2, %ymm0, %ymm0
-; AVX1-NEXT:    vaddpd %ymm7, %ymm5, %ymm2
-; AVX1-NEXT:    vaddpd %ymm2, %ymm1, %ymm1
+; AVX1-NEXT:    vaddpd %ymm4, %ymm6, %ymm2
+; AVX1-NEXT:    vaddpd %ymm0, %ymm2, %ymm0
+; AVX1-NEXT:    vaddpd %ymm5, %ymm7, %ymm2
+; AVX1-NEXT:    vaddpd %ymm1, %ymm2, %ymm1
 ; AVX1-NEXT:    retq
 ;
 ; AVX512-LABEL: reassociate_adds_v8f64:
 ; AVX512:       # %bb.0:
 ; AVX512-NEXT:    vfmadd213pd {{.*#+}} zmm0 = (zmm1 * zmm0) + zmm2
 ; AVX512-NEXT:    vaddpd %zmm0, %zmm3, %zmm0
 ; AVX512-NEXT:    retq
   %t0 = fmul contract reassoc nsz <8 x double> %x0, %x1

 ; SSE-NEXT:    mulps {{[0-9]+}}(%rsp), %xmm2
 ; SSE-NEXT:    mulps {{[0-9]+}}(%rsp), %xmm3
 ; SSE-NEXT:    retq
 ;
 ; AVX1-LABEL: reassociate_muls_v16f32:
 ; AVX1:       # %bb.0:
 ; AVX1-NEXT:    vaddps %ymm2, %ymm0, %ymm0
 ; AVX1-NEXT:    vaddps %ymm3, %ymm1, %ymm1
-; AVX1-NEXT:    vmulps %ymm6, %ymm4, %ymm2
-; AVX1-NEXT:    vmulps %ymm2, %ymm0, %ymm0
-; AVX1-NEXT:    vmulps %ymm7, %ymm5, %ymm2
-; AVX1-NEXT:    vmulps %ymm2, %ymm1, %ymm1
+; AVX1-NEXT:    vmulps %ymm4, %ymm6, %ymm2
+; AVX1-NEXT:    vmulps %ymm0, %ymm2, %ymm0
+; AVX1-NEXT:    vmulps %ymm5, %ymm7, %ymm2
+; AVX1-NEXT:    vmulps %ymm1, %ymm2, %ymm1
 ; AVX1-NEXT:    retq
 ;
 ; AVX512-LABEL: reassociate_muls_v16f32:
 ; AVX512:       # %bb.0:
 ; AVX512-NEXT:    vaddps %zmm1, %zmm0, %zmm0
-; AVX512-NEXT:    vmulps %zmm3, %zmm2, %zmm1
-; AVX512-NEXT:    vmulps %zmm1, %zmm0, %zmm0
+; AVX512-NEXT:    vmulps %zmm2, %zmm3, %zmm1
+; AVX512-NEXT:    vmulps %zmm0, %zmm1, %zmm0
 ; AVX512-NEXT:    retq
   %t0 = fadd reassoc nsz <16 x float> %x0, %x1
   %t1 = fmul reassoc nsz <16 x float> %x2, %t0
   %t2 = fmul reassoc nsz <16 x float> %x3, %t1
   ret <16 x float> %t2
 }
 
 ; Verify that AVX512 512-bit vector double-precision multiplies are reassociated.

 ; SSE-NEXT:    mulpd {{[0-9]+}}(%rsp), %xmm2
 ; SSE-NEXT:    mulpd {{[0-9]+}}(%rsp), %xmm3
 ; SSE-NEXT:    retq
 ;
 ; AVX1-LABEL: reassociate_muls_v8f64:
 ; AVX1:       # %bb.0:
 ; AVX1-NEXT:    vaddpd %ymm2, %ymm0, %ymm0
 ; AVX1-NEXT:    vaddpd %ymm3, %ymm1, %ymm1
-; AVX1-NEXT:    vmulpd %ymm6, %ymm4, %ymm2
-; AVX1-NEXT:    vmulpd %ymm2, %ymm0, %ymm0
-; AVX1-NEXT:    vmulpd %ymm7, %ymm5, %ymm2
-; AVX1-NEXT:    vmulpd %ymm2, %ymm1, %ymm1
+; AVX1-NEXT:    vmulpd %ymm4, %ymm6, %ymm2
+; AVX1-NEXT:    vmulpd %ymm0, %ymm2, %ymm0
+; AVX1-NEXT:    vmulpd %ymm5, %ymm7, %ymm2
+; AVX1-NEXT:    vmulpd %ymm1, %ymm2, %ymm1
 ; AVX1-NEXT:    retq
 ;
 ; AVX512-LABEL: reassociate_muls_v8f64:
 ; AVX512:       # %bb.0:
 ; AVX512-NEXT:    vaddpd %zmm1, %zmm0, %zmm0
-; AVX512-NEXT:    vmulpd %zmm3, %zmm2, %zmm1
-; AVX512-NEXT:    vmulpd %zmm1, %zmm0, %zmm0
+; AVX512-NEXT:    vmulpd %zmm2, %zmm3, %zmm1
+; AVX512-NEXT:    vmulpd %zmm0, %zmm1, %zmm0
 ; AVX512-NEXT:    retq
   %t0 = fadd reassoc nsz <8 x double> %x0, %x1
   %t1 = fmul reassoc nsz <8 x double> %x2, %t0
   %t2 = fmul reassoc nsz <8 x double> %x3, %t1
   ret <8 x double> %t2
 }
 
 ; Verify that SSE and AVX scalar single-precision minimum ops are reassociated.
 
 define float @reassociate_mins_single(float %x0, float %x1, float %x2, float %x3) {
 ; SSE-LABEL: reassociate_mins_single:
 ; SSE:       # %bb.0:
 ; SSE-NEXT:    divss %xmm1, %xmm0
 ; SSE-NEXT:    minss %xmm3, %xmm2
 ; SSE-NEXT:    minss %xmm2, %xmm0
 ; SSE-NEXT:    retq
 ;
 ; AVX-LABEL: reassociate_mins_single:
 ; AVX:       # %bb.0:
 ; AVX-NEXT:    vdivss %xmm1, %xmm0, %xmm0
-; AVX-NEXT:    vminss %xmm3, %xmm2, %xmm1
-; AVX-NEXT:    vminss %xmm1, %xmm0, %xmm0
+; AVX-NEXT:    vminss %xmm2, %xmm3, %xmm1
+; AVX-NEXT:    vminss %xmm0, %xmm1, %xmm0
 ; AVX-NEXT:    retq
   %t0 = fdiv float %x0, %x1
   %cmp1 = fcmp olt float %x2, %t0
   %sel1 = select i1 %cmp1, float %x2, float %t0
   %cmp2 = fcmp olt float %x3, %sel1
   %sel2 = select i1 %cmp2, float %x3, float %sel1
   ret float %sel2
 }
 
 ; Verify that SSE and AVX scalar single-precision maximum ops are reassociated.
 
 define float @reassociate_maxs_single(float %x0, float %x1, float %x2, float %x3) {
 ; SSE-LABEL: reassociate_maxs_single:
 ; SSE:       # %bb.0:
 ; SSE-NEXT:    divss %xmm1, %xmm0
 ; SSE-NEXT:    maxss %xmm3, %xmm2
 ; SSE-NEXT:    maxss %xmm2, %xmm0
 ; SSE-NEXT:    retq
 ;
 ; AVX-LABEL: reassociate_maxs_single:
 ; AVX:       # %bb.0:
 ; AVX-NEXT:    vdivss %xmm1, %xmm0, %xmm0
-; AVX-NEXT:    vmaxss %xmm3, %xmm2, %xmm1
-; AVX-NEXT:    vmaxss %xmm1, %xmm0, %xmm0
+; AVX-NEXT:    vmaxss %xmm2, %xmm3, %xmm1
+; AVX-NEXT:    vmaxss %xmm0, %xmm1, %xmm0
 ; AVX-NEXT:    retq
   %t0 = fdiv float %x0, %x1
   %cmp1 = fcmp ogt float %x2, %t0
   %sel1 = select i1 %cmp1, float %x2, float %t0
   %cmp2 = fcmp ogt float %x3, %sel1
   %sel2 = select i1 %cmp2, float %x3, float %sel1
   ret float %sel2
 }
 
 ; Verify that SSE and AVX scalar double-precision minimum ops are reassociated.
 
 define double @reassociate_mins_double(double %x0, double %x1, double %x2, double %x3) {
 ; SSE-LABEL: reassociate_mins_double:
 ; SSE:       # %bb.0:
 ; SSE-NEXT:    divsd %xmm1, %xmm0
 ; SSE-NEXT:    minsd %xmm3, %xmm2
 ; SSE-NEXT:    minsd %xmm2, %xmm0
 ; SSE-NEXT:    retq
 ;
 ; AVX-LABEL: reassociate_mins_double:
 ; AVX:       # %bb.0:
 ; AVX-NEXT:    vdivsd %xmm1, %xmm0, %xmm0
-; AVX-NEXT:    vminsd %xmm3, %xmm2, %xmm1
-; AVX-NEXT:    vminsd %xmm1, %xmm0, %xmm0
+; AVX-NEXT:    vminsd %xmm2, %xmm3, %xmm1
+; AVX-NEXT:    vminsd %xmm0, %xmm1, %xmm0
 ; AVX-NEXT:    retq
   %t0 = fdiv double %x0, %x1
   %cmp1 = fcmp olt double %x2, %t0
   %sel1 = select i1 %cmp1, double %x2, double %t0
   %cmp2 = fcmp olt double %x3, %sel1
   %sel2 = select i1 %cmp2, double %x3, double %sel1
   ret double %sel2
 }
 
 ; Verify that SSE and AVX scalar double-precision maximum ops are reassociated.
 
 define double @reassociate_maxs_double(double %x0, double %x1, double %x2, double %x3) {
 ; SSE-LABEL: reassociate_maxs_double:
 ; SSE:       # %bb.0:
 ; SSE-NEXT:    divsd %xmm1, %xmm0
 ; SSE-NEXT:    maxsd %xmm3, %xmm2
 ; SSE-NEXT:    maxsd %xmm2, %xmm0
 ; SSE-NEXT:    retq
 ;
 ; AVX-LABEL: reassociate_maxs_double:
 ; AVX:       # %bb.0:
 ; AVX-NEXT:    vdivsd %xmm1, %xmm0, %xmm0
-; AVX-NEXT:    vmaxsd %xmm3, %xmm2, %xmm1
-; AVX-NEXT:    vmaxsd %xmm1, %xmm0, %xmm0
+; AVX-NEXT:    vmaxsd %xmm2, %xmm3, %xmm1
+; AVX-NEXT:    vmaxsd %xmm0, %xmm1, %xmm0
 ; AVX-NEXT:    retq
   %t0 = fdiv double %x0, %x1
   %cmp1 = fcmp ogt double %x2, %t0
   %sel1 = select i1 %cmp1, double %x2, double %t0
   %cmp2 = fcmp ogt double %x3, %sel1
   %sel2 = select i1 %cmp2, double %x3, double %sel1
   ret double %sel2
 }
 
 ; Verify that SSE and AVX 128-bit vector single-precision minimum ops are reassociated.
 
 define <4 x float> @reassociate_mins_v4f32(<4 x float> %x0, <4 x float> %x1, <4 x float> %x2, <4 x float> %x3) {
 ; SSE-LABEL: reassociate_mins_v4f32:
 ; SSE:       # %bb.0:
 ; SSE-NEXT:    addps %xmm1, %xmm0
 ; SSE-NEXT:    minps %xmm3, %xmm2
 ; SSE-NEXT:    minps %xmm2, %xmm0
 ; SSE-NEXT:    retq
 ;
 ; AVX-LABEL: reassociate_mins_v4f32:
 ; AVX:       # %bb.0:
 ; AVX-NEXT:    vaddps %xmm1, %xmm0, %xmm0
-; AVX-NEXT:    vminps %xmm3, %xmm2, %xmm1
-; AVX-NEXT:    vminps %xmm1, %xmm0, %xmm0
+; AVX-NEXT:    vminps %xmm2, %xmm3, %xmm1
+; AVX-NEXT:    vminps %xmm0, %xmm1, %xmm0
 ; AVX-NEXT:    retq
   %t0 = fadd <4 x float> %x0, %x1
   %cmp1 = fcmp olt <4 x float> %x2, %t0
   %sel1 = select <4 x i1> %cmp1, <4 x float> %x2, <4 x float> %t0
   %cmp2 = fcmp olt <4 x float> %x3, %sel1
   %sel2 = select <4 x i1> %cmp2, <4 x float> %x3, <4 x float> %sel1
   ret <4 x float> %sel2
 }
 
 ; Verify that SSE and AVX 128-bit vector single-precision maximum ops are reassociated.
 
 define <4 x float> @reassociate_maxs_v4f32(<4 x float> %x0, <4 x float> %x1, <4 x float> %x2, <4 x float> %x3) {
 ; SSE-LABEL: reassociate_maxs_v4f32:
 ; SSE:       # %bb.0:
 ; SSE-NEXT:    addps %xmm1, %xmm0
 ; SSE-NEXT:    maxps %xmm3, %xmm2
 ; SSE-NEXT:    maxps %xmm2, %xmm0
 ; SSE-NEXT:    retq
 ;
 ; AVX-LABEL: reassociate_maxs_v4f32:
 ; AVX:       # %bb.0:
 ; AVX-NEXT:    vaddps %xmm1, %xmm0, %xmm0
-; AVX-NEXT:    vmaxps %xmm3, %xmm2, %xmm1
-; AVX-NEXT:    vmaxps %xmm1, %xmm0, %xmm0
+; AVX-NEXT:    vmaxps %xmm2, %xmm3, %xmm1
+; AVX-NEXT:    vmaxps %xmm0, %xmm1, %xmm0
 ; AVX-NEXT:    retq
   %t0 = fadd <4 x float> %x0, %x1
   %cmp1 = fcmp ogt <4 x float> %x2, %t0
   %sel1 = select <4 x i1> %cmp1, <4 x float> %x2, <4 x float> %t0
   %cmp2 = fcmp ogt <4 x float> %x3, %sel1
   %sel2 = select <4 x i1> %cmp2, <4 x float> %x3, <4 x float> %sel1
   ret <4 x float> %sel2
 }
 
 ; Verify that SSE and AVX 128-bit vector double-precision minimum ops are reassociated.
 
 define <2 x double> @reassociate_mins_v2f64(<2 x double> %x0, <2 x double> %x1, <2 x double> %x2, <2 x double> %x3) {
 ; SSE-LABEL: reassociate_mins_v2f64:
 ; SSE:       # %bb.0:
 ; SSE-NEXT:    addpd %xmm1, %xmm0
 ; SSE-NEXT:    minpd %xmm3, %xmm2
 ; SSE-NEXT:    minpd %xmm2, %xmm0
 ; SSE-NEXT:    retq
 ;
 ; AVX-LABEL: reassociate_mins_v2f64:
 ; AVX:       # %bb.0:
 ; AVX-NEXT:    vaddpd %xmm1, %xmm0, %xmm0
-; AVX-NEXT:    vminpd %xmm3, %xmm2, %xmm1
-; AVX-NEXT:    vminpd %xmm1, %xmm0, %xmm0
+; AVX-NEXT:    vminpd %xmm2, %xmm3, %xmm1
+; AVX-NEXT:    vminpd %xmm0, %xmm1, %xmm0
 ; AVX-NEXT:    retq
   %t0 = fadd <2 x double> %x0, %x1
   %cmp1 = fcmp olt <2 x double> %x2, %t0
   %sel1 = select <2 x i1> %cmp1, <2 x double> %x2, <2 x double> %t0
   %cmp2 = fcmp olt <2 x double> %x3, %sel1
   %sel2 = select <2 x i1> %cmp2, <2 x double> %x3, <2 x double> %sel1
   ret <2 x double> %sel2
 }
 
 ; Verify that SSE and AVX 128-bit vector double-precision maximum ops are reassociated.
 
 define <2 x double> @reassociate_maxs_v2f64(<2 x double> %x0, <2 x double> %x1, <2 x double> %x2, <2 x double> %x3) {
 ; SSE-LABEL: reassociate_maxs_v2f64:
 ; SSE:       # %bb.0:
 ; SSE-NEXT:    addpd %xmm1, %xmm0
 ; SSE-NEXT:    maxpd %xmm3, %xmm2
 ; SSE-NEXT:    maxpd %xmm2, %xmm0
 ; SSE-NEXT:    retq
 ;
 ; AVX-LABEL: reassociate_maxs_v2f64:
 ; AVX:       # %bb.0:
 ; AVX-NEXT:    vaddpd %xmm1, %xmm0, %xmm0
-; AVX-NEXT:    vmaxpd %xmm3, %xmm2, %xmm1
-; AVX-NEXT:    vmaxpd %xmm1, %xmm0, %xmm0
+; AVX-NEXT:    vmaxpd %xmm2, %xmm3, %xmm1
+; AVX-NEXT:    vmaxpd %xmm0, %xmm1, %xmm0
 ; AVX-NEXT:    retq
   %t0 = fadd <2 x double> %x0, %x1
   %cmp1 = fcmp ogt <2 x double> %x2, %t0
   %sel1 = select <2 x i1> %cmp1, <2 x double> %x2, <2 x double> %t0
   %cmp2 = fcmp ogt <2 x double> %x3, %sel1
   %sel2 = select <2 x i1> %cmp2, <2 x double> %x3, <2 x double> %sel1
   ret <2 x double> %sel2
 }

 ; SSE-NEXT:    minps %xmm4, %xmm0
 ; SSE-NEXT:    minps %xmm7, %xmm5
 ; SSE-NEXT:    minps %xmm5, %xmm1
 ; SSE-NEXT:    retq
 ;
 ; AVX-LABEL: reassociate_mins_v8f32:
 ; AVX:       # %bb.0:
 ; AVX-NEXT:    vaddps %ymm1, %ymm0, %ymm0
-; AVX-NEXT:    vminps %ymm3, %ymm2, %ymm1
-; AVX-NEXT:    vminps %ymm1, %ymm0, %ymm0
+; AVX-NEXT:    vminps %ymm2, %ymm3, %ymm1
+; AVX-NEXT:    vminps %ymm0, %ymm1, %ymm0
 ; AVX-NEXT:    retq
   %t0 = fadd <8 x float> %x0, %x1
   %cmp1 = fcmp olt <8 x float> %x2, %t0
   %sel1 = select <8 x i1> %cmp1, <8 x float> %x2, <8 x float> %t0
   %cmp2 = fcmp olt <8 x float> %x3, %sel1
   %sel2 = select <8 x i1> %cmp2, <8 x float> %x3, <8 x float> %sel1
   ret <8 x float> %sel2
 }

 ; SSE-NEXT:    maxps %xmm4, %xmm0
 ; SSE-NEXT:    maxps %xmm7, %xmm5
 ; SSE-NEXT:    maxps %xmm5, %xmm1
 ; SSE-NEXT:    retq
 ;
 ; AVX-LABEL: reassociate_maxs_v8f32:
 ; AVX:       # %bb.0:
 ; AVX-NEXT:    vaddps %ymm1, %ymm0, %ymm0
-; AVX-NEXT:    vmaxps %ymm3, %ymm2, %ymm1
-; AVX-NEXT:    vmaxps %ymm1, %ymm0, %ymm0
+; AVX-NEXT:    vmaxps %ymm2, %ymm3, %ymm1
+; AVX-NEXT:    vmaxps %ymm0, %ymm1, %ymm0
 ; AVX-NEXT:    retq
   %t0 = fadd <8 x float> %x0, %x1
   %cmp1 = fcmp ogt <8 x float> %x2, %t0
   %sel1 = select <8 x i1> %cmp1, <8 x float> %x2, <8 x float> %t0
   %cmp2 = fcmp ogt <8 x float> %x3, %sel1
   %sel2 = select <8 x i1> %cmp2, <8 x float> %x3, <8 x float> %sel1
   ret <8 x float> %sel2
 }

 ; SSE-NEXT:    minpd %xmm4, %xmm0
 ; SSE-NEXT:    minpd %xmm7, %xmm5
 ; SSE-NEXT:    minpd %xmm5, %xmm1
 ; SSE-NEXT:    retq
 ;
 ; AVX-LABEL: reassociate_mins_v4f64:
 ; AVX:       # %bb.0:
 ; AVX-NEXT:    vaddpd %ymm1, %ymm0, %ymm0
-; AVX-NEXT:    vminpd %ymm3, %ymm2, %ymm1
-; AVX-NEXT:    vminpd %ymm1, %ymm0, %ymm0
+; AVX-NEXT:    vminpd %ymm2, %ymm3, %ymm1
+; AVX-NEXT:    vminpd %ymm0, %ymm1, %ymm0
 ; AVX-NEXT:    retq
   %t0 = fadd <4 x double> %x0, %x1
   %cmp1 = fcmp olt <4 x double> %x2, %t0
   %sel1 = select <4 x i1> %cmp1, <4 x double> %x2, <4 x double> %t0
   %cmp2 = fcmp olt <4 x double> %x3, %sel1
   %sel2 = select <4 x i1> %cmp2, <4 x double> %x3, <4 x double> %sel1
   ret <4 x double> %sel2
 }

 ; SSE-NEXT:    maxpd %xmm4, %xmm0
 ; SSE-NEXT:    maxpd %xmm7, %xmm5
 ; SSE-NEXT:    maxpd %xmm5, %xmm1
 ; SSE-NEXT:    retq
 ;
 ; AVX-LABEL: reassociate_maxs_v4f64:
 ; AVX:       # %bb.0:
 ; AVX-NEXT:    vaddpd %ymm1, %ymm0, %ymm0
-; AVX-NEXT:    vmaxpd %ymm3, %ymm2, %ymm1
-; AVX-NEXT:    vmaxpd %ymm1, %ymm0, %ymm0
+; AVX-NEXT:    vmaxpd %ymm2, %ymm3, %ymm1
+; AVX-NEXT:    vmaxpd %ymm0, %ymm1, %ymm0
 ; AVX-NEXT:    retq
   %t0 = fadd <4 x double> %x0, %x1
   %cmp1 = fcmp ogt <4 x double> %x2, %t0
   %sel1 = select <4 x i1> %cmp1, <4 x double> %x2, <4 x double> %t0
   %cmp2 = fcmp ogt <4 x double> %x3, %sel1
   %sel2 = select <4 x i1> %cmp2, <4 x double> %x3, <4 x double> %sel1
   ret <4 x double> %sel2
 }

 ; SSE-NEXT:    minps {{[0-9]+}}(%rsp), %xmm2
 ; SSE-NEXT:    minps {{[0-9]+}}(%rsp), %xmm3
 ; SSE-NEXT:    retq
 ;
 ; AVX1-LABEL: reassociate_mins_v16f32:
 ; AVX1:       # %bb.0:
 ; AVX1-NEXT:    vaddps %ymm2, %ymm0, %ymm0
 ; AVX1-NEXT:    vaddps %ymm3, %ymm1, %ymm1
-; AVX1-NEXT:    vminps %ymm6, %ymm4, %ymm2
-; AVX1-NEXT:    vminps %ymm2, %ymm0, %ymm0
-; AVX1-NEXT:    vminps %ymm7, %ymm5, %ymm2
-; AVX1-NEXT:    vminps %ymm2, %ymm1, %ymm1
+; AVX1-NEXT:    vminps %ymm4, %ymm6, %ymm2
+; AVX1-NEXT:    vminps %ymm0, %ymm2, %ymm0
+; AVX1-NEXT:    vminps %ymm5, %ymm7, %ymm2
+; AVX1-NEXT:    vminps %ymm1, %ymm2, %ymm1
 ; AVX1-NEXT:    retq
 ;
 ; AVX512-LABEL: reassociate_mins_v16f32:
 ; AVX512:       # %bb.0:
 ; AVX512-NEXT:    vaddps %zmm1, %zmm0, %zmm0
-; AVX512-NEXT:    vminps %zmm3, %zmm2, %zmm1
-; AVX512-NEXT:    vminps %zmm1, %zmm0, %zmm0
+; AVX512-NEXT:    vminps %zmm2, %zmm3, %zmm1
+; AVX512-NEXT:    vminps %zmm0, %zmm1, %zmm0
 ; AVX512-NEXT:    retq
   %t0 = fadd <16 x float> %x0, %x1
   %cmp1 = fcmp olt <16 x float> %x2, %t0
   %sel1 = select <16 x i1> %cmp1, <16 x float> %x2, <16 x float> %t0
   %cmp2 = fcmp olt <16 x float> %x3, %sel1
   %sel2 = select <16 x i1> %cmp2, <16 x float> %x3, <16 x float> %sel1
   ret <16 x float> %sel2
 }

 ; SSE-NEXT:    maxps {{[0-9]+}}(%rsp), %xmm2
 ; SSE-NEXT:    maxps {{[0-9]+}}(%rsp), %xmm3
 ; SSE-NEXT:    retq
 ;
 ; AVX1-LABEL: reassociate_maxs_v16f32:
 ; AVX1:       # %bb.0:
 ; AVX1-NEXT:    vaddps %ymm2, %ymm0, %ymm0
 ; AVX1-NEXT:    vaddps %ymm3, %ymm1, %ymm1
-; AVX1-NEXT:    vmaxps %ymm6, %ymm4, %ymm2
-; AVX1-NEXT:    vmaxps %ymm2, %ymm0, %ymm0
-; AVX1-NEXT:    vmaxps %ymm7, %ymm5, %ymm2
-; AVX1-NEXT:    vmaxps %ymm2, %ymm1, %ymm1
+; AVX1-NEXT:    vmaxps %ymm4, %ymm6, %ymm2
+; AVX1-NEXT:    vmaxps %ymm0, %ymm2, %ymm0
+; AVX1-NEXT:    vmaxps %ymm5, %ymm7, %ymm2
+; AVX1-NEXT:    vmaxps %ymm1, %ymm2, %ymm1
 ; AVX1-NEXT:    retq
 ;
 ; AVX512-LABEL: reassociate_maxs_v16f32:
 ; AVX512:       # %bb.0:
 ; AVX512-NEXT:    vaddps %zmm1, %zmm0, %zmm0
-; AVX512-NEXT:    vmaxps %zmm3, %zmm2, %zmm1
-; AVX512-NEXT:    vmaxps %zmm1, %zmm0, %zmm0
+; AVX512-NEXT:    vmaxps %zmm2, %zmm3, %zmm1
+; AVX512-NEXT:    vmaxps %zmm0, %zmm1, %zmm0
 ; AVX512-NEXT:    retq
   %t0 = fadd <16 x float> %x0, %x1
   %cmp1 = fcmp ogt <16 x float> %x2, %t0
   %sel1 = select <16 x i1> %cmp1, <16 x float> %x2, <16 x float> %t0
   %cmp2 = fcmp ogt <16 x float> %x3, %sel1
   %sel2 = select <16 x i1> %cmp2, <16 x float> %x3, <16 x float> %sel1
   ret <16 x float> %sel2
 }

 ; SSE-NEXT:    minpd {{[0-9]+}}(%rsp), %xmm2
 ; SSE-NEXT:    minpd {{[0-9]+}}(%rsp), %xmm3
 ; SSE-NEXT:    retq
 ;
 ; AVX1-LABEL: reassociate_mins_v8f64:
 ; AVX1:       # %bb.0:
 ; AVX1-NEXT:    vaddpd %ymm2, %ymm0, %ymm0
 ; AVX1-NEXT:    vaddpd %ymm3, %ymm1, %ymm1
-; AVX1-NEXT:    vminpd %ymm6, %ymm4, %ymm2
-; AVX1-NEXT:    vminpd %ymm2, %ymm0, %ymm0
-; AVX1-NEXT:    vminpd %ymm7, %ymm5, %ymm2
-; AVX1-NEXT:    vminpd %ymm2, %ymm1, %ymm1
+; AVX1-NEXT:    vminpd %ymm4, %ymm6, %ymm2
+; AVX1-NEXT:    vminpd %ymm0, %ymm2, %ymm0
+; AVX1-NEXT:    vminpd %ymm5, %ymm7, %ymm2
+; AVX1-NEXT:    vminpd %ymm1, %ymm2, %ymm1
 ; AVX1-NEXT:    retq
 ;
 ; AVX512-LABEL: reassociate_mins_v8f64:
 ; AVX512:       # %bb.0:
 ; AVX512-NEXT:    vaddpd %zmm1, %zmm0, %zmm0
-; AVX512-NEXT:    vminpd %zmm3, %zmm2, %zmm1
-; AVX512-NEXT:    vminpd %zmm1, %zmm0, %zmm0
+; AVX512-NEXT:    vminpd %zmm2, %zmm3, %zmm1
+; AVX512-NEXT:    vminpd %zmm0, %zmm1, %zmm0
 ; AVX512-NEXT:    retq
   %t0 = fadd <8 x double> %x0, %x1
   %cmp1 = fcmp olt <8 x double> %x2, %t0
   %sel1 = select <8 x i1> %cmp1, <8 x double> %x2, <8 x double> %t0
   %cmp2 = fcmp olt <8 x double> %x3, %sel1
   %sel2 = select <8 x i1> %cmp2, <8 x double> %x3, <8 x double> %sel1
   ret <8 x double> %sel2
 }

 ; SSE-NEXT:    maxpd {{[0-9]+}}(%rsp), %xmm2
 ; SSE-NEXT:    maxpd {{[0-9]+}}(%rsp), %xmm3
 ; SSE-NEXT:    retq
 ;
 ; AVX1-LABEL: reassociate_maxs_v8f64:
 ; AVX1:       # %bb.0:
 ; AVX1-NEXT:    vaddpd %ymm2, %ymm0, %ymm0
 ; AVX1-NEXT:    vaddpd %ymm3, %ymm1, %ymm1
-; AVX1-NEXT:    vmaxpd %ymm6, %ymm4, %ymm2
-; AVX1-NEXT:    vmaxpd %ymm2, %ymm0, %ymm0
-; AVX1-NEXT:    vmaxpd %ymm7, %ymm5, %ymm2
-; AVX1-NEXT:    vmaxpd %ymm2, %ymm1, %ymm1
+; AVX1-NEXT:    vmaxpd %ymm4, %ymm6, %ymm2
+; AVX1-NEXT:    vmaxpd %ymm0, %ymm2, %ymm0
+; AVX1-NEXT:    vmaxpd %ymm5, %ymm7, %ymm2
+; AVX1-NEXT:    vmaxpd %ymm1, %ymm2, %ymm1
 ; AVX1-NEXT:    retq
 ;
 ; AVX512-LABEL: reassociate_maxs_v8f64:
 ; AVX512:       # %bb.0:
 ; AVX512-NEXT:    vaddpd %zmm1, %zmm0, %zmm0
-; AVX512-NEXT:    vmaxpd %zmm3, %zmm2, %zmm1
-; AVX512-NEXT:    vmaxpd %zmm1, %zmm0, %zmm0
+; AVX512-NEXT:    vmaxpd %zmm2, %zmm3, %zmm1
+; AVX512-NEXT:    vmaxpd %zmm0, %zmm1, %zmm0
 ; AVX512-NEXT:    retq
   %t0 = fadd <8 x double> %x0, %x1
   %cmp1 = fcmp ogt <8 x double> %x2, %t0
   %sel1 = select <8 x i1> %cmp1, <8 x double> %x2, <8 x double> %t0
   %cmp2 = fcmp ogt <8 x double> %x3, %sel1
   %sel2 = select <8 x i1> %cmp2, <8 x double> %x3, <8 x double> %sel1
   ret <8 x double> %sel2
 }

llvm/test/CodeGen/X86/madd.ll

 ; AVX-NEXT:    vpmaddwd (%rsi), %xmm0, %xmm0
 ; AVX-NEXT:    vmovdqu (%rdx), %xmm1
 ; AVX-NEXT:    vpmaddwd (%rcx), %xmm1, %xmm1
 ; AVX-NEXT:    vmovdqu (%r8), %xmm2
 ; AVX-NEXT:    vpmaddwd (%r9), %xmm2, %xmm2
 ; AVX-NEXT:    vpaddd %xmm2, %xmm0, %xmm0
 ; AVX-NEXT:    vmovdqu (%r10), %xmm2
 ; AVX-NEXT:    vpmaddwd (%rax), %xmm2, %xmm2
-; AVX-NEXT:    vpaddd %xmm2, %xmm0, %xmm0
-; AVX-NEXT:    vpaddd %xmm0, %xmm1, %xmm0
+; AVX-NEXT:    vpaddd %xmm0, %xmm2, %xmm0
+; AVX-NEXT:    vpaddd %xmm1, %xmm0, %xmm0
 ; AVX-NEXT:    vpshufd {{.*#+}} xmm1 = xmm0[2,3,2,3]
 ; AVX-NEXT:    vpaddd %xmm1, %xmm0, %xmm0
 ; AVX-NEXT:    vpshufd {{.*#+}} xmm1 = xmm0[1,1,1,1]
 ; AVX-NEXT:    vpaddd %xmm1, %xmm0, %xmm0
 ; AVX-NEXT:    vmovd %xmm0, %eax
 ; AVX-NEXT:    retq
   %tmp = load <8 x i16>, <8 x i16>* %arg, align 1
   %tmp6 = load <8 x i16>, <8 x i16>* %arg1, align 1

llvm/test/CodeGen/X86/masked_gather_scatter.ll

 ; KNL_64-LABEL: test9:
 ; KNL_64:       # %bb.0: # %entry
 ; KNL_64-NEXT:    vpbroadcastq %rdi, %zmm2
 ; KNL_64-NEXT:    vpbroadcastq {{.*#+}} zmm3 = [824,824,824,824,824,824,824,824]
 ; KNL_64-NEXT:    vpmuludq %zmm3, %zmm0, %zmm4
 ; KNL_64-NEXT:    vpsrlq $32, %zmm0, %zmm0
 ; KNL_64-NEXT:    vpmuludq %zmm3, %zmm0, %zmm0
 ; KNL_64-NEXT:    vpsllq $32, %zmm0, %zmm0
-; KNL_64-NEXT:    vpaddq %zmm2, %zmm0, %zmm0
+; KNL_64-NEXT:    vpaddq %zmm0, %zmm2, %zmm0
 ; KNL_64-NEXT:    vpmovzxdq {{.*#+}} zmm1 = ymm1[0],zero,ymm1[1],zero,ymm1[2],zero,ymm1[3],zero,ymm1[4],zero,ymm1[5],zero,ymm1[6],zero,ymm1[7],zero
 ; KNL_64-NEXT:    vpmuldq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm1, %zmm1
-; KNL_64-NEXT:    vpaddq %zmm1, %zmm0, %zmm0
-; KNL_64-NEXT:    vpaddq %zmm0, %zmm4, %zmm1
+; KNL_64-NEXT:    vpaddq %zmm1, %zmm4, %zmm1
+; KNL_64-NEXT:    vpaddq %zmm1, %zmm0, %zmm1
 ; KNL_64-NEXT:    kxnorw %k0, %k0, %k1
 ; KNL_64-NEXT:    vpxor %xmm0, %xmm0, %xmm0
 ; KNL_64-NEXT:    vpgatherqd 72(,%zmm1), %ymm0 {%k1}
 ; KNL_64-NEXT:    retq
 ;
 ; KNL_32-LABEL: test9:
 ; KNL_32:       # %bb.0: # %entry
 ; KNL_32-NEXT:    vpbroadcastd {{[0-9]+}}(%esp), %ymm2

 ; KNL_64-LABEL: test10:
 ; KNL_64:       # %bb.0: # %entry
 ; KNL_64-NEXT:    vpbroadcastq %rdi, %zmm2
 ; KNL_64-NEXT:    vpbroadcastq {{.*#+}} zmm3 = [824,824,824,824,824,824,824,824]
 ; KNL_64-NEXT:    vpmuludq %zmm3, %zmm0, %zmm4
 ; KNL_64-NEXT:    vpsrlq $32, %zmm0, %zmm0
 ; KNL_64-NEXT:    vpmuludq %zmm3, %zmm0, %zmm0
 ; KNL_64-NEXT:    vpsllq $32, %zmm0, %zmm0
-; KNL_64-NEXT:    vpaddq %zmm2, %zmm0, %zmm0
+; KNL_64-NEXT:    vpaddq %zmm0, %zmm2, %zmm0
 ; KNL_64-NEXT:    vpmovzxdq {{.*#+}} zmm1 = ymm1[0],zero,ymm1[1],zero,ymm1[2],zero,ymm1[3],zero,ymm1[4],zero,ymm1[5],zero,ymm1[6],zero,ymm1[7],zero
 ; KNL_64-NEXT:    vpmuldq {{\.?LCPI[0-9]+_[0-9]+}}(%rip){1to8}, %zmm1, %zmm1
-; KNL_64-NEXT:    vpaddq %zmm1, %zmm0, %zmm0
-; KNL_64-NEXT:    vpaddq %zmm0, %zmm4, %zmm1
+; KNL_64-NEXT:    vpaddq %zmm1, %zmm4, %zmm1
+; KNL_64-NEXT:    vpaddq %zmm1, %zmm0, %zmm1
 ; KNL_64-NEXT:    kxnorw %k0, %k0, %k1
 ; KNL_64-NEXT:    vpxor %xmm0, %xmm0, %xmm0
 ; KNL_64-NEXT:    vpgatherqd 72(,%zmm1), %ymm0 {%k1}
 ; KNL_64-NEXT:    retq
 ;
 ; KNL_32-LABEL: test10:
 ; KNL_32:       # %bb.0: # %entry
 ; KNL_32-NEXT:    vpbroadcastd {{[0-9]+}}(%esp), %ymm2

llvm/test/CodeGen/X86/mul-constant-i64.ll

 ; X86-NEXT:    .cfi_def_cfa_offset 8
 ; X86-NEXT:    .cfi_offset %esi, -8
 ; X86-NEXT:    movl {{[0-9]+}}(%esp), %ecx
 ; X86-NEXT:    leal (%ecx,%ecx,8), %eax
 ; X86-NEXT:    leal (%eax,%eax,2), %esi
 ; X86-NEXT:    addl %ecx, %ecx
 ; X86-NEXT:    movl $29, %eax
 ; X86-NEXT:    mull {{[0-9]+}}(%esp)
-; X86-NEXT:    addl %ecx, %edx
 ; X86-NEXT:    addl %esi, %edx
+; X86-NEXT:    addl %ecx, %edx
 ; X86-NEXT:    popl %esi
 ; X86-NEXT:    .cfi_def_cfa_offset 4
 ; X86-NEXT:    retl
 ;
 ; X86-NOOPT-LABEL: test_mul_by_29:
 ; X86-NOOPT:       # %bb.0:
 ; X86-NOOPT-NEXT:    movl $29, %eax
 ; X86-NOOPT-NEXT:    mull {{[0-9]+}}(%esp)

llvm/test/CodeGen/X86/pr46877.ll

 ; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
 ; RUN: llc -O3 < %s -mcpu=haswell -mtriple=x86_64 | FileCheck %s
 
 ; Verify that we are not exponentially increasing compiling time.
 define void @tester(float %0, float %1, float %2, float %3, float %4, float %5, float %6, float %7, float %8, float %9, float %10, float %11, float %12, float %13, float %14, float %15, float %16, float %17, float %18, float %19, float %20, float %21, float %22, float %23, float %24, float %25, float %26, float %27, float %28, float %29, float %30, float %31, float %32, float %33, float %34, float %35, float %36, float %37, float %38, float %39, float %40, float %41, float %42, float %43, float %44, float %45, float %46, float %47, float %48, float %49, float %50, float %51, float %52, float %53, float %54, float %55, float %56, float %57, float %58, float %59, float %60, float %61, float %62, float %63, float %64, float %65, float %66, float %67, float %68, float %69, float %70, float %71, float %72, float %73, float %74, float %75, float %76, float %77, float %78, float %79, ptr %80) {
 ; CHECK-LABEL: tester:
 ; CHECK:       # %bb.0: # %entry
 ; CHECK-NEXT:    vmovaps %xmm3, %xmm15
 ; CHECK-NEXT:    vmovss {{.*#+}} xmm14 = mem[0],zero,zero,zero
 ; CHECK-NEXT:    vmovss {{.*#+}} xmm9 = mem[0],zero,zero,zero
 ; CHECK-NEXT:    vmovss {{.*#+}} xmm13 = mem[0],zero,zero,zero
 ; CHECK-NEXT:    vsubss %xmm1, %xmm0, %xmm12
 ; CHECK-NEXT:    vmulss %xmm2, %xmm1, %xmm10
 ; CHECK-NEXT:    vfmsub213ss {{.*#+}} xmm10 = (xmm3 * xmm10) - xmm0
 ; CHECK-NEXT:    vfnmadd213ss {{.*#+}} xmm5 = -(xmm12 * xmm5) + xmm0
-; CHECK-NEXT:    vmulss %xmm5, %xmm4, %xmm2
+; CHECK-NEXT:    vmulss %xmm4, %xmm5, %xmm2
 ; CHECK-NEXT:    vmulss %xmm2, %xmm10, %xmm4
 ; CHECK-NEXT:    vmulss %xmm6, %xmm12, %xmm2
 ; CHECK-NEXT:    vfnmadd213ss {{.*#+}} xmm2 = -(xmm7 * xmm2) + xmm0
 ; CHECK-NEXT:    vmulss %xmm4, %xmm2, %xmm5
 ; CHECK-NEXT:    vmulss %xmm0, %xmm13, %xmm2
 ; CHECK-NEXT:    vmovss %xmm2, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill
 ; CHECK-NEXT:    vmulss %xmm2, %xmm9, %xmm2
 ; CHECK-NEXT:    vfnmadd132ss {{.*#+}} xmm2 = -(xmm2 * mem) + xmm0
 ; CHECK-NEXT:    vmulss {{[0-9]+}}(%rsp), %xmm7, %xmm3
 ; CHECK-NEXT:    vfnmadd132ss {{.*#+}} xmm3 = -(xmm3 * mem) + xmm0
-; CHECK-NEXT:    vmulss %xmm3, %xmm2, %xmm2
+; CHECK-NEXT:    vmulss %xmm2, %xmm3, %xmm2
 ; CHECK-NEXT:    vmulss {{[0-9]+}}(%rsp), %xmm0, %xmm3
 ; CHECK-NEXT:    vmulss {{[0-9]+}}(%rsp), %xmm3, %xmm4
 ; CHECK-NEXT:    vfnmadd213ss {{.*#+}} xmm4 = -(xmm14 * xmm4) + xmm0
-; CHECK-NEXT:    vmulss %xmm4, %xmm5, %xmm4
+; CHECK-NEXT:    vmulss %xmm5, %xmm4, %xmm4
 ; CHECK-NEXT:    vmovss {{.*#+}} xmm5 = mem[0],zero,zero,zero
 ; CHECK-NEXT:    vfnmadd132ss {{.*#+}} xmm5 = -(xmm5 * mem) + xmm0
-; CHECK-NEXT:    vmulss %xmm5, %xmm2, %xmm2
+; CHECK-NEXT:    vmulss %xmm2, %xmm5, %xmm2
 ; CHECK-NEXT:    vmovss {{.*#+}} xmm7 = mem[0],zero,zero,zero
 ; CHECK-NEXT:    vmulss {{[0-9]+}}(%rsp), %xmm7, %xmm5
 ; CHECK-NEXT:    vfnmadd213ss {{.*#+}} xmm5 = -(xmm9 * xmm5) + xmm0
-; CHECK-NEXT:    vmulss %xmm5, %xmm4, %xmm4
+; CHECK-NEXT:    vmulss %xmm4, %xmm5, %xmm4
 ; CHECK-NEXT:    vmovss {{.*#+}} xmm5 = mem[0],zero,zero,zero
 ; CHECK-NEXT:    vmulss %xmm0, %xmm5, %xmm8
 ; CHECK-NEXT:    vmovss %xmm8, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill
 ; CHECK-NEXT:    vmovaps %xmm5, %xmm10
 ; CHECK-NEXT:    vmulss %xmm14, %xmm8, %xmm5
 ; CHECK-NEXT:    vfnmadd213ss {{.*#+}} xmm5 = -(xmm12 * xmm5) + xmm0
-; CHECK-NEXT:    vmulss %xmm5, %xmm2, %xmm2
+; CHECK-NEXT:    vmulss %xmm2, %xmm5, %xmm2
 ; CHECK-NEXT:    vmovss {{.*#+}} xmm5 = mem[0],zero,zero,zero
 ; CHECK-NEXT:    vfnmadd213ss {{.*#+}} xmm5 = -(xmm13 * xmm5) + xmm0
-; CHECK-NEXT:    vmulss %xmm5, %xmm4, %xmm4
+; CHECK-NEXT:    vmulss %xmm4, %xmm5, %xmm4
 ; CHECK-NEXT:    vmulss {{[0-9]+}}(%rsp), %xmm3, %xmm11
 ; CHECK-NEXT:    vmovss {{.*#+}} xmm3 = mem[0],zero,zero,zero
 ; CHECK-NEXT:    vfnmadd213ss {{.*#+}} xmm3 = -(xmm11 * xmm3) + xmm0
-; CHECK-NEXT:    vmulss %xmm3, %xmm2, %xmm2
-; CHECK-NEXT:    vmulss %xmm2, %xmm4, %xmm2
+; CHECK-NEXT:    vmulss %xmm2, %xmm3, %xmm2
+; CHECK-NEXT:    vmulss %xmm4, %xmm2, %xmm2
 ; CHECK-NEXT:    vmulss {{[0-9]+}}(%rsp), %xmm2, %xmm2
 ; CHECK-NEXT:    vmovss {{.*#+}} xmm3 = mem[0],zero,zero,zero
 ; CHECK-NEXT:    vfnmadd213ss {{.*#+}} xmm3 = -(xmm15 * xmm3) + xmm0
 ; CHECK-NEXT:    vmulss %xmm2, %xmm3, %xmm2
 ; CHECK-NEXT:    vmulss {{[0-9]+}}(%rsp), %xmm2, %xmm2
 ; CHECK-NEXT:    vmovss %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill
 ; CHECK-NEXT:    vmulss {{[0-9]+}}(%rsp), %xmm1, %xmm4
 ; CHECK-NEXT:    vfnmadd132ss {{.*#+}} xmm4 = -(xmm4 * mem) + xmm0
 ; CHECK-NEXT:    vmovss {{.*#+}} xmm8 = mem[0],zero,zero,zero
 ; CHECK-NEXT:    vmulss {{[0-9]+}}(%rsp), %xmm8, %xmm6
 ; CHECK-NEXT:    vfnmadd132ss {{.*#+}} xmm6 = -(xmm6 * mem) + xmm0
-; CHECK-NEXT:    vmulss %xmm6, %xmm4, %xmm4
-; CHECK-NEXT:    vmulss %xmm4, %xmm2, %xmm2
+; CHECK-NEXT:    vmulss %xmm4, %xmm6, %xmm4
+; CHECK-NEXT:    vmulss %xmm2, %xmm4, %xmm2
 ; CHECK-NEXT:    vmulss {{[0-9]+}}(%rsp), %xmm2, %xmm2
 ; CHECK-NEXT:    vmulss {{[0-9]+}}(%rsp), %xmm2, %xmm2
 ; CHECK-NEXT:    vmulss {{[0-9]+}}(%rsp), %xmm2, %xmm2
 ; CHECK-NEXT:    vmulss {{[0-9]+}}(%rsp), %xmm9, %xmm4
 ; CHECK-NEXT:    vfnmadd132ss {{.*#+}} xmm4 = -(xmm4 * mem) + xmm0
 ; CHECK-NEXT:    vmulss %xmm2, %xmm4, %xmm2
 ; CHECK-NEXT:    vmulss {{[0-9]+}}(%rsp), %xmm2, %xmm2
 ; CHECK-NEXT:    vmovss {{.*#+}} xmm4 = mem[0],zero,zero,zero
 ; CHECK-NEXT:    vfnmadd213ss {{.*#+}} xmm4 = -(xmm1 * xmm4) + xmm0
 ; CHECK-NEXT:    vmovss {{.*#+}} xmm6 = mem[0],zero,zero,zero
 ; CHECK-NEXT:    vfnmadd132ss {{.*#+}} xmm6 = -(xmm6 * mem) + xmm0
-; CHECK-NEXT:    vmulss %xmm6, %xmm4, %xmm4
-; CHECK-NEXT:    vmulss %xmm4, %xmm2, %xmm2
+; CHECK-NEXT:    vmulss %xmm4, %xmm6, %xmm4
+; CHECK-NEXT:    vmulss %xmm2, %xmm4, %xmm2
 ; CHECK-NEXT:    vmulss {{[0-9]+}}(%rsp), %xmm2, %xmm2
 ; CHECK-NEXT:    vmovss {{.*#+}} xmm4 = mem[0],zero,zero,zero
 ; CHECK-NEXT:    vmulss {{[0-9]+}}(%rsp), %xmm10, %xmm1
 ; CHECK-NEXT:    vmovss %xmm1, {{[-0-9]+}}(%r{{[sb]}}p) # 4-byte Spill
 ; CHECK-NEXT:    vfnmadd213ss {{.*#+}} xmm4 = -(xmm1 * xmm4) + xmm0
 ; CHECK-NEXT:    vmulss %xmm2, %xmm4, %xmm4
 ; CHECK-NEXT:    vmulss %xmm0, %xmm12, %xmm5
 ; CHECK-NEXT:    vmulss {{[0-9]+}}(%rsp), %xmm5, %xmm10
 ; CHECK-NEXT:    vfnmadd132ss {{.*#+}} xmm10 = -(xmm10 * mem) + xmm0
 ; CHECK-NEXT:    vmulss {{[0-9]+}}(%rsp), %xmm13, %xmm12
 ; CHECK-NEXT:    vfnmadd213ss {{.*#+}} xmm12 = -(xmm7 * xmm12) + xmm0
-; CHECK-NEXT:    vmulss %xmm12, %xmm10, %xmm10
+; CHECK-NEXT:    vmulss %xmm10, %xmm12, %xmm10
 ; CHECK-NEXT:    vmulss {{[0-9]+}}(%rsp), %xmm4, %xmm4
 ; CHECK-NEXT:    vmulss {{[0-9]+}}(%rsp), %xmm4, %xmm4
 ; CHECK-NEXT:    vmulss %xmm4, %xmm10, %xmm12
 ; CHECK-NEXT:    vmovss {{.*#+}} xmm2 = mem[0],zero,zero,zero
 ; CHECK-NEXT:    vfnmadd213ss {{.*#+}} xmm2 = -(xmm7 * xmm2) + xmm0
 ; CHECK-NEXT:    vmovss {{.*#+}} xmm3 = mem[0],zero,zero,zero
 ; CHECK-NEXT:    vmulss %xmm5, %xmm3, %xmm6
 ; CHECK-NEXT:    vfnmadd132ss {{.*#+}} xmm6 = -(xmm6 * mem) + xmm0
 ; CHECK-NEXT:    vmulss {{[0-9]+}}(%rsp), %xmm0, %xmm9
 ; CHECK-NEXT:    vmulss {{[0-9]+}}(%rsp), %xmm9, %xmm1
 ; CHECK-NEXT:    vfnmadd132ss {{.*#+}} xmm1 = -(xmm1 * mem) + xmm0
-; CHECK-NEXT:    vmulss %xmm6, %xmm2, %xmm2
+; CHECK-NEXT:    vmulss %xmm2, %xmm6, %xmm2
 ; CHECK-NEXT:    vmulss {{[0-9]+}}(%rsp), %xmm3, %xmm6
 ; CHECK-NEXT:    vfnmadd132ss {{.*#+}} xmm6 = -(xmm6 * mem) + xmm0
-; CHECK-NEXT:    vmulss %xmm1, %xmm2, %xmm1
-; CHECK-NEXT:    vmulss %xmm6, %xmm1, %xmm1
+; CHECK-NEXT:    vmulss %xmm2, %xmm1, %xmm1
+; CHECK-NEXT:    vmulss %xmm1, %xmm6, %xmm1
 ; CHECK-NEXT:    vmulss {{[0-9]+}}(%rsp), %xmm3, %xmm2
 ; CHECK-NEXT:    vfnmadd213ss {{.*#+}} xmm2 = -(xmm13 * xmm2) + xmm0
-; CHECK-NEXT:    vmulss %xmm2, %xmm1, %xmm1
+; CHECK-NEXT:    vmulss %xmm1, %xmm2, %xmm1
 ; CHECK-NEXT:    vmulss {{[0-9]+}}(%rsp), %xmm12, %xmm2
 ; CHECK-NEXT:    vmulss {{[0-9]+}}(%rsp), %xmm2, %xmm2
-; CHECK-NEXT:    vmulss %xmm1, %xmm2, %xmm4
+; CHECK-NEXT:    vmulss %xmm2, %xmm1, %xmm4
 ; CHECK-NEXT:    vmovss {{.*#+}} xmm12 = mem[0],zero,zero,zero
 ; CHECK-NEXT:    vmovss {{.*#+}} xmm6 = mem[0],zero,zero,zero
 ; CHECK-NEXT:    vmulss {{[0-9]+}}(%rsp), %xmm6, %xmm3
 ; CHECK-NEXT:    vfnmadd213ss {{.*#+}} xmm3 = -(xmm12 * xmm3) + xmm0
 ; CHECK-NEXT:    vmulss {{[0-9]+}}(%rsp), %xmm5, %xmm2
 ; CHECK-NEXT:    vfnmadd132ss {{.*#+}} xmm2 = -(xmm2 * mem) + xmm0
 ; CHECK-NEXT:    vmovss {{[-0-9]+}}(%r{{[sb]}}p), %xmm1 # 4-byte Reload
 ; CHECK-NEXT:    # xmm1 = mem[0],zero,zero,zero
 ; CHECK-NEXT:    vmulss {{[0-9]+}}(%rsp), %xmm1, %xmm1
-; CHECK-NEXT:    vmulss %xmm2, %xmm3, %xmm2
+; CHECK-NEXT:    vmulss %xmm3, %xmm2, %xmm2
 ; CHECK-NEXT:    vmovss {{.*#+}} xmm3 = mem[0],zero,zero,zero
 ; CHECK-NEXT:    vfnmadd213ss {{.*#+}} xmm1 = -(xmm3 * xmm1) + xmm0
-; CHECK-NEXT:    vmulss %xmm1, %xmm2, %xmm1
+; CHECK-NEXT:    vmulss %xmm2, %xmm1, %xmm1
 ; CHECK-NEXT:    vmulss {{[0-9]+}}(%rsp), %xmm4, %xmm2
 ; CHECK-NEXT:    vmulss {{[0-9]+}}(%rsp), %xmm2, %xmm2
-; CHECK-NEXT:    vmulss %xmm1, %xmm2, %xmm1
+; CHECK-NEXT:    vmulss %xmm2, %xmm1, %xmm1
 ; CHECK-NEXT:    vmovss {{[-0-9]+}}(%r{{[sb]}}p), %xmm10 # 4-byte Reload
 ; CHECK-NEXT:    # xmm10 = mem[0],zero,zero,zero
 ; CHECK-NEXT:    vmulss {{[0-9]+}}(%rsp), %xmm10, %xmm2
 ; CHECK-NEXT:    vfnmadd132ss {{.*#+}} xmm7 = -(xmm7 * mem) + xmm0
 ; CHECK-NEXT:    vfnmadd213ss {{.*#+}} xmm2 = -(xmm12 * xmm2) + xmm0
-; CHECK-NEXT:    vmulss %xmm7, %xmm2, %xmm2
+; CHECK-NEXT:    vmulss %xmm2, %xmm7, %xmm2
 ; CHECK-NEXT:    vmulss {{[0-9]+}}(%rsp), %xmm1, %xmm1
 ; CHECK-NEXT:    vmulss {{[0-9]+}}(%rsp), %xmm1, %xmm1
 ; CHECK-NEXT:    vfnmadd132ss {{.*#+}} xmm8 = -(xmm8 * mem) + xmm0
 ; CHECK-NEXT:    vmulss %xmm2, %xmm8, %xmm2
-; CHECK-NEXT:    vmulss %xmm2, %xmm1, %xmm1
+; CHECK-NEXT:    vmulss %xmm1, %xmm2, %xmm1
 ; CHECK-NEXT:    vmulss {{[0-9]+}}(%rsp), %xmm1, %xmm1
 ; CHECK-NEXT:    vmovss {{.*#+}} xmm2 = mem[0],zero,zero,zero
 ; CHECK-NEXT:    vfnmadd213ss {{.*#+}} xmm2 = -(xmm15 * xmm2) + xmm0
 ; CHECK-NEXT:    vmulss %xmm1, %xmm2, %xmm1
 ; CHECK-NEXT:    vmulss %xmm0, %xmm6, %xmm2
 ; CHECK-NEXT:    vmulss %xmm3, %xmm2, %xmm2
 ; CHECK-NEXT:    vfnmadd132ss {{.*#+}} xmm2 = -(xmm2 * mem) + xmm0
 ; CHECK-NEXT:    vmovss {{.*#+}} xmm3 = mem[0],zero,zero,zero
 ; CHECK-NEXT:    vfnmadd213ss {{.*#+}} xmm3 = -(xmm6 * xmm3) + xmm0
-; CHECK-NEXT:    vmulss %xmm2, %xmm3, %xmm2
+; CHECK-NEXT:    vmulss %xmm3, %xmm2, %xmm2
 ; CHECK-NEXT:    vmulss {{[0-9]+}}(%rsp), %xmm9, %xmm3
 ; CHECK-NEXT:    vmulss {{[0-9]+}}(%rsp), %xmm9, %xmm4
 ; CHECK-NEXT:    vfnmadd132ss {{.*#+}} xmm4 = -(xmm4 * mem) + xmm0
-; CHECK-NEXT:    vmulss %xmm4, %xmm2, %xmm2
+; CHECK-NEXT:    vmulss %xmm2, %xmm4, %xmm2
 ; CHECK-NEXT:    vmulss {{[0-9]+}}(%rsp), %xmm1, %xmm1
-; CHECK-NEXT:    vmulss %xmm2, %xmm1, %xmm1
+; CHECK-NEXT:    vmulss %xmm1, %xmm2, %xmm1
 ; CHECK-NEXT:    vfnmadd213ss {{.*#+}} xmm11 = -(xmm6 * xmm11) + xmm0
 ; CHECK-NEXT:    vmulss {{[0-9]+}}(%rsp), %xmm5, %xmm2
 ; CHECK-NEXT:    vfnmadd213ss {{.*#+}} xmm2 = -(xmm15 * xmm2) + xmm0
 ; CHECK-NEXT:    vmovss {{.*#+}} xmm4 = mem[0],zero,zero,zero
 ; CHECK-NEXT:    vmulss {{[0-9]+}}(%rsp), %xmm4, %xmm4
 ; CHECK-NEXT:    vfnmadd132ss {{.*#+}} xmm4 = -(xmm4 * mem) + xmm0
 ; CHECK-NEXT:    vmulss %xmm2, %xmm11, %xmm2
-; CHECK-NEXT:    vmulss %xmm4, %xmm2, %xmm2
+; CHECK-NEXT:    vmulss %xmm2, %xmm4, %xmm2
 ; CHECK-NEXT:    vfnmadd132ss {{[-0-9]+}}(%r{{[sb]}}p), %xmm0, %xmm14 # 4-byte Folded Reload
 ; CHECK-NEXT:    # xmm14 = -(xmm14 * mem) + xmm0
 ; CHECK-NEXT:    vmulss %xmm2, %xmm14, %xmm4
 ; CHECK-NEXT:    vmulss {{[0-9]+}}(%rsp), %xmm0, %xmm2
 ; CHECK-NEXT:    vmulss {{[0-9]+}}(%rsp), %xmm2, %xmm2
 ; CHECK-NEXT:    vfnmadd132ss {{.*#+}} xmm2 = -(xmm2 * mem) + xmm0
 ; CHECK-NEXT:    vmovss {{.*#+}} xmm6 = mem[0],zero,zero,zero
 ; CHECK-NEXT:    vmulss %xmm6, %xmm13, %xmm7

 ; CHECK-NEXT:    vmulss {{[0-9]+}}(%rsp), %xmm10, %xmm10
 ; CHECK-NEXT:    vmulss %xmm0, %xmm12, %xmm11
 ; CHECK-NEXT:    vmulss {{[0-9]+}}(%rsp), %xmm11, %xmm11
 ; CHECK-NEXT:    vmovss {{.*#+}} xmm12 = mem[0],zero,zero,zero
 ; CHECK-NEXT:    vfnmadd213ss {{.*#+}} xmm11 = -(xmm12 * xmm11) + xmm0
 ; CHECK-NEXT:    vfnmadd213ss {{.*#+}} xmm10 = -(xmm12 * xmm10) + xmm0
 ; CHECK-NEXT:    vfmsub213ss {{.*#+}} xmm8 = (xmm15 * xmm8) - xmm0
 ; CHECK-NEXT:    vfnmadd132ss {{.*#+}} xmm3 = -(xmm3 * mem) + xmm0
-; CHECK-NEXT:    vmulss %xmm3, %xmm4, %xmm0
-; CHECK-NEXT:    vmulss %xmm5, %xmm0, %xmm0
+; CHECK-NEXT:    vmulss %xmm4, %xmm3, %xmm0
+; CHECK-NEXT:    vmulss %xmm0, %xmm5, %xmm0
 ; CHECK-NEXT:    vmulss %xmm0, %xmm9, %xmm0
-; CHECK-NEXT:    vmulss %xmm7, %xmm0, %xmm0
+; CHECK-NEXT:    vmulss %xmm0, %xmm7, %xmm0
 ; CHECK-NEXT:    vmulss {{[0-9]+}}(%rsp), %xmm1, %xmm1
-; CHECK-NEXT:    vmulss %xmm0, %xmm1, %xmm0
-; CHECK-NEXT:    vmulss %xmm6, %xmm2, %xmm1
+; CHECK-NEXT:    vmulss %xmm1, %xmm0, %xmm0
+; CHECK-NEXT:    vmulss %xmm2, %xmm6, %xmm1
 ; CHECK-NEXT:    vmulss %xmm1, %xmm11, %xmm1
 ; CHECK-NEXT:    vmulss %xmm1, %xmm10, %xmm1
 ; CHECK-NEXT:    vmulss {{[0-9]+}}(%rsp), %xmm0, %xmm0
 ; CHECK-NEXT:    vmulss %xmm1, %xmm8, %xmm1
-; CHECK-NEXT:    vmulss %xmm1, %xmm0, %xmm0
+; CHECK-NEXT:    vmulss %xmm0, %xmm1, %xmm0
 ; CHECK-NEXT:    vmovss %xmm0, (%rdi)
 ; CHECK-NEXT:    retq
 entry:
   %81 = fsub reassoc nsz contract float %0, %1
   %82 = fmul reassoc nsz contract float %1, %2
   %83 = fmul reassoc nsz contract float %3, %82
   %84 = fsub reassoc nsz contract float %0, %83
   %85 = fmul reassoc nsz contract float %84, %4

llvm/test/CodeGen/X86/sqrt-fastmath.ll

 ; AVX1:       # %bb.0:
 ; AVX1-NEXT:    vmulss %xmm1, %xmm1, %xmm1
 ; AVX1-NEXT:    vmulss %xmm2, %xmm1, %xmm1
 ; AVX1-NEXT:    vrsqrtss %xmm1, %xmm1, %xmm2
 ; AVX1-NEXT:    vmulss %xmm2, %xmm1, %xmm1
 ; AVX1-NEXT:    vmulss %xmm2, %xmm1, %xmm1
 ; AVX1-NEXT:    vaddss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
 ; AVX1-NEXT:    vmulss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2
-; AVX1-NEXT:    vmulss %xmm0, %xmm2, %xmm0
-; AVX1-NEXT:    vmulss %xmm0, %xmm1, %xmm0
+; AVX1-NEXT:    vmulss %xmm2, %xmm0, %xmm0
+; AVX1-NEXT:    vmulss %xmm1, %xmm0, %xmm0
 ; AVX1-NEXT:    retq
 ;
 ; AVX512-LABEL: div_sqrt_fabs_f32:
 ; AVX512:       # %bb.0:
 ; AVX512-NEXT:    vmulss %xmm1, %xmm1, %xmm1
 ; AVX512-NEXT:    vmulss %xmm2, %xmm1, %xmm1
 ; AVX512-NEXT:    vrsqrtss %xmm1, %xmm1, %xmm2
 ; AVX512-NEXT:    vmulss %xmm2, %xmm1, %xmm1
 ; AVX512-NEXT:    vfmadd213ss {{.*#+}} xmm1 = (xmm2 * xmm1) + mem
 ; AVX512-NEXT:    vmulss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2
-; AVX512-NEXT:    vmulss %xmm0, %xmm2, %xmm0
-; AVX512-NEXT:    vmulss %xmm0, %xmm1, %xmm0
+; AVX512-NEXT:    vmulss %xmm2, %xmm0, %xmm0
+; AVX512-NEXT:    vmulss %xmm1, %xmm0, %xmm0
 ; AVX512-NEXT:    retq
   %s = call fast float @llvm.sqrt.f32(float %z)
   %a = call fast float @llvm.fabs.f32(float %y)
   %m = fmul fast float %s, %a
   %d = fdiv fast float %x, %m
   ret float %d
 }
 

 ; AVX1:       # %bb.0:
 ; AVX1-NEXT:    vmulss %xmm1, %xmm1, %xmm2
 ; AVX1-NEXT:    vmulss %xmm1, %xmm2, %xmm1
 ; AVX1-NEXT:    vrsqrtss %xmm1, %xmm1, %xmm2
 ; AVX1-NEXT:    vmulss %xmm2, %xmm1, %xmm1
 ; AVX1-NEXT:    vmulss %xmm2, %xmm1, %xmm1
 ; AVX1-NEXT:    vaddss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm1, %xmm1
 ; AVX1-NEXT:    vmulss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2
-; AVX1-NEXT:    vmulss %xmm0, %xmm2, %xmm0
-; AVX1-NEXT:    vmulss %xmm0, %xmm1, %xmm0
+; AVX1-NEXT:    vmulss %xmm2, %xmm0, %xmm0
+; AVX1-NEXT:    vmulss %xmm1, %xmm0, %xmm0
 ; AVX1-NEXT:    retq
 ;
 ; AVX512-LABEL: div_sqrt_f32:
 ; AVX512:       # %bb.0:
 ; AVX512-NEXT:    vmulss %xmm1, %xmm1, %xmm2
 ; AVX512-NEXT:    vmulss %xmm1, %xmm2, %xmm1
 ; AVX512-NEXT:    vrsqrtss %xmm1, %xmm1, %xmm2
 ; AVX512-NEXT:    vmulss %xmm2, %xmm1, %xmm1
 ; AVX512-NEXT:    vfmadd213ss {{.*#+}} xmm1 = (xmm2 * xmm1) + mem
 ; AVX512-NEXT:    vmulss {{\.?LCPI[0-9]+_[0-9]+}}(%rip), %xmm2, %xmm2
-; AVX512-NEXT:    vmulss %xmm0, %xmm2, %xmm0
-; AVX512-NEXT:    vmulss %xmm0, %xmm1, %xmm0
+; AVX512-NEXT:    vmulss %xmm2, %xmm0, %xmm0
+; AVX512-NEXT:    vmulss %xmm1, %xmm0, %xmm0
 ; AVX512-NEXT:    retq
   %s = call fast float @llvm.sqrt.f32(float %y)
   %m = fmul fast float %s, %y
   %d = fdiv fast float %x, %m
   ret float %d
 }
 
 ; This is a special case for the general pattern above -

llvm/test/CodeGen/X86/umulo-128-legalisation-lowering.ll

 ; X86-NEXT:    movl %esi, 4(%ecx)
 ; X86-NEXT:    movl {{[-0-9]+}}(%e{{[sb]}}p), %esi # 4-byte Reload
 ; X86-NEXT:    movl %esi, (%ecx)
 ; X86-NEXT:    movl %eax, 8(%ecx)
 ; X86-NEXT:    movl %edx, 12(%ecx)
 ; X86-NEXT:    setne %al
 ; X86-NEXT:    andb %bl, %al
 ; X86-NEXT:    orb {{[-0-9]+}}(%e{{[sb]}}p), %al # 1-byte Folded Reload
-; X86-NEXT:    orb {{[-0-9]+}}(%e{{[sb]}}p), %al # 1-byte Folded Reload
-; X86-NEXT:    orb {{[-0-9]+}}(%e{{[sb]}}p), %al # 1-byte Folded Reload
-; X86-NEXT:    orb %bh, %al
-; X86-NEXT:    andb $1, %al
-; X86-NEXT:    movb %al, 16(%ecx)
+; X86-NEXT:    orb {{[-0-9]+}}(%e{{[sb]}}p), %bh # 1-byte Folded Reload
+; X86-NEXT:    orb {{[-0-9]+}}(%e{{[sb]}}p), %bh # 1-byte Folded Reload
+; X86-NEXT:    orb %al, %bh
+; X86-NEXT:    andb $1, %bh
+; X86-NEXT:    movb %bh, 16(%ecx)
 ; X86-NEXT:    movl %ecx, %eax
 ; X86-NEXT:    addl $24, %esp
 ; X86-NEXT:    .cfi_def_cfa_offset 20
 ; X86-NEXT:    popl %esi
 ; X86-NEXT:    .cfi_def_cfa_offset 16
 ; X86-NEXT:    popl %edi
 ; X86-NEXT:    .cfi_def_cfa_offset 12
 ; X86-NEXT:    popl %ebx

llvm/test/CodeGen/X86/x86-interleaved-access.ll

 ; AVX1-NEXT:    vandnps %ymm2, %ymm5, %ymm2
 ; AVX1-NEXT:    vandps %ymm5, %ymm8, %ymm5
 ; AVX1-NEXT:    vorps %ymm2, %ymm5, %ymm2
 ; AVX1-NEXT:    vpalignr {{.*#+}} xmm3 = xmm3[11,12,13,14,15],xmm6[0,1,2,3,4,5,6,7,8,9,10]
 ; AVX1-NEXT:    vpalignr {{.*#+}} xmm3 = xmm3[10,11,12,13,14,15,0,1,2,3,4,5,6,7,8,9]
 ; AVX1-NEXT:    vpalignr {{.*#+}} xmm0 = xmm0[11,12,13,14,15],xmm7[0,1,2,3,4,5,6,7,8,9,10]
 ; AVX1-NEXT:    vpalignr {{.*#+}} xmm0 = xmm0[10,11,12,13,14,15,0,1,2,3,4,5,6,7,8,9]
 ; AVX1-NEXT:    vextractf128 $1, %ymm2, %xmm5
-; AVX1-NEXT:    vpaddb %xmm4, %xmm5, %xmm4
-; AVX1-NEXT:    vpaddb %xmm4, %xmm3, %xmm3
-; AVX1-NEXT:    vpaddb %xmm1, %xmm2, %xmm1
-; AVX1-NEXT:    vpaddb %xmm1, %xmm0, %xmm0
+; AVX1-NEXT:    vpaddb %xmm5, %xmm4, %xmm4
+; AVX1-NEXT:    vpaddb %xmm3, %xmm4, %xmm3
+; AVX1-NEXT:    vpaddb %xmm2, %xmm1, %xmm1
+; AVX1-NEXT:    vpaddb %xmm0, %xmm1, %xmm0
 ; AVX1-NEXT:    vinsertf128 $1, %xmm3, %ymm0, %ymm0
 ; AVX1-NEXT:    retq
 ;
 ; AVX2OR512-LABEL: interleaved_load_vf32_i8_stride3:
 ; AVX2OR512:       # %bb.0:
 ; AVX2OR512-NEXT:    vmovdqa (%rdi), %xmm0
 ; AVX2OR512-NEXT:    vmovdqa 16(%rdi), %xmm1
 ; AVX2OR512-NEXT:    vmovdqa 32(%rdi), %xmm2
 ; AVX2OR512-NEXT:    vinserti128 $1, 48(%rdi), %ymm0, %ymm0
 ; AVX2OR512-NEXT:    vinserti128 $1, 64(%rdi), %ymm1, %ymm1
 ; AVX2OR512-NEXT:    vinserti128 $1, 80(%rdi), %ymm2, %ymm2
 ; AVX2OR512-NEXT:    vmovdqa {{.*#+}} ymm3 = [0,3,6,9,12,15,2,5,8,11,14,1,4,7,10,13,0,3,6,9,12,15,2,5,8,11,14,1,4,7,10,13]
 ; AVX2OR512-NEXT:    vpshufb %ymm3, %ymm0, %ymm0
 ; AVX2OR512-NEXT:    vpshufb %ymm3, %ymm1, %ymm1
 ; AVX2OR512-NEXT:    vpshufb %ymm3, %ymm2, %ymm2
 ; AVX2OR512-NEXT:    vpalignr {{.*#+}} ymm3 = ymm2[11,12,13,14,15],ymm0[0,1,2,3,4,5,6,7,8,9,10],ymm2[27,28,29,30,31],ymm0[16,17,18,19,20,21,22,23,24,25,26]
 ; AVX2OR512-NEXT:    vpalignr {{.*#+}} ymm0 = ymm0[11,12,13,14,15],ymm1[0,1,2,3,4,5,6,7,8,9,10],ymm0[27,28,29,30,31],ymm1[16,17,18,19,20,21,22,23,24,25,26]
 ; AVX2OR512-NEXT:    vpalignr {{.*#+}} ymm1 = ymm1[11,12,13,14,15],ymm2[0,1,2,3,4,5,6,7,8,9,10],ymm1[27,28,29,30,31],ymm2[16,17,18,19,20,21,22,23,24,25,26]
 ; AVX2OR512-NEXT:    vpalignr {{.*#+}} ymm2 = ymm3[11,12,13,14,15],ymm1[0,1,2,3,4,5,6,7,8,9,10],ymm3[27,28,29,30,31],ymm1[16,17,18,19,20,21,22,23,24,25,26]
 ; AVX2OR512-NEXT:    vmovdqa {{.*#+}} ymm4 = [255,255,255,255,255,255,255,255,255,255,255,0,0,0,0,0,255,255,255,255,255,255,255,255,255,255,255,0,0,0,0,0]
 ; AVX2OR512-NEXT:    vpblendvb %ymm4, %ymm0, %ymm1, %ymm1
-; AVX2OR512-NEXT:    vpaddb %ymm2, %ymm1, %ymm1
+; AVX2OR512-NEXT:    vpaddb %ymm1, %ymm2, %ymm1
 ; AVX2OR512-NEXT:    vpalignr {{.*#+}} ymm0 = ymm0[11,12,13,14,15],ymm3[0,1,2,3,4,5,6,7,8,9,10],ymm0[27,28,29,30,31],ymm3[16,17,18,19,20,21,22,23,24,25,26]
 ; AVX2OR512-NEXT:    vpalignr {{.*#+}} ymm0 = ymm0[10,11,12,13,14,15,0,1,2,3,4,5,6,7,8,9,26,27,28,29,30,31,16,17,18,19,20,21,22,23,24,25]
-; AVX2OR512-NEXT:    vpaddb %ymm1, %ymm0, %ymm0
+; AVX2OR512-NEXT:    vpaddb %ymm0, %ymm1, %ymm0
 ; AVX2OR512-NEXT:    retq
   %wide.vec = load <96 x i8>, ptr %ptr
   %v1 = shufflevector <96 x i8> %wide.vec, <96 x i8> undef,<32 x i32> <i32 0,i32 3,i32 6,i32 9,i32 12,i32 15,i32 18,i32 21,i32 24,i32 27,i32 30,i32 33,i32 36,i32 39,i32 42,i32 45,i32 48,i32 51,i32 54,i32 57,i32 60,i32 63,i32 66,i32 69,i32 72,i32 75,i32 78,i32 81,i32 84,i32 87,i32 90,i32 93>
   %v2 = shufflevector <96 x i8> %wide.vec, <96 x i8> undef,<32 x i32> <i32 1,i32 4,i32 7,i32 10,i32 13,i32 16,i32 19,i32 22,i32 25,i32 28,i32 31,i32 34,i32 37,i32 40,i32 43,i32 46,i32 49,i32 52,i32 55,i32 58,i32 61,i32 64,i32 67,i32 70,i32 73,i32 76,i32 79,i32 82,i32 85,i32 88,i32 91,i32 94>
   %v3 = shufflevector <96 x i8> %wide.vec, <96 x i8> undef,<32 x i32> <i32 2,i32 5,i32 8,i32 11,i32 14,i32 17,i32 20,i32 23,i32 26,i32 29,i32 32,i32 35,i32 38,i32 41,i32 44,i32 47,i32 50,i32 53,i32 56,i32 59,i32 62,i32 65,i32 68,i32 71,i32 74,i32 77,i32 80,i32 83,i32 86,i32 89,i32 92,i32 95>
   %add1 = add <32 x i8> %v1, %v2
   %add2 = add <32 x i8> %v3, %add1
   ret <32 x i8> %add2

 ; AVX-NEXT:    vpshufb %xmm3, %xmm1, %xmm1
 ; AVX-NEXT:    vpshufb %xmm3, %xmm2, %xmm2
 ; AVX-NEXT:    vpalignr {{.*#+}} xmm3 = xmm2[11,12,13,14,15],xmm0[0,1,2,3,4,5,6,7,8,9,10]
 ; AVX-NEXT:    vpalignr {{.*#+}} xmm0 = xmm0[11,12,13,14,15],xmm1[0,1,2,3,4,5,6,7,8,9,10]
 ; AVX-NEXT:    vpalignr {{.*#+}} xmm1 = xmm1[11,12,13,14,15],xmm2[0,1,2,3,4,5,6,7,8,9,10]
 ; AVX-NEXT:    vpalignr {{.*#+}} xmm2 = xmm3[11,12,13,14,15],xmm1[0,1,2,3,4,5,6,7,8,9,10]
 ; AVX-NEXT:    vmovdqa {{.*#+}} xmm4 = [255,255,255,255,255,255,255,255,255,255,255,0,0,0,0,0]
 ; AVX-NEXT:    vpblendvb %xmm4, %xmm0, %xmm1, %xmm1
-; AVX-NEXT:    vpaddb %xmm2, %xmm1, %xmm1
+; AVX-NEXT:    vpaddb %xmm1, %xmm2, %xmm1
 ; AVX-NEXT:    vpalignr {{.*#+}} xmm0 = xmm0[11,12,13,14,15],xmm3[0,1,2,3,4,5,6,7,8,9,10]
 ; AVX-NEXT:    vpalignr {{.*#+}} xmm0 = xmm0[10,11,12,13,14,15,0,1,2,3,4,5,6,7,8,9]
-; AVX-NEXT:    vpaddb %xmm1, %xmm0, %xmm0
+; AVX-NEXT:    vpaddb %xmm0, %xmm1, %xmm0
 ; AVX-NEXT:    retq
   %wide.vec = load <48 x i8>, ptr %ptr
   %v1 = shufflevector <48 x i8> %wide.vec, <48 x i8> undef,<16 x i32> <i32 0,i32 3,i32 6,i32 9,i32 12,i32 15,i32 18,i32 21,i32 24,i32 27,i32 30,i32 33,i32 36,i32 39,i32 42 ,i32 45>
   %v2 = shufflevector <48 x i8> %wide.vec, <48 x i8> undef,<16 x i32> <i32 1,i32 4,i32 7,i32 10,i32 13,i32 16,i32 19,i32 22,i32 25,i32 28,i32 31,i32 34,i32 37,i32 40,i32 43,i32 46>
   %v3 = shufflevector <48 x i8> %wide.vec, <48 x i8> undef,<16 x i32> <i32 2,i32 5,i32 8,i32 11,i32 14,i32 17,i32 20,i32 23,i32 26,i32 29,i32 32,i32 35,i32 38,i32 41,i32 44,i32 47>
   %add1 = add <16 x i8> %v1, %v2
   %add2 = add <16 x i8> %v3, %add1
   ret <16 x i8> %add2
 }
 
 define <8 x i8> @interleaved_load_vf8_i8_stride3(ptr %ptr){
 ; AVX-LABEL: interleaved_load_vf8_i8_stride3:
 ; AVX:       # %bb.0:
 ; AVX-NEXT:    vmovdqa (%rdi), %xmm0
 ; AVX-NEXT:    vmovdqa 16(%rdi), %xmm1
 ; AVX-NEXT:    vpshufb {{.*#+}} xmm2 = zero,zero,zero,zero,zero,zero,xmm1[2,5,u,u,u,u,u,u,u,u]
 ; AVX-NEXT:    vpshufb {{.*#+}} xmm3 = xmm0[0,3,6,9,12,15],zero,zero,xmm0[u,u,u,u,u,u,u,u]
 ; AVX-NEXT:    vpor %xmm2, %xmm3, %xmm2
 ; AVX-NEXT:    vpshufb {{.*#+}} xmm3 = zero,zero,zero,zero,zero,xmm1[0,3,6,u,u,u,u,u,u,u,u]
 ; AVX-NEXT:    vpshufb {{.*#+}} xmm4 = xmm0[1,4,7,10,13],zero,zero,zero,xmm0[u,u,u,u,u,u,u,u]
 ; AVX-NEXT:    vpor %xmm3, %xmm4, %xmm3
 ; AVX-NEXT:    vpshufb {{.*#+}} xmm1 = zero,zero,zero,zero,zero,xmm1[1,4,7,u,u,u,u,u,u,u,u]
 ; AVX-NEXT:    vpshufb {{.*#+}} xmm0 = xmm0[2,5,8,11,14],zero,zero,zero,xmm0[u,u,u,u,u,u,u,u]
 ; AVX-NEXT:    vpor %xmm1, %xmm0, %xmm0
-; AVX-NEXT:    vpaddb %xmm0, %xmm3, %xmm0
-; AVX-NEXT:    vpaddb %xmm0, %xmm2, %xmm0
+; AVX-NEXT:    vpaddb %xmm3, %xmm0, %xmm0
+; AVX-NEXT:    vpaddb %xmm2, %xmm0, %xmm0
 ; AVX-NEXT:    retq
   %wide.vec = load <24 x i8>, ptr %ptr
   %v1 = shufflevector <24 x i8> %wide.vec, <24 x i8> undef,<8 x i32> <i32 0,i32 3,i32 6,i32  9,i32 12,i32 15,i32 18,i32 21>
   %v2 = shufflevector <24 x i8> %wide.vec, <24 x i8> undef,<8 x i32> <i32 1,i32 4,i32 7,i32 10,i32 13,i32 16,i32 19,i32 22>
   %v3 = shufflevector <24 x i8> %wide.vec, <24 x i8> undef,<8 x i32> <i32 2,i32 5,i32 8,i32 11,i32 14,i32 17,i32 20,i32 23>
   %add1 = add <8 x i8> %v1, %v2
   %add2 = add <8 x i8> %v3, %add1
   ret <8 x i8> %add2

 ; AVX1-NEXT:    vpshufb %xmm0, %xmm4, %xmm0
 ; AVX1-NEXT:    vpor %xmm0, %xmm11, %xmm0
 ; AVX1-NEXT:    vpalignr {{.*#+}} xmm5 = xmm11[11,12,13,14,15],xmm5[0,1,2,3,4,5,6,7,8,9,10]
 ; AVX1-NEXT:    vmovdqa {{.*#+}} xmm9 = [0,1,2,3,4,5,6,7,8,9,10,128,128,128,128,128]
 ; AVX1-NEXT:    vpshufb %xmm9, %xmm10, %xmm10
 ; AVX1-NEXT:    vmovdqa {{.*#+}} xmm11 = [128,128,128,128,128,128,128,128,128,128,128,2,5,8,11,14]
 ; AVX1-NEXT:    vpshufb %xmm11, %xmm4, %xmm4
 ; AVX1-NEXT:    vpor %xmm4, %xmm10, %xmm4
-; AVX1-NEXT:    vpaddb %xmm5, %xmm4, %xmm4
+; AVX1-NEXT:    vpaddb %xmm4, %xmm5, %xmm4
 ; AVX1-NEXT:    vmovdqa {{[-0-9]+}}(%r{{[sb]}}p), %xmm3 # 16-byte Reload
 ; AVX1-NEXT:    vpshufb %xmm9, %xmm3, %xmm5
 ; AVX1-NEXT:    vpshufb %xmm11, %xmm8, %xmm8
 ; AVX1-NEXT:    vpor %xmm5, %xmm8, %xmm5
-; AVX1-NEXT:    vpaddb %xmm2, %xmm5, %xmm2
+; AVX1-NEXT:    vpaddb %xmm5, %xmm2, %xmm2
 ; AVX1-NEXT:    vmovdqa {{[-0-9]+}}(%r{{[sb]}}p), %xmm3 # 16-byte Reload
 ; AVX1-NEXT:    vpshufb %xmm9, %xmm3, %xmm5
 ; AVX1-NEXT:    vpshufb %xmm11, %xmm12, %xmm8
 ; AVX1-NEXT:    vpor %xmm5, %xmm8, %xmm5
-; AVX1-NEXT:    vpaddb %xmm1, %xmm5, %xmm1
+; AVX1-NEXT:    vpaddb %xmm5, %xmm1, %xmm1
 ; AVX1-NEXT:    vmovdqa {{[-0-9]+}}(%r{{[sb]}}p), %xmm3 # 16-byte Reload
 ; AVX1-NEXT:    vpshufb %xmm9, %xmm3, %xmm5
 ; AVX1-NEXT:    vpshufb %xmm11, %xmm15, %xmm8
 ; AVX1-NEXT:    vpor %xmm5, %xmm8, %xmm5
-; AVX1-NEXT:    vpaddb %xmm6, %xmm5, %xmm5
+; AVX1-NEXT:    vpaddb %xmm5, %xmm6, %xmm5
 ; AVX1-NEXT:    vmovdqa {{.*#+}} xmm6 = [5,6,7,8,9,10,128,128,128,128,128,0,1,2,3,4]
 ; AVX1-NEXT:    vpshufb %xmm6, %xmm0, %xmm0
 ; AVX1-NEXT:    vmovdqa {{.*#+}} xmm8 = [128,128,128,128,128,128,2,5,8,11,14,128,128,128,128,128]
 ; AVX1-NEXT:    vmovdqa {{[-0-9]+}}(%r{{[sb]}}p), %xmm3 # 16-byte Reload
 ; AVX1-NEXT:    vpshufb %xmm8, %xmm3, %xmm3
 ; AVX1-NEXT:    vpor %xmm3, %xmm0, %xmm0
-; AVX1-NEXT:    vpaddb %xmm4, %xmm0, %xmm0
+; AVX1-NEXT:    vpaddb %xmm0, %xmm4, %xmm0
 ; AVX1-NEXT:    vpshufb %xmm6, %xmm7, %xmm3
 ; AVX1-NEXT:    vmovdqa {{[-0-9]+}}(%r{{[sb]}}p), %xmm4 # 16-byte Reload
 ; AVX1-NEXT:    vpshufb %xmm8, %xmm4, %xmm4
 ; AVX1-NEXT:    vpor %xmm4, %xmm3, %xmm3
-; AVX1-NEXT:    vpaddb %xmm2, %xmm3, %xmm2
+; AVX1-NEXT:    vpaddb %xmm3, %xmm2, %xmm2
 ; AVX1-NEXT:    vpshufb %xmm6, %xmm14, %xmm3
 ; AVX1-NEXT:    vmovdqa {{[-0-9]+}}(%r{{[sb]}}p), %xmm4 # 16-byte Reload
 ; AVX1-NEXT:    vpshufb %xmm8, %xmm4, %xmm4
 ; AVX1-NEXT:    vpor %xmm4, %xmm3, %xmm3
-; AVX1-NEXT:    vpaddb %xmm1, %xmm3, %xmm1
+; AVX1-NEXT:    vpaddb %xmm3, %xmm1, %xmm1
 ; AVX1-NEXT:    vpshufb %xmm6, %xmm13, %xmm3
 ; AVX1-NEXT:    vmovdqa {{[-0-9]+}}(%r{{[sb]}}p), %xmm4 # 16-byte Reload
 ; AVX1-NEXT:    vpshufb %xmm8, %xmm4, %xmm4
 ; AVX1-NEXT:    vpor %xmm4, %xmm3, %xmm3
-; AVX1-NEXT:    vpaddb %xmm5, %xmm3, %xmm3
+; AVX1-NEXT:    vpaddb %xmm3, %xmm5, %xmm3
 ; AVX1-NEXT:    vinsertf128 $1, %xmm0, %ymm2, %ymm0
 ; AVX1-NEXT:    vinsertf128 $1, %xmm1, %ymm3, %ymm1
 ; AVX1-NEXT:    retq
 ;
 ; AVX2-LABEL: interleaved_load_vf64_i8_stride3:
 ; AVX2:       # %bb.0:
 ; AVX2-NEXT:    vmovdqu (%rdi), %xmm0
 ; AVX2-NEXT:    vmovdqu 16(%rdi), %xmm1

 ; AVX2-NEXT:    vpor %ymm4, %ymm3, %ymm3
 ; AVX2-NEXT:    vpaddb %ymm3, %ymm8, %ymm3
 ; AVX2-NEXT:    vpalignr {{.*#+}} ymm4 = ymm7[5,6,7,8,9,10,11,12,13,14,15,0,1,2,3,4,21,22,23,24,25,26,27,28,29,30,31,16,17,18,19,20]
 ; AVX2-NEXT:    vmovdqa {{.*#+}} ymm6 = <u,u,u,u,u,u,2,5,8,11,14,u,u,u,u,u,u,u,u,u,u,u,2,5,8,11,14,u,u,u,u,u>
 ; AVX2-NEXT:    vpshufb %ymm6, %ymm0, %ymm0
 ; AVX2-NEXT:    vbroadcasti128 {{.*#+}} ymm7 = [255,255,255,255,255,255,0,0,0,0,0,255,255,255,255,255,255,255,255,255,255,255,0,0,0,0,0,255,255,255,255,255]
 ; AVX2-NEXT:    # ymm7 = mem[0,1,0,1]
 ; AVX2-NEXT:    vpblendvb %ymm7, %ymm4, %ymm0, %ymm0
-; AVX2-NEXT:    vpaddb %ymm2, %ymm0, %ymm0
+; AVX2-NEXT:    vpaddb %ymm0, %ymm2, %ymm0
 ; AVX2-NEXT:    vpalignr {{.*#+}} ymm2 = ymm5[5,6,7,8,9,10,11,12,13,14,15,0,1,2,3,4,21,22,23,24,25,26,27,28,29,30,31,16,17,18,19,20]
 ; AVX2-NEXT:    vpshufb %ymm6, %ymm1, %ymm1
 ; AVX2-NEXT:    vpblendvb %ymm7, %ymm2, %ymm1, %ymm1
-; AVX2-NEXT:    vpaddb %ymm3, %ymm1, %ymm1
+; AVX2-NEXT:    vpaddb %ymm1, %ymm3, %ymm1
 ; AVX2-NEXT:    retq
 ;
 ; AVX512-LABEL: interleaved_load_vf64_i8_stride3:
 ; AVX512:       # %bb.0:
 ; AVX512-NEXT:    vmovdqu (%rdi), %xmm0
 ; AVX512-NEXT:    vmovdqu 16(%rdi), %xmm1
 ; AVX512-NEXT:    vmovdqu 32(%rdi), %xmm2
 ; AVX512-NEXT:    vmovdqu 96(%rdi), %xmm3

 ; AVX512-NEXT:    vpshufb %zmm3, %zmm2, %zmm2
 ; AVX512-NEXT:    vpalignr {{.*#+}} zmm3 = zmm2[11,12,13,14,15],zmm0[0,1,2,3,4,5,6,7,8,9,10],zmm2[27,28,29,30,31],zmm0[16,17,18,19,20,21,22,23,24,25,26],zmm2[43,44,45,46,47],zmm0[32,33,34,35,36,37,38,39,40,41,42],zmm2[59,60,61,62,63],zmm0[48,49,50,51,52,53,54,55,56,57,58]
 ; AVX512-NEXT:    vpalignr {{.*#+}} zmm0 = zmm0[11,12,13,14,15],zmm1[0,1,2,3,4,5,6,7,8,9,10],zmm0[27,28,29,30,31],zmm1[16,17,18,19,20,21,22,23,24,25,26],zmm0[43,44,45,46,47],zmm1[32,33,34,35,36,37,38,39,40,41,42],zmm0[59,60,61,62,63],zmm1[48,49,50,51,52,53,54,55,56,57,58]
 ; AVX512-NEXT:    vpalignr {{.*#+}} zmm1 = zmm1[11,12,13,14,15],zmm2[0,1,2,3,4,5,6,7,8,9,10],zmm1[27,28,29,30,31],zmm2[16,17,18,19,20,21,22,23,24,25,26],zmm1[43,44,45,46,47],zmm2[32,33,34,35,36,37,38,39,40,41,42],zmm1[59,60,61,62,63],zmm2[48,49,50,51,52,53,54,55,56,57,58]
 ; AVX512-NEXT:    movabsq $-576188069258921984, %rax # imm = 0xF800F800F800F800
 ; AVX512-NEXT:    kmovq %rax, %k1
 ; AVX512-NEXT:    vpblendmb %zmm1, %zmm0, %zmm2 {%k1}
 ; AVX512-NEXT:    vpalignr {{.*#+}} zmm1 = zmm3[11,12,13,14,15],zmm1[0,1,2,3,4,5,6,7,8,9,10],zmm3[27,28,29,30,31],zmm1[16,17,18,19,20,21,22,23,24,25,26],zmm3[43,44,45,46,47],zmm1[32,33,34,35,36,37,38,39,40,41,42],zmm3[59,60,61,62,63],zmm1[48,49,50,51,52,53,54,55,56,57,58]
-; AVX512-NEXT:    vpaddb %zmm1, %zmm2, %zmm1
+; AVX512-NEXT:    vpaddb %zmm2, %zmm1, %zmm1
 ; AVX512-NEXT:    vpalignr {{.*#+}} zmm0 = zmm0[11,12,13,14,15],zmm3[0,1,2,3,4,5,6,7,8,9,10],zmm0[27,28,29,30,31],zmm3[16,17,18,19,20,21,22,23,24,25,26],zmm0[43,44,45,46,47],zmm3[32,33,34,35,36,37,38,39,40,41,42],zmm0[59,60,61,62,63],zmm3[48,49,50,51,52,53,54,55,56,57,58]
 ; AVX512-NEXT:    vpalignr {{.*#+}} zmm0 = zmm0[10,11,12,13,14,15,0,1,2,3,4,5,6,7,8,9,26,27,28,29,30,31,16,17,18,19,20,21,22,23,24,25,42,43,44,45,46,47,32,33,34,35,36,37,38,39,40,41,58,59,60,61,62,63,48,49,50,51,52,53,54,55,56,57]
-; AVX512-NEXT:    vpaddb %zmm1, %zmm0, %zmm0
+; AVX512-NEXT:    vpaddb %zmm0, %zmm1, %zmm0
 ; AVX512-NEXT:    retq
 %wide.vec = load <192 x i8>, ptr %ptr, align 1
 %v1 = shufflevector <192 x i8> %wide.vec, <192 x i8> undef, <64 x i32> <i32 0, i32 3, i32 6, i32 9, i32 12, i32 15, i32 18, i32 21, i32 24, i32 27, i32 30, i32 33, i32 36, i32 39, i32 42, i32 45, i32 48, i32 51, i32 54, i32 57, i32 60, i32 63, i32 66, i32 69, i32 72, i32 75, i32 78, i32 81, i32 84, i32 87, i32 90, i32 93, i32 96, i32 99, i32 102, i32 105, i32 108, i32 111, i32 114, i32 117, i32 120, i32 123, i32 126, i32 129, i32 132, i32 135, i32 138, i32 141, i32 144, i32 147, i32 150, i32 153, i32 156, i32 159, i32 162, i32 165, i32 168, i32 171, i32 174, i32 177, i32 180, i32 183, i32 186, i32 189>
 %v2 = shufflevector <192 x i8> %wide.vec, <192 x i8> undef, <64 x i32> <i32 1, i32 4, i32 7, i32 10, i32 13, i32 16, i32 19, i32 22, i32 25, i32 28, i32 31, i32 34, i32 37, i32 40, i32 43, i32 46, i32 49, i32 52, i32 55, i32 58, i32 61, i32 64, i32 67, i32 70, i32 73, i32 76, i32 79, i32 82, i32 85, i32 88, i32 91, i32 94, i32 97, i32 100, i32 103, i32 106, i32 109, i32 112, i32 115, i32 118, i32 121, i32 124, i32 127, i32 130, i32 133, i32 136, i32 139, i32 142, i32 145, i32 148, i32 151, i32 154, i32 157, i32 160, i32 163, i32 166, i32 169, i32 172, i32 175, i32 178, i32 181, i32 184, i32 187, i32 190>
 %v3 = shufflevector <192 x i8> %wide.vec, <192 x i8> undef, <64 x i32> <i32 2, i32 5, i32 8, i32 11, i32 14, i32 17, i32 20, i32 23, i32 26, i32 29, i32 32, i32 35, i32 38, i32 41, i32 44, i32 47, i32 50, i32 53, i32 56, i32 59, i32 62, i32 65, i32 68, i32 71, i32 74, i32 77, i32 80, i32 83, i32 86, i32 89, i32 92, i32 95, i32 98, i32 101, i32 104, i32 107, i32 110, i32 113, i32 116, i32 119, i32 122, i32 125, i32 128, i32 131, i32 134, i32 137, i32 140, i32 143, i32 146, i32 149, i32 152, i32 155, i32 158, i32 161, i32 164, i32 167, i32 170, i32 173, i32 176, i32 179, i32 182, i32 185, i32 188, i32 191>
 %add1 = add <64 x i8> %v1, %v2
 %add2 = add <64 x i8> %v3, %add1
 ret <64 x i8> %add2