Looks good to me except one nit.

LGTM. Thanks for improving this.

Hi @arsenm , I created a github issue for the crashes this patch hits, would you please help to have a look? https://github.com/llvm/llvm-project/issues/61430. Thanks!

We should already have case for leaf/non-leaf functions. Can we also add cases on the boundary conditions for redzone with below MIR?

---
name:            test
tracksRegLiveness: true
stack:
  - { id: 0, size: 288, alignment: 16 }
body: |
  bb.0:
    BLR8 implicit $lr8, implicit $rm
...

@arsenm Hi Matt, thanks for confirmation for the direction. I will continue to fix all the LIT failures and the crashes in the AMDGPU LIT cases.

fix the table-gen tests

gentle ping @nemanjai . Do you have further comments? Thank you!

I have been waiting for some days for D144711 for potential issues. Since no issues reported, I will reland this patch.

I think this is a good direction. For example we can avoid the crash in https://github.com/llvm/llvm-project/issues/60959 and give a clear diagnostic message.

add a new case GlobalISelEmitter-notypeoperand.ll

LGTM. Thank you for the fix!

address @foad comments

address @nemanjai comments

gentle ping.
We really want this to move forward on PPC. More patterns on PPC tds are without MVTs or register classes. Thank you!

gentle ping

LGTM. Thanks!

use getUnderlyingObject()

remove the unnecessary parameter.

LGTM with one nit.

address @foad comments

still reuse the first store pointer info for cases where narrow stores all point to the same underlying object

LGTM. Please wait for some days for other reviewers.

LGTM. Thanks for the improvement.

I'm not familiar with scheduler, but it looks to me like a general scheduler problem rather than X86 specific. I have filed 60744.
BTW, I found the problem cannot be reproduced without this patch. I guess it's the change happen to trigger the schedule.

To me, this patch is innocent for the failure https://bugs.chromium.org/p/chromium/issues/detail?id=1412740. The patch exposes an issue in the pre-ra machine scheduler on X86 target.

LGTM.

address comments from @amyk

In D138899#4108103, @nemanjai wrote:

@shchenz You neither incorporated nor responded to the comments I left when approving the patch. Could you please respond to the two comments as to why you felt they did not need to be incorporated into the final patch?

Thanks for review @nemanjai .

address @nemanjai comments and rebase

LGTM. Thanks for the improvement. Please wait for some days for other reviewers.

LGTM. Thanks for improving this.

@tstellar Hi, could you please help to confirm if the AMDGPU case changes are valid? Thank you very much.

Seems for patch that addresses github issues, you can add a comment Fixes #59315 in the description.

hmm, another issue cause by inconsistent logic for the tail call check between the IR coro-split pass and the instruction selection pass. Should we make them be consistent to avoid more issues?
For example, can we refactor IsEligibleForTailCallOptimization_64SVR4 and IsEligibleForTailCallOptimization() and call them in the TTI function supportsTailCallFor? I see there is a SelectionDAG &DAG parameter for these two functions, but the DAG is used to get the Caller Function, I think it should be easy to change the SelectionDAG to a Function parameter?

Looks right now. Thanks for adding this support.

In D139813#4034807, @Esme wrote:

Addressed comments and verified the materialization results.
However, I can't find a proper instruction to turn 0xABCD ADDD ABCD ADDD into 0xABCD ABCD ABCD ADDD, ie. modify Lo16OfHi32 (bits 32...47), so I didn't handle the pattern like 0xABCD ABCD ABCD ADDD.

gentle ping

gentle ping

LGTM. Thanks for working on this.

address comments from @arsenm and @nemanjai