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shchenz (ChenZheng)
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User Since
Jun 28 2018, 9:57 PM (121 w, 3 d)

Recent Activity

Yesterday

shchenz added inline comments to D89855: [PowerPC] Extend folding RLWINM + RLWINM to post-RA..
Sun, Oct 25, 8:13 PM · Restricted Project
shchenz added a comment to D89084: [PowerPC] Combine select_cc (x, 0, t, f, lt) to avoid generating `isel`.

I guess this opt should also be profitable for opcode SELECT, is there any reason we don't do this?

Sun, Oct 25, 6:45 PM · Restricted Project

Fri, Oct 23

shchenz added inline comments to D89855: [PowerPC] Extend folding RLWINM + RLWINM to post-RA..
Fri, Oct 23, 7:49 AM · Restricted Project
shchenz updated subscribers of D86864: [MachineSinking] sink more profitable loads.

Ah, I used @nikic perf testing tool for this patch. (Thanks for this great tool ^-^) Here is the result of the compiling time: https://llvm-compile-time-tracker.com/compare.php?from=2d25004a137223a02aa06e8bfd512a648f3b3f94&to=abf39366779bed8b9f2d276cd199c3b78471e3b1&stat=instructions

Fri, Oct 23, 7:07 AM · Restricted Project
shchenz updated subscribers of D89665: [LSR] ignore profitable chain optimization when instruction number is the major cost.

@jonpa @uweigand FYI as well for SystemZ. SystemZ does not take register number as major cost either.

Fri, Oct 23, 6:58 AM · Restricted Project
shchenz committed rG1e0b6c1df0f2: [LSR] ignore profitable chain when reg num is not major cost. (authored by shchenz).
[LSR] ignore profitable chain when reg num is not major cost.
Fri, Oct 23, 6:36 AM
shchenz closed D89665: [LSR] ignore profitable chain optimization when instruction number is the major cost.
Fri, Oct 23, 6:36 AM · Restricted Project

Thu, Oct 22

shchenz updated the diff for D86864: [MachineSinking] sink more profitable loads.

1: address Lint suggestion

Thu, Oct 22, 2:43 AM · Restricted Project
shchenz added a comment to D86864: [MachineSinking] sink more profitable loads.

Thanks very much for your review. @qcolombet Update accordingly. I collected some compiling time numbers for llvm test-suite. No obivious degradation found.

Thu, Oct 22, 1:58 AM · Restricted Project
shchenz updated the diff for D86864: [MachineSinking] sink more profitable loads.

1: clear the cache just before function returns
2: cache handled bb while calling depth_first() for a block

Thu, Oct 22, 1:46 AM · Restricted Project

Wed, Oct 21

shchenz committed rG2d71f26c8193: [LSR] add testcase for LSR profitable chain change, nfc (authored by shchenz).
[LSR] add testcase for LSR profitable chain change, nfc
Wed, Oct 21, 6:56 PM
shchenz added a comment to D89855: [PowerPC] Extend folding RLWINM + RLWINM to post-RA..

It would be great if we could split this patch into two parts:
1: extend rlwinm + rlwinm folding to post-ra and add some post-ra testcases, MIR cases are better.
2: add new simplication for rlwinm + andi_rec and add some post-ra and pre-ra testcases.

Wed, Oct 21, 6:25 PM · Restricted Project
shchenz accepted D89846: [NFC][PowerPC] Move the folding RLWINMs from ppc-mi-peephole to PPCInstrInfo..

Thanks for trying to extend it for post-RA. This makes sense to me as some RLWINM will be generated after RA. One nit and please also fix the lint suggestions.

Wed, Oct 21, 6:18 PM · Restricted Project
shchenz updated the diff for D89665: [LSR] ignore profitable chain optimization when instruction number is the major cost.

update:
1: merge header element checking into the new loop

Wed, Oct 21, 5:59 PM · Restricted Project
shchenz added inline comments to D89665: [LSR] ignore profitable chain optimization when instruction number is the major cost.
Wed, Oct 21, 5:53 PM · Restricted Project
shchenz added inline comments to D89665: [LSR] ignore profitable chain optimization when instruction number is the major cost.
Wed, Oct 21, 5:49 PM · Restricted Project
shchenz updated the diff for D89665: [LSR] ignore profitable chain optimization when instruction number is the major cost.

update:
1: put new added hook after isProfitableLSRChainElement for real...

Wed, Oct 21, 7:58 AM · Restricted Project
shchenz added inline comments to D89665: [LSR] ignore profitable chain optimization when instruction number is the major cost.
Wed, Oct 21, 7:22 AM · Restricted Project
shchenz updated the diff for D89665: [LSR] ignore profitable chain optimization when instruction number is the major cost.

update:
1: modify the new hook name
2: move it after isProfitableLSRChainElement

Wed, Oct 21, 7:22 AM · Restricted Project

Tue, Oct 20

shchenz added inline comments to D89665: [LSR] ignore profitable chain optimization when instruction number is the major cost.
Tue, Oct 20, 8:37 PM · Restricted Project
shchenz updated the summary of D89665: [LSR] ignore profitable chain optimization when instruction number is the major cost.
Tue, Oct 20, 8:33 PM · Restricted Project
shchenz updated the diff for D89665: [LSR] ignore profitable chain optimization when instruction number is the major cost.

add a new target hook isRegisterNumberMajorCost

Tue, Oct 20, 8:33 PM · Restricted Project
shchenz added a comment to D86864: [MachineSinking] sink more profitable loads.

gentle ping ^^

Tue, Oct 20, 3:28 AM · Restricted Project
shchenz added a comment to D88126: [Machinesink] add more profitable pattern if target bb register pressure is not too high.

gentle ping

Tue, Oct 20, 3:25 AM · Restricted Project

Sun, Oct 18

shchenz requested review of D89665: [LSR] ignore profitable chain optimization when instruction number is the major cost.
Sun, Oct 18, 8:33 PM · Restricted Project

Sun, Oct 11

shchenz added a comment to D88126: [Machinesink] add more profitable pattern if target bb register pressure is not too high.

gentle ping

Sun, Oct 11, 6:41 PM · Restricted Project

Thu, Oct 8

shchenz added inline comments to D89084: [PowerPC] Combine select_cc (x, 0, t, f, lt) to avoid generating `isel`.
Thu, Oct 8, 10:18 PM · Restricted Project
shchenz added a comment to D89084: [PowerPC] Combine select_cc (x, 0, t, f, lt) to avoid generating `isel`.

Thanks for doing this. This is what we should do for PPC target.

Thu, Oct 8, 10:15 PM · Restricted Project

Wed, Oct 7

shchenz added a comment to D87490: [MachineInstr] return mayAlias for not mayLoadOrStore instructions..

I think to make a fundamental interface strong, it is always possible to add some unreachable path for current code base to protect some furture improper callers. This is very like the assert statement. There should always no code path can trigger the assertion.

Wed, Oct 7, 8:01 AM · Restricted Project
shchenz added a comment to D87490: [MachineInstr] return mayAlias for not mayLoadOrStore instructions..

So why are we adding dead code then?

Wed, Oct 7, 7:39 AM · Restricted Project
shchenz added a comment to D87490: [MachineInstr] return mayAlias for not mayLoadOrStore instructions..

For starters, this is missing a test.

Wed, Oct 7, 7:21 AM · Restricted Project

Tue, Oct 6

shchenz committed rGed46e84c7aaf: [MachineInstr] exclude call instruction in mayAlias (authored by shchenz).
[MachineInstr] exclude call instruction in mayAlias
Tue, Oct 6, 9:19 PM
shchenz closed D87490: [MachineInstr] return mayAlias for not mayLoadOrStore instructions..
Tue, Oct 6, 9:19 PM · Restricted Project
shchenz added a comment to D87490: [MachineInstr] return mayAlias for not mayLoadOrStore instructions..

This is a quite 'small' patch and it should be a NFC patch as if any existing case hits this pattern, it gets a wrong aliasing query result.

Tue, Oct 6, 9:18 PM · Restricted Project
shchenz committed rGf05608707c64: [PowerPC] implement target hook getTgtMemIntrinsic (authored by shchenz).
[PowerPC] implement target hook getTgtMemIntrinsic
Tue, Oct 6, 9:04 PM
shchenz closed D88373: [PowerPC] implement target hook getTgtMemIntrinsic.
Tue, Oct 6, 9:04 PM · Restricted Project
shchenz committed rG0492dd91c49c: [PowerPC] add more builtins for PPCTargetLowering::getTgtMemIntrinsic (authored by shchenz).
[PowerPC] add more builtins for PPCTargetLowering::getTgtMemIntrinsic
Tue, Oct 6, 8:50 PM
shchenz closed D88374: [PowerPC] add more builtins to PPCTargetLowering::getTgtMemIntrinsic.
Tue, Oct 6, 8:50 PM · Restricted Project

Wed, Sep 30

shchenz accepted D88274: [PowerPC] Put the CR field in low bits of GRC during copying CRRC to GRC..

LGTM too. Thanks for sharing the background. Before committing this, it's better to update the description for later reference like @nemanjai pointed out?

Wed, Sep 30, 7:04 PM · Restricted Project
shchenz added a comment to D86864: [MachineSinking] sink more profitable loads.

@efriedma @qcolombet haha, thanks for your review. Please take your time. ^-^ . I want to make the alias check simple(find all basic blocks in all paths from block From to block To), so I guard the dominance between From and To as From dominates To and To post dominates From. This will make us still miss some cases in which load instruction can be sunk. But it can make the implementation simple.

Wed, Sep 30, 6:58 PM · Restricted Project

Tue, Sep 29

shchenz added a comment to D87490: [MachineInstr] return mayAlias for not mayLoadOrStore instructions..

gentle ping

Tue, Sep 29, 4:50 PM · Restricted Project
shchenz added a comment to D88126: [Machinesink] add more profitable pattern if target bb register pressure is not too high.

gentle ping

Tue, Sep 29, 4:49 PM · Restricted Project
shchenz added a comment to D86864: [MachineSinking] sink more profitable loads.

gentle ping

Tue, Sep 29, 4:49 PM · Restricted Project

Sun, Sep 27

shchenz updated the diff for D88373: [PowerPC] implement target hook getTgtMemIntrinsic.

code format fix

Sun, Sep 27, 1:56 AM · Restricted Project
shchenz requested review of D88374: [PowerPC] add more builtins to PPCTargetLowering::getTgtMemIntrinsic.
Sun, Sep 27, 1:52 AM · Restricted Project
shchenz requested review of D88373: [PowerPC] implement target hook getTgtMemIntrinsic.
Sun, Sep 27, 1:19 AM · Restricted Project

Sat, Sep 26

shchenz committed rGc8f6c0f961ee: [Machinesink] add one more profitable loop related pattern (authored by shchenz).
[Machinesink] add one more profitable loop related pattern
Sat, Sep 26, 7:12 PM
shchenz closed D86925: [MachineSink] add one more profitable pattern for sinking.
Sat, Sep 26, 7:11 PM · Restricted Project
shchenz added inline comments to D88274: [PowerPC] Put the CR field in low bits of GRC during copying CRRC to GRC..
Sat, Sep 26, 5:48 PM · Restricted Project

Sep 22 2020

shchenz added a comment to D86864: [MachineSinking] sink more profitable loads.

gentle ping

Sep 22 2020, 10:32 PM · Restricted Project
shchenz requested review of D88126: [Machinesink] add more profitable pattern if target bb register pressure is not too high.
Sep 22 2020, 6:09 PM · Restricted Project

Sep 20 2020

shchenz added a comment to D87490: [MachineInstr] return mayAlias for not mayLoadOrStore instructions..

Hi @efriedma could you please help to have another look for this simple fix? Thanks.

Sep 20 2020, 4:56 PM · Restricted Project

Sep 18 2020

shchenz added a comment to D86925: [MachineSink] add one more profitable pattern for sinking.

Ah sorry about that. I was expecting a new file, whereas the diff only shows a change in sinking for that file.

Sep 18 2020, 6:52 PM · Restricted Project

Sep 17 2020

shchenz planned changes to D82709: [MachineLICM] [PowerPC] hoisting rematerializable cheap instructions based on register pressure..
Sep 17 2020, 7:35 PM · Restricted Project
shchenz added a comment to D86925: [MachineSink] add one more profitable pattern for sinking.

1: add one more mir test case

Did you forget to do git add, I don't see it.

Sep 17 2020, 5:24 PM · Restricted Project
shchenz updated the diff for D86925: [MachineSink] add one more profitable pattern for sinking.

delete unused variables

Sep 17 2020, 5:17 PM · Restricted Project

Sep 16 2020

shchenz added a comment to D86925: [MachineSink] add one more profitable pattern for sinking.

Thanks very much, updated, could you please help to have another look? @qcolombet

Sep 16 2020, 7:27 PM · Restricted Project
shchenz updated the diff for D86925: [MachineSink] add one more profitable pattern for sinking.

1: add one more mir test case
2: fix code format

Sep 16 2020, 7:26 PM · Restricted Project
shchenz committed rG5782ab0f52db: [MachineSink] add one more mir case - nfc (authored by shchenz).
[MachineSink] add one more mir case - nfc
Sep 16 2020, 7:04 PM

Sep 15 2020

shchenz updated the summary of D86925: [MachineSink] add one more profitable pattern for sinking.
Sep 15 2020, 9:52 PM · Restricted Project
shchenz added a comment to D86925: [MachineSink] add one more profitable pattern for sinking.

Given adding that is going to take some time, you could push your patch for the cases we know are always profitable: when the uses are alive across the whole loop (line 636 in the current implementation.)

Sep 15 2020, 9:50 PM · Restricted Project
shchenz updated the diff for D86925: [MachineSink] add one more profitable pattern for sinking.

address @qcolombet comments:
1: firstly add the always profitable pattern

Sep 15 2020, 9:45 PM · Restricted Project

Sep 14 2020

shchenz added a comment to D86925: [MachineSink] add one more profitable pattern for sinking.

@qcolombet Thanks for your good comments.

Sep 14 2020, 9:25 PM · Restricted Project

Sep 13 2020

shchenz added a comment to D86925: [MachineSink] add one more profitable pattern for sinking.

gentle ping

Sep 13 2020, 7:13 PM · Restricted Project
shchenz updated the summary of D87490: [MachineInstr] return mayAlias for not mayLoadOrStore instructions..
Sep 13 2020, 7:02 PM · Restricted Project
shchenz updated the diff for D87490: [MachineInstr] return mayAlias for not mayLoadOrStore instructions..

explicitly check for isCall

Sep 13 2020, 6:53 PM · Restricted Project

Sep 10 2020

shchenz abandoned D85504: [Reassociate] [PowerPC] stop common out mul factors if fma is preferred on target.

we will use other solution for this issue.

Sep 10 2020, 10:11 PM · Restricted Project
shchenz updated the diff for D87490: [MachineInstr] return mayAlias for not mayLoadOrStore instructions..
Sep 10 2020, 9:41 PM · Restricted Project
shchenz updated the summary of D87490: [MachineInstr] return mayAlias for not mayLoadOrStore instructions..
Sep 10 2020, 9:26 PM · Restricted Project
shchenz requested review of D87490: [MachineInstr] return mayAlias for not mayLoadOrStore instructions..
Sep 10 2020, 9:25 PM · Restricted Project
shchenz added a comment to D82709: [MachineLICM] [PowerPC] hoisting rematerializable cheap instructions based on register pressure..

It doesn't happen in your case because the weight of %0 is pretty small and in particular, smaller than the rematerializable live-intervals (e.g., %157).

Sep 10 2020, 6:02 PM · Restricted Project

Sep 9 2020

shchenz added a comment to D82709: [MachineLICM] [PowerPC] hoisting rematerializable cheap instructions based on register pressure..

Hi @qcolombet , I saw you added comments for other patch about Greedy Register Pressure like "The greedy allocator is already very complicated". I am not sure my proposal change in above comment in greedyRA will increase the complexity or if it is the right way to go. Could you please help to confirm this? Thanks.

Sep 9 2020, 7:29 AM · Restricted Project

Sep 6 2020

shchenz added inline comments to D86925: [MachineSink] add one more profitable pattern for sinking.
Sep 6 2020, 6:46 PM · Restricted Project
shchenz updated the diff for D86925: [MachineSink] add one more profitable pattern for sinking.

use registerclassweight

Sep 6 2020, 6:46 PM · Restricted Project
shchenz committed rGd5c45041f146: [machinesink] add testcase for more sinking - NFC (authored by shchenz).
[machinesink] add testcase for more sinking - NFC
Sep 6 2020, 6:36 PM

Sep 2 2020

shchenz updated the summary of D86925: [MachineSink] add one more profitable pattern for sinking.
Sep 2 2020, 6:04 PM · Restricted Project
shchenz added a comment to D86864: [MachineSinking] sink more profitable loads.

Do we need some threshold to limit the analysis? I'm worried this could get very expensive.

Sep 2 2020, 3:47 AM · Restricted Project
shchenz updated the diff for D86864: [MachineSinking] sink more profitable loads.

1: can not check alias for call instruction by using mayAlias
2: add one more cache to save compiling time.

Sep 2 2020, 3:46 AM · Restricted Project

Sep 1 2020

shchenz updated the summary of D86925: [MachineSink] add one more profitable pattern for sinking.
Sep 1 2020, 3:43 AM · Restricted Project
shchenz requested review of D86925: [MachineSink] add one more profitable pattern for sinking.
Sep 1 2020, 3:34 AM · Restricted Project
shchenz updated the diff for D86864: [MachineSinking] sink more profitable loads.

handle further more cases to sink profitable loads

Sep 1 2020, 2:57 AM · Restricted Project

Aug 31 2020

shchenz updated the summary of D86864: [MachineSinking] sink more profitable loads.
Aug 31 2020, 5:06 AM · Restricted Project
shchenz requested review of D86864: [MachineSinking] sink more profitable loads.
Aug 31 2020, 2:11 AM · Restricted Project

Aug 30 2020

shchenz added a comment to D82709: [MachineLICM] [PowerPC] hoisting rematerializable cheap instructions based on register pressure..

Hi @qcolombet, for the log in https://reviews.llvm.org/P8231, you can just see the RA result at the end. Ideally, we can remat registers %267 ~ %309(2132B - 2216B) to their use, and then we can free some physical registers and assign the physical registers to %166 ~ %190 to save the spills.

Aug 30 2020, 7:35 PM · Restricted Project

Aug 21 2020

shchenz added a comment to D82709: [MachineLICM] [PowerPC] hoisting rematerializable cheap instructions based on register pressure..

Hi @qcolombet the log for the new added case(With the change in https://reviews.llvm.org/D82709#2121904) is put https://reviews.llvm.org/P8231

Aug 21 2020, 7:38 PM · Restricted Project

Aug 20 2020

shchenz requested review of D82709: [MachineLICM] [PowerPC] hoisting rematerializable cheap instructions based on register pressure..
Aug 20 2020, 9:18 AM · Restricted Project
shchenz added a comment to D82709: [MachineLICM] [PowerPC] hoisting rematerializable cheap instructions based on register pressure..

Hi @efriedma after a long time investigation about greedy register allocation, I have some findings. I think the reason why the remat lis is not sinked down by RA as our expected is the limitation of current greedy register allocation. Hi @qcolombet sorry to bother you, If I am wrong at the comment about greedyRA, please correct me. ^-^

Aug 20 2020, 9:17 AM · Restricted Project

Aug 16 2020

shchenz committed rG4d52ebb9b9c7: [PowerPC] Make StartMI ignore COPY like instructions. (authored by shchenz).
[PowerPC] Make StartMI ignore COPY like instructions.
Aug 16 2020, 11:13 PM
shchenz added a comment to D85659: [PowerPC] in fixupIsDeadOrKill before RA, get def instructions by calling getVRegDef .

Thanks for your review @lkail The nits are updated in the commit

Aug 16 2020, 11:13 PM · Restricted Project
shchenz closed D85659: [PowerPC] in fixupIsDeadOrKill before RA, get def instructions by calling getVRegDef .
Aug 16 2020, 11:13 PM · Restricted Project
shchenz added a comment to D85659: [PowerPC] in fixupIsDeadOrKill before RA, get def instructions by calling getVRegDef .

gentle ping...

Aug 16 2020, 6:28 PM · Restricted Project

Aug 10 2020

shchenz added a comment to D85599: [PowerPC] Remove isTerminator for TRAP instruction.

With this change, we get verify failure for below case:

int test_builtin_trap(int num) {
  volatile int i = 0;
  if (num > 0)
    __builtin_unreachable();
  return i;
}
Aug 10 2020, 7:40 PM · Restricted Project, Restricted Project, Restricted Project
shchenz updated the diff for D85659: [PowerPC] in fixupIsDeadOrKill before RA, get def instructions by calling getVRegDef .

make sure StartMI is a def through COPY

Aug 10 2020, 5:17 PM · Restricted Project
shchenz retitled D85659: [PowerPC] in fixupIsDeadOrKill before RA, get def instructions by calling getVRegDef from [PowerPC] before RA, get def instructions by calling getVRegDef to [PowerPC] in fixupIsDeadOrKill before RA, get def instructions by calling getVRegDef .
Aug 10 2020, 9:07 AM · Restricted Project
shchenz requested review of D85659: [PowerPC] in fixupIsDeadOrKill before RA, get def instructions by calling getVRegDef .
Aug 10 2020, 9:06 AM · Restricted Project
shchenz added a comment to D85504: [Reassociate] [PowerPC] stop common out mul factors if fma is preferred on target.

Thanks @spatel @nemanjai for your comments. So it should be a common-sense that we should not add TTI/TLI hook inside Reassociate Pass which was already kindly pointed out by @lebedev.ri . I have learned this now ^_^.
I will investigate all the suggested places to do the reversal (DAGCombine, other PPC specific pass or CGP) later.

Aug 10 2020, 6:18 AM · Restricted Project

Aug 7 2020

shchenz planned changes to D85504: [Reassociate] [PowerPC] stop common out mul factors if fma is preferred on target.

Good catch for the a*b * c*d + e*f * c*d case, Roman. That's a degradation after this patch. Thanks for your good review. ^-^

Aug 7 2020, 2:07 AM · Restricted Project
shchenz updated the summary of D85504: [Reassociate] [PowerPC] stop common out mul factors if fma is preferred on target.
Aug 7 2020, 1:14 AM · Restricted Project
shchenz added a comment to D85504: [Reassociate] [PowerPC] stop common out mul factors if fma is preferred on target.

(can you please maybe spellcheck both the patch description and the wording within the patch? it is really hard to read)

Done

I'm not really sure this is the way forward.

  1. This is a target-agnostic pass, it we add arbitrary restrictions it will likely miss some intended transforms

Could you be more specific? I verified this change on PowerPC for some benchmarks, no degradation found.

Aug 7 2020, 1:11 AM · Restricted Project
shchenz updated the summary of D85504: [Reassociate] [PowerPC] stop common out mul factors if fma is preferred on target.
Aug 7 2020, 1:02 AM · Restricted Project