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shchenz (ChenZheng)
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User Since
Jun 28 2018, 9:57 PM (81 w, 1 d)

Recent Activity

Mon, Jan 13

shchenz created D72683: [PowerPC] set instruction number as 1st priority for lsr cost model.
Mon, Jan 13, 11:39 PM · Restricted Project
shchenz committed rG671544c25b12: [PowerPC] [NFC] set instruction number as 1st priority of lsr cost model. (authored by shchenz).
[PowerPC] [NFC] set instruction number as 1st priority of lsr cost model.
Mon, Jan 13, 11:21 PM

Sun, Jan 12

shchenz committed rGa6342c247a17: [SCEV] accurate range for addrecexpr with nuw flag (authored by shchenz).
[SCEV] accurate range for addrecexpr with nuw flag
Sun, Jan 12, 5:28 PM
shchenz closed D71690: [SCEV] get a more accurate range for AddRecExpr with nuw flag.
Sun, Jan 12, 5:28 PM · Restricted Project

Sat, Jan 11

shchenz committed rG569ccfc384a5: [SCEV] more accurate range for addrecexpr with nsw flag. (authored by shchenz).
[SCEV] more accurate range for addrecexpr with nsw flag.
Sat, Jan 11, 8:32 PM
shchenz closed D72436: [SCEV] get a more accurate range for AddRecExpr with nsw flag.
Sat, Jan 11, 8:32 PM · Restricted Project
shchenz added a comment to D71690: [SCEV] get a more accurate range for AddRecExpr with nuw flag.

Hi @sanjoy.google , could you please help to have another look at this? Thanks a lot.

Sat, Jan 11, 8:23 PM · Restricted Project
shchenz added inline comments to D72436: [SCEV] get a more accurate range for AddRecExpr with nsw flag.
Sat, Jan 11, 8:23 PM · Restricted Project

Fri, Jan 10

shchenz updated the diff for D72436: [SCEV] get a more accurate range for AddRecExpr with nsw flag.

use getNonEmpty() interface & add more test cases

Fri, Jan 10, 8:00 PM · Restricted Project
shchenz committed rGa701be8f036a: [SCEV] [NFC] add more test cases for range of addrecexpr with nsw flag (authored by shchenz).
[SCEV] [NFC] add more test cases for range of addrecexpr with nsw flag
Fri, Jan 10, 7:50 PM
shchenz updated the diff for D72436: [SCEV] get a more accurate range for AddRecExpr with nsw flag.

operand 0 does not required to be NonPos/NonNeg

Fri, Jan 10, 7:43 AM · Restricted Project
shchenz added inline comments to D72436: [SCEV] get a more accurate range for AddRecExpr with nsw flag.
Fri, Jan 10, 7:43 AM · Restricted Project

Thu, Jan 9

shchenz updated the diff for D71690: [SCEV] get a more accurate range for AddRecExpr with nuw flag.

use unsigned range min as initial value

Thu, Jan 9, 5:27 PM · Restricted Project

Wed, Jan 8

shchenz created D72436: [SCEV] get a more accurate range for AddRecExpr with nsw flag.
Wed, Jan 8, 10:34 PM · Restricted Project
shchenz committed rG4ebb589629b0: [SCEV] [NFC] add testcase for constant range for addrecexpr with nsw flag (authored by shchenz).
[SCEV] [NFC] add testcase for constant range for addrecexpr with nsw flag
Wed, Jan 8, 10:34 PM
shchenz added inline comments to D71690: [SCEV] get a more accurate range for AddRecExpr with nuw flag.
Wed, Jan 8, 7:01 PM · Restricted Project
shchenz committed rG26ba160d4722: [PowerPC] when folding rlwinm+rlwinm. to andi., we should use first rlwinm… (authored by shchenz).
[PowerPC] when folding rlwinm+rlwinm. to andi., we should use first rlwinm…
Wed, Jan 8, 6:06 PM
shchenz closed D71885: [PowerPC] replace rlwinm operand 1 with src rlwinm operand 1.
Wed, Jan 8, 6:06 PM · Restricted Project

Tue, Jan 7

shchenz updated the diff for D71690: [SCEV] get a more accurate range for AddRecExpr with nuw flag.

rebase after D64869

Tue, Jan 7, 6:19 PM · Restricted Project
shchenz committed rG8b8ba44047d4: [SCEV] get more accurate range for AddExpr with wrap flag. (authored by shchenz).
[SCEV] get more accurate range for AddExpr with wrap flag.
Tue, Jan 7, 6:10 PM
shchenz closed D64869: [SCEV] get more accurate range for AddExpr with NW flag.
Tue, Jan 7, 6:09 PM · Restricted Project

Sun, Jan 5

shchenz added a comment to D71690: [SCEV] get a more accurate range for AddRecExpr with nuw flag.

gentle ping

Sun, Jan 5, 9:19 PM · Restricted Project

Thu, Jan 2

shchenz updated the diff for D71885: [PowerPC] replace rlwinm operand 1 with src rlwinm operand 1.

address @steven.zhang comments

Thu, Jan 2, 6:16 PM · Restricted Project

Wed, Jan 1

shchenz updated the diff for D71885: [PowerPC] replace rlwinm operand 1 with src rlwinm operand 1.

update testing point

Wed, Jan 1, 5:51 PM · Restricted Project

Mon, Dec 30

shchenz added inline comments to D71885: [PowerPC] replace rlwinm operand 1 with src rlwinm operand 1.
Mon, Dec 30, 4:18 AM · Restricted Project
shchenz added inline comments to D71885: [PowerPC] replace rlwinm operand 1 with src rlwinm operand 1.
Mon, Dec 30, 2:26 AM · Restricted Project
shchenz added inline comments to D71885: [PowerPC] replace rlwinm operand 1 with src rlwinm operand 1.
Mon, Dec 30, 2:14 AM · Restricted Project
shchenz updated the diff for D71885: [PowerPC] replace rlwinm operand 1 with src rlwinm operand 1.

address comments

Mon, Dec 30, 1:29 AM · Restricted Project
shchenz added inline comments to D71885: [PowerPC] replace rlwinm operand 1 with src rlwinm operand 1.
Mon, Dec 30, 1:29 AM · Restricted Project

Sun, Dec 29

shchenz updated the diff for D71690: [SCEV] get a more accurate range for AddRecExpr with nuw flag.
Sun, Dec 29, 8:53 PM · Restricted Project
shchenz added inline comments to D71690: [SCEV] get a more accurate range for AddRecExpr with nuw flag.
Sun, Dec 29, 7:50 PM · Restricted Project
shchenz updated the diff for D71690: [SCEV] get a more accurate range for AddRecExpr with nuw flag.

for signed range with nsw flag, we can only use the sign min value when constant range for START can not cross 0.

Sun, Dec 29, 7:41 PM · Restricted Project

Fri, Dec 27

shchenz added inline comments to D71690: [SCEV] get a more accurate range for AddRecExpr with nuw flag.
Fri, Dec 27, 1:21 AM · Restricted Project
shchenz planned changes to D71690: [SCEV] get a more accurate range for AddRecExpr with nuw flag.
Fri, Dec 27, 1:21 AM · Restricted Project

Thu, Dec 26

shchenz accepted D71829: [PowerPC] Exploit the rlwinm instructions for "and" with constant..

LGTM with one nit comment.

Thu, Dec 26, 1:54 AM · Restricted Project

Wed, Dec 25

shchenz added inline comments to D71829: [PowerPC] Exploit the rlwinm instructions for "and" with constant..
Wed, Dec 25, 10:34 PM · Restricted Project
shchenz added inline comments to D71829: [PowerPC] Exploit the rlwinm instructions for "and" with constant..
Wed, Dec 25, 7:56 PM · Restricted Project
shchenz created D71885: [PowerPC] replace rlwinm operand 1 with src rlwinm operand 1.
Wed, Dec 25, 7:27 PM · Restricted Project
shchenz committed rG1b57749a5334: [PowerPC] stop folding if result rlwinm mask is wrap while original rlwinm is… (authored by shchenz).
[PowerPC] stop folding if result rlwinm mask is wrap while original rlwinm is…
Wed, Dec 25, 7:00 PM
shchenz closed D71833: [PowerPC] if value type is changed after folding rlwinm, stop folding.
Wed, Dec 25, 6:59 PM · Restricted Project
shchenz updated the diff for D71833: [PowerPC] if value type is changed after folding rlwinm, stop folding.

fix result mask MB > ME cases.

Wed, Dec 25, 6:06 PM · Restricted Project
shchenz retitled D71833: [PowerPC] if value type is changed after folding rlwinm, stop folding from [PowerPC] Fix some bugs of the rlwinm folding to [PowerPC] if value type is changed after folding rlwinm, stop folding.
Wed, Dec 25, 5:55 PM · Restricted Project
shchenz added a comment to D71833: [PowerPC] if value type is changed after folding rlwinm, stop folding.

I would suggest to retitle it to be more descriptive about code behavior, like 'Add check' blah blah. Describe what bugs it can fix in summary field.

Wed, Dec 25, 5:55 PM · Restricted Project

Mon, Dec 23

shchenz accepted D71693: [NFC][PowerPC] Add a function tryAndWithMask.

LGTM. Some minor comment, you can handle it as you like.

Mon, Dec 23, 7:09 PM · Restricted Project
shchenz updated the summary of D71833: [PowerPC] if value type is changed after folding rlwinm, stop folding.
Mon, Dec 23, 6:40 PM · Restricted Project
shchenz commandeered D71833: [PowerPC] if value type is changed after folding rlwinm, stop folding.

Thanks for finding out this bug. As discussed, I will take this patch.

Mon, Dec 23, 6:31 PM · Restricted Project
shchenz added a comment to D71833: [PowerPC] if value type is changed after folding rlwinm, stop folding.

Seems there is indeed some bug for current folding. If the wrap relationship between mb and me for folding result rlwinm is different with he wrap relationship in MI.

Mon, Dec 23, 6:03 PM · Restricted Project
shchenz added inline comments to D71693: [NFC][PowerPC] Add a function tryAndWithMask.
Mon, Dec 23, 5:54 PM · Restricted Project
shchenz added a comment to D71833: [PowerPC] if value type is changed after folding rlwinm, stop folding.

Thanks for finding the bug in the testcases. I have modified them in NFC patch https://reviews.llvm.org/rG79b3325be0b016fdc1a2c55bce65ec9f1e5f4eb6

Mon, Dec 23, 7:45 AM · Restricted Project
shchenz committed rG79b3325be0b0: [PowerPC] NFC - fix the testcase bug of folding rlwinm (authored by shchenz).
[PowerPC] NFC - fix the testcase bug of folding rlwinm
Mon, Dec 23, 7:35 AM
shchenz added inline comments to D71690: [SCEV] get a more accurate range for AddRecExpr with nuw flag.
Mon, Dec 23, 4:12 AM · Restricted Project
shchenz abandoned D65262: [SCEV] simplify more icmps with pred sle/ule to pred slt/ult.

Right solution should be https://reviews.llvm.org/D71690. We can convert sle to slt if get(Signed|Unsigned)RangeMin(LHS) is not min value. In https://reviews.llvm.org/D71690, we can get a more accurate min value for AddRec with flag nsw|nuw.

Mon, Dec 23, 12:36 AM · Restricted Project

Sun, Dec 22

shchenz updated the diff for D64869: [SCEV] get more accurate range for AddExpr with NW flag.

address @nikic comments

Sun, Dec 22, 11:38 PM · Restricted Project
shchenz added inline comments to D64869: [SCEV] get more accurate range for AddExpr with NW flag.
Sun, Dec 22, 11:38 PM · Restricted Project
shchenz added inline comments to D71690: [SCEV] get a more accurate range for AddRecExpr with nuw flag.
Sun, Dec 22, 10:22 PM · Restricted Project
shchenz updated the diff for D71690: [SCEV] get a more accurate range for AddRecExpr with nuw flag.

fix @sanjoy.google comments

Sun, Dec 22, 10:22 PM · Restricted Project
shchenz committed rG7259f04dde82: [SCEV] add testcase for get accurate range for addrecexpr with nuw flag (authored by shchenz).
[SCEV] add testcase for get accurate range for addrecexpr with nuw flag
Sun, Dec 22, 5:59 PM

Dec 19 2019

shchenz added inline comments to D71690: [SCEV] get a more accurate range for AddRecExpr with nuw flag.
Dec 19 2019, 4:21 AM · Restricted Project
shchenz updated the diff for D64869: [SCEV] get more accurate range for AddExpr with NW flag.
Dec 19 2019, 1:34 AM · Restricted Project
shchenz removed a parent revision for D64869: [SCEV] get more accurate range for AddExpr with NW flag: D64868: [SCEV] add NW flag for AddExpr (start + stride).
Dec 19 2019, 1:25 AM · Restricted Project
shchenz removed a child revision for D64868: [SCEV] add NW flag for AddExpr (start + stride): D64869: [SCEV] get more accurate range for AddExpr with NW flag.
Dec 19 2019, 1:25 AM · Restricted Project
shchenz updated the summary of D64869: [SCEV] get more accurate range for AddExpr with NW flag.
Dec 19 2019, 1:25 AM · Restricted Project
shchenz added a comment to D64869: [SCEV] get more accurate range for AddExpr with NW flag.

Seems we can not simply add nsw|nuw for start + stride as I did in https://reviews.llvm.org/D64868. Since SCEV are shared with expressions in different blocks, we must ensure all expressions mapped to same SCEV can be added with nsw|nuw.

Dec 19 2019, 1:25 AM · Restricted Project
shchenz committed rGd588a00206ac: [SCEV] NFC - add testcase for get accurate range for AddExpr (authored by shchenz).
[SCEV] NFC - add testcase for get accurate range for AddExpr
Dec 19 2019, 1:15 AM

Dec 18 2019

shchenz created D71690: [SCEV] get a more accurate range for AddRecExpr with nuw flag.
Dec 18 2019, 11:51 PM · Restricted Project
shchenz committed rGf5440ec41d8e: [PowerPC] make lwa as a valid ds candidate in ppcloopinstrformprep pass (authored by shchenz).
[PowerPC] make lwa as a valid ds candidate in ppcloopinstrformprep pass
Dec 18 2019, 6:09 PM
shchenz closed D71346: [PowerPC] support loop ds form prep for lwa.
Dec 18 2019, 6:09 PM · Restricted Project
shchenz added inline comments to D71346: [PowerPC] support loop ds form prep for lwa.
Dec 18 2019, 5:59 PM · Restricted Project
shchenz added a comment to rGaaa5a5e7ff1a: DebugInfo: Include DW_AT_base_addr even in gmlt with no inline functions.

Hi @dblaikie seems this commit makes check llvm fail on PowerPC.

: 'RUN: at line 1';  ./llvm-project/llvm/build/bin/llc --function-sections < ./llvm-project/llvm/test/DebugInfo/X86/gmlt-empty-base-address.ll -filetype=obj | ./llvm-project/llvm/build/bin/llvm-dwarfdump -v -debug-info - | ./llvm-project/llvm/build/bin/FileCheck ./llvm-project/llvm/test/DebugInfo/X86/gmlt-empty-base-address.ll
--
Exit Code: 1
Dec 18 2019, 5:50 PM
shchenz added a comment to D71589: [PowerPC] Adding a match pattern to recognize the and mask with RLWINM8.

Right, current patch should still be with bug.

Dec 18 2019, 3:17 AM · Restricted Project

Dec 17 2019

shchenz accepted D71589: [PowerPC] Adding a match pattern to recognize the and mask with RLWINM8.

LGTM too.

Dec 17 2019, 5:29 PM · Restricted Project

Dec 11 2019

shchenz created D71346: [PowerPC] support loop ds form prep for lwa.
Dec 11 2019, 5:04 AM · Restricted Project
shchenz committed rGbf4580b7e740: [PowerPC][NFC] add test case for lwa - loop ds form prep (authored by shchenz).
[PowerPC][NFC] add test case for lwa - loop ds form prep
Dec 11 2019, 3:14 AM

Dec 9 2019

shchenz accepted D71002: [PowerPC] Exploitate the Vector Integer Average Instructions.

LGTM. Thanks for exploiting these instructions.

Dec 9 2019, 10:52 PM · Restricted Project
shchenz added inline comments to D71002: [PowerPC] Exploitate the Vector Integer Average Instructions.
Dec 9 2019, 7:35 PM · Restricted Project

Dec 3 2019

shchenz committed rGf0ba1aec35d5: [PowerPC] folding rlwinm + rlwinm to rlwinm (authored by shchenz).
[PowerPC] folding rlwinm + rlwinm to rlwinm
Dec 3 2019, 6:55 PM
shchenz closed D70374: [PowerPC] combine rlwinm + rlwinm to rlwinm.
Dec 3 2019, 6:55 PM · Restricted Project

Nov 28 2019

shchenz requested review of D70374: [PowerPC] combine rlwinm + rlwinm to rlwinm.
Nov 28 2019, 5:37 PM · Restricted Project
shchenz updated the diff for D70374: [PowerPC] combine rlwinm + rlwinm to rlwinm.

fix the failure cases found by buildbot.

Nov 28 2019, 5:25 PM · Restricted Project

Nov 27 2019

shchenz planned changes to D70374: [PowerPC] combine rlwinm + rlwinm to rlwinm.
Nov 27 2019, 12:51 AM · Restricted Project
shchenz reopened D70374: [PowerPC] combine rlwinm + rlwinm to rlwinm.

This patch caused failure in http://lab.llvm.org:8011/builders/clang-ppc64be-linux-multistage/builds/21918

Nov 27 2019, 12:51 AM · Restricted Project

Nov 26 2019

shchenz committed rG98189755cd98: [PowerPC] [NFC] change PPCLoopPreIncPrep class name after D67088. Afer https… (authored by shchenz).
[PowerPC] [NFC] change PPCLoopPreIncPrep class name after D67088. Afer https…
Nov 26 2019, 9:00 PM
shchenz closed D70371: [PowerPC] [NFC] rename PPCLoopPreIncPrep to PPCLoopInstrFormPrep after D67088.
Nov 26 2019, 9:00 PM · Restricted Project
shchenz abandoned D70704: [PowerPC] [NFC] rename PPCLoopPreIncPrep.cpp to PPCLoopInstrFormPrep.cpp after D67088.

is it caused by the way I sent out the review? I git mv the file, git diff to get diff patch and upload the diff patch here. Not sure which step is wrong. I will abandon this patch.

Nov 26 2019, 4:05 PM · Restricted Project
shchenz accepted D70716: [PowerPC] [NFC] rename PPCLoopPreIncPrep.cpp to PPCLoopInstrFormPrep.cpp after D67088.

LGTM

Nov 26 2019, 4:00 PM · Restricted Project

Nov 25 2019

shchenz added a comment to D70371: [PowerPC] [NFC] rename PPCLoopPreIncPrep to PPCLoopInstrFormPrep after D67088.

I don't think we should delete PPCLoopPreIncPrep.cpp, then add a new file PPCLoopInstrFormPrep.cpp.

I think we should use git mv to rename it, so that we can keep the history.

diff --git a/llvm/lib/Target/PowerPC/PPCLoopPreIncPrep.cpp b/llvm/lib/Target/PowerPC/PPCLoopInstrFormPrep.cpp
similarity index 100%
rename from llvm/lib/Target/PowerPC/PPCLoopPreIncPrep.cpp
rename to llvm/lib/Target/PowerPC/PPCLoopInstrFormPrep.cpp
Nov 25 2019, 6:57 PM · Restricted Project
shchenz added a parent revision for D70371: [PowerPC] [NFC] rename PPCLoopPreIncPrep to PPCLoopInstrFormPrep after D67088: D70704: [PowerPC] [NFC] rename PPCLoopPreIncPrep.cpp to PPCLoopInstrFormPrep.cpp after D67088.
Nov 25 2019, 6:54 PM · Restricted Project
shchenz updated the diff for D70371: [PowerPC] [NFC] rename PPCLoopPreIncPrep to PPCLoopInstrFormPrep after D67088.

Address @jsji comments.

Nov 25 2019, 6:54 PM · Restricted Project
shchenz added a child revision for D70704: [PowerPC] [NFC] rename PPCLoopPreIncPrep.cpp to PPCLoopInstrFormPrep.cpp after D67088: D70371: [PowerPC] [NFC] rename PPCLoopPreIncPrep to PPCLoopInstrFormPrep after D67088.
Nov 25 2019, 6:54 PM · Restricted Project
shchenz created D70704: [PowerPC] [NFC] rename PPCLoopPreIncPrep.cpp to PPCLoopInstrFormPrep.cpp after D67088.
Nov 25 2019, 6:54 PM · Restricted Project

Nov 24 2019

shchenz committed rGd1c16598b71c: Revert "[PowerPC] combine rlwinm+rlwinm to rlwinm" (authored by shchenz).
Revert "[PowerPC] combine rlwinm+rlwinm to rlwinm"
Nov 24 2019, 7:47 PM
shchenz added a reverting change for rG29f6f9b2b2bf: [PowerPC] combine rlwinm+rlwinm to rlwinm combine x3 = rlwinm x3, 27, 5, 31 x3…: rGd1c16598b71c: Revert "[PowerPC] combine rlwinm+rlwinm to rlwinm".
Nov 24 2019, 7:47 PM
shchenz added a comment to rG29f6f9b2b2bf: [PowerPC] combine rlwinm+rlwinm to rlwinm combine x3 = rlwinm x3, 27, 5, 31 x3….

It seems it needs a big endian machine to fail as all the little endian machines seem to be unaffected. And also it will fail in stage 2 not stage 1 as shown in the link.

Nov 24 2019, 7:20 PM
shchenz added a comment to rG29f6f9b2b2bf: [PowerPC] combine rlwinm+rlwinm to rlwinm combine x3 = rlwinm x3, 27, 5, 31 x3….

Hello,

This change set is breaking the buildbot :

clang-ppc64be-linux-multistage http://lab.llvm.org:8011/builders/clang-ppc64be-linux-multistage/builds/21918

Thanks,
Anil Mahmud

Nov 24 2019, 6:12 PM

Nov 21 2019

shchenz committed rG29f6f9b2b2bf: [PowerPC] combine rlwinm+rlwinm to rlwinm combine x3 = rlwinm x3, 27, 5, 31 x3… (authored by shchenz).
[PowerPC] combine rlwinm+rlwinm to rlwinm combine x3 = rlwinm x3, 27, 5, 31 x3…
Nov 21 2019, 9:09 PM
shchenz closed D70374: [PowerPC] combine rlwinm + rlwinm to rlwinm.
Nov 21 2019, 9:09 PM · Restricted Project
shchenz added a comment to D70223: [DAGCombine] Split vector load-update-store into single element stores.

This is a very good idea. Love it!.

Nov 21 2019, 1:19 AM · Restricted Project

Nov 20 2019

shchenz accepted D69601: [Power9] Implement the vector extend sign instruction pattern match.

Thanks for this exploitation. LGTM too.

Nov 20 2019, 10:55 PM · Restricted Project

Nov 19 2019

shchenz updated the diff for D70374: [PowerPC] combine rlwinm + rlwinm to rlwinm.

fix @steven.zhang comment and rebase after https://reviews.llvm.org/D69032 committed.

Nov 19 2019, 1:32 AM · Restricted Project
shchenz committed rGfd03be363421: [APInt] add wrap support for `setBits` and `getBitsSet` (authored by shchenz).
[APInt] add wrap support for `setBits` and `getBitsSet`
Nov 19 2019, 12:58 AM