[AArch64] Add SME 2 target feature for Armv8-A and Armv9-A 2022 Architecture Extension

[CarolineConcatto]

Summary

First patch in a series adding MC layer support for Scalable Matrix
Extension 2 (SME2).

This patch adds the following feature:

sme2

The 2022 Architecture Extension release adds other feature flags(eg.:sme2.1),
that will be in follow-up patches.

The reference can be found here:
https://developer.arm.com/documentation/ddi0602/2022-09

[sdesmalen]

llvm/test/MC/AArch64/SME2/feature.s

1

nit: Can you rename this test-file to something more descriptive, e.g. feature-sme2-implies-sme.s ?

[CarolineConcatto]

llvm/test/MC/AArch64/SME2/feature.s

1

Yes, not a problem.
That is just the same name we have for sme.
llvm/test/MC/AArch64/SME/feature.s

[CarolineConcatto]

• Change the test file name from feature.s to feature-sme2-implies-sme.s

[aemerson]

LGTM.

[CarolineConcatto]

Add sme2 feature in the unitest:

llvm/unittests/Support/TargetParserTest.cpp

Because
x64 debian > LLVM-Unit.Support/_/SupportTests/TargetParserTest::AArch64ExtensionFeatures
Script: -- /var/lib/buildkite-agent/builds/llvm-project/build/unittests/Support/./SupportTests --gtest_filter=TargetParserTest.AArch64ExtensionFeatures

llvm/include/llvm/Support/AArch64TargetParser.h

 //===-- AArch64TargetParser - Parser for AArch64 features -------*- C++ -*-===//
 //
 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
 // See https://llvm.org/LICENSE.txt for license information.
 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
 //
 //===----------------------------------------------------------------------===//
 //
 // This file implements a target parser to recognise AArch64 hardware features
enum ArchExtKind : uint64_t {
   AEK_PAUTH =       1ULL << 35, // FEAT_PAuth
   AEK_FLAGM =       1ULL << 36, // FEAT_FlagM
   AEK_SME =         1ULL << 37, // FEAT_SME
   AEK_SMEF64 =      1ULL << 38, // FEAT_SME_F64F64
   AEK_SMEI64 =      1ULL << 39, // FEAT_SME_I16I64
   AEK_HBC =         1ULL << 40, // FEAT_HBC
   AEK_MOPS =        1ULL << 41, // FEAT_MOPS
   AEK_PERFMON =     1ULL << 42, // FEAT_PMUv3
+  AEK_SME2 =        1ULL << 43, // FEAT_SME2
 };
 
 enum class ArchKind {
 #define AARCH64_ARCH(NAME, ID, CPU_ATTR, SUB_ARCH, ARCH_ATTR, ARCH_FPU, ARCH_BASE_EXT) ID,
 #include "AArch64TargetParser.def"
 };
 
 const ARM::ArchNames<ArchKind> AArch64ARCHNames[] = {

llvm/include/llvm/Support/AArch64TargetParser.def

 AARCH64_ARCH_EXT_NAME("tme",          AArch64::AEK_TME,         "+tme",          "-tme")
 AARCH64_ARCH_EXT_NAME("ls64",         AArch64::AEK_LS64,        "+ls64",         "-ls64")
 AARCH64_ARCH_EXT_NAME("brbe",         AArch64::AEK_BRBE,        "+brbe",         "-brbe")
 AARCH64_ARCH_EXT_NAME("pauth",        AArch64::AEK_PAUTH,       "+pauth",        "-pauth")
 AARCH64_ARCH_EXT_NAME("flagm",        AArch64::AEK_FLAGM,       "+flagm",        "-flagm")
 AARCH64_ARCH_EXT_NAME("sme",          AArch64::AEK_SME,         "+sme",          "-sme")
 AARCH64_ARCH_EXT_NAME("sme-f64",      AArch64::AEK_SMEF64,      "+sme-f64",      "-sme-f64")
 AARCH64_ARCH_EXT_NAME("sme-i64",      AArch64::AEK_SMEI64,      "+sme-i64",      "-sme-i64")
+AARCH64_ARCH_EXT_NAME("sme2",         AArch64::AEK_SME2,        "+sme2",         "-sme2")
 AARCH64_ARCH_EXT_NAME("hbc",          AArch64::AEK_HBC,         "+hbc",          "-hbc")
 AARCH64_ARCH_EXT_NAME("mops",         AArch64::AEK_MOPS,        "+mops",         "-mops")
 AARCH64_ARCH_EXT_NAME("pmuv3",        AArch64::AEK_PERFMON,     "+perfmon",      "-perfmon")
 #undef AARCH64_ARCH_EXT_NAME
 
 #ifndef AARCH64_CPU_NAME
 #define AARCH64_CPU_NAME(NAME, ID, DEFAULT_FPU, IS_DEFAULT, DEFAULT_EXT)
 #endif

llvm/lib/Target/AArch64/AArch64.td

def FeatureSME : SubtargetFeature<"sme", "HasSME", "true",
   "Enable Scalable Matrix Extension (SME) (FEAT_SME)", [FeatureBF16, FeatureUseScalarIncVL]>;
 
 def FeatureSMEF64 : SubtargetFeature<"sme-f64", "HasSMEF64", "true",
   "Enable Scalable Matrix Extension (SME) F64F64 instructions (FEAT_SME_F64F64)", [FeatureSME]>;
 
 def FeatureSMEI64 : SubtargetFeature<"sme-i64", "HasSMEI64", "true",
   "Enable Scalable Matrix Extension (SME) I16I64 instructions (FEAT_SME_I16I64)", [FeatureSME]>;
 
+def FeatureSME2 : SubtargetFeature<"sme2", "HasSME2", "true",
+  "Enable Scalable Matrix Extension 2 (SME2) instructions", [FeatureSME]>;
+
 def FeatureAppleA7SysReg  : SubtargetFeature<"apple-a7-sysreg", "HasAppleA7SysReg", "true",
   "Apple A7 (the CPU formerly known as Cyclone)">;
 
 def FeatureEL2VMSA : SubtargetFeature<"el2vmsa", "HasEL2VMSA", "true",
   "Enable Exception Level 2 Virtual Memory System Architecture">;
 
 def FeatureEL3 : SubtargetFeature<"el3", "HasEL3", "true",
   "Enable Exception Level 3">;
let F = [HasSVE, HasSVE2, HasSVE2AES, HasSVE2SM4, HasSVE2SHA3,
            HasSVE2BitPerm, HasSVEorSME, HasSVE2orSME];
 }
 
 def PAUnsupported : AArch64Unsupported {
   let F = [HasPAuth];
 }
 
 def SMEUnsupported : AArch64Unsupported {
-  let F = [HasSME, HasSMEF64, HasSMEI64];
+  let F = [HasSME, HasSMEF64, HasSMEI64, HasSME2];
 }
 
 include "AArch64SchedA53.td"
 include "AArch64SchedA55.td"
 include "AArch64SchedA57.td"
 include "AArch64SchedCyclone.td"
 include "AArch64SchedFalkor.td"
 include "AArch64SchedKryo.td"

llvm/lib/Target/AArch64/AArch64InstrInfo.td

 def HasSVE2BitPerm   : Predicate<"Subtarget->hasSVE2BitPerm()">,
                                  AssemblerPredicateWithAll<(all_of FeatureSVE2BitPerm), "sve2-bitperm">;
 def HasSME           : Predicate<"Subtarget->hasSME()">,
                                  AssemblerPredicateWithAll<(all_of FeatureSME), "sme">;
 def HasSMEF64        : Predicate<"Subtarget->hasSMEF64()">,
                                  AssemblerPredicateWithAll<(all_of FeatureSMEF64), "sme-f64">;
 def HasSMEI64        : Predicate<"Subtarget->hasSMEI64()">,
                                  AssemblerPredicateWithAll<(all_of FeatureSMEI64), "sme-i64">;
+def HasSME2          : Predicate<"Subtarget->hasSME2()">,
+                                 AssemblerPredicate<(all_of FeatureSME2), "sme2">;
 // A subset of SVE(2) instructions are legal in Streaming SVE execution mode,
 // they should be enabled if either has been specified.
 def HasSVEorSME
     : Predicate<"Subtarget->hasSVE() || Subtarget->hasSME()">,
                 AssemblerPredicateWithAll<(any_of FeatureSVE, FeatureSME),
                 "sve or sme">;
 def HasSVE2orSME
     : Predicate<"Subtarget->hasSVE2() || Subtarget->hasSME()">,

llvm/lib/Target/AArch64/AArch64SchedA64FX.td

def A64FXModel : SchedMachineModel {
   let MispredictPenalty     =  12; // Extra cycles for mispredicted branch.
   // Determined via a mix of micro-arch details and experimentation.
   let LoopMicroOpBufferSize = 128;
   let PostRAScheduler       =   1; // Using PostRA sched.
   let CompleteModel         =   1;
 
   list<Predicate> UnsupportedFeatures =
     [HasSVE2, HasSVE2AES, HasSVE2SM4, HasSVE2SHA3, HasSVE2BitPerm, HasPAuth,
-     HasSVE2orSME, HasMTE, HasMatMulInt8, HasBF16];
+     HasSVE2orSME, HasMTE, HasMatMulInt8, HasBF16, HasSME2];
 
   let FullInstRWOverlapCheck = 0;
 }
 
 let SchedModel = A64FXModel in {
 
 // Define the issue ports.
 

llvm/lib/Target/AArch64/AArch64SchedThunderX3T110.td

def ThunderX3T110Model : SchedMachineModel {
   let MispredictPenalty     =  12; // Extra cycles for mispredicted branch.
   // Determined via a mix of micro-arch details and experimentation.
   let LoopMicroOpBufferSize = 128; // FIXME: might be much bigger in TX3.
   let PostRAScheduler       =   1; // Using PostRA sched.
   let CompleteModel         =   1;
 
   list<Predicate> UnsupportedFeatures = !listconcat(SVEUnsupported.F,
                                                     PAUnsupported.F,
+                                                    SMEUnsupported.F,
                                                     [HasMTE]);
   // FIXME: Remove when all errors have been fixed.
   let FullInstRWOverlapCheck = 0;
 }
 
 let SchedModel = ThunderX3T110Model in {
 
 // Issue ports.

llvm/test/MC/AArch64/SME2/feature.s

+// This test verifies SME2 implies SME.
+
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2  2>&1 < %s \
+// RUN:        | FileCheck %s
+
+addha   za0.s, p0/m, p0/m, z0.s
+// CHECK-NOT: instruction requires: sme
+// CHECK: addha   za0.s, p0/m, p0/m, z0.s