[AArch64]SME2 Non-contiguous load and store

[CarolineConcatto]

Summary

This patch adds the assembly/disassembly for the following instruction:

Non-constiguous load with stride resgisters:

LD1B (scalar + immediate): Contiguous load of bytes to multiple strided vectors (immediate index).
     (scalar + scalar): Contiguous load of bytes to multiple strided vectors (scalar index).
LD1D (scalar + immediate): Contiguous load of doublewords to multiple strided vectors (immediate index).
     (scalar + scalar): Contiguous load of doublewords to multiple strided vectors (scalar index).
LD1H (scalar + immediate): Contiguous load of halfwords to multiple strided vectors (immediate index).
     (scalar + scalar): Contiguous load of halfwords to multiple strided vectors (scalar index).
LD1W (scalar + immediate): Contiguous load of words to multiple strided vectors (immediate index).
     (scalar + scalar): Contiguous load of words to multiple strided vectors (scalar index).

LDNT1B (scalar + immediate): Contiguous load non-temporal of bytes to multiple strided vectors (immediate index).
       (scalar + scalar): Contiguous load non-temporal of bytes to multiple strided vectors (scalar index).
LDNT1D (scalar + immediate): Contiguous load non-temporal of doublewords to multiple strided vectors (immediate index).
       (scalar + scalar): Contiguous load non-temporal of doublewords to multiple strided vectors (scalar index).
LDNT1H (scalar + immediate): Contiguous load non-temporal of halfwords to multiple strided vectors (immediate index).
       (scalar + scalar): Contiguous load non-temporal of halfwords to multiple strided vectors (scalar index).
LDNT1W (scalar + immediate): Contiguous load non-temporal of words to multiple strided vectors (immediate index).
       (scalar + scalar): Contiguous load non-temporal of words to multiple strided vectors (scalar index).

Non-constiguous store with stride resgisters:

ST1B (scalar + immediate): Contiguous store of bytes from multiple strided vectors (immediate index).
     (scalar + scalar): Contiguous store of bytes from multiple strided vectors (scalar index).
ST1D (scalar + immediate): Contiguous store of doublewords from multiple strided vectors (immediate index).
     (scalar + scalar): Contiguous store of doublewords from multiple strided vectors (scalar index).
ST1H (scalar + immediate): Contiguous store of halfwords from multiple strided vectors (immediate index).
     (scalar + scalar): Contiguous store of halfwords from multiple strided vectors (scalar index).
ST1W (scalar + immediate): Contiguous store of words from multiple strided vectors (immediate index).
     (scalar + scalar): Contiguous store of words from multiple strided vectors (scalar index).

STNT1B (scalar + immediate): Contiguous store non-temporal of bytes from multiple strided vectors (immediate index).
       (scalar + scalar): Contiguous store non-temporal of bytes from multiple strided vectors (scalar index).
STNT1D (scalar + immediate): Contiguous store non-temporal of doublewords from multiple strided vectors (immediate index).
       (scalar + scalar): Contiguous store non-temporal of doublewords from multiple strided vectors (scalar index).
STNT1H (scalar + immediate): Contiguous store non-temporal of halfwords from multiple strided vectors (immediate index).
       (scalar + scalar): Contiguous store non-temporal of halfwords from multiple strided vectors (scalar index).
STNT1W (scalar + immediate): Contiguous store non-temporal of words from multiple strided vectors (immediate index).
       (scalar + scalar): Contiguous store non-temporal of words from multiple strided vectors (scalar index).

The reference can be found here:

https://developer.arm.com/documentation/ddi0602/2022-09

This patch also adds a new SVE vector list to represent the stride loads/stores
ZPRVectorListStrided and the sets of 2 and 4 ZA registers:
ZZ_[b|h|w|d]_strided and ZZZZ_[b|h|w|d]_strided

Depends on: D136172

[CarolineConcatto]

-Rebase

[CarolineConcatto]

It is merged with https://reviews.llvm.org/D136172.

llvm/lib/Target/AArch64/AArch64RegisterInfo.td

def ZZZZ_d_mul_r : RegisterOperand<ZPR4Mul4, "printTypedVectorList<0,'d'>"> {
     let ParserMatchClass = ZPRVectorListMul<64, 4>;
   }
 
   def ZZZZ_q_mul_r : RegisterOperand<ZPR4, "printTypedVectorList<0,'q'>"> {
     let ParserMatchClass = ZPRVectorListMul<128, 4>;
   }
 } // end let EncoderMethod/DecoderMethod
 
+// SME2 strided multi-vector operands
+
+// ZStridedPairs
+//
+// A group of two Z vectors with strided numbering consisting of:
+//   Zn+0.T and Zn+8.T
+// where n is in the range 0 to 7 and 16 to 23 inclusive, and T is one of B, H,
+// S, or D.
+
+// Z0_Z8, Z1_Z9, Z2_Z10, Z3_Z11, Z4_Z12, Z5_Z13, Z6_Z14, Z7_Z15
+def ZStridedPairsLo : RegisterTuples<[zsub0, zsub1], [
+  (trunc (rotl ZPR, 0), 8), (trunc (rotl ZPR, 8), 8)
+]>;
+
+// Z16_Z24, Z17_Z25, Z18_Z26, Z19_Z27, Z20_Z28, Z21_Z29, Z22_Z30, Z23_Z31
+def ZStridedPairsHi : RegisterTuples<[zsub0, zsub1], [
+  (trunc (rotl ZPR, 16), 8), (trunc (rotl ZPR, 24), 8)
+]>;
+
+// ZStridedQuads
+//
+// A group of four Z vectors with strided numbering consisting of:
+//   Zn+0.T, Zn+4.T, Zn+8.T and Zn+12.T
+// where n is in the range 0 to 3 and 16 to 19 inclusive, and T is one of B, H,
+// S, or D.
+
+// Z0_Z4_Z8_Z12, Z1_Z5_Z9_Z13, Z2_Z6_Z10_Z14, Z3_Z7_Z11_Z15
+def ZStridedQuadsLo : RegisterTuples<[zsub0, zsub1, zsub2, zsub3], [
+  (trunc (rotl ZPR, 0), 4), (trunc (rotl ZPR, 4), 4),
+  (trunc (rotl ZPR, 8), 4), (trunc (rotl ZPR, 12), 4)
+]>;
+// Z16_Z20_Z24_Z28, Z17_Z21_Z25_Z29, Z18_Z22_Z26_Z30, Z19_Z23_Z27_Z31
+def ZStridedQuadsHi : RegisterTuples<[zsub0, zsub1, zsub2, zsub3], [
+  (trunc (rotl ZPR, 16), 4), (trunc (rotl ZPR, 20), 4),
+  (trunc (rotl ZPR, 24), 4), (trunc (rotl ZPR, 28), 4)
+]>;
+
+def ZPR2Strided : RegisterClass<"AArch64", [untyped], 256,
+                                (add ZStridedPairsLo, ZStridedPairsHi)>  {
+  let Size = 256;
+}
+def ZPR4Strided : RegisterClass<"AArch64", [untyped], 512,
+                                (add ZStridedQuadsLo, ZStridedQuadsHi)>  {
+  let Size = 512;
+}
+
+
+class ZPRVectorListStrided<int ElementWidth, int NumRegs, int Stride>
+    : ZPRVectorList<ElementWidth, NumRegs> {
+  let Name = "SVEVectorListStrided" # NumRegs # "x" # ElementWidth;
+  let DiagnosticType = "Invalid" # Name;
+  let PredicateMethod = "isTypedVectorListStrided<RegKind::SVEDataVector, "
+                        # NumRegs # "," # Stride # "," # ElementWidth # ">";
+  let RenderMethod = "addStridedVectorListOperands<" # NumRegs # ">";
+}
+
+let EncoderMethod = "EncodeZPR2StridedRegisterClass",
+    DecoderMethod = "DecodeZPR2StridedRegisterClass" in {
+  def ZZ_b_strided
+      : RegisterOperand<ZPR2Strided, "printTypedVectorList<0, 'b'>"> {
+    let ParserMatchClass = ZPRVectorListStrided<8, 2, 8>;
+  }
+
+  def ZZ_h_strided
+      : RegisterOperand<ZPR2Strided, "printTypedVectorList<0, 'h'>"> {
+    let ParserMatchClass = ZPRVectorListStrided<16, 2, 8>;
+  }
+
+  def ZZ_s_strided
+      : RegisterOperand<ZPR2Strided, "printTypedVectorList<0,'s'>"> {
+    let ParserMatchClass = ZPRVectorListStrided<32, 2, 8>;
+  }
+
+  def ZZ_d_strided
+      : RegisterOperand<ZPR2Strided, "printTypedVectorList<0,'d'>"> {
+    let ParserMatchClass = ZPRVectorListStrided<64, 2, 8>;
+  }
+}
+
+let EncoderMethod = "EncodeZPR4StridedRegisterClass",
+    DecoderMethod = "DecodeZPR4StridedRegisterClass" in {
+  def ZZZZ_b_strided
+      : RegisterOperand<ZPR4Strided, "printTypedVectorList<0,'b'>"> {
+    let ParserMatchClass = ZPRVectorListStrided<8, 4, 4>;
+  }
+
+  def ZZZZ_h_strided
+      : RegisterOperand<ZPR4Strided, "printTypedVectorList<0,'h'>"> {
+    let ParserMatchClass = ZPRVectorListStrided<16, 4, 4>;
+  }
+
+  def ZZZZ_s_strided
+      : RegisterOperand<ZPR4Strided, "printTypedVectorList<0,'s'>"> {
+    let ParserMatchClass = ZPRVectorListStrided<32, 4, 4>;
+  }
+
+  def ZZZZ_d_strided
+      : RegisterOperand<ZPR4Strided, "printTypedVectorList<0,'d'>"> {
+    let ParserMatchClass = ZPRVectorListStrided<64, 4, 4>;
+  }
+}
+
 class ZPRExtendAsmOperand<string ShiftExtend, int RegWidth, int Scale,
                           bit ScaleAlwaysSame = 0b0> : AsmOperandClass {
   let Name = "ZPRExtend" # ShiftExtend # RegWidth # Scale
                          # !if(ScaleAlwaysSame, "Only", "");
 
   let PredicateMethod = "isSVEDataVectorRegWithShiftExtend<"
                           # RegWidth # ", AArch64::ZPRRegClassID, "
                           # "AArch64_AM::" # ShiftExtend # ", "

llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td

 defm FRINTM_4Z4Z: sme2_frint_vector_vg4_multi<"frintm", 0b010>;
 defm FRINTN_2Z2Z: sme2_frint_vector_vg2_multi<"frintn", 0b000>;
 defm FRINTN_4Z4Z: sme2_frint_vector_vg4_multi<"frintn", 0b000>;
 defm FRINTP_2Z2Z: sme2_frint_vector_vg2_multi<"frintp", 0b001>;
 defm FRINTP_4Z4Z: sme2_frint_vector_vg4_multi<"frintp", 0b001>;
 
 defm SEL_VG2_2ZP2Z2Z: sme2_sel_vector_vg2<"sel">;
 defm SEL_VG4_4ZP4Z4Z: sme2_sel_vector_vg4<"sel">;
+
+def  LD1B_VG2_M2ZPXX : sme2_ld_vector_vg2_multi_scalar_scalar<0b00, 0b0,    ZZ_b_strided,    GPR64shifted8, "ld1b">;
+def  LD1B_VG4_M4ZPXX : sme2_ld_vector_vg4_multi_scalar_scalar<0b00, 0b0,    ZZZZ_b_strided,  GPR64shifted8, "ld1b">;
+defm LD1B_VG2_M2ZPXI : sme2_ld_vector_vg2_multi_scalar_immediate<0b00, 0b0, ZZ_b_strided,    simm4s2, "ld1b">;
+defm LD1B_VG4_M4ZPXI : sme2_ld_vector_vg4_multi_scalar_immediate<0b00, 0b0, ZZZZ_b_strided,  simm4s4, "ld1b">;
+def  LD1H_VG2_M2ZPXX : sme2_ld_vector_vg2_multi_scalar_scalar<0b01, 0b0,    ZZ_h_strided,    GPR64shifted16, "ld1h">;
+def  LD1H_VG4_M4ZPXX : sme2_ld_vector_vg4_multi_scalar_scalar<0b01, 0b0,    ZZZZ_h_strided,  GPR64shifted16, "ld1h">;
+defm LD1H_VG2_M2ZPXI : sme2_ld_vector_vg2_multi_scalar_immediate<0b01, 0b0, ZZ_h_strided,    simm4s2, "ld1h">;
+defm LD1H_VG4_M4ZPXI : sme2_ld_vector_vg4_multi_scalar_immediate<0b01, 0b0, ZZZZ_h_strided,  simm4s4, "ld1h">;
+def  LD1W_VG2_M2ZPXX : sme2_ld_vector_vg2_multi_scalar_scalar<0b10, 0b0,    ZZ_s_strided,    GPR64shifted32, "ld1w">;
+def  LD1W_VG4_M4ZPXX : sme2_ld_vector_vg4_multi_scalar_scalar<0b10, 0b0,    ZZZZ_s_strided,  GPR64shifted32, "ld1w">;
+defm LD1W_VG2_M2ZPXI : sme2_ld_vector_vg2_multi_scalar_immediate<0b10, 0b0, ZZ_s_strided,    simm4s2, "ld1w">;
+defm LD1W_VG4_M4ZPXI : sme2_ld_vector_vg4_multi_scalar_immediate<0b10, 0b0, ZZZZ_s_strided,  simm4s4, "ld1w">;
+def  LD1D_VG2_M2ZPXX : sme2_ld_vector_vg2_multi_scalar_scalar<0b11, 0b0,    ZZ_d_strided,    GPR64shifted64, "ld1d">;
+def  LD1D_VG4_M4ZPXX : sme2_ld_vector_vg4_multi_scalar_scalar<0b11, 0b0,    ZZZZ_d_strided,  GPR64shifted64, "ld1d">;
+defm LD1D_VG2_M2ZPXI : sme2_ld_vector_vg2_multi_scalar_immediate<0b11, 0b0, ZZ_d_strided,    simm4s2, "ld1d">;
+defm LD1D_VG4_M4ZPXI : sme2_ld_vector_vg4_multi_scalar_immediate<0b11, 0b0, ZZZZ_d_strided,  simm4s4, "ld1d">;
+
+def  LDNT1B_VG2_M2ZPXX : sme2_ld_vector_vg2_multi_scalar_scalar<0b00, 0b1,    ZZ_b_strided,   GPR64shifted8, "ldnt1b">;
+def  LDNT1B_VG4_M4ZPXX : sme2_ld_vector_vg4_multi_scalar_scalar<0b00, 0b1,    ZZZZ_b_strided, GPR64shifted8, "ldnt1b">;
+defm LDNT1B_VG2_M2ZPXI : sme2_ld_vector_vg2_multi_scalar_immediate<0b00, 0b1, ZZ_b_strided,   simm4s2, "ldnt1b">;
+defm LDNT1B_VG4_M4ZPXI : sme2_ld_vector_vg4_multi_scalar_immediate<0b00, 0b1, ZZZZ_b_strided, simm4s4, "ldnt1b">;
+def  LDNT1H_VG2_M2ZPXX : sme2_ld_vector_vg2_multi_scalar_scalar<0b01, 0b1,    ZZ_h_strided,   GPR64shifted16, "ldnt1h">;
+def  LDNT1H_VG4_M4ZPXX : sme2_ld_vector_vg4_multi_scalar_scalar<0b01, 0b1,    ZZZZ_h_strided, GPR64shifted16, "ldnt1h">;
+defm LDNT1H_VG2_M2ZPXI : sme2_ld_vector_vg2_multi_scalar_immediate<0b01, 0b1, ZZ_h_strided,   simm4s2, "ldnt1h">;
+defm LDNT1H_VG4_M4ZPXI : sme2_ld_vector_vg4_multi_scalar_immediate<0b01, 0b1, ZZZZ_h_strided, simm4s4, "ldnt1h">;
+def  LDNT1W_VG2_M2ZPXX : sme2_ld_vector_vg2_multi_scalar_scalar<0b10, 0b1,    ZZ_s_strided,   GPR64shifted32, "ldnt1w">;
+def  LDNT1W_VG4_M4ZPXX : sme2_ld_vector_vg4_multi_scalar_scalar<0b10, 0b1,    ZZZZ_s_strided, GPR64shifted32, "ldnt1w">;
+defm LDNT1W_VG2_M2ZPXI : sme2_ld_vector_vg2_multi_scalar_immediate<0b10, 0b1, ZZ_s_strided,   simm4s2, "ldnt1w">;
+defm LDNT1W_VG4_M4ZPXI : sme2_ld_vector_vg4_multi_scalar_immediate<0b10, 0b1, ZZZZ_s_strided, simm4s4, "ldnt1w">;
+def  LDNT1D_VG2_M2ZPXX : sme2_ld_vector_vg2_multi_scalar_scalar<0b11, 0b1,    ZZ_d_strided,   GPR64shifted64, "ldnt1d">;
+def  LDNT1D_VG4_M4ZPXX : sme2_ld_vector_vg4_multi_scalar_scalar<0b11, 0b1,    ZZZZ_d_strided, GPR64shifted64, "ldnt1d">;
+defm LDNT1D_VG2_M2ZPXI : sme2_ld_vector_vg2_multi_scalar_immediate<0b11, 0b1, ZZ_d_strided,   simm4s2, "ldnt1d">;
+defm LDNT1D_VG4_M4ZPXI : sme2_ld_vector_vg4_multi_scalar_immediate<0b11, 0b1, ZZZZ_d_strided, simm4s4, "ldnt1d">;
+
+def  ST1B_VG2_M2ZPXX : sme2_st_vector_vg2_multi_scalar_scalar<0b00, 0b0,     ZZ_b_strided,   GPR64shifted8, "st1b">;
+def  ST1B_VG4_M4ZPXX : sme2_st_vector_vg4_multi_scalar_scalar<0b00, 0b0,     ZZZZ_b_strided, GPR64shifted8, "st1b">;
+defm ST1B_VG2_M2ZPXI : sme2_st_vector_vg2_multi_scalar_immediate<0b00, 0b0,  ZZ_b_strided,   simm4s2, "st1b">;
+defm ST1B_VG4_M4ZPXI : sme2_st_vector_vg4_multi_scalar_immediate<0b00, 0b0,  ZZZZ_b_strided, simm4s4, "st1b">;
+def  ST1H_VG2_M2ZPXX : sme2_st_vector_vg2_multi_scalar_scalar<0b01, 0b0,     ZZ_h_strided,   GPR64shifted16, "st1h">;
+def  ST1H_VG4_M4ZPXX : sme2_st_vector_vg4_multi_scalar_scalar<0b01, 0b0,     ZZZZ_h_strided, GPR64shifted16, "st1h">;
+defm ST1H_VG2_M2ZPXI : sme2_st_vector_vg2_multi_scalar_immediate<0b01, 0b0,  ZZ_h_strided,   simm4s2, "st1h">;
+defm ST1H_VG4_M4ZPXI : sme2_st_vector_vg4_multi_scalar_immediate<0b01, 0b0,  ZZZZ_h_strided, simm4s4, "st1h">;
+def  ST1W_VG2_M2ZPXX : sme2_st_vector_vg2_multi_scalar_scalar<0b10, 0b0,     ZZ_s_strided,   GPR64shifted32, "st1w">;
+def  ST1W_VG4_M4ZPXX : sme2_st_vector_vg4_multi_scalar_scalar<0b10, 0b0,     ZZZZ_s_strided, GPR64shifted32, "st1w">;
+defm ST1W_VG2_M2ZPXI : sme2_st_vector_vg2_multi_scalar_immediate<0b10, 0b0,  ZZ_s_strided,   simm4s2, "st1w">;
+defm ST1W_VG4_M4ZPXI : sme2_st_vector_vg4_multi_scalar_immediate<0b10, 0b0,  ZZZZ_s_strided, simm4s4, "st1w">;
+def  ST1D_VG2_M2ZPXX : sme2_st_vector_vg2_multi_scalar_scalar<0b11, 0b0,     ZZ_d_strided,   GPR64shifted64, "st1d">;
+def  ST1D_VG4_M4ZPXX : sme2_st_vector_vg4_multi_scalar_scalar<0b11, 0b0,     ZZZZ_d_strided, GPR64shifted64, "st1d">;
+defm ST1D_VG2_M2ZPXI : sme2_st_vector_vg2_multi_scalar_immediate<0b11, 0b0,  ZZ_d_strided,   simm4s2, "st1d">;
+defm ST1D_VG4_M4ZPXI : sme2_st_vector_vg4_multi_scalar_immediate<0b11, 0b0, ZZZZ_d_strided,  simm4s4, "st1d">;
+
+def  STNT1B_VG2_M2ZPXX : sme2_st_vector_vg2_multi_scalar_scalar<0b00, 0b1,    ZZ_b_strided,   GPR64shifted8, "stnt1b">;
+def  STNT1B_VG4_M4ZPXX : sme2_st_vector_vg4_multi_scalar_scalar<0b00, 0b1,    ZZZZ_b_strided, GPR64shifted8, "stnt1b">;
+defm STNT1B_VG2_M2ZPXI : sme2_st_vector_vg2_multi_scalar_immediate<0b00, 0b1, ZZ_b_strided,   simm4s2, "stnt1b">;
+defm STNT1B_VG4_M4ZPXI : sme2_st_vector_vg4_multi_scalar_immediate<0b00, 0b1, ZZZZ_b_strided, simm4s4, "stnt1b">;
+def  STNT1H_VG2_M2ZPXX : sme2_st_vector_vg2_multi_scalar_scalar<0b01, 0b1,    ZZ_h_strided,   GPR64shifted16, "stnt1h">;
+def  STNT1H_VG4_M4ZPXX : sme2_st_vector_vg4_multi_scalar_scalar<0b01, 0b1,    ZZZZ_h_strided, GPR64shifted16, "stnt1h">;
+defm STNT1H_VG2_M2ZPXI : sme2_st_vector_vg2_multi_scalar_immediate<0b01, 0b1, ZZ_h_strided,   simm4s2, "stnt1h">;
+defm STNT1H_VG4_M4ZPXI : sme2_st_vector_vg4_multi_scalar_immediate<0b01, 0b1, ZZZZ_h_strided, simm4s4, "stnt1h">;
+def  STNT1W_VG2_M2ZPXX : sme2_st_vector_vg2_multi_scalar_scalar<0b10, 0b1,    ZZ_s_strided,   GPR64shifted32, "stnt1w">;
+def  STNT1W_VG4_M4ZPXX : sme2_st_vector_vg4_multi_scalar_scalar<0b10, 0b1,    ZZZZ_s_strided, GPR64shifted32, "stnt1w">;
+defm STNT1W_VG2_M2ZPXI : sme2_st_vector_vg2_multi_scalar_immediate<0b10, 0b1, ZZ_s_strided,   simm4s2, "stnt1w">;
+defm STNT1W_VG4_M4ZPXI : sme2_st_vector_vg4_multi_scalar_immediate<0b10, 0b1, ZZZZ_s_strided, simm4s4, "stnt1w">;
+def  STNT1D_VG2_M2ZPXX : sme2_st_vector_vg2_multi_scalar_scalar<0b11, 0b1,    ZZ_d_strided,   GPR64shifted64, "stnt1d">;
+def  STNT1D_VG4_M4ZPXX : sme2_st_vector_vg4_multi_scalar_scalar<0b11, 0b1,    ZZZZ_d_strided, GPR64shifted64, "stnt1d">;
+defm STNT1D_VG2_M2ZPXI : sme2_st_vector_vg2_multi_scalar_immediate<0b11, 0b1, ZZ_d_strided,   simm4s2, "stnt1d">;
+defm STNT1D_VG4_M4ZPXI : sme2_st_vector_vg4_multi_scalar_immediate<0b11, 0b1, ZZZZ_d_strided, simm4s4, "stnt1d">;
 }
 
 let Predicates = [HasSME2, HasSMEI16I64] in {
 defm ADD_VG2_M2ZZ_D  : sme2_dot_mla_add_sub_array_vg24_single<"add", 0b1011010, MatrixOp64, ZZ_d, ZPR4b64>;
 defm ADD_VG4_M4ZZ_D  : sme2_dot_mla_add_sub_array_vg24_single<"add", 0b1111010, MatrixOp64, ZZZZ_d, ZPR4b64>;
 defm ADD_VG2_M2Z2Z_D : sme2_dot_mla_add_sub_array_vg2_multi<"add", 0b111010, MatrixOp64, ZZ_d_mul_r>;
 defm ADD_VG4_M4Z4Z_D : sme2_dot_mla_add_sub_array_vg4_multi<"add", 0b111010, MatrixOp64, ZZZZ_d_mul_r>;
 

llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp

private:
   bool parseDirectiveSEHMachineFrame(SMLoc L);
   bool parseDirectiveSEHContext(SMLoc L);
   bool parseDirectiveSEHClearUnwoundToCall(SMLoc L);
   bool parseDirectiveSEHPACSignLR(SMLoc L);
   bool parseDirectiveSEHSaveAnyReg(SMLoc L, bool Paired, bool Writeback);
 
   bool validateInstruction(MCInst &Inst, SMLoc &IDLoc,
                            SmallVectorImpl<SMLoc> &Loc);
+  unsigned getNumRegsForRegKind(RegKind K);
   bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
                                OperandVector &Operands, MCStreamer &Out,
                                uint64_t &ErrorInfo,
                                bool MatchingInlineAsm) override;
 /// @name Auto-generated Match Functions
 /// {
 
 #define GET_ASSEMBLER_HEADER
private:
 
   struct MatrixTileListOp {
     unsigned RegMask = 0;
   };
 
   struct VectorListOp {
     unsigned RegNum;
     unsigned Count;
+    unsigned Stride;
     unsigned NumElements;
     unsigned ElementWidth;
     RegKind  RegisterKind;
   };
 
   struct VectorIndexOp {
     int Val;
   };
unsigned getVectorListStart() const {
     return VectorList.RegNum;
   }
 
   unsigned getVectorListCount() const {
     assert(Kind == k_VectorList && "Invalid access!");
     return VectorList.Count;
   }
 
+  unsigned getVectorListStride() const {
+    assert(Kind == k_VectorList && "Invalid access!");
+    return VectorList.Stride;
+  }
+
   int getVectorIndex() const {
     assert(Kind == k_VectorIndex && "Invalid access!");
     return VectorIndex.Val;
   }
 
   StringRef getSysReg() const {
     assert(Kind == k_SysReg && "Invalid access!");
     return StringRef(SysReg.Data, SysReg.Length);
public:
   template <RegKind VectorKind, unsigned NumRegs>
   bool isImplicitlyTypedVectorList() const {
     return Kind == k_VectorList && VectorList.Count == NumRegs &&
            VectorList.NumElements == 0 &&
            VectorList.RegisterKind == VectorKind;
   }
 
   template <RegKind VectorKind, unsigned NumRegs, unsigned NumElements,
-            unsigned ElementWidth>
+            unsigned ElementWidth, unsigned Stride = 1>
   bool isTypedVectorList() const {
     if (Kind != k_VectorList)
       return false;
     if (VectorList.Count != NumRegs)
       return false;
     if (VectorList.RegisterKind != VectorKind)
       return false;
     if (VectorList.ElementWidth != ElementWidth)
       return false;
+    if (VectorList.Stride != Stride)
+      return false;
     return VectorList.NumElements == NumElements;
   }
 
   template <RegKind VectorKind, unsigned NumRegs, unsigned NumElements,
             unsigned ElementWidth>
   DiagnosticPredicate isTypedVectorListMultiple() const {
     bool Res =
         isTypedVectorList<VectorKind, NumRegs, NumElements, ElementWidth>();
     if (!Res)
       return DiagnosticPredicateTy::NoMatch;
     if (((VectorList.RegNum - AArch64::Z0) % NumRegs) != 0)
       return DiagnosticPredicateTy::NearMatch;
     return DiagnosticPredicateTy::Match;
   }
 
+  template <RegKind VectorKind, unsigned NumRegs, unsigned Stride,
+            unsigned ElementWidth>
+  DiagnosticPredicate isTypedVectorListStrided() const {
+    if (Kind != k_VectorList)
+      return DiagnosticPredicateTy::NoMatch;
+    if (VectorList.Count != NumRegs)
+      return DiagnosticPredicateTy::NoMatch;
+    if (VectorList.RegisterKind != VectorKind)
+      return DiagnosticPredicateTy::NoMatch;
+    if (VectorList.NumElements != 0)
+      return DiagnosticPredicateTy::NoMatch;
+    if (VectorList.ElementWidth != ElementWidth)
+      return DiagnosticPredicateTy::NearMatch;
+    if (VectorList.Stride != Stride)
+      return DiagnosticPredicateTy::NearMatch;
+    if ((VectorList.RegNum < (AArch64::Z0 + Stride)) ||
+        ((VectorList.RegNum >= AArch64::Z16) &&
+         (VectorList.RegNum < (AArch64::Z16 + Stride))))
+      return DiagnosticPredicateTy::Match;
+    return DiagnosticPredicateTy::NoMatch;
+  }
+
   template <int Min, int Max>
   DiagnosticPredicate isVectorIndex() const {
     if (Kind != k_VectorIndex)
       return DiagnosticPredicateTy::NoMatch;
     if (VectorIndex.Val >= Min && VectorIndex.Val <= Max)
       return DiagnosticPredicateTy::Match;
     return DiagnosticPredicateTy::NearMatch;
   }
void addVectorListOperands(MCInst &Inst, unsigned N) const {
     assert((RegTy != VecListIdx_ZReg || NumRegs <= 4) &&
            " NumRegs must be <= 4 for ZRegs");
 
     unsigned FirstReg = FirstRegs[(unsigned)RegTy][NumRegs];
     Inst.addOperand(MCOperand::createReg(FirstReg + getVectorListStart() -
                                          FirstRegs[(unsigned)RegTy][0]));
   }
 
+  template <unsigned NumRegs>
+  void addStridedVectorListOperands(MCInst &Inst, unsigned N) const {
+    assert(N == 1 && "Invalid number of operands!");
+    assert((NumRegs == 2 || NumRegs == 4) && " NumRegs must be 2 or 4");
+
+    switch (NumRegs) {
+    case 2:
+      if ((getVectorListStart() - AArch64::Z0) < 16)
+        Inst.addOperand(MCOperand::createReg(
+            AArch64::Z0_Z8 + getVectorListStart() - AArch64::Z0));
+      else
+        Inst.addOperand(MCOperand::createReg(
+            AArch64::Z16_Z24 + getVectorListStart() - AArch64::Z16));
+      break;
+    case 4:
+      if ((getVectorListStart() - AArch64::Z0) < 16)
+        Inst.addOperand(MCOperand::createReg(
+            AArch64::Z0_Z4_Z8_Z12 + getVectorListStart() - AArch64::Z0));
+      else
+        Inst.addOperand(MCOperand::createReg(
+            AArch64::Z16_Z20_Z24_Z28 + getVectorListStart() - AArch64::Z16));
+      break;
+    default:
+      llvm_unreachable("Unsupported number of registers for strided vec list");
+    }
+  }
+
   void addMatrixTileListOperands(MCInst &Inst, unsigned N) const {
     assert(N == 1 && "Invalid number of operands!");
     unsigned RegMask = getMatrixTileListRegMask();
     assert(RegMask <= 0xFF && "Invalid mask!");
     Inst.addOperand(MCOperand::createImm(RegMask));
   }
 
   void addVectorIndexOperands(MCInst &Inst, unsigned N) const {
assert((Kind == RegKind::NeonVector || Kind == RegKind::SVEDataVector ||
            "Invalid vector kind");
     auto Op = CreateReg(RegNum, Kind, S, E, Ctx, EqualsReg, ExtTy, ShiftAmount,
                         HasExplicitAmount);
     Op->Reg.ElementWidth = ElementWidth;
     return Op;
   }
 
   static std::unique_ptr<AArch64Operand>
-  CreateVectorList(unsigned RegNum, unsigned Count, unsigned NumElements,
-                   unsigned ElementWidth, RegKind RegisterKind, SMLoc S, SMLoc E,
-                   MCContext &Ctx) {
+  CreateVectorList(unsigned RegNum, unsigned Count, unsigned Stride,
+                   unsigned NumElements, unsigned ElementWidth,
+                   RegKind RegisterKind, SMLoc S, SMLoc E, MCContext &Ctx) {
     auto Op = std::make_unique<AArch64Operand>(k_VectorList, Ctx);
     Op->VectorList.RegNum = RegNum;
     Op->VectorList.Count = Count;
+    Op->VectorList.Stride = Stride;
     Op->VectorList.NumElements = NumElements;
     Op->VectorList.ElementWidth = ElementWidth;
     Op->VectorList.RegisterKind = RegisterKind;
     Op->StartLoc = S;
     Op->EndLoc = E;
     return Op;
   }
 
void AArch64Operand::print(raw_ostream &OS) const {
   }
   case k_CondCode:
     OS << "<condcode " << getCondCode() << ">";
     break;
   case k_VectorList: {
     OS << "<vectorlist ";
     unsigned Reg = getVectorListStart();
     for (unsigned i = 0, e = getVectorListCount(); i != e; ++i)
-      OS << Reg + i << " ";
+      OS << Reg + i * getVectorListStride() << " ";
     OS << ">";
     break;
   }
   case k_VectorIndex:
     OS << "<vectorindex " << getVectorIndex() << ">";
     break;
   case k_SysReg:
     OS << "<sysreg: " << getSysReg() << '>';
if (!RegNum) {
 
     // set RegNum if the match is the right kind of register
     if (Kind == Entry->getValue().first)
       RegNum = Entry->getValue().second;
   }
   return RegNum;
 }
 
+unsigned AArch64AsmParser::getNumRegsForRegKind(RegKind K) {
+  switch (K) {
+  case RegKind::Scalar:
+  case RegKind::NeonVector:
+  case RegKind::SVEDataVector:
+    return 32;
+  case RegKind::Matrix:
+  case RegKind::SVEPredicateVector:
+  case RegKind::SMEPredicateAsCounter:
+    return 16;
+  default:
+    llvm_unreachable("Unsupported RegKind");
+  }
+}
+
 /// tryParseScalarRegister - Try to parse a register name. The token must be an
 /// Identifier when called, and if it is a register name the token is eaten and
 /// the register is added to the operand list.
 OperandMatchResultTy
 AArch64AsmParser::tryParseScalarRegister(unsigned &RegNum) {
   const AsmToken &Tok = getTok();
   if (Tok.isNot(AsmToken::Identifier))
     return MatchOperand_NoMatch;
if (RegTok.isNot(AsmToken::Identifier) ||
          !RegTok.getString().startswith_insensitive("za"))) {
       Error(Loc, "vector register expected");
       return MatchOperand_ParseFail;
     }
 
     return MatchOperand_NoMatch;
   };
 
+  int NumRegs = getNumRegsForRegKind(VectorKind);
   SMLoc S = getLoc();
   auto LCurly = getTok();
   Lex(); // Eat left bracket token.
 
   StringRef Kind;
   unsigned FirstReg;
   auto ParseRes = ParseVector(FirstReg, Kind, getLoc(), ExpectMatch);
 
   // Put back the original left bracket if there was no match, so that
   // different types of list-operands can be matched (e.g. SVE, Neon).
   if (ParseRes == MatchOperand_NoMatch)
     Parser.getLexer().UnLex(LCurly);
 
   if (ParseRes != MatchOperand_Success)
     return ParseRes;
 
   int64_t PrevReg = FirstReg;
   unsigned Count = 1;
 
+  int Stride = 1;
   if (parseOptionalToken(AsmToken::Minus)) {
     SMLoc Loc = getLoc();
     StringRef NextKind;
 
     unsigned Reg;
     ParseRes = ParseVector(Reg, NextKind, getLoc(), true);
     if (ParseRes != MatchOperand_Success)
       return ParseRes;
if (parseOptionalToken(AsmToken::Minus)) {
     if (Space == 0 || Space > 3) {
       Error(Loc, "invalid number of vectors");
       return MatchOperand_ParseFail;
     }
 
     Count += Space;
   }
   else {
+    bool HasCalculatedStride = false;
     while (parseOptionalToken(AsmToken::Comma)) {
       SMLoc Loc = getLoc();
       StringRef NextKind;
       unsigned Reg;
       ParseRes = ParseVector(Reg, NextKind, getLoc(), true);
       if (ParseRes != MatchOperand_Success)
         return ParseRes;
 
       // Any Kind suffices must match on all regs in the list.
       if (Kind != NextKind) {
         Error(Loc, "mismatched register size suffix");
         return MatchOperand_ParseFail;
       }
 
-      // Registers must be incremental (with wraparound at 31)
-      if (getContext().getRegisterInfo()->getEncodingValue(Reg) !=
-          (getContext().getRegisterInfo()->getEncodingValue(PrevReg) + 1) % 32) {
-        Error(Loc, "registers must be sequential");
+      unsigned RegVal = getContext().getRegisterInfo()->getEncodingValue(Reg);
+      unsigned PrevRegVal =
+          getContext().getRegisterInfo()->getEncodingValue(PrevReg);
+      if (!HasCalculatedStride) {
+        Stride = (PrevRegVal < RegVal) ? (RegVal - PrevRegVal)
+                                       : (RegVal + NumRegs - PrevRegVal);
+        HasCalculatedStride = true;
+      }
+
+      // Register must be incremental (with a wraparound at last register).
+      if (Stride == 0 || RegVal != ((PrevRegVal + Stride) % NumRegs)) {
+        Error(Loc, "registers must have the same sequential stride");
         return MatchOperand_ParseFail;
       }
 
       PrevReg = Reg;
       ++Count;
     }
   }
 
   if (parseToken(AsmToken::RCurly, "'}' expected"))
     return MatchOperand_ParseFail;
 
   if (Count > 4) {
     Error(S, "invalid number of vectors");
     return MatchOperand_ParseFail;
   }
 
   unsigned NumElements = 0;
   unsigned ElementWidth = 0;
   if (!Kind.empty()) {
     if (const auto &VK = parseVectorKind(Kind, VectorKind))
       std::tie(NumElements, ElementWidth) = *VK;
   }
 
   Operands.push_back(AArch64Operand::CreateVectorList(
-      FirstReg, Count, NumElements, ElementWidth, VectorKind, S, getLoc(),
-      getContext()));
+      FirstReg, Count, Stride, NumElements, ElementWidth, VectorKind, S,
+      getLoc(), getContext()));
 
   return MatchOperand_Success;
 }
 
 /// parseNeonVectorList - Parse a vector list operand for AdvSIMD instructions.
 bool AArch64AsmParser::parseNeonVectorList(OperandVector &Operands) {
   auto ParseRes = tryParseVectorList<RegKind::NeonVector>(Operands, true);
   if (ParseRes != MatchOperand_Success)

 
 bool AArch64AsmParser::areEqualRegs(const MCParsedAsmOperand &Op1,
                                     const MCParsedAsmOperand &Op2) const {
   auto &AOp1 = static_cast<const AArch64Operand&>(Op1);
   auto &AOp2 = static_cast<const AArch64Operand&>(Op2);
 
   if (AOp1.isVectorList() && AOp2.isVectorList())
     return AOp1.getVectorListCount() == AOp2.getVectorListCount() &&
-           AOp1.getVectorListStart() == AOp2.getVectorListStart();
+           AOp1.getVectorListStart() == AOp2.getVectorListStart() &&
+           AOp1.getVectorListStride() == AOp2.getVectorListStride();
 
   if (!AOp1.isReg() || !AOp2.isReg())
     return false;
 
   if (AOp1.getRegEqualityTy() == RegConstraintEqualityTy::EqualsReg &&
       AOp2.getRegEqualityTy() == RegConstraintEqualityTy::EqualsReg)
     return MCTargetAsmParser::areEqualRegs(Op1, Op2);
 
return Error(Loc, "Invalid vector list, expected list with 2 consecutive "
                       "and with matching element types");
   case Match_InvalidSVEVectorListMul4x8:
   case Match_InvalidSVEVectorListMul4x16:
   case Match_InvalidSVEVectorListMul4x32:
   case Match_InvalidSVEVectorListMul4x64:
     return Error(Loc, "Invalid vector list, expected list with 4 consecutive "
                       "SVE vectors, where the first vector is a multiple of 4 "
                       "and with matching element types");
+  case Match_InvalidSVEVectorListStrided2x8:
+  case Match_InvalidSVEVectorListStrided2x16:
+  case Match_InvalidSVEVectorListStrided2x32:
+  case Match_InvalidSVEVectorListStrided2x64:
+    return Error(
+        Loc,
+        "Invalid vector list, expected list with each SVE vector in the list "
+        "8 registers apart, and the first register in the range [z0, z7] or "
+        "[z16, z23] and with correct element type");
+  case Match_InvalidSVEVectorListStrided4x8:
+  case Match_InvalidSVEVectorListStrided4x16:
+  case Match_InvalidSVEVectorListStrided4x32:
+  case Match_InvalidSVEVectorListStrided4x64:
+    return Error(
+        Loc,
+        "Invalid vector list, expected list with each SVE vector in the list "
+        "4 registers apart, and the first register in the range [z0, z3] or "
+        "[z16, z19] and with correct element type");
   case Match_InvalidZT0:
     return Error(Loc, "operand must be zt0 register");
   default:
     llvm_unreachable("unexpected error code!");
   }
 }
 
 static const char *getSubtargetFeatureName(uint64_t Val);
bool AArch64AsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
   case Match_InvalidSVEVectorListMul2x8:
   case Match_InvalidSVEVectorListMul2x16:
   case Match_InvalidSVEVectorListMul2x32:
   case Match_InvalidSVEVectorListMul2x64:
   case Match_InvalidSVEVectorListMul4x8:
   case Match_InvalidSVEVectorListMul4x16:
   case Match_InvalidSVEVectorListMul4x32:
   case Match_InvalidSVEVectorListMul4x64:
+  case Match_InvalidSVEVectorListStrided2x8:
+  case Match_InvalidSVEVectorListStrided2x16:
+  case Match_InvalidSVEVectorListStrided2x32:
+  case Match_InvalidSVEVectorListStrided2x64:
+  case Match_InvalidSVEVectorListStrided4x8:
+  case Match_InvalidSVEVectorListStrided4x16:
+  case Match_InvalidSVEVectorListStrided4x32:
+  case Match_InvalidSVEVectorListStrided4x64:
   case Match_MSR:
   case Match_MRS: {
     if (ErrorInfo >= Operands.size())
       return Error(IDLoc, "too few operands for instruction", SMRange(IDLoc, (*Operands.back()).getEndLoc()));
     // Any time we get here, there's nothing fancy to do. Just get the
     // operand SMLoc and display the diagnostic.
     SMLoc ErrorLoc = ((AArch64Operand &)*Operands[ErrorInfo]).getStartLoc();
     if (ErrorLoc == SMLoc())

llvm/lib/Target/AArch64/Disassembler/AArch64Disassembler.cpp

static DecodeStatus DecodeZPR4RegisterClass(MCInst &Inst, unsigned RegNo,
                                             uint64_t Address,
                                             const MCDisassembler *Decoder);
 static DecodeStatus DecodeZPR2Mul2RegisterClass(MCInst &Inst, unsigned RegNo,
                                                 uint64_t Address,
                                                 const void *Decoder);
 static DecodeStatus DecodeZPR4Mul4RegisterClass(MCInst &Inst, unsigned RegNo,
                                                 uint64_t Address,
                                                 const void *Decoder);
+static DecodeStatus DecodeZPR2StridedRegisterClass(MCInst &Inst, unsigned RegNo,
+                                                   uint64_t Address,
+                                                   const void *Decoder);
+static DecodeStatus DecodeZPR4StridedRegisterClass(MCInst &Inst, unsigned RegNo,
+                                                   uint64_t Address,
+                                                   const void *Decoder);
 template <unsigned NumBitsForTile>
 static DecodeStatus DecodeMatrixTile(MCInst &Inst, unsigned RegNo,
                                      uint64_t Address,
                                      const MCDisassembler *Decoder);
 static DecodeStatus
 DecodeMatrixTileListRegisterClass(MCInst &Inst, unsigned RegMask,
                                   uint64_t Address,
                                   const MCDisassembler *Decoder);
static DecodeStatus DecodeZPR4Mul4RegisterClass(MCInst &Inst, unsigned RegNo,
   if (RegNo * 4 > 28)
     return Fail;
   unsigned Register =
       AArch64MCRegisterClasses[AArch64::ZPR4RegClassID].getRegister(RegNo * 4);
   Inst.addOperand(MCOperand::createReg(Register));
   return Success;
 }
 
+static DecodeStatus DecodeZPR2StridedRegisterClass(MCInst &Inst, unsigned RegNo,
+                                                   uint64_t Address,
+                                                   const void *Decoder) {
+  if (RegNo > 15)
+    return Fail;
+  unsigned Register =
+      AArch64MCRegisterClasses[AArch64::ZPR2StridedRegClassID].getRegister(
+          RegNo);
+  Inst.addOperand(MCOperand::createReg(Register));
+  return Success;
+}
+
+static DecodeStatus DecodeZPR4StridedRegisterClass(MCInst &Inst, unsigned RegNo,
+                                                   uint64_t Address,
+                                                   const void *Decoder) {
+  if (RegNo > 7)
+    return Fail;
+  unsigned Register =
+      AArch64MCRegisterClasses[AArch64::ZPR4StridedRegClassID].getRegister(
+          RegNo);
+  Inst.addOperand(MCOperand::createReg(Register));
+  return Success;
+}
+
 static DecodeStatus
 DecodeMatrixTileListRegisterClass(MCInst &Inst, unsigned RegMask,
                                   uint64_t Address,
                                   const MCDisassembler *Decoder) {
   if (RegMask > 0xFF)
     return Fail;
   Inst.addOperand(MCOperand::createImm(RegMask));
   return Success;

llvm/lib/Target/AArch64/MCTargetDesc/AArch64InstPrinter.cpp

void AArch64InstPrinter::printVectorList(const MCInst *MI, unsigned OpNum,
   unsigned Reg = MI->getOperand(OpNum).getReg();
 
   O << "{ ";
 
   // Work out how many registers there are in the list (if there is an actual
   // list).
   unsigned NumRegs = 1;
   if (MRI.getRegClass(AArch64::DDRegClassID).contains(Reg) ||
-      MRI.getRegClass(AArch64::ZPR2RegClassID).contains(Reg) ||
-      MRI.getRegClass(AArch64::QQRegClassID).contains(Reg))
+      MRI.getRegClass(AArch64::ZPR2StridedRegClassID).contains(Reg) ||
+      MRI.getRegClass(AArch64::QQRegClassID).contains(Reg) ||
+      MRI.getRegClass(AArch64::ZPR2RegClassID).contains(Reg))
     NumRegs = 2;
   else if (MRI.getRegClass(AArch64::DDDRegClassID).contains(Reg) ||
            MRI.getRegClass(AArch64::ZPR3RegClassID).contains(Reg) ||
            MRI.getRegClass(AArch64::QQQRegClassID).contains(Reg))
     NumRegs = 3;
   else if (MRI.getRegClass(AArch64::DDDDRegClassID).contains(Reg) ||
            MRI.getRegClass(AArch64::ZPR4RegClassID).contains(Reg) ||
-           MRI.getRegClass(AArch64::QQQQRegClassID).contains(Reg))
+           MRI.getRegClass(AArch64::QQQQRegClassID).contains(Reg) ||
+           MRI.getRegClass(AArch64::ZPR4StridedRegClassID).contains(Reg))
     NumRegs = 4;
 
+  unsigned Stride = 1;
+  if (MRI.getRegClass(AArch64::ZPR2StridedRegClassID).contains(Reg))
+    Stride = 8;
+  else if (MRI.getRegClass(AArch64::ZPR4StridedRegClassID).contains(Reg))
+    Stride = 4;
+
   // Now forget about the list and find out what the first register is.
   if (unsigned FirstReg = MRI.getSubReg(Reg, AArch64::dsub0))
     Reg = FirstReg;
   else if (unsigned FirstReg = MRI.getSubReg(Reg, AArch64::qsub0))
     Reg = FirstReg;
   else if (unsigned FirstReg = MRI.getSubReg(Reg, AArch64::zsub0))
     Reg = FirstReg;
 
   // If it's a D-reg, we need to promote it to the equivalent Q-reg before
   // printing (otherwise getRegisterName fails).
   if (MRI.getRegClass(AArch64::FPR64RegClassID).contains(Reg)) {
     const MCRegisterClass &FPR128RC =
         MRI.getRegClass(AArch64::FPR128RegClassID);
     Reg = MRI.getMatchingSuperReg(Reg, AArch64::dsub, &FPR128RC);
   }
 
   if (MRI.getRegClass(AArch64::ZPRRegClassID).contains(Reg) && NumRegs > 1 &&
       // Do not print the range when the last register is lower than the first.
       // Because it is a wrap-around register.
-      Reg < getNextVectorRegister(Reg, NumRegs - 1)) {
+      Reg < getNextVectorRegister(Reg, NumRegs - 1) && Stride == 1) {
     printRegName(O, Reg);
     O << LayoutSuffix;
     if (NumRegs > 1) {
       // Set of two sve registers should be separated by ','
       StringRef split_char = NumRegs == 2 ? ", " : " - ";
       O << split_char;
       printRegName(O, (getNextVectorRegister(Reg, NumRegs - 1)));
       O << LayoutSuffix;
     }
   } else {
-    for (unsigned i = 0; i < NumRegs; ++i, Reg = getNextVectorRegister(Reg)) {
+    for (unsigned i = 0; i < NumRegs;
+         ++i, Reg = getNextVectorRegister(Reg, Stride)) {
       // wrap-around sve register
-      if (MRI.getRegClass(AArch64::ZPRRegClassID).contains(Reg))
+      if (MRI.getRegClass(AArch64::ZPRRegClassID).contains(Reg) ||
+          MRI.getRegClass(AArch64::ZPR2RegClassID).contains(Reg) ||
+          MRI.getRegClass(AArch64::ZPR4RegClassID).contains(Reg))
         printRegName(O, Reg);
       else
         printRegName(O, Reg, AArch64::vreg);
       O << LayoutSuffix;
       if (i + 1 != NumRegs)
         O << ", ";
     }
   }

llvm/lib/Target/AArch64/MCTargetDesc/AArch64MCCodeEmitter.cpp

public:
   uint32_t EncodeRegAsMultipleOf(const MCInst &MI, unsigned OpIdx,
                                  SmallVectorImpl<MCFixup> &Fixups,
                                  const MCSubtargetInfo &STI) const;
 
   uint32_t EncodePPR_3b_p8_p15(const MCInst &MI, unsigned OpIdx,
                                SmallVectorImpl<MCFixup> &Fixups,
                                const MCSubtargetInfo &STI) const;
 
+  uint32_t EncodeZPR2StridedRegisterClass(const MCInst &MI, unsigned OpIdx,
+                                          SmallVectorImpl<MCFixup> &Fixups,
+                                          const MCSubtargetInfo &STI) const;
+  uint32_t EncodeZPR4StridedRegisterClass(const MCInst &MI, unsigned OpIdx,
+                                          SmallVectorImpl<MCFixup> &Fixups,
+                                          const MCSubtargetInfo &STI) const;
+
   uint32_t EncodeMatrixTileListRegisterClass(const MCInst &MI, unsigned OpIdx,
                                              SmallVectorImpl<MCFixup> &Fixups,
                                              const MCSubtargetInfo &STI) const;
   template <unsigned BaseReg>
   uint32_t encodeMatrixIndexGPR32(const MCInst &MI, unsigned OpIdx,
                                   SmallVectorImpl<MCFixup> &Fixups,
                                   const MCSubtargetInfo &STI) const;
 };

 uint32_t
 AArch64MCCodeEmitter::EncodePPR_3b_p8_p15(const MCInst &MI, unsigned OpIdx,
                                           SmallVectorImpl<MCFixup> &Fixups,
                                           const MCSubtargetInfo &STI) const {
   auto RegOpnd = MI.getOperand(OpIdx).getReg();
   return RegOpnd - AArch64::P8;
 }
 
+uint32_t AArch64MCCodeEmitter::EncodeZPR2StridedRegisterClass(
+    const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups,
+    const MCSubtargetInfo &STI) const {
+  auto RegOpnd = MI.getOperand(OpIdx).getReg();
+  unsigned RegVal = Ctx.getRegisterInfo()->getEncodingValue(RegOpnd);
+  unsigned T = (RegVal & 0x10) >> 1;
+  unsigned Zt = RegVal & 0x7;
+  return T | Zt;
+}
+
+uint32_t AArch64MCCodeEmitter::EncodeZPR4StridedRegisterClass(
+    const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups,
+    const MCSubtargetInfo &STI) const {
+  auto RegOpnd = MI.getOperand(OpIdx).getReg();
+  unsigned RegVal = Ctx.getRegisterInfo()->getEncodingValue(RegOpnd);
+  unsigned T = (RegVal & 0x10) >> 2;
+  unsigned Zt = RegVal & 0x3;
+  return T | Zt;
+}
+
 uint32_t AArch64MCCodeEmitter::EncodeMatrixTileListRegisterClass(
     const MCInst &MI, unsigned OpIdx, SmallVectorImpl<MCFixup> &Fixups,
     const MCSubtargetInfo &STI) const {
   unsigned RegMask = MI.getOperand(OpIdx).getImm();
   assert(RegMask <= 0xFF && "Invalid register mask!");
   return RegMask;
 }
 

llvm/lib/Target/AArch64/SMEInstrFormats.td

class sme2_sel_vector_vg4<bits<2> sz, RegisterOperand vector_ty,
   let Inst{1}     = 0b0;
 }
 multiclass sme2_sel_vector_vg4<string mnemonic> {
   def _B : sme2_sel_vector_vg4<0b00, ZZZZ_b_mul_r, mnemonic>;
   def _H : sme2_sel_vector_vg4<0b01, ZZZZ_h_mul_r, mnemonic>;
   def _S : sme2_sel_vector_vg4<0b10, ZZZZ_s_mul_r, mnemonic>;
   def _D : sme2_sel_vector_vg4<0b11, ZZZZ_d_mul_r, mnemonic>;
 }
+
+//===----------------------------------------------------------------------===//
+// Non contiguous Load and Store
+
+class sme2_ld_vector_vg24_multi_scalar_scalar<bits<2> msz, bit n,
+                                              RegisterOperand multi_vector_ty,
+                                              RegisterOperand gpr_ty,
+                                              string mnemonic>
+   : I<(outs multi_vector_ty:$Zt),
+       (ins PNRAny_p8_p15:$PNg, GPR64sp:$Rn, gpr_ty:$Rm),
+       mnemonic, "\t$Zt, $PNg/z, [$Rn, $Rm]",
+       "", []>, Sched<[]> {
+   bits<5> Rm;
+   bits<3> PNg;
+   bits<5> Rn;
+   let Inst{31-21} = 0b10100001000;
+   let Inst{20-16} = Rm;
+   let Inst{14-13} = msz;
+   let Inst{12-10} = PNg;
+   let Inst{9-5}   = Rn;
+   let Inst{3}     = n;
+
+   let mayLoad = 1;
+}
+class sme2_ld_vector_vg2_multi_scalar_scalar<bits<2> msz, bit n,
+                                             RegisterOperand multi_vector_ty,
+                                             RegisterOperand gpr_ty,
+                                             string mnemonic>
+  : sme2_ld_vector_vg24_multi_scalar_scalar<msz, n, multi_vector_ty, gpr_ty,
+                                            mnemonic> {
+  bits<4> Zt;
+  let Inst{15}  = 0b0;
+  let Inst{4} = Zt{3};
+  let Inst{2-0} = Zt{2-0};
+}
+
+class sme2_ld_vector_vg4_multi_scalar_scalar<bits<2> msz, bit n,
+                                             RegisterOperand multi_vector_ty,
+                                             RegisterOperand gpr_ty,
+                                             string mnemonic>
+  : sme2_ld_vector_vg24_multi_scalar_scalar<msz, n, multi_vector_ty, gpr_ty,
+                                            mnemonic> {
+   bits<3> Zt;
+   let Inst{15}  = 0b1;
+   let Inst{4} = Zt{2};
+   let Inst{2} = 0b0;
+   let Inst{1-0} = Zt{1-0};
+}
+
+
+class sme2_ld_vector_vg24_multi_scalar_immediate<bits<2> msz, bit n,
+                                                 RegisterOperand multi_vector_ty,
+                                                 Operand index_ty,
+                                                  string mnemonic>
+    : I<(outs multi_vector_ty:$Zt),
+        (ins PNRAny_p8_p15:$PNg, GPR64sp:$Rn, index_ty:$imm4),
+        mnemonic,  "\t$Zt, $PNg/z, [$Rn, $imm4, mul vl]",
+        "", []>, Sched<[]> {
+   bits<4> imm4;
+   bits<3> PNg;
+   bits<5> Rn;
+   let Inst{31-20} = 0b101000010100;
+   let Inst{19-16} = imm4;
+   let Inst{14-13} = msz;
+   let Inst{12-10} = PNg;
+   let Inst{9-5}   = Rn;
+   let Inst{3}     = n;
+
+   let mayLoad = 1;
+}
+
+multiclass sme2_ld_vector_vg2_multi_scalar_immediate<bits<2> msz, bit n,
+                                                RegisterOperand multi_vector_ty,
+                                                Operand index_ty,
+                                                 string mnemonic>{
+  def NAME : sme2_ld_vector_vg24_multi_scalar_immediate<msz, n, multi_vector_ty,
+                                               index_ty, mnemonic> {
+  bits<4> Zt;
+  let Inst{15}  = 0b0;
+  let Inst{4} = Zt{3};
+  let Inst{2-0} = Zt{2-0};
+}
+
+   def : InstAlias<mnemonic # "\t$Zt, $PNg/z, [$Rn, $imm4, mul vl]",
+                 (!cast<Instruction>(NAME) multi_vector_ty:$Zt, PNRAny_p8_p15:$PNg, GPR64sp:$Rn, index_ty:$imm4), 0>;
+
+    def : InstAlias<mnemonic # "\t$Zt, $PNg/z, [$Rn]",
+                   (!cast<Instruction>(NAME) multi_vector_ty:$Zt, PNRAny_p8_p15:$PNg, GPR64sp:$Rn, 0), 1>;
+}
+
+multiclass sme2_ld_vector_vg4_multi_scalar_immediate<bits<2> msz, bit n,
+                                                 RegisterOperand multi_vector_ty,
+                                                 Operand index_ty,
+                                                 string mnemonic> {
+  def NAME : sme2_ld_vector_vg24_multi_scalar_immediate<msz, n, multi_vector_ty,
+                                               index_ty, mnemonic> {
+   bits<3> Zt;
+   let Inst{15}  = 0b1;
+   let Inst{4} = Zt{2};
+   let Inst{2} = 0b0;
+   let Inst{1-0} = Zt{1-0};
+}
+
+   def : InstAlias<mnemonic # "\t$Zt, $PNg/z, [$Rn, $imm4, mul vl]",
+                 (!cast<Instruction>(NAME) multi_vector_ty:$Zt, PNRAny_p8_p15:$PNg, GPR64sp:$Rn, index_ty:$imm4), 0>;
+
+   def : InstAlias<mnemonic # "\t$Zt, $PNg/z, [$Rn]",
+                   (!cast<Instruction>(NAME) multi_vector_ty:$Zt, PNRAny_p8_p15:$PNg, GPR64sp:$Rn, 0), 1>;
+}
+
+//===----------------------------------------------------------------------===//
+// SME2 Non-Contiguous Store
+class sme2_st_vector_vg24_multi_scalar_scalar<bits<2> msz, bit n,
+                                              RegisterOperand multi_vector_ty,
+                                              RegisterOperand gpr_ty,
+                                              string mnemonic>
+   : I<(outs ),
+       (ins multi_vector_ty:$Zt, PNRAny_p8_p15:$PNg, GPR64sp:$Rn, gpr_ty:$Rm),
+       mnemonic, "\t$Zt, $PNg, [$Rn, $Rm]",
+       "", []>, Sched<[]> {
+   bits<5> Rm;
+   bits<3> PNg;
+   bits<5> Rn;
+   let Inst{31-21} = 0b10100001001;
+   let Inst{20-16} = Rm;
+   let Inst{14-13} = msz;
+   let Inst{12-10} = PNg;
+   let Inst{9-5}   = Rn;
+   let Inst{3}     = n;
+
+   let mayStore    = 1;
+}
+
+class sme2_st_vector_vg2_multi_scalar_scalar<bits<2> msz, bit n,
+                                                 RegisterOperand multi_vector_ty,
+                                                 RegisterOperand gpr_ty,
+                                                 string mnemonic>
+  : sme2_st_vector_vg24_multi_scalar_scalar<msz, n, multi_vector_ty,
+                                            gpr_ty, mnemonic> {
+  bits<4> Zt;
+  let Inst{15}  = 0b0;
+  let Inst{4}   = Zt{3};
+  let Inst{2-0} = Zt{2-0};
+}
+
+class sme2_st_vector_vg4_multi_scalar_scalar<bits<2> msz, bit n,
+                                             RegisterOperand multi_vector_ty,
+                                             RegisterOperand gpr_ty,
+                                             string mnemonic>
+  : sme2_st_vector_vg24_multi_scalar_scalar<msz, n, multi_vector_ty,
+                                            gpr_ty, mnemonic> {
+   bits<3> Zt;
+   let Inst{15}  = 0b1;
+   let Inst{4} = Zt{2};
+   let Inst{2} = 0b0;
+   let Inst{1-0} = Zt{1-0};
+}
+
+class sme2_st_vector_vg24_multi_scalar_immediate<bits<2> msz, bit n,
+                                                 RegisterOperand multi_vector_ty,
+                                                 Operand index_ty,
+                                                 string mnemonic>
+    : I<(outs ),
+        (ins multi_vector_ty:$Zt, PNRAny_p8_p15:$PNg, GPR64sp:$Rn, index_ty:$imm4),
+        mnemonic,  "\t$Zt, $PNg, [$Rn, $imm4, mul vl]",
+        "", []>, Sched<[]> {
+   bits<4> imm4;
+   bits<3> PNg;
+   bits<5> Rn;
+   let Inst{31-20} = 0b101000010110;
+   let Inst{19-16} = imm4;
+   let Inst{14-13} = msz;
+   let Inst{12-10} = PNg;
+   let Inst{9-5}   = Rn;
+   let Inst{3}     = n;
+
+   let mayStore    = 1;
+}
+
+
+multiclass sme2_st_vector_vg2_multi_scalar_immediate<bits<2> msz, bit n,
+                                                RegisterOperand multi_vector_ty,
+                                                Operand index_ty,
+                                                string mnemonic> {
+  def NAME: sme2_st_vector_vg24_multi_scalar_immediate<msz, n, multi_vector_ty,
+                                               index_ty, mnemonic> {
+  bits<4> Zt;
+  let Inst{15}  = 0b0;
+  let Inst{4}   = Zt{3};
+  let Inst{2-0} = Zt{2-0};
+}
+
+    def : InstAlias<mnemonic # "\t$Zt, $PNg, [$Rn, $imm4, mul vl]",
+                 (!cast<Instruction>(NAME) multi_vector_ty:$Zt, PNRAny_p8_p15:$PNg, GPR64sp:$Rn, index_ty:$imm4), 0>;
+
+    def : InstAlias<mnemonic # "\t$Zt, $PNg, [$Rn]",
+                   (!cast<Instruction>(NAME) multi_vector_ty:$Zt, PNRAny_p8_p15:$PNg, GPR64sp:$Rn,0), 1>;
+}
+
+multiclass sme2_st_vector_vg4_multi_scalar_immediate<bits<2> msz, bit n,
+                                                RegisterOperand multi_vector_ty,
+                                                Operand index_ty,
+                                                string mnemonic> {
+  def NAME : sme2_st_vector_vg24_multi_scalar_immediate<msz, n, multi_vector_ty,
+                                               index_ty, mnemonic> {
+   bits<3> Zt;
+   let Inst{15}  = 0b1;
+   let Inst{4}   = Zt{2};
+   let Inst{2}   = 0b0;
+   let Inst{1-0} = Zt{1-0};
+}
+
+    def : InstAlias<mnemonic # "\t$Zt, $PNg, [$Rn, $imm4, mul vl]",
+                 (!cast<Instruction>(NAME) multi_vector_ty:$Zt, PNRAny_p8_p15:$PNg, GPR64sp:$Rn, index_ty:$imm4), 0>;
+
+    def : InstAlias<mnemonic # "\t$Zt, $PNg, [$Rn]",
+                   (!cast<Instruction>(NAME) multi_vector_ty:$Zt, PNRAny_p8_p15:$PNg, GPR64sp:$Rn,0), 1>;
+}

llvm/test/MC/AArch64/SME2/add-diagnostics.s

 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
 // CHECK-NEXT: za.d[w8, 0, vgx2], {z0.d-z3.d}, z0.d
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 // --------------------------------------------------------------------------//
 // Invalid vector list.
 
 add za.d[w8, 0], {z0.d,z2.d}, {z0.d,z2.d}
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must be sequential
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
 // CHECK-NEXT: add za.d[w8, 0], {z0.d,z2.d}, {z0.d,z2.d}
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 add za.s[w10, 3, vgx2], {z10.s-z11.s}, {z21.s-z22.s}
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors, where the first vector is a multiple of 2 and with matching element types
 // CHECK-NEXT: add za.s[w10, 3, vgx2], {z10.s-z11.s}, {z21.s-z22.s}
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 

 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 add {z0.s,z1.s}, {z2.s,z3.s}, z15.s
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register list
 // CHECK-NEXT: add {z0.s,z1.s}, {z2.s,z3.s}, z15.s
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 add {z0.s,z1.s}, {z0.s,z2.s}, z15.s
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must be sequential
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
 // CHECK-NEXT: add {z0.s,z1.s}, {z0.s,z2.s}, z15.s
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 add {z0.s,z1.s}, {z0.s,z1.s,z2.s}, z15.s
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
 // CHECK-NEXT: add {z0.s,z1.s}, {z0.s,z1.s,z2.s}, z15.s
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 add {z0.s,z1.s}, {z0.d,z1.d}, z15.s
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
 // CHECK-NEXT: add {z0.s,z1.s}, {z0.d,z1.d}, z15.s
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 

llvm/test/MC/AArch64/SME2/fmla-diagnostics.s

 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
 // CHECK-NEXT: za.d[w8, 0, vgx2], {z0.d-z3.d}, z0.d
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 // --------------------------------------------------------------------------//
 // Invalid vector list.
 
 fmla za.d[w8, 0], {z0.d,z2.d}, {z0.d,z2.d}
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must be sequential
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
 // CHECK-NEXT: fmla za.d[w8, 0], {z0.d,z2.d}, {z0.d,z2.d}
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 fmla za.s[w10, 3, vgx2], {z10.s-z11.s}, {z21.s-z22.s}
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors, where the first vector is a multiple of 2 and with matching element types
 // CHECK-NEXT: fmla za.s[w10, 3, vgx2], {z10.s-z11.s}, {z21.s-z22.s}
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 

llvm/test/MC/AArch64/SME2/fmls-diagnostics.s

 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
 // CHECK-NEXT: za.d[w8, 0, vgx2], {z0.d-z3.d}, z0.d
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 // --------------------------------------------------------------------------//
 // Invalid vector list.
 
 fmls za.d[w8, 0], {z0.d,z2.d}, {z0.d,z2.d}
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must be sequential
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
 // CHECK-NEXT: fmls za.d[w8, 0], {z0.d,z2.d}, {z0.d,z2.d}
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 fmls za.s[w10, 3, vgx2], {z10.s-z11.s}, {z21.s-z22.s}
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors, where the first vector is a multiple of 2 and with matching element types
 // CHECK-NEXT: fmls za.s[w10, 3, vgx2], {z10.s-z11.s}, {z21.s-z22.s}
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 

llvm/test/MC/AArch64/SME2/ld1b.s

+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
+// RUN:        | llvm-objdump -d --mattr=+sme2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
+// RUN:        | sed '/.text/d' | sed 's/.*encoding: //g' \
+// RUN:        | llvm-mc -triple=aarch64 -mattr=+sme2 -disassemble -show-encoding \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+
+
+ld1b    {z0.b, z8.b}, pn8/z, [x0, x0]  // 10100001-00000000-00000000-00000000
+// CHECK-INST: ld1b    { z0.b, z8.b }, pn8/z, [x0, x0]
+// CHECK-ENCODING: [0x00,0x00,0x00,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a1000000 <unknown>
+
+ld1b    {z21.b, z29.b}, pn13/z, [x10, x21]  // 10100001-00010101-00010101-01010101
+// CHECK-INST: ld1b    { z21.b, z29.b }, pn13/z, [x10, x21]
+// CHECK-ENCODING: [0x55,0x15,0x15,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a1151555 <unknown>
+
+ld1b    {z23.b, z31.b}, pn11/z, [x13, x8]  // 10100001-00001000-00001101-10110111
+// CHECK-INST: ld1b    { z23.b, z31.b }, pn11/z, [x13, x8]
+// CHECK-ENCODING: [0xb7,0x0d,0x08,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a1080db7 <unknown>
+
+ld1b    {z23.b, z31.b}, pn15/z, [sp, xzr]  // 10100001-00011111-00011111-11110111
+// CHECK-INST: ld1b    { z23.b, z31.b }, pn15/z, [sp, xzr]
+// CHECK-ENCODING: [0xf7,0x1f,0x1f,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a11f1ff7 <unknown>
+
+
+ld1b    {z0.b, z8.b}, pn8/z, [x0]  // 10100001-01000000-00000000-00000000
+// CHECK-INST: ld1b    { z0.b, z8.b }, pn8/z, [x0]
+// CHECK-ENCODING: [0x00,0x00,0x40,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a1400000 <unknown>
+
+ld1b    {z21.b, z29.b}, pn13/z, [x10, #10, mul vl]  // 10100001-01000101-00010101-01010101
+// CHECK-INST: ld1b    { z21.b, z29.b }, pn13/z, [x10, #10, mul vl]
+// CHECK-ENCODING: [0x55,0x15,0x45,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a1451555 <unknown>
+
+ld1b    {z23.b, z31.b}, pn11/z, [x13, #-16, mul vl]  // 10100001-01001000-00001101-10110111
+// CHECK-INST: ld1b    { z23.b, z31.b }, pn11/z, [x13, #-16, mul vl]
+// CHECK-ENCODING: [0xb7,0x0d,0x48,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a1480db7 <unknown>
+
+ld1b    {z23.b, z31.b}, pn15/z, [sp, #-2, mul vl]  // 10100001-01001111-00011111-11110111
+// CHECK-INST: ld1b    { z23.b, z31.b }, pn15/z, [sp, #-2, mul vl]
+// CHECK-ENCODING: [0xf7,0x1f,0x4f,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a14f1ff7 <unknown>
+
+
+ld1b    {z0.b, z4.b, z8.b, z12.b}, pn8/z, [x0, x0]  // 10100001-00000000-10000000-00000000
+// CHECK-INST: ld1b    { z0.b, z4.b, z8.b, z12.b }, pn8/z, [x0, x0]
+// CHECK-ENCODING: [0x00,0x80,0x00,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a1008000 <unknown>
+
+ld1b    {z17.b, z21.b, z25.b, z29.b}, pn13/z, [x10, x21]  // 10100001-00010101-10010101-01010001
+// CHECK-INST: ld1b    { z17.b, z21.b, z25.b, z29.b }, pn13/z, [x10, x21]
+// CHECK-ENCODING: [0x51,0x95,0x15,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a1159551 <unknown>
+
+ld1b    {z19.b, z23.b, z27.b, z31.b}, pn11/z, [x13, x8]  // 10100001-00001000-10001101-10110011
+// CHECK-INST: ld1b    { z19.b, z23.b, z27.b, z31.b }, pn11/z, [x13, x8]
+// CHECK-ENCODING: [0xb3,0x8d,0x08,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a1088db3 <unknown>
+
+ld1b    {z19.b, z23.b, z27.b, z31.b}, pn15/z, [sp, xzr]  // 10100001-00011111-10011111-11110011
+// CHECK-INST: ld1b    { z19.b, z23.b, z27.b, z31.b }, pn15/z, [sp, xzr]
+// CHECK-ENCODING: [0xf3,0x9f,0x1f,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a11f9ff3 <unknown>
+
+
+ld1b    {z0.b, z4.b, z8.b, z12.b}, pn8/z, [x0]  // 10100001-01000000-10000000-00000000
+// CHECK-INST: ld1b    { z0.b, z4.b, z8.b, z12.b }, pn8/z, [x0]
+// CHECK-ENCODING: [0x00,0x80,0x40,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a1408000 <unknown>
+
+ld1b    {z17.b, z21.b, z25.b, z29.b}, pn13/z, [x10, #20, mul vl]  // 10100001-01000101-10010101-01010001
+// CHECK-INST: ld1b    { z17.b, z21.b, z25.b, z29.b }, pn13/z, [x10, #20, mul vl]
+// CHECK-ENCODING: [0x51,0x95,0x45,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a1459551 <unknown>
+
+ld1b    {z19.b, z23.b, z27.b, z31.b}, pn11/z, [x13, #-32, mul vl]  // 10100001-01001000-10001101-10110011
+// CHECK-INST: ld1b    { z19.b, z23.b, z27.b, z31.b }, pn11/z, [x13, #-32, mul vl]
+// CHECK-ENCODING: [0xb3,0x8d,0x48,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a1488db3 <unknown>
+
+ld1b    {z19.b, z23.b, z27.b, z31.b}, pn15/z, [sp, #-4, mul vl]  // 10100001-01001111-10011111-11110011
+// CHECK-INST: ld1b    { z19.b, z23.b, z27.b, z31.b }, pn15/z, [sp, #-4, mul vl]
+// CHECK-ENCODING: [0xf3,0x9f,0x4f,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a14f9ff3 <unknown>
+

llvm/test/MC/AArch64/SME2/ld1d.s

+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
+// RUN:        | llvm-objdump -d --mattr=+sme2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
+// RUN:        | sed '/.text/d' | sed 's/.*encoding: //g' \
+// RUN:        | llvm-mc -triple=aarch64 -mattr=+sme2 -disassemble -show-encoding \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+
+
+ld1d    {z0.d, z8.d}, pn8/z, [x0, x0, lsl #3]  // 10100001-00000000-01100000-00000000
+// CHECK-INST: ld1d    { z0.d, z8.d }, pn8/z, [x0, x0, lsl #3]
+// CHECK-ENCODING: [0x00,0x60,0x00,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a1006000 <unknown>
+
+ld1d    {z21.d, z29.d}, pn13/z, [x10, x21, lsl #3]  // 10100001-00010101-01110101-01010101
+// CHECK-INST: ld1d    { z21.d, z29.d }, pn13/z, [x10, x21, lsl #3]
+// CHECK-ENCODING: [0x55,0x75,0x15,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a1157555 <unknown>
+
+ld1d    {z23.d, z31.d}, pn11/z, [x13, x8, lsl #3]  // 10100001-00001000-01101101-10110111
+// CHECK-INST: ld1d    { z23.d, z31.d }, pn11/z, [x13, x8, lsl #3]
+// CHECK-ENCODING: [0xb7,0x6d,0x08,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a1086db7 <unknown>
+
+ld1d    {z23.d, z31.d}, pn15/z, [sp, xzr, lsl #3]  // 10100001-00011111-01111111-11110111
+// CHECK-INST: ld1d    { z23.d, z31.d }, pn15/z, [sp, xzr, lsl #3]
+// CHECK-ENCODING: [0xf7,0x7f,0x1f,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a11f7ff7 <unknown>
+
+
+ld1d    {z0.d, z8.d}, pn8/z, [x0]  // 10100001-01000000-01100000-00000000
+// CHECK-INST: ld1d    { z0.d, z8.d }, pn8/z, [x0]
+// CHECK-ENCODING: [0x00,0x60,0x40,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a1406000 <unknown>
+
+ld1d    {z21.d, z29.d}, pn13/z, [x10, #10, mul vl]  // 10100001-01000101-01110101-01010101
+// CHECK-INST: ld1d    { z21.d, z29.d }, pn13/z, [x10, #10, mul vl]
+// CHECK-ENCODING: [0x55,0x75,0x45,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a1457555 <unknown>
+
+ld1d    {z23.d, z31.d}, pn11/z, [x13, #-16, mul vl]  // 10100001-01001000-01101101-10110111
+// CHECK-INST: ld1d    { z23.d, z31.d }, pn11/z, [x13, #-16, mul vl]
+// CHECK-ENCODING: [0xb7,0x6d,0x48,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a1486db7 <unknown>
+
+ld1d    {z23.d, z31.d}, pn15/z, [sp, #-2, mul vl]  // 10100001-01001111-01111111-11110111
+// CHECK-INST: ld1d    { z23.d, z31.d }, pn15/z, [sp, #-2, mul vl]
+// CHECK-ENCODING: [0xf7,0x7f,0x4f,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a14f7ff7 <unknown>
+
+
+ld1d    {z0.d, z4.d, z8.d, z12.d}, pn8/z, [x0, x0, lsl #3]  // 10100001-00000000-11100000-00000000
+// CHECK-INST: ld1d    { z0.d, z4.d, z8.d, z12.d }, pn8/z, [x0, x0, lsl #3]
+// CHECK-ENCODING: [0x00,0xe0,0x00,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a100e000 <unknown>
+
+ld1d    {z17.d, z21.d, z25.d, z29.d}, pn13/z, [x10, x21, lsl #3]  // 10100001-00010101-11110101-01010001
+// CHECK-INST: ld1d    { z17.d, z21.d, z25.d, z29.d }, pn13/z, [x10, x21, lsl #3]
+// CHECK-ENCODING: [0x51,0xf5,0x15,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a115f551 <unknown>
+
+ld1d    {z19.d, z23.d, z27.d, z31.d}, pn11/z, [x13, x8, lsl #3]  // 10100001-00001000-11101101-10110011
+// CHECK-INST: ld1d    { z19.d, z23.d, z27.d, z31.d }, pn11/z, [x13, x8, lsl #3]
+// CHECK-ENCODING: [0xb3,0xed,0x08,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a108edb3 <unknown>
+
+ld1d    {z19.d, z23.d, z27.d, z31.d}, pn15/z, [sp, xzr, lsl #3]  // 10100001-00011111-11111111-11110011
+// CHECK-INST: ld1d    { z19.d, z23.d, z27.d, z31.d }, pn15/z, [sp, xzr, lsl #3]
+// CHECK-ENCODING: [0xf3,0xff,0x1f,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a11ffff3 <unknown>
+
+
+ld1d    {z0.d, z4.d, z8.d, z12.d}, pn8/z, [x0]  // 10100001-01000000-11100000-00000000
+// CHECK-INST: ld1d    { z0.d, z4.d, z8.d, z12.d }, pn8/z, [x0]
+// CHECK-ENCODING: [0x00,0xe0,0x40,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a140e000 <unknown>
+
+ld1d    {z17.d, z21.d, z25.d, z29.d}, pn13/z, [x10, #20, mul vl]  // 10100001-01000101-11110101-01010001
+// CHECK-INST: ld1d    { z17.d, z21.d, z25.d, z29.d }, pn13/z, [x10, #20, mul vl]
+// CHECK-ENCODING: [0x51,0xf5,0x45,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a145f551 <unknown>
+
+ld1d    {z19.d, z23.d, z27.d, z31.d}, pn11/z, [x13, #-32, mul vl]  // 10100001-01001000-11101101-10110011
+// CHECK-INST: ld1d    { z19.d, z23.d, z27.d, z31.d }, pn11/z, [x13, #-32, mul vl]
+// CHECK-ENCODING: [0xb3,0xed,0x48,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a148edb3 <unknown>
+
+ld1d    {z19.d, z23.d, z27.d, z31.d}, pn15/z, [sp, #-4, mul vl]  // 10100001-01001111-11111111-11110011
+// CHECK-INST: ld1d    { z19.d, z23.d, z27.d, z31.d }, pn15/z, [sp, #-4, mul vl]
+// CHECK-ENCODING: [0xf3,0xff,0x4f,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a14ffff3 <unknown>
+

llvm/test/MC/AArch64/SME2/ld1h.s

+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
+// RUN:        | llvm-objdump -d --mattr=+sme2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
+// RUN:        | sed '/.text/d' | sed 's/.*encoding: //g' \
+// RUN:        | llvm-mc -triple=aarch64 -mattr=+sme2 -disassemble -show-encoding \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+
+
+ld1h    {z0.h, z8.h}, pn8/z, [x0, x0, lsl #1]  // 10100001-00000000-00100000-00000000
+// CHECK-INST: ld1h    { z0.h, z8.h }, pn8/z, [x0, x0, lsl #1]
+// CHECK-ENCODING: [0x00,0x20,0x00,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a1002000 <unknown>
+
+ld1h    {z21.h, z29.h}, pn13/z, [x10, x21, lsl #1]  // 10100001-00010101-00110101-01010101
+// CHECK-INST: ld1h    { z21.h, z29.h }, pn13/z, [x10, x21, lsl #1]
+// CHECK-ENCODING: [0x55,0x35,0x15,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a1153555 <unknown>
+
+ld1h    {z23.h, z31.h}, pn11/z, [x13, x8, lsl #1]  // 10100001-00001000-00101101-10110111
+// CHECK-INST: ld1h    { z23.h, z31.h }, pn11/z, [x13, x8, lsl #1]
+// CHECK-ENCODING: [0xb7,0x2d,0x08,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a1082db7 <unknown>
+
+ld1h    {z23.h, z31.h}, pn15/z, [sp, xzr, lsl #1]  // 10100001-00011111-00111111-11110111
+// CHECK-INST: ld1h    { z23.h, z31.h }, pn15/z, [sp, xzr, lsl #1]
+// CHECK-ENCODING: [0xf7,0x3f,0x1f,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a11f3ff7 <unknown>
+
+
+ld1h    {z0.h, z8.h}, pn8/z, [x0]  // 10100001-01000000-00100000-00000000
+// CHECK-INST: ld1h    { z0.h, z8.h }, pn8/z, [x0]
+// CHECK-ENCODING: [0x00,0x20,0x40,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a1402000 <unknown>
+
+ld1h    {z21.h, z29.h}, pn13/z, [x10, #10, mul vl]  // 10100001-01000101-00110101-01010101
+// CHECK-INST: ld1h    { z21.h, z29.h }, pn13/z, [x10, #10, mul vl]
+// CHECK-ENCODING: [0x55,0x35,0x45,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a1453555 <unknown>
+
+ld1h    {z23.h, z31.h}, pn11/z, [x13, #-16, mul vl]  // 10100001-01001000-00101101-10110111
+// CHECK-INST: ld1h    { z23.h, z31.h }, pn11/z, [x13, #-16, mul vl]
+// CHECK-ENCODING: [0xb7,0x2d,0x48,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a1482db7 <unknown>
+
+ld1h    {z23.h, z31.h}, pn15/z, [sp, #-2, mul vl]  // 10100001-01001111-00111111-11110111
+// CHECK-INST: ld1h    { z23.h, z31.h }, pn15/z, [sp, #-2, mul vl]
+// CHECK-ENCODING: [0xf7,0x3f,0x4f,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a14f3ff7 <unknown>
+
+
+ld1h    {z0.h, z4.h, z8.h, z12.h}, pn8/z, [x0, x0, lsl #1]  // 10100001-00000000-10100000-00000000
+// CHECK-INST: ld1h    { z0.h, z4.h, z8.h, z12.h }, pn8/z, [x0, x0, lsl #1]
+// CHECK-ENCODING: [0x00,0xa0,0x00,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a100a000 <unknown>
+
+ld1h    {z17.h, z21.h, z25.h, z29.h}, pn13/z, [x10, x21, lsl #1]  // 10100001-00010101-10110101-01010001
+// CHECK-INST: ld1h    { z17.h, z21.h, z25.h, z29.h }, pn13/z, [x10, x21, lsl #1]
+// CHECK-ENCODING: [0x51,0xb5,0x15,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a115b551 <unknown>
+
+ld1h    {z19.h, z23.h, z27.h, z31.h}, pn11/z, [x13, x8, lsl #1]  // 10100001-00001000-10101101-10110011
+// CHECK-INST: ld1h    { z19.h, z23.h, z27.h, z31.h }, pn11/z, [x13, x8, lsl #1]
+// CHECK-ENCODING: [0xb3,0xad,0x08,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a108adb3 <unknown>
+
+ld1h    {z19.h, z23.h, z27.h, z31.h}, pn15/z, [sp, xzr, lsl #1]  // 10100001-00011111-10111111-11110011
+// CHECK-INST: ld1h    { z19.h, z23.h, z27.h, z31.h }, pn15/z, [sp, xzr, lsl #1]
+// CHECK-ENCODING: [0xf3,0xbf,0x1f,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a11fbff3 <unknown>
+
+
+ld1h    {z0.h, z4.h, z8.h, z12.h}, pn8/z, [x0]  // 10100001-01000000-10100000-00000000
+// CHECK-INST: ld1h    { z0.h, z4.h, z8.h, z12.h }, pn8/z, [x0]
+// CHECK-ENCODING: [0x00,0xa0,0x40,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a140a000 <unknown>
+
+ld1h    {z17.h, z21.h, z25.h, z29.h}, pn13/z, [x10, #20, mul vl]  // 10100001-01000101-10110101-01010001
+// CHECK-INST: ld1h    { z17.h, z21.h, z25.h, z29.h }, pn13/z, [x10, #20, mul vl]
+// CHECK-ENCODING: [0x51,0xb5,0x45,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a145b551 <unknown>
+
+ld1h    {z19.h, z23.h, z27.h, z31.h}, pn11/z, [x13, #-32, mul vl]  // 10100001-01001000-10101101-10110011
+// CHECK-INST: ld1h    { z19.h, z23.h, z27.h, z31.h }, pn11/z, [x13, #-32, mul vl]
+// CHECK-ENCODING: [0xb3,0xad,0x48,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a148adb3 <unknown>
+
+ld1h    {z19.h, z23.h, z27.h, z31.h}, pn15/z, [sp, #-4, mul vl]  // 10100001-01001111-10111111-11110011
+// CHECK-INST: ld1h    { z19.h, z23.h, z27.h, z31.h }, pn15/z, [sp, #-4, mul vl]
+// CHECK-ENCODING: [0xf3,0xbf,0x4f,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a14fbff3 <unknown>
+

llvm/test/MC/AArch64/SME2/ld1w.s

+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
+// RUN:        | llvm-objdump -d --mattr=+sme2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
+// RUN:        | sed '/.text/d' | sed 's/.*encoding: //g' \
+// RUN:        | llvm-mc -triple=aarch64 -mattr=+sme2 -disassemble -show-encoding \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+
+
+ld1w    {z0.s, z8.s}, pn8/z, [x0, x0, lsl #2]  // 10100001-00000000-01000000-00000000
+// CHECK-INST: ld1w    { z0.s, z8.s }, pn8/z, [x0, x0, lsl #2]
+// CHECK-ENCODING: [0x00,0x40,0x00,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a1004000 <unknown>
+
+ld1w    {z21.s, z29.s}, pn13/z, [x10, x21, lsl #2]  // 10100001-00010101-01010101-01010101
+// CHECK-INST: ld1w    { z21.s, z29.s }, pn13/z, [x10, x21, lsl #2]
+// CHECK-ENCODING: [0x55,0x55,0x15,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a1155555 <unknown>
+
+ld1w    {z23.s, z31.s}, pn11/z, [x13, x8, lsl #2]  // 10100001-00001000-01001101-10110111
+// CHECK-INST: ld1w    { z23.s, z31.s }, pn11/z, [x13, x8, lsl #2]
+// CHECK-ENCODING: [0xb7,0x4d,0x08,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a1084db7 <unknown>
+
+ld1w    {z23.s, z31.s}, pn15/z, [sp, xzr, lsl #2]  // 10100001-00011111-01011111-11110111
+// CHECK-INST: ld1w    { z23.s, z31.s }, pn15/z, [sp, xzr, lsl #2]
+// CHECK-ENCODING: [0xf7,0x5f,0x1f,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a11f5ff7 <unknown>
+
+
+ld1w    {z0.s, z8.s}, pn8/z, [x0]  // 10100001-01000000-01000000-00000000
+// CHECK-INST: ld1w    { z0.s, z8.s }, pn8/z, [x0]
+// CHECK-ENCODING: [0x00,0x40,0x40,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a1404000 <unknown>
+
+ld1w    {z21.s, z29.s}, pn13/z, [x10, #10, mul vl]  // 10100001-01000101-01010101-01010101
+// CHECK-INST: ld1w    { z21.s, z29.s }, pn13/z, [x10, #10, mul vl]
+// CHECK-ENCODING: [0x55,0x55,0x45,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a1455555 <unknown>
+
+ld1w    {z23.s, z31.s}, pn11/z, [x13, #-16, mul vl]  // 10100001-01001000-01001101-10110111
+// CHECK-INST: ld1w    { z23.s, z31.s }, pn11/z, [x13, #-16, mul vl]
+// CHECK-ENCODING: [0xb7,0x4d,0x48,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a1484db7 <unknown>
+
+ld1w    {z23.s, z31.s}, pn15/z, [sp, #-2, mul vl]  // 10100001-01001111-01011111-11110111
+// CHECK-INST: ld1w    { z23.s, z31.s }, pn15/z, [sp, #-2, mul vl]
+// CHECK-ENCODING: [0xf7,0x5f,0x4f,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a14f5ff7 <unknown>
+
+
+ld1w    {z0.s, z4.s, z8.s, z12.s}, pn8/z, [x0, x0, lsl #2]  // 10100001-00000000-11000000-00000000
+// CHECK-INST: ld1w    { z0.s, z4.s, z8.s, z12.s }, pn8/z, [x0, x0, lsl #2]
+// CHECK-ENCODING: [0x00,0xc0,0x00,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a100c000 <unknown>
+
+ld1w    {z17.s, z21.s, z25.s, z29.s}, pn13/z, [x10, x21, lsl #2]  // 10100001-00010101-11010101-01010001
+// CHECK-INST: ld1w    { z17.s, z21.s, z25.s, z29.s }, pn13/z, [x10, x21, lsl #2]
+// CHECK-ENCODING: [0x51,0xd5,0x15,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a115d551 <unknown>
+
+ld1w    {z19.s, z23.s, z27.s, z31.s}, pn11/z, [x13, x8, lsl #2]  // 10100001-00001000-11001101-10110011
+// CHECK-INST: ld1w    { z19.s, z23.s, z27.s, z31.s }, pn11/z, [x13, x8, lsl #2]
+// CHECK-ENCODING: [0xb3,0xcd,0x08,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a108cdb3 <unknown>
+
+ld1w    {z19.s, z23.s, z27.s, z31.s}, pn15/z, [sp, xzr, lsl #2]  // 10100001-00011111-11011111-11110011
+// CHECK-INST: ld1w    { z19.s, z23.s, z27.s, z31.s }, pn15/z, [sp, xzr, lsl #2]
+// CHECK-ENCODING: [0xf3,0xdf,0x1f,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a11fdff3 <unknown>
+
+
+ld1w    {z0.s, z4.s, z8.s, z12.s}, pn8/z, [x0]  // 10100001-01000000-11000000-00000000
+// CHECK-INST: ld1w    { z0.s, z4.s, z8.s, z12.s }, pn8/z, [x0]
+// CHECK-ENCODING: [0x00,0xc0,0x40,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a140c000 <unknown>
+
+ld1w    {z17.s, z21.s, z25.s, z29.s}, pn13/z, [x10, #20, mul vl]  // 10100001-01000101-11010101-01010001
+// CHECK-INST: ld1w    { z17.s, z21.s, z25.s, z29.s }, pn13/z, [x10, #20, mul vl]
+// CHECK-ENCODING: [0x51,0xd5,0x45,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a145d551 <unknown>
+
+ld1w    {z19.s, z23.s, z27.s, z31.s}, pn11/z, [x13, #-32, mul vl]  // 10100001-01001000-11001101-10110011
+// CHECK-INST: ld1w    { z19.s, z23.s, z27.s, z31.s }, pn11/z, [x13, #-32, mul vl]
+// CHECK-ENCODING: [0xb3,0xcd,0x48,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a148cdb3 <unknown>
+
+ld1w    {z19.s, z23.s, z27.s, z31.s}, pn15/z, [sp, #-4, mul vl]  // 10100001-01001111-11011111-11110011
+// CHECK-INST: ld1w    { z19.s, z23.s, z27.s, z31.s }, pn15/z, [sp, #-4, mul vl]
+// CHECK-ENCODING: [0xf3,0xdf,0x4f,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a14fdff3 <unknown>
+

llvm/test/MC/AArch64/SME2/ldnt1b.s

+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
+// RUN:        | llvm-objdump -d --mattr=+sme2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
+// RUN:        | sed '/.text/d' | sed 's/.*encoding: //g' \
+// RUN:        | llvm-mc -triple=aarch64 -mattr=+sme2 -disassemble -show-encoding \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+
+
+ldnt1b  {z0.b, z8.b}, pn8/z, [x0, x0]  // 10100001-00000000-00000000-00001000
+// CHECK-INST: ldnt1b  { z0.b, z8.b }, pn8/z, [x0, x0]
+// CHECK-ENCODING: [0x08,0x00,0x00,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a1000008 <unknown>
+
+ldnt1b  {z21.b, z29.b}, pn13/z, [x10, x21]  // 10100001-00010101-00010101-01011101
+// CHECK-INST: ldnt1b  { z21.b, z29.b }, pn13/z, [x10, x21]
+// CHECK-ENCODING: [0x5d,0x15,0x15,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a115155d <unknown>
+
+ldnt1b  {z23.b, z31.b}, pn11/z, [x13, x8]  // 10100001-00001000-00001101-10111111
+// CHECK-INST: ldnt1b  { z23.b, z31.b }, pn11/z, [x13, x8]
+// CHECK-ENCODING: [0xbf,0x0d,0x08,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a1080dbf <unknown>
+
+ldnt1b  {z23.b, z31.b}, pn15/z, [sp, xzr]  // 10100001-00011111-00011111-11111111
+// CHECK-INST: ldnt1b  { z23.b, z31.b }, pn15/z, [sp, xzr]
+// CHECK-ENCODING: [0xff,0x1f,0x1f,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a11f1fff <unknown>
+
+
+ldnt1b  {z0.b, z8.b}, pn8/z, [x0]  // 10100001-01000000-00000000-00001000
+// CHECK-INST: ldnt1b  { z0.b, z8.b }, pn8/z, [x0]
+// CHECK-ENCODING: [0x08,0x00,0x40,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a1400008 <unknown>
+
+ldnt1b  {z21.b, z29.b}, pn13/z, [x10, #10, mul vl]  // 10100001-01000101-00010101-01011101
+// CHECK-INST: ldnt1b  { z21.b, z29.b }, pn13/z, [x10, #10, mul vl]
+// CHECK-ENCODING: [0x5d,0x15,0x45,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a145155d <unknown>
+
+ldnt1b  {z23.b, z31.b}, pn11/z, [x13, #-16, mul vl]  // 10100001-01001000-00001101-10111111
+// CHECK-INST: ldnt1b  { z23.b, z31.b }, pn11/z, [x13, #-16, mul vl]
+// CHECK-ENCODING: [0xbf,0x0d,0x48,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a1480dbf <unknown>
+
+ldnt1b  {z23.b, z31.b}, pn15/z, [sp, #-2, mul vl]  // 10100001-01001111-00011111-11111111
+// CHECK-INST: ldnt1b  { z23.b, z31.b }, pn15/z, [sp, #-2, mul vl]
+// CHECK-ENCODING: [0xff,0x1f,0x4f,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a14f1fff <unknown>
+
+
+ldnt1b  {z0.b, z4.b, z8.b, z12.b}, pn8/z, [x0, x0]  // 10100001-00000000-10000000-00001000
+// CHECK-INST: ldnt1b  { z0.b, z4.b, z8.b, z12.b }, pn8/z, [x0, x0]
+// CHECK-ENCODING: [0x08,0x80,0x00,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a1008008 <unknown>
+
+ldnt1b  {z17.b, z21.b, z25.b, z29.b}, pn13/z, [x10, x21]  // 10100001-00010101-10010101-01011001
+// CHECK-INST: ldnt1b  { z17.b, z21.b, z25.b, z29.b }, pn13/z, [x10, x21]
+// CHECK-ENCODING: [0x59,0x95,0x15,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a1159559 <unknown>
+
+ldnt1b  {z19.b, z23.b, z27.b, z31.b}, pn11/z, [x13, x8]  // 10100001-00001000-10001101-10111011
+// CHECK-INST: ldnt1b  { z19.b, z23.b, z27.b, z31.b }, pn11/z, [x13, x8]
+// CHECK-ENCODING: [0xbb,0x8d,0x08,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a1088dbb <unknown>
+
+ldnt1b  {z19.b, z23.b, z27.b, z31.b}, pn15/z, [sp, xzr]  // 10100001-00011111-10011111-11111011
+// CHECK-INST: ldnt1b  { z19.b, z23.b, z27.b, z31.b }, pn15/z, [sp, xzr]
+// CHECK-ENCODING: [0xfb,0x9f,0x1f,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a11f9ffb <unknown>
+
+
+ldnt1b  {z0.b, z4.b, z8.b, z12.b}, pn8/z, [x0]  // 10100001-01000000-10000000-00001000
+// CHECK-INST: ldnt1b  { z0.b, z4.b, z8.b, z12.b }, pn8/z, [x0]
+// CHECK-ENCODING: [0x08,0x80,0x40,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a1408008 <unknown>
+
+ldnt1b  {z17.b, z21.b, z25.b, z29.b}, pn13/z, [x10, #20, mul vl]  // 10100001-01000101-10010101-01011001
+// CHECK-INST: ldnt1b  { z17.b, z21.b, z25.b, z29.b }, pn13/z, [x10, #20, mul vl]
+// CHECK-ENCODING: [0x59,0x95,0x45,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a1459559 <unknown>
+
+ldnt1b  {z19.b, z23.b, z27.b, z31.b}, pn11/z, [x13, #-32, mul vl]  // 10100001-01001000-10001101-10111011
+// CHECK-INST: ldnt1b  { z19.b, z23.b, z27.b, z31.b }, pn11/z, [x13, #-32, mul vl]
+// CHECK-ENCODING: [0xbb,0x8d,0x48,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a1488dbb <unknown>
+
+ldnt1b  {z19.b, z23.b, z27.b, z31.b}, pn15/z, [sp, #-4, mul vl]  // 10100001-01001111-10011111-11111011
+// CHECK-INST: ldnt1b  { z19.b, z23.b, z27.b, z31.b }, pn15/z, [sp, #-4, mul vl]
+// CHECK-ENCODING: [0xfb,0x9f,0x4f,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a14f9ffb <unknown>
+

llvm/test/MC/AArch64/SME2/ldnt1d.s

+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
+// RUN:        | llvm-objdump -d --mattr=+sme2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
+// RUN:        | sed '/.text/d' | sed 's/.*encoding: //g' \
+// RUN:        | llvm-mc -triple=aarch64 -mattr=+sme2 -disassemble -show-encoding \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+
+
+ldnt1d  {z0.d, z8.d}, pn8/z, [x0, x0, lsl #3]  // 10100001-00000000-01100000-00001000
+// CHECK-INST: ldnt1d  { z0.d, z8.d }, pn8/z, [x0, x0, lsl #3]
+// CHECK-ENCODING: [0x08,0x60,0x00,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a1006008 <unknown>
+
+ldnt1d  {z21.d, z29.d}, pn13/z, [x10, x21, lsl #3]  // 10100001-00010101-01110101-01011101
+// CHECK-INST: ldnt1d  { z21.d, z29.d }, pn13/z, [x10, x21, lsl #3]
+// CHECK-ENCODING: [0x5d,0x75,0x15,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a115755d <unknown>
+
+ldnt1d  {z23.d, z31.d}, pn11/z, [x13, x8, lsl #3]  // 10100001-00001000-01101101-10111111
+// CHECK-INST: ldnt1d  { z23.d, z31.d }, pn11/z, [x13, x8, lsl #3]
+// CHECK-ENCODING: [0xbf,0x6d,0x08,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a1086dbf <unknown>
+
+ldnt1d  {z23.d, z31.d}, pn15/z, [sp, xzr, lsl #3]  // 10100001-00011111-01111111-11111111
+// CHECK-INST: ldnt1d  { z23.d, z31.d }, pn15/z, [sp, xzr, lsl #3]
+// CHECK-ENCODING: [0xff,0x7f,0x1f,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a11f7fff <unknown>
+
+
+ldnt1d  {z0.d, z8.d}, pn8/z, [x0]  // 10100001-01000000-01100000-00001000
+// CHECK-INST: ldnt1d  { z0.d, z8.d }, pn8/z, [x0]
+// CHECK-ENCODING: [0x08,0x60,0x40,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a1406008 <unknown>
+
+ldnt1d  {z21.d, z29.d}, pn13/z, [x10, #10, mul vl]  // 10100001-01000101-01110101-01011101
+// CHECK-INST: ldnt1d  { z21.d, z29.d }, pn13/z, [x10, #10, mul vl]
+// CHECK-ENCODING: [0x5d,0x75,0x45,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a145755d <unknown>
+
+ldnt1d  {z23.d, z31.d}, pn11/z, [x13, #-16, mul vl]  // 10100001-01001000-01101101-10111111
+// CHECK-INST: ldnt1d  { z23.d, z31.d }, pn11/z, [x13, #-16, mul vl]
+// CHECK-ENCODING: [0xbf,0x6d,0x48,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a1486dbf <unknown>
+
+ldnt1d  {z23.d, z31.d}, pn15/z, [sp, #-2, mul vl]  // 10100001-01001111-01111111-11111111
+// CHECK-INST: ldnt1d  { z23.d, z31.d }, pn15/z, [sp, #-2, mul vl]
+// CHECK-ENCODING: [0xff,0x7f,0x4f,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a14f7fff <unknown>
+
+
+ldnt1d  {z0.d, z4.d, z8.d, z12.d}, pn8/z, [x0, x0, lsl #3]  // 10100001-00000000-11100000-00001000
+// CHECK-INST: ldnt1d  { z0.d, z4.d, z8.d, z12.d }, pn8/z, [x0, x0, lsl #3]
+// CHECK-ENCODING: [0x08,0xe0,0x00,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a100e008 <unknown>
+
+ldnt1d  {z17.d, z21.d, z25.d, z29.d}, pn13/z, [x10, x21, lsl #3]  // 10100001-00010101-11110101-01011001
+// CHECK-INST: ldnt1d  { z17.d, z21.d, z25.d, z29.d }, pn13/z, [x10, x21, lsl #3]
+// CHECK-ENCODING: [0x59,0xf5,0x15,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a115f559 <unknown>
+
+ldnt1d  {z19.d, z23.d, z27.d, z31.d}, pn11/z, [x13, x8, lsl #3]  // 10100001-00001000-11101101-10111011
+// CHECK-INST: ldnt1d  { z19.d, z23.d, z27.d, z31.d }, pn11/z, [x13, x8, lsl #3]
+// CHECK-ENCODING: [0xbb,0xed,0x08,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a108edbb <unknown>
+
+ldnt1d  {z19.d, z23.d, z27.d, z31.d}, pn15/z, [sp, xzr, lsl #3]  // 10100001-00011111-11111111-11111011
+// CHECK-INST: ldnt1d  { z19.d, z23.d, z27.d, z31.d }, pn15/z, [sp, xzr, lsl #3]
+// CHECK-ENCODING: [0xfb,0xff,0x1f,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a11ffffb <unknown>
+
+
+ldnt1d  {z0.d, z4.d, z8.d, z12.d}, pn8/z, [x0]  // 10100001-01000000-11100000-00001000
+// CHECK-INST: ldnt1d  { z0.d, z4.d, z8.d, z12.d }, pn8/z, [x0]
+// CHECK-ENCODING: [0x08,0xe0,0x40,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a140e008 <unknown>
+
+ldnt1d  {z17.d, z21.d, z25.d, z29.d}, pn13/z, [x10, #20, mul vl]  // 10100001-01000101-11110101-01011001
+// CHECK-INST: ldnt1d  { z17.d, z21.d, z25.d, z29.d }, pn13/z, [x10, #20, mul vl]
+// CHECK-ENCODING: [0x59,0xf5,0x45,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a145f559 <unknown>
+
+ldnt1d  {z19.d, z23.d, z27.d, z31.d}, pn11/z, [x13, #-32, mul vl]  // 10100001-01001000-11101101-10111011
+// CHECK-INST: ldnt1d  { z19.d, z23.d, z27.d, z31.d }, pn11/z, [x13, #-32, mul vl]
+// CHECK-ENCODING: [0xbb,0xed,0x48,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a148edbb <unknown>
+
+ldnt1d  {z19.d, z23.d, z27.d, z31.d}, pn15/z, [sp, #-4, mul vl]  // 10100001-01001111-11111111-11111011
+// CHECK-INST: ldnt1d  { z19.d, z23.d, z27.d, z31.d }, pn15/z, [sp, #-4, mul vl]
+// CHECK-ENCODING: [0xfb,0xff,0x4f,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a14ffffb <unknown>
+

llvm/test/MC/AArch64/SME2/ldnt1h.s

+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
+// RUN:        | llvm-objdump -d --mattr=+sme2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
+// RUN:        | sed '/.text/d' | sed 's/.*encoding: //g' \
+// RUN:        | llvm-mc -triple=aarch64 -mattr=+sme2 -disassemble -show-encoding \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+
+
+ldnt1h  {z0.h, z8.h}, pn8/z, [x0, x0, lsl #1]  // 10100001-00000000-00100000-00001000
+// CHECK-INST: ldnt1h  { z0.h, z8.h }, pn8/z, [x0, x0, lsl #1]
+// CHECK-ENCODING: [0x08,0x20,0x00,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a1002008 <unknown>
+
+ldnt1h  {z21.h, z29.h}, pn13/z, [x10, x21, lsl #1]  // 10100001-00010101-00110101-01011101
+// CHECK-INST: ldnt1h  { z21.h, z29.h }, pn13/z, [x10, x21, lsl #1]
+// CHECK-ENCODING: [0x5d,0x35,0x15,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a115355d <unknown>
+
+ldnt1h  {z23.h, z31.h}, pn11/z, [x13, x8, lsl #1]  // 10100001-00001000-00101101-10111111
+// CHECK-INST: ldnt1h  { z23.h, z31.h }, pn11/z, [x13, x8, lsl #1]
+// CHECK-ENCODING: [0xbf,0x2d,0x08,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a1082dbf <unknown>
+
+ldnt1h  {z23.h, z31.h}, pn15/z, [sp, xzr, lsl #1]  // 10100001-00011111-00111111-11111111
+// CHECK-INST: ldnt1h  { z23.h, z31.h }, pn15/z, [sp, xzr, lsl #1]
+// CHECK-ENCODING: [0xff,0x3f,0x1f,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a11f3fff <unknown>
+
+
+ldnt1h  {z0.h, z8.h}, pn8/z, [x0]  // 10100001-01000000-00100000-00001000
+// CHECK-INST: ldnt1h  { z0.h, z8.h }, pn8/z, [x0]
+// CHECK-ENCODING: [0x08,0x20,0x40,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a1402008 <unknown>
+
+ldnt1h  {z21.h, z29.h}, pn13/z, [x10, #10, mul vl]  // 10100001-01000101-00110101-01011101
+// CHECK-INST: ldnt1h  { z21.h, z29.h }, pn13/z, [x10, #10, mul vl]
+// CHECK-ENCODING: [0x5d,0x35,0x45,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a145355d <unknown>
+
+ldnt1h  {z23.h, z31.h}, pn11/z, [x13, #-16, mul vl]  // 10100001-01001000-00101101-10111111
+// CHECK-INST: ldnt1h  { z23.h, z31.h }, pn11/z, [x13, #-16, mul vl]
+// CHECK-ENCODING: [0xbf,0x2d,0x48,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a1482dbf <unknown>
+
+ldnt1h  {z23.h, z31.h}, pn15/z, [sp, #-2, mul vl]  // 10100001-01001111-00111111-11111111
+// CHECK-INST: ldnt1h  { z23.h, z31.h }, pn15/z, [sp, #-2, mul vl]
+// CHECK-ENCODING: [0xff,0x3f,0x4f,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a14f3fff <unknown>
+
+
+ldnt1h  {z0.h, z4.h, z8.h, z12.h}, pn8/z, [x0, x0, lsl #1]  // 10100001-00000000-10100000-00001000
+// CHECK-INST: ldnt1h  { z0.h, z4.h, z8.h, z12.h }, pn8/z, [x0, x0, lsl #1]
+// CHECK-ENCODING: [0x08,0xa0,0x00,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a100a008 <unknown>
+
+ldnt1h  {z17.h, z21.h, z25.h, z29.h}, pn13/z, [x10, x21, lsl #1]  // 10100001-00010101-10110101-01011001
+// CHECK-INST: ldnt1h  { z17.h, z21.h, z25.h, z29.h }, pn13/z, [x10, x21, lsl #1]
+// CHECK-ENCODING: [0x59,0xb5,0x15,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a115b559 <unknown>
+
+ldnt1h  {z19.h, z23.h, z27.h, z31.h}, pn11/z, [x13, x8, lsl #1]  // 10100001-00001000-10101101-10111011
+// CHECK-INST: ldnt1h  { z19.h, z23.h, z27.h, z31.h }, pn11/z, [x13, x8, lsl #1]
+// CHECK-ENCODING: [0xbb,0xad,0x08,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a108adbb <unknown>
+
+ldnt1h  {z19.h, z23.h, z27.h, z31.h}, pn15/z, [sp, xzr, lsl #1]  // 10100001-00011111-10111111-11111011
+// CHECK-INST: ldnt1h  { z19.h, z23.h, z27.h, z31.h }, pn15/z, [sp, xzr, lsl #1]
+// CHECK-ENCODING: [0xfb,0xbf,0x1f,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a11fbffb <unknown>
+
+
+ldnt1h  {z0.h, z4.h, z8.h, z12.h}, pn8/z, [x0]  // 10100001-01000000-10100000-00001000
+// CHECK-INST: ldnt1h  { z0.h, z4.h, z8.h, z12.h }, pn8/z, [x0]
+// CHECK-ENCODING: [0x08,0xa0,0x40,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a140a008 <unknown>
+
+ldnt1h  {z17.h, z21.h, z25.h, z29.h}, pn13/z, [x10, #20, mul vl]  // 10100001-01000101-10110101-01011001
+// CHECK-INST: ldnt1h  { z17.h, z21.h, z25.h, z29.h }, pn13/z, [x10, #20, mul vl]
+// CHECK-ENCODING: [0x59,0xb5,0x45,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a145b559 <unknown>
+
+ldnt1h  {z19.h, z23.h, z27.h, z31.h}, pn11/z, [x13, #-32, mul vl]  // 10100001-01001000-10101101-10111011
+// CHECK-INST: ldnt1h  { z19.h, z23.h, z27.h, z31.h }, pn11/z, [x13, #-32, mul vl]
+// CHECK-ENCODING: [0xbb,0xad,0x48,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a148adbb <unknown>
+
+ldnt1h  {z19.h, z23.h, z27.h, z31.h}, pn15/z, [sp, #-4, mul vl]  // 10100001-01001111-10111111-11111011
+// CHECK-INST: ldnt1h  { z19.h, z23.h, z27.h, z31.h }, pn15/z, [sp, #-4, mul vl]
+// CHECK-ENCODING: [0xfb,0xbf,0x4f,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a14fbffb <unknown>
+

llvm/test/MC/AArch64/SME2/ldnt1w.s

+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
+// RUN:        | llvm-objdump -d --mattr=+sme2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
+// RUN:        | sed '/.text/d' | sed 's/.*encoding: //g' \
+// RUN:        | llvm-mc -triple=aarch64 -mattr=+sme2 -disassemble -show-encoding \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+
+
+ldnt1w  {z0.s, z8.s}, pn8/z, [x0, x0, lsl #2]  // 10100001-00000000-01000000-00001000
+// CHECK-INST: ldnt1w  { z0.s, z8.s }, pn8/z, [x0, x0, lsl #2]
+// CHECK-ENCODING: [0x08,0x40,0x00,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a1004008 <unknown>
+
+ldnt1w  {z21.s, z29.s}, pn13/z, [x10, x21, lsl #2]  // 10100001-00010101-01010101-01011101
+// CHECK-INST: ldnt1w  { z21.s, z29.s }, pn13/z, [x10, x21, lsl #2]
+// CHECK-ENCODING: [0x5d,0x55,0x15,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a115555d <unknown>
+
+ldnt1w  {z23.s, z31.s}, pn11/z, [x13, x8, lsl #2]  // 10100001-00001000-01001101-10111111
+// CHECK-INST: ldnt1w  { z23.s, z31.s }, pn11/z, [x13, x8, lsl #2]
+// CHECK-ENCODING: [0xbf,0x4d,0x08,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a1084dbf <unknown>
+
+ldnt1w  {z23.s, z31.s}, pn15/z, [sp, xzr, lsl #2]  // 10100001-00011111-01011111-11111111
+// CHECK-INST: ldnt1w  { z23.s, z31.s }, pn15/z, [sp, xzr, lsl #2]
+// CHECK-ENCODING: [0xff,0x5f,0x1f,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a11f5fff <unknown>
+
+
+ldnt1w  {z0.s, z8.s}, pn8/z, [x0]  // 10100001-01000000-01000000-00001000
+// CHECK-INST: ldnt1w  { z0.s, z8.s }, pn8/z, [x0]
+// CHECK-ENCODING: [0x08,0x40,0x40,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a1404008 <unknown>
+
+ldnt1w  {z21.s, z29.s}, pn13/z, [x10, #10, mul vl]  // 10100001-01000101-01010101-01011101
+// CHECK-INST: ldnt1w  { z21.s, z29.s }, pn13/z, [x10, #10, mul vl]
+// CHECK-ENCODING: [0x5d,0x55,0x45,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a145555d <unknown>
+
+ldnt1w  {z23.s, z31.s}, pn11/z, [x13, #-16, mul vl]  // 10100001-01001000-01001101-10111111
+// CHECK-INST: ldnt1w  { z23.s, z31.s }, pn11/z, [x13, #-16, mul vl]
+// CHECK-ENCODING: [0xbf,0x4d,0x48,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a1484dbf <unknown>
+
+ldnt1w  {z23.s, z31.s}, pn15/z, [sp, #-2, mul vl]  // 10100001-01001111-01011111-11111111
+// CHECK-INST: ldnt1w  { z23.s, z31.s }, pn15/z, [sp, #-2, mul vl]
+// CHECK-ENCODING: [0xff,0x5f,0x4f,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a14f5fff <unknown>
+
+
+ldnt1w  {z0.s, z4.s, z8.s, z12.s}, pn8/z, [x0, x0, lsl #2]  // 10100001-00000000-11000000-00001000
+// CHECK-INST: ldnt1w  { z0.s, z4.s, z8.s, z12.s }, pn8/z, [x0, x0, lsl #2]
+// CHECK-ENCODING: [0x08,0xc0,0x00,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a100c008 <unknown>
+
+ldnt1w  {z17.s, z21.s, z25.s, z29.s}, pn13/z, [x10, x21, lsl #2]  // 10100001-00010101-11010101-01011001
+// CHECK-INST: ldnt1w  { z17.s, z21.s, z25.s, z29.s }, pn13/z, [x10, x21, lsl #2]
+// CHECK-ENCODING: [0x59,0xd5,0x15,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a115d559 <unknown>
+
+ldnt1w  {z19.s, z23.s, z27.s, z31.s}, pn11/z, [x13, x8, lsl #2]  // 10100001-00001000-11001101-10111011
+// CHECK-INST: ldnt1w  { z19.s, z23.s, z27.s, z31.s }, pn11/z, [x13, x8, lsl #2]
+// CHECK-ENCODING: [0xbb,0xcd,0x08,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a108cdbb <unknown>
+
+ldnt1w  {z19.s, z23.s, z27.s, z31.s}, pn15/z, [sp, xzr, lsl #2]  // 10100001-00011111-11011111-11111011
+// CHECK-INST: ldnt1w  { z19.s, z23.s, z27.s, z31.s }, pn15/z, [sp, xzr, lsl #2]
+// CHECK-ENCODING: [0xfb,0xdf,0x1f,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a11fdffb <unknown>
+
+
+ldnt1w  {z0.s, z4.s, z8.s, z12.s}, pn8/z, [x0]  // 10100001-01000000-11000000-00001000
+// CHECK-INST: ldnt1w  { z0.s, z4.s, z8.s, z12.s }, pn8/z, [x0]
+// CHECK-ENCODING: [0x08,0xc0,0x40,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a140c008 <unknown>
+
+ldnt1w  {z17.s, z21.s, z25.s, z29.s}, pn13/z, [x10, #20, mul vl]  // 10100001-01000101-11010101-01011001
+// CHECK-INST: ldnt1w  { z17.s, z21.s, z25.s, z29.s }, pn13/z, [x10, #20, mul vl]
+// CHECK-ENCODING: [0x59,0xd5,0x45,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a145d559 <unknown>
+
+ldnt1w  {z19.s, z23.s, z27.s, z31.s}, pn11/z, [x13, #-32, mul vl]  // 10100001-01001000-11001101-10111011
+// CHECK-INST: ldnt1w  { z19.s, z23.s, z27.s, z31.s }, pn11/z, [x13, #-32, mul vl]
+// CHECK-ENCODING: [0xbb,0xcd,0x48,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a148cdbb <unknown>
+
+ldnt1w  {z19.s, z23.s, z27.s, z31.s}, pn15/z, [sp, #-4, mul vl]  // 10100001-01001111-11011111-11111011
+// CHECK-INST: ldnt1w  { z19.s, z23.s, z27.s, z31.s }, pn15/z, [sp, #-4, mul vl]
+// CHECK-ENCODING: [0xfb,0xdf,0x4f,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a14fdffb <unknown>
+

llvm/test/MC/AArch64/SME2/sqdmulh-diagnostics.s

 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 sqdmulh {z0.s,z1.s}, {z2.s,z3.s}, z15.s
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register list
 // CHECK-NEXT: sqdmulh {z0.s,z1.s}, {z2.s,z3.s}, z15.s
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 sqdmulh {z0.s,z1.s}, {z0.s,z2.s}, z15.s
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must be sequential
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
 // CHECK-NEXT: sqdmulh {z0.s,z1.s}, {z0.s,z2.s}, z15.s
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 sqdmulh {z0.s,z1.s}, {z0.s,z1.s,z2.s}, z15.s
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
 // CHECK-NEXT: sqdmulh {z0.s,z1.s}, {z0.s,z1.s,z2.s}, z15.s
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 

llvm/test/MC/AArch64/SME2/st1b

+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
+// RUN:        | llvm-objdump -d --mattr=+sme2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
+// RUN:        | sed '/.text/d' | sed 's/.*encoding: //g' \
+// RUN:        | llvm-mc -triple=aarch64 -mattr=+sme2 -disassemble -show-encoding \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+
+
+st1b    {z0.b, z1.b}, pn8, [x0, x0]  // 10100000, 00100000, 00000000, 00000000
+// CHECK, INST: st1b    { z0.b, z1.b }, pn8, [x0, x0]
+// CHECK-ENCODING: [0x00,0x00,0x20,0xa0]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: a0200000 <unknown>
+
+st1b    {z20.b, z21.b}, pn13, [x10, x21]  // 10100000, 00110101, 00010101, 01010100
+// CHECK, INST: st1b    { z20.b, z21.b }, pn13, [x10, x21]
+// CHECK-ENCODING: [0x54,0x15,0x35,0xa0]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: a0351554 <unknown>
+
+st1b    {z22.b, z23.b}, pn11, [x13, x8]  // 10100000, 00101000, 00001101, 10110110
+// CHECK, INST: st1b    { z22.b, z23.b }, pn11, [x13, x8]
+// CHECK-ENCODING: [0xb6,0x0d,0x28,0xa0]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: a0280db6 <unknown>
+
+st1b    {z30.b, z31.b}, pn15, [sp, xzr]  // 10100000, 00111111, 00011111, 11111110
+// CHECK, INST: st1b    { z30.b, z31.b }, pn15, [sp, xzr]
+// CHECK-ENCODING: [0xfe,0x1f,0x3f,0xa0]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: a03f1ffe <unknown>
+
+
+st1b    {z0.b, z1.b}, pn8, [x0]  // 10100000, 01100000, 00000000, 00000000
+// CHECK, INST: st1b    { z0.b, z1.b }, pn8, [x0]
+// CHECK-ENCODING: [0x00,0x00,0x60,0xa0]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: a0600000 <unknown>
+
+st1b    {z20.b, z21.b}, pn13, [x10, #10, mul vl]  // 10100000, 01100101, 00010101, 01010100
+// CHECK, INST: st1b    { z20.b, z21.b }, pn13, [x10, #10, mul vl]
+// CHECK-ENCODING: [0x54,0x15,0x65,0xa0]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: a0651554 <unknown>
+
+st1b    {z22.b, z23.b}, pn11, [x13, #, 16, mul vl]  // 10100000, 01101000, 00001101, 10110110
+// CHECK, INST: st1b    { z22.b, z23.b }, pn11, [x13, #, 16, mul vl]
+// CHECK-ENCODING: [0xb6,0x0d,0x68,0xa0]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: a0680db6 <unknown>
+
+st1b    {z30.b, z31.b}, pn15, [sp, #, 2, mul vl]  // 10100000, 01101111, 00011111, 11111110
+// CHECK, INST: st1b    { z30.b, z31.b }, pn15, [sp, #, 2, mul vl]
+// CHECK-ENCODING: [0xfe,0x1f,0x6f,0xa0]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: a06f1ffe <unknown>
+
+
+st1b    {z0.b, z8.b}, pn8, [x0, x0]  // 10100001-00100000-00000000-00000000
+// CHECK-INST: st1b    { z0.b, z8.b }, pn8, [x0, x0]
+// CHECK-ENCODING: [0x00,0x00,0x20,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a1200000 <unknown>
+
+st1b    {z21.b, z29.b}, pn13, [x10, x21]  // 10100001-00110101-00010101-01010101
+// CHECK-INST: st1b    { z21.b, z29.b }, pn13, [x10, x21]
+// CHECK-ENCODING: [0x55,0x15,0x35,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a1351555 <unknown>
+
+st1b    {z23.b, z31.b}, pn11, [x13, x8]  // 10100001-00101000-00001101-10110111
+// CHECK-INST: st1b    { z23.b, z31.b }, pn11, [x13, x8]
+// CHECK-ENCODING: [0xb7,0x0d,0x28,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a1280db7 <unknown>
+
+st1b    {z23.b, z31.b}, pn15, [sp, xzr]  // 10100001-00111111-00011111-11110111
+// CHECK-INST: st1b    { z23.b, z31.b }, pn15, [sp, xzr]
+// CHECK-ENCODING: [0xf7,0x1f,0x3f,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a13f1ff7 <unknown>
+
+
+st1b    {z0.b, z8.b}, pn8, [x0]  // 10100001-01100000-00000000-00000000
+// CHECK-INST: st1b    { z0.b, z8.b }, pn8, [x0]
+// CHECK-ENCODING: [0x00,0x00,0x60,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a1600000 <unknown>
+
+st1b    {z21.b, z29.b}, pn13, [x10, #10, mul vl]  // 10100001-01100101-00010101-01010101
+// CHECK-INST: st1b    { z21.b, z29.b }, pn13, [x10, #10, mul vl]
+// CHECK-ENCODING: [0x55,0x15,0x65,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a1651555 <unknown>
+
+st1b    {z23.b, z31.b}, pn11, [x13, #-16, mul vl]  // 10100001-01101000-00001101-10110111
+// CHECK-INST: st1b    { z23.b, z31.b }, pn11, [x13, #-16, mul vl]
+// CHECK-ENCODING: [0xb7,0x0d,0x68,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a1680db7 <unknown>
+
+st1b    {z23.b, z31.b}, pn15, [sp, #-2, mul vl]  // 10100001-01101111-00011111-11110111
+// CHECK-INST: st1b    { z23.b, z31.b }, pn15, [sp, #-2, mul vl]
+// CHECK-ENCODING: [0xf7,0x1f,0x6f,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a16f1ff7 <unknown>
+
+
+st1b    {z0.b-z3.b}, pn8, [x0, x0]  // 10100000-00100000-10000000-00000000
+// CHECK-INST: st1b    { z0.b-z3.b }, pn8, [x0, x0]
+// CHECK-ENCODING: [0x00,0x80,0x20,0xa0]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: a0208000 <unknown>
+
+st1b    {z20.b-z23.b}, pn13, [x10, x21]  // 10100000-00110101-10010101-01010100
+// CHECK-INST: st1b    { z20.b-z23.b }, pn13, [x10, x21]
+// CHECK-ENCODING: [0x54,0x95,0x35,0xa0]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: a0359554 <unknown>
+
+st1b    {z20.b-z23.b}, pn11, [x13, x8]  // 10100000-00101000-10001101-10110100
+// CHECK-INST: st1b    { z20.b-z23.b }, pn11, [x13, x8]
+// CHECK-ENCODING: [0xb4,0x8d,0x28,0xa0]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: a0288db4 <unknown>
+
+st1b    {z28.b-z31.b}, pn15, [sp, xzr]  // 10100000-00111111-10011111-11111100
+// CHECK-INST: st1b    { z28.b-z31.b }, pn15, [sp, xzr]
+// CHECK-ENCODING: [0xfc,0x9f,0x3f,0xa0]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: a03f9ffc <unknown>
+
+
+st1b    {z0.b-z3.b}, pn8, [x0]  // 10100000-01100000-10000000-00000000
+// CHECK-INST: st1b    { z0.b-z3.b }, pn8, [x0]
+// CHECK-ENCODING: [0x00,0x80,0x60,0xa0]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: a0608000 <unknown>
+
+st1b    {z20.b-z23.b}, pn13, [x10, #20, mul vl]  // 10100000-01100101-10010101-01010100
+// CHECK-INST: st1b    { z20.b-z23.b }, pn13, [x10, #20, mul vl]
+// CHECK-ENCODING: [0x54,0x95,0x65,0xa0]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: a0659554 <unknown>
+
+st1b    {z20.b-z23.b}, pn11, [x13, #-32, mul vl]  // 10100000-01101000-10001101-10110100
+// CHECK-INST: st1b    { z20.b-z23.b }, pn11, [x13, #-32, mul vl]
+// CHECK-ENCODING: [0xb4,0x8d,0x68,0xa0]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: a0688db4 <unknown>
+
+st1b    {z28.b-z31.b}, pn15, [sp, #-4, mul vl]  // 10100000-01101111-10011111-11111100
+// CHECK-INST: st1b    { z28.b-z31.b }, pn15, [sp, #-4, mul vl]
+// CHECK-ENCODING: [0xfc,0x9f,0x6f,0xa0]
+// CHECK-ERROR: instruction requires: sme2 or sve2p1
+// CHECK-UNKNOWN: a06f9ffc <unknown>
+
+
+st1b    {z0.b, z4.b, z8.b, z12.b}, pn8, [x0, x0]  // 10100001-00100000-10000000-00000000
+// CHECK-INST: st1b    { z0.b, z4.b, z8.b, z12.b }, pn8, [x0, x0]
+// CHECK-ENCODING: [0x00,0x80,0x20,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a1208000 <unknown>
+
+st1b    {z17.b, z21.b, z25.b, z29.b}, pn13, [x10, x21]  // 10100001-00110101-10010101-01010001
+// CHECK-INST: st1b    { z17.b, z21.b, z25.b, z29.b }, pn13, [x10, x21]
+// CHECK-ENCODING: [0x51,0x95,0x35,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a1359551 <unknown>
+
+st1b    {z19.b, z23.b, z27.b, z31.b}, pn11, [x13, x8]  // 10100001-00101000-10001101-10110011
+// CHECK-INST: st1b    { z19.b, z23.b, z27.b, z31.b }, pn11, [x13, x8]
+// CHECK-ENCODING: [0xb3,0x8d,0x28,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a1288db3 <unknown>
+
+st1b    {z19.b, z23.b, z27.b, z31.b}, pn15, [sp, xzr]  // 10100001-00111111-10011111-11110011
+// CHECK-INST: st1b    { z19.b, z23.b, z27.b, z31.b }, pn15, [sp, xzr]
+// CHECK-ENCODING: [0xf3,0x9f,0x3f,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a13f9ff3 <unknown>
+
+
+st1b    {z0.b, z4.b, z8.b, z12.b}, pn8, [x0]  // 10100001-01100000-10000000-00000000
+// CHECK-INST: st1b    { z0.b, z4.b, z8.b, z12.b }, pn8, [x0]
+// CHECK-ENCODING: [0x00,0x80,0x60,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a1608000 <unknown>
+
+st1b    {z17.b, z21.b, z25.b, z29.b}, pn13, [x10, #20, mul vl]  // 10100001-01100101-10010101-01010001
+// CHECK-INST: st1b    { z17.b, z21.b, z25.b, z29.b }, pn13, [x10, #20, mul vl]
+// CHECK-ENCODING: [0x51,0x95,0x65,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a1659551 <unknown>
+
+st1b    {z19.b, z23.b, z27.b, z31.b}, pn11, [x13, #-32, mul vl]  // 10100001-01101000-10001101-10110011
+// CHECK-INST: st1b    { z19.b, z23.b, z27.b, z31.b }, pn11, [x13, #-32, mul vl]
+// CHECK-ENCODING: [0xb3,0x8d,0x68,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a1688db3 <unknown>
+
+st1b    {z19.b, z23.b, z27.b, z31.b}, pn15, [sp, #-4, mul vl]  // 10100001-01101111-10011111-11110011
+// CHECK-INST: st1b    { z19.b, z23.b, z27.b, z31.b }, pn15, [sp, #-4, mul vl]
+// CHECK-ENCODING: [0xf3,0x9f,0x6f,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a16f9ff3 <unknown>
+

llvm/test/MC/AArch64/SME2/st1b.s

+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
+// RUN:        | llvm-objdump -d --mattr=+sme2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
+// RUN:        | sed '/.text/d' | sed 's/.*encoding: //g' \
+// RUN:        | llvm-mc -triple=aarch64 -mattr=+sme2 -disassemble -show-encoding \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+
+
+st1b    {z0.b, z8.b}, pn8, [x0, x0]  // 10100001-00100000-00000000-00000000
+// CHECK-INST: st1b    { z0.b, z8.b }, pn8, [x0, x0]
+// CHECK-ENCODING: [0x00,0x00,0x20,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a1200000 <unknown>
+
+st1b    {z21.b, z29.b}, pn13, [x10, x21]  // 10100001-00110101-00010101-01010101
+// CHECK-INST: st1b    { z21.b, z29.b }, pn13, [x10, x21]
+// CHECK-ENCODING: [0x55,0x15,0x35,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a1351555 <unknown>
+
+st1b    {z23.b, z31.b}, pn11, [x13, x8]  // 10100001-00101000-00001101-10110111
+// CHECK-INST: st1b    { z23.b, z31.b }, pn11, [x13, x8]
+// CHECK-ENCODING: [0xb7,0x0d,0x28,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a1280db7 <unknown>
+
+st1b    {z23.b, z31.b}, pn15, [sp, xzr]  // 10100001-00111111-00011111-11110111
+// CHECK-INST: st1b    { z23.b, z31.b }, pn15, [sp, xzr]
+// CHECK-ENCODING: [0xf7,0x1f,0x3f,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a13f1ff7 <unknown>
+
+
+st1b    {z0.b, z8.b}, pn8, [x0]  // 10100001-01100000-00000000-00000000
+// CHECK-INST: st1b    { z0.b, z8.b }, pn8, [x0]
+// CHECK-ENCODING: [0x00,0x00,0x60,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a1600000 <unknown>
+
+st1b    {z21.b, z29.b}, pn13, [x10, #10, mul vl]  // 10100001-01100101-00010101-01010101
+// CHECK-INST: st1b    { z21.b, z29.b }, pn13, [x10, #10, mul vl]
+// CHECK-ENCODING: [0x55,0x15,0x65,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a1651555 <unknown>
+
+st1b    {z23.b, z31.b}, pn11, [x13, #-16, mul vl]  // 10100001-01101000-00001101-10110111
+// CHECK-INST: st1b    { z23.b, z31.b }, pn11, [x13, #-16, mul vl]
+// CHECK-ENCODING: [0xb7,0x0d,0x68,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a1680db7 <unknown>
+
+st1b    {z23.b, z31.b}, pn15, [sp, #-2, mul vl]  // 10100001-01101111-00011111-11110111
+// CHECK-INST: st1b    { z23.b, z31.b }, pn15, [sp, #-2, mul vl]
+// CHECK-ENCODING: [0xf7,0x1f,0x6f,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a16f1ff7 <unknown>
+
+
+st1b    {z0.b, z4.b, z8.b, z12.b}, pn8, [x0, x0]  // 10100001-00100000-10000000-00000000
+// CHECK-INST: st1b    { z0.b, z4.b, z8.b, z12.b }, pn8, [x0, x0]
+// CHECK-ENCODING: [0x00,0x80,0x20,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a1208000 <unknown>
+
+st1b    {z17.b, z21.b, z25.b, z29.b}, pn13, [x10, x21]  // 10100001-00110101-10010101-01010001
+// CHECK-INST: st1b    { z17.b, z21.b, z25.b, z29.b }, pn13, [x10, x21]
+// CHECK-ENCODING: [0x51,0x95,0x35,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a1359551 <unknown>
+
+st1b    {z19.b, z23.b, z27.b, z31.b}, pn11, [x13, x8]  // 10100001-00101000-10001101-10110011
+// CHECK-INST: st1b    { z19.b, z23.b, z27.b, z31.b }, pn11, [x13, x8]
+// CHECK-ENCODING: [0xb3,0x8d,0x28,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a1288db3 <unknown>
+
+st1b    {z19.b, z23.b, z27.b, z31.b}, pn15, [sp, xzr]  // 10100001-00111111-10011111-11110011
+// CHECK-INST: st1b    { z19.b, z23.b, z27.b, z31.b }, pn15, [sp, xzr]
+// CHECK-ENCODING: [0xf3,0x9f,0x3f,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a13f9ff3 <unknown>
+
+
+st1b    {z0.b, z4.b, z8.b, z12.b}, pn8, [x0]  // 10100001-01100000-10000000-00000000
+// CHECK-INST: st1b    { z0.b, z4.b, z8.b, z12.b }, pn8, [x0]
+// CHECK-ENCODING: [0x00,0x80,0x60,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a1608000 <unknown>
+
+st1b    {z17.b, z21.b, z25.b, z29.b}, pn13, [x10, #20, mul vl]  // 10100001-01100101-10010101-01010001
+// CHECK-INST: st1b    { z17.b, z21.b, z25.b, z29.b }, pn13, [x10, #20, mul vl]
+// CHECK-ENCODING: [0x51,0x95,0x65,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a1659551 <unknown>
+
+st1b    {z19.b, z23.b, z27.b, z31.b}, pn11, [x13, #-32, mul vl]  // 10100001-01101000-10001101-10110011
+// CHECK-INST: st1b    { z19.b, z23.b, z27.b, z31.b }, pn11, [x13, #-32, mul vl]
+// CHECK-ENCODING: [0xb3,0x8d,0x68,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a1688db3 <unknown>
+
+st1b    {z19.b, z23.b, z27.b, z31.b}, pn15, [sp, #-4, mul vl]  // 10100001-01101111-10011111-11110011
+// CHECK-INST: st1b    { z19.b, z23.b, z27.b, z31.b }, pn15, [sp, #-4, mul vl]
+// CHECK-ENCODING: [0xf3,0x9f,0x6f,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a16f9ff3 <unknown>
+

llvm/test/MC/AArch64/SME2/st1d.s

+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
+// RUN:        | llvm-objdump -d --mattr=+sme2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
+// RUN:        | sed '/.text/d' | sed 's/.*encoding: //g' \
+// RUN:        | llvm-mc -triple=aarch64 -mattr=+sme2 -disassemble -show-encoding \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+
+
+st1d    {z0.d, z8.d}, pn8, [x0, x0, lsl #3]  // 10100001-00100000-01100000-00000000
+// CHECK-INST: st1d    { z0.d, z8.d }, pn8, [x0, x0, lsl #3]
+// CHECK-ENCODING: [0x00,0x60,0x20,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a1206000 <unknown>
+
+st1d    {z21.d, z29.d}, pn13, [x10, x21, lsl #3]  // 10100001-00110101-01110101-01010101
+// CHECK-INST: st1d    { z21.d, z29.d }, pn13, [x10, x21, lsl #3]
+// CHECK-ENCODING: [0x55,0x75,0x35,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a1357555 <unknown>
+
+st1d    {z23.d, z31.d}, pn11, [x13, x8, lsl #3]  // 10100001-00101000-01101101-10110111
+// CHECK-INST: st1d    { z23.d, z31.d }, pn11, [x13, x8, lsl #3]
+// CHECK-ENCODING: [0xb7,0x6d,0x28,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a1286db7 <unknown>
+
+st1d    {z23.d, z31.d}, pn15, [sp, xzr, lsl #3]  // 10100001-00111111-01111111-11110111
+// CHECK-INST: st1d    { z23.d, z31.d }, pn15, [sp, xzr, lsl #3]
+// CHECK-ENCODING: [0xf7,0x7f,0x3f,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a13f7ff7 <unknown>
+
+
+st1d    {z0.d, z8.d}, pn8, [x0]  // 10100001-01100000-01100000-00000000
+// CHECK-INST: st1d    { z0.d, z8.d }, pn8, [x0]
+// CHECK-ENCODING: [0x00,0x60,0x60,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a1606000 <unknown>
+
+st1d    {z21.d, z29.d}, pn13, [x10, #10, mul vl]  // 10100001-01100101-01110101-01010101
+// CHECK-INST: st1d    { z21.d, z29.d }, pn13, [x10, #10, mul vl]
+// CHECK-ENCODING: [0x55,0x75,0x65,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a1657555 <unknown>
+
+st1d    {z23.d, z31.d}, pn11, [x13, #-16, mul vl]  // 10100001-01101000-01101101-10110111
+// CHECK-INST: st1d    { z23.d, z31.d }, pn11, [x13, #-16, mul vl]
+// CHECK-ENCODING: [0xb7,0x6d,0x68,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a1686db7 <unknown>
+
+st1d    {z23.d, z31.d}, pn15, [sp, #-2, mul vl]  // 10100001-01101111-01111111-11110111
+// CHECK-INST: st1d    { z23.d, z31.d }, pn15, [sp, #-2, mul vl]
+// CHECK-ENCODING: [0xf7,0x7f,0x6f,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a16f7ff7 <unknown>
+
+
+st1d    {z0.d, z4.d, z8.d, z12.d}, pn8, [x0, x0, lsl #3]  // 10100001-00100000-11100000-00000000
+// CHECK-INST: st1d    { z0.d, z4.d, z8.d, z12.d }, pn8, [x0, x0, lsl #3]
+// CHECK-ENCODING: [0x00,0xe0,0x20,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a120e000 <unknown>
+
+st1d    {z17.d, z21.d, z25.d, z29.d}, pn13, [x10, x21, lsl #3]  // 10100001-00110101-11110101-01010001
+// CHECK-INST: st1d    { z17.d, z21.d, z25.d, z29.d }, pn13, [x10, x21, lsl #3]
+// CHECK-ENCODING: [0x51,0xf5,0x35,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a135f551 <unknown>
+
+st1d    {z19.d, z23.d, z27.d, z31.d}, pn11, [x13, x8, lsl #3]  // 10100001-00101000-11101101-10110011
+// CHECK-INST: st1d    { z19.d, z23.d, z27.d, z31.d }, pn11, [x13, x8, lsl #3]
+// CHECK-ENCODING: [0xb3,0xed,0x28,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a128edb3 <unknown>
+
+st1d    {z19.d, z23.d, z27.d, z31.d}, pn15, [sp, xzr, lsl #3]  // 10100001-00111111-11111111-11110011
+// CHECK-INST: st1d    { z19.d, z23.d, z27.d, z31.d }, pn15, [sp, xzr, lsl #3]
+// CHECK-ENCODING: [0xf3,0xff,0x3f,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a13ffff3 <unknown>
+
+
+st1d    {z0.d, z4.d, z8.d, z12.d}, pn8, [x0]  // 10100001-01100000-11100000-00000000
+// CHECK-INST: st1d    { z0.d, z4.d, z8.d, z12.d }, pn8, [x0]
+// CHECK-ENCODING: [0x00,0xe0,0x60,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a160e000 <unknown>
+
+st1d    {z17.d, z21.d, z25.d, z29.d}, pn13, [x10, #20, mul vl]  // 10100001-01100101-11110101-01010001
+// CHECK-INST: st1d    { z17.d, z21.d, z25.d, z29.d }, pn13, [x10, #20, mul vl]
+// CHECK-ENCODING: [0x51,0xf5,0x65,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a165f551 <unknown>
+
+st1d    {z19.d, z23.d, z27.d, z31.d}, pn11, [x13, #-32, mul vl]  // 10100001-01101000-11101101-10110011
+// CHECK-INST: st1d    { z19.d, z23.d, z27.d, z31.d }, pn11, [x13, #-32, mul vl]
+// CHECK-ENCODING: [0xb3,0xed,0x68,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a168edb3 <unknown>
+
+st1d    {z19.d, z23.d, z27.d, z31.d}, pn15, [sp, #-4, mul vl]  // 10100001-01101111-11111111-11110011
+// CHECK-INST: st1d    { z19.d, z23.d, z27.d, z31.d }, pn15, [sp, #-4, mul vl]
+// CHECK-ENCODING: [0xf3,0xff,0x6f,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a16ffff3 <unknown>
+

llvm/test/MC/AArch64/SME2/st1h.s

+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
+// RUN:        | llvm-objdump -d --mattr=+sme2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
+// RUN:        | sed '/.text/d' | sed 's/.*encoding: //g' \
+// RUN:        | llvm-mc -triple=aarch64 -mattr=+sme2 -disassemble -show-encoding \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+
+
+st1h    {z0.h, z8.h}, pn8, [x0, x0, lsl #1]  // 10100001-00100000-00100000-00000000
+// CHECK-INST: st1h    { z0.h, z8.h }, pn8, [x0, x0, lsl #1]
+// CHECK-ENCODING: [0x00,0x20,0x20,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a1202000 <unknown>
+
+st1h    {z21.h, z29.h}, pn13, [x10, x21, lsl #1]  // 10100001-00110101-00110101-01010101
+// CHECK-INST: st1h    { z21.h, z29.h }, pn13, [x10, x21, lsl #1]
+// CHECK-ENCODING: [0x55,0x35,0x35,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a1353555 <unknown>
+
+st1h    {z23.h, z31.h}, pn11, [x13, x8, lsl #1]  // 10100001-00101000-00101101-10110111
+// CHECK-INST: st1h    { z23.h, z31.h }, pn11, [x13, x8, lsl #1]
+// CHECK-ENCODING: [0xb7,0x2d,0x28,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a1282db7 <unknown>
+
+st1h    {z23.h, z31.h}, pn15, [sp, xzr, lsl #1]  // 10100001-00111111-00111111-11110111
+// CHECK-INST: st1h    { z23.h, z31.h }, pn15, [sp, xzr, lsl #1]
+// CHECK-ENCODING: [0xf7,0x3f,0x3f,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a13f3ff7 <unknown>
+
+
+st1h    {z0.h, z8.h}, pn8, [x0]  // 10100001-01100000-00100000-00000000
+// CHECK-INST: st1h    { z0.h, z8.h }, pn8, [x0]
+// CHECK-ENCODING: [0x00,0x20,0x60,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a1602000 <unknown>
+
+st1h    {z21.h, z29.h}, pn13, [x10, #10, mul vl]  // 10100001-01100101-00110101-01010101
+// CHECK-INST: st1h    { z21.h, z29.h }, pn13, [x10, #10, mul vl]
+// CHECK-ENCODING: [0x55,0x35,0x65,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a1653555 <unknown>
+
+st1h    {z23.h, z31.h}, pn11, [x13, #-16, mul vl]  // 10100001-01101000-00101101-10110111
+// CHECK-INST: st1h    { z23.h, z31.h }, pn11, [x13, #-16, mul vl]
+// CHECK-ENCODING: [0xb7,0x2d,0x68,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a1682db7 <unknown>
+
+st1h    {z23.h, z31.h}, pn15, [sp, #-2, mul vl]  // 10100001-01101111-00111111-11110111
+// CHECK-INST: st1h    { z23.h, z31.h }, pn15, [sp, #-2, mul vl]
+// CHECK-ENCODING: [0xf7,0x3f,0x6f,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a16f3ff7 <unknown>
+
+
+st1h    {z0.h, z4.h, z8.h, z12.h}, pn8, [x0, x0, lsl #1]  // 10100001-00100000-10100000-00000000
+// CHECK-INST: st1h    { z0.h, z4.h, z8.h, z12.h }, pn8, [x0, x0, lsl #1]
+// CHECK-ENCODING: [0x00,0xa0,0x20,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a120a000 <unknown>
+
+st1h    {z17.h, z21.h, z25.h, z29.h}, pn13, [x10, x21, lsl #1]  // 10100001-00110101-10110101-01010001
+// CHECK-INST: st1h    { z17.h, z21.h, z25.h, z29.h }, pn13, [x10, x21, lsl #1]
+// CHECK-ENCODING: [0x51,0xb5,0x35,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a135b551 <unknown>
+
+st1h    {z19.h, z23.h, z27.h, z31.h}, pn11, [x13, x8, lsl #1]  // 10100001-00101000-10101101-10110011
+// CHECK-INST: st1h    { z19.h, z23.h, z27.h, z31.h }, pn11, [x13, x8, lsl #1]
+// CHECK-ENCODING: [0xb3,0xad,0x28,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a128adb3 <unknown>
+
+st1h    {z19.h, z23.h, z27.h, z31.h}, pn15, [sp, xzr, lsl #1]  // 10100001-00111111-10111111-11110011
+// CHECK-INST: st1h    { z19.h, z23.h, z27.h, z31.h }, pn15, [sp, xzr, lsl #1]
+// CHECK-ENCODING: [0xf3,0xbf,0x3f,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a13fbff3 <unknown>
+
+
+st1h    {z0.h, z4.h, z8.h, z12.h}, pn8, [x0]  // 10100001-01100000-10100000-00000000
+// CHECK-INST: st1h    { z0.h, z4.h, z8.h, z12.h }, pn8, [x0]
+// CHECK-ENCODING: [0x00,0xa0,0x60,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a160a000 <unknown>
+
+st1h    {z17.h, z21.h, z25.h, z29.h}, pn13, [x10, #20, mul vl]  // 10100001-01100101-10110101-01010001
+// CHECK-INST: st1h    { z17.h, z21.h, z25.h, z29.h }, pn13, [x10, #20, mul vl]
+// CHECK-ENCODING: [0x51,0xb5,0x65,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a165b551 <unknown>
+
+st1h    {z19.h, z23.h, z27.h, z31.h}, pn11, [x13, #-32, mul vl]  // 10100001-01101000-10101101-10110011
+// CHECK-INST: st1h    { z19.h, z23.h, z27.h, z31.h }, pn11, [x13, #-32, mul vl]
+// CHECK-ENCODING: [0xb3,0xad,0x68,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a168adb3 <unknown>
+
+st1h    {z19.h, z23.h, z27.h, z31.h}, pn15, [sp, #-4, mul vl]  // 10100001-01101111-10111111-11110011
+// CHECK-INST: st1h    { z19.h, z23.h, z27.h, z31.h }, pn15, [sp, #-4, mul vl]
+// CHECK-ENCODING: [0xf3,0xbf,0x6f,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a16fbff3 <unknown>
+

llvm/test/MC/AArch64/SME2/st1w.s

+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
+// RUN:        | llvm-objdump -d --mattr=+sme2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
+// RUN:        | sed '/.text/d' | sed 's/.*encoding: //g' \
+// RUN:        | llvm-mc -triple=aarch64 -mattr=+sme2 -disassemble -show-encoding \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+
+
+st1w    {z0.s, z8.s}, pn8, [x0, x0, lsl #2]  // 10100001-00100000-01000000-00000000
+// CHECK-INST: st1w    { z0.s, z8.s }, pn8, [x0, x0, lsl #2]
+// CHECK-ENCODING: [0x00,0x40,0x20,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a1204000 <unknown>
+
+st1w    {z21.s, z29.s}, pn13, [x10, x21, lsl #2]  // 10100001-00110101-01010101-01010101
+// CHECK-INST: st1w    { z21.s, z29.s }, pn13, [x10, x21, lsl #2]
+// CHECK-ENCODING: [0x55,0x55,0x35,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a1355555 <unknown>
+
+st1w    {z23.s, z31.s}, pn11, [x13, x8, lsl #2]  // 10100001-00101000-01001101-10110111
+// CHECK-INST: st1w    { z23.s, z31.s }, pn11, [x13, x8, lsl #2]
+// CHECK-ENCODING: [0xb7,0x4d,0x28,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a1284db7 <unknown>
+
+st1w    {z23.s, z31.s}, pn15, [sp, xzr, lsl #2]  // 10100001-00111111-01011111-11110111
+// CHECK-INST: st1w    { z23.s, z31.s }, pn15, [sp, xzr, lsl #2]
+// CHECK-ENCODING: [0xf7,0x5f,0x3f,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a13f5ff7 <unknown>
+
+
+st1w    {z0.s, z8.s}, pn8, [x0]  // 10100001-01100000-01000000-00000000
+// CHECK-INST: st1w    { z0.s, z8.s }, pn8, [x0]
+// CHECK-ENCODING: [0x00,0x40,0x60,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a1604000 <unknown>
+
+st1w    {z21.s, z29.s}, pn13, [x10, #10, mul vl]  // 10100001-01100101-01010101-01010101
+// CHECK-INST: st1w    { z21.s, z29.s }, pn13, [x10, #10, mul vl]
+// CHECK-ENCODING: [0x55,0x55,0x65,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a1655555 <unknown>
+
+st1w    {z23.s, z31.s}, pn11, [x13, #-16, mul vl]  // 10100001-01101000-01001101-10110111
+// CHECK-INST: st1w    { z23.s, z31.s }, pn11, [x13, #-16, mul vl]
+// CHECK-ENCODING: [0xb7,0x4d,0x68,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a1684db7 <unknown>
+
+st1w    {z23.s, z31.s}, pn15, [sp, #-2, mul vl]  // 10100001-01101111-01011111-11110111
+// CHECK-INST: st1w    { z23.s, z31.s }, pn15, [sp, #-2, mul vl]
+// CHECK-ENCODING: [0xf7,0x5f,0x6f,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a16f5ff7 <unknown>
+
+
+st1w    {z0.s, z4.s, z8.s, z12.s}, pn8, [x0, x0, lsl #2]  // 10100001-00100000-11000000-00000000
+// CHECK-INST: st1w    { z0.s, z4.s, z8.s, z12.s }, pn8, [x0, x0, lsl #2]
+// CHECK-ENCODING: [0x00,0xc0,0x20,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a120c000 <unknown>
+
+st1w    {z17.s, z21.s, z25.s, z29.s}, pn13, [x10, x21, lsl #2]  // 10100001-00110101-11010101-01010001
+// CHECK-INST: st1w    { z17.s, z21.s, z25.s, z29.s }, pn13, [x10, x21, lsl #2]
+// CHECK-ENCODING: [0x51,0xd5,0x35,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a135d551 <unknown>
+
+st1w    {z19.s, z23.s, z27.s, z31.s}, pn11, [x13, x8, lsl #2]  // 10100001-00101000-11001101-10110011
+// CHECK-INST: st1w    { z19.s, z23.s, z27.s, z31.s }, pn11, [x13, x8, lsl #2]
+// CHECK-ENCODING: [0xb3,0xcd,0x28,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a128cdb3 <unknown>
+
+st1w    {z19.s, z23.s, z27.s, z31.s}, pn15, [sp, xzr, lsl #2]  // 10100001-00111111-11011111-11110011
+// CHECK-INST: st1w    { z19.s, z23.s, z27.s, z31.s }, pn15, [sp, xzr, lsl #2]
+// CHECK-ENCODING: [0xf3,0xdf,0x3f,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a13fdff3 <unknown>
+
+
+st1w    {z0.s, z4.s, z8.s, z12.s}, pn8, [x0]  // 10100001-01100000-11000000-00000000
+// CHECK-INST: st1w    { z0.s, z4.s, z8.s, z12.s }, pn8, [x0]
+// CHECK-ENCODING: [0x00,0xc0,0x60,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a160c000 <unknown>
+
+st1w    {z17.s, z21.s, z25.s, z29.s}, pn13, [x10, #20, mul vl]  // 10100001-01100101-11010101-01010001
+// CHECK-INST: st1w    { z17.s, z21.s, z25.s, z29.s }, pn13, [x10, #20, mul vl]
+// CHECK-ENCODING: [0x51,0xd5,0x65,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a165d551 <unknown>
+
+st1w    {z19.s, z23.s, z27.s, z31.s}, pn11, [x13, #-32, mul vl]  // 10100001-01101000-11001101-10110011
+// CHECK-INST: st1w    { z19.s, z23.s, z27.s, z31.s }, pn11, [x13, #-32, mul vl]
+// CHECK-ENCODING: [0xb3,0xcd,0x68,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a168cdb3 <unknown>
+
+st1w    {z19.s, z23.s, z27.s, z31.s}, pn15, [sp, #-4, mul vl]  // 10100001-01101111-11011111-11110011
+// CHECK-INST: st1w    { z19.s, z23.s, z27.s, z31.s }, pn15, [sp, #-4, mul vl]
+// CHECK-ENCODING: [0xf3,0xdf,0x6f,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a16fdff3 <unknown>
+

llvm/test/MC/AArch64/SME2/stnt1b.s

+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
+// RUN:        | llvm-objdump -d --mattr=+sme2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
+// RUN:        | sed '/.text/d' | sed 's/.*encoding: //g' \
+// RUN:        | llvm-mc -triple=aarch64 -mattr=+sme2 -disassemble -show-encoding \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+
+
+stnt1b  {z0.b, z8.b}, pn8, [x0, x0]  // 10100001-00100000-00000000-00001000
+// CHECK-INST: stnt1b  { z0.b, z8.b }, pn8, [x0, x0]
+// CHECK-ENCODING: [0x08,0x00,0x20,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a1200008 <unknown>
+
+stnt1b  {z21.b, z29.b}, pn13, [x10, x21]  // 10100001-00110101-00010101-01011101
+// CHECK-INST: stnt1b  { z21.b, z29.b }, pn13, [x10, x21]
+// CHECK-ENCODING: [0x5d,0x15,0x35,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a135155d <unknown>
+
+stnt1b  {z23.b, z31.b}, pn11, [x13, x8]  // 10100001-00101000-00001101-10111111
+// CHECK-INST: stnt1b  { z23.b, z31.b }, pn11, [x13, x8]
+// CHECK-ENCODING: [0xbf,0x0d,0x28,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a1280dbf <unknown>
+
+stnt1b  {z23.b, z31.b}, pn15, [sp, xzr]  // 10100001-00111111-00011111-11111111
+// CHECK-INST: stnt1b  { z23.b, z31.b }, pn15, [sp, xzr]
+// CHECK-ENCODING: [0xff,0x1f,0x3f,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a13f1fff <unknown>
+
+
+stnt1b  {z0.b, z8.b}, pn8, [x0]  // 10100001-01100000-00000000-00001000
+// CHECK-INST: stnt1b  { z0.b, z8.b }, pn8, [x0]
+// CHECK-ENCODING: [0x08,0x00,0x60,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a1600008 <unknown>
+
+stnt1b  {z21.b, z29.b}, pn13, [x10, #10, mul vl]  // 10100001-01100101-00010101-01011101
+// CHECK-INST: stnt1b  { z21.b, z29.b }, pn13, [x10, #10, mul vl]
+// CHECK-ENCODING: [0x5d,0x15,0x65,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a165155d <unknown>
+
+stnt1b  {z23.b, z31.b}, pn11, [x13, #-16, mul vl]  // 10100001-01101000-00001101-10111111
+// CHECK-INST: stnt1b  { z23.b, z31.b }, pn11, [x13, #-16, mul vl]
+// CHECK-ENCODING: [0xbf,0x0d,0x68,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a1680dbf <unknown>
+
+stnt1b  {z23.b, z31.b}, pn15, [sp, #-2, mul vl]  // 10100001-01101111-00011111-11111111
+// CHECK-INST: stnt1b  { z23.b, z31.b }, pn15, [sp, #-2, mul vl]
+// CHECK-ENCODING: [0xff,0x1f,0x6f,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a16f1fff <unknown>
+
+
+stnt1b  {z0.b, z4.b, z8.b, z12.b}, pn8, [x0, x0]  // 10100001-00100000-10000000-00001000
+// CHECK-INST: stnt1b  { z0.b, z4.b, z8.b, z12.b }, pn8, [x0, x0]
+// CHECK-ENCODING: [0x08,0x80,0x20,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a1208008 <unknown>
+
+stnt1b  {z17.b, z21.b, z25.b, z29.b}, pn13, [x10, x21]  // 10100001-00110101-10010101-01011001
+// CHECK-INST: stnt1b  { z17.b, z21.b, z25.b, z29.b }, pn13, [x10, x21]
+// CHECK-ENCODING: [0x59,0x95,0x35,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a1359559 <unknown>
+
+stnt1b  {z19.b, z23.b, z27.b, z31.b}, pn11, [x13, x8]  // 10100001-00101000-10001101-10111011
+// CHECK-INST: stnt1b  { z19.b, z23.b, z27.b, z31.b }, pn11, [x13, x8]
+// CHECK-ENCODING: [0xbb,0x8d,0x28,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a1288dbb <unknown>
+
+stnt1b  {z19.b, z23.b, z27.b, z31.b}, pn15, [sp, xzr]  // 10100001-00111111-10011111-11111011
+// CHECK-INST: stnt1b  { z19.b, z23.b, z27.b, z31.b }, pn15, [sp, xzr]
+// CHECK-ENCODING: [0xfb,0x9f,0x3f,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a13f9ffb <unknown>
+
+
+stnt1b  {z0.b, z4.b, z8.b, z12.b}, pn8, [x0]  // 10100001-01100000-10000000-00001000
+// CHECK-INST: stnt1b  { z0.b, z4.b, z8.b, z12.b }, pn8, [x0]
+// CHECK-ENCODING: [0x08,0x80,0x60,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a1608008 <unknown>
+
+stnt1b  {z17.b, z21.b, z25.b, z29.b}, pn13, [x10, #20, mul vl]  // 10100001-01100101-10010101-01011001
+// CHECK-INST: stnt1b  { z17.b, z21.b, z25.b, z29.b }, pn13, [x10, #20, mul vl]
+// CHECK-ENCODING: [0x59,0x95,0x65,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a1659559 <unknown>
+
+stnt1b  {z19.b, z23.b, z27.b, z31.b}, pn11, [x13, #-32, mul vl]  // 10100001-01101000-10001101-10111011
+// CHECK-INST: stnt1b  { z19.b, z23.b, z27.b, z31.b }, pn11, [x13, #-32, mul vl]
+// CHECK-ENCODING: [0xbb,0x8d,0x68,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a1688dbb <unknown>
+
+stnt1b  {z19.b, z23.b, z27.b, z31.b}, pn15, [sp, #-4, mul vl]  // 10100001-01101111-10011111-11111011
+// CHECK-INST: stnt1b  { z19.b, z23.b, z27.b, z31.b }, pn15, [sp, #-4, mul vl]
+// CHECK-ENCODING: [0xfb,0x9f,0x6f,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a16f9ffb <unknown>
+

llvm/test/MC/AArch64/SME2/stnt1d.s

+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
+// RUN:        | llvm-objdump -d --mattr=+sme2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
+// RUN:        | sed '/.text/d' | sed 's/.*encoding: //g' \
+// RUN:        | llvm-mc -triple=aarch64 -mattr=+sme2 -disassemble -show-encoding \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+
+
+stnt1d  {z0.d, z8.d}, pn8, [x0, x0, lsl #3]  // 10100001-00100000-01100000-00001000
+// CHECK-INST: stnt1d  { z0.d, z8.d }, pn8, [x0, x0, lsl #3]
+// CHECK-ENCODING: [0x08,0x60,0x20,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a1206008 <unknown>
+
+stnt1d  {z21.d, z29.d}, pn13, [x10, x21, lsl #3]  // 10100001-00110101-01110101-01011101
+// CHECK-INST: stnt1d  { z21.d, z29.d }, pn13, [x10, x21, lsl #3]
+// CHECK-ENCODING: [0x5d,0x75,0x35,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a135755d <unknown>
+
+stnt1d  {z23.d, z31.d}, pn11, [x13, x8, lsl #3]  // 10100001-00101000-01101101-10111111
+// CHECK-INST: stnt1d  { z23.d, z31.d }, pn11, [x13, x8, lsl #3]
+// CHECK-ENCODING: [0xbf,0x6d,0x28,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a1286dbf <unknown>
+
+stnt1d  {z23.d, z31.d}, pn15, [sp, xzr, lsl #3]  // 10100001-00111111-01111111-11111111
+// CHECK-INST: stnt1d  { z23.d, z31.d }, pn15, [sp, xzr, lsl #3]
+// CHECK-ENCODING: [0xff,0x7f,0x3f,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a13f7fff <unknown>
+
+
+stnt1d  {z0.d, z8.d}, pn8, [x0]  // 10100001-01100000-01100000-00001000
+// CHECK-INST: stnt1d  { z0.d, z8.d }, pn8, [x0]
+// CHECK-ENCODING: [0x08,0x60,0x60,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a1606008 <unknown>
+
+stnt1d  {z21.d, z29.d}, pn13, [x10, #10, mul vl]  // 10100001-01100101-01110101-01011101
+// CHECK-INST: stnt1d  { z21.d, z29.d }, pn13, [x10, #10, mul vl]
+// CHECK-ENCODING: [0x5d,0x75,0x65,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a165755d <unknown>
+
+stnt1d  {z23.d, z31.d}, pn11, [x13, #-16, mul vl]  // 10100001-01101000-01101101-10111111
+// CHECK-INST: stnt1d  { z23.d, z31.d }, pn11, [x13, #-16, mul vl]
+// CHECK-ENCODING: [0xbf,0x6d,0x68,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a1686dbf <unknown>
+
+stnt1d  {z23.d, z31.d}, pn15, [sp, #-2, mul vl]  // 10100001-01101111-01111111-11111111
+// CHECK-INST: stnt1d  { z23.d, z31.d }, pn15, [sp, #-2, mul vl]
+// CHECK-ENCODING: [0xff,0x7f,0x6f,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a16f7fff <unknown>
+
+
+stnt1d  {z0.d, z4.d, z8.d, z12.d}, pn8, [x0, x0, lsl #3]  // 10100001-00100000-11100000-00001000
+// CHECK-INST: stnt1d  { z0.d, z4.d, z8.d, z12.d }, pn8, [x0, x0, lsl #3]
+// CHECK-ENCODING: [0x08,0xe0,0x20,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a120e008 <unknown>
+
+stnt1d  {z17.d, z21.d, z25.d, z29.d}, pn13, [x10, x21, lsl #3]  // 10100001-00110101-11110101-01011001
+// CHECK-INST: stnt1d  { z17.d, z21.d, z25.d, z29.d }, pn13, [x10, x21, lsl #3]
+// CHECK-ENCODING: [0x59,0xf5,0x35,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a135f559 <unknown>
+
+stnt1d  {z19.d, z23.d, z27.d, z31.d}, pn11, [x13, x8, lsl #3]  // 10100001-00101000-11101101-10111011
+// CHECK-INST: stnt1d  { z19.d, z23.d, z27.d, z31.d }, pn11, [x13, x8, lsl #3]
+// CHECK-ENCODING: [0xbb,0xed,0x28,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a128edbb <unknown>
+
+stnt1d  {z19.d, z23.d, z27.d, z31.d}, pn15, [sp, xzr, lsl #3]  // 10100001-00111111-11111111-11111011
+// CHECK-INST: stnt1d  { z19.d, z23.d, z27.d, z31.d }, pn15, [sp, xzr, lsl #3]
+// CHECK-ENCODING: [0xfb,0xff,0x3f,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a13ffffb <unknown>
+
+
+stnt1d  {z0.d, z4.d, z8.d, z12.d}, pn8, [x0]  // 10100001-01100000-11100000-00001000
+// CHECK-INST: stnt1d  { z0.d, z4.d, z8.d, z12.d }, pn8, [x0]
+// CHECK-ENCODING: [0x08,0xe0,0x60,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a160e008 <unknown>
+
+stnt1d  {z17.d, z21.d, z25.d, z29.d}, pn13, [x10, #20, mul vl]  // 10100001-01100101-11110101-01011001
+// CHECK-INST: stnt1d  { z17.d, z21.d, z25.d, z29.d }, pn13, [x10, #20, mul vl]
+// CHECK-ENCODING: [0x59,0xf5,0x65,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a165f559 <unknown>
+
+stnt1d  {z19.d, z23.d, z27.d, z31.d}, pn11, [x13, #-32, mul vl]  // 10100001-01101000-11101101-10111011
+// CHECK-INST: stnt1d  { z19.d, z23.d, z27.d, z31.d }, pn11, [x13, #-32, mul vl]
+// CHECK-ENCODING: [0xbb,0xed,0x68,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a168edbb <unknown>
+
+stnt1d  {z19.d, z23.d, z27.d, z31.d}, pn15, [sp, #-4, mul vl]  // 10100001-01101111-11111111-11111011
+// CHECK-INST: stnt1d  { z19.d, z23.d, z27.d, z31.d }, pn15, [sp, #-4, mul vl]
+// CHECK-ENCODING: [0xfb,0xff,0x6f,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a16ffffb <unknown>
+

llvm/test/MC/AArch64/SME2/stnt1h.s

+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
+// RUN:        | llvm-objdump -d --mattr=+sme2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
+// RUN:        | sed '/.text/d' | sed 's/.*encoding: //g' \
+// RUN:        | llvm-mc -triple=aarch64 -mattr=+sme2 -disassemble -show-encoding \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+
+
+stnt1h  {z0.h, z8.h}, pn8, [x0, x0, lsl #1]  // 10100001-00100000-00100000-00001000
+// CHECK-INST: stnt1h  { z0.h, z8.h }, pn8, [x0, x0, lsl #1]
+// CHECK-ENCODING: [0x08,0x20,0x20,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a1202008 <unknown>
+
+stnt1h  {z21.h, z29.h}, pn13, [x10, x21, lsl #1]  // 10100001-00110101-00110101-01011101
+// CHECK-INST: stnt1h  { z21.h, z29.h }, pn13, [x10, x21, lsl #1]
+// CHECK-ENCODING: [0x5d,0x35,0x35,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a135355d <unknown>
+
+stnt1h  {z23.h, z31.h}, pn11, [x13, x8, lsl #1]  // 10100001-00101000-00101101-10111111
+// CHECK-INST: stnt1h  { z23.h, z31.h }, pn11, [x13, x8, lsl #1]
+// CHECK-ENCODING: [0xbf,0x2d,0x28,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a1282dbf <unknown>
+
+stnt1h  {z23.h, z31.h}, pn15, [sp, xzr, lsl #1]  // 10100001-00111111-00111111-11111111
+// CHECK-INST: stnt1h  { z23.h, z31.h }, pn15, [sp, xzr, lsl #1]
+// CHECK-ENCODING: [0xff,0x3f,0x3f,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a13f3fff <unknown>
+
+
+stnt1h  {z0.h, z8.h}, pn8, [x0]  // 10100001-01100000-00100000-00001000
+// CHECK-INST: stnt1h  { z0.h, z8.h }, pn8, [x0]
+// CHECK-ENCODING: [0x08,0x20,0x60,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a1602008 <unknown>
+
+stnt1h  {z21.h, z29.h}, pn13, [x10, #10, mul vl]  // 10100001-01100101-00110101-01011101
+// CHECK-INST: stnt1h  { z21.h, z29.h }, pn13, [x10, #10, mul vl]
+// CHECK-ENCODING: [0x5d,0x35,0x65,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a165355d <unknown>
+
+stnt1h  {z23.h, z31.h}, pn11, [x13, #-16, mul vl]  // 10100001-01101000-00101101-10111111
+// CHECK-INST: stnt1h  { z23.h, z31.h }, pn11, [x13, #-16, mul vl]
+// CHECK-ENCODING: [0xbf,0x2d,0x68,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a1682dbf <unknown>
+
+stnt1h  {z23.h, z31.h}, pn15, [sp, #-2, mul vl]  // 10100001-01101111-00111111-11111111
+// CHECK-INST: stnt1h  { z23.h, z31.h }, pn15, [sp, #-2, mul vl]
+// CHECK-ENCODING: [0xff,0x3f,0x6f,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a16f3fff <unknown>
+
+
+stnt1h  {z0.h, z4.h, z8.h, z12.h}, pn8, [x0, x0, lsl #1]  // 10100001-00100000-10100000-00001000
+// CHECK-INST: stnt1h  { z0.h, z4.h, z8.h, z12.h }, pn8, [x0, x0, lsl #1]
+// CHECK-ENCODING: [0x08,0xa0,0x20,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a120a008 <unknown>
+
+stnt1h  {z17.h, z21.h, z25.h, z29.h}, pn13, [x10, x21, lsl #1]  // 10100001-00110101-10110101-01011001
+// CHECK-INST: stnt1h  { z17.h, z21.h, z25.h, z29.h }, pn13, [x10, x21, lsl #1]
+// CHECK-ENCODING: [0x59,0xb5,0x35,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a135b559 <unknown>
+
+stnt1h  {z19.h, z23.h, z27.h, z31.h}, pn11, [x13, x8, lsl #1]  // 10100001-00101000-10101101-10111011
+// CHECK-INST: stnt1h  { z19.h, z23.h, z27.h, z31.h }, pn11, [x13, x8, lsl #1]
+// CHECK-ENCODING: [0xbb,0xad,0x28,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a128adbb <unknown>
+
+stnt1h  {z19.h, z23.h, z27.h, z31.h}, pn15, [sp, xzr, lsl #1]  // 10100001-00111111-10111111-11111011
+// CHECK-INST: stnt1h  { z19.h, z23.h, z27.h, z31.h }, pn15, [sp, xzr, lsl #1]
+// CHECK-ENCODING: [0xfb,0xbf,0x3f,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a13fbffb <unknown>
+
+
+stnt1h  {z0.h, z4.h, z8.h, z12.h}, pn8, [x0]  // 10100001-01100000-10100000-00001000
+// CHECK-INST: stnt1h  { z0.h, z4.h, z8.h, z12.h }, pn8, [x0]
+// CHECK-ENCODING: [0x08,0xa0,0x60,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a160a008 <unknown>
+
+stnt1h  {z17.h, z21.h, z25.h, z29.h}, pn13, [x10, #20, mul vl]  // 10100001-01100101-10110101-01011001
+// CHECK-INST: stnt1h  { z17.h, z21.h, z25.h, z29.h }, pn13, [x10, #20, mul vl]
+// CHECK-ENCODING: [0x59,0xb5,0x65,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a165b559 <unknown>
+
+stnt1h  {z19.h, z23.h, z27.h, z31.h}, pn11, [x13, #-32, mul vl]  // 10100001-01101000-10101101-10111011
+// CHECK-INST: stnt1h  { z19.h, z23.h, z27.h, z31.h }, pn11, [x13, #-32, mul vl]
+// CHECK-ENCODING: [0xbb,0xad,0x68,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a168adbb <unknown>
+
+stnt1h  {z19.h, z23.h, z27.h, z31.h}, pn15, [sp, #-4, mul vl]  // 10100001-01101111-10111111-11111011
+// CHECK-INST: stnt1h  { z19.h, z23.h, z27.h, z31.h }, pn15, [sp, #-4, mul vl]
+// CHECK-ENCODING: [0xfb,0xbf,0x6f,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a16fbffb <unknown>
+

llvm/test/MC/AArch64/SME2/stnt1w.s

+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
+// RUN:        | llvm-objdump -d --mattr=+sme2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
+// RUN:        | sed '/.text/d' | sed 's/.*encoding: //g' \
+// RUN:        | llvm-mc -triple=aarch64 -mattr=+sme2 -disassemble -show-encoding \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+
+
+stnt1w  {z0.s, z8.s}, pn8, [x0, x0, lsl #2]  // 10100001-00100000-01000000-00001000
+// CHECK-INST: stnt1w  { z0.s, z8.s }, pn8, [x0, x0, lsl #2]
+// CHECK-ENCODING: [0x08,0x40,0x20,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a1204008 <unknown>
+
+stnt1w  {z21.s, z29.s}, pn13, [x10, x21, lsl #2]  // 10100001-00110101-01010101-01011101
+// CHECK-INST: stnt1w  { z21.s, z29.s }, pn13, [x10, x21, lsl #2]
+// CHECK-ENCODING: [0x5d,0x55,0x35,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a135555d <unknown>
+
+stnt1w  {z23.s, z31.s}, pn11, [x13, x8, lsl #2]  // 10100001-00101000-01001101-10111111
+// CHECK-INST: stnt1w  { z23.s, z31.s }, pn11, [x13, x8, lsl #2]
+// CHECK-ENCODING: [0xbf,0x4d,0x28,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a1284dbf <unknown>
+
+stnt1w  {z23.s, z31.s}, pn15, [sp, xzr, lsl #2]  // 10100001-00111111-01011111-11111111
+// CHECK-INST: stnt1w  { z23.s, z31.s }, pn15, [sp, xzr, lsl #2]
+// CHECK-ENCODING: [0xff,0x5f,0x3f,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a13f5fff <unknown>
+
+
+stnt1w  {z0.s, z8.s}, pn8, [x0]  // 10100001-01100000-01000000-00001000
+// CHECK-INST: stnt1w  { z0.s, z8.s }, pn8, [x0]
+// CHECK-ENCODING: [0x08,0x40,0x60,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a1604008 <unknown>
+
+stnt1w  {z21.s, z29.s}, pn13, [x10, #10, mul vl]  // 10100001-01100101-01010101-01011101
+// CHECK-INST: stnt1w  { z21.s, z29.s }, pn13, [x10, #10, mul vl]
+// CHECK-ENCODING: [0x5d,0x55,0x65,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a165555d <unknown>
+
+stnt1w  {z23.s, z31.s}, pn11, [x13, #-16, mul vl]  // 10100001-01101000-01001101-10111111
+// CHECK-INST: stnt1w  { z23.s, z31.s }, pn11, [x13, #-16, mul vl]
+// CHECK-ENCODING: [0xbf,0x4d,0x68,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a1684dbf <unknown>
+
+stnt1w  {z23.s, z31.s}, pn15, [sp, #-2, mul vl]  // 10100001-01101111-01011111-11111111
+// CHECK-INST: stnt1w  { z23.s, z31.s }, pn15, [sp, #-2, mul vl]
+// CHECK-ENCODING: [0xff,0x5f,0x6f,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a16f5fff <unknown>
+
+
+stnt1w  {z0.s, z4.s, z8.s, z12.s}, pn8, [x0, x0, lsl #2]  // 10100001-00100000-11000000-00001000
+// CHECK-INST: stnt1w  { z0.s, z4.s, z8.s, z12.s }, pn8, [x0, x0, lsl #2]
+// CHECK-ENCODING: [0x08,0xc0,0x20,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a120c008 <unknown>
+
+stnt1w  {z17.s, z21.s, z25.s, z29.s}, pn13, [x10, x21, lsl #2]  // 10100001-00110101-11010101-01011001
+// CHECK-INST: stnt1w  { z17.s, z21.s, z25.s, z29.s }, pn13, [x10, x21, lsl #2]
+// CHECK-ENCODING: [0x59,0xd5,0x35,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a135d559 <unknown>
+
+stnt1w  {z19.s, z23.s, z27.s, z31.s}, pn11, [x13, x8, lsl #2]  // 10100001-00101000-11001101-10111011
+// CHECK-INST: stnt1w  { z19.s, z23.s, z27.s, z31.s }, pn11, [x13, x8, lsl #2]
+// CHECK-ENCODING: [0xbb,0xcd,0x28,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a128cdbb <unknown>
+
+stnt1w  {z19.s, z23.s, z27.s, z31.s}, pn15, [sp, xzr, lsl #2]  // 10100001-00111111-11011111-11111011
+// CHECK-INST: stnt1w  { z19.s, z23.s, z27.s, z31.s }, pn15, [sp, xzr, lsl #2]
+// CHECK-ENCODING: [0xfb,0xdf,0x3f,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a13fdffb <unknown>
+
+
+stnt1w  {z0.s, z4.s, z8.s, z12.s}, pn8, [x0]  // 10100001-01100000-11000000-00001000
+// CHECK-INST: stnt1w  { z0.s, z4.s, z8.s, z12.s }, pn8, [x0]
+// CHECK-ENCODING: [0x08,0xc0,0x60,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a160c008 <unknown>
+
+stnt1w  {z17.s, z21.s, z25.s, z29.s}, pn13, [x10, #20, mul vl]  // 10100001-01100101-11010101-01011001
+// CHECK-INST: stnt1w  { z17.s, z21.s, z25.s, z29.s }, pn13, [x10, #20, mul vl]
+// CHECK-ENCODING: [0x59,0xd5,0x65,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a165d559 <unknown>
+
+stnt1w  {z19.s, z23.s, z27.s, z31.s}, pn11, [x13, #-32, mul vl]  // 10100001-01101000-11001101-10111011
+// CHECK-INST: stnt1w  { z19.s, z23.s, z27.s, z31.s }, pn11, [x13, #-32, mul vl]
+// CHECK-ENCODING: [0xbb,0xcd,0x68,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a168cdbb <unknown>
+
+stnt1w  {z19.s, z23.s, z27.s, z31.s}, pn15, [sp, #-4, mul vl]  // 10100001-01101111-11011111-11111011
+// CHECK-INST: stnt1w  { z19.s, z23.s, z27.s, z31.s }, pn15, [sp, #-4, mul vl]
+// CHECK-ENCODING: [0xfb,0xdf,0x6f,0xa1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: a16fdffb <unknown>
+

llvm/test/MC/AArch64/SME2/sub-diagnostics.s

 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
 // CHECK-NEXT: za.d[w8, 0, vgx2], {z0.d-z3.d}, z0.d
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 // --------------------------------------------------------------------------//
 // Invalid vector list.
 
 sub za.d[w8, 0], {z0.d,z2.d}, {z0.d,z2.d}
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must be sequential
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
 // CHECK-NEXT: sub za.d[w8, 0], {z0.d,z2.d}, {z0.d,z2.d}
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 sub za.s[w10, 3, vgx2], {z10.s-z11.s}, {z21.s-z22.s}
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors, where the first vector is a multiple of 2 and with matching element types
 // CHECK-NEXT: sub za.s[w10, 3, vgx2], {z10.s-z11.s}, {z21.s-z22.s}
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 

llvm/test/MC/AArch64/SVE/ld2b-diagnostics.s

 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ld2b { z0.b, z1.h }, p0/z, [x0]
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: mismatched register size suffix
 // CHECK-NEXT: ld2b { z0.b, z1.h }, p0/z, [x0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ld2b { z0.b, z2.b }, p0/z, [x0]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must be sequential
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
 // CHECK-NEXT: ld2b { z0.b, z2.b }, p0/z, [x0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ld2b { v0.2d, v1.2d }, p0/z, [x0]
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
 // CHECK-NEXT: ld2b { v0.2d, v1.2d }, p0/z, [x0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 

llvm/test/MC/AArch64/SVE/ld2d-diagnostics.s

 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ld2d { z0.d, z1.b }, p0/z, [x0]
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: mismatched register size suffix
 // CHECK-NEXT: ld2d { z0.d, z1.b }, p0/z, [x0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ld2d { z0.d, z2.d }, p0/z, [x0]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must be sequential
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
 // CHECK-NEXT: ld2d { z0.d, z2.d }, p0/z, [x0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ld2d { v0.2d, v1.2d }, p0/z, [x0]
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
 // CHECK-NEXT: ld2d { v0.2d, v1.2d }, p0/z, [x0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 

llvm/test/MC/AArch64/SVE/ld2h-diagnostics.s

 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ld2h { z0.h, z1.s }, p0/z, [x0]
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: mismatched register size suffix
 // CHECK-NEXT: ld2h { z0.h, z1.s }, p0/z, [x0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ld2h { z0.h, z2.h }, p0/z, [x0]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must be sequential
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
 // CHECK-NEXT: ld2h { z0.h, z2.h }, p0/z, [x0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ld2h { v0.2d, v1.2d }, p0/z, [x0]
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
 // CHECK-NEXT: ld2h { v0.2d, v1.2d }, p0/z, [x0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 

llvm/test/MC/AArch64/SVE/ld2w-diagnostics.s

 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ld2w { z0.s, z1.d }, p0/z, [x0]
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: mismatched register size suffix
 // CHECK-NEXT: ld2w { z0.s, z1.d }, p0/z, [x0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ld2w { z0.s, z2.s }, p0/z, [x0]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must be sequential
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
 // CHECK-NEXT: ld2w { z0.s, z2.s }, p0/z, [x0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ld2w { v0.2d, v1.2d }, p0/z, [x0]
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
 // CHECK-NEXT: ld2w { v0.2d, v1.2d }, p0/z, [x0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 

llvm/test/MC/AArch64/SVE/ld3b-diagnostics.s

 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ld3b { z0.b, z1.b, z2.h }, p0/z, [x0]
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: mismatched register size suffix
 // CHECK-NEXT: ld3b { z0.b, z1.b, z2.h }, p0/z, [x0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ld3b { z0.b, z1.b, z3.b }, p0/z, [x0]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must be sequential
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must have the same sequential stride
 // CHECK-NEXT: ld3b { z0.b, z1.b, z3.b }, p0/z, [x0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ld3b { v0.16b, v1.16b, v2.16b }, p0/z, [x0]
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
 // CHECK-NEXT: ld3b { v0.16b, v1.16b, v2.16b }, p0/z, [x0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 

llvm/test/MC/AArch64/SVE/ld3d-diagnostics.s

 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ld3d { z0.d, z1.d, z2.b }, p0/z, [x0]
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: mismatched register size suffix
 // CHECK-NEXT: ld3d { z0.d, z1.d, z2.b }, p0/z, [x0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ld3d { z0.d, z1.d, z3.d }, p0/z, [x0]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must be sequential
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must have the same sequential stride
 // CHECK-NEXT: ld3d { z0.d, z1.d, z3.d }, p0/z, [x0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ld3d { v0.2d, v1.2d, v2.2d }, p0/z, [x0]
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
 // CHECK-NEXT: ld3d { v0.2d, v1.2d, v2.2d }, p0/z, [x0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 

llvm/test/MC/AArch64/SVE/ld3h-diagnostics.s

 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ld3h { z0.h, z1.h, z2.s }, p0/z, [x0]
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: mismatched register size suffix
 // CHECK-NEXT: ld3h { z0.h, z1.h, z2.s }, p0/z, [x0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ld3h { z0.h, z1.h, z3.h }, p0/z, [x0]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must be sequential
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must have the same sequential stride
 // CHECK-NEXT: ld3h { z0.h, z1.h, z3.h }, p0/z, [x0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ld3h { v0.8h, v1.8h, v2.8h }, p0/z, [x0]
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
 // CHECK-NEXT: ld3h { v0.8h, v1.8h, v2.8h }, p0/z, [x0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 

llvm/test/MC/AArch64/SVE/ld3w-diagnostics.s

 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ld3w { z0.s, z1.s, z2.d }, p0/z, [x0]
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: mismatched register size suffix
 // CHECK-NEXT: ld3w { z0.s, z1.s, z2.d }, p0/z, [x0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ld3w { z0.s, z1.s, z3.s }, p0/z, [x0]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must be sequential
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must have the same sequential stride
 // CHECK-NEXT: ld3w { z0.s, z1.s, z3.s }, p0/z, [x0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ld3w { v0.4s, v1.4s, v2.4s }, p0/z, [x0]
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
 // CHECK-NEXT: ld3w { v0.4s, v1.4s, v2.4s }, p0/z, [x0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 

llvm/test/MC/AArch64/SVE/ld4b-diagnostics.s

 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ld4b { z0.b, z1.b, z2.b, z3.h }, p0/z, [x0]
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: mismatched register size suffix
 // CHECK-NEXT: ld4b { z0.b, z1.b, z2.b, z3.h }, p0/z, [x0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ld4b { z0.b, z1.b, z3.b, z5.b }, p0/z, [x0]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must be sequential
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must have the same sequential stride
 // CHECK-NEXT: ld4b { z0.b, z1.b, z3.b, z5.b }, p0/z, [x0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ld4b { v0.16b, v1.16b, v2.16b }, p0/z, [x0]
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
 // CHECK-NEXT: ld4b { v0.16b, v1.16b, v2.16b }, p0/z, [x0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 

llvm/test/MC/AArch64/SVE/ld4d-diagnostics.s

 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ld4d { z0.d, z1.d, z2.d, z3.b }, p0/z, [x0]
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: mismatched register size suffix
 // CHECK-NEXT: ld4d { z0.d, z1.d, z2.d, z3.b }, p0/z, [x0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ld4d { z0.d, z1.d, z3.d, z5.d }, p0/z, [x0]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must be sequential
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must have the same sequential stride
 // CHECK-NEXT: ld4d { z0.d, z1.d, z3.d, z5.d }, p0/z, [x0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ld4d { v0.2d, v1.2d, v2.2d }, p0/z, [x0]
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
 // CHECK-NEXT: ld4d { v0.2d, v1.2d, v2.2d }, p0/z, [x0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 

llvm/test/MC/AArch64/SVE/ld4h-diagnostics.s

 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ld4h { z0.h, z1.h, z2.h, z3.s }, p0/z, [x0]
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: mismatched register size suffix
 // CHECK-NEXT: ld4h { z0.h, z1.h, z2.h, z3.s }, p0/z, [x0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ld4h { z0.h, z1.h, z3.h, z5.h }, p0/z, [x0]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must be sequential
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must have the same sequential stride
 // CHECK-NEXT: ld4h { z0.h, z1.h, z3.h, z5.h }, p0/z, [x0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ld4h { v0.8h, v1.8h, v2.8h }, p0/z, [x0]
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
 // CHECK-NEXT: ld4h { v0.8h, v1.8h, v2.8h }, p0/z, [x0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 

llvm/test/MC/AArch64/SVE/ld4w-diagnostics.s

 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ld4w { z0.s, z1.s, z2.s, z3.d }, p0/z, [x0]
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: mismatched register size suffix
 // CHECK-NEXT: ld4w { z0.s, z1.s, z2.s, z3.d }, p0/z, [x0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ld4w { z0.s, z1.s, z3.s, z5.s }, p0/z, [x0]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must be sequential
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must have the same sequential stride
 // CHECK-NEXT: ld4w { z0.s, z1.s, z3.s, z5.s }, p0/z, [x0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ld4w { v0.4s, v1.4s, v2.4s }, p0/z, [x0]
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
 // CHECK-NEXT: ld4w { v0.4s, v1.4s, v2.4s }, p0/z, [x0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 

llvm/test/MC/AArch64/SVE/st2b-diagnostics.s

 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 st2b { z0.b, z1.h }, p0, [x0]
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: mismatched register size suffix
 // CHECK-NEXT: st2b { z0.b, z1.h }, p0, [x0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 st2b { z0.b, z2.b }, p0, [x0]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must be sequential
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
 // CHECK-NEXT: st2b { z0.b, z2.b }, p0, [x0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 st2b { v0.2d, v1.2d }, p0, [x0]
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
 // CHECK-NEXT: st2b { v0.2d, v1.2d }, p0, [x0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 

llvm/test/MC/AArch64/SVE/st2d-diagnostics.s

 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 st2d { z0.d, z1.b }, p0, [x0]
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: mismatched register size suffix
 // CHECK-NEXT: st2d { z0.d, z1.b }, p0, [x0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 st2d { z0.d, z2.d }, p0, [x0]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must be sequential
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
 // CHECK-NEXT: st2d { z0.d, z2.d }, p0, [x0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 st2d { v0.2d, v1.2d }, p0, [x0]
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
 // CHECK-NEXT: st2d { v0.2d, v1.2d }, p0, [x0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 

llvm/test/MC/AArch64/SVE/st2h-diagnostics.s

 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 st2h { z0.h, z1.s }, p0, [x0]
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: mismatched register size suffix
 // CHECK-NEXT: st2h { z0.h, z1.s }, p0, [x0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 st2h { z0.h, z2.h }, p0, [x0]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must be sequential
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
 // CHECK-NEXT: st2h { z0.h, z2.h }, p0, [x0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 st2h { v0.2d, v1.2d }, p0, [x0]
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
 // CHECK-NEXT: st2h { v0.2d, v1.2d }, p0, [x0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 

llvm/test/MC/AArch64/SVE/st2w-diagnostics.s

 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 st2w { z0.s, z1.d }, p0, [x0]
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: mismatched register size suffix
 // CHECK-NEXT: st2w { z0.s, z1.d }, p0, [x0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 st2w { z0.s, z2.s }, p0, [x0]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must be sequential
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
 // CHECK-NEXT: st2w { z0.s, z2.s }, p0, [x0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 st2w { v0.2d, v1.2d }, p0, [x0]
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
 // CHECK-NEXT: st2w { v0.2d, v1.2d }, p0, [x0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 

llvm/test/MC/AArch64/SVE/st3b-diagnostics.s

 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 st3b { z0.b, z1.b, z2.h }, p0, [x0]
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: mismatched register size suffix
 // CHECK-NEXT: st3b { z0.b, z1.b, z2.h }, p0, [x0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 st3b { z0.b, z1.b, z3.b }, p0, [x0]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must be sequential
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must have the same sequential stride
 // CHECK-NEXT: st3b { z0.b, z1.b, z3.b }, p0, [x0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 st3b { v0.16b, v1.16b, v2.16b }, p0, [x0]
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
 // CHECK-NEXT: st3b { v0.16b, v1.16b, v2.16b }, p0, [x0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 

llvm/test/MC/AArch64/SVE/st3d-diagnostics.s

 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 st3d { z0.d, z1.d, z2.b }, p0, [x0]
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: mismatched register size suffix
 // CHECK-NEXT: st3d { z0.d, z1.d, z2.b }, p0, [x0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 st3d { z0.d, z1.d, z3.d }, p0, [x0]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must be sequential
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must have the same sequential stride
 // CHECK-NEXT: st3d { z0.d, z1.d, z3.d }, p0, [x0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 st3d { v0.2d, v1.2d, v2.2d }, p0, [x0]
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
 // CHECK-NEXT: st3d { v0.2d, v1.2d, v2.2d }, p0, [x0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 

llvm/test/MC/AArch64/SVE/st3h-diagnostics.s

 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 st3h { z0.h, z1.h, z2.s }, p0, [x0]
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: mismatched register size suffix
 // CHECK-NEXT: st3h { z0.h, z1.h, z2.s }, p0, [x0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 st3h { z0.h, z1.h, z3.h }, p0, [x0]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must be sequential
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must have the same sequential stride
 // CHECK-NEXT: st3h { z0.h, z1.h, z3.h }, p0, [x0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 st3h { v0.8h, v1.8h, v2.8h }, p0, [x0]
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
 // CHECK-NEXT: st3h { v0.8h, v1.8h, v2.8h }, p0, [x0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 

llvm/test/MC/AArch64/SVE/st3w-diagnostics.s

 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 st3w { z0.s, z1.s, z2.d }, p0, [x0]
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: mismatched register size suffix
 // CHECK-NEXT: st3w { z0.s, z1.s, z2.d }, p0, [x0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 st3w { z0.s, z1.s, z3.s }, p0, [x0]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must be sequential
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must have the same sequential stride
 // CHECK-NEXT: st3w { z0.s, z1.s, z3.s }, p0, [x0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 st3w { v0.4s, v1.4s, v2.4s }, p0, [x0]
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
 // CHECK-NEXT: st3w { v0.4s, v1.4s, v2.4s }, p0, [x0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 

llvm/test/MC/AArch64/SVE/st4b-diagnostics.s

 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 st4b { z0.b, z1.b, z2.b, z3.h }, p0, [x0]
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: mismatched register size suffix
 // CHECK-NEXT: st4b { z0.b, z1.b, z2.b, z3.h }, p0, [x0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 st4b { z0.b, z1.b, z3.b, z5.b }, p0, [x0]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must be sequential
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must have the same sequential stride
 // CHECK-NEXT: st4b { z0.b, z1.b, z3.b, z5.b }, p0, [x0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 st4b { v0.16b, v1.16b, v2.16b }, p0, [x0]
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
 // CHECK-NEXT: st4b { v0.16b, v1.16b, v2.16b }, p0, [x0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 

llvm/test/MC/AArch64/SVE/st4d-diagnostics.s

 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 st4d { z0.d, z1.d, z2.d, z3.b }, p0, [x0]
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: mismatched register size suffix
 // CHECK-NEXT: st4d { z0.d, z1.d, z2.d, z3.b }, p0, [x0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 st4d { z0.d, z1.d, z3.d, z5.d }, p0, [x0]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must be sequential
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must have the same sequential stride
 // CHECK-NEXT: st4d { z0.d, z1.d, z3.d, z5.d }, p0, [x0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 st4d { v0.2d, v1.2d, v2.2d }, p0, [x0]
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
 // CHECK-NEXT: st4d { v0.2d, v1.2d, v2.2d }, p0, [x0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 

llvm/test/MC/AArch64/SVE/st4h-diagnostics.s

 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 st4h { z0.h, z1.h, z2.h, z3.s }, p0, [x0]
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: mismatched register size suffix
 // CHECK-NEXT: st4h { z0.h, z1.h, z2.h, z3.s }, p0, [x0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 st4h { z0.h, z1.h, z3.h, z5.h }, p0, [x0]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must be sequential
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must have the same sequential stride
 // CHECK-NEXT: st4h { z0.h, z1.h, z3.h, z5.h }, p0, [x0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 st4h { v0.8h, v1.8h, v2.8h }, p0, [x0]
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
 // CHECK-NEXT: st4h { v0.8h, v1.8h, v2.8h }, p0, [x0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 

llvm/test/MC/AArch64/SVE/st4w-diagnostics.s

 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 st4w { z0.s, z1.s, z2.s, z3.d }, p0, [x0]
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: mismatched register size suffix
 // CHECK-NEXT: st4w { z0.s, z1.s, z2.s, z3.d }, p0, [x0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 st4w { z0.s, z1.s, z3.s, z5.s }, p0, [x0]
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must be sequential
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must have the same sequential stride
 // CHECK-NEXT: st4w { z0.s, z1.s, z3.s, z5.s }, p0, [x0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 st4w { v0.4s, v1.4s, v2.4s }, p0, [x0]
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand
 // CHECK-NEXT: st4w { v0.4s, v1.4s, v2.4s }, p0, [x0]
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 

llvm/test/MC/AArch64/SVE2/ext-diagnostics.s

 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ext z0.b, { z1.b, z2.h }, #0
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: mismatched register size suffix
 // CHECK-NEXT: ext z0.b, { z1.b, z2.h }, #0
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ext z0.b, { z1.b, z31.b }, #0
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must be sequential
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
 // CHECK-NEXT: ext z0.b, { z1.b, z31.b }, #0
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 ext z0.b, { v0.4b, v1.4b }, #0
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
 // CHECK-NEXT: ext z0.b, { v0.4b, v1.4b }, #0
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 

llvm/test/MC/AArch64/SVE2/splice-diagnostics.s

 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 splice z0.b, p0, { z1.b, z2.h }
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: mismatched register size suffix
 // CHECK-NEXT: splice z0.b, p0, { z1.b, z2.h }
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 splice z0.b, p0, { z1.b, z31.b }
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must be sequential
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
 // CHECK-NEXT: splice z0.b, p0, { z1.b, z31.b }
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 splice z0.b, p0, { v0.4b, v1.4b }
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
 // CHECK-NEXT: splice z0.b, p0, { v0.4b, v1.4b }
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 

llvm/test/MC/AArch64/SVE2/tbl-diagnostics.s

 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 tbl z0.d, { z1.d, z2.b }, z3.d
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: mismatched register size suffix
 // CHECK-NEXT: tbl z0.d, { z1.d, z2.b }, z3.d
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 tbl z0.d, { z1.d, z21.d }, z3.d
-// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must be sequential
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
 // CHECK-NEXT: tbl z0.d, { z1.d, z21.d }, z3.d
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 tbl z0.d, { v0.2d, v1.2d }, z1.d
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
 // CHECK-NEXT: tbl z0.d, { v0.2d, v1.2d }, z1.d
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 

llvm/test/MC/AArch64/neon-diagnostics.s

// CHECK-ERROR:                       ^
 
          ld1 {v0.16b, v2.16b}, [x0]
          ld1 {v0.8h, v1.8h, v2.8h, v3.8h, v4.8h}, [x0]
          ld1 v0.8b, v1.8b}, [x0]
          ld1 {v0.8h-v4.8h}, [x0]
          ld1 {v1.8h-v1.8h}, [x0]
          ld1 {v15.8h-v17.4h}, [x15]
          ld1 {v0.8b-v2.8b, [x0]
-// CHECK-ERROR: error: registers must be sequential
+// CHECK-ERROR: error: invalid operand for instruction
 // CHECK-ERROR:        ld1 {v0.16b, v2.16b}, [x0]
 // CHECK-ERROR:                     ^
 // CHECK-ERROR: error: invalid number of vectors
 // CHECK-ERROR:        ld1 {v0.8h, v1.8h, v2.8h, v3.8h, v4.8h}, [x0]
 // CHECK-ERROR:                                         ^
 // CHECK-ERROR: error: invalid operand for instruction
 // CHECK-ERROR:        ld1 v0.8b, v1.8b}, [x0]
 // CHECK-ERROR:            ^
// CHECK-ERROR:                        ^
          ld2 {v15.8h, v16.4h}, [x15]
          ld2 {v0.8b, v2.8b}, [x0]
          ld2 {v15.4h, v16.4h, v17.4h}, [x32]
          ld2 {v15.8h-v16.4h}, [x15]
          ld2 {v0.2d-v2.2d}, [x0]
 // CHECK-ERROR: error: mismatched register size suffix
 // CHECK-ERROR:        ld2 {v15.8h, v16.4h}, [x15]
 // CHECK-ERROR:                     ^
-// CHECK-ERROR: error: registers must be sequential
+// CHECK-ERROR: error: invalid operand for instruction
 // CHECK-ERROR:        ld2 {v0.8b, v2.8b}, [x0]
 // CHECK-ERROR:                    ^
 // CHECK-ERROR:        ld2 {v15.4h, v16.4h, v17.4h}, [x32]
 // CHECK-ERROR:            ^
 // CHECK-ERROR: error: mismatched register size suffix
 // CHECK-ERROR:        ld2 {v15.8h-v16.4h}, [x15]
 // CHECK-ERROR:                        ^
 // CHECK-ERROR: error: invalid operand for instruction
 // CHECK-ERROR:        ld2 {v0.2d-v2.2d}, [x0]
 // CHECK-ERROR:            ^
 
          ld3 {v15.8h, v16.8h, v17.4h}, [x15]
          ld3 {v0.8b, v1,8b, v2.8b, v3.8b}, [x0]
          ld3 {v0.8b, v2.8b, v3.8b}, [x0]
          ld3 {v15.8h-v17.4h}, [x15]
          ld3 {v31.4s-v2.4s}, [sp]
 // CHECK-ERROR: error: mismatched register size suffix
 // CHECK-ERROR:        ld3 {v15.8h, v16.8h, v17.4h}, [x15]
 // CHECK-ERROR:                             ^
 // CHECK-ERROR: error: mismatched register size suffix
 // CHECK-ERROR:        ld3 {v0.8b, v1,8b, v2.8b, v3.8b}, [x0]
 // CHECK-ERROR:                    ^
-// CHECK-ERROR: error: registers must be sequential
+// CHECK-ERROR: error: registers must have the same sequential stride
 // CHECK-ERROR:        ld3 {v0.8b, v2.8b, v3.8b}, [x0]
 // CHECK-ERROR:                    ^
 // CHECK-ERROR: error: mismatched register size suffix
 // CHECK-ERROR:        ld3 {v15.8h-v17.4h}, [x15]
 // CHECK-ERROR:                        ^
 // CHECK-ERROR: error: invalid operand for instruction
 // CHECK-ERROR:        ld3 {v31.4s-v2.4s}, [sp]
 // CHECK-ERROR:            ^
 
          ld4 {v15.8h, v16.8h, v17.4h, v18.8h}, [x15]
          ld4 {v0.8b, v2.8b, v3.8b, v4.8b}, [x0]
          ld4 {v15.4h, v16.4h, v17.4h, v18.4h, v19.4h}, [x31]
          ld4 {v15.8h-v18.4h}, [x15]
          ld4 {v31.2s-v1.2s}, [x31]
 // CHECK-ERROR: error: mismatched register size suffix
 // CHECK-ERROR:        ld4 {v15.8h, v16.8h, v17.4h, v18.8h}, [x15]
 // CHECK-ERROR:                             ^
-// CHECK-ERROR: error: registers must be sequential
+// CHECK-ERROR: error: registers must have the same sequential stride
 // CHECK-ERROR:        ld4 {v0.8b, v2.8b, v3.8b, v4.8b}, [x0]
 // CHECK-ERROR:                    ^
 // CHECK-ERROR: error: invalid number of vectors
 // CHECK-ERROR:        ld4 {v15.4h, v16.4h, v17.4h, v18.4h, v19.4h}, [x31]
 // CHECK-ERROR:                                             ^
 // CHECK-ERROR: error: mismatched register size suffix
 // CHECK-ERROR:        ld4 {v15.8h-v18.4h}, [x15]
 // CHECK-ERROR:                        ^
// CHECK-ERROR:                       ^
 
          st1 {v0.16b, v2.16b}, [x0]
          st1 {v0.8h, v1.8h, v2.8h, v3.8h, v4.8h}, [x0]
          st1 v0.8b, v1.8b}, [x0]
          st1 {v0.8h-v4.8h}, [x0]
          st1 {v1.8h-v1.8h}, [x0]
          st1 {v15.8h-v17.4h}, [x15]
          st1 {v0.8b-v2.8b, [x0]
-// CHECK-ERROR: error: registers must be sequential
+// CHECK-ERROR: error: invalid operand for instruction
 // CHECK-ERROR:        st1 {v0.16b, v2.16b}, [x0]
 // CHECK-ERROR:                     ^
 // CHECK-ERROR: error: invalid number of vectors
 // CHECK-ERROR:        st1 {v0.8h, v1.8h, v2.8h, v3.8h, v4.8h}, [x0]
 // CHECK-ERROR:                                         ^
 // CHECK-ERROR: error: invalid operand for instruction
 // CHECK-ERROR:        st1 v0.8b, v1.8b}, [x0]
 // CHECK-ERROR:            ^
// CHECK-ERROR:                        ^
          st2 {v15.8h, v16.4h}, [x15]
          st2 {v0.8b, v2.8b}, [x0]
          st2 {v15.4h, v16.4h, v17.4h}, [x30]
          st2 {v15.8h-v16.4h}, [x15]
          st2 {v0.2d-v2.2d}, [x0]
 // CHECK-ERROR: error: mismatched register size suffix
 // CHECK-ERROR:        st2 {v15.8h, v16.4h}, [x15]
 // CHECK-ERROR:                     ^
-// CHECK-ERROR: error: registers must be sequential
+// CHECK-ERROR: error: invalid operand for instruction
 // CHECK-ERROR:        st2 {v0.8b, v2.8b}, [x0]
 // CHECK-ERROR:                    ^
 // CHECK-ERROR: error: invalid operand for instruction
 // CHECK-ERROR:        st2 {v15.4h, v16.4h, v17.4h}, [x30]
 // CHECK-ERROR:            ^
 // CHECK-ERROR: error: mismatched register size suffix
 // CHECK-ERROR:        st2 {v15.8h-v16.4h}, [x15]
 // CHECK-ERROR:                        ^
 // CHECK-ERROR: error: invalid operand for instruction
 // CHECK-ERROR:        st2 {v0.2d-v2.2d}, [x0]
 // CHECK-ERROR:            ^
 
          st3 {v15.8h, v16.8h, v17.4h}, [x15]
          st3 {v0.8b, v1,8b, v2.8b, v3.8b}, [x0]
          st3 {v0.8b, v2.8b, v3.8b}, [x0]
          st3 {v15.8h-v17.4h}, [x15]
          st3 {v31.4s-v2.4s}, [sp]
 // CHECK-ERROR: error: mismatched register size suffix
 // CHECK-ERROR:        st3 {v15.8h, v16.8h, v17.4h}, [x15]
 // CHECK-ERROR:                             ^
 // CHECK-ERROR: error: mismatched register size suffix
 // CHECK-ERROR:        st3 {v0.8b, v1,8b, v2.8b, v3.8b}, [x0]
 // CHECK-ERROR:                    ^
-// CHECK-ERROR: error: registers must be sequential
+// CHECK-ERROR: error: registers must have the same sequential stride
 // CHECK-ERROR:        st3 {v0.8b, v2.8b, v3.8b}, [x0]
 // CHECK-ERROR:                    ^
 // CHECK-ERROR: error: mismatched register size suffix
 // CHECK-ERROR:        st3 {v15.8h-v17.4h}, [x15]
 // CHECK-ERROR:                        ^
 // CHECK-ERROR: error: invalid operand for instruction
 // CHECK-ERROR:        st3 {v31.4s-v2.4s}, [sp]
 // CHECK-ERROR:            ^
 
          st4 {v15.8h, v16.8h, v17.4h, v18.8h}, [x15]
          st4 {v0.8b, v2.8b, v3.8b, v4.8b}, [x0]
          st4 {v15.4h, v16.4h, v17.4h, v18.4h, v19.4h}, [x31]
          st4 {v15.8h-v18.4h}, [x15]
          st4 {v31.2s-v1.2s}, [x31]
 // CHECK-ERROR: error: mismatched register size suffix
 // CHECK-ERROR:        st4 {v15.8h, v16.8h, v17.4h, v18.8h}, [x15]
 // CHECK-ERROR:                             ^
-// CHECK-ERROR: error: registers must be sequential
+// CHECK-ERROR: error: registers must have the same sequential stride
 // CHECK-ERROR:        st4 {v0.8b, v2.8b, v3.8b, v4.8b}, [x0]
 // CHECK-ERROR:                    ^
 // CHECK-ERROR: error: invalid number of vectors
 // CHECK-ERROR:        st4 {v15.4h, v16.4h, v17.4h, v18.4h, v19.4h}, [x31]
 // CHECK-ERROR:                                             ^
 // CHECK-ERROR: error: mismatched register size suffix
 // CHECK-ERROR:        st4 {v15.8h-v18.4h}, [x15]
 // CHECK-ERROR:                        ^