[AArch64]SME2 Multi-single vector SVE Destructive 2 and 4 Registers

[CarolineConcatto]

Summary

This patch adds the assembly/disassembly for the following instructions:

ADD (to vector): Add replicated single vector to multi-vector with multi-vector result.
SQDMULH (multiple and single vector): Multi-vector signed saturating doubling multiply high by vector.

for 2 and 4 ZA SVE registers.

The reference can be found here:

https://developer.arm.com/documentation/ddi0602/2022-09

It also adds more size for the multiple register tuple:

ZZ_b_mul_r,  ZZ_h_mul_r,
ZZZZ_b_mul_r,  ZZZZ_h_mul_r,

for 8 bits and 16 bits with 2 and 4 ZA registers.

Depends on: D135468

[CarolineConcatto]

• Add missing diagnostics for the ZA multiple operands

[CarolineConcatto]

• Rebase

[dmgreen]

llvm/test/MC/AArch64/SME2/add.s

47

Your find-and-replace looks like it went a bit too far :)

[sdesmalen]

llvm/lib/Target/AArch64/AArch64RegisterInfo.td

1100

Using ZPR2 here (and ZPR4 for ZZZZ_b_mul_r) isn't correct.

ZPR2 allows:

{z0.b, z1.b}
{z1.b, z2.b}
{z2.b, z3.b}
{z3.b, z4.b}
...

But {z1.b, z2.b} and {z3.b, z4.b} are not valid for ZZ_b_mul_r, because the first register must be a multiple of 2.

To fix this, you can create a new register class that only takes the "even" pairs (for ZPR2) or every fourth quad (for ZPR4) like this:

// SME2 multiple-of-2 or 4 multi-vector operands
def ZPR2Mul2 : RegisterClass<"AArch64", [untyped], 128, (add (decimate ZSeqPairs, 2))> {
  let Size = 256;
}

def ZPR4Mul4 : RegisterClass<"AArch64", [untyped], 128, (add (decimate ZSeqQuads, 4))> {
  let Size = 512;
}

[david-arm]

llvm/lib/Target/AArch64/AArch64RegisterInfo.td

1100

This makes sense, although the diagnostics tests do show that we correctly reject registers starting at non-multiples I think? Not sure why this works - perhaps the ParserMatchClass takes care of it?

[sdesmalen]

llvm/lib/Target/AArch64/AArch64RegisterInfo.td

1100

That's indeed because of the ParserMatchClass (through the PredicateMethod), which is only relevant to the assembler.

[CarolineConcatto]

-Rebase on top of D135468

[sdesmalen]

LGTM

llvm/test/MC/AArch64/SME2/add.s

1349

nit: redundant newline here and in other places in this file.

llvm/include/llvm/MC/MCParser/MCTargetAsmParser.h

public:
   /// any complex target predicates not expressible via match classes.
   virtual unsigned checkTargetMatchPredicate(MCInst &Inst) {
     return Match_Success;
   }
 
   virtual void convertToMapAndConstraints(unsigned Kind,
                                           const OperandVector &Operands) = 0;
 
-  /// Returns whether two registers are equal and is used by the tied-operands
-  /// checks in the AsmMatcher. This method can be overridden allow e.g. a
-  /// sub- or super-register as the tied operand.
-  virtual bool regsEqual(const MCParsedAsmOperand &Op1,
+  /// Returns whether two operands are registers and are equal. This is used
+  /// by the tied-operands checks in the AsmMatcher. This method can be
+  /// overridden to allow e.g. a sub- or super-register as the tied operand.
+  virtual bool areEqualRegs(const MCParsedAsmOperand &Op1,
                             const MCParsedAsmOperand &Op2) const {
-    assert(Op1.isReg() && Op2.isReg() && "Operands not all regs");
-    return Op1.getReg() == Op2.getReg();
+    return Op1.isReg() && Op2.isReg() && Op1.getReg() == Op2.getReg();
   }
 
   // Return whether this parser uses assignment statements with equals tokens
   virtual bool equalIsAsmAssignment() { return true; };
   // Return whether this start of statement identifier is a label
   virtual bool isLabel(AsmToken &Token) { return true; };
   // Return whether this parser accept star as start of statement
   virtual bool starIsStartOfStatement() { return false; };

llvm/lib/Target/AArch64/AArch64RegisterInfo.td

 def ZPRAsmOp3b8   : ZPRAsmOperand<"Vector3bB", 8, "_3b">;
 def ZPRAsmOp3b16  : ZPRAsmOperand<"Vector3bH", 16, "_3b">;
 def ZPRAsmOp3b32  : ZPRAsmOperand<"Vector3bS", 32, "_3b">;
 
 def ZPR3b8  : ZPRRegOp<"b", ZPRAsmOp3b8,  ElementSizeB, ZPR_3b>;
 def ZPR3b16 : ZPRRegOp<"h", ZPRAsmOp3b16, ElementSizeH, ZPR_3b>;
 def ZPR3b32 : ZPRRegOp<"s", ZPRAsmOp3b32, ElementSizeS, ZPR_3b>;
 
+def ZPRAsmOp4b8   : ZPRAsmOperand<"Vector4bB", 8,  "_4b">;
 def ZPRAsmOp4b16  : ZPRAsmOperand<"Vector4bH", 16, "_4b">;
 def ZPRAsmOp4b32  : ZPRAsmOperand<"Vector4bS", 32, "_4b">;
 def ZPRAsmOp4b64  : ZPRAsmOperand<"Vector4bD", 64, "_4b">;
 
+def ZPR4b8  : ZPRRegOp<"b", ZPRAsmOp4b8,  ElementSizeB, ZPR_4b>;
 def ZPR4b16 : ZPRRegOp<"h", ZPRAsmOp4b16, ElementSizeH, ZPR_4b>;
 def ZPR4b32 : ZPRRegOp<"s", ZPRAsmOp4b32, ElementSizeS, ZPR_4b>;
 def ZPR4b64 : ZPRRegOp<"d", ZPRAsmOp4b64, ElementSizeD, ZPR_4b>;
 
 class FPRasZPR<int Width> : AsmOperandClass{
   let Name = "FPR" # Width # "asZPR";
   let PredicateMethod = "isFPRasZPR<AArch64::FPR" # Width # "RegClassID>";
   let RenderMethod = "addFPRasZPRRegOperands<" # Width # ">";
class ZPRVectorListMul<int ElementWidth, int NumRegs> : ZPRVectorList<ElementWidth, NumRegs> {
   let DiagnosticType = "Invalid" # Name;
   let PredicateMethod =
       "isTypedVectorListMultiple<RegKind::SVEDataVector, " # NumRegs # ", 0, "
                                                            # ElementWidth # ">";
 }
 
 let EncoderMethod = "EncodeRegAsMultipleOf<2>",
     DecoderMethod = "DecodeZPR2Mul2RegisterClass" in {
+  def ZZ_b_mul_r : RegisterOperand<ZPR2Mul2, "printTypedVectorList<0,'b'>"> {
+    let ParserMatchClass = ZPRVectorListMul<8, 2>;
+  }
+
+  def ZZ_h_mul_r : RegisterOperand<ZPR2Mul2, "printTypedVectorList<0, 'h'>"> {
+    let ParserMatchClass = ZPRVectorListMul<16, 2>;
+  }
+
   def ZZ_s_mul_r : RegisterOperand<ZPR2Mul2, "printTypedVectorList<0,'s'>"> {
     let ParserMatchClass = ZPRVectorListMul<32, 2>;
   }
 
   def ZZ_d_mul_r : RegisterOperand<ZPR2Mul2, "printTypedVectorList<0,'d'>"> {
     let ParserMatchClass = ZPRVectorListMul<64, 2>;
   }
 } // end let EncoderMethod/DecoderMethod
 
 let EncoderMethod = "EncodeRegAsMultipleOf<4>",
     DecoderMethod = "DecodeZPR4Mul4RegisterClass" in {
+  def ZZZZ_b_mul_r : RegisterOperand<ZPR4, "printTypedVectorList<0,'b'>"> {
+    let ParserMatchClass = ZPRVectorListMul<8, 4>;
+  }
+
+  def ZZZZ_h_mul_r : RegisterOperand<ZPR4Mul4, "printTypedVectorList<0,'h'>"> {
+    let ParserMatchClass = ZPRVectorListMul<16, 4>;
+  }
+
   def ZZZZ_s_mul_r : RegisterOperand<ZPR4Mul4, "printTypedVectorList<0,'s'>"> {
     let ParserMatchClass = ZPRVectorListMul<32, 4>;
   }
 
   def ZZZZ_d_mul_r : RegisterOperand<ZPR4Mul4, "printTypedVectorList<0,'d'>"> {
     let ParserMatchClass = ZPRVectorListMul<64, 4>;
   }
 } // end let EncoderMethod/DecoderMethod

llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td

 defm FMLA_VG4_M4ZZ_S  : sme2_mla_add_sub_array_vg4_single_S<"fmla", 0b00>;
 defm FMLA_VG2_M2Z2Z_S : sme2_mla_add_sub_array_vg2_multi_S<"fmla", 0b00>;
 defm FMLA_VG4_M4Z4Z_S : sme2_mla_add_sub_array_vg4_multi_S<"fmla", 0b00>;
 
 defm FMLS_VG2_M2ZZ_S  : sme2_mla_add_sub_array_vg2_single_S<"fmls", 0b01>;
 defm FMLS_VG4_M4ZZ_S  : sme2_mla_add_sub_array_vg4_single_S<"fmls", 0b01>;
 defm FMLS_VG2_M2Z2Z_S : sme2_mla_add_sub_array_vg2_multi_S<"fmls", 0b01>;
 defm FMLS_VG4_M4Z4Z_S : sme2_mla_add_sub_array_vg4_multi_S<"fmls", 0b01>;
+
+defm ADD_VG2_2ZZ  : sme2_sqdmulh_add_vector_vg2_single<"add", 0b011000>;
+defm ADD_VG4_4ZZ  : sme2_sqdmulh_add_vector_vg4_single<"add", 0b011000>;
+
+defm SQDMULH_2ZZ : sme2_sqdmulh_add_vector_vg2_single<"sqdmulh", 0b100000>;
+defm SQDMULH_4ZZ : sme2_sqdmulh_add_vector_vg4_single<"sqdmulh", 0b100000>;
 }
 
 
 let Predicates = [HasSME2, HasSMEI16I64] in {
 defm ADD_VG2_M2ZZ_D  : sme2_mla_add_sub_array_vg2_single_D<"add", 0b10>;
 defm ADD_VG4_M4ZZ_D  : sme2_mla_add_sub_array_vg4_single_D<"add", 0b10>;
 defm ADD_VG2_M2Z2Z_D : sme2_mla_add_sub_array_vg2_multi_D<"add", 0b10>;
 defm ADD_VG4_M4Z4Z_D : sme2_mla_add_sub_array_vg4_multi_D<"add", 0b10>;

llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp

AArch64AsmParser(const MCSubtargetInfo &STI, MCAsmParser &Parser,
     Parser.addAliasForDirective(".word", ".4byte");
     Parser.addAliasForDirective(".dword", ".8byte");
     Parser.addAliasForDirective(".xword", ".8byte");
 
     // Initialize the set of available features.
     setAvailableFeatures(ComputeAvailableFeatures(getSTI().getFeatureBits()));
   }
 
-  bool regsEqual(const MCParsedAsmOperand &Op1,
+  bool areEqualRegs(const MCParsedAsmOperand &Op1,
                     const MCParsedAsmOperand &Op2) const override;
   bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
                         SMLoc NameLoc, OperandVector &Operands) override;
   bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override;
   OperandMatchResultTy tryParseRegister(unsigned &RegNo, SMLoc &StartLoc,
                                         SMLoc &EndLoc) override;
   bool ParseDirective(AsmToken DirectiveID) override;
   unsigned validateTargetOperandClass(MCParsedAsmOperand &Op,
                                       unsigned Kind) override;
if (Kind != k_SVCR)
       return false;
     return SVCR.PStateField != -1U;
   }
 
   bool isReg() const override {
     return Kind == k_Register;
   }
 
+  bool isVectorList() const { return Kind == k_VectorList; }
+
   bool isScalarReg() const {
     return Kind == k_Register && Reg.Kind == RegKind::Scalar;
   }
 
   bool isNeonVectorReg() const {
     return Kind == k_Register && Reg.Kind == RegKind::NeonVector;
   }
 
if (check(Reg < First || Reg > RangeEnd, Start,
             Twine("expected register in range ") +
                 AArch64InstPrinter::getRegisterName(First) + " to " +
                 AArch64InstPrinter::getRegisterName(Last)))
     return true;
   Out = Reg - Base;
   return false;
 }
 
-bool AArch64AsmParser::regsEqual(const MCParsedAsmOperand &Op1,
+bool AArch64AsmParser::areEqualRegs(const MCParsedAsmOperand &Op1,
                                     const MCParsedAsmOperand &Op2) const {
   auto &AOp1 = static_cast<const AArch64Operand&>(Op1);
   auto &AOp2 = static_cast<const AArch64Operand&>(Op2);
+
+  if (AOp1.isVectorList() && AOp2.isVectorList())
+    return AOp1.getVectorListCount() == AOp2.getVectorListCount() &&
+           AOp1.getVectorListStart() == AOp2.getVectorListStart();
+
+  if (!AOp1.isReg() || !AOp2.isReg())
+    return false;
+
   if (AOp1.getRegEqualityTy() == RegConstraintEqualityTy::EqualsReg &&
       AOp2.getRegEqualityTy() == RegConstraintEqualityTy::EqualsReg)
-    return MCTargetAsmParser::regsEqual(Op1, Op2);
+    return MCTargetAsmParser::areEqualRegs(Op1, Op2);
 
   assert(AOp1.isScalarReg() && AOp2.isScalarReg() &&
          "Testing equality of non-scalar registers not supported");
 
   // Check if a registers match their sub/super register classes.
   if (AOp1.getRegEqualityTy() == EqualsSuperReg)
     return getXRegFromWReg(Op1.getReg()) == Op2.getReg();
   if (AOp1.getRegEqualityTy() == EqualsSubReg)
static std::string AArch64MnemonicSpellCheck(StringRef S,
                                              const FeatureBitset &FBS,
                                              unsigned VariantID = 0);
 
 bool AArch64AsmParser::showMatchError(SMLoc Loc, unsigned ErrCode,
                                       uint64_t ErrorInfo,
                                       OperandVector &Operands) {
   switch (ErrCode) {
   case Match_InvalidTiedOperand: {
-    RegConstraintEqualityTy EqTy =
-        static_cast<const AArch64Operand &>(*Operands[ErrorInfo])
-            .getRegEqualityTy();
-    switch (EqTy) {
+    auto &Op = static_cast<const AArch64Operand &>(*Operands[ErrorInfo]);
+    if (Op.isVectorList())
+      return Error(Loc, "operand must match destination register list");
+
+    assert(Op.isReg() && "Unexpected operand type");
+    switch (Op.getRegEqualityTy()) {
     case RegConstraintEqualityTy::EqualsSubReg:
       return Error(Loc, "operand must be 64-bit form of destination register");
     case RegConstraintEqualityTy::EqualsSuperReg:
       return Error(Loc, "operand must be 32-bit form of destination register");
     case RegConstraintEqualityTy::EqualsReg:
       return Error(Loc, "operand must match destination register");
     }
     llvm_unreachable("Unknown RegConstraintEqualityTy");
bool AArch64AsmParser::showMatchError(SMLoc Loc, unsigned ErrCode,
   case Match_InvalidZPR128:
     return Error(Loc, "invalid element width");
   case Match_InvalidZPR_3b8:
     return Error(Loc, "Invalid restricted vector register, expected z0.b..z7.b");
   case Match_InvalidZPR_3b16:
     return Error(Loc, "Invalid restricted vector register, expected z0.h..z7.h");
   case Match_InvalidZPR_3b32:
     return Error(Loc, "Invalid restricted vector register, expected z0.s..z7.s");
+  case Match_InvalidZPR_4b8:
+    return Error(Loc,
+                 "Invalid restricted vector register, expected z0.b..z15.b");
   case Match_InvalidZPR_4b16:
     return Error(Loc, "Invalid restricted vector register, expected z0.h..z15.h");
   case Match_InvalidZPR_4b32:
     return Error(Loc, "Invalid restricted vector register, expected z0.s..z15.s");
   case Match_InvalidZPR_4b64:
     return Error(Loc, "Invalid restricted vector register, expected z0.d..z15.d");
   case Match_InvalidSVEPattern:
     return Error(Loc, "invalid predicate pattern");
bool AArch64AsmParser::showMatchError(SMLoc Loc, unsigned ErrCode,
   case Match_InvalidMatrix32:
     return Error(Loc, "invalid matrix operand, expected suffix .s");
   case Match_InvalidMatrix64:
     return Error(Loc, "invalid matrix operand, expected suffix .d");
   case Match_InvalidMatrixIndexGPR32_12_15:
     return Error(Loc, "operand must be a register in range [w12, w15]");
   case Match_InvalidMatrixIndexGPR32_8_11:
     return Error(Loc, "operand must be a register in range [w8, w11]");
+  case Match_InvalidSVEVectorListMul2x8:
+  case Match_InvalidSVEVectorListMul2x16:
   case Match_InvalidSVEVectorListMul2x32:
   case Match_InvalidSVEVectorListMul2x64:
     return Error(Loc, "Invalid vector list, expected list with 2 consecutive "
                       "SVE vectors, where the first vector is a multiple of 2 "
                       "and with matching element types");
+  case Match_InvalidSVEVectorListMul4x8:
+  case Match_InvalidSVEVectorListMul4x16:
   case Match_InvalidSVEVectorListMul4x32:
   case Match_InvalidSVEVectorListMul4x64:
     return Error(Loc, "Invalid vector list, expected list with 4 consecutive "
                       "SVE vectors, where the first vector is a multiple of 4 "
                       "and with matching element types");
   default:
     llvm_unreachable("unexpected error code!");
   }
bool AArch64AsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
   case Match_InvalidZPR8:
   case Match_InvalidZPR16:
   case Match_InvalidZPR32:
   case Match_InvalidZPR64:
   case Match_InvalidZPR128:
   case Match_InvalidZPR_3b8:
   case Match_InvalidZPR_3b16:
   case Match_InvalidZPR_3b32:
+  case Match_InvalidZPR_4b8:
   case Match_InvalidZPR_4b16:
   case Match_InvalidZPR_4b32:
   case Match_InvalidZPR_4b64:
   case Match_InvalidSVEPredicateAnyReg:
   case Match_InvalidSVEPattern:
   case Match_InvalidSVEPredicateBReg:
   case Match_InvalidSVEPredicateHReg:
   case Match_InvalidSVEPredicateSReg:
bool AArch64AsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
   case Match_InvalidMatrixTileVectorV8:
   case Match_InvalidMatrixTileVectorV16:
   case Match_InvalidMatrixTileVectorV32:
   case Match_InvalidMatrixTileVectorV64:
   case Match_InvalidMatrixTileVectorV128:
   case Match_InvalidSVCR:
   case Match_InvalidMatrixIndexGPR32_12_15:
   case Match_InvalidMatrixIndexGPR32_8_11:
+  case Match_InvalidSVEVectorListMul2x8:
+  case Match_InvalidSVEVectorListMul2x16:
   case Match_InvalidSVEVectorListMul2x32:
   case Match_InvalidSVEVectorListMul2x64:
+  case Match_InvalidSVEVectorListMul4x8:
+  case Match_InvalidSVEVectorListMul4x16:
   case Match_InvalidSVEVectorListMul4x32:
   case Match_InvalidSVEVectorListMul4x64:
   case Match_MSR:
   case Match_MRS: {
     if (ErrorInfo >= Operands.size())
       return Error(IDLoc, "too few operands for instruction", SMRange(IDLoc, (*Operands.back()).getEndLoc()));
     // Any time we get here, there's nothing fancy to do. Just get the
     // operand SMLoc and display the diagnostic.

llvm/lib/Target/AArch64/SMEInstrFormats.td

 }
 
 multiclass sme2_mla_add_sub_array_vg4_multi_D<string mnemonic, bits<2> op>{
   def NAME : sme2_mla_add_sub_array_vg4_multi_base<0b1, op, MatrixOp64, ZZZZ_d_mul_r, mnemonic>;
 
   def : InstAlias<mnemonic # "\t$ZAd[$Rv, $imm3], $Zn, $Zm",
                  (!cast<Instruction>(NAME) MatrixOp64:$ZAd,  MatrixIndexGPR32Op8_11:$Rv, sme_elm_idx0_7:$imm3, ZZZZ_d_mul_r:$Zn, ZZZZ_d_mul_r:$Zm), 0>;
 }
+
+//===----------------------------------------------------------------------===//
+// SME2 Multi-vector - Multiple and Single SVE Destructive
+// Two and Four registers
+
+class sme2_sqdmulh_add_vector_vg2_single<bits<2> sz, bits<6> op,
+                                         RegisterOperand vector_ty,
+                                         ZPRRegOp zpr_ty, string mnemonic>
+    : I<(outs vector_ty:$Zdn), (ins vector_ty:$_Zdn, zpr_ty:$Zm),
+        mnemonic, "\t$Zdn, $_Zdn, $Zm",
+        "", []>, Sched<[]> {
+  bits<4> Zm;
+  bits<4> Zdn;
+  let Inst{31-24} = 0b11000001;
+  let Inst{23-22} = sz;
+  let Inst{21-20} = 0b10;
+  let Inst{19-16} = Zm;
+  let Inst{15-11} = 0b10100;
+  let Inst{10-5}  = op;
+  let Inst{4-1}   = Zdn;
+  let Inst{0}     = 0b0;
+  let Constraints = "$Zdn = $_Zdn";
+}
+
+multiclass sme2_sqdmulh_add_vector_vg2_single<string mnemonic, bits<6> op> {
+  def _B : sme2_sqdmulh_add_vector_vg2_single<0b00, op, ZZ_b_mul_r, ZPR4b8, mnemonic>;
+  def _H : sme2_sqdmulh_add_vector_vg2_single<0b01, op, ZZ_h_mul_r, ZPR4b16, mnemonic>;
+  def _S : sme2_sqdmulh_add_vector_vg2_single<0b10, op, ZZ_s_mul_r, ZPR4b32, mnemonic>;
+  def _D : sme2_sqdmulh_add_vector_vg2_single<0b11, op, ZZ_d_mul_r, ZPR4b64, mnemonic>;
+}
+
+class sme2_sqdmulh_add_vector_vg4_single<bits<2> sz, bits<6> op,
+                                         RegisterOperand vector_ty,
+                                         ZPRRegOp zpr_ty, string mnemonic>
+    : I<(outs vector_ty:$Zdn), (ins vector_ty:$_Zdn, zpr_ty:$Zm),
+        mnemonic, "\t$Zdn, $_Zdn, $Zm",
+        "", []>, Sched<[]> {
+  bits<4> Zm;
+  bits<3> Zdn;
+  let Inst{31-24} = 0b11000001;
+  let Inst{23-22} = sz;
+  let Inst{21-20} = 0b10;
+  let Inst{19-16} = Zm;
+  let Inst{15-11} = 0b10101;
+  let Inst{10-5}  = op;
+  let Inst{4-2}   = Zdn;
+  let Inst{1-0}   = 0b00;
+  let Constraints = "$Zdn = $_Zdn";
+}
+
+multiclass sme2_sqdmulh_add_vector_vg4_single<string mnemonic, bits<6> op> {
+  def _B : sme2_sqdmulh_add_vector_vg4_single<0b00, op, ZZZZ_b_mul_r, ZPR4b8, mnemonic>;
+  def _H : sme2_sqdmulh_add_vector_vg4_single<0b01, op, ZZZZ_h_mul_r, ZPR4b16, mnemonic>;
+  def _S : sme2_sqdmulh_add_vector_vg4_single<0b10, op, ZZZZ_s_mul_r, ZPR4b32, mnemonic>;
+  def _D : sme2_sqdmulh_add_vector_vg4_single<0b11, op, ZZZZ_d_mul_r, ZPR4b64, mnemonic>;
+}
+

llvm/test/MC/AArch64/SME2/add-diagnostics.s

 // CHECK-NEXT: add za.s[w12, 0], {z0.s-z1.s}, z0.s
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 add     za.s[w7, 0], {z0.s - z1.s}, {z2.s - z3.s}
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must be a register in range [w8, w11]
 // CHECK-NEXT: add     za.s[w7, 0], {z0.s - z1.s}, {z2.s - z3.s}
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:$
 
-
 // --------------------------------------------------------------------------//
 // Invalid Matrix Operand
 
 add za.h[w8, #0], {z0.h-z3.h}, z4.h
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid matrix operand, expected suffix .d
 // CHECK-NEXT: add za.h[w8, #0], {z0.h-z3.h}, z4.h
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 

 // CHECK-NEXT: add za.s[w10, 3, vgx2], {z10.s-z11.s}, {z21.s-z22.s}
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 add za.d[w11, 7, vgx4], {z12.d-z15.d}, {z9.d-z12.d}
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 4 consecutive SVE vectors, where the first vector is a multiple of 4 and with matching element types
 // CHECK-NEXT: add za.d[w11, 7, vgx4], {z12.d-z15.d}, {z9.d-z12.d}
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
-
 add za.s[w10, 3], {z10.b-z11.b}, {z20.b-z21.b}
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
 // CHECK-NEXT: add za.s[w10, 3], {z10.b-z11.b}, {z20.b-z21.b}
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
 
 add     za.d[w11, 7], {z28.h - z31.h}, {z28.h - z31.h}
 // CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
 // CHECK-NEXT: add     za.d[w11, 7], {z28.h - z31.h}, {z28.h - z31.h}
 // CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// The tied operands must match, even for vector groups.
+
+add {z0.s-z1.s}, {z2.s-z3.s}, z15.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register list
+// CHECK-NEXT: add {z0.s-z1.s}, {z2.s-z3.s}, z15.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+add {z0.s,z1.s}, {z2.s,z3.s}, z15.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register list
+// CHECK-NEXT: add {z0.s,z1.s}, {z2.s,z3.s}, z15.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+add {z0.s,z1.s}, {z0.s,z2.s}, z15.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must be sequential
+// CHECK-NEXT: add {z0.s,z1.s}, {z0.s,z2.s}, z15.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+add {z0.s,z1.s}, {z0.s,z1.s,z2.s}, z15.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: add {z0.s,z1.s}, {z0.s,z1.s,z2.s}, z15.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+add {z0.s,z1.s}, {z0.d,z1.d}, z15.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: add {z0.s,z1.s}, {z0.d,z1.d}, z15.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+

llvm/test/MC/AArch64/SME2/add.s

 // RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2,+sme-i16i64 < %s \
 // RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
 // RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
 // RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2,+sme-i16i64 < %s \
 // RUN:        | llvm-objdump -d --mattr=+sme2,+sme-i16i64 - | FileCheck %s --check-prefix=CHECK-INST
 // RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2,+sme-i16i64 < %s \
 // RUN:        | llvm-objdump -d --mattr=-sme2 - | FileCheck %s --check-prefix=CHECK-UNKNOWN
 // RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2,+sme-i16i64 < %s \
 // RUN:        | sed '/.text/d' | sed 's/.*encoding: //g' \
 // RUN:        | llvm-mc -triple=aarch64 -mattr=+sme2,+sme-i16i64 -disassemble -show-encoding \
 // RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
 
 
+add     {z0.h, z1.h}, {z0.h, z1.h}, z0.h  // 11000001-01100000-10100011-00000000
+// CHECK-INST: add     { z0.h, z1.h }, { z0.h, z1.h }, z0.h
+// CHECK-ENCODING: [0x00,0xa3,0x60,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c160a300 <unknown>
+
+add     {z20.h, z21.h}, {z20.h, z21.h}, z5.h  // 11000001-01100101-10100011-00010100
+// CHECK-INST: add     { z20.h, z21.h }, { z20.h, z21.h }, z5.h
+// CHECK-ENCODING: [0x14,0xa3,0x65,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c165a314 <unknown>
+
+add     {z22.h, z23.h}, {z22.h, z23.h}, z8.h  // 11000001-01101000-10100011-00010110
+// CHECK-INST: add     { z22.h, z23.h }, { z22.h, z23.h }, z8.h
+// CHECK-ENCODING: [0x16,0xa3,0x68,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c168a316 <unknown>
+
+add     {z30.h, z31.h}, {z30.h, z31.h}, z15.h  // 11000001-01101111-10100011-00011110
+// CHECK-INST: add     { z30.h, z31.h }, { z30.h, z31.h }, z15.h
+// CHECK-ENCODING: [0x1e,0xa3,0x6f,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c16fa31e <unknown>
+
+
 add     za.s[w8, 0, vgx2], {z0.s, z1.s}, z0.s  // 11000001, 00100000, 00011000, 00010000
 // CHECK-INST: add     za.s[w8, 0, vgx2], { z0.s, z1.s }, z0.s
 // CHECK-ENCODING: [0x10,0x18,0x20,0xc1]
 // CHECK-ERROR: instruction requires: sme2
 // CHECK-UNKNOWN: c1201810 <unknown>
 
 add     za.s[w8, 0], {z0.s - z1.s}, z0.s  // 11000001-00100000-00011000-00010000
 // CHECK-INST: add     za.s[w8, 0, vgx2], { z0.s, z1.s }, z0.s
 // CHECK-ENCODING: [0x10,0x18,0x20,0xc1]
 // CHECK-ERROR: instruction requires: sme2
 // CHECK-UNKNOWN: c1201810 <unknown>
 
 add     za.s[w10, 5, vgx2], {z10.s, z11.s}, z5.s  // 11000001, 00100101, 01011001, 01010101
 // CHECK-INST: add     za.s[w10, 5, vgx2], { z10.s, z11.s }, z5.s
 // CHECK-ENCODING: [0x55,0x59,0x25,0xc1]
 // CHECK-ERROR: instruction requires: sme2

 
 add     za.s[w9, 7], {z12.s - z13.s}, z11.s  // 11000001-00101011-00111001-10010111
 // CHECK-INST: add     za.s[w9, 7, vgx2], { z12.s, z13.s }, z11.s
 // CHECK-ENCODING: [0x97,0x39,0x2b,0xc1]
 // CHECK-ERROR: instruction requires: sme2
 // CHECK-UNKNOWN: c12b3997 <unknown>
 
 
+add     {z0.s-z1.s}, {z0.s-z1.s}, z0.s  // 11000001-10100000-10100011-00000000
+// CHECK-INST: add     { z0.s, z1.s }, { z0.s, z1.s }, z0.s
+// CHECK-ENCODING: [0x00,0xa3,0xa0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a0a300 <unknown>
+
+add     {z20.s-z21.s}, {z20.s-z21.s}, z5.s  // 11000001-10100101-10100011-00010100
+// CHECK-INST: add     { z20.s, z21.s }, { z20.s, z21.s }, z5.s
+// CHECK-ENCODING: [0x14,0xa3,0xa5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a5a314 <unknown>
+
+add     {z22.s-z23.s}, {z22.s-z23.s}, z8.s  // 11000001-10101000-10100011-00010110
+// CHECK-INST: add     { z22.s, z23.s }, { z22.s, z23.s }, z8.s
+// CHECK-ENCODING: [0x16,0xa3,0xa8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a8a316 <unknown>
+
+add     {z30.s-z31.s}, {z30.s-z31.s}, z15.s  // 11000001-10101111-10100011-00011110
+// CHECK-INST: add     { z30.s, z31.s }, { z30.s, z31.s }, z15.s
+// CHECK-ENCODING: [0x1e,0xa3,0xaf,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1afa31e <unknown>
+
+
 add     za.s[w8, 0, vgx2], {z0.s, z1.s}, {z0.s, z1.s}  // 11000001, 10100000, 00011000, 00010000
 // CHECK-INST: add     za.s[w8, 0, vgx2], { z0.s, z1.s }, { z0.s, z1.s }
 // CHECK-ENCODING: [0x10,0x18,0xa0,0xc1]
 // CHECK-ERROR: instruction requires: sme2
 // CHECK-UNKNOWN: c1a01810 <unknown>
 
 add     za.s[w8, 0], {z0.s - z1.s}, {z0.s - z1.s}  // 11000001-10100000-00011000-00010000
 // CHECK-INST: add     za.s[w8, 0, vgx2], { z0.s, z1.s }, { z0.s, z1.s }

 
 add     za.d[w9, 7], {z12.d - z13.d}, z11.d  // 11000001-01101011-00111001-10010111
 // CHECK-INST: add     za.d[w9, 7, vgx2], { z12.d, z13.d }, z11.d
 // CHECK-ENCODING: [0x97,0x39,0x6b,0xc1]
 // CHECK-ERROR: instruction requires: sme2
 // CHECK-UNKNOWN: c16b3997 <unknown>
 
 
+add     {z0.d-z1.d}, {z0.d-z1.d}, z0.d  // 11000001-11100000-10100011-00000000
+// CHECK-INST: add     { z0.d, z1.d }, { z0.d, z1.d }, z0.d
+// CHECK-ENCODING: [0x00,0xa3,0xe0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e0a300 <unknown>
+
+add     {z20.d-z21.d}, {z20.d-z21.d}, z5.d  // 11000001-11100101-10100011-00010100
+// CHECK-INST: add     { z20.d, z21.d }, { z20.d, z21.d }, z5.d
+// CHECK-ENCODING: [0x14,0xa3,0xe5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e5a314 <unknown>
+
+add     {z22.d-z23.d}, {z22.d-z23.d}, z8.d  // 11000001-11101000-10100011-00010110
+// CHECK-INST: add     { z22.d, z23.d }, { z22.d, z23.d }, z8.d
+// CHECK-ENCODING: [0x16,0xa3,0xe8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e8a316 <unknown>
+
+add     {z30.d-z31.d}, {z30.d-z31.d}, z15.d  // 11000001-11101111-10100011-00011110
+// CHECK-INST: add     { z30.d, z31.d }, { z30.d, z31.d }, z15.d
+// CHECK-ENCODING: [0x1e,0xa3,0xef,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1efa31e <unknown>
+
+
 add     za.d[w8, 0, vgx2], {z0.d, z1.d}, {z0.d, z1.d}  // 11000001, 11100000, 00011000, 00010000
 // CHECK-INST: add     za.d[w8, 0, vgx2], { z0.d, z1.d }, { z0.d, z1.d }
 // CHECK-ENCODING: [0x10,0x18,0xe0,0xc1]
 // CHECK-ERROR: instruction requires: sme2
 // CHECK-UNKNOWN: c1e01810 <unknown>
 
 add     za.d[w8, 0], {z0.d - z1.d}, {z0.d - z1.d}  // 11000001-11100000-00011000-00010000
 // CHECK-INST: add     za.d[w8, 0, vgx2], { z0.d, z1.d }, { z0.d, z1.d }

 // CHECK-UNKNOWN: c1fe1811 <unknown>
 
 add     za.d[w8, 1], {z0.d - z1.d}, {z30.d - z31.d}  // 11000001-11111110-00011000-00010001
 // CHECK-INST: add     za.d[w8, 1, vgx2], { z0.d, z1.d }, { z30.d, z31.d }
 // CHECK-ENCODING: [0x11,0x18,0xfe,0xc1]
 // CHECK-ERROR: instruction requires: sme2
 // CHECK-UNKNOWN: c1fe1811 <unknown>
 
+
 add     za.d[w10, 0, vgx2], {z18.d, z19.d}, {z20.d, z21.d}  // 11000001, 11110100, 01011010, 01010000
 // CHECK-INST: add     za.d[w10, 0, vgx2], { z18.d, z19.d }, { z20.d, z21.d }
 // CHECK-ENCODING: [0x50,0x5a,0xf4,0xc1]
 // CHECK-ERROR: instruction requires: sme2
 // CHECK-UNKNOWN: c1f45a50 <unknown>
 
 add     za.d[w10, 0], {z18.d - z19.d}, {z20.d - z21.d}  // 11000001-11110100-01011010-01010000
 // CHECK-INST: add     za.d[w10, 0, vgx2], { z18.d, z19.d }, { z20.d, z21.d }

 
 add     za.d[w9, 7], {z12.d - z13.d}, {z10.d - z11.d}  // 11000001-11101010-00111001-10010111
 // CHECK-INST: add     za.d[w9, 7, vgx2], { z12.d, z13.d }, { z10.d, z11.d }
 // CHECK-ENCODING: [0x97,0x39,0xea,0xc1]
 // CHECK-ERROR: instruction requires: sme2
 // CHECK-UNKNOWN: c1ea3997 <unknown>
 
 
-add     za.s[w8, 0, vgx4], {z0.s - z3.s}, z0.s  // 11000001-00110000-00011000-00010000
+add     {z0.b-z1.b}, {z0.b-z1.b}, z0.b  // 11000001-00100000-10100011-00000000
+// CHECK-INST: add     { z0.b, z1.b }, { z0.b, z1.b }, z0.b
+// CHECK-ENCODING: [0x00,0xa3,0x20,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c120a300 <unknown>
+
+add     {z20.b-z21.b}, {z20.b-z21.b}, z5.b  // 11000001-00100101-10100011-00010100
+// CHECK-INST: add     { z20.b, z21.b }, { z20.b, z21.b }, z5.b
+// CHECK-ENCODING: [0x14,0xa3,0x25,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c125a314 <unknown>
+
+add     {z22.b-z23.b}, {z22.b-z23.b}, z8.b  // 11000001-00101000-10100011-00010110
+// CHECK-INST: add     { z22.b, z23.b }, { z22.b, z23.b }, z8.b
+// CHECK-ENCODING: [0x16,0xa3,0x28,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c128a316 <unknown>
+
+add     {z30.b-z31.b}, {z30.b-z31.b}, z15.b  // 11000001-00101111-10100011-00011110
+// CHECK-INST: add     { z30.b, z31.b }, { z30.b, z31.b }, z15.b
+// CHECK-ENCODING: [0x1e,0xa3,0x2f,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c12fa31e <unknown>
+
+
+add     {z0.h - z3.h}, {z0.h - z3.h}, z0.h  // 11000001-01100000-10101011-00000000
+// CHECK-INST: add     { z0.h - z3.h }, { z0.h - z3.h }, z0.h
+// CHECK-ENCODING: [0x00,0xab,0x60,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c160ab00 <unknown>
+
+add     {z20.h - z23.h}, {z20.h - z23.h}, z5.h  // 11000001-01100101-10101011-00010100
+// CHECK-INST: add     { z20.h - z23.h }, { z20.h - z23.h }, z5.h
+// CHECK-ENCODING: [0x14,0xab,0x65,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c165ab14 <unknown>
+
+add     {z20.h - z23.h}, {z20.h - z23.h}, z8.h  // 11000001-01101000-10101011-00010100
+// CHECK-INST: add     { z20.h - z23.h }, { z20.h - z23.h }, z8.h
+// CHECK-ENCODING: [0x14,0xab,0x68,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c168ab14 <unknown>
+
+add     {z28.h - z31.h}, {z28.h - z31.h}, z15.h  // 11000001-01101111-10101011-00011100
+// CHECK-INST: add     { z28.h - z31.h }, { z28.h - z31.h }, z15.h
+// CHECK-ENCODING: [0x1c,0xab,0x6f,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c16fab1c <unknown>
+
+
+add     za.s[w8, 0, vgx4], {z0.s-z3.s}, z0.s  // 11000001-00110000-00011000-00010000
 // CHECK-INST: add     za.s[w8, 0, vgx4], { z0.s - z3.s }, z0.s
 // CHECK-ENCODING: [0x10,0x18,0x30,0xc1]
 // CHECK-ERROR: instruction requires: sme2
 // CHECK-UNKNOWN: c1301810 <unknown>
 
 add     za.s[w8, 0], {z0.s - z3.s}, z0.s  // 11000001-00110000-00011000-00010000
 // CHECK-INST: add     za.s[w8, 0, vgx4], { z0.s - z3.s }, z0.s
 // CHECK-ENCODING: [0x10,0x18,0x30,0xc1]

 
 add     za.s[w9, 7], {z12.s - z15.s}, z11.s  // 11000001-00111011-00111001-10010111
 // CHECK-INST: add     za.s[w9, 7, vgx4], { z12.s - z15.s }, z11.s
 // CHECK-ENCODING: [0x97,0x39,0x3b,0xc1]
 // CHECK-ERROR: instruction requires: sme2
 // CHECK-UNKNOWN: c13b3997 <unknown>
 
 
-add     za.s[w8, 0], {z0.s - z3.s}, {z0.s - z3.s}  // 11000001-10100001-00011000-00010000
+add     {z0.s-z3.s}, {z0.s-z3.s}, z0.s  // 11000001-10100000-10101011-00000000
+// CHECK-INST: add     { z0.s - z3.s }, { z0.s - z3.s }, z0.s
+// CHECK-ENCODING: [0x00,0xab,0xa0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a0ab00 <unknown>
+
+add     {z20.s-z23.s}, {z20.s-z23.s}, z5.s  // 11000001-10100101-10101011-00010100
+// CHECK-INST: add     { z20.s - z23.s }, { z20.s - z23.s }, z5.s
+// CHECK-ENCODING: [0x14,0xab,0xa5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a5ab14 <unknown>
+
+add     {z20.s-z23.s}, {z20.s-z23.s}, z8.s  // 11000001-10101000-10101011-00010100
+// CHECK-INST: add     { z20.s - z23.s }, { z20.s - z23.s }, z8.s
+// CHECK-ENCODING: [0x14,0xab,0xa8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a8ab14 <unknown>
+
+add     {z28.s-z31.s}, {z28.s-z31.s}, z15.s  // 11000001-10101111-10101011-00011100
+// CHECK-INST: add     { z28.s - z31.s }, { z28.s - z31.s }, z15.s
+// CHECK-ENCODING: [0x1c,0xab,0xaf,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1afab1c <unknown>
+
+
+add     za.s[w8, 0, vgx4], {z0.s-z3.s}, {z0.s-z3.s}  // 11000001-10100001-00011000-00010000
+// CHECK-INST: add     za.s[w8, 0, vgx4], { z0.s - z3.s }, { z0.s - z3.s }
+// CHECK-ENCODING: [0x10,0x18,0xa1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a11810 <unknown>
+
+add     za.s[w8, 0], {z0.s-z3.s}, {z0.s-z3.s}  // 11000001-10100001-00011000-00010000
 // CHECK-INST: add     za.s[w8, 0, vgx4], { z0.s - z3.s }, { z0.s - z3.s }
 // CHECK-ENCODING: [0x10,0x18,0xa1,0xc1]
 // CHECK-ERROR: instruction requires: sme2
 // CHECK-UNKNOWN: c1a11810 <unknown>
 
 add     za.s[w10, 5, vgx4], {z8.s - z11.s}, {z20.s - z23.s}  // 11000001-10110101-01011001-00010101
 // CHECK-INST: add     za.s[w10, 5, vgx4], { z8.s - z11.s }, { z20.s - z23.s }
 // CHECK-ENCODING: [0x15,0x59,0xb5,0xc1]

 // CHECK-ERROR: instruction requires: sme2
 // CHECK-UNKNOWN: c1e93997 <unknown>
 
 add     za.d[w9, 7], {z12.d - z15.d}, {z8.d - z11.d}  // 11000001-11101001-00111001-10010111
 // CHECK-INST: add     za.d[w9, 7, vgx4], { z12.d - z15.d }, { z8.d - z11.d }
 // CHECK-ENCODING: [0x97,0x39,0xe9,0xc1]
 // CHECK-ERROR: instruction requires: sme2
 // CHECK-UNKNOWN: c1e93997 <unknown>
+
+
+add     {z0.d-z3.d}, {z0.d-z3.d}, z0.d  // 11000001-11100000-10101011-00000000
+// CHECK-INST: add     { z0.d - z3.d }, { z0.d - z3.d }, z0.d
+// CHECK-ENCODING: [0x00,0xab,0xe0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e0ab00 <unknown>
+
+add     {z20.d-z23.d}, {z20.d-z23.d}, z5.d  // 11000001-11100101-10101011-00010100
+// CHECK-INST: add     { z20.d - z23.d }, { z20.d - z23.d }, z5.d
+// CHECK-ENCODING: [0x14,0xab,0xe5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e5ab14 <unknown>
+
+add     {z20.d-z23.d}, {z20.d-z23.d}, z8.d  // 11000001-11101000-10101011-00010100
+// CHECK-INST: add     { z20.d - z23.d }, { z20.d - z23.d }, z8.d
+// CHECK-ENCODING: [0x14,0xab,0xe8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e8ab14 <unknown>
+
+add     {z28.d-z31.d}, {z28.d-z31.d}, z15.d  // 11000001-11101111-10101011-00011100
+// CHECK-INST: add     { z28.d - z31.d }, { z28.d - z31.d }, z15.d
+// CHECK-ENCODING: [0x1c,0xab,0xef,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1efab1c <unknown>
+
+
+add     za.d[w8, 0, vgx4], {z0.d-z3.d}, {z0.d-z3.d}  // 11000001-11100001-00011000-00010000
+// CHECK-INST: add     za.d[w8, 0, vgx4], { z0.d - z3.d }, { z0.d - z3.d }
+// CHECK-ENCODING: [0x10,0x18,0xe1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e11810 <unknown>
+
+add     za.d[w8, 0], {z0.d - z3.d}, {z0.d - z3.d}  // 11000001-11100001-00011000-00010000
+// CHECK-INST: add     za.d[w8, 0, vgx4], { z0.d - z3.d }, { z0.d - z3.d }
+// CHECK-ENCODING: [0x10,0x18,0xe1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e11810 <unknown>
+
+add     za.d[w10, 5, vgx4], {z8.d - z11.d}, {z20.d - z23.d}  // 11000001-11110101-01011001-00010101
+// CHECK-INST: add     za.d[w10, 5, vgx4], { z8.d - z11.d }, { z20.d - z23.d }
+// CHECK-ENCODING: [0x15,0x59,0xf5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1f55915 <unknown>
+
+add     za.d[w10, 5], {z8.d - z11.d}, {z20.d - z23.d}  // 11000001-11110101-01011001-00010101
+// CHECK-INST: add     za.d[w10, 5, vgx4], { z8.d - z11.d }, { z20.d - z23.d }
+// CHECK-ENCODING: [0x15,0x59,0xf5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1f55915 <unknown>
+
+add     za.d[w11, 7, vgx4], {z12.d - z15.d}, {z8.d - z11.d}  // 11000001-11101001-01111001-10010111
+// CHECK-INST: add     za.d[w11, 7, vgx4], { z12.d - z15.d }, { z8.d - z11.d }
+// CHECK-ENCODING: [0x97,0x79,0xe9,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e97997 <unknown>
+
+add     za.d[w11, 7], {z12.d - z15.d}, {z8.d - z11.d}  // 11000001-11101001-01111001-10010111
+// CHECK-INST: add     za.d[w11, 7, vgx4], { z12.d - z15.d }, { z8.d - z11.d }
+// CHECK-ENCODING: [0x97,0x79,0xe9,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e97997 <unknown>
+
+add     za.d[w11, 7, vgx4], {z28.d - z31.d}, {z28.d - z31.d}  // 11000001-11111101-01111011-10010111
+// CHECK-INST: add     za.d[w11, 7, vgx4], { z28.d - z31.d }, { z28.d - z31.d }
+// CHECK-ENCODING: [0x97,0x7b,0xfd,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1fd7b97 <unknown>
+
+add     za.d[w11, 7], {z28.d - z31.d}, {z28.d - z31.d}  // 11000001-11111101-01111011-10010111
+// CHECK-INST: add     za.d[w11, 7, vgx4], { z28.d - z31.d }, { z28.d - z31.d }
+// CHECK-ENCODING: [0x97,0x7b,0xfd,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1fd7b97 <unknown>
+
+add     za.d[w8, 5, vgx4], {z16.d - z19.d}, {z16.d - z19.d}  // 11000001-11110001-00011010-00010101
+// CHECK-INST: add     za.d[w8, 5, vgx4], { z16.d - z19.d }, { z16.d - z19.d }
+// CHECK-ENCODING: [0x15,0x1a,0xf1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1f11a15 <unknown>
+
+add     za.d[w8, 5], {z16.d - z19.d}, {z16.d - z19.d}  // 11000001-11110001-00011010-00010101
+// CHECK-INST: add     za.d[w8, 5, vgx4], { z16.d - z19.d }, { z16.d - z19.d }
+// CHECK-ENCODING: [0x15,0x1a,0xf1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1f11a15 <unknown>
+
+add     za.d[w8, 1, vgx4], {z0.d - z3.d}, {z28.d - z31.d}  // 11000001-11111101-00011000-00010001
+// CHECK-INST: add     za.d[w8, 1, vgx4], { z0.d - z3.d }, { z28.d - z31.d }
+// CHECK-ENCODING: [0x11,0x18,0xfd,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1fd1811 <unknown>
+
+add     za.d[w8, 1], {z0.d - z3.d}, {z28.d - z31.d}  // 11000001-11111101-00011000-00010001
+// CHECK-INST: add     za.d[w8, 1, vgx4], { z0.d - z3.d }, { z28.d - z31.d }
+// CHECK-ENCODING: [0x11,0x18,0xfd,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1fd1811 <unknown>
+
+add     za.d[w10, 0, vgx4], {z16.d - z19.d}, {z20.d - z23.d}  // 11000001-11110101-01011010-00010000
+// CHECK-INST: add     za.d[w10, 0, vgx4], { z16.d - z19.d }, { z20.d - z23.d }
+// CHECK-ENCODING: [0x10,0x5a,0xf5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1f55a10 <unknown>
+
+add     za.d[w10, 0], {z16.d - z19.d}, {z20.d - z23.d}  // 11000001-11110101-01011010-00010000
+// CHECK-INST: add     za.d[w10, 0, vgx4], { z16.d - z19.d }, { z20.d - z23.d }
+// CHECK-ENCODING: [0x10,0x5a,0xf5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1f55a10 <unknown>
+
+add     za.d[w8, 0, vgx4], {z12.d - z15.d}, {z0.d - z3.d}  // 11000001-11100001-00011001-10010000
+// CHECK-INST: add     za.d[w8, 0, vgx4], { z12.d - z15.d }, { z0.d - z3.d }
+// CHECK-ENCODING: [0x90,0x19,0xe1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e11990 <unknown>
+
+add     za.d[w8, 0], {z12.d - z15.d}, {z0.d - z3.d}  // 11000001-11100001-00011001-10010000
+// CHECK-INST: add     za.d[w8, 0, vgx4], { z12.d - z15.d }, { z0.d - z3.d }
+// CHECK-ENCODING: [0x90,0x19,0xe1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e11990 <unknown>
+
+add     za.d[w10, 1, vgx4], {z0.d - z3.d}, {z24.d - z27.d}  // 11000001-11111001-01011000-00010001
+// CHECK-INST: add     za.d[w10, 1, vgx4], { z0.d - z3.d }, { z24.d - z27.d }
+// CHECK-ENCODING: [0x11,0x58,0xf9,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1f95811 <unknown>
+
+add     za.d[w10, 1], {z0.d - z3.d}, {z24.d - z27.d}  // 11000001-11111001-01011000-00010001
+// CHECK-INST: add     za.d[w10, 1, vgx4], { z0.d - z3.d }, { z24.d - z27.d }
+// CHECK-ENCODING: [0x11,0x58,0xf9,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1f95811 <unknown>
+
+add     za.d[w8, 5, vgx4], {z20.d - z23.d}, {z28.d - z31.d}  // 11000001-11111101-00011010-10010101
+// CHECK-INST: add     za.d[w8, 5, vgx4], { z20.d - z23.d }, { z28.d - z31.d }
+// CHECK-ENCODING: [0x95,0x1a,0xfd,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1fd1a95 <unknown>
+
+add     za.d[w8, 5], {z20.d - z23.d}, {z28.d - z31.d}  // 11000001-11111101-00011010-10010101
+// CHECK-INST: add     za.d[w8, 5, vgx4], { z20.d - z23.d }, { z28.d - z31.d }
+// CHECK-ENCODING: [0x95,0x1a,0xfd,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1fd1a95 <unknown>
+
+add     za.d[w11, 2, vgx4], {z8.d - z11.d}, {z0.d - z3.d}  // 11000001-11100001-01111001-00010010
+// CHECK-INST: add     za.d[w11, 2, vgx4], { z8.d - z11.d }, { z0.d - z3.d }
+// CHECK-ENCODING: [0x12,0x79,0xe1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e17912 <unknown>
+
+add     za.d[w11, 2], {z8.d - z11.d}, {z0.d - z3.d}  // 11000001-11100001-01111001-00010010
+// CHECK-INST: add     za.d[w11, 2, vgx4], { z8.d - z11.d }, { z0.d - z3.d }
+// CHECK-ENCODING: [0x12,0x79,0xe1,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e17912 <unknown>
+
+add     za.d[w9, 7, vgx4], {z12.d - z15.d}, {z8.d - z11.d}  // 11000001-11101001-00111001-10010111
+// CHECK-INST: add     za.d[w9, 7, vgx4], { z12.d - z15.d }, { z8.d - z11.d }
+// CHECK-ENCODING: [0x97,0x39,0xe9,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e93997 <unknown>
+
+add     za.d[w9, 7], {z12.d - z15.d}, {z8.d - z11.d}  // 11000001-11101001-00111001-10010111
+// CHECK-INST: add     za.d[w9, 7, vgx4], { z12.d - z15.d }, { z8.d - z11.d }
+// CHECK-ENCODING: [0x97,0x39,0xe9,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e93997 <unknown>
+
+
+add     {z0.b-z3.b}, {z0.b-z3.b}, z0.b  // 11000001-00100000-10101011-00000000
+// CHECK-INST: add     { z0.b - z3.b }, { z0.b - z3.b }, z0.b
+// CHECK-ENCODING: [0x00,0xab,0x20,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c120ab00 <unknown>
+
+add     {z20.b-z23.b}, {z20.b-z23.b}, z5.b  // 11000001-00100101-10101011-00010100
+// CHECK-INST: add     { z20.b - z23.b }, { z20.b - z23.b }, z5.b
+// CHECK-ENCODING: [0x14,0xab,0x25,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c125ab14 <unknown>
+
+add     {z20.b-z23.b}, {z20.b-z23.b}, z8.b  // 11000001-00101000-10101011-00010100
+// CHECK-INST: add     { z20.b - z23.b }, { z20.b - z23.b }, z8.b
+// CHECK-ENCODING: [0x14,0xab,0x28,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c128ab14 <unknown>
+
+add     {z28.b-z31.b}, {z28.b-z31.b}, z15.b  // 11000001-00101111-10101011-00011100
+// CHECK-INST: add     { z28.b - z31.b }, { z28.b - z31.b }, z15.b
+// CHECK-ENCODING: [0x1c,0xab,0x2f,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c12fab1c <unknown>
+

llvm/test/MC/AArch64/SME2/sqdmulh-diagnostics.s

+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2,+sme-i64 2>&1 < %s | FileCheck %s
+
+// --------------------------------------------------------------------------//
+// Invalid vector list
+
+sqdmulh {z0.h-z2.h}, {z0.h-z1.h}, z0.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: sqdmulh {z0.h-z2.h}, {z0.h-z1.h}, z0.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+sqdmulh {z28.s-z31.s}, {z0.s-z4.s}, z15.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid number of vectors
+// CHECK-NEXT: sqdmulh {z28.s-z31.s}, {z0.s-z4.s}, z15.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+sqdmulh {z1.d-z4.d}, {z0.d-z3.d}, z0.d
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 4 consecutive SVE vectors, where the first vector is a multiple of 4 and with matching element types
+// CHECK-NEXT: sqdmulh {z1.d-z4.d}, {z0.d-z3.d}, z0.d
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+sqdmulh {z28.b-z29.b}, {z1.b-z2.b}, z15.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors, where the first vector is a multiple of 2 and with matching element types
+// CHECK-NEXT: sqdmulh {z28.b-z29.b}, {z1.b-z2.b}, z15.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+sqdmulh {z28.h-z29.h}, {z1.h-z2.h}, z15.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors, where the first vector is a multiple of 2 and with matching element types
+// CHECK-NEXT: sqdmulh {z28.h-z29.h}, {z1.h-z2.h}, z15.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Invalid single vector register
+
+sqdmulh {z28.b-z29.b}, {z0.b-z1.b}, z16.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected z0.b..z15.b
+// CHECK-NEXT: sqdmulh {z28.b-z29.b}, {z0.b-z1.b}, z16.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Invalid register suffix
+
+sqdmulh {z0.d-z3.d}, {z0.d-z3.d}, z0.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid restricted vector register, expected z0.d..z15.d
+// CHECK-NEXT: sqdmulh {z0.d-z3.d}, {z0.d-z3.d}, z0.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+sqdmulh {z0.d-z3.h}, {z0.d-z3.d}, z0.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: mismatched register size suffix
+// CHECK-NEXT: sqdmulh {z0.d-z3.h}, {z0.d-z3.d}, z0.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// The tied operands must match, even for vector groups.
+
+sqdmulh {z0.s-z1.s}, {z2.s-z3.s}, z15.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register list
+// CHECK-NEXT: sqdmulh {z0.s-z1.s}, {z2.s-z3.s}, z15.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+sqdmulh {z0.s,z1.s}, {z2.s,z3.s}, z15.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: operand must match destination register list
+// CHECK-NEXT: sqdmulh {z0.s,z1.s}, {z2.s,z3.s}, z15.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+sqdmulh {z0.s,z1.s}, {z0.s,z2.s}, z15.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: registers must be sequential
+// CHECK-NEXT: sqdmulh {z0.s,z1.s}, {z0.s,z2.s}, z15.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+sqdmulh {z0.s,z1.s}, {z0.s,z1.s,z2.s}, z15.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: sqdmulh {z0.s,z1.s}, {z0.s,z1.s,z2.s}, z15.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+sqdmulh {z0.s,z1.s}, {z0.d,z1.d}, z15.s
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: sqdmulh {z0.s,z1.s}, {z0.d,z1.d}, z15.s
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+

llvm/test/MC/AArch64/SME2/sqdmulh.s

+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
+// RUN:        | llvm-objdump -d --mattr=+sme2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
+// RUN:        | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
+// RUN:        | sed '/.text/d' | sed 's/.*encoding: //g' \
+// RUN:        | llvm-mc -triple=aarch64 -mattr=+sme2 -disassemble -show-encoding \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+
+
+sqdmulh {z0.h - z1.h}, {z0.h - z1.h}, z0.h  // 11000001-01100000-10100100-00000000
+// CHECK-INST: sqdmulh { z0.h, z1.h }, { z0.h, z1.h }, z0.h
+// CHECK-ENCODING: [0x00,0xa4,0x60,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c160a400 <unknown>
+
+sqdmulh {z20.h - z21.h}, {z20.h - z21.h}, z5.h  // 11000001-01100101-10100100-00010100
+// CHECK-INST: sqdmulh { z20.h, z21.h }, { z20.h, z21.h }, z5.h
+// CHECK-ENCODING: [0x14,0xa4,0x65,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c165a414 <unknown>
+
+sqdmulh {z22.h - z23.h}, {z22.h - z23.h}, z8.h  // 11000001-01101000-10100100-00010110
+// CHECK-INST: sqdmulh { z22.h, z23.h }, { z22.h, z23.h }, z8.h
+// CHECK-ENCODING: [0x16,0xa4,0x68,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c168a416 <unknown>
+
+sqdmulh {z30.h - z31.h}, {z30.h - z31.h}, z15.h  // 11000001-01101111-10100100-00011110
+// CHECK-INST: sqdmulh { z30.h, z31.h }, { z30.h, z31.h }, z15.h
+// CHECK-ENCODING: [0x1e,0xa4,0x6f,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c16fa41e <unknown>
+
+
+sqdmulh {z0.s - z1.s}, {z0.s - z1.s}, z0.s  // 11000001-10100000-10100100-00000000
+// CHECK-INST: sqdmulh { z0.s, z1.s }, { z0.s, z1.s }, z0.s
+// CHECK-ENCODING: [0x00,0xa4,0xa0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a0a400 <unknown>
+
+sqdmulh {z20.s - z21.s}, {z20.s - z21.s}, z5.s  // 11000001-10100101-10100100-00010100
+// CHECK-INST: sqdmulh { z20.s, z21.s }, { z20.s, z21.s }, z5.s
+// CHECK-ENCODING: [0x14,0xa4,0xa5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a5a414 <unknown>
+
+sqdmulh {z22.s - z23.s}, {z22.s - z23.s}, z8.s  // 11000001-10101000-10100100-00010110
+// CHECK-INST: sqdmulh { z22.s, z23.s }, { z22.s, z23.s }, z8.s
+// CHECK-ENCODING: [0x16,0xa4,0xa8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a8a416 <unknown>
+
+sqdmulh {z30.s - z31.s}, {z30.s - z31.s}, z15.s  // 11000001-10101111-10100100-00011110
+// CHECK-INST: sqdmulh { z30.s, z31.s }, { z30.s, z31.s }, z15.s
+// CHECK-ENCODING: [0x1e,0xa4,0xaf,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1afa41e <unknown>
+
+
+sqdmulh {z0.d - z1.d}, {z0.d - z1.d}, z0.d  // 11000001-11100000-10100100-00000000
+// CHECK-INST: sqdmulh { z0.d, z1.d }, { z0.d, z1.d }, z0.d
+// CHECK-ENCODING: [0x00,0xa4,0xe0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e0a400 <unknown>
+
+sqdmulh {z20.d - z21.d}, {z20.d - z21.d}, z5.d  // 11000001-11100101-10100100-00010100
+// CHECK-INST: sqdmulh { z20.d, z21.d }, { z20.d, z21.d }, z5.d
+// CHECK-ENCODING: [0x14,0xa4,0xe5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e5a414 <unknown>
+
+sqdmulh {z22.d - z23.d}, {z22.d - z23.d}, z8.d  // 11000001-11101000-10100100-00010110
+// CHECK-INST: sqdmulh { z22.d, z23.d }, { z22.d, z23.d }, z8.d
+// CHECK-ENCODING: [0x16,0xa4,0xe8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e8a416 <unknown>
+
+sqdmulh {z30.d - z31.d}, {z30.d - z31.d}, z15.d  // 11000001-11101111-10100100-00011110
+// CHECK-INST: sqdmulh { z30.d, z31.d }, { z30.d, z31.d }, z15.d
+// CHECK-ENCODING: [0x1e,0xa4,0xef,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1efa41e <unknown>
+
+
+sqdmulh {z0.b - z1.b}, {z0.b - z1.b}, z0.b  // 11000001-00100000-10100100-00000000
+// CHECK-INST: sqdmulh { z0.b, z1.b }, { z0.b, z1.b }, z0.b
+// CHECK-ENCODING: [0x00,0xa4,0x20,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c120a400 <unknown>
+
+sqdmulh {z20.b - z21.b}, {z20.b - z21.b}, z5.b  // 11000001-00100101-10100100-00010100
+// CHECK-INST: sqdmulh { z20.b, z21.b }, { z20.b, z21.b }, z5.b
+// CHECK-ENCODING: [0x14,0xa4,0x25,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c125a414 <unknown>
+
+sqdmulh {z22.b - z23.b}, {z22.b - z23.b}, z8.b  // 11000001-00101000-10100100-00010110
+// CHECK-INST: sqdmulh { z22.b, z23.b }, { z22.b, z23.b }, z8.b
+// CHECK-ENCODING: [0x16,0xa4,0x28,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c128a416 <unknown>
+
+sqdmulh {z30.b - z31.b}, {z30.b - z31.b}, z15.b  // 11000001-00101111-10100100-00011110
+// CHECK-INST: sqdmulh { z30.b, z31.b }, { z30.b, z31.b }, z15.b
+// CHECK-ENCODING: [0x1e,0xa4,0x2f,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c12fa41e <unknown>
+
+
+sqdmulh {z0.h - z3.h}, {z0.h - z3.h}, z0.h  // 11000001-01100000-10101100-00000000
+// CHECK-INST: sqdmulh { z0.h - z3.h }, { z0.h - z3.h }, z0.h
+// CHECK-ENCODING: [0x00,0xac,0x60,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c160ac00 <unknown>
+
+sqdmulh {z20.h - z23.h}, {z20.h - z23.h}, z5.h  // 11000001-01100101-10101100-00010100
+// CHECK-INST: sqdmulh { z20.h - z23.h }, { z20.h - z23.h }, z5.h
+// CHECK-ENCODING: [0x14,0xac,0x65,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c165ac14 <unknown>
+
+sqdmulh {z20.h - z23.h}, {z20.h - z23.h}, z8.h  // 11000001-01101000-10101100-00010100
+// CHECK-INST: sqdmulh { z20.h - z23.h }, { z20.h - z23.h }, z8.h
+// CHECK-ENCODING: [0x14,0xac,0x68,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c168ac14 <unknown>
+
+sqdmulh {z28.h - z31.h}, {z28.h - z31.h}, z15.h  // 11000001-01101111-10101100-00011100
+// CHECK-INST: sqdmulh { z28.h - z31.h }, { z28.h - z31.h }, z15.h
+// CHECK-ENCODING: [0x1c,0xac,0x6f,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c16fac1c <unknown>
+
+
+sqdmulh {z0.s - z3.s}, {z0.s - z3.s}, z0.s  // 11000001-10100000-10101100-00000000
+// CHECK-INST: sqdmulh { z0.s - z3.s }, { z0.s - z3.s }, z0.s
+// CHECK-ENCODING: [0x00,0xac,0xa0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a0ac00 <unknown>
+
+sqdmulh {z20.s - z23.s}, {z20.s - z23.s}, z5.s  // 11000001-10100101-10101100-00010100
+// CHECK-INST: sqdmulh { z20.s - z23.s }, { z20.s - z23.s }, z5.s
+// CHECK-ENCODING: [0x14,0xac,0xa5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a5ac14 <unknown>
+
+sqdmulh {z20.s - z23.s}, {z20.s - z23.s}, z8.s  // 11000001-10101000-10101100-00010100
+// CHECK-INST: sqdmulh { z20.s - z23.s }, { z20.s - z23.s }, z8.s
+// CHECK-ENCODING: [0x14,0xac,0xa8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a8ac14 <unknown>
+
+sqdmulh {z28.s - z31.s}, {z28.s - z31.s}, z15.s  // 11000001-10101111-10101100-00011100
+// CHECK-INST: sqdmulh { z28.s - z31.s }, { z28.s - z31.s }, z15.s
+// CHECK-ENCODING: [0x1c,0xac,0xaf,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1afac1c <unknown>
+
+
+sqdmulh {z0.d - z3.d}, {z0.d - z3.d}, z0.d  // 11000001-11100000-10101100-00000000
+// CHECK-INST: sqdmulh { z0.d - z3.d }, { z0.d - z3.d }, z0.d
+// CHECK-ENCODING: [0x00,0xac,0xe0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e0ac00 <unknown>
+
+sqdmulh {z20.d - z23.d}, {z20.d - z23.d}, z5.d  // 11000001-11100101-10101100-00010100
+// CHECK-INST: sqdmulh { z20.d - z23.d }, { z20.d - z23.d }, z5.d
+// CHECK-ENCODING: [0x14,0xac,0xe5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e5ac14 <unknown>
+
+sqdmulh {z20.d - z23.d}, {z20.d - z23.d}, z8.d  // 11000001-11101000-10101100-00010100
+// CHECK-INST: sqdmulh { z20.d - z23.d }, { z20.d - z23.d }, z8.d
+// CHECK-ENCODING: [0x14,0xac,0xe8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e8ac14 <unknown>
+
+sqdmulh {z28.d - z31.d}, {z28.d - z31.d}, z15.d  // 11000001-11101111-10101100-00011100
+// CHECK-INST: sqdmulh { z28.d - z31.d }, { z28.d - z31.d }, z15.d
+// CHECK-ENCODING: [0x1c,0xac,0xef,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1efac1c <unknown>
+
+
+sqdmulh {z0.b - z3.b}, {z0.b - z3.b}, z0.b  // 11000001-00100000-10101100-00000000
+// CHECK-INST: sqdmulh { z0.b - z3.b }, { z0.b - z3.b }, z0.b
+// CHECK-ENCODING: [0x00,0xac,0x20,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c120ac00 <unknown>
+
+sqdmulh {z20.b - z23.b}, {z20.b - z23.b}, z5.b  // 11000001-00100101-10101100-00010100
+// CHECK-INST: sqdmulh { z20.b - z23.b }, { z20.b - z23.b }, z5.b
+// CHECK-ENCODING: [0x14,0xac,0x25,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c125ac14 <unknown>
+
+sqdmulh {z20.b - z23.b}, {z20.b - z23.b}, z8.b  // 11000001-00101000-10101100-00010100
+// CHECK-INST: sqdmulh { z20.b - z23.b }, { z20.b - z23.b }, z8.b
+// CHECK-ENCODING: [0x14,0xac,0x28,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c128ac14 <unknown>
+
+sqdmulh {z28.b - z31.b}, {z28.b - z31.b}, z15.b  // 11000001-00101111-10101100-00011100
+// CHECK-INST: sqdmulh { z28.b - z31.b }, { z28.b - z31.b }, z15.b
+// CHECK-ENCODING: [0x1c,0xac,0x2f,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c12fac1c <unknown>

llvm/utils/TableGen/AsmMatcherEmitter.cpp

static void emitAsmTiedOperandConstraints(CodeGenTarget &Target,
   OS << "      assert(OpIdx < (size_t)(std::end(TiedAsmOperandTable) -\n";
   OS << "                              std::begin(TiedAsmOperandTable)) &&\n";
   OS << "             \"Tied operand not found\");\n";
   OS << "      unsigned OpndNum1 = TiedAsmOperandTable[OpIdx][1];\n";
   OS << "      unsigned OpndNum2 = TiedAsmOperandTable[OpIdx][2];\n";
   OS << "      if (OpndNum1 != OpndNum2) {\n";
   OS << "        auto &SrcOp1 = Operands[OpndNum1];\n";
   OS << "        auto &SrcOp2 = Operands[OpndNum2];\n";
-  OS << "        if (SrcOp1->isReg() && SrcOp2->isReg()) {\n";
-  OS << "          if (!AsmParser.regsEqual(*SrcOp1, *SrcOp2)) {\n";
-  OS << "            ErrorInfo = OpndNum2;\n";
-  OS << "            return false;\n";
-  OS << "          }\n";
-  OS << "        }\n";
-  OS << "      }\n";
+  OS << "        if (!AsmParser.areEqualRegs(*SrcOp1, *SrcOp2)) {\n";
+  OS << "          ErrorInfo = OpndNum2;\n";
+  OS << "          return false;\n";
+  OS << "        }\n";
+  OS << "      }\n";
   OS << "      break;\n";
   OS << "    }\n";
   OS << "    default:\n";
   OS << "      break;\n";
   OS << "    }\n";
   OS << "  }\n";
   OS << "  return true;\n";
   OS << "}\n\n";