This patch adds the assembly/disassembly for the following instruction:
INT:
SDOT (2-way, multiple and single vector): Multi-vector signed integer dot-product by vector.
(2-way, multiple vectors): Multi-vector signed integer dot-product.
UDOT (2-way, multiple and single vector): Multi-vector unsigned integer dot-product by vector.
(2-way, multiple vectors): Multi-vector unsigned integer dot-product.
SUDOT (multiple and indexed vector): Multi-vector signed by unsigned integer dot-product by indexed elements.
(multiple and single vector): Multi-vector signed by unsigned integer dot-product by vector.
USDOT (multiple and single vector): Multi-vector unsigned by signed integer dot-product by vector.
(multiple vectors): Multi-vector unsigned by signed integer dot-product.FP:
BFDOT(multiple and single vector): Multi-vector BFloat16 floating-point dot-product by vector.
(multiple vectors): Multi-vector BFloat16 floating-point dot-product.
FDOT (multiple and single vector): Multi-vector half-precision floating-point dot-product by vector.
(multiple vectors): Multi-vector half-precision floating-point dot-product.For set of 2 and 4 ZA registers
The reference can be found here:
https://developer.arm.com/documentation/ddi0602/2022-09
Depends on:D135455
This to me looks almost identical too sme2_mla_add_sub_array_vg2_multi which makes sense given they share the same encoding parent SME2 Multi-vector - Multiple Array Vectors (Two registers). I think you're focusing too much on trying to share instruction definitions between vg2 and vg4 whereas looking at the encoding groups they typically sit in different tables. This means your having to create far more instruction/base classes than you need to.
I'm not saying everything in SME2 Multi-vector - Multiple Array Vectors (Two registers) can be represented using a single instruction/base class but many take the form ZA.S[<Wv>, <imm>{, VGx2}], { <Zn1>.?-<Zn2>.? }, { <Zm1>.?-<Zm2>.? } and so I'd expect much more reuse than is currently the case.