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Differential D137411

[AArch64][SVE2] Add the SVE2.1 integer quadword reduction instructions
ClosedPublic

Authored by david-arm on Nov 4 2022, 5:05 AM.

Details

Reviewers
sdesmalen
aemerson
paulwalker-arm
CarolineConcatto
kmclaughlin
efriedma
Commits
rG835de8dcf102: [AArch64][SVE2] Add the SVE2.1 integer quadword reduction instructions
Summary

This patch adds the assembly/disassembly for the following instructions:

addqv : Unsigned add reduction of quadword vector segments
andqv : Bitwise AND reduction of quadword vector segments
eorqv : Bitwise exclusive OR reduction of quadword vector segments
orqv : Bitwise inclusive OR reduction of quadword vector segments
smaxqv : Signed maximum reduction of quadword vector segments
sminqv : Signed minimum reduction of quadword vector segments
umaxqv : Unsigned maximum reduction of quadword vector segments
uminqv : Unsigned minimum reduction of quadword vector segments

The reference can be found here:
https://developer.arm.com/documentation/ddi0602/2022-09

Diff Detail

Event Timeline

david-arm created this revision.Nov 4 2022, 5:05 AM
Herald added a reviewer: efriedma. · View Herald TranscriptNov 4 2022, 5:05 AM
Herald added a project: Restricted Project. · View Herald Transcript
Herald added subscribers: hiraditya, kristof.beyls, tschuett. · View Herald Transcript
david-arm requested review of this revision.Nov 4 2022, 5:05 AM
Herald added a project: Restricted Project. · View Herald TranscriptNov 4 2022, 5:05 AM
Herald added a subscriber: llvm-commits. · View Herald Transcript
david-arm added a parent revision: D137410: [AArch64] Add SME2.1 target feature for Armv9-A 2022 Architecture Extension.Nov 4 2022, 5:05 AM
david-arm added a child revision: D137412: [AArch64][SVE2] Add the SVE2.1 add quadword reduction instruction.Nov 4 2022, 5:11 AM
Harbormaster completed remote builds in B196115: Diff 473196.Nov 4 2022, 6:03 AM
paulwalker-arm added inline comments.Nov 4 2022, 7:28 AM
llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
3744

Please add the usual register suffixes, so _VPZ in this case?

llvm/lib/Target/AArch64/SVEInstrFormats.td
9289

Not your fault but this is a shame because otherwise we could just extend sve_int_reduce.

With that said, are you able to follow the same idiom as sve_int_reduce for the QV reductions because your current direction will mean a separate instruction class per type of reduction and I cannot immediately see a need for that.

paulwalker-arm mentioned this in D137412: [AArch64][SVE2] Add the SVE2.1 add quadword reduction instruction.Nov 4 2022, 9:30 AM
paulwalker-arm mentioned this in D137419: [AArch64][SVE2] Add the SVE2.1 FP quadword reduction instructions.
paulwalker-arm mentioned this in D137420: [AArch64][SVE2] Add the SVE2.1 integer quadword min/max reduction instructions.
Matt added a subscriber: Matt.Nov 5 2022, 8:34 PM
david-arm added inline comments.Nov 7 2022, 1:48 AM
llvm/lib/Target/AArch64/SVEInstrFormats.td
9289

Given they are quite different encodings does this really make sense?

These three encoding groups all differ by 3 bits on top of the opc
SVE bitwise logical reduction (quadwords): bits 21-19: 011
SVE integer add reduction (quadwords): bits 21-19: 000
SVE integer min/max reduction (quadwords): bits 21-19: 001

To be honest I'm quite confused by how the existing sve_int_reduce hierarchy is written. For example, what does the _1 in sve_int_reduce_1 mean and how does that relate to the instructions? Is it just a random suffix? Personally, if we have to go down this route I'd prefer something more meaningful than just copying how we've done this before. Would this be ok?

defm EORQV_VPZ : sve2p1_log_int_reduce_q<...>;
...
defm ADDQV_VPZ : sve2p1_arith_int_reduce_q<...>;
...
defm SMAXQV_VPZ : sve2p1_minmax_int_reduce_q<...>;

where the multiclasses look like

multiclass sve2p1_log_int_reduce_q<bits<2> opc, string mnemonic> {

def _B : sve2p1_int_reduction_q<0b00, opc, 0b011, mnemonic, ZPR8,  "16b">;
def _H : sve2p1_int_reduction_q<0b01, opc, 0b011, mnemonic, ZPR16, "8h">;
def _S : sve2p1_int_reduction_q<0b10, opc, 0b011, mnemonic, ZPR32, "4s">;
def _D : sve2p1_int_reduction_q<0b11, opc, 0b011, mnemonic, ZPR64, "2d">;

}

where 0b011 refers to bits 21-19 of the encoding group.

paulwalker-arm added inline comments.Nov 7 2022, 3:01 AM
llvm/lib/Target/AArch64/SVEInstrFormats.td
9289

From what I can see all the quadword reductions (e.g. SMAXQV) differ by a single bit (18) when compared to their equivalent predicated reductions (e.g. SMAXV). Given this I don't see any reason why you should not use the same structure.

In this instance I'm not asking you to reuse any existing classes (that would be amazing but the current parsing of NEON registers precludes it) so I guess I'm just saying you can copy sve_int_reduce as sve_int_reduce_quadwards and then create the three multiclasses as you've described above.

Please go with whatever names you think best. The use of numerical suffixes were an attempt to maintain alignment within AArch64SVEInstrInfo, but there's no requirement for that. I will say the names are somewhat irrelevant though, it's the instruction names that people will be searching for.

david-arm updated this revision to Diff 474227.Nov 9 2022, 4:55 AM
david-arm retitled this revision from [AArch64][SVE2] Add the SVE2.1 logical quadword reduction instructions to [AArch64][SVE2] Add the SVE2.1 integer quadword reduction instructions.
david-arm edited the summary of this revision. (Show Details)
  • Rewrite as a single class to cover all the logical/add/min/max reductions from this patch and D137412, D137420.
david-arm marked 2 inline comments as done.Nov 9 2022, 4:56 AM
david-arm added inline comments.
llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
3744

I just realised I forgot to add the suffixes. I can do that in a follow-up.

paulwalker-arm accepted this revision.Nov 9 2022, 5:48 AM
This revision is now accepted and ready to land.Nov 9 2022, 5:48 AM
paulwalker-arm added inline comments.Nov 9 2022, 5:50 AM
llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td
3744

Thanks @david-arm, please remember to do this before landing the patch.

This revision was landed with ongoing or failed builds.Nov 9 2022, 6:26 AM
Closed by commit rG835de8dcf102: [AArch64][SVE2] Add the SVE2.1 integer quadword reduction instructions (authored by david-arm). · Explain Why
This revision was automatically updated to reflect the committed changes.
david-arm added a commit: rG835de8dcf102: [AArch64][SVE2] Add the SVE2.1 integer quadword reduction instructions.
Harbormaster completed remote builds in B196875: Diff 474227.Nov 9 2022, 6:34 AM

Revision Contents

PathSize
llvm/
lib/
Target/
AArch64/
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29 lines
test/
MC/
AArch64/
SVE2p1/
30 lines
110 lines
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30 lines
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Diff 474254

llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td

Show First 20 Lines • Show All 3,735 Lines • ▼ Show 20 Lines
defm WHILELE_CXX : sve2p1_int_while_rr_pn<"whilele", 0b011>; defm WHILELE_CXX : sve2p1_int_while_rr_pn<"whilele", 0b011>;
defm WHILEHS_CXX : sve2p1_int_while_rr_pn<"whilehs", 0b100>; defm WHILEHS_CXX : sve2p1_int_while_rr_pn<"whilehs", 0b100>;
defm WHILEHI_CXX : sve2p1_int_while_rr_pn<"whilehi", 0b101>; defm WHILEHI_CXX : sve2p1_int_while_rr_pn<"whilehi", 0b101>;
defm WHILELO_CXX : sve2p1_int_while_rr_pn<"whilelo", 0b110>; defm WHILELO_CXX : sve2p1_int_while_rr_pn<"whilelo", 0b110>;
defm WHILELS_CXX : sve2p1_int_while_rr_pn<"whilels", 0b111>; defm WHILELS_CXX : sve2p1_int_while_rr_pn<"whilels", 0b111>;
} // End HasSVE2p1_or_HasSME2 } // End HasSVE2p1_or_HasSME2
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
// SVE2.1 non-widening BFloat16 to BFloat16 instructions // SVE2.1 non-widening BFloat16 to BFloat16 instructions
paulwalker-armUnsubmitted
Not Done
ReplyInline Actions

Please add the usual register suffixes, so _VPZ in this case?

paulwalker-arm: Please add the usual register suffixes, so `_VPZ` in this case?
david-armAuthorUnsubmitted
Done
ReplyInline Actions

I just realised I forgot to add the suffixes. I can do that in a follow-up.

david-arm: I just realised I forgot to add the suffixes. I can do that in a follow-up.
paulwalker-armUnsubmitted
Not Done
ReplyInline Actions

Thanks @david-arm, please remember to do this before landing the patch.

paulwalker-arm: Thanks @david-arm, please remember to do this before landing the patch.
//===----------------------------------------------------------------------===// //===----------------------------------------------------------------------===//
let Predicates = [HasSVE2p1_or_HasSME2p1, HasB16B16] in { let Predicates = [HasSVE2p1_or_HasSME2p1, HasB16B16] in {
def BFADD_ZZZ : sve_fp_3op_u_zd<0b00, 0b000, "bfadd", ZPR16>; def BFADD_ZZZ : sve_fp_3op_u_zd<0b00, 0b000, "bfadd", ZPR16>;
def BFSUB_ZZZ : sve_fp_3op_u_zd<0b00, 0b001, "bfsub", ZPR16>; def BFSUB_ZZZ : sve_fp_3op_u_zd<0b00, 0b001, "bfsub", ZPR16>;
def BFMUL_ZZZ : sve_fp_3op_u_zd<0b00, 0b010, "bfmul", ZPR16>; def BFMUL_ZZZ : sve_fp_3op_u_zd<0b00, 0b010, "bfmul", ZPR16>;
def BFMLA_ZPmZZ : sve_fp_3op_p_zds_a<0b00, 0b00, "bfmla", ZPR16>; def BFMLA_ZPmZZ : sve_fp_3op_p_zds_a<0b00, 0b00, "bfmla", ZPR16>;
Show All 26 Lines
defm FMAXQV : sve2p1_fp_reduction_q<0b110, "fmaxqv">; defm FMAXQV : sve2p1_fp_reduction_q<0b110, "fmaxqv">;
defm FMINQV : sve2p1_fp_reduction_q<0b111, "fminqv">; defm FMINQV : sve2p1_fp_reduction_q<0b111, "fminqv">;
defm DUPQ_ZZI : sve2p1_dupq<"dupq">; defm DUPQ_ZZI : sve2p1_dupq<"dupq">;
def EXTQ_ZZI : sve2p1_extq<"extq">; def EXTQ_ZZI : sve2p1_extq<"extq">;
defm PMOV_PZI : sve2p1_vector_to_pred<"pmov">; defm PMOV_PZI : sve2p1_vector_to_pred<"pmov">;
defm PMOV_ZIP : sve2p1_pred_to_vector<"pmov">; defm PMOV_ZIP : sve2p1_pred_to_vector<"pmov">;
defm ORQV_VPZ : sve2p1_int_reduce_q<0b1100, "orqv">;
defm EORQV_VPZ : sve2p1_int_reduce_q<0b1101, "eorqv">;
defm ANDQV_VPZ : sve2p1_int_reduce_q<0b1110, "andqv">;
defm ADDQV_VPZ : sve2p1_int_reduce_q<0b0001, "addqv">;
defm SMAXQV_VPZ : sve2p1_int_reduce_q<0b0100, "smaxqv">;
defm UMAXQV_VPZ : sve2p1_int_reduce_q<0b0101, "umaxqv">;
defm SMINQV_VPZ : sve2p1_int_reduce_q<0b0110, "sminqv">;
defm UMINQV_VPZ : sve2p1_int_reduce_q<0b0111, "uminqv">;
} // End HasSVE2p1_or_HasSME2p1 } // End HasSVE2p1_or_HasSME2p1

llvm/lib/Target/AArch64/SVEInstrFormats.td

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 9,280 Lines • ▼ Show 20 Lines def : InstAlias<mnemonic # " $Zt, $Pg, [$Zn]",
(!cast<Instruction>(NAME) Z_q:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, XZR), 1>; (!cast<Instruction>(NAME) Z_q:$Zt, PPR3bAny:$Pg, ZPR64:$Zn, XZR), 1>;
} }
// SVE contiguous load (quadwords, scalar plus immediate) // SVE contiguous load (quadwords, scalar plus immediate)
class sve_mem_128b_cld_si<bits<2> dtype, string mnemonic> class sve_mem_128b_cld_si<bits<2> dtype, string mnemonic>
: I<(outs Z_q:$Zt), (ins PPR3bAny:$Pg, GPR64sp:$Rn, simm4s1:$imm4), : I<(outs Z_q:$Zt), (ins PPR3bAny:$Pg, GPR64sp:$Rn, simm4s1:$imm4),
mnemonic, "\t$Zt, $Pg/z, [$Rn, $imm4, mul vl]", mnemonic, "\t$Zt, $Pg/z, [$Rn, $imm4, mul vl]",
"", []>, Sched<[]> { "", []>, Sched<[]> {
paulwalker-armUnsubmitted
Done
ReplyInline Actions

Not your fault but this is a shame because otherwise we could just extend sve_int_reduce.

With that said, are you able to follow the same idiom as sve_int_reduce for the QV reductions because your current direction will mean a separate instruction class per type of reduction and I cannot immediately see a need for that.

paulwalker-arm: Not your fault but this is a shame because otherwise we could just extend `sve_int_reduce`.
david-armAuthorUnsubmitted
Done
ReplyInline Actions

Given they are quite different encodings does this really make sense?

These three encoding groups all differ by 3 bits on top of the opc
SVE bitwise logical reduction (quadwords): bits 21-19: 011
SVE integer add reduction (quadwords): bits 21-19: 000
SVE integer min/max reduction (quadwords): bits 21-19: 001

To be honest I'm quite confused by how the existing sve_int_reduce hierarchy is written. For example, what does the _1 in sve_int_reduce_1 mean and how does that relate to the instructions? Is it just a random suffix? Personally, if we have to go down this route I'd prefer something more meaningful than just copying how we've done this before. Would this be ok?

defm EORQV_VPZ : sve2p1_log_int_reduce_q<...>;
...
defm ADDQV_VPZ : sve2p1_arith_int_reduce_q<...>;
...
defm SMAXQV_VPZ : sve2p1_minmax_int_reduce_q<...>;

where the multiclasses look like

multiclass sve2p1_log_int_reduce_q<bits<2> opc, string mnemonic> {

def _B : sve2p1_int_reduction_q<0b00, opc, 0b011, mnemonic, ZPR8,  "16b">;
def _H : sve2p1_int_reduction_q<0b01, opc, 0b011, mnemonic, ZPR16, "8h">;
def _S : sve2p1_int_reduction_q<0b10, opc, 0b011, mnemonic, ZPR32, "4s">;
def _D : sve2p1_int_reduction_q<0b11, opc, 0b011, mnemonic, ZPR64, "2d">;

}

where 0b011 refers to bits 21-19 of the encoding group.

david-arm: Given they are quite different encodings does this really make sense? These three encoding…
paulwalker-armUnsubmitted
Done
ReplyInline Actions

From what I can see all the quadword reductions (e.g. SMAXQV) differ by a single bit (18) when compared to their equivalent predicated reductions (e.g. SMAXV). Given this I don't see any reason why you should not use the same structure.

In this instance I'm not asking you to reuse any existing classes (that would be amazing but the current parsing of NEON registers precludes it) so I guess I'm just saying you can copy sve_int_reduce as sve_int_reduce_quadwards and then create the three multiclasses as you've described above.

Please go with whatever names you think best. The use of numerical suffixes were an attempt to maintain alignment within AArch64SVEInstrInfo, but there's no requirement for that. I will say the names are somewhat irrelevant though, it's the instruction names that people will be searching for.

paulwalker-arm: From what I can see all the quadword reductions (e.g. SMAXQV) differ by a single bit (18) when…
bits<5> Zt; bits<5> Zt;
bits<5> Rn; bits<5> Rn;
bits<3> Pg; bits<3> Pg;
bits<4> imm4; bits<4> imm4;
let Inst{31-25} = 0b1010010; let Inst{31-25} = 0b1010010;
let Inst{24-23} = dtype; let Inst{24-23} = dtype;
let Inst{22-20} = 0b001; let Inst{22-20} = 0b001;
let Inst{19-16} = imm4; let Inst{19-16} = imm4;
▲ Show 20 Lines • Show All 198 Lines • ▼ Show 20 Lines def _D : sve2p1_pred_to_vector<{1, ?, ?, ?}, mnemonic, PPR64, VectorIndexH32b> {
bits<3> index; bits<3> index;
let Inst{22} = index{2}; let Inst{22} = index{2};
let Inst{18-17} = index{1-0}; let Inst{18-17} = index{1-0};
} }
def : InstAlias<mnemonic # "\t$Zd, $Pn", def : InstAlias<mnemonic # "\t$Zd, $Pn",
(!cast<Instruction>(NAME # _B) ZPRAny:$Zd, 0, PPR8:$Pn), 1>; (!cast<Instruction>(NAME # _B) ZPRAny:$Zd, 0, PPR8:$Pn), 1>;
} }
// SVE bitwise logical/add/min/max reductions (quadwords)
class sve2p1_int_reduce_q<bits<2> sz, bits<4> opc, string mnemonic,
RegisterOperand zpr_ty, string vec_sfx>
: I<(outs V128:$Vd), (ins PPR3bAny:$Pg, zpr_ty:$Zn),
mnemonic, "\t$Vd." # vec_sfx # ", $Pg, $Zn",
"", []>, Sched<[]> {
bits<5> Vd;
bits<5> Zn;
bits<3> Pg;
let Inst{31-24} = 0b00000100;
let Inst{23-22} = sz;
let Inst{21} = 0b0;
let Inst{20-19} = opc{3-2};
let Inst{18} = 0b1;
let Inst{17-16} = opc{1-0};
let Inst{15-13} = 0b001;
let Inst{12-10} = Pg;
let Inst{9-5} = Zn;
let Inst{4-0} = Vd;
}
multiclass sve2p1_int_reduce_q<bits<4> opc, string mnemonic> {
def _B : sve2p1_int_reduce_q<0b00, opc, mnemonic, ZPR8, "16b">;
def _H : sve2p1_int_reduce_q<0b01, opc, mnemonic, ZPR16, "8h">;
def _S : sve2p1_int_reduce_q<0b10, opc, mnemonic, ZPR32, "4s">;
def _D : sve2p1_int_reduce_q<0b11, opc, mnemonic, ZPR64, "2d">;
}

llvm/test/MC/AArch64/SVE2p1/addqv-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p1 2>&1 < %s | FileCheck %s
// --------------------------------------------------------------------------//
// Invalid predicate register
addqv v0.2d, p11, z0.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: addqv v0.2d, p11, z0.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Invalid vector register
addqv v0.4h, p1, z0.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: addqv v0.4h, p1, z0.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
addqv z1.s, p1, z0.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: addqv z1.s, p1, z0.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Invalid vector suffix
addqv v0.8h, p1, z0.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: addqv v0.8h, p1, z0.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/test/MC/AArch64/SVE2p1/addqv.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p1 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p1 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2p1 < %s \
// RUN: | llvm-objdump -d --mattr=+sme2p1 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2p1 < %s \
// RUN: | llvm-objdump -d --mattr=-sme2p1,-sve2p1 - | FileCheck %s --check-prefix=CHECK-UNKNOWN
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p1 < %s \
// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
// RUN: | llvm-mc -triple=aarch64 -mattr=+sme2p1 -disassemble -show-encoding \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
addqv v0.8h, p0, z0.h // 00000100-01000101-00100000-00000000
// CHECK-INST: addqv v0.8h, p0, z0.h
// CHECK-ENCODING: [0x00,0x20,0x45,0x04]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 04452000 <unknown>
addqv v21.8h, p5, z10.h // 00000100-01000101-00110101-01010101
// CHECK-INST: addqv v21.8h, p5, z10.h
// CHECK-ENCODING: [0x55,0x35,0x45,0x04]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 04453555 <unknown>
addqv v23.8h, p3, z13.h // 00000100-01000101-00101101-10110111
// CHECK-INST: addqv v23.8h, p3, z13.h
// CHECK-ENCODING: [0xb7,0x2d,0x45,0x04]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 04452db7 <unknown>
addqv v31.8h, p7, z31.h // 00000100-01000101-00111111-11111111
// CHECK-INST: addqv v31.8h, p7, z31.h
// CHECK-ENCODING: [0xff,0x3f,0x45,0x04]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 04453fff <unknown>
addqv v0.4s, p0, z0.s // 00000100-10000101-00100000-00000000
// CHECK-INST: addqv v0.4s, p0, z0.s
// CHECK-ENCODING: [0x00,0x20,0x85,0x04]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 04852000 <unknown>
addqv v21.4s, p5, z10.s // 00000100-10000101-00110101-01010101
// CHECK-INST: addqv v21.4s, p5, z10.s
// CHECK-ENCODING: [0x55,0x35,0x85,0x04]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 04853555 <unknown>
addqv v23.4s, p3, z13.s // 00000100-10000101-00101101-10110111
// CHECK-INST: addqv v23.4s, p3, z13.s
// CHECK-ENCODING: [0xb7,0x2d,0x85,0x04]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 04852db7 <unknown>
addqv v31.4s, p7, z31.s // 00000100-10000101-00111111-11111111
// CHECK-INST: addqv v31.4s, p7, z31.s
// CHECK-ENCODING: [0xff,0x3f,0x85,0x04]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 04853fff <unknown>
addqv v0.2d, p0, z0.d // 00000100-11000101-00100000-00000000
// CHECK-INST: addqv v0.2d, p0, z0.d
// CHECK-ENCODING: [0x00,0x20,0xc5,0x04]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 04c52000 <unknown>
addqv v21.2d, p5, z10.d // 00000100-11000101-00110101-01010101
// CHECK-INST: addqv v21.2d, p5, z10.d
// CHECK-ENCODING: [0x55,0x35,0xc5,0x04]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 04c53555 <unknown>
addqv v23.2d, p3, z13.d // 00000100-11000101-00101101-10110111
// CHECK-INST: addqv v23.2d, p3, z13.d
// CHECK-ENCODING: [0xb7,0x2d,0xc5,0x04]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 04c52db7 <unknown>
addqv v31.2d, p7, z31.d // 00000100-11000101-00111111-11111111
// CHECK-INST: addqv v31.2d, p7, z31.d
// CHECK-ENCODING: [0xff,0x3f,0xc5,0x04]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 04c53fff <unknown>
addqv v0.16b, p0, z0.b // 00000100-00000101-00100000-00000000
// CHECK-INST: addqv v0.16b, p0, z0.b
// CHECK-ENCODING: [0x00,0x20,0x05,0x04]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 04052000 <unknown>
addqv v21.16b, p5, z10.b // 00000100-00000101-00110101-01010101
// CHECK-INST: addqv v21.16b, p5, z10.b
// CHECK-ENCODING: [0x55,0x35,0x05,0x04]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 04053555 <unknown>
addqv v23.16b, p3, z13.b // 00000100-00000101-00101101-10110111
// CHECK-INST: addqv v23.16b, p3, z13.b
// CHECK-ENCODING: [0xb7,0x2d,0x05,0x04]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 04052db7 <unknown>
addqv v31.16b, p7, z31.b // 00000100-00000101-00111111-11111111
// CHECK-INST: addqv v31.16b, p7, z31.b
// CHECK-ENCODING: [0xff,0x3f,0x05,0x04]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 04053fff <unknown>

llvm/test/MC/AArch64/SVE2p1/andqv-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p1 2>&1 < %s | FileCheck %s
// --------------------------------------------------------------------------//
// Invalid predicate register
andqv v0.2d, p11, z0.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: andqv v0.2d, p11, z0.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Invalid vector register
andqv v0.4h, p1, z0.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: andqv v0.4h, p1, z0.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
andqv z1.s, p1, z0.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: andqv z1.s, p1, z0.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Invalid vector suffix
andqv v0.8h, p1, z0.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: andqv v0.8h, p1, z0.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/test/MC/AArch64/SVE2p1/andqv.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p1 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p1 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2p1 < %s \
// RUN: | llvm-objdump -d --mattr=+sme2p1 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2p1 < %s \
// RUN: | llvm-objdump -d --mattr=-sme2p1,-sve2p1 - | FileCheck %s --check-prefix=CHECK-UNKNOWN
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p1 < %s \
// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
// RUN: | llvm-mc -triple=aarch64 -mattr=+sme2p1 -disassemble -show-encoding \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
andqv v0.8h, p0, z0.h // 00000100-01011110-00100000-00000000
// CHECK-INST: andqv v0.8h, p0, z0.h
// CHECK-ENCODING: [0x00,0x20,0x5e,0x04]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 045e2000 <unknown>
andqv v21.8h, p5, z10.h // 00000100-01011110-00110101-01010101
// CHECK-INST: andqv v21.8h, p5, z10.h
// CHECK-ENCODING: [0x55,0x35,0x5e,0x04]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 045e3555 <unknown>
andqv v23.8h, p3, z13.h // 00000100-01011110-00101101-10110111
// CHECK-INST: andqv v23.8h, p3, z13.h
// CHECK-ENCODING: [0xb7,0x2d,0x5e,0x04]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 045e2db7 <unknown>
andqv v31.8h, p7, z31.h // 00000100-01011110-00111111-11111111
// CHECK-INST: andqv v31.8h, p7, z31.h
// CHECK-ENCODING: [0xff,0x3f,0x5e,0x04]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 045e3fff <unknown>
andqv v0.4s, p0, z0.s // 00000100-10011110-00100000-00000000
// CHECK-INST: andqv v0.4s, p0, z0.s
// CHECK-ENCODING: [0x00,0x20,0x9e,0x04]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 049e2000 <unknown>
andqv v21.4s, p5, z10.s // 00000100-10011110-00110101-01010101
// CHECK-INST: andqv v21.4s, p5, z10.s
// CHECK-ENCODING: [0x55,0x35,0x9e,0x04]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 049e3555 <unknown>
andqv v23.4s, p3, z13.s // 00000100-10011110-00101101-10110111
// CHECK-INST: andqv v23.4s, p3, z13.s
// CHECK-ENCODING: [0xb7,0x2d,0x9e,0x04]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 049e2db7 <unknown>
andqv v31.4s, p7, z31.s // 00000100-10011110-00111111-11111111
// CHECK-INST: andqv v31.4s, p7, z31.s
// CHECK-ENCODING: [0xff,0x3f,0x9e,0x04]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 049e3fff <unknown>
andqv v0.2d, p0, z0.d // 00000100-11011110-00100000-00000000
// CHECK-INST: andqv v0.2d, p0, z0.d
// CHECK-ENCODING: [0x00,0x20,0xde,0x04]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 04de2000 <unknown>
andqv v21.2d, p5, z10.d // 00000100-11011110-00110101-01010101
// CHECK-INST: andqv v21.2d, p5, z10.d
// CHECK-ENCODING: [0x55,0x35,0xde,0x04]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 04de3555 <unknown>
andqv v23.2d, p3, z13.d // 00000100-11011110-00101101-10110111
// CHECK-INST: andqv v23.2d, p3, z13.d
// CHECK-ENCODING: [0xb7,0x2d,0xde,0x04]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 04de2db7 <unknown>
andqv v31.2d, p7, z31.d // 00000100-11011110-00111111-11111111
// CHECK-INST: andqv v31.2d, p7, z31.d
// CHECK-ENCODING: [0xff,0x3f,0xde,0x04]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 04de3fff <unknown>
andqv v0.16b, p0, z0.b // 00000100-00011110-00100000-00000000
// CHECK-INST: andqv v0.16b, p0, z0.b
// CHECK-ENCODING: [0x00,0x20,0x1e,0x04]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 041e2000 <unknown>
andqv v21.16b, p5, z10.b // 00000100-00011110-00110101-01010101
// CHECK-INST: andqv v21.16b, p5, z10.b
// CHECK-ENCODING: [0x55,0x35,0x1e,0x04]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 041e3555 <unknown>
andqv v23.16b, p3, z13.b // 00000100-00011110-00101101-10110111
// CHECK-INST: andqv v23.16b, p3, z13.b
// CHECK-ENCODING: [0xb7,0x2d,0x1e,0x04]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 041e2db7 <unknown>
andqv v31.16b, p7, z31.b // 00000100-00011110-00111111-11111111
// CHECK-INST: andqv v31.16b, p7, z31.b
// CHECK-ENCODING: [0xff,0x3f,0x1e,0x04]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 041e3fff <unknown>

llvm/test/MC/AArch64/SVE2p1/eorqv-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p1 2>&1 < %s | FileCheck %s
// --------------------------------------------------------------------------//
// Invalid predicate register
eorqv v0.2d, p11, z0.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: eorqv v0.2d, p11, z0.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Invalid vector register
eorqv v0.4h, p1, z0.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: eorqv v0.4h, p1, z0.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
eorqv z1.s, p1, z0.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: eorqv z1.s, p1, z0.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Invalid vector suffix
eorqv v0.8h, p1, z0.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: eorqv v0.8h, p1, z0.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/test/MC/AArch64/SVE2p1/eorqv.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p1 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p1 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2p1 < %s \
// RUN: | llvm-objdump -d --mattr=+sme2p1 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2p1 < %s \
// RUN: | llvm-objdump -d --mattr=-sme2p1,-sve2p1 - | FileCheck %s --check-prefix=CHECK-UNKNOWN
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p1 < %s \
// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
// RUN: | llvm-mc -triple=aarch64 -mattr=+sme2p1 -disassemble -show-encoding \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
eorqv v0.8h, p0, z0.h // 00000100-01011101-00100000-00000000
// CHECK-INST: eorqv v0.8h, p0, z0.h
// CHECK-ENCODING: [0x00,0x20,0x5d,0x04]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 045d2000 <unknown>
eorqv v21.8h, p5, z10.h // 00000100-01011101-00110101-01010101
// CHECK-INST: eorqv v21.8h, p5, z10.h
// CHECK-ENCODING: [0x55,0x35,0x5d,0x04]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 045d3555 <unknown>
eorqv v23.8h, p3, z13.h // 00000100-01011101-00101101-10110111
// CHECK-INST: eorqv v23.8h, p3, z13.h
// CHECK-ENCODING: [0xb7,0x2d,0x5d,0x04]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 045d2db7 <unknown>
eorqv v31.8h, p7, z31.h // 00000100-01011101-00111111-11111111
// CHECK-INST: eorqv v31.8h, p7, z31.h
// CHECK-ENCODING: [0xff,0x3f,0x5d,0x04]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 045d3fff <unknown>
eorqv v0.4s, p0, z0.s // 00000100-10011101-00100000-00000000
// CHECK-INST: eorqv v0.4s, p0, z0.s
// CHECK-ENCODING: [0x00,0x20,0x9d,0x04]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 049d2000 <unknown>
eorqv v21.4s, p5, z10.s // 00000100-10011101-00110101-01010101
// CHECK-INST: eorqv v21.4s, p5, z10.s
// CHECK-ENCODING: [0x55,0x35,0x9d,0x04]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 049d3555 <unknown>
eorqv v23.4s, p3, z13.s // 00000100-10011101-00101101-10110111
// CHECK-INST: eorqv v23.4s, p3, z13.s
// CHECK-ENCODING: [0xb7,0x2d,0x9d,0x04]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 049d2db7 <unknown>
eorqv v31.4s, p7, z31.s // 00000100-10011101-00111111-11111111
// CHECK-INST: eorqv v31.4s, p7, z31.s
// CHECK-ENCODING: [0xff,0x3f,0x9d,0x04]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 049d3fff <unknown>
eorqv v0.2d, p0, z0.d // 00000100-11011101-00100000-00000000
// CHECK-INST: eorqv v0.2d, p0, z0.d
// CHECK-ENCODING: [0x00,0x20,0xdd,0x04]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 04dd2000 <unknown>
eorqv v21.2d, p5, z10.d // 00000100-11011101-00110101-01010101
// CHECK-INST: eorqv v21.2d, p5, z10.d
// CHECK-ENCODING: [0x55,0x35,0xdd,0x04]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 04dd3555 <unknown>
eorqv v23.2d, p3, z13.d // 00000100-11011101-00101101-10110111
// CHECK-INST: eorqv v23.2d, p3, z13.d
// CHECK-ENCODING: [0xb7,0x2d,0xdd,0x04]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 04dd2db7 <unknown>
eorqv v31.2d, p7, z31.d // 00000100-11011101-00111111-11111111
// CHECK-INST: eorqv v31.2d, p7, z31.d
// CHECK-ENCODING: [0xff,0x3f,0xdd,0x04]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 04dd3fff <unknown>
eorqv v0.16b, p0, z0.b // 00000100-00011101-00100000-00000000
// CHECK-INST: eorqv v0.16b, p0, z0.b
// CHECK-ENCODING: [0x00,0x20,0x1d,0x04]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 041d2000 <unknown>
eorqv v21.16b, p5, z10.b // 00000100-00011101-00110101-01010101
// CHECK-INST: eorqv v21.16b, p5, z10.b
// CHECK-ENCODING: [0x55,0x35,0x1d,0x04]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 041d3555 <unknown>
eorqv v23.16b, p3, z13.b // 00000100-00011101-00101101-10110111
// CHECK-INST: eorqv v23.16b, p3, z13.b
// CHECK-ENCODING: [0xb7,0x2d,0x1d,0x04]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 041d2db7 <unknown>
eorqv v31.16b, p7, z31.b // 00000100-00011101-00111111-11111111
// CHECK-INST: eorqv v31.16b, p7, z31.b
// CHECK-ENCODING: [0xff,0x3f,0x1d,0x04]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 041d3fff <unknown>

llvm/test/MC/AArch64/SVE2p1/orqv-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p1 2>&1 < %s | FileCheck %s
// --------------------------------------------------------------------------//
// Invalid predicate register
orqv v0.2d, p11, z0.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: orqv v0.2d, p11, z0.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Invalid vector register
orqv v0.4h, p1, z0.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: orqv v0.4h, p1, z0.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
orqv z1.s, p1, z0.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: orqv z1.s, p1, z0.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Invalid vector suffix
orqv v0.8h, p1, z0.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: orqv v0.8h, p1, z0.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/test/MC/AArch64/SVE2p1/orqv.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p1 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p1 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2p1 < %s \
// RUN: | llvm-objdump -d --mattr=+sme2p1 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2p1 < %s \
// RUN: | llvm-objdump -d --mattr=-sme2p1,-sve2p1 - | FileCheck %s --check-prefix=CHECK-UNKNOWN
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p1 < %s \
// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
// RUN: | llvm-mc -triple=aarch64 -mattr=+sme2p1 -disassemble -show-encoding \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
orqv v0.8h, p0, z0.h // 00000100-01011100-00100000-00000000
// CHECK-INST: orqv v0.8h, p0, z0.h
// CHECK-ENCODING: [0x00,0x20,0x5c,0x04]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 045c2000 <unknown>
orqv v21.8h, p5, z10.h // 00000100-01011100-00110101-01010101
// CHECK-INST: orqv v21.8h, p5, z10.h
// CHECK-ENCODING: [0x55,0x35,0x5c,0x04]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 045c3555 <unknown>
orqv v23.8h, p3, z13.h // 00000100-01011100-00101101-10110111
// CHECK-INST: orqv v23.8h, p3, z13.h
// CHECK-ENCODING: [0xb7,0x2d,0x5c,0x04]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 045c2db7 <unknown>
orqv v31.8h, p7, z31.h // 00000100-01011100-00111111-11111111
// CHECK-INST: orqv v31.8h, p7, z31.h
// CHECK-ENCODING: [0xff,0x3f,0x5c,0x04]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 045c3fff <unknown>
orqv v0.4s, p0, z0.s // 00000100-10011100-00100000-00000000
// CHECK-INST: orqv v0.4s, p0, z0.s
// CHECK-ENCODING: [0x00,0x20,0x9c,0x04]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 049c2000 <unknown>
orqv v21.4s, p5, z10.s // 00000100-10011100-00110101-01010101
// CHECK-INST: orqv v21.4s, p5, z10.s
// CHECK-ENCODING: [0x55,0x35,0x9c,0x04]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 049c3555 <unknown>
orqv v23.4s, p3, z13.s // 00000100-10011100-00101101-10110111
// CHECK-INST: orqv v23.4s, p3, z13.s
// CHECK-ENCODING: [0xb7,0x2d,0x9c,0x04]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 049c2db7 <unknown>
orqv v31.4s, p7, z31.s // 00000100-10011100-00111111-11111111
// CHECK-INST: orqv v31.4s, p7, z31.s
// CHECK-ENCODING: [0xff,0x3f,0x9c,0x04]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 049c3fff <unknown>
orqv v0.2d, p0, z0.d // 00000100-11011100-00100000-00000000
// CHECK-INST: orqv v0.2d, p0, z0.d
// CHECK-ENCODING: [0x00,0x20,0xdc,0x04]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 04dc2000 <unknown>
orqv v21.2d, p5, z10.d // 00000100-11011100-00110101-01010101
// CHECK-INST: orqv v21.2d, p5, z10.d
// CHECK-ENCODING: [0x55,0x35,0xdc,0x04]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 04dc3555 <unknown>
orqv v23.2d, p3, z13.d // 00000100-11011100-00101101-10110111
// CHECK-INST: orqv v23.2d, p3, z13.d
// CHECK-ENCODING: [0xb7,0x2d,0xdc,0x04]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 04dc2db7 <unknown>
orqv v31.2d, p7, z31.d // 00000100-11011100-00111111-11111111
// CHECK-INST: orqv v31.2d, p7, z31.d
// CHECK-ENCODING: [0xff,0x3f,0xdc,0x04]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 04dc3fff <unknown>
orqv v0.16b, p0, z0.b // 00000100-00011100-00100000-00000000
// CHECK-INST: orqv v0.16b, p0, z0.b
// CHECK-ENCODING: [0x00,0x20,0x1c,0x04]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 041c2000 <unknown>
orqv v21.16b, p5, z10.b // 00000100-00011100-00110101-01010101
// CHECK-INST: orqv v21.16b, p5, z10.b
// CHECK-ENCODING: [0x55,0x35,0x1c,0x04]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 041c3555 <unknown>
orqv v23.16b, p3, z13.b // 00000100-00011100-00101101-10110111
// CHECK-INST: orqv v23.16b, p3, z13.b
// CHECK-ENCODING: [0xb7,0x2d,0x1c,0x04]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 041c2db7 <unknown>
orqv v31.16b, p7, z31.b // 00000100-00011100-00111111-11111111
// CHECK-INST: orqv v31.16b, p7, z31.b
// CHECK-ENCODING: [0xff,0x3f,0x1c,0x04]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 041c3fff <unknown>

llvm/test/MC/AArch64/SVE2p1/smaxqv-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p1 2>&1 < %s | FileCheck %s
// --------------------------------------------------------------------------//
// Invalid predicate register
smaxqv v0.2d, p11, z0.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: smaxqv v0.2d, p11, z0.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Invalid vector register
smaxqv v0.4h, p1, z0.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: smaxqv v0.4h, p1, z0.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
smaxqv z1.s, p1, z0.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: smaxqv z1.s, p1, z0.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Invalid vector suffix
smaxqv v0.8h, p1, z0.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: smaxqv v0.8h, p1, z0.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/test/MC/AArch64/SVE2p1/smaxqv.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p1 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p1 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2p1 < %s \
// RUN: | llvm-objdump -d --mattr=+sme2p1 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2p1 < %s \
// RUN: | llvm-objdump -d --mattr=-sme2p1,-sve2p1 - | FileCheck %s --check-prefix=CHECK-UNKNOWN
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p1 < %s \
// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
// RUN: | llvm-mc -triple=aarch64 -mattr=+sme2p1 -disassemble -show-encoding \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
smaxqv v0.8h, p0, z0.h // 00000100-01001100-00100000-00000000
// CHECK-INST: smaxqv v0.8h, p0, z0.h
// CHECK-ENCODING: [0x00,0x20,0x4c,0x04]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 044c2000 <unknown>
smaxqv v21.8h, p5, z10.h // 00000100-01001100-00110101-01010101
// CHECK-INST: smaxqv v21.8h, p5, z10.h
// CHECK-ENCODING: [0x55,0x35,0x4c,0x04]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 044c3555 <unknown>
smaxqv v23.8h, p3, z13.h // 00000100-01001100-00101101-10110111
// CHECK-INST: smaxqv v23.8h, p3, z13.h
// CHECK-ENCODING: [0xb7,0x2d,0x4c,0x04]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 044c2db7 <unknown>
smaxqv v31.8h, p7, z31.h // 00000100-01001100-00111111-11111111
// CHECK-INST: smaxqv v31.8h, p7, z31.h
// CHECK-ENCODING: [0xff,0x3f,0x4c,0x04]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 044c3fff <unknown>
smaxqv v0.4s, p0, z0.s // 00000100-10001100-00100000-00000000
// CHECK-INST: smaxqv v0.4s, p0, z0.s
// CHECK-ENCODING: [0x00,0x20,0x8c,0x04]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 048c2000 <unknown>
smaxqv v21.4s, p5, z10.s // 00000100-10001100-00110101-01010101
// CHECK-INST: smaxqv v21.4s, p5, z10.s
// CHECK-ENCODING: [0x55,0x35,0x8c,0x04]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 048c3555 <unknown>
smaxqv v23.4s, p3, z13.s // 00000100-10001100-00101101-10110111
// CHECK-INST: smaxqv v23.4s, p3, z13.s
// CHECK-ENCODING: [0xb7,0x2d,0x8c,0x04]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 048c2db7 <unknown>
smaxqv v31.4s, p7, z31.s // 00000100-10001100-00111111-11111111
// CHECK-INST: smaxqv v31.4s, p7, z31.s
// CHECK-ENCODING: [0xff,0x3f,0x8c,0x04]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 048c3fff <unknown>
smaxqv v0.2d, p0, z0.d // 00000100-11001100-00100000-00000000
// CHECK-INST: smaxqv v0.2d, p0, z0.d
// CHECK-ENCODING: [0x00,0x20,0xcc,0x04]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 04cc2000 <unknown>
smaxqv v21.2d, p5, z10.d // 00000100-11001100-00110101-01010101
// CHECK-INST: smaxqv v21.2d, p5, z10.d
// CHECK-ENCODING: [0x55,0x35,0xcc,0x04]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 04cc3555 <unknown>
smaxqv v23.2d, p3, z13.d // 00000100-11001100-00101101-10110111
// CHECK-INST: smaxqv v23.2d, p3, z13.d
// CHECK-ENCODING: [0xb7,0x2d,0xcc,0x04]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 04cc2db7 <unknown>
smaxqv v31.2d, p7, z31.d // 00000100-11001100-00111111-11111111
// CHECK-INST: smaxqv v31.2d, p7, z31.d
// CHECK-ENCODING: [0xff,0x3f,0xcc,0x04]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 04cc3fff <unknown>
smaxqv v0.16b, p0, z0.b // 00000100-00001100-00100000-00000000
// CHECK-INST: smaxqv v0.16b, p0, z0.b
// CHECK-ENCODING: [0x00,0x20,0x0c,0x04]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 040c2000 <unknown>
smaxqv v21.16b, p5, z10.b // 00000100-00001100-00110101-01010101
// CHECK-INST: smaxqv v21.16b, p5, z10.b
// CHECK-ENCODING: [0x55,0x35,0x0c,0x04]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 040c3555 <unknown>
smaxqv v23.16b, p3, z13.b // 00000100-00001100-00101101-10110111
// CHECK-INST: smaxqv v23.16b, p3, z13.b
// CHECK-ENCODING: [0xb7,0x2d,0x0c,0x04]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 040c2db7 <unknown>
smaxqv v31.16b, p7, z31.b // 00000100-00001100-00111111-11111111
// CHECK-INST: smaxqv v31.16b, p7, z31.b
// CHECK-ENCODING: [0xff,0x3f,0x0c,0x04]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 040c3fff <unknown>

llvm/test/MC/AArch64/SVE2p1/sminqv-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p1 2>&1 < %s | FileCheck %s
// --------------------------------------------------------------------------//
// Invalid predicate register
sminqv v0.2d, p11, z0.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: sminqv v0.2d, p11, z0.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Invalid vector register
sminqv v0.4h, p1, z0.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: sminqv v0.4h, p1, z0.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
sminqv z1.s, p1, z0.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: sminqv z1.s, p1, z0.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Invalid vector suffix
sminqv v0.8h, p1, z0.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: sminqv v0.8h, p1, z0.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/test/MC/AArch64/SVE2p1/sminqv.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p1 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p1 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2p1 < %s \
// RUN: | llvm-objdump -d --mattr=+sme2p1 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2p1 < %s \
// RUN: | llvm-objdump -d --mattr=-sme2p1,-sve2p1 - | FileCheck %s --check-prefix=CHECK-UNKNOWN
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p1 < %s \
// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
// RUN: | llvm-mc -triple=aarch64 -mattr=+sme2p1 -disassemble -show-encoding \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
sminqv v0.8h, p0, z0.h // 00000100-01001110-00100000-00000000
// CHECK-INST: sminqv v0.8h, p0, z0.h
// CHECK-ENCODING: [0x00,0x20,0x4e,0x04]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 044e2000 <unknown>
sminqv v21.8h, p5, z10.h // 00000100-01001110-00110101-01010101
// CHECK-INST: sminqv v21.8h, p5, z10.h
// CHECK-ENCODING: [0x55,0x35,0x4e,0x04]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 044e3555 <unknown>
sminqv v23.8h, p3, z13.h // 00000100-01001110-00101101-10110111
// CHECK-INST: sminqv v23.8h, p3, z13.h
// CHECK-ENCODING: [0xb7,0x2d,0x4e,0x04]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 044e2db7 <unknown>
sminqv v31.8h, p7, z31.h // 00000100-01001110-00111111-11111111
// CHECK-INST: sminqv v31.8h, p7, z31.h
// CHECK-ENCODING: [0xff,0x3f,0x4e,0x04]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 044e3fff <unknown>
sminqv v0.4s, p0, z0.s // 00000100-10001110-00100000-00000000
// CHECK-INST: sminqv v0.4s, p0, z0.s
// CHECK-ENCODING: [0x00,0x20,0x8e,0x04]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 048e2000 <unknown>
sminqv v21.4s, p5, z10.s // 00000100-10001110-00110101-01010101
// CHECK-INST: sminqv v21.4s, p5, z10.s
// CHECK-ENCODING: [0x55,0x35,0x8e,0x04]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 048e3555 <unknown>
sminqv v23.4s, p3, z13.s // 00000100-10001110-00101101-10110111
// CHECK-INST: sminqv v23.4s, p3, z13.s
// CHECK-ENCODING: [0xb7,0x2d,0x8e,0x04]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 048e2db7 <unknown>
sminqv v31.4s, p7, z31.s // 00000100-10001110-00111111-11111111
// CHECK-INST: sminqv v31.4s, p7, z31.s
// CHECK-ENCODING: [0xff,0x3f,0x8e,0x04]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 048e3fff <unknown>
sminqv v0.2d, p0, z0.d // 00000100-11001110-00100000-00000000
// CHECK-INST: sminqv v0.2d, p0, z0.d
// CHECK-ENCODING: [0x00,0x20,0xce,0x04]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 04ce2000 <unknown>
sminqv v21.2d, p5, z10.d // 00000100-11001110-00110101-01010101
// CHECK-INST: sminqv v21.2d, p5, z10.d
// CHECK-ENCODING: [0x55,0x35,0xce,0x04]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 04ce3555 <unknown>
sminqv v23.2d, p3, z13.d // 00000100-11001110-00101101-10110111
// CHECK-INST: sminqv v23.2d, p3, z13.d
// CHECK-ENCODING: [0xb7,0x2d,0xce,0x04]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 04ce2db7 <unknown>
sminqv v31.2d, p7, z31.d // 00000100-11001110-00111111-11111111
// CHECK-INST: sminqv v31.2d, p7, z31.d
// CHECK-ENCODING: [0xff,0x3f,0xce,0x04]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 04ce3fff <unknown>
sminqv v0.16b, p0, z0.b // 00000100-00001110-00100000-00000000
// CHECK-INST: sminqv v0.16b, p0, z0.b
// CHECK-ENCODING: [0x00,0x20,0x0e,0x04]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 040e2000 <unknown>
sminqv v21.16b, p5, z10.b // 00000100-00001110-00110101-01010101
// CHECK-INST: sminqv v21.16b, p5, z10.b
// CHECK-ENCODING: [0x55,0x35,0x0e,0x04]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 040e3555 <unknown>
sminqv v23.16b, p3, z13.b // 00000100-00001110-00101101-10110111
// CHECK-INST: sminqv v23.16b, p3, z13.b
// CHECK-ENCODING: [0xb7,0x2d,0x0e,0x04]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 040e2db7 <unknown>
sminqv v31.16b, p7, z31.b // 00000100-00001110-00111111-11111111
// CHECK-INST: sminqv v31.16b, p7, z31.b
// CHECK-ENCODING: [0xff,0x3f,0x0e,0x04]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 040e3fff <unknown>

llvm/test/MC/AArch64/SVE2p1/umaxqv-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p1 2>&1 < %s | FileCheck %s
// --------------------------------------------------------------------------//
// Invalid predicate register
umaxqv v0.2d, p11, z0.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: umaxqv v0.2d, p11, z0.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Invalid vector register
umaxqv v0.4h, p1, z0.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: umaxqv v0.4h, p1, z0.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
umaxqv z1.s, p1, z0.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: umaxqv z1.s, p1, z0.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Invalid vector suffix
umaxqv v0.8h, p1, z0.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: umaxqv v0.8h, p1, z0.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/test/MC/AArch64/SVE2p1/umaxqv.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p1 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p1 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2p1 < %s \
// RUN: | llvm-objdump -d --mattr=+sme2p1 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2p1 < %s \
// RUN: | llvm-objdump -d --mattr=-sme2p1,-sve2p1 - | FileCheck %s --check-prefix=CHECK-UNKNOWN
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p1 < %s \
// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
// RUN: | llvm-mc -triple=aarch64 -mattr=+sme2p1 -disassemble -show-encoding \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
umaxqv v0.8h, p0, z0.h // 00000100-01001101-00100000-00000000
// CHECK-INST: umaxqv v0.8h, p0, z0.h
// CHECK-ENCODING: [0x00,0x20,0x4d,0x04]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 044d2000 <unknown>
umaxqv v21.8h, p5, z10.h // 00000100-01001101-00110101-01010101
// CHECK-INST: umaxqv v21.8h, p5, z10.h
// CHECK-ENCODING: [0x55,0x35,0x4d,0x04]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 044d3555 <unknown>
umaxqv v23.8h, p3, z13.h // 00000100-01001101-00101101-10110111
// CHECK-INST: umaxqv v23.8h, p3, z13.h
// CHECK-ENCODING: [0xb7,0x2d,0x4d,0x04]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 044d2db7 <unknown>
umaxqv v31.8h, p7, z31.h // 00000100-01001101-00111111-11111111
// CHECK-INST: umaxqv v31.8h, p7, z31.h
// CHECK-ENCODING: [0xff,0x3f,0x4d,0x04]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 044d3fff <unknown>
umaxqv v0.4s, p0, z0.s // 00000100-10001101-00100000-00000000
// CHECK-INST: umaxqv v0.4s, p0, z0.s
// CHECK-ENCODING: [0x00,0x20,0x8d,0x04]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 048d2000 <unknown>
umaxqv v21.4s, p5, z10.s // 00000100-10001101-00110101-01010101
// CHECK-INST: umaxqv v21.4s, p5, z10.s
// CHECK-ENCODING: [0x55,0x35,0x8d,0x04]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 048d3555 <unknown>
umaxqv v23.4s, p3, z13.s // 00000100-10001101-00101101-10110111
// CHECK-INST: umaxqv v23.4s, p3, z13.s
// CHECK-ENCODING: [0xb7,0x2d,0x8d,0x04]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 048d2db7 <unknown>
umaxqv v31.4s, p7, z31.s // 00000100-10001101-00111111-11111111
// CHECK-INST: umaxqv v31.4s, p7, z31.s
// CHECK-ENCODING: [0xff,0x3f,0x8d,0x04]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 048d3fff <unknown>
umaxqv v0.2d, p0, z0.d // 00000100-11001101-00100000-00000000
// CHECK-INST: umaxqv v0.2d, p0, z0.d
// CHECK-ENCODING: [0x00,0x20,0xcd,0x04]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 04cd2000 <unknown>
umaxqv v21.2d, p5, z10.d // 00000100-11001101-00110101-01010101
// CHECK-INST: umaxqv v21.2d, p5, z10.d
// CHECK-ENCODING: [0x55,0x35,0xcd,0x04]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 04cd3555 <unknown>
umaxqv v23.2d, p3, z13.d // 00000100-11001101-00101101-10110111
// CHECK-INST: umaxqv v23.2d, p3, z13.d
// CHECK-ENCODING: [0xb7,0x2d,0xcd,0x04]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 04cd2db7 <unknown>
umaxqv v31.2d, p7, z31.d // 00000100-11001101-00111111-11111111
// CHECK-INST: umaxqv v31.2d, p7, z31.d
// CHECK-ENCODING: [0xff,0x3f,0xcd,0x04]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 04cd3fff <unknown>
umaxqv v0.16b, p0, z0.b // 00000100-00001101-00100000-00000000
// CHECK-INST: umaxqv v0.16b, p0, z0.b
// CHECK-ENCODING: [0x00,0x20,0x0d,0x04]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 040d2000 <unknown>
umaxqv v21.16b, p5, z10.b // 00000100-00001101-00110101-01010101
// CHECK-INST: umaxqv v21.16b, p5, z10.b
// CHECK-ENCODING: [0x55,0x35,0x0d,0x04]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 040d3555 <unknown>
umaxqv v23.16b, p3, z13.b // 00000100-00001101-00101101-10110111
// CHECK-INST: umaxqv v23.16b, p3, z13.b
// CHECK-ENCODING: [0xb7,0x2d,0x0d,0x04]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 040d2db7 <unknown>
umaxqv v31.16b, p7, z31.b // 00000100-00001101-00111111-11111111
// CHECK-INST: umaxqv v31.16b, p7, z31.b
// CHECK-ENCODING: [0xff,0x3f,0x0d,0x04]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 040d3fff <unknown>

llvm/test/MC/AArch64/SVE2p1/uminqv-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p1 2>&1 < %s | FileCheck %s
// --------------------------------------------------------------------------//
// Invalid predicate register
uminqv v0.2d, p11, z0.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: uminqv v0.2d, p11, z0.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Invalid vector register
uminqv v0.4h, p1, z0.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: uminqv v0.4h, p1, z0.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
uminqv z1.s, p1, z0.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: uminqv z1.s, p1, z0.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Invalid vector suffix
uminqv v0.8h, p1, z0.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: uminqv v0.8h, p1, z0.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/test/MC/AArch64/SVE2p1/uminqv.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p1 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p1 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2p1 < %s \
// RUN: | llvm-objdump -d --mattr=+sme2p1 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2p1 < %s \
// RUN: | llvm-objdump -d --mattr=-sme2p1,-sve2p1 - | FileCheck %s --check-prefix=CHECK-UNKNOWN
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p1 < %s \
// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
// RUN: | llvm-mc -triple=aarch64 -mattr=+sme2p1 -disassemble -show-encoding \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
uminqv v0.8h, p0, z0.h // 00000100-01001111-00100000-00000000
// CHECK-INST: uminqv v0.8h, p0, z0.h
// CHECK-ENCODING: [0x00,0x20,0x4f,0x04]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 044f2000 <unknown>
uminqv v21.8h, p5, z10.h // 00000100-01001111-00110101-01010101
// CHECK-INST: uminqv v21.8h, p5, z10.h
// CHECK-ENCODING: [0x55,0x35,0x4f,0x04]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 044f3555 <unknown>
uminqv v23.8h, p3, z13.h // 00000100-01001111-00101101-10110111
// CHECK-INST: uminqv v23.8h, p3, z13.h
// CHECK-ENCODING: [0xb7,0x2d,0x4f,0x04]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 044f2db7 <unknown>
uminqv v31.8h, p7, z31.h // 00000100-01001111-00111111-11111111
// CHECK-INST: uminqv v31.8h, p7, z31.h
// CHECK-ENCODING: [0xff,0x3f,0x4f,0x04]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 044f3fff <unknown>
uminqv v0.4s, p0, z0.s // 00000100-10001111-00100000-00000000
// CHECK-INST: uminqv v0.4s, p0, z0.s
// CHECK-ENCODING: [0x00,0x20,0x8f,0x04]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 048f2000 <unknown>
uminqv v21.4s, p5, z10.s // 00000100-10001111-00110101-01010101
// CHECK-INST: uminqv v21.4s, p5, z10.s
// CHECK-ENCODING: [0x55,0x35,0x8f,0x04]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 048f3555 <unknown>
uminqv v23.4s, p3, z13.s // 00000100-10001111-00101101-10110111
// CHECK-INST: uminqv v23.4s, p3, z13.s
// CHECK-ENCODING: [0xb7,0x2d,0x8f,0x04]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 048f2db7 <unknown>
uminqv v31.4s, p7, z31.s // 00000100-10001111-00111111-11111111
// CHECK-INST: uminqv v31.4s, p7, z31.s
// CHECK-ENCODING: [0xff,0x3f,0x8f,0x04]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 048f3fff <unknown>
uminqv v0.2d, p0, z0.d // 00000100-11001111-00100000-00000000
// CHECK-INST: uminqv v0.2d, p0, z0.d
// CHECK-ENCODING: [0x00,0x20,0xcf,0x04]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 04cf2000 <unknown>
uminqv v21.2d, p5, z10.d // 00000100-11001111-00110101-01010101
// CHECK-INST: uminqv v21.2d, p5, z10.d
// CHECK-ENCODING: [0x55,0x35,0xcf,0x04]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 04cf3555 <unknown>
uminqv v23.2d, p3, z13.d // 00000100-11001111-00101101-10110111
// CHECK-INST: uminqv v23.2d, p3, z13.d
// CHECK-ENCODING: [0xb7,0x2d,0xcf,0x04]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 04cf2db7 <unknown>
uminqv v31.2d, p7, z31.d // 00000100-11001111-00111111-11111111
// CHECK-INST: uminqv v31.2d, p7, z31.d
// CHECK-ENCODING: [0xff,0x3f,0xcf,0x04]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 04cf3fff <unknown>
uminqv v0.16b, p0, z0.b // 00000100-00001111-00100000-00000000
// CHECK-INST: uminqv v0.16b, p0, z0.b
// CHECK-ENCODING: [0x00,0x20,0x0f,0x04]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 040f2000 <unknown>
uminqv v21.16b, p5, z10.b // 00000100-00001111-00110101-01010101
// CHECK-INST: uminqv v21.16b, p5, z10.b
// CHECK-ENCODING: [0x55,0x35,0x0f,0x04]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 040f3555 <unknown>
uminqv v23.16b, p3, z13.b // 00000100-00001111-00101101-10110111
// CHECK-INST: uminqv v23.16b, p3, z13.b
// CHECK-ENCODING: [0xb7,0x2d,0x0f,0x04]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 040f2db7 <unknown>
uminqv v31.16b, p7, z31.b // 00000100-00001111-00111111-11111111
// CHECK-INST: uminqv v31.16b, p7, z31.b
// CHECK-ENCODING: [0xff,0x3f,0x0f,0x04]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 040f3fff <unknown>