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Differential D137412

[AArch64][SVE2] Add the SVE2.1 add quadword reduction instruction
AbandonedPublic

Authored by david-arm on Nov 4 2022, 5:11 AM.

Details

Reviewers
sdesmalen
aemerson
paulwalker-arm
CarolineConcatto
kmclaughlin
efriedma
Summary

This patch adds the assembly/disassembly for the following instruction:

addqv : Unsigned add reduction of quadword vector segments

The reference can be found here:
https://developer.arm.com/documentation/ddi0602/2022-09

Diff Detail

Event Timeline

david-arm created this revision.Nov 4 2022, 5:11 AM
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david-arm requested review of this revision.Nov 4 2022, 5:11 AM
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david-arm added a parent revision: D137411: [AArch64][SVE2] Add the SVE2.1 integer quadword reduction instructions.Nov 4 2022, 5:11 AM
Harbormaster completed remote builds in B196116: Diff 473197.Nov 4 2022, 5:50 AM
david-arm added a child revision: D137419: [AArch64][SVE2] Add the SVE2.1 FP quadword reduction instructions.Nov 4 2022, 6:05 AM
paulwalker-arm added inline comments.Nov 4 2022, 9:30 AM
llvm/lib/Target/AArch64/SVEInstrFormats.td
9232–9235

As per my comment on D137411, can you use a similar class hierarchy as use by the normal reduction intrinsics?

Matt added a subscriber: Matt.Nov 5 2022, 8:34 PM
david-arm abandoned this revision.Nov 9 2022, 4:55 AM
david-arm mentioned this in D137411: [AArch64][SVE2] Add the SVE2.1 integer quadword reduction instructions.

Now covered by D137411

Revision Contents

PathSize
llvm/
lib/
Target/
AArch64/
1 line
27 lines
test/
MC/
AArch64/
SVE2p1/
30 lines
115 lines

Diff 473197

llvm/lib/Target/AArch64/AArch64SVEInstrInfo.td

Show First 20 Lines • Show All 3,695 Lines • ▼ Show 20 Lines
defm WHILELO_CXX : sve2p1_int_while_rr_pn<"whilelo", 0b110>; defm WHILELO_CXX : sve2p1_int_while_rr_pn<"whilelo", 0b110>;
defm WHILELS_CXX : sve2p1_int_while_rr_pn<"whilels", 0b111>; defm WHILELS_CXX : sve2p1_int_while_rr_pn<"whilels", 0b111>;
} // End HasSVE2p1_or_HasSME2 } // End HasSVE2p1_or_HasSME2
let Predicates = [HasSVE2p1_or_HasSME2p1] in { let Predicates = [HasSVE2p1_or_HasSME2p1] in {
defm ORQV : sve2p1_log_reduction_q<0b00, "orqv">; defm ORQV : sve2p1_log_reduction_q<0b00, "orqv">;
defm EORQV : sve2p1_log_reduction_q<0b01, "eorqv">; defm EORQV : sve2p1_log_reduction_q<0b01, "eorqv">;
defm ANDQV : sve2p1_log_reduction_q<0b10, "andqv">; defm ANDQV : sve2p1_log_reduction_q<0b10, "andqv">;
defm ADDQV : sve2p1_add_reduction_q<0b01, "addqv">;
} }

llvm/lib/Target/AArch64/SVEInstrFormats.td

  • This file is larger than 256 KB, so syntax highlighting is disabled by default.
Show First 20 Lines • Show All 9,220 Lines • ▼ Show 20 Lines
} }
multiclass sve2p1_log_reduction_q<bits<2> opc, string mnemonic> { multiclass sve2p1_log_reduction_q<bits<2> opc, string mnemonic> {
def _B : sve2p1_log_reduction_q<0b00, opc, mnemonic, ZPR8, "16b">; def _B : sve2p1_log_reduction_q<0b00, opc, mnemonic, ZPR8, "16b">;
def _H : sve2p1_log_reduction_q<0b01, opc, mnemonic, ZPR16, "8h">; def _H : sve2p1_log_reduction_q<0b01, opc, mnemonic, ZPR16, "8h">;
def _S : sve2p1_log_reduction_q<0b10, opc, mnemonic, ZPR32, "4s">; def _S : sve2p1_log_reduction_q<0b10, opc, mnemonic, ZPR32, "4s">;
def _D : sve2p1_log_reduction_q<0b11, opc, mnemonic, ZPR64, "2d">; def _D : sve2p1_log_reduction_q<0b11, opc, mnemonic, ZPR64, "2d">;
} }
// SVE integer add reduction (quadwords)
class sve2p1_add_reduction_q<bits<2> sz, bits<2> opc, string mnemonic,
RegisterOperand zpr_ty, string vec_sfx>
: I<(outs V128:$Vd), (ins PPR3bAny:$Pg, zpr_ty:$Zn),
mnemonic, "\t$Vd." # vec_sfx # ", $Pg, $Zn",
paulwalker-armUnsubmitted
Not Done
ReplyInline Actions

As per my comment on D137411, can you use a similar class hierarchy as use by the normal reduction intrinsics?

paulwalker-arm: As per my comment on D137411, can you use a similar class hierarchy as use by the normal…
"", []>, Sched<[]> {
bits<5> Vd;
bits<5> Zn;
bits<3> Pg;
let Inst{31-24} = 0b00000100;
let Inst{23-22} = sz;
let Inst{21-18} = 0b0001;
let Inst{17-16} = opc;
let Inst{15-13} = 0b001;
let Inst{12-10} = Pg;
let Inst{9-5} = Zn;
let Inst{4-0} = Vd;
}
multiclass sve2p1_add_reduction_q<bits<2> opc, string mnemonic> {
def _B : sve2p1_add_reduction_q<0b00, opc, mnemonic, ZPR8, "16b">;
def _H : sve2p1_add_reduction_q<0b01, opc, mnemonic, ZPR16, "8h">;
def _S : sve2p1_add_reduction_q<0b10, opc, mnemonic, ZPR32, "4s">;
def _D : sve2p1_add_reduction_q<0b11, opc, mnemonic, ZPR64, "2d">;
}

llvm/test/MC/AArch64/SVE2p1/addqv-diagnostics.s

  • This file was added.
// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p1 2>&1 < %s | FileCheck %s
// --------------------------------------------------------------------------//
// Invalid predicate register
addqv v0.2d, p11, z0.d
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid restricted predicate register, expected p0..p7 (without element suffix)
// CHECK-NEXT: addqv v0.2d, p11, z0.d
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Invalid vector register
addqv v0.4h, p1, z0.h
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: addqv v0.4h, p1, z0.h
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
addqv z1.s, p1, z0.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
// CHECK-NEXT: addqv z1.s, p1, z0.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
// --------------------------------------------------------------------------//
// Invalid vector suffix
addqv v0.8h, p1, z0.s
// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid element width
// CHECK-NEXT: addqv v0.8h, p1, z0.s
// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/test/MC/AArch64/SVE2p1/addqv.s

  • This file was added.
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p1 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sve2p1 < %s \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
// RUN: | FileCheck %s --check-prefix=CHECK-ERROR
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2p1 < %s \
// RUN: | llvm-objdump -d --mattr=+sme2p1 - | FileCheck %s --check-prefix=CHECK-INST
// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2p1 < %s \
// RUN: | llvm-objdump -d - | FileCheck %s --check-prefix=CHECK-UNKNOWN
// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2p1 < %s \
// RUN: | sed '/.text/d' | sed 's/.*encoding: //g' \
// RUN: | llvm-mc -triple=aarch64 -mattr=+sme2p1 -disassemble -show-encoding \
// RUN: | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
addqv v0.8h, p0, z0.h // 00000100-01000101-00100000-00000000
// CHECK-INST: addqv v0.8h, p0, z0.h
// CHECK-ENCODING: [0x00,0x20,0x45,0x04]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 04452000 <unknown>
addqv v21.8h, p5, z10.h // 00000100-01000101-00110101-01010101
// CHECK-INST: addqv v21.8h, p5, z10.h
// CHECK-ENCODING: [0x55,0x35,0x45,0x04]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 04453555 <unknown>
addqv v23.8h, p3, z13.h // 00000100-01000101-00101101-10110111
// CHECK-INST: addqv v23.8h, p3, z13.h
// CHECK-ENCODING: [0xb7,0x2d,0x45,0x04]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 04452db7 <unknown>
addqv v31.8h, p7, z31.h // 00000100-01000101-00111111-11111111
// CHECK-INST: addqv v31.8h, p7, z31.h
// CHECK-ENCODING: [0xff,0x3f,0x45,0x04]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 04453fff <unknown>
addqv v0.4s, p0, z0.s // 00000100-10000101-00100000-00000000
// CHECK-INST: addqv v0.4s, p0, z0.s
// CHECK-ENCODING: [0x00,0x20,0x85,0x04]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 04852000 <unknown>
addqv v21.4s, p5, z10.s // 00000100-10000101-00110101-01010101
// CHECK-INST: addqv v21.4s, p5, z10.s
// CHECK-ENCODING: [0x55,0x35,0x85,0x04]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 04853555 <unknown>
addqv v23.4s, p3, z13.s // 00000100-10000101-00101101-10110111
// CHECK-INST: addqv v23.4s, p3, z13.s
// CHECK-ENCODING: [0xb7,0x2d,0x85,0x04]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 04852db7 <unknown>
addqv v31.4s, p7, z31.s // 00000100-10000101-00111111-11111111
// CHECK-INST: addqv v31.4s, p7, z31.s
// CHECK-ENCODING: [0xff,0x3f,0x85,0x04]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 04853fff <unknown>
addqv v0.2d, p0, z0.d // 00000100-11000101-00100000-00000000
// CHECK-INST: addqv v0.2d, p0, z0.d
// CHECK-ENCODING: [0x00,0x20,0xc5,0x04]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 04c52000 <unknown>
addqv v21.2d, p5, z10.d // 00000100-11000101-00110101-01010101
// CHECK-INST: addqv v21.2d, p5, z10.d
// CHECK-ENCODING: [0x55,0x35,0xc5,0x04]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 04c53555 <unknown>
addqv v23.2d, p3, z13.d // 00000100-11000101-00101101-10110111
// CHECK-INST: addqv v23.2d, p3, z13.d
// CHECK-ENCODING: [0xb7,0x2d,0xc5,0x04]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 04c52db7 <unknown>
addqv v31.2d, p7, z31.d // 00000100-11000101-00111111-11111111
// CHECK-INST: addqv v31.2d, p7, z31.d
// CHECK-ENCODING: [0xff,0x3f,0xc5,0x04]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 04c53fff <unknown>
addqv v0.16b, p0, z0.b // 00000100-00000101-00100000-00000000
// CHECK-INST: addqv v0.16b, p0, z0.b
// CHECK-ENCODING: [0x00,0x20,0x05,0x04]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 04052000 <unknown>
addqv v21.16b, p5, z10.b // 00000100-00000101-00110101-01010101
// CHECK-INST: addqv v21.16b, p5, z10.b
// CHECK-ENCODING: [0x55,0x35,0x05,0x04]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 04053555 <unknown>
addqv v23.16b, p3, z13.b // 00000100-00000101-00101101-10110111
// CHECK-INST: addqv v23.16b, p3, z13.b
// CHECK-ENCODING: [0xb7,0x2d,0x05,0x04]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 04052db7 <unknown>
addqv v31.16b, p7, z31.b // 00000100-00000101-00111111-11111111
// CHECK-INST: addqv v31.16b, p7, z31.b
// CHECK-ENCODING: [0xff,0x3f,0x05,0x04]
// CHECK-ERROR: instruction requires: sme2p1 or sve2p1
// CHECK-UNKNOWN: 04053fff <unknown>