[AArch64] SME2 multi-vec unpack, ZIP, frint for two and four registers

[CarolineConcatto]

Summary

This patch adds the assembly/disassembly for the following instructions:

SUNPK: Unpack and sign-extend multi-vector elements.
UUNPK: Unpack and zero-extend multi-vector elements.
ZIP (four registers): Interleave elements from four vectors.
ZIP (two registers): Interleave elements from two vectors.
FRINTA: Multi-vector floating-point round to integral value, to nearest with ties away from zero.
FRINTM: Multi-vector floating-point round to integral value, toward minus Infinity.
FRINTN: Multi-vector floating-point round to integral value, to nearest with ties to even.
FRINTP: Multi-vector floating-point round to integral value, toward plus Infinity.

The reference can be found here:

https://developer.arm.com/documentation/ddi0602/2022-09

[CarolineConcatto]

Reuse clamp class
Rebase

[CarolineConcatto]

• Reuse cvt class for zip

[paulwalker-arm]

llvm/lib/Target/AArch64/AArch64RegisterInfo.td

1237

I'd expect this to be ZPR2Mul2?

1260

ZPR4Mul4?

llvm/lib/Target/AArch64/SMEInstrFormats.td

1924–1925

Have you reached the point where this class can just represent SME2 Multi-vector - SVE Constructive Unary? Perhaps not all instructions within that encoding group fit but looking at this new definition of Inst, which I very much like by the way, suggests that is what this class effectively represents. So you just need to change a few opcodes to match the documentation.

[paulwalker-arm]

llvm/lib/Target/AArch64/SMEInstrFormats.td

1924–1925

Actually looking at the register layouts perhaps this is not quite so clear cut, but I do think it's worth investigating to see if there's an options for more reuse. If you decide the current class is still the best route then I do think streaming the opcode across three variables is not great.

[CarolineConcatto]

• Address review comments

llvm/lib/Target/AArch64/SMEInstrFormats.td

1924–1925

I looked before trying to merge them, but the registers sizes change between the group of instructions.

I reduced from 4 to 3 set of bit. The problem is that for cvt we need 3 bits to select the instructions, and for zip it doesn't, the same 3 bits need to be set because they are also the size.

[paulwalker-arm]

llvm/lib/Target/AArch64/SMEInstrFormats.td

1924–1925

Sure I get the register sizes are different so we cannot have a single register class but it looks like we could have a smaller number of base classes based on register sizes? For example a class which represents the "SME2 Multi-vector - SVE Constructive Unary" encoding group can support all instructions where both registers are 3 bit. So:

SME2 multi-vec FP to int convert four registers
SME2 multi-vec int to FP four registers
SME2 multi-vec quadwords ZIP four registers
SME2 multi-vec ZIP four registers
SME2 multi-vec FRINT four registers

Likewise and class similar to the above but where the registers are 4bit can be used for:

SME2 multi-vec FP to int convert two registers
SME2 multi-vec int to FP two registers
SME2 multi-vec FRINT two registers

So with these 2 base classes you cover half of the groups within this parent encoding group. It starts to be a case of diminishing returns after this but even then "SME2 multi-vec FP down convert two registers" and "SME2 multi-vec int down convert two registers" can be grouped together.

[CarolineConcatto]

• Refactor the classes for all the instructions under Multi-vector - SVE Constructive Unary

[CarolineConcatto]

Hey Paul,
I also pushed FRINT instructions to be in this class

llvm/lib/Target/AArch64/SMEInstrFormats.td

1924–1925

I could not do what you asked. So I refactored the entire class.
Now I have a main class sme2_sve_constructive_unary
and many other small classes derived from sme2_sve_constructive_unary.
The Zd and Zn size are different in every class that I had to create.

[CarolineConcatto]

• More refactoring in the classes

[CarolineConcatto]

• Update commit message

[CarolineConcatto]

Hi Paul,
After we had a chat I try again to merge more classes.
I believe that is what we want.

[paulwalker-arm]

llvm/lib/Target/AArch64/SMEInstrFormats.td

1788

This should be NAME because you're already suffixing the instructions with _StoS.

1853–1854

Inst{21-18} = 0b1000;

llvm/lib/Target/AArch64/AArch64RegisterInfo.td

let EncoderMethod = "EncodeRegAsMultipleOf<2>",
 
   def ZZ_s_mul_r : RegisterOperand<ZPR2Mul2, "printTypedVectorList<0,'s'>"> {
     let ParserMatchClass = ZPRVectorListMul<32, 2>;
   }
 
   def ZZ_d_mul_r : RegisterOperand<ZPR2Mul2, "printTypedVectorList<0,'d'>"> {
     let ParserMatchClass = ZPRVectorListMul<64, 2>;
   }
+
+  def ZZ_q_mul_r : RegisterOperand<ZPR2Mul2, "printTypedVectorList<0,'q'>"> {
+    let ParserMatchClass = ZPRVectorListMul<128, 2>;
+  }
 } // end let EncoderMethod/DecoderMethod
 
 let EncoderMethod = "EncodeRegAsMultipleOf<4>",
     DecoderMethod = "DecodeZPR4Mul4RegisterClass" in {
   def ZZZZ_b_mul_r : RegisterOperand<ZPR4Mul4, "printTypedVectorList<0,'b'>"> {
     let ParserMatchClass = ZPRVectorListMul<8, 4>;
   }
 
   def ZZZZ_h_mul_r : RegisterOperand<ZPR4Mul4, "printTypedVectorList<0,'h'>"> {
     let ParserMatchClass = ZPRVectorListMul<16, 4>;
   }
 
   def ZZZZ_s_mul_r : RegisterOperand<ZPR4Mul4, "printTypedVectorList<0,'s'>"> {
     let ParserMatchClass = ZPRVectorListMul<32, 4>;
   }
 
   def ZZZZ_d_mul_r : RegisterOperand<ZPR4Mul4, "printTypedVectorList<0,'d'>"> {
     let ParserMatchClass = ZPRVectorListMul<64, 4>;
   }
+
+  def ZZZZ_q_mul_r : RegisterOperand<ZPR4Mul4, "printTypedVectorList<0,'q'>"> {
+    let ParserMatchClass = ZPRVectorListMul<128, 4>;
+  }
 } // end let EncoderMethod/DecoderMethod
 
 class ZPRExtendAsmOperand<string ShiftExtend, int RegWidth, int Scale,
                           bit ScaleAlwaysSame = 0b0> : AsmOperandClass {
   let Name = "ZPRExtend" # ShiftExtend # RegWidth # Scale
                          # !if(ScaleAlwaysSame, "Only", "");
 
   let PredicateMethod = "isSVEDataVectorRegWithShiftExtend<"

llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td

 defm UMLSL_VG2_M2ZZI : sme2_int_mla_long_array_vg2_index<"umlsl",  0b11>;
 defm UMLSL_VG4_M4ZZI : sme2_int_mla_long_array_vg4_index<"umlsl",  0b11>;
 defm UMLSL_MZZ       : sme2_mla_long_array_single<"umlsl",0b01,    0b11>;
 defm UMLSL_VG2_M2ZZ  : sme2_int_mla_long_array_vg2_single<"umlsl", 0b11>;
 defm UMLSL_VG4_M4ZZ  : sme2_int_mla_long_array_vg4_single<"umlsl", 0b11>;
 defm UMLSL_VG2_M2Z2Z : sme2_int_mla_long_array_vg2_multi<"umlsl",  0b11>;
 defm UMLSL_VG4_M4Z4Z : sme2_int_mla_long_array_vg4_multi<"umlsl",  0b11>;
 
-def FCVT_Z2Z_StoH   : sme2_cvt_vg2_single<"fcvt",   0b00, 0b00>;
-def FCVTN_Z2Z_StoH  : sme2_cvt_vg2_single<"fcvtn",  0b01, 0b00>;
-def BFCVT_Z2Z_StoH  : sme2_cvt_vg2_single<"bfcvt",  0b10, 0b00>;
-def BFCVTN_Z2Z_StoH : sme2_cvt_vg2_single<"bfcvtn", 0b11, 0b00>;
-
-def SQCVT_Z2Z_StoH  : sme2_cvt_vg2_single<"sqcvt", 0b00, 0b11>;
-def UQCVT_Z2Z_StoH  : sme2_cvt_vg2_single<"uqcvt", 0b01, 0b11>;
-def SQCVTU_Z2Z_StoH : sme2_cvt_vg2_single<"sqcvtu", 0b10, 0b11>;
+defm FCVT_Z2Z_StoH   : sme2_cvt_vg2_single<"fcvt",   0b0000>;
+defm FCVTN_Z2Z_StoH  : sme2_cvt_vg2_single<"fcvtn",  0b0001>;
+defm BFCVT_Z2Z_StoH  : sme2_cvt_vg2_single<"bfcvt",  0b1000>;
+defm BFCVTN_Z2Z_StoH : sme2_cvt_vg2_single<"bfcvtn", 0b1001>;
+
+defm SQCVT_Z2Z_StoH  : sme2_cvt_vg2_single<"sqcvt",  0b0110>;
+defm UQCVT_Z2Z_StoH  : sme2_cvt_vg2_single<"uqcvt",  0b0111>;
+defm SQCVTU_Z2Z_StoH : sme2_cvt_vg2_single<"sqcvtu", 0b1110>;
 defm SQCVT_Z4Z      : sme2_int_cvt_vg4_single<"sqcvt", 0b000>;
 defm UQCVT_Z4Z      : sme2_int_cvt_vg4_single<"uqcvt", 0b001>;
 defm SQCVTU_Z4Z     : sme2_int_cvt_vg4_single<"sqcvtu", 0b100>;
 defm SQCVTN_Z4Z     : sme2_int_cvt_vg4_single<"sqcvtn", 0b010>;
 defm SQCVTUN_Z4Z    : sme2_int_cvt_vg4_single<"sqcvtun", 0b110>;
 defm UQCVTN_Z4Z     : sme2_int_cvt_vg4_single<"uqcvtn", 0b011>;
 
-def FCVTZS_2Z2Z_StoS : sme2_fp_cvt_vg2_multi<"fcvtzs", 0b010>;
-def FCVTZS_4Z4Z_StoS : sme2_fp_cvt_vg4_multi<"fcvtzs", 0b010>;
-def FCVTZU_2Z2Z_StoS : sme2_fp_cvt_vg2_multi<"fcvtzu", 0b011>;
-def FCVTZU_4Z4Z_StoS : sme2_fp_cvt_vg4_multi<"fcvtzu", 0b011>;
-def SCVTF_2Z2Z_StoS  : sme2_fp_cvt_vg2_multi<"scvtf", 0b100>;
-def SCVTF_4Z4Z_StoS  : sme2_fp_cvt_vg4_multi<"scvtf", 0b100>;
-def UCVTF_2Z2Z_StoS  : sme2_fp_cvt_vg2_multi<"ucvtf", 0b101>;
-def UCVTF_4Z4Z_StoS  : sme2_fp_cvt_vg4_multi<"ucvtf", 0b101>;
+defm FCVTZS_2Z2Z_StoS : sme2_fp_cvt_vg2_multi<"fcvtzs", 0b00010>;
+defm FCVTZS_4Z4Z_StoS : sme2_fp_cvt_vg4_multi<"fcvtzs", 0b0001000>;
+defm FCVTZU_2Z2Z_StoS : sme2_fp_cvt_vg2_multi<"fcvtzu", 0b00011>;
+defm FCVTZU_4Z4Z_StoS : sme2_fp_cvt_vg4_multi<"fcvtzu", 0b0001010>;
+defm SCVTF_2Z2Z_StoS  : sme2_fp_cvt_vg2_multi<"scvtf", 0b00100>;
+defm SCVTF_4Z4Z_StoS  : sme2_fp_cvt_vg4_multi<"scvtf", 0b0010000>;
+defm UCVTF_2Z2Z_StoS  : sme2_fp_cvt_vg2_multi<"ucvtf", 0b00101>;
+defm UCVTF_4Z4Z_StoS  : sme2_fp_cvt_vg4_multi<"ucvtf", 0b0010010>;
 
 defm SMAX_VG2_2ZZ  : sme2_int_sve_destructive_vector_vg2_single<"smax", 0b0000000>;
 defm SMAX_VG4_4ZZ  : sme2_int_sve_destructive_vector_vg4_single<"smax", 0b0000000>;
 defm SMAX_VG2_2Z2Z : sme2_int_sve_destructive_vector_vg2_multi<"smax",  0b0000000>;
 defm SMAX_VG4_4Z4Z : sme2_int_sve_destructive_vector_vg4_multi<"smax",  0b0000000>;
 
 defm UMAX_VG2_2ZZ  : sme2_int_sve_destructive_vector_vg2_single<"umax", 0b0000001>;
 defm UMAX_VG4_4ZZ  : sme2_int_sve_destructive_vector_vg4_single<"umax", 0b0000001>;

 
 defm LUTI2_ZTZI  : sme2_luti2_vector_index<"luti2">;
 defm LUTI2_2ZTZI : sme2_luti2_vector_vg2_index<"luti2">;
 defm LUTI2_4ZTZI : sme2_luti2_vector_vg4_index<"luti2">;
 
 defm LUTI4_ZTZI  : sme2_luti4_vector_index<"luti4">;
 defm LUTI4_2ZTZI : sme2_luti4_vector_vg2_index<"luti4">;
 defm LUTI4_4ZTZI : sme2_luti4_vector_vg4_index<"luti4">;
+
+defm SUNPK_VG2_2ZZ  : sme2_unpk_vector_vg2<"sunpk", 0b0>;
+defm SUNPK_VG4_4Z2Z : sme2_unpk_vector_vg4<"sunpk", 0b0>;
+defm UUNPK_VG2_2ZZ  : sme2_unpk_vector_vg2<"uunpk", 0b1>;
+defm UUNPK_VG4_4Z2Z : sme2_unpk_vector_vg4<"uunpk", 0b1>;
+
+defm ZIP_VG2_2ZZZ : sme2_zip_vector_vg2<"zip", 0b0>;
+defm UZP_VG2_2ZZZ : sme2_zip_vector_vg2<"uzp", 0b1>;
+defm ZIP_VG4_4Z4Z : sme2_zip_vector_vg4<"zip", 0b0110000>;
+defm UZP_VG4_4Z4Z : sme2_zip_vector_vg4<"uzp", 0b0110001>;
+defm ZIP_VG4_4Z4Z_Q : sme2_zip_vector_vg4_Q<"zip", 0b0111000>;
+defm UZP_VG4_4Z4Z_Q : sme2_zip_vector_vg4_Q<"uzp", 0b0111001>;
+
+defm FRINTA_2Z2Z: sme2_frint_vector_vg2_multi<"frinta", 0b11000>;
+defm FRINTA_4Z4Z: sme2_frint_vector_vg4_multi<"frinta", 0b1100000>;
+defm FRINTM_2Z2Z: sme2_frint_vector_vg2_multi<"frintm", 0b10100>;
+defm FRINTM_4Z4Z: sme2_frint_vector_vg4_multi<"frintm", 0b1010000>;
+defm FRINTN_2Z2Z: sme2_frint_vector_vg2_multi<"frintn", 0b10000>;
+defm FRINTN_4Z4Z: sme2_frint_vector_vg4_multi<"frintn", 0b1000000>;
+defm FRINTP_2Z2Z: sme2_frint_vector_vg2_multi<"frintp", 0b10010>;
+defm FRINTP_4Z4Z: sme2_frint_vector_vg4_multi<"frintp", 0b1001000>;
 }
 
 let Predicates = [HasSME2, HasSMEI16I64] in {
 defm ADD_VG2_M2ZZ_D  : sme2_dot_mla_add_sub_array_vg24_single<"add", 0b1011010, MatrixOp64, ZZ_d, ZPR4b64>;
 defm ADD_VG4_M4ZZ_D  : sme2_dot_mla_add_sub_array_vg24_single<"add", 0b1111010, MatrixOp64, ZZZZ_d, ZPR4b64>;
 defm ADD_VG2_M2Z2Z_D : sme2_dot_mla_add_sub_array_vg2_multi<"add", 0b111010, MatrixOp64, ZZ_d_mul_r>;
 defm ADD_VG4_M4Z4Z_D : sme2_dot_mla_add_sub_array_vg4_multi<"add", 0b111010, MatrixOp64, ZZZZ_d_mul_r>;
 

llvm/lib/Target/AArch64/SMEInstrFormats.td

 multiclass sme2_int_mla_long_array_vg4_multi<string mnemonic, bits<2> op> {
   def _S : sme2_mla_long_array_vg4_multi<mnemonic, 0b11, op>;
 
   def : InstAlias<mnemonic # "\t$ZAda[$Rv, $imm2], $Zn, $Zm",
                  (!cast<Instruction>(NAME #_S) MatrixOp32:$ZAda,  MatrixIndexGPR32Op8_11:$Rv, uimm2s2range:$imm2, ZZZZ_h_mul_r:$Zn, ZZZZ_h_mul_r:$Zm), 0>;
 }
 
 //===----------------------------------------------------------------------===//
-// SME2 multi-vec INT/ FP down convert
+class sme2_frint_cvt_vg2_multi<bits<2>sz, bits<5>op, RegisterOperand first_ty,
+                               RegisterOperand second_ty, string mnemonic>
+    : I<(outs first_ty:$Zd), (ins second_ty:$Zn),
+        mnemonic, "\t$Zd, $Zn", "", []>, Sched<[]> {
+  bits<4> Zn;
+  bits<4> Zd;
+  let Inst{31-24} = 0b11000001;
+  let Inst{23-22} = sz;
+  let Inst{21-20} = 0b10;
+  let Inst{19-16} = op{4-1};
+  let Inst{15-10} = 0b111000;
+  let Inst{9-6}   = Zn;
+  let Inst{5}     = op{0};
+  let Inst{4-1}   = Zd;
+  let Inst{0}     = 0b0;
+}
+
+// SME2 multi-vec FP to int convert two registers
+// SME2 multi-vec int to FP two registers
+multiclass sme2_fp_cvt_vg2_multi<string mnemonic, bits<5> op> {
+  def NAME : sme2_frint_cvt_vg2_multi<0b00, op, ZZ_s_mul_r, ZZ_s_mul_r, mnemonic>;
+}
+
+// SME2 multi-vec FRINT two registers
+multiclass sme2_frint_vector_vg2_multi<string mnemonic, bits<5> op> {
+  def _S : sme2_frint_cvt_vg2_multi<0b10, op, ZZ_s_mul_r, ZZ_s_mul_r, mnemonic>;
+}
+
+class sme2_frint_zip_cvt_vg4_multi<bits<2>sz, bits<7>op, RegisterOperand first_ty,
+                                   RegisterOperand second_ty, string mnemonic>
+    : I<(outs first_ty:$Zd), (ins second_ty:$Zn),
+        mnemonic, "\t$Zd, $Zn", "", []>, Sched<[]> {
+  bits<3> Zn;
+  bits<3> Zd;
+  let Inst{31-24} = 0b11000001;
+  let Inst{23-22} = sz;
+  let Inst{21-20} = 0b11;
+  let Inst{19-16} = op{6-3};
+  let Inst{15-10} = 0b111000;
+  let Inst{9-7}   = Zn;
+  let Inst{6-5}   = op{2-1};
+  let Inst{4-2}   = Zd;
+  let Inst{1}     = op{0};
+  let Inst{0}     = 0b0;
+}
+
+// SME2 multi-vec FP to int convert four registers
+// SME2 multi-vec int to FP four registers
+multiclass sme2_fp_cvt_vg4_multi<string mnemonic, bits<7> op> {
+  def _S : sme2_frint_zip_cvt_vg4_multi<0b00, op, ZZZZ_s_mul_r, ZZZZ_s_mul_r, mnemonic>;
+}
+
+// SME2 multi-vec quadwords ZIP four registers
+multiclass sme2_zip_vector_vg4<string mnemonic, bits<7> op> {
+  def _B : sme2_frint_zip_cvt_vg4_multi<0b00, op, ZZZZ_b_mul_r, ZZZZ_b_mul_r,
+                                        mnemonic>;
+  def _H : sme2_frint_zip_cvt_vg4_multi<0b01, op, ZZZZ_h_mul_r, ZZZZ_h_mul_r,
+                                        mnemonic>;
+  def _S : sme2_frint_zip_cvt_vg4_multi<0b10, op, ZZZZ_s_mul_r, ZZZZ_s_mul_r,
+                                        mnemonic>;
+  def _D : sme2_frint_zip_cvt_vg4_multi<0b11, op, ZZZZ_d_mul_r, ZZZZ_d_mul_r,
+                                         mnemonic>;
+}
+
+// SME2 multi-vec quadwords ZIP four registers
+multiclass sme2_zip_vector_vg4_Q<string mnemonic, bits<7> op> {
+  def NAME: sme2_frint_zip_cvt_vg4_multi<0b00, op, ZZZZ_q_mul_r, ZZZZ_q_mul_r,
+                                         mnemonic>;
+}
 
-class sme2_cvt_vg2_single<string mnemonic, bits<2> op, bits<2> is_int>
+// SME2 multi-vec FRINT four registers
+multiclass sme2_frint_vector_vg4_multi<string mnemonic, bits<7> op> {
+  def _S :  sme2_frint_zip_cvt_vg4_multi<0b10, op, ZZZZ_s_mul_r, ZZZZ_s_mul_r,
+                                         mnemonic>;
+}
+
+class sme2_cvt_vg2_single<string mnemonic, bits<4> op>
     : I<(outs ZPR16:$Zd), (ins ZZ_s_mul_r:$Zn),
         mnemonic, "\t$Zd, $Zn", "", []>, Sched<[]> {
   bits<4> Zn;
   bits<5> Zd;
   let Inst{31-23} = 0b110000010;
-  let Inst{22}    = op{1};
+  let Inst{22}    = op{3};
   let Inst{21-18} = 0b1000;
-  let Inst{17-16} = is_int;
+  let Inst{17-16} = op{2-1};
   let Inst{15-10} = 0b111000;
   let Inst{9-6}   = Zn;
   let Inst{5}     = op{0};
   let Inst{4-0}   = Zd;
 }
 
+// SME2 multi-vec FP down convert two registers
+// SME2 multi-vec int down convert two registers
+multiclass sme2_cvt_vg2_single<string mnemonic, bits<4> op> {
+  def NAME :  sme2_cvt_vg2_single<mnemonic, op>;
+}
 
-class sme2_cvt_vg4_single<bit sz,bits<3> op, ZPRRegOp zpr_ty, RegisterOperand vector_ty,
-                           string mnemonic>
-    : I<(outs zpr_ty:$Zd), (ins vector_ty:$Zn),
+
+class sme2_unpk_vector_vg2<bits<2>sz, bit u, RegisterOperand first_ty,
+                           RegisterOperand second_ty, string mnemonic>
+    : I<(outs first_ty:$Zd), (ins second_ty:$Zn),
+        mnemonic, "\t$Zd, $Zn", "", []>, Sched<[]> {
+  bits<5> Zn;
+  bits<4> Zd;
+  let Inst{31-24} = 0b11000001;
+  let Inst{23-22} = sz;
+  let Inst{21-10} = 0b100101111000;
+  let Inst{9-5}   = Zn;
+  let Inst{4-1}   = Zd;
+  let Inst{0}     = u;
+}
+
+// SME2 multi-vec unpack two registers
+multiclass sme2_unpk_vector_vg2<string mnemonic, bit u> {
+  def _H : sme2_unpk_vector_vg2<0b01, u, ZZ_h_mul_r, ZPR8, mnemonic>;
+  def _S : sme2_unpk_vector_vg2<0b10, u, ZZ_s_mul_r, ZPR16, mnemonic>;
+  def _D : sme2_unpk_vector_vg2<0b11, u, ZZ_d_mul_r, ZPR32, mnemonic>;
+}
+
+
+class sme2_cvt_vg4_single<bit sz, bits<3> op, RegisterOperand first_ty,
+                          RegisterOperand second_ty, string mnemonic>
+    : I<(outs first_ty:$Zd), (ins second_ty:$Zn),
         mnemonic, "\t$Zd, $Zn", "", []>, Sched<[]> {
   bits<3> Zn;
   bits<5> Zd;
   let Inst{31-24} = 0b11000001;
   let Inst{23}    = sz;
   let Inst{22}    = op{2};
-  let Inst{21-16} = 0b110011;
-  let Inst{15-10} = 0b111000;
+  let Inst{21-10} = 0b110011111000;
   let Inst{9-7}   = Zn;
   let Inst{6-5}   = op{1-0};
   let Inst{4-0}   = Zd;
 }
 
-
+// SME2 multi-vec int down convert four registers
 multiclass sme2_int_cvt_vg4_single<string mnemonic, bits<3> op> {
-def _StoB : sme2_cvt_vg4_single<0b0, op, ZPR8, ZZZZ_s_mul_r, mnemonic>;
-def _DtoH : sme2_cvt_vg4_single<0b1, op, ZPR16, ZZZZ_d_mul_r, mnemonic>;
+def _StoB : sme2_cvt_vg4_single<0, op, ZPR8, ZZZZ_s_mul_r, mnemonic>;
+def _DtoH : sme2_cvt_vg4_single<1, op, ZPR16, ZZZZ_d_mul_r, mnemonic>;
 }
 
-class sme2_fp_cvt_vg2_multi<string mnemonic, bits<3> op>
-    : I<(outs ZZ_s_mul_r:$Zd), (ins ZZ_s_mul_r:$Zn),
-         mnemonic, "\t$Zd, $Zn", "", []>, Sched<[]> {
+class sme2_unpk_vector_vg4<bits<2>sz, bit u, RegisterOperand first_ty,
+                           RegisterOperand second_ty, string mnemonic>
+    : I<(outs first_ty:$Zd), (ins second_ty:$Zn),
   bits<4> Zn;
-  bits<4> Zd;
-  let Inst{31-18} = 0b11000001001000;
-  let Inst{17-16} = op{2-1};
-  let Inst{15-10} = 0b111000;
+  bits<3> Zd;
+  let Inst{31-24} = 0b11000001;
+  let Inst{23-22} = sz;
+  let Inst{21-10} = 0b110101111000;
   let Inst{9-6}   = Zn;
-  let Inst{5}     = op{0};
-  let Inst{4-1}   = Zd;
-  let Inst{0}     = 0b0;
+  let Inst{5}     = 0b0;
+  let Inst{4-2}   = Zd;
+  let Inst{1}     = 0b0;
+  let Inst{0}     = u;
 }
 
-
-class sme2_fp_cvt_vg4_multi<string mnemonic, bits<3> op>
-    : I<(outs ZZZZ_s_mul_r:$Zd), (ins ZZZZ_s_mul_r:$Zn),
-         mnemonic, "\t$Zd, $Zn", "", []>, Sched<[]> {
-  bits<3> Zn;
-  bits<3> Zd;
-  let Inst{31-18} = 0b11000001001100;
-  let Inst{17-16} = op{2-1};
-  let Inst{15-10} = 0b111000;
-  let Inst{9-7}   = Zn;
-  let Inst{6}     = 0b0;
-  let Inst{5}     = op{0};
-  let Inst{4-2}   = Zd;
-  let Inst{1-0}   = 0b00;
+// SME2 multi-vec UNPK four registers
+multiclass sme2_unpk_vector_vg4<string mnemonic, bit u> {
+  def _H : sme2_unpk_vector_vg4<0b01, u, ZZZZ_h_mul_r, ZZ_b_mul_r, mnemonic>;
+  def _S : sme2_unpk_vector_vg4<0b10, u, ZZZZ_s_mul_r, ZZ_h_mul_r, mnemonic>;
+  def _D : sme2_unpk_vector_vg4<0b11, u, ZZZZ_d_mul_r, ZZ_s_mul_r, mnemonic>;
 }
 
 //===----------------------------------------------------------------------===//
 // SME2 multi-vec CLAMP registers
 
-class sme2_clamp_vector_vg24_multi<bits<2> sz, bits<2> op1, bit u,
+class sme2_zip_clamp_vector_vg24_multi<bits<2> sz, bits<3> op1, bit u,
                                        RegisterOperand multi_vector_ty,
                                        ZPRRegOp vector_ty, string mnemonic>
     : I<(outs multi_vector_ty:$Zd),
         (ins  multi_vector_ty:$_Zd, vector_ty:$Zn, vector_ty:$Zm),
         mnemonic, "\t$Zd, $Zn, $Zm",
         "", []>, Sched<[]>{
   bits<5> Zm;
   bits<5> Zn;
   let Inst{31-24} = 0b11000001;
   let Inst{23-22} = sz;
   let Inst{21}    = 0b1;
   let Inst{20-16} = Zm;
-  let Inst{15-12} = 0b1100;
-  let Inst{11-10} = op1;
+  let Inst{15-13} = 0b110;
+  let Inst{12-10} = op1;
   let Inst{9-5}   = Zn;
   let Inst{0}     = u;
 
   let Constraints = "$Zd = $_Zd";
 }
 
-class sme2_clamp_vector_vg2_multi<bits<2> sz, bits<2> op1, bit u,
+class sme2_zip_clamp_vector_vg2_multi<bits<2> sz, bits<3> op1, bit u,
                                       RegisterOperand multi_vector_ty,
                                       ZPRRegOp vector_ty, string mnemonic>
-    : sme2_clamp_vector_vg24_multi<sz, op1, u, multi_vector_ty, vector_ty,
+    : sme2_zip_clamp_vector_vg24_multi<sz, op1, u, multi_vector_ty, vector_ty,
                                    mnemonic>{
   bits<4> Zd;
   let Inst{4-1} = Zd;
 }
 
 multiclass sme2_fp_clamp_vector_vg2_multi<string mnemonic>{
-  def _H : sme2_clamp_vector_vg2_multi<0b01, 0b00, 0b0, ZZ_h_mul_r, ZPR16, mnemonic>;
-  def _S : sme2_clamp_vector_vg2_multi<0b10, 0b00, 0b0, ZZ_s_mul_r, ZPR32, mnemonic>;
-  def _D : sme2_clamp_vector_vg2_multi<0b11, 0b00, 0b0, ZZ_d_mul_r, ZPR64, mnemonic>;
+  def _H : sme2_zip_clamp_vector_vg2_multi<0b01, 0b000, 0b0, ZZ_h_mul_r, ZPR16, mnemonic>;
+  def _S : sme2_zip_clamp_vector_vg2_multi<0b10, 0b000, 0b0, ZZ_s_mul_r, ZPR32, mnemonic>;
+  def _D : sme2_zip_clamp_vector_vg2_multi<0b11, 0b000, 0b0, ZZ_d_mul_r, ZPR64, mnemonic>;
 }
 
 multiclass sme2_int_clamp_vector_vg2_multi<string mnemonic, bit u>{
-  def _B : sme2_clamp_vector_vg2_multi<0b00, 0b01, u, ZZ_b_mul_r, ZPR8, mnemonic>;
-  def _H : sme2_clamp_vector_vg2_multi<0b01, 0b01, u, ZZ_h_mul_r, ZPR16, mnemonic>;
-  def _S : sme2_clamp_vector_vg2_multi<0b10, 0b01, u, ZZ_s_mul_r, ZPR32, mnemonic>;
-  def _D : sme2_clamp_vector_vg2_multi<0b11, 0b01, u, ZZ_d_mul_r, ZPR64, mnemonic>;
+  def _B : sme2_zip_clamp_vector_vg2_multi<0b00, 0b001, u, ZZ_b_mul_r, ZPR8, mnemonic>;
+  def _H : sme2_zip_clamp_vector_vg2_multi<0b01, 0b001, u, ZZ_h_mul_r, ZPR16, mnemonic>;
+  def _S : sme2_zip_clamp_vector_vg2_multi<0b10, 0b001, u, ZZ_s_mul_r, ZPR32, mnemonic>;
+  def _D : sme2_zip_clamp_vector_vg2_multi<0b11, 0b001, u, ZZ_d_mul_r, ZPR64, mnemonic>;
 }
 
-class sme2_clamp_vector_vg4_multi<bits<2> sz, bits<2> op1, bit u,
+multiclass sme2_zip_vector_vg2<string mnemonic, bit op> {
+  def _B : sme2_zip_clamp_vector_vg2_multi<0b00, 0b100, op, ZZ_b_mul_r, ZPR8, mnemonic>;
+  def _H : sme2_zip_clamp_vector_vg2_multi<0b01, 0b100, op, ZZ_h_mul_r, ZPR16, mnemonic>;
+  def _S : sme2_zip_clamp_vector_vg2_multi<0b10, 0b100, op, ZZ_s_mul_r, ZPR32, mnemonic>;
+  def _D : sme2_zip_clamp_vector_vg2_multi<0b11, 0b100, op, ZZ_d_mul_r, ZPR64, mnemonic>;
+  def _Q : sme2_zip_clamp_vector_vg2_multi<0b00, 0b101, op, ZZ_q_mul_r, ZPR128, mnemonic>;
+}
+
+class sme2_clamp_vector_vg4_multi<bits<2> sz, bits<3> op1, bit u,
                                   RegisterOperand multi_vector_ty,
                                   ZPRRegOp vector_ty, string mnemonic>
-    : sme2_clamp_vector_vg24_multi<sz, op1, u,  multi_vector_ty, vector_ty,
+    : sme2_zip_clamp_vector_vg24_multi<sz, op1, u,  multi_vector_ty, vector_ty,
                                    mnemonic>{
   bits<3> Zd;
   let Inst{4-2} = Zd;
   let Inst{1}   = 0b0;
 }
 
 multiclass sme2_fp_clamp_vector_vg4_multi<string mnemonic>{
-  def _H : sme2_clamp_vector_vg4_multi<0b01, 0b10, 0b0, ZZZZ_h_mul_r, ZPR16, mnemonic>;
-  def _S : sme2_clamp_vector_vg4_multi<0b10, 0b10, 0b0, ZZZZ_s_mul_r, ZPR32, mnemonic>;
-  def _D : sme2_clamp_vector_vg4_multi<0b11, 0b10, 0b0, ZZZZ_d_mul_r, ZPR64, mnemonic>;
+  def _H : sme2_clamp_vector_vg4_multi<0b01, 0b010, 0b0, ZZZZ_h_mul_r, ZPR16, mnemonic>;
+  def _S : sme2_clamp_vector_vg4_multi<0b10, 0b010, 0b0, ZZZZ_s_mul_r, ZPR32, mnemonic>;
+  def _D : sme2_clamp_vector_vg4_multi<0b11, 0b010, 0b0, ZZZZ_d_mul_r, ZPR64, mnemonic>;
 }
 
 multiclass sme2_int_clamp_vector_vg4_multi<string mnemonic, bit u>{
-  def _B : sme2_clamp_vector_vg4_multi<0b00, 0b11, u, ZZZZ_b_mul_r, ZPR8, mnemonic>;
-  def _H : sme2_clamp_vector_vg4_multi<0b01, 0b11, u, ZZZZ_h_mul_r, ZPR16, mnemonic>;
-  def _S : sme2_clamp_vector_vg4_multi<0b10, 0b11, u, ZZZZ_s_mul_r, ZPR32, mnemonic>;
-  def _D : sme2_clamp_vector_vg4_multi<0b11, 0b11, u, ZZZZ_d_mul_r, ZPR64, mnemonic>;
+  def _B : sme2_clamp_vector_vg4_multi<0b00, 0b011, u, ZZZZ_b_mul_r, ZPR8, mnemonic>;
+  def _H : sme2_clamp_vector_vg4_multi<0b01, 0b011, u, ZZZZ_h_mul_r, ZPR16, mnemonic>;
+  def _S : sme2_clamp_vector_vg4_multi<0b10, 0b011, u, ZZZZ_s_mul_r, ZPR32, mnemonic>;
+  def _D : sme2_clamp_vector_vg4_multi<0b11, 0b011, u, ZZZZ_d_mul_r, ZPR64, mnemonic>;
 }
 
 //===----------------------------------------------------------------------===//
 // SME2 Dot Products and MLA
 
 // SME2 multi-vec ternary indexed two registers 32-bit
 class sme2_multi_vec_array_vg2_index_32b<bits<4> op,
                                          RegisterOperand multi_vector_ty,
class sme2_luti4_vector_vg4_index<bits<2> sz, RegisterOperand vector_ty,
   bits<1> i;
   let Inst{16}    = i;
 }
 
 multiclass sme2_luti4_vector_vg4_index<string mnemonic> {
   def _H : sme2_luti4_vector_vg4_index<0b01, ZZZZ_h_mul_r, mnemonic>;
   def _S : sme2_luti4_vector_vg4_index<0b10, ZZZZ_s_mul_r, mnemonic>;
 }
+

llvm/test/MC/AArch64/SME2/frinta-diagnostics.s

+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 2>&1 < %s | FileCheck %s
+
+// --------------------------------------------------------------------------//
+// Invalid vector list
+
+frinta {z0.s-z1.s}, {z0.s-z2.s}
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: frinta {z0.s-z1.s}, {z0.s-z2.s}
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+frinta {z1.s-z2.s}, {z0.s-z1.s}
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors, where the first vector is a multiple of 2 and with matching element types
+// CHECK-NEXT: frinta {z1.s-z2.s}, {z0.s-z1.s}
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Invalid Register Suffix
+
+frinta {z0.s-z1.s}, {z2.d-z3.d}
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: frinta {z0.s-z1.s}, {z2.d-z3.d}
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/test/MC/AArch64/SME2/frinta.s

+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
+// RUN:        | llvm-objdump -d --mattr=+sme2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
+// RUN:        | llvm-objdump -d --mattr=-sme2 - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
+// RUN:        | sed '/.text/d' | sed 's/.*encoding: //g' \
+// RUN:        | llvm-mc -triple=aarch64 -mattr=+sme2 -disassemble -show-encoding \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+
+
+frinta  {z0.s - z1.s}, {z0.s - z1.s}  // 11000001-10101100-11100000-00000000
+// CHECK-INST: frinta  { z0.s, z1.s }, { z0.s, z1.s }
+// CHECK-ENCODING: [0x00,0xe0,0xac,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1ace000 <unknown>
+
+frinta  {z20.s - z21.s}, {z10.s - z11.s}  // 11000001-10101100-11100001-01010100
+// CHECK-INST: frinta  { z20.s, z21.s }, { z10.s, z11.s }
+// CHECK-ENCODING: [0x54,0xe1,0xac,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1ace154 <unknown>
+
+frinta  {z22.s - z23.s}, {z12.s - z13.s}  // 11000001-10101100-11100001-10010110
+// CHECK-INST: frinta  { z22.s, z23.s }, { z12.s, z13.s }
+// CHECK-ENCODING: [0x96,0xe1,0xac,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1ace196 <unknown>
+
+frinta  {z30.s - z31.s}, {z30.s - z31.s}  // 11000001-10101100-11100011-11011110
+// CHECK-INST: frinta  { z30.s, z31.s }, { z30.s, z31.s }
+// CHECK-ENCODING: [0xde,0xe3,0xac,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1ace3de <unknown>
+
+
+frinta  {z0.s - z3.s}, {z0.s - z3.s}  // 11000001-10111100-11100000-00000000
+// CHECK-INST: frinta  { z0.s - z3.s }, { z0.s - z3.s }
+// CHECK-ENCODING: [0x00,0xe0,0xbc,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1bce000 <unknown>
+
+frinta  {z20.s - z23.s}, {z8.s - z11.s}  // 11000001-10111100-11100001-00010100
+// CHECK-INST: frinta  { z20.s - z23.s }, { z8.s - z11.s }
+// CHECK-ENCODING: [0x14,0xe1,0xbc,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1bce114 <unknown>
+
+frinta  {z20.s - z23.s}, {z12.s - z15.s}  // 11000001-10111100-11100001-10010100
+// CHECK-INST: frinta  { z20.s - z23.s }, { z12.s - z15.s }
+// CHECK-ENCODING: [0x94,0xe1,0xbc,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1bce194 <unknown>
+
+frinta  {z28.s - z31.s}, {z28.s - z31.s}  // 11000001-10111100-11100011-10011100
+// CHECK-INST: frinta  { z28.s - z31.s }, { z28.s - z31.s }
+// CHECK-ENCODING: [0x9c,0xe3,0xbc,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1bce39c <unknown>

llvm/test/MC/AArch64/SME2/frintm-diagnostics.s

+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 2>&1 < %s | FileCheck %s
+
+// --------------------------------------------------------------------------//
+// Invalid vector list
+
+frintm {z0.s-z1.s}, {z0.s-z2.s}
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: frintm {z0.s-z1.s}, {z0.s-z2.s}
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+frintm {z1.s-z2.s}, {z0.s-z1.s}
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors, where the first vector is a multiple of 2 and with matching element types
+// CHECK-NEXT: frintm {z1.s-z2.s}, {z0.s-z1.s}
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Invalid Register Suffix
+
+frintm {z0.s-z1.s}, {z2.d-z3.d}
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: frintm {z0.s-z1.s}, {z2.d-z3.d}
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/test/MC/AArch64/SME2/frintm.s

+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
+// RUN:        | llvm-objdump -d --mattr=+sme2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
+// RUN:        | llvm-objdump -d --mattr=-sme2 - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
+// RUN:        | sed '/.text/d' | sed 's/.*encoding: //g' \
+// RUN:        | llvm-mc -triple=aarch64 -mattr=+sme2 -disassemble -show-encoding \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+
+
+frintm  {z0.s - z1.s}, {z0.s - z1.s}  // 11000001-10101010-11100000-00000000
+// CHECK-INST: frintm  { z0.s, z1.s }, { z0.s, z1.s }
+// CHECK-ENCODING: [0x00,0xe0,0xaa,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1aae000 <unknown>
+
+frintm  {z20.s - z21.s}, {z10.s - z11.s}  // 11000001-10101010-11100001-01010100
+// CHECK-INST: frintm  { z20.s, z21.s }, { z10.s, z11.s }
+// CHECK-ENCODING: [0x54,0xe1,0xaa,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1aae154 <unknown>
+
+frintm  {z22.s - z23.s}, {z12.s - z13.s}  // 11000001-10101010-11100001-10010110
+// CHECK-INST: frintm  { z22.s, z23.s }, { z12.s, z13.s }
+// CHECK-ENCODING: [0x96,0xe1,0xaa,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1aae196 <unknown>
+
+frintm  {z30.s - z31.s}, {z30.s - z31.s}  // 11000001-10101010-11100011-11011110
+// CHECK-INST: frintm  { z30.s, z31.s }, { z30.s, z31.s }
+// CHECK-ENCODING: [0xde,0xe3,0xaa,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1aae3de <unknown>
+
+
+frintm  {z0.s - z3.s}, {z0.s - z3.s}  // 11000001-10111010-11100000-00000000
+// CHECK-INST: frintm  { z0.s - z3.s }, { z0.s - z3.s }
+// CHECK-ENCODING: [0x00,0xe0,0xba,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1bae000 <unknown>
+
+frintm  {z20.s - z23.s}, {z8.s - z11.s}  // 11000001-10111010-11100001-00010100
+// CHECK-INST: frintm  { z20.s - z23.s }, { z8.s - z11.s }
+// CHECK-ENCODING: [0x14,0xe1,0xba,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1bae114 <unknown>
+
+frintm  {z20.s - z23.s}, {z12.s - z15.s}  // 11000001-10111010-11100001-10010100
+// CHECK-INST: frintm  { z20.s - z23.s }, { z12.s - z15.s }
+// CHECK-ENCODING: [0x94,0xe1,0xba,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1bae194 <unknown>
+
+frintm  {z28.s - z31.s}, {z28.s - z31.s}  // 11000001-10111010-11100011-10011100
+// CHECK-INST: frintm  { z28.s - z31.s }, { z28.s - z31.s }
+// CHECK-ENCODING: [0x9c,0xe3,0xba,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1bae39c <unknown>
+

llvm/test/MC/AArch64/SME2/frintn-diagnostics.s

+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 2>&1 < %s | FileCheck %s
+
+// --------------------------------------------------------------------------//
+// Invalid vector list
+
+frintn {z0.s-z1.s}, {z0.s-z2.s}
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: frintn {z0.s-z1.s}, {z0.s-z2.s}
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+frintn {z1.s-z2.s}, {z0.s-z1.s}
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors, where the first vector is a multiple of 2 and with matching element types
+// CHECK-NEXT: frintn {z1.s-z2.s}, {z0.s-z1.s}
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Invalid Register Suffix
+
+frintn {z0.s-z1.s}, {z2.d-z3.d}
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: frintn {z0.s-z1.s}, {z2.d-z3.d}
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/test/MC/AArch64/SME2/frintn.s

+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
+// RUN:        | llvm-objdump -d --mattr=+sme2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
+// RUN:        | llvm-objdump -d --mattr=-sme2 - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
+// RUN:        | sed '/.text/d' | sed 's/.*encoding: //g' \
+// RUN:        | llvm-mc -triple=aarch64 -mattr=+sme2 -disassemble -show-encoding \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+
+
+frintn  {z0.s - z1.s}, {z0.s - z1.s}  // 11000001-10101000-11100000-00000000
+// CHECK-INST: frintn  { z0.s, z1.s }, { z0.s, z1.s }
+// CHECK-ENCODING: [0x00,0xe0,0xa8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a8e000 <unknown>
+
+frintn  {z20.s - z21.s}, {z10.s - z11.s}  // 11000001-10101000-11100001-01010100
+// CHECK-INST: frintn  { z20.s, z21.s }, { z10.s, z11.s }
+// CHECK-ENCODING: [0x54,0xe1,0xa8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a8e154 <unknown>
+
+frintn  {z22.s - z23.s}, {z12.s - z13.s}  // 11000001-10101000-11100001-10010110
+// CHECK-INST: frintn  { z22.s, z23.s }, { z12.s, z13.s }
+// CHECK-ENCODING: [0x96,0xe1,0xa8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a8e196 <unknown>
+
+frintn  {z30.s - z31.s}, {z30.s - z31.s}  // 11000001-10101000-11100011-11011110
+// CHECK-INST: frintn  { z30.s, z31.s }, { z30.s, z31.s }
+// CHECK-ENCODING: [0xde,0xe3,0xa8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a8e3de <unknown>
+
+
+frintn  {z0.s - z3.s}, {z0.s - z3.s}  // 11000001-10111000-11100000-00000000
+// CHECK-INST: frintn  { z0.s - z3.s }, { z0.s - z3.s }
+// CHECK-ENCODING: [0x00,0xe0,0xb8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1b8e000 <unknown>
+
+frintn  {z20.s - z23.s}, {z8.s - z11.s}  // 11000001-10111000-11100001-00010100
+// CHECK-INST: frintn  { z20.s - z23.s }, { z8.s - z11.s }
+// CHECK-ENCODING: [0x14,0xe1,0xb8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1b8e114 <unknown>
+
+frintn  {z20.s - z23.s}, {z12.s - z15.s}  // 11000001-10111000-11100001-10010100
+// CHECK-INST: frintn  { z20.s - z23.s }, { z12.s - z15.s }
+// CHECK-ENCODING: [0x94,0xe1,0xb8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1b8e194 <unknown>
+
+frintn  {z28.s - z31.s}, {z28.s - z31.s}  // 11000001-10111000-11100011-10011100
+// CHECK-INST: frintn  { z28.s - z31.s }, { z28.s - z31.s }
+// CHECK-ENCODING: [0x9c,0xe3,0xb8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1b8e39c <unknown>
+

llvm/test/MC/AArch64/SME2/frintp-diagnostics.s

+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 2>&1 < %s | FileCheck %s
+
+// --------------------------------------------------------------------------//
+// Invalid vector list
+
+frintp {z0.s-z1.s}, {z0.s-z2.s}
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: frintp {z0.s-z1.s}, {z0.s-z2.s}
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+frintp {z1.s-z2.s}, {z0.s-z1.s}
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors, where the first vector is a multiple of 2 and with matching element types
+// CHECK-NEXT: frintp {z1.s-z2.s}, {z0.s-z1.s}
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Invalid Register Suffix
+
+frintp {z0.s-z1.s}, {z2.d-z3.d}
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: frintp {z0.s-z1.s}, {z2.d-z3.d}
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/test/MC/AArch64/SME2/frintp.s

+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
+// RUN:        | llvm-objdump -d --mattr=+sme2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
+// RUN:        | llvm-objdump -d --mattr=-sme2 - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
+// RUN:        | sed '/.text/d' | sed 's/.*encoding: //g' \
+// RUN:        | llvm-mc -triple=aarch64 -mattr=+sme2 -disassemble -show-encoding \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+
+
+frintp  {z0.s - z1.s}, {z0.s - z1.s}  // 11000001-10101001-11100000-00000000
+// CHECK-INST: frintp  { z0.s, z1.s }, { z0.s, z1.s }
+// CHECK-ENCODING: [0x00,0xe0,0xa9,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a9e000 <unknown>
+
+frintp  {z20.s - z21.s}, {z10.s - z11.s}  // 11000001-10101001-11100001-01010100
+// CHECK-INST: frintp  { z20.s, z21.s }, { z10.s, z11.s }
+// CHECK-ENCODING: [0x54,0xe1,0xa9,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a9e154 <unknown>
+
+frintp  {z22.s - z23.s}, {z12.s - z13.s}  // 11000001-10101001-11100001-10010110
+// CHECK-INST: frintp  { z22.s, z23.s }, { z12.s, z13.s }
+// CHECK-ENCODING: [0x96,0xe1,0xa9,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a9e196 <unknown>
+
+frintp  {z30.s - z31.s}, {z30.s - z31.s}  // 11000001-10101001-11100011-11011110
+// CHECK-INST: frintp  { z30.s, z31.s }, { z30.s, z31.s }
+// CHECK-ENCODING: [0xde,0xe3,0xa9,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a9e3de <unknown>
+
+
+frintp  {z0.s - z3.s}, {z0.s - z3.s}  // 11000001-10111001-11100000-00000000
+// CHECK-INST: frintp  { z0.s - z3.s }, { z0.s - z3.s }
+// CHECK-ENCODING: [0x00,0xe0,0xb9,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1b9e000 <unknown>
+
+frintp  {z20.s - z23.s}, {z8.s - z11.s}  // 11000001-10111001-11100001-00010100
+// CHECK-INST: frintp  { z20.s - z23.s }, { z8.s - z11.s }
+// CHECK-ENCODING: [0x14,0xe1,0xb9,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1b9e114 <unknown>
+
+frintp  {z20.s - z23.s}, {z12.s - z15.s}  // 11000001-10111001-11100001-10010100
+// CHECK-INST: frintp  { z20.s - z23.s }, { z12.s - z15.s }
+// CHECK-ENCODING: [0x94,0xe1,0xb9,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1b9e194 <unknown>
+
+frintp  {z28.s - z31.s}, {z28.s - z31.s}  // 11000001-10111001-11100011-10011100
+// CHECK-INST: frintp  { z28.s - z31.s }, { z28.s - z31.s }
+// CHECK-ENCODING: [0x9c,0xe3,0xb9,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1b9e39c <unknown>

llvm/test/MC/AArch64/SME2/sunpk-diagnostics.s

+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 2>&1 < %s | FileCheck %s
+
+// --------------------------------------------------------------------------//
+// Invalid vector list
+
+sunpk {z0.h-z2.h}, z0.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: sunpk {z0.h-z2.h}, z0.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+sunpk {z1.s-z2.s}, z0.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors, where the first vector is a multiple of 2 and with matching element types
+// CHECK-NEXT: sunpk {z1.s-z2.s}, z0.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+sunpk {z0.d-z5.d}, {z8.s-z9.s}
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid number of vectors
+// CHECK-NEXT: sunpk {z0.d-z5.d}, {z8.s-z9.s}
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+sunpk {z0.s-z3.s}, {z9.h-z11.h}
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: sunpk {z0.s-z3.s}, {z9.h-z11.h}
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Invalid Register Suffix
+
+sunpk {z0.s-z3.s}, {z8.s-z9.s}
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: sunpk {z0.s-z3.s}, {z8.s-z9.s}
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/test/MC/AArch64/SME2/sunpk.s

+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
+// RUN:        | llvm-objdump -d --mattr=+sme2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
+// RUN:        | llvm-objdump -d --mattr=-sme2 - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
+// RUN:        | sed '/.text/d' | sed 's/.*encoding: //g' \
+// RUN:        | llvm-mc -triple=aarch64 -mattr=+sme2 -disassemble -show-encoding \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+
+
+sunpk   {z0.h - z1.h}, z0.b  // 11000001-01100101-11100000-00000000
+// CHECK-INST: sunpk   { z0.h, z1.h }, z0.b
+// CHECK-ENCODING: [0x00,0xe0,0x65,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c165e000 <unknown>
+
+sunpk   {z20.h - z21.h}, z10.b  // 11000001-01100101-11100001-01010100
+// CHECK-INST: sunpk   { z20.h, z21.h }, z10.b
+// CHECK-ENCODING: [0x54,0xe1,0x65,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c165e154 <unknown>
+
+sunpk   {z22.h - z23.h}, z13.b  // 11000001-01100101-11100001-10110110
+// CHECK-INST: sunpk   { z22.h, z23.h }, z13.b
+// CHECK-ENCODING: [0xb6,0xe1,0x65,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c165e1b6 <unknown>
+
+sunpk   {z30.h - z31.h}, z31.b  // 11000001-01100101-11100011-11111110
+// CHECK-INST: sunpk   { z30.h, z31.h }, z31.b
+// CHECK-ENCODING: [0xfe,0xe3,0x65,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c165e3fe <unknown>
+
+
+sunpk   {z0.s - z1.s}, z0.h  // 11000001-10100101-11100000-00000000
+// CHECK-INST: sunpk   { z0.s, z1.s }, z0.h
+// CHECK-ENCODING: [0x00,0xe0,0xa5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a5e000 <unknown>
+
+sunpk   {z20.s - z21.s}, z10.h  // 11000001-10100101-11100001-01010100
+// CHECK-INST: sunpk   { z20.s, z21.s }, z10.h
+// CHECK-ENCODING: [0x54,0xe1,0xa5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a5e154 <unknown>
+
+sunpk   {z22.s - z23.s}, z13.h  // 11000001-10100101-11100001-10110110
+// CHECK-INST: sunpk   { z22.s, z23.s }, z13.h
+// CHECK-ENCODING: [0xb6,0xe1,0xa5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a5e1b6 <unknown>
+
+sunpk   {z30.s - z31.s}, z31.h  // 11000001-10100101-11100011-11111110
+// CHECK-INST: sunpk   { z30.s, z31.s }, z31.h
+// CHECK-ENCODING: [0xfe,0xe3,0xa5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a5e3fe <unknown>
+
+
+sunpk   {z0.d - z1.d}, z0.s  // 11000001-11100101-11100000-00000000
+// CHECK-INST: sunpk   { z0.d, z1.d }, z0.s
+// CHECK-ENCODING: [0x00,0xe0,0xe5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e5e000 <unknown>
+
+sunpk   {z20.d - z21.d}, z10.s  // 11000001-11100101-11100001-01010100
+// CHECK-INST: sunpk   { z20.d, z21.d }, z10.s
+// CHECK-ENCODING: [0x54,0xe1,0xe5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e5e154 <unknown>
+
+sunpk   {z22.d - z23.d}, z13.s  // 11000001-11100101-11100001-10110110
+// CHECK-INST: sunpk   { z22.d, z23.d }, z13.s
+// CHECK-ENCODING: [0xb6,0xe1,0xe5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e5e1b6 <unknown>
+
+sunpk   {z30.d - z31.d}, z31.s  // 11000001-11100101-11100011-11111110
+// CHECK-INST: sunpk   { z30.d, z31.d }, z31.s
+// CHECK-ENCODING: [0xfe,0xe3,0xe5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e5e3fe <unknown>
+
+
+sunpk   {z0.h - z3.h}, {z0.b - z1.b}  // 11000001-01110101-11100000-00000000
+// CHECK-INST: sunpk   { z0.h - z3.h }, { z0.b, z1.b }
+// CHECK-ENCODING: [0x00,0xe0,0x75,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c175e000 <unknown>
+
+sunpk   {z20.h - z23.h}, {z10.b - z11.b}  // 11000001-01110101-11100001-01010100
+// CHECK-INST: sunpk   { z20.h - z23.h }, { z10.b, z11.b }
+// CHECK-ENCODING: [0x54,0xe1,0x75,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c175e154 <unknown>
+
+sunpk   {z20.h - z23.h}, {z12.b - z13.b}  // 11000001-01110101-11100001-10010100
+// CHECK-INST: sunpk   { z20.h - z23.h }, { z12.b, z13.b }
+// CHECK-ENCODING: [0x94,0xe1,0x75,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c175e194 <unknown>
+
+sunpk   {z28.h - z31.h}, {z30.b - z31.b}  // 11000001-01110101-11100011-11011100
+// CHECK-INST: sunpk   { z28.h - z31.h }, { z30.b, z31.b }
+// CHECK-ENCODING: [0xdc,0xe3,0x75,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c175e3dc <unknown>
+
+
+sunpk   {z0.s - z3.s}, {z0.h - z1.h}  // 11000001-10110101-11100000-00000000
+// CHECK-INST: sunpk   { z0.s - z3.s }, { z0.h, z1.h }
+// CHECK-ENCODING: [0x00,0xe0,0xb5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1b5e000 <unknown>
+
+sunpk   {z20.s - z23.s}, {z10.h - z11.h}  // 11000001-10110101-11100001-01010100
+// CHECK-INST: sunpk   { z20.s - z23.s }, { z10.h, z11.h }
+// CHECK-ENCODING: [0x54,0xe1,0xb5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1b5e154 <unknown>
+
+sunpk   {z20.s - z23.s}, {z12.h - z13.h}  // 11000001-10110101-11100001-10010100
+// CHECK-INST: sunpk   { z20.s - z23.s }, { z12.h, z13.h }
+// CHECK-ENCODING: [0x94,0xe1,0xb5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1b5e194 <unknown>
+
+sunpk   {z28.s - z31.s}, {z30.h - z31.h}  // 11000001-10110101-11100011-11011100
+// CHECK-INST: sunpk   { z28.s - z31.s }, { z30.h, z31.h }
+// CHECK-ENCODING: [0xdc,0xe3,0xb5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1b5e3dc <unknown>
+
+
+sunpk   {z0.d - z3.d}, {z0.s - z1.s}  // 11000001-11110101-11100000-00000000
+// CHECK-INST: sunpk   { z0.d - z3.d }, { z0.s, z1.s }
+// CHECK-ENCODING: [0x00,0xe0,0xf5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1f5e000 <unknown>
+
+sunpk   {z20.d - z23.d}, {z10.s - z11.s}  // 11000001-11110101-11100001-01010100
+// CHECK-INST: sunpk   { z20.d - z23.d }, { z10.s, z11.s }
+// CHECK-ENCODING: [0x54,0xe1,0xf5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1f5e154 <unknown>
+
+sunpk   {z20.d - z23.d}, {z12.s - z13.s}  // 11000001-11110101-11100001-10010100
+// CHECK-INST: sunpk   { z20.d - z23.d }, { z12.s, z13.s }
+// CHECK-ENCODING: [0x94,0xe1,0xf5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1f5e194 <unknown>
+
+sunpk   {z28.d - z31.d}, {z30.s - z31.s}  // 11000001-11110101-11100011-11011100
+// CHECK-INST: sunpk   { z28.d - z31.d }, { z30.s, z31.s }
+// CHECK-ENCODING: [0xdc,0xe3,0xf5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1f5e3dc <unknown>
+

llvm/test/MC/AArch64/SME2/uunpk-diagnostics.s

+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 2>&1 < %s | FileCheck %s
+
+// --------------------------------------------------------------------------//
+// Invalid vector list
+
+uunpk {z0.h-z2.h}, z0.b
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: uunpk {z0.h-z2.h}, z0.b
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+uunpk {z1.s-z2.s}, z0.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors, where the first vector is a multiple of 2 and with matching element types
+// CHECK-NEXT: uunpk {z1.s-z2.s}, z0.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+uunpk {z0.d-z5.d}, {z8.s-z9.s}
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid number of vectors
+// CHECK-NEXT: uunpk {z0.d-z5.d}, {z8.s-z9.s}
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+uunpk {z0.s-z3.s}, {z9.h-z11.h}
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: uunpk {z0.s-z3.s}, {z9.h-z11.h}
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+// --------------------------------------------------------------------------//
+// Invalid Register Suffix
+
+uunpk {z0.s-z3.s}, {z8.s-z9.s}
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: uunpk {z0.s-z3.s}, {z8.s-z9.s}
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:

llvm/test/MC/AArch64/SME2/uunpk.s

+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
+// RUN:        | llvm-objdump -d --mattr=+sme2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
+// RUN:        | llvm-objdump -d --mattr=-sme2 - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
+// RUN:        | sed '/.text/d' | sed 's/.*encoding: //g' \
+// RUN:        | llvm-mc -triple=aarch64 -mattr=+sme2 -disassemble -show-encoding \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+
+
+uunpk   {z0.h - z1.h}, z0.b  // 11000001-01100101-11100000-00000001
+// CHECK-INST: uunpk   { z0.h, z1.h }, z0.b
+// CHECK-ENCODING: [0x01,0xe0,0x65,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c165e001 <unknown>
+
+uunpk   {z20.h - z21.h}, z10.b  // 11000001-01100101-11100001-01010101
+// CHECK-INST: uunpk   { z20.h, z21.h }, z10.b
+// CHECK-ENCODING: [0x55,0xe1,0x65,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c165e155 <unknown>
+
+uunpk   {z22.h - z23.h}, z13.b  // 11000001-01100101-11100001-10110111
+// CHECK-INST: uunpk   { z22.h, z23.h }, z13.b
+// CHECK-ENCODING: [0xb7,0xe1,0x65,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c165e1b7 <unknown>
+
+uunpk   {z30.h - z31.h}, z31.b  // 11000001-01100101-11100011-11111111
+// CHECK-INST: uunpk   { z30.h, z31.h }, z31.b
+// CHECK-ENCODING: [0xff,0xe3,0x65,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c165e3ff <unknown>
+
+
+uunpk   {z0.s - z1.s}, z0.h  // 11000001-10100101-11100000-00000001
+// CHECK-INST: uunpk   { z0.s, z1.s }, z0.h
+// CHECK-ENCODING: [0x01,0xe0,0xa5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a5e001 <unknown>
+
+uunpk   {z20.s - z21.s}, z10.h  // 11000001-10100101-11100001-01010101
+// CHECK-INST: uunpk   { z20.s, z21.s }, z10.h
+// CHECK-ENCODING: [0x55,0xe1,0xa5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a5e155 <unknown>
+
+uunpk   {z22.s - z23.s}, z13.h  // 11000001-10100101-11100001-10110111
+// CHECK-INST: uunpk   { z22.s, z23.s }, z13.h
+// CHECK-ENCODING: [0xb7,0xe1,0xa5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a5e1b7 <unknown>
+
+uunpk   {z30.s - z31.s}, z31.h  // 11000001-10100101-11100011-11111111
+// CHECK-INST: uunpk   { z30.s, z31.s }, z31.h
+// CHECK-ENCODING: [0xff,0xe3,0xa5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a5e3ff <unknown>
+
+
+uunpk   {z0.d - z1.d}, z0.s  // 11000001-11100101-11100000-00000001
+// CHECK-INST: uunpk   { z0.d, z1.d }, z0.s
+// CHECK-ENCODING: [0x01,0xe0,0xe5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e5e001 <unknown>
+
+uunpk   {z20.d - z21.d}, z10.s  // 11000001-11100101-11100001-01010101
+// CHECK-INST: uunpk   { z20.d, z21.d }, z10.s
+// CHECK-ENCODING: [0x55,0xe1,0xe5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e5e155 <unknown>
+
+uunpk   {z22.d - z23.d}, z13.s  // 11000001-11100101-11100001-10110111
+// CHECK-INST: uunpk   { z22.d, z23.d }, z13.s
+// CHECK-ENCODING: [0xb7,0xe1,0xe5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e5e1b7 <unknown>
+
+uunpk   {z30.d - z31.d}, z31.s  // 11000001-11100101-11100011-11111111
+// CHECK-INST: uunpk   { z30.d, z31.d }, z31.s
+// CHECK-ENCODING: [0xff,0xe3,0xe5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e5e3ff <unknown>
+
+
+uunpk   {z0.h - z3.h}, {z0.b - z1.b}  // 11000001-01110101-11100000-00000001
+// CHECK-INST: uunpk   { z0.h - z3.h }, { z0.b, z1.b }
+// CHECK-ENCODING: [0x01,0xe0,0x75,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c175e001 <unknown>
+
+uunpk   {z20.h - z23.h}, {z10.b - z11.b}  // 11000001-01110101-11100001-01010101
+// CHECK-INST: uunpk   { z20.h - z23.h }, { z10.b, z11.b }
+// CHECK-ENCODING: [0x55,0xe1,0x75,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c175e155 <unknown>
+
+uunpk   {z20.h - z23.h}, {z12.b - z13.b}  // 11000001-01110101-11100001-10010101
+// CHECK-INST: uunpk   { z20.h - z23.h }, { z12.b, z13.b }
+// CHECK-ENCODING: [0x95,0xe1,0x75,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c175e195 <unknown>
+
+uunpk   {z28.h - z31.h}, {z30.b - z31.b}  // 11000001-01110101-11100011-11011101
+// CHECK-INST: uunpk   { z28.h - z31.h }, { z30.b, z31.b }
+// CHECK-ENCODING: [0xdd,0xe3,0x75,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c175e3dd <unknown>
+
+
+uunpk   {z0.s - z3.s}, {z0.h - z1.h}  // 11000001-10110101-11100000-00000001
+// CHECK-INST: uunpk   { z0.s - z3.s }, { z0.h, z1.h }
+// CHECK-ENCODING: [0x01,0xe0,0xb5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1b5e001 <unknown>
+
+uunpk   {z20.s - z23.s}, {z10.h - z11.h}  // 11000001-10110101-11100001-01010101
+// CHECK-INST: uunpk   { z20.s - z23.s }, { z10.h, z11.h }
+// CHECK-ENCODING: [0x55,0xe1,0xb5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1b5e155 <unknown>
+
+uunpk   {z20.s - z23.s}, {z12.h - z13.h}  // 11000001-10110101-11100001-10010101
+// CHECK-INST: uunpk   { z20.s - z23.s }, { z12.h, z13.h }
+// CHECK-ENCODING: [0x95,0xe1,0xb5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1b5e195 <unknown>
+
+uunpk   {z28.s - z31.s}, {z30.h - z31.h}  // 11000001-10110101-11100011-11011101
+// CHECK-INST: uunpk   { z28.s - z31.s }, { z30.h, z31.h }
+// CHECK-ENCODING: [0xdd,0xe3,0xb5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1b5e3dd <unknown>
+
+
+uunpk   {z0.d - z3.d}, {z0.s - z1.s}  // 11000001-11110101-11100000-00000001
+// CHECK-INST: uunpk   { z0.d - z3.d }, { z0.s, z1.s }
+// CHECK-ENCODING: [0x01,0xe0,0xf5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1f5e001 <unknown>
+
+uunpk   {z20.d - z23.d}, {z10.s - z11.s}  // 11000001-11110101-11100001-01010101
+// CHECK-INST: uunpk   { z20.d - z23.d }, { z10.s, z11.s }
+// CHECK-ENCODING: [0x55,0xe1,0xf5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1f5e155 <unknown>
+
+uunpk   {z20.d - z23.d}, {z12.s - z13.s}  // 11000001-11110101-11100001-10010101
+// CHECK-INST: uunpk   { z20.d - z23.d }, { z12.s, z13.s }
+// CHECK-ENCODING: [0x95,0xe1,0xf5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1f5e195 <unknown>
+
+uunpk   {z28.d - z31.d}, {z30.s - z31.s}  // 11000001-11110101-11100011-11011101
+// CHECK-INST: uunpk   { z28.d - z31.d }, { z30.s, z31.s }
+// CHECK-ENCODING: [0xdd,0xe3,0xf5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1f5e3dd <unknown>
+

llvm/test/MC/AArch64/SME2/uzp-diagnostics.s

+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 2>&1 < %s | FileCheck %s
+
+// --------------------------------------------------------------------------//
+// Invalid vector list
+
+uzp {z0.q-z2.q}, z0.q, z0.q
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: uzp {z0.q-z2.q}, z0.q, z0.q
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+uzp {z21.h-z22.h}, z10.h, z21.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors, where the first vector is a multiple of 2 and with matching element types
+// CHECK-NEXT: uzp {z21.h-z22.h}, z10.h, z21.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+uzp {z0.s-z4.s}, {z0.s-z3.s}
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid number of vectors
+// CHECK-NEXT: uzp {z0.s-z4.s}, {z0.s-z3.s}
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+uzp {z20.b-z23.b}, {z9.b-z12.b}
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 4 consecutive SVE vectors, where the first vector is a multiple of 4 and with matching element types
+// CHECK-NEXT: uzp {z20.b-z23.b}, {z9.b-z12.b}
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+

llvm/test/MC/AArch64/SME2/uzp.s

+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
+// RUN:        | llvm-objdump -d --mattr=+sme2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
+// RUN:        | llvm-objdump -d --mattr=-sme2 - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
+// RUN:        | sed '/.text/d' | sed 's/.*encoding: //g' \
+// RUN:        | llvm-mc -triple=aarch64 -mattr=+sme2 -disassemble -show-encoding \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+
+
+uzp     {z0.q - z1.q}, z0.q, z0.q  // 11000001-00100000-11010100-00000001
+// CHECK-INST: uzp     { z0.q, z1.q }, z0.q, z0.q
+// CHECK-ENCODING: [0x01,0xd4,0x20,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c120d401 <unknown>
+
+uzp     {z20.q - z21.q}, z10.q, z21.q  // 11000001-00110101-11010101-01010101
+// CHECK-INST: uzp     { z20.q, z21.q }, z10.q, z21.q
+// CHECK-ENCODING: [0x55,0xd5,0x35,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c135d555 <unknown>
+
+uzp     {z22.q - z23.q}, z13.q, z8.q  // 11000001-00101000-11010101-10110111
+// CHECK-INST: uzp     { z22.q, z23.q }, z13.q, z8.q
+// CHECK-ENCODING: [0xb7,0xd5,0x28,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c128d5b7 <unknown>
+
+uzp     {z30.q - z31.q}, z31.q, z31.q  // 11000001-00111111-11010111-11111111
+// CHECK-INST: uzp     { z30.q, z31.q }, z31.q, z31.q
+// CHECK-ENCODING: [0xff,0xd7,0x3f,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c13fd7ff <unknown>
+
+
+uzp     {z0.h - z1.h}, z0.h, z0.h  // 11000001-01100000-11010000-00000001
+// CHECK-INST: uzp     { z0.h, z1.h }, z0.h, z0.h
+// CHECK-ENCODING: [0x01,0xd0,0x60,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c160d001 <unknown>
+
+uzp     {z20.h - z21.h}, z10.h, z21.h  // 11000001-01110101-11010001-01010101
+// CHECK-INST: uzp     { z20.h, z21.h }, z10.h, z21.h
+// CHECK-ENCODING: [0x55,0xd1,0x75,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c175d155 <unknown>
+
+uzp     {z22.h - z23.h}, z13.h, z8.h  // 11000001-01101000-11010001-10110111
+// CHECK-INST: uzp     { z22.h, z23.h }, z13.h, z8.h
+// CHECK-ENCODING: [0xb7,0xd1,0x68,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c168d1b7 <unknown>
+
+uzp     {z30.h - z31.h}, z31.h, z31.h  // 11000001-01111111-11010011-11111111
+// CHECK-INST: uzp     { z30.h, z31.h }, z31.h, z31.h
+// CHECK-ENCODING: [0xff,0xd3,0x7f,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c17fd3ff <unknown>
+
+
+uzp     {z0.s - z1.s}, z0.s, z0.s  // 11000001-10100000-11010000-00000001
+// CHECK-INST: uzp     { z0.s, z1.s }, z0.s, z0.s
+// CHECK-ENCODING: [0x01,0xd0,0xa0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a0d001 <unknown>
+
+uzp     {z20.s - z21.s}, z10.s, z21.s  // 11000001-10110101-11010001-01010101
+// CHECK-INST: uzp     { z20.s, z21.s }, z10.s, z21.s
+// CHECK-ENCODING: [0x55,0xd1,0xb5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1b5d155 <unknown>
+
+uzp     {z22.s - z23.s}, z13.s, z8.s  // 11000001-10101000-11010001-10110111
+// CHECK-INST: uzp     { z22.s, z23.s }, z13.s, z8.s
+// CHECK-ENCODING: [0xb7,0xd1,0xa8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a8d1b7 <unknown>
+
+uzp     {z30.s - z31.s}, z31.s, z31.s  // 11000001-10111111-11010011-11111111
+// CHECK-INST: uzp     { z30.s, z31.s }, z31.s, z31.s
+// CHECK-ENCODING: [0xff,0xd3,0xbf,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1bfd3ff <unknown>
+
+
+uzp     {z0.d - z1.d}, z0.d, z0.d  // 11000001-11100000-11010000-00000001
+// CHECK-INST: uzp     { z0.d, z1.d }, z0.d, z0.d
+// CHECK-ENCODING: [0x01,0xd0,0xe0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e0d001 <unknown>
+
+uzp     {z20.d - z21.d}, z10.d, z21.d  // 11000001-11110101-11010001-01010101
+// CHECK-INST: uzp     { z20.d, z21.d }, z10.d, z21.d
+// CHECK-ENCODING: [0x55,0xd1,0xf5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1f5d155 <unknown>
+
+uzp     {z22.d - z23.d}, z13.d, z8.d  // 11000001-11101000-11010001-10110111
+// CHECK-INST: uzp     { z22.d, z23.d }, z13.d, z8.d
+// CHECK-ENCODING: [0xb7,0xd1,0xe8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e8d1b7 <unknown>
+
+uzp     {z30.d - z31.d}, z31.d, z31.d  // 11000001-11111111-11010011-11111111
+// CHECK-INST: uzp     { z30.d, z31.d }, z31.d, z31.d
+// CHECK-ENCODING: [0xff,0xd3,0xff,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1ffd3ff <unknown>
+
+
+uzp     {z0.b - z1.b}, z0.b, z0.b  // 11000001-00100000-11010000-00000001
+// CHECK-INST: uzp     { z0.b, z1.b }, z0.b, z0.b
+// CHECK-ENCODING: [0x01,0xd0,0x20,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c120d001 <unknown>
+
+uzp     {z20.b - z21.b}, z10.b, z21.b  // 11000001-00110101-11010001-01010101
+// CHECK-INST: uzp     { z20.b, z21.b }, z10.b, z21.b
+// CHECK-ENCODING: [0x55,0xd1,0x35,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c135d155 <unknown>
+
+uzp     {z22.b - z23.b}, z13.b, z8.b  // 11000001-00101000-11010001-10110111
+// CHECK-INST: uzp     { z22.b, z23.b }, z13.b, z8.b
+// CHECK-ENCODING: [0xb7,0xd1,0x28,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c128d1b7 <unknown>
+
+uzp     {z30.b - z31.b}, z31.b, z31.b  // 11000001-00111111-11010011-11111111
+// CHECK-INST: uzp     { z30.b, z31.b }, z31.b, z31.b
+// CHECK-ENCODING: [0xff,0xd3,0x3f,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c13fd3ff <unknown>
+
+
+uzp     {z0.q - z3.q}, {z0.q - z3.q}  // 11000001-00110111-11100000-00000010
+// CHECK-INST: uzp     { z0.q - z3.q }, { z0.q - z3.q }
+// CHECK-ENCODING: [0x02,0xe0,0x37,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c137e002 <unknown>
+
+uzp     {z20.q - z23.q}, {z8.q - z11.q}  // 11000001-00110111-11100001-00010110
+// CHECK-INST: uzp     { z20.q - z23.q }, { z8.q - z11.q }
+// CHECK-ENCODING: [0x16,0xe1,0x37,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c137e116 <unknown>
+
+uzp     {z20.q - z23.q}, {z12.q - z15.q}  // 11000001-00110111-11100001-10010110
+// CHECK-INST: uzp     { z20.q - z23.q }, { z12.q - z15.q }
+// CHECK-ENCODING: [0x96,0xe1,0x37,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c137e196 <unknown>
+
+uzp     {z28.q - z31.q}, {z28.q - z31.q}  // 11000001-00110111-11100011-10011110
+// CHECK-INST: uzp     { z28.q - z31.q }, { z28.q - z31.q }
+// CHECK-ENCODING: [0x9e,0xe3,0x37,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c137e39e <unknown>
+
+
+uzp     {z0.h - z3.h}, {z0.h - z3.h}  // 11000001-01110110-11100000-00000010
+// CHECK-INST: uzp     { z0.h - z3.h }, { z0.h - z3.h }
+// CHECK-ENCODING: [0x02,0xe0,0x76,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c176e002 <unknown>
+
+uzp     {z20.h - z23.h}, {z8.h - z11.h}  // 11000001-01110110-11100001-00010110
+// CHECK-INST: uzp     { z20.h - z23.h }, { z8.h - z11.h }
+// CHECK-ENCODING: [0x16,0xe1,0x76,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c176e116 <unknown>
+
+uzp     {z20.h - z23.h}, {z12.h - z15.h}  // 11000001-01110110-11100001-10010110
+// CHECK-INST: uzp     { z20.h - z23.h }, { z12.h - z15.h }
+// CHECK-ENCODING: [0x96,0xe1,0x76,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c176e196 <unknown>
+
+uzp     {z28.h - z31.h}, {z28.h - z31.h}  // 11000001-01110110-11100011-10011110
+// CHECK-INST: uzp     { z28.h - z31.h }, { z28.h - z31.h }
+// CHECK-ENCODING: [0x9e,0xe3,0x76,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c176e39e <unknown>
+
+
+uzp     {z0.s - z3.s}, {z0.s - z3.s}  // 11000001-10110110-11100000-00000010
+// CHECK-INST: uzp     { z0.s - z3.s }, { z0.s - z3.s }
+// CHECK-ENCODING: [0x02,0xe0,0xb6,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1b6e002 <unknown>
+
+uzp     {z20.s - z23.s}, {z8.s - z11.s}  // 11000001-10110110-11100001-00010110
+// CHECK-INST: uzp     { z20.s - z23.s }, { z8.s - z11.s }
+// CHECK-ENCODING: [0x16,0xe1,0xb6,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1b6e116 <unknown>
+
+uzp     {z20.s - z23.s}, {z12.s - z15.s}  // 11000001-10110110-11100001-10010110
+// CHECK-INST: uzp     { z20.s - z23.s }, { z12.s - z15.s }
+// CHECK-ENCODING: [0x96,0xe1,0xb6,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1b6e196 <unknown>
+
+uzp     {z28.s - z31.s}, {z28.s - z31.s}  // 11000001-10110110-11100011-10011110
+// CHECK-INST: uzp     { z28.s - z31.s }, { z28.s - z31.s }
+// CHECK-ENCODING: [0x9e,0xe3,0xb6,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1b6e39e <unknown>
+
+
+uzp     {z0.d - z3.d}, {z0.d - z3.d}  // 11000001-11110110-11100000-00000010
+// CHECK-INST: uzp     { z0.d - z3.d }, { z0.d - z3.d }
+// CHECK-ENCODING: [0x02,0xe0,0xf6,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1f6e002 <unknown>
+
+uzp     {z20.d - z23.d}, {z8.d - z11.d}  // 11000001-11110110-11100001-00010110
+// CHECK-INST: uzp     { z20.d - z23.d }, { z8.d - z11.d }
+// CHECK-ENCODING: [0x16,0xe1,0xf6,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1f6e116 <unknown>
+
+uzp     {z20.d - z23.d}, {z12.d - z15.d}  // 11000001-11110110-11100001-10010110
+// CHECK-INST: uzp     { z20.d - z23.d }, { z12.d - z15.d }
+// CHECK-ENCODING: [0x96,0xe1,0xf6,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1f6e196 <unknown>
+
+uzp     {z28.d - z31.d}, {z28.d - z31.d}  // 11000001-11110110-11100011-10011110
+// CHECK-INST: uzp     { z28.d - z31.d }, { z28.d - z31.d }
+// CHECK-ENCODING: [0x9e,0xe3,0xf6,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1f6e39e <unknown>
+
+
+uzp     {z0.b - z3.b}, {z0.b - z3.b}  // 11000001-00110110-11100000-00000010
+// CHECK-INST: uzp     { z0.b - z3.b }, { z0.b - z3.b }
+// CHECK-ENCODING: [0x02,0xe0,0x36,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c136e002 <unknown>
+
+uzp     {z20.b - z23.b}, {z8.b - z11.b}  // 11000001-00110110-11100001-00010110
+// CHECK-INST: uzp     { z20.b - z23.b }, { z8.b - z11.b }
+// CHECK-ENCODING: [0x16,0xe1,0x36,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c136e116 <unknown>
+
+uzp     {z20.b - z23.b}, {z12.b - z15.b}  // 11000001-00110110-11100001-10010110
+// CHECK-INST: uzp     { z20.b - z23.b }, { z12.b - z15.b }
+// CHECK-ENCODING: [0x96,0xe1,0x36,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c136e196 <unknown>
+
+uzp     {z28.b - z31.b}, {z28.b - z31.b}  // 11000001-00110110-11100011-10011110
+// CHECK-INST: uzp     { z28.b - z31.b }, { z28.b - z31.b }
+// CHECK-ENCODING: [0x9e,0xe3,0x36,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c136e39e <unknown>
+

llvm/test/MC/AArch64/SME2/zip-diagnostics.s

+// RUN: not llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 2>&1 < %s | FileCheck %s
+
+// --------------------------------------------------------------------------//
+// Invalid vector list
+
+zip {z0.q-z2.q}, z0.q, z0.q
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid operand for instruction
+// CHECK-NEXT: zip {z0.q-z2.q}, z0.q, z0.q
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+zip {z21.h-z22.h}, z10.h, z21.h
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 2 consecutive SVE vectors, where the first vector is a multiple of 2 and with matching element types
+// CHECK-NEXT: zip {z21.h-z22.h}, z10.h, z21.h
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+zip {z0.s-z4.s}, {z0.s-z3.s}
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: invalid number of vectors
+// CHECK-NEXT: zip {z0.s-z4.s}, {z0.s-z3.s}
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+
+zip {z20.b-z23.b}, {z9.b-z12.b}
+// CHECK: [[@LINE-1]]:{{[0-9]+}}: error: Invalid vector list, expected list with 4 consecutive SVE vectors, where the first vector is a multiple of 4 and with matching element types
+// CHECK-NEXT: zip {z20.b-z23.b}, {z9.b-z12.b}
+// CHECK-NOT: [[@LINE-1]]:{{[0-9]+}}:
+

llvm/test/MC/AArch64/SME2/zip.s

+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+// RUN: not llvm-mc -triple=aarch64 -show-encoding < %s 2>&1 \
+// RUN:        | FileCheck %s --check-prefix=CHECK-ERROR
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
+// RUN:        | llvm-objdump -d --mattr=+sme2 - | FileCheck %s --check-prefix=CHECK-INST
+// RUN: llvm-mc -triple=aarch64 -filetype=obj -mattr=+sme2 < %s \
+// RUN:        | llvm-objdump -d --mattr=-sme2  - | FileCheck %s --check-prefix=CHECK-UNKNOWN
+// RUN: llvm-mc -triple=aarch64 -show-encoding -mattr=+sme2 < %s \
+// RUN:        | sed '/.text/d' | sed 's/.*encoding: //g' \
+// RUN:        | llvm-mc -triple=aarch64 -mattr=+sme2 -disassemble -show-encoding \
+// RUN:        | FileCheck %s --check-prefixes=CHECK-ENCODING,CHECK-INST
+
+
+zip     {z0.q - z1.q}, z0.q, z0.q  // 11000001-00100000-11010100-00000000
+// CHECK-INST: zip     { z0.q, z1.q }, z0.q, z0.q
+// CHECK-ENCODING: [0x00,0xd4,0x20,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c120d400 <unknown>
+
+zip     {z20.q - z21.q}, z10.q, z21.q  // 11000001-00110101-11010101-01010100
+// CHECK-INST: zip     { z20.q, z21.q }, z10.q, z21.q
+// CHECK-ENCODING: [0x54,0xd5,0x35,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c135d554 <unknown>
+
+zip     {z22.q - z23.q}, z13.q, z8.q  // 11000001-00101000-11010101-10110110
+// CHECK-INST: zip     { z22.q, z23.q }, z13.q, z8.q
+// CHECK-ENCODING: [0xb6,0xd5,0x28,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c128d5b6 <unknown>
+
+zip     {z30.q - z31.q}, z31.q, z31.q  // 11000001-00111111-11010111-11111110
+// CHECK-INST: zip     { z30.q, z31.q }, z31.q, z31.q
+// CHECK-ENCODING: [0xfe,0xd7,0x3f,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c13fd7fe <unknown>
+
+
+zip     {z0.h - z1.h}, z0.h, z0.h  // 11000001-01100000-11010000-00000000
+// CHECK-INST: zip     { z0.h, z1.h }, z0.h, z0.h
+// CHECK-ENCODING: [0x00,0xd0,0x60,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c160d000 <unknown>
+
+zip     {z20.h - z21.h}, z10.h, z21.h  // 11000001-01110101-11010001-01010100
+// CHECK-INST: zip     { z20.h, z21.h }, z10.h, z21.h
+// CHECK-ENCODING: [0x54,0xd1,0x75,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c175d154 <unknown>
+
+zip     {z22.h - z23.h}, z13.h, z8.h  // 11000001-01101000-11010001-10110110
+// CHECK-INST: zip     { z22.h, z23.h }, z13.h, z8.h
+// CHECK-ENCODING: [0xb6,0xd1,0x68,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c168d1b6 <unknown>
+
+zip     {z30.h - z31.h}, z31.h, z31.h  // 11000001-01111111-11010011-11111110
+// CHECK-INST: zip     { z30.h, z31.h }, z31.h, z31.h
+// CHECK-ENCODING: [0xfe,0xd3,0x7f,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c17fd3fe <unknown>
+
+
+zip     {z0.s - z1.s}, z0.s, z0.s  // 11000001-10100000-11010000-00000000
+// CHECK-INST: zip     { z0.s, z1.s }, z0.s, z0.s
+// CHECK-ENCODING: [0x00,0xd0,0xa0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a0d000 <unknown>
+
+zip     {z20.s - z21.s}, z10.s, z21.s  // 11000001-10110101-11010001-01010100
+// CHECK-INST: zip     { z20.s, z21.s }, z10.s, z21.s
+// CHECK-ENCODING: [0x54,0xd1,0xb5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1b5d154 <unknown>
+
+zip     {z22.s - z23.s}, z13.s, z8.s  // 11000001-10101000-11010001-10110110
+// CHECK-INST: zip     { z22.s, z23.s }, z13.s, z8.s
+// CHECK-ENCODING: [0xb6,0xd1,0xa8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1a8d1b6 <unknown>
+
+zip     {z30.s - z31.s}, z31.s, z31.s  // 11000001-10111111-11010011-11111110
+// CHECK-INST: zip     { z30.s, z31.s }, z31.s, z31.s
+// CHECK-ENCODING: [0xfe,0xd3,0xbf,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1bfd3fe <unknown>
+
+
+zip     {z0.d - z1.d}, z0.d, z0.d  // 11000001-11100000-11010000-00000000
+// CHECK-INST: zip     { z0.d, z1.d }, z0.d, z0.d
+// CHECK-ENCODING: [0x00,0xd0,0xe0,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e0d000 <unknown>
+
+zip     {z20.d - z21.d}, z10.d, z21.d  // 11000001-11110101-11010001-01010100
+// CHECK-INST: zip     { z20.d, z21.d }, z10.d, z21.d
+// CHECK-ENCODING: [0x54,0xd1,0xf5,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1f5d154 <unknown>
+
+zip     {z22.d - z23.d}, z13.d, z8.d  // 11000001-11101000-11010001-10110110
+// CHECK-INST: zip     { z22.d, z23.d }, z13.d, z8.d
+// CHECK-ENCODING: [0xb6,0xd1,0xe8,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1e8d1b6 <unknown>
+
+zip     {z30.d - z31.d}, z31.d, z31.d  // 11000001-11111111-11010011-11111110
+// CHECK-INST: zip     { z30.d, z31.d }, z31.d, z31.d
+// CHECK-ENCODING: [0xfe,0xd3,0xff,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1ffd3fe <unknown>
+
+
+zip     {z0.b - z1.b}, z0.b, z0.b  // 11000001-00100000-11010000-00000000
+// CHECK-INST: zip     { z0.b, z1.b }, z0.b, z0.b
+// CHECK-ENCODING: [0x00,0xd0,0x20,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c120d000 <unknown>
+
+zip     {z20.b, z21.b}, z10.b, z21.b  // 11000001-00110101-11010001-01010100
+// CHECK-INST: zip     { z20.b, z21.b }, z10.b, z21.b
+// CHECK-ENCODING: [0x54,0xd1,0x35,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c135d154 <unknown>
+
+zip     {z22.b - z23.b}, z13.b, z8.b  // 11000001-00101000-11010001-10110110
+// CHECK-INST: zip     { z22.b, z23.b }, z13.b, z8.b
+// CHECK-ENCODING: [0xb6,0xd1,0x28,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c128d1b6 <unknown>
+
+zip     {z30.b - z31.b}, z31.b, z31.b  // 11000001-00111111-11010011-11111110
+// CHECK-INST: zip     { z30.b, z31.b }, z31.b, z31.b
+// CHECK-ENCODING: [0xfe,0xd3,0x3f,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c13fd3fe <unknown>
+
+
+zip     {z0.q - z3.q}, {z0.q - z3.q}  // 11000001-00110111-11100000-00000000
+// CHECK-INST: zip     { z0.q - z3.q }, { z0.q - z3.q }
+// CHECK-ENCODING: [0x00,0xe0,0x37,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c137e000 <unknown>
+
+zip     {z20.q - z23.q}, {z8.q - z11.q}  // 11000001-00110111-11100001-00010100
+// CHECK-INST: zip     { z20.q - z23.q }, { z8.q - z11.q }
+// CHECK-ENCODING: [0x14,0xe1,0x37,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c137e114 <unknown>
+
+zip     {z20.q - z23.q}, {z12.q - z15.q}  // 11000001-00110111-11100001-10010100
+// CHECK-INST: zip     { z20.q - z23.q }, { z12.q - z15.q }
+// CHECK-ENCODING: [0x94,0xe1,0x37,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c137e194 <unknown>
+
+zip     {z28.q - z31.q}, {z28.q - z31.q}  // 11000001-00110111-11100011-10011100
+// CHECK-INST: zip     { z28.q - z31.q }, { z28.q - z31.q }
+// CHECK-ENCODING: [0x9c,0xe3,0x37,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c137e39c <unknown>
+
+
+zip     {z0.h - z3.h}, {z0.h - z3.h}  // 11000001-01110110-11100000-00000000
+// CHECK-INST: zip     { z0.h - z3.h }, { z0.h - z3.h }
+// CHECK-ENCODING: [0x00,0xe0,0x76,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c176e000 <unknown>
+
+zip     {z20.h - z23.h}, {z8.h - z11.h}  // 11000001-01110110-11100001-00010100
+// CHECK-INST: zip     { z20.h - z23.h }, { z8.h - z11.h }
+// CHECK-ENCODING: [0x14,0xe1,0x76,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c176e114 <unknown>
+
+zip     {z20.h - z23.h}, {z12.h - z15.h}  // 11000001-01110110-11100001-10010100
+// CHECK-INST: zip     { z20.h - z23.h }, { z12.h - z15.h }
+// CHECK-ENCODING: [0x94,0xe1,0x76,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c176e194 <unknown>
+
+zip     {z28.h - z31.h}, {z28.h - z31.h}  // 11000001-01110110-11100011-10011100
+// CHECK-INST: zip     { z28.h - z31.h }, { z28.h - z31.h }
+// CHECK-ENCODING: [0x9c,0xe3,0x76,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c176e39c <unknown>
+
+
+zip     {z0.s - z3.s}, {z0.s - z3.s}  // 11000001-10110110-11100000-00000000
+// CHECK-INST: zip     { z0.s - z3.s }, { z0.s - z3.s }
+// CHECK-ENCODING: [0x00,0xe0,0xb6,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1b6e000 <unknown>
+
+zip     {z20.s - z23.s}, {z8.s - z11.s}  // 11000001-10110110-11100001-00010100
+// CHECK-INST: zip     { z20.s - z23.s }, { z8.s - z11.s }
+// CHECK-ENCODING: [0x14,0xe1,0xb6,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1b6e114 <unknown>
+
+zip     {z20.s - z23.s}, {z12.s - z15.s}  // 11000001-10110110-11100001-10010100
+// CHECK-INST: zip     { z20.s - z23.s }, { z12.s - z15.s }
+// CHECK-ENCODING: [0x94,0xe1,0xb6,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1b6e194 <unknown>
+
+zip     {z28.s - z31.s}, {z28.s - z31.s}  // 11000001-10110110-11100011-10011100
+// CHECK-INST: zip     { z28.s - z31.s }, { z28.s - z31.s }
+// CHECK-ENCODING: [0x9c,0xe3,0xb6,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1b6e39c <unknown>
+
+
+zip     {z0.d - z3.d}, {z0.d - z3.d}  // 11000001-11110110-11100000-00000000
+// CHECK-INST: zip     { z0.d - z3.d }, { z0.d - z3.d }
+// CHECK-ENCODING: [0x00,0xe0,0xf6,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1f6e000 <unknown>
+
+zip     {z20.d - z23.d}, {z8.d - z11.d}  // 11000001-11110110-11100001-00010100
+// CHECK-INST: zip     { z20.d - z23.d }, { z8.d - z11.d }
+// CHECK-ENCODING: [0x14,0xe1,0xf6,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1f6e114 <unknown>
+
+zip     {z20.d - z23.d}, {z12.d - z15.d}  // 11000001-11110110-11100001-10010100
+// CHECK-INST: zip     { z20.d - z23.d }, { z12.d - z15.d }
+// CHECK-ENCODING: [0x94,0xe1,0xf6,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1f6e194 <unknown>
+
+zip     {z28.d - z31.d}, {z28.d - z31.d}  // 11000001-11110110-11100011-10011100
+// CHECK-INST: zip     { z28.d - z31.d }, { z28.d - z31.d }
+// CHECK-ENCODING: [0x9c,0xe3,0xf6,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c1f6e39c <unknown>
+
+
+zip     {z0.b - z3.b}, {z0.b - z3.b}  // 11000001-00110110-11100000-00000000
+// CHECK-INST: zip     { z0.b - z3.b }, { z0.b - z3.b }
+// CHECK-ENCODING: [0x00,0xe0,0x36,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c136e000 <unknown>
+
+zip     {z20.b - z23.b}, {z8.b - z11.b}  // 11000001-00110110-11100001-00010100
+// CHECK-INST: zip     { z20.b - z23.b }, { z8.b - z11.b }
+// CHECK-ENCODING: [0x14,0xe1,0x36,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c136e114 <unknown>
+
+zip     {z20.b - z23.b}, {z12.b - z15.b}  // 11000001-00110110-11100001-10010100
+// CHECK-INST: zip     { z20.b - z23.b }, { z12.b - z15.b }
+// CHECK-ENCODING: [0x94,0xe1,0x36,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c136e194 <unknown>
+
+zip     {z28.b - z31.b}, {z28.b - z31.b}  // 11000001-00110110-11100011-10011100
+// CHECK-INST: zip     { z28.b - z31.b }, { z28.b - z31.b }
+// CHECK-ENCODING: [0x9c,0xe3,0x36,0xc1]
+// CHECK-ERROR: instruction requires: sme2
+// CHECK-UNKNOWN: c136e39c <unknown>
+