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[AArch64]SME2 Multi-vector ternary indexed DOT and FMLA instructions
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Authored by CarolineConcatto on Oct 11 2022, 7:42 AM.

Details

Summary

This patch adds the assembly/disassembly for the following instruction:
FP:

FMLA (multiple and indexed vector): Multi-vector floating-point fused multiply-add by indexed element.
FMLS(multiple and indexed vector): Multi-vector floating-point fused multiply-subtract by indexed element.

BFDOT (multiple and indexed vector): Multi-vector BFloat16 floating-point dot-product by indexed element.
FDOT (multiple and indexed vector): Multi-vector half-precision floating-point dot-product by indexed element.
BFVDOT: Multi-vector BFloat16 floating-point vertical dot-product by indexed element.
FVDOT: Multi-vector half-precision floating-point vertical dot-product by indexed element.

INT:

SDOT (2-way, multiple and indexed vector): Multi-vector signed integer dot-product by indexed element.
             (4-way, multiple and indexed vector): Multi-vector signed integer dot-product by indexed element.
SUDOT (multiple and indexed vector): Multi-vector signed by unsigned integer dot-product by indexed elements.
SUVDOT: Multi-vector signed by unsigned integer vertical dot-product by indexed element.
UDOT (2-way, multiple and indexed vector): Multi-vector unsigned integer dot-product by indexed element.
             (4-way, multiple and indexed vector): Multi-vector unsigned integer dot-product by indexed element.
USDOT (multiple and indexed vector): Multi-vector unsigned by signed integer dot-product by indexed element.
USVDOT: Multi-vector unsigned by signed integer vertical dot-product by indexed element.

For the multi-vec ternary indexed with 2 and 4 ZA single-vectors for
32 and 64 bits according to the instruction

The reference can be found here:

https://developer.arm.com/documentation/ddi0602/2022-09

Depends on:D135563

Diff Detail

Event Timeline

CarolineConcatto requested review of this revision.Oct 11 2022, 7:42 AM
Herald added a project: Restricted Project. · View Herald TranscriptOct 11 2022, 7:42 AM
Matt added a subscriber: Matt.Oct 11 2022, 11:46 AM
CarolineConcatto edited the summary of this revision. (Show Details)

-Rebase to update the test outpu

llvm/test/MC/AArch64/SME2/fdot.s
46

Needs to remove this

  • FDOT assembly tests added in the correct file.
llvm/lib/Target/AArch64/SMEInstrFormats.td
1964–1986

Rather than three classes can you create a single multiclass for sme2_multi_vec_array_vg2_index_32b of the same name that takes the same operands? If you're worried about the instruction alias, you should be able to use ZPRRegOp:$Zm.

This same comment likely applies to the other classes below.

1965

You may as well just pass in opc untouched and do the split within sme2_multi_vec_array_vg2_index_32b.

  • Create a generic multiclass for each class.
  • rebase
CarolineConcatto marked 2 inline comments as done.Oct 24 2022, 4:01 PM
paulwalker-arm accepted this revision.Oct 24 2022, 5:52 PM

One more request but otherwise looks good.

llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td
468

For consistency please can all the dot instructions have a suffix even when there's only a single variant of the instruction. Doing this makes it easier to know what the instruction does from the name alone. So for this case it'll be USVDOT_VG4_M4ZZI_BtoS.

This revision is now accepted and ready to land.Oct 24 2022, 5:52 PM