This is an archive of the discontinued LLVM Phabricator instance.

[AArch64]SME2 Multi-vector - Index/Single/Multi Array Vectors LONG INT MLA sources
ClosedPublic

Authored by CarolineConcatto on Oct 17 2022, 6:09 AM.

Details

Summary
This patch adds the assembly/disassembly for the following instructions:

  SMLALL: (multiple and indexed vector): Multi-vector signed integer multiply-add long long by indexed element.
          (multiple and single vector): Multi-vector signed integer multiply-add long long by vector.
          (multiple vectors): Multi-vector signed integer multiply-add long long.

  SMLSLL: (multiple and indexed vector): Multi-vector signed integer multiply-subtract long long by indexed element.
          (multiple and single vector): Multi-vector signed integer multiply-subtract long long by vector.
          (multiple vectors): Multi-vector signed integer multiply-subtract long long.
  SUMLALL: (multiple and indexed vector): Multi-vector signed by unsigned integer multiply-add long long by indexed element.
            (multiple and single vector): Multi-vector signed by unsigned integer multiply-add long long by vector.

  UMLALL: (multiple and indexed vector): Multi-vector unsigned integer multiply-add long long by indexed element.
          (multiple and single vector): Multi-vector unsigned integer multiply-add long long by vector.
          (multiple vectors): Multi-vector unsigned integer multiply-add long long.

  UMLSLL: (multiple and indexed vector): Multi-vector unsigned integer multiply-subtract long long by indexed element.
          (multiple and single vector): Multi-vector unsigned integer multiply-subtract long long by vector.
          (multiple vectors): Multi-vector unsigned integer multiply-subtract long long.

  USMLALL: (multiple and indexed vector): Multi-vector unsigned by signed integer multiply-add long long by indexed element.
          (multiple and single vector): Multi-vector unsigned by signed integer multiply-add long long by vector.
          (multiple vectors): Multi-vector unsigned by signed integer multiply-add long long.

The reference can be found here:

https://developer.arm.com/documentation/ddi0602/2022-09

 It also adds a new immediate:
     uimm2s4range for off2
     uimm1s4range for o1
   to represent the vector select offset.
The new operands have the range between the first and the last vector position.

Depends on : D135785

Diff Detail

Event Timeline

CarolineConcatto requested review of this revision.Oct 17 2022, 6:09 AM
Herald added a project: Restricted Project. · View Herald TranscriptOct 17 2022, 6:09 AM
Matt added a subscriber: Matt.Oct 21 2022, 12:38 PM

Add generic multiclass for the classes
Rebase

paulwalker-arm added inline comments.Oct 26 2022, 4:46 PM
llvm/lib/Target/AArch64/AArch64InstrFormats.td
1389–1394

Perhaps better placed after uimm2s2range or uimm1s4range depending on what you prefer to sort on.

llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
5497–5498

Logically these belong after Match_InvalidMemoryIndexedRange2U....

How does this diagnostic relate to memory?

Does the "depending on the instruction" part related to the difference between 4UImm1 and 4UImm2? If yes then I think separate diagnostics are better so that it's clear to the user what the expectation is.

llvm/lib/Target/AArch64/SMEInstrFormats.td
2163

This is 4 bits but I only see i{2,1-0} used to create Inst.

CarolineConcatto marked an inline comment as done.
  • Address review comments
  • nit
llvm/lib/Target/AArch64/AArch64InstrFormats.td
1389–1394

Not a problem, I was grouping by multiples, but I guess that works too.

llvm/lib/Target/AArch64/SMEInstrFormats.td
2163

'i' size is wrong here in the declaration for
Four ZA quad-vectors of 64-bit elements
and
Two ZA quad-vectors of 64-bit elements
it should be bits<3> i;
However the assignment is correct. bit{10}= ih; and bit{2-1}= il

paulwalker-arm added inline comments.Oct 27 2022, 9:01 AM
llvm/lib/Target/AArch64/AArch64SMEInstrInfo.td
512

Despite there being no _HtoD variant I think it's worth being consistent and using _BtoS for USMLALL and SUMLALL.

llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
5512–5518

I cannot see any tests for this diagnostic.

llvm/lib/Target/AArch64/SMEInstrFormats.td
2101

bits<3>?

2129

FYI: You can also use bit instead of bits<1>.

2274

Please add a comment specifying the encoding group.

2310

Please add a comment specifying the encoding group.

CarolineConcatto marked 6 inline comments as done.

-Address review comments

llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
5512–5518

Paul, I could not make the parser print this error message. It always end up being matched with
class MCK_UImm1s4Range to print the error message.

Maybe we can improve this, but I don't believe it should be in this patch.
Probably I need to create another to fix this and probably
Match_InvalidMemoryIndexedRange2UImm2
Match_InvalidMemoryIndexedRange2UImm3
too.

The problems is with the parser
Because I can see the instruction is being checked with the correct instruction.
Trying to match opcode SUMLALL_MZZI_BtoS for SUMLALL za.s[w8, 9:12], z22.b, z1.b[2]

Matching formal operand class MCK_UImm2s4Range against actual operand at index 4 (<immrange 9:12>): Opcode result: multiple operand mismatches, ignoring this opcode

But for some reason it prints error for another instructions:
UMLALL_VG4_M4ZZI_BtoS

Matching formal operand class MCK_UImm1s4Range against actual operand at index 4 (<immrange 9:12>): Opcode result: multiple operand mismatches, ignoring this opcode
llvm/lib/Target/AArch64/SMEInstrFormats.td
2101

Oh...dear!

paulwalker-arm accepted this revision.Oct 28 2022, 7:45 AM
paulwalker-arm added inline comments.
llvm/lib/Target/AArch64/AsmParser/AArch64AsmParser.cpp
5512–5518

Thanks for investigating Carol. This does sound a little worrying but as you say there's no value in holding up this patch for it.

This revision is now accepted and ready to land.Oct 28 2022, 7:45 AM
  • Add missing diagnostic for uimm2s4range
This revision was landed with ongoing or failed builds.Oct 28 2022, 9:40 AM
This revision was automatically updated to reflect the committed changes.